1//===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Lanai implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
14#define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
15
16#include "LanaiRegisterInfo.h"
17#include "MCTargetDesc/LanaiMCTargetDesc.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "LanaiGenInstrInfo.inc"
22
23namespace llvm {
24
25class LanaiSubtarget;
26
27class LanaiInstrInfo : public LanaiGenInstrInfo {
28 const LanaiRegisterInfo RegisterInfo;
29
30public:
31 LanaiInstrInfo(const LanaiSubtarget &STI);
32
33 // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
34 // such, whenever a client has an instance of instruction info, it should
35 // always be able to get register info as well (through this method).
36 virtual const LanaiRegisterInfo &getRegisterInfo() const {
37 return RegisterInfo;
38 }
39
40 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
41 const MachineInstr &MIb) const override;
42
43 Register isLoadFromStackSlot(const MachineInstr &MI,
44 int &FrameIndex) const override;
45
46 Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
47 int &FrameIndex) const override;
48
49 Register isStoreToStackSlot(const MachineInstr &MI,
50 int &FrameIndex) const override;
51
52 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
53 const DebugLoc &DL, Register DestinationRegister,
54 Register SourceRegister, bool KillSource,
55 bool RenamableDest = false,
56 bool RenamableSrc = false) const override;
57
58 void storeRegToStackSlot(
59 MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
60 Register SourceRegister, bool IsKill, int FrameIndex,
61 const TargetRegisterClass *RegisterClass, Register VReg,
62 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
63
64 void loadRegFromStackSlot(
65 MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
66 Register DestinationRegister, int FrameIndex,
67 const TargetRegisterClass *RegisterClass, Register VReg,
68 unsigned SubReg = 0,
69 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
70
71 bool expandPostRAPseudo(MachineInstr &MI) const override;
72
73 bool getMemOperandsWithOffsetWidth(
74 const MachineInstr &LdSt,
75 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
76 bool &OffsetIsScalable, LocationSize &Width) const override;
77
78 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
79 const MachineOperand *&BaseOp,
80 int64_t &Offset, LocationSize &Width) const;
81
82 std::pair<unsigned, unsigned>
83 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
84
85 ArrayRef<std::pair<unsigned, const char *>>
86 getSerializableDirectMachineOperandTargetFlags() const override;
87
88 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock,
89 MachineBasicBlock *&FalseBlock,
90 SmallVectorImpl<MachineOperand> &Condition,
91 bool AllowModify) const override;
92
93 unsigned removeBranch(MachineBasicBlock &MBB,
94 int *BytesRemoved = nullptr) const override;
95
96 // For a comparison instruction, return the source registers in SrcReg and
97 // SrcReg2 if having two register operands, and the value it compares against
98 // in CmpValue. Return true if the comparison instruction can be analyzed.
99 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
100 Register &SrcReg2, int64_t &CmpMask,
101 int64_t &CmpValue) const override;
102
103 // See if the comparison instruction can be converted into something more
104 // efficient. E.g., on Lanai register-register instructions can set the flag
105 // register, obviating the need for a separate compare.
106 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
107 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
108 const MachineRegisterInfo *MRI) const override;
109
110 // Given a select instruction that was understood by analyzeSelect and
111 // returned Optimizable = true, attempt to optimize MI by merging it with one
112 // of its operands. Returns NULL on failure.
113 //
114 // When successful, returns the new select instruction. The client is
115 // responsible for deleting MI.
116 //
117 // If both sides of the select can be optimized, the TrueOp is modifed.
118 // PreferFalse is not used.
119 MachineInstr *optimizeSelect(MachineInstr &MI,
120 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
121 bool PreferFalse) const override;
122
123 bool reverseBranchCondition(
124 SmallVectorImpl<MachineOperand> &Condition) const override;
125
126 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
127 MachineBasicBlock *FalseBlock,
128 ArrayRef<MachineOperand> Condition,
129 const DebugLoc &DL,
130 int *BytesAdded = nullptr) const override;
131};
132
133static inline bool isSPLSOpcode(unsigned Opcode) {
134 switch (Opcode) {
135 case Lanai::LDBs_RI:
136 case Lanai::LDBz_RI:
137 case Lanai::LDHs_RI:
138 case Lanai::LDHz_RI:
139 case Lanai::STB_RI:
140 case Lanai::STH_RI:
141 return true;
142 default:
143 return false;
144 }
145}
146
147static inline bool isRMOpcode(unsigned Opcode) {
148 switch (Opcode) {
149 case Lanai::LDW_RI:
150 case Lanai::SW_RI:
151 return true;
152 default:
153 return false;
154 }
155}
156
157static inline bool isRRMOpcode(unsigned Opcode) {
158 switch (Opcode) {
159 case Lanai::LDBs_RR:
160 case Lanai::LDBz_RR:
161 case Lanai::LDHs_RR:
162 case Lanai::LDHz_RR:
163 case Lanai::LDWz_RR:
164 case Lanai::LDW_RR:
165 case Lanai::STB_RR:
166 case Lanai::STH_RR:
167 case Lanai::SW_RR:
168 return true;
169 default:
170 return false;
171 }
172}
173
174} // namespace llvm
175
176#endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
177