1//=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
15
16#include "LoongArchRegisterInfo.h"
17#include "llvm/CodeGen/TargetInstrInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "LoongArchGenInstrInfo.inc"
21
22namespace llvm {
23
24class LoongArchSubtarget;
25
26class LoongArchInstrInfo : public LoongArchGenInstrInfo {
27 const LoongArchRegisterInfo RegInfo;
28
29public:
30 explicit LoongArchInstrInfo(const LoongArchSubtarget &STI);
31
32 const LoongArchRegisterInfo &getRegisterInfo() const { return RegInfo; }
33
34 MCInst getNop() const override;
35
36 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
37 const DebugLoc &DL, Register DstReg, Register SrcReg,
38 bool KillSrc, bool RenamableDest = false,
39 bool RenamableSrc = false) const override;
40
41 void storeRegToStackSlot(
42 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
43 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
44 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
45 void loadRegFromStackSlot(
46 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
47 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
48 unsigned SubReg = 0,
49 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
50
51 Register isLoadFromStackSlot(const MachineInstr &MI,
52 int &FrameIndex) const override;
53 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
54 TypeSize &MemBytes) const override;
55 Register isStoreToStackSlot(const MachineInstr &MI,
56 int &FrameIndex) const override;
57 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
58 TypeSize &MemBytes) const override;
59
60 // Materializes the given integer Val into DstReg.
61 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
62 const DebugLoc &DL, Register DstReg, uint64_t Val,
63 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
64
65 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
66
67 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
68
69 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
70
71 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
72 MachineBasicBlock *&FBB,
73 SmallVectorImpl<MachineOperand> &Cond,
74 bool AllowModify) const override;
75
76 bool isBranchOffsetInRange(unsigned BranchOpc,
77 int64_t BrOffset) const override;
78
79 bool isSafeToMove(const MachineInstr &MI, const MachineBasicBlock *MBB,
80 const MachineFunction &MF) const override;
81
82 bool isSchedulingBoundary(const MachineInstr &MI,
83 const MachineBasicBlock *MBB,
84 const MachineFunction &MF) const override;
85
86 unsigned removeBranch(MachineBasicBlock &MBB,
87 int *BytesRemoved = nullptr) const override;
88
89 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
90 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
91 const DebugLoc &dl,
92 int *BytesAdded = nullptr) const override;
93
94 void insertIndirectBranch(MachineBasicBlock &MBB,
95 MachineBasicBlock &NewDestBB,
96 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
97 int64_t BrOffset, RegScavenger *RS) const override;
98
99 bool
100 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
101
102 std::pair<unsigned, unsigned>
103 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
104
105 ArrayRef<std::pair<unsigned, const char *>>
106 getSerializableDirectMachineOperandTargetFlags() const override;
107
108 ArrayRef<std::pair<unsigned, const char *>>
109 getSerializableBitmaskMachineOperandTargetFlags() const override;
110
111 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
112 const MachineInstr &AddrI,
113 ExtAddrMode &AM) const override;
114 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
115 const ExtAddrMode &AM) const override;
116
117protected:
118 const LoongArchSubtarget &STI;
119};
120
121namespace LoongArch {
122
123// Returns true if this is the sext.w pattern, addi.w rd, rs, 0.
124bool isSEXT_W(const MachineInstr &MI);
125
126// Mask assignments for floating-point.
127static constexpr unsigned FClassMaskSignalingNaN = 0x001;
128static constexpr unsigned FClassMaskQuietNaN = 0x002;
129static constexpr unsigned FClassMaskNegativeInfinity = 0x004;
130static constexpr unsigned FClassMaskNegativeNormal = 0x008;
131static constexpr unsigned FClassMaskNegativeSubnormal = 0x010;
132static constexpr unsigned FClassMaskNegativeZero = 0x020;
133static constexpr unsigned FClassMaskPositiveInfinity = 0x040;
134static constexpr unsigned FClassMaskPositiveNormal = 0x080;
135static constexpr unsigned FClassMaskPositiveSubnormal = 0x100;
136static constexpr unsigned FClassMaskPositiveZero = 0x200;
137} // namespace LoongArch
138
139} // end namespace llvm
140#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
141