1//=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
15
16#include "LoongArchRegisterInfo.h"
17#include "llvm/CodeGen/TargetInstrInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "LoongArchGenInstrInfo.inc"
21
22namespace llvm {
23
24class LoongArchSubtarget;
25
26class LoongArchInstrInfo : public LoongArchGenInstrInfo {
27 const LoongArchRegisterInfo RegInfo;
28
29public:
30 explicit LoongArchInstrInfo(const LoongArchSubtarget &STI);
31
32 const LoongArchRegisterInfo &getRegisterInfo() const { return RegInfo; }
33
34 const TargetRegisterClass *getInlineAsmMemoryOperandRegClass(
35 InlineAsm::ConstraintCode C) const override {
36 return &LoongArch::GPRRegClass;
37 }
38
39 MCInst getNop() const override;
40
41 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
42 const DebugLoc &DL, Register DstReg, Register SrcReg,
43 bool KillSrc, bool RenamableDest = false,
44 bool RenamableSrc = false) const override;
45
46 void storeRegToStackSlot(
47 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
48 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
49 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
50 void loadRegFromStackSlot(
51 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
52 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
53 unsigned SubReg = 0,
54 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
55
56 Register isLoadFromStackSlot(const MachineInstr &MI,
57 int &FrameIndex) const override;
58 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
59 TypeSize &MemBytes) const override;
60 Register isStoreToStackSlot(const MachineInstr &MI,
61 int &FrameIndex) const override;
62 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
63 TypeSize &MemBytes) const override;
64
65 // Materializes the given integer Val into DstReg.
66 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
67 const DebugLoc &DL, Register DstReg, uint64_t Val,
68 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
69
70 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
71
72 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
73
74 int getJumpTableIndex(const MachineInstr &MI) const override;
75
76 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
77
78 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
79 MachineBasicBlock *&FBB,
80 SmallVectorImpl<MachineOperand> &Cond,
81 bool AllowModify) const override;
82
83 bool isBranchOffsetInRange(unsigned BranchOpc,
84 int64_t BrOffset) const override;
85
86 bool isSafeToMove(const MachineInstr &MI, const MachineBasicBlock *MBB,
87 const MachineFunction &MF) const override;
88
89 bool isSchedulingBoundary(const MachineInstr &MI,
90 const MachineBasicBlock *MBB,
91 const MachineFunction &MF) const override;
92
93 unsigned removeBranch(MachineBasicBlock &MBB,
94 int *BytesRemoved = nullptr) const override;
95
96 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
97 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
98 const DebugLoc &dl,
99 int *BytesAdded = nullptr) const override;
100
101 void insertIndirectBranch(MachineBasicBlock &MBB,
102 MachineBasicBlock &NewDestBB,
103 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
104 int64_t BrOffset, RegScavenger *RS) const override;
105
106 bool
107 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
108
109 std::pair<unsigned, unsigned>
110 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
111
112 ArrayRef<std::pair<unsigned, const char *>>
113 getSerializableDirectMachineOperandTargetFlags() const override;
114
115 ArrayRef<std::pair<unsigned, const char *>>
116 getSerializableBitmaskMachineOperandTargetFlags() const override;
117
118 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
119 const MachineInstr &AddrI,
120 ExtAddrMode &AM) const override;
121 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
122 const ExtAddrMode &AM) const override;
123
124protected:
125 const LoongArchSubtarget &STI;
126};
127
128namespace LoongArch {
129
130// Returns true if this is the sext.w pattern, addi.w rd, rs, 0.
131bool isSEXT_W(const MachineInstr &MI);
132
133// Mask assignments for floating-point.
134static constexpr unsigned FClassMaskSignalingNaN = 0x001;
135static constexpr unsigned FClassMaskQuietNaN = 0x002;
136static constexpr unsigned FClassMaskNegativeInfinity = 0x004;
137static constexpr unsigned FClassMaskNegativeNormal = 0x008;
138static constexpr unsigned FClassMaskNegativeSubnormal = 0x010;
139static constexpr unsigned FClassMaskNegativeZero = 0x020;
140static constexpr unsigned FClassMaskPositiveInfinity = 0x040;
141static constexpr unsigned FClassMaskPositiveNormal = 0x080;
142static constexpr unsigned FClassMaskPositiveSubnormal = 0x100;
143static constexpr unsigned FClassMaskPositiveZero = 0x200;
144} // namespace LoongArch
145
146} // end namespace llvm
147#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
148