1//=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
15
16#include "LoongArchRegisterInfo.h"
17#include "llvm/CodeGen/TargetInstrInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "LoongArchGenInstrInfo.inc"
21
22namespace llvm {
23
24class LoongArchSubtarget;
25
26class LoongArchInstrInfo : public LoongArchGenInstrInfo {
27 const LoongArchRegisterInfo RegInfo;
28
29public:
30 explicit LoongArchInstrInfo(const LoongArchSubtarget &STI);
31
32 const LoongArchRegisterInfo &getRegisterInfo() const { return RegInfo; }
33
34 MCInst getNop() const override;
35
36 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
37 const DebugLoc &DL, Register DstReg, Register SrcReg,
38 bool KillSrc, bool RenamableDest = false,
39 bool RenamableSrc = false) const override;
40
41 void storeRegToStackSlot(
42 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
43 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
44 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
45 void loadRegFromStackSlot(
46 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
47 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
48 unsigned SubReg = 0,
49 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
50
51 // Materializes the given integer Val into DstReg.
52 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
53 const DebugLoc &DL, Register DstReg, uint64_t Val,
54 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
55
56 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
57
58 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
59
60 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
61
62 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
63 MachineBasicBlock *&FBB,
64 SmallVectorImpl<MachineOperand> &Cond,
65 bool AllowModify) const override;
66
67 bool isBranchOffsetInRange(unsigned BranchOpc,
68 int64_t BrOffset) const override;
69
70 bool isSafeToMove(const MachineInstr &MI, const MachineBasicBlock *MBB,
71 const MachineFunction &MF) const override;
72
73 bool isSchedulingBoundary(const MachineInstr &MI,
74 const MachineBasicBlock *MBB,
75 const MachineFunction &MF) const override;
76
77 unsigned removeBranch(MachineBasicBlock &MBB,
78 int *BytesRemoved = nullptr) const override;
79
80 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
81 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
82 const DebugLoc &dl,
83 int *BytesAdded = nullptr) const override;
84
85 void insertIndirectBranch(MachineBasicBlock &MBB,
86 MachineBasicBlock &NewDestBB,
87 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
88 int64_t BrOffset, RegScavenger *RS) const override;
89
90 bool
91 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
92
93 std::pair<unsigned, unsigned>
94 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
95
96 ArrayRef<std::pair<unsigned, const char *>>
97 getSerializableDirectMachineOperandTargetFlags() const override;
98
99 ArrayRef<std::pair<unsigned, const char *>>
100 getSerializableBitmaskMachineOperandTargetFlags() const override;
101
102 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
103 const MachineInstr &AddrI,
104 ExtAddrMode &AM) const override;
105 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
106 const ExtAddrMode &AM) const override;
107
108protected:
109 const LoongArchSubtarget &STI;
110};
111
112namespace LoongArch {
113
114// Returns true if this is the sext.w pattern, addi.w rd, rs, 0.
115bool isSEXT_W(const MachineInstr &MI);
116
117// Mask assignments for floating-point.
118static constexpr unsigned FClassMaskSignalingNaN = 0x001;
119static constexpr unsigned FClassMaskQuietNaN = 0x002;
120static constexpr unsigned FClassMaskNegativeInfinity = 0x004;
121static constexpr unsigned FClassMaskNegativeNormal = 0x008;
122static constexpr unsigned FClassMaskNegativeSubnormal = 0x010;
123static constexpr unsigned FClassMaskNegativeZero = 0x020;
124static constexpr unsigned FClassMaskPositiveInfinity = 0x040;
125static constexpr unsigned FClassMaskPositiveNormal = 0x080;
126static constexpr unsigned FClassMaskPositiveSubnormal = 0x100;
127static constexpr unsigned FClassMaskPositiveZero = 0x200;
128} // namespace LoongArch
129
130} // end namespace llvm
131#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
132