1//===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the MipsAsmBackend class.
10//
11//===----------------------------------------------------------------------===//
12//
13
14#include "MCTargetDesc/MipsAsmBackend.h"
15#include "MCTargetDesc/MipsABIInfo.h"
16#include "MCTargetDesc/MipsFixupKinds.h"
17#include "MCTargetDesc/MipsMCTargetDesc.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/MC/MCAsmBackend.h"
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCELFObjectWriter.h"
23#include "llvm/MC/MCObjectWriter.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/MCTargetOptions.h"
26#include "llvm/MC/MCValue.h"
27#include "llvm/Support/EndianStream.h"
28#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/MathExtras.h"
30#include "llvm/Support/raw_ostream.h"
31
32using namespace llvm;
33
34// Prepare value for the target space for it
35static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
36 MCContext &Ctx) {
37
38 unsigned Kind = Fixup.getKind();
39
40 // Add/subtract and shift
41 switch (Kind) {
42 default:
43 return 0;
44 case FK_Data_2:
45 case Mips::fixup_Mips_LO16:
46 case Mips::fixup_Mips_GPREL16:
47 case Mips::fixup_Mips_GPOFF_HI:
48 case Mips::fixup_Mips_GPOFF_LO:
49 case Mips::fixup_Mips_GOT_PAGE:
50 case Mips::fixup_Mips_GOT_OFST:
51 case Mips::fixup_Mips_GOT_DISP:
52 case Mips::fixup_Mips_GOT_LO16:
53 case Mips::fixup_Mips_CALL_LO16:
54 case Mips::fixup_MICROMIPS_GPOFF_HI:
55 case Mips::fixup_MICROMIPS_GPOFF_LO:
56 case Mips::fixup_MICROMIPS_LO16:
57 case Mips::fixup_MICROMIPS_GOT_PAGE:
58 case Mips::fixup_MICROMIPS_GOT_OFST:
59 case Mips::fixup_MICROMIPS_GOT_DISP:
60 case Mips::fixup_MIPS_PCLO16:
61 Value &= 0xffff;
62 break;
63 case Mips::fixup_Mips_AnyImm16:
64 if (!isInt<16>(x: Value) && !isUInt<16>(x: Value))
65 Ctx.reportError(L: Fixup.getLoc(),
66 Msg: "fixup value out of range [-32768, 65535]");
67 break;
68 case Mips::fixup_Mips_GPREL32:
69 case Mips::fixup_Mips_DTPREL32:
70 case Mips::fixup_Mips_DTPREL64:
71 case Mips::fixup_Mips_TPREL32:
72 case Mips::fixup_Mips_TPREL64:
73 case FK_Data_4:
74 case FK_Data_8:
75 case Mips::fixup_Mips_SUB:
76 case Mips::fixup_MICROMIPS_SUB:
77 break;
78 case Mips::fixup_Mips_PC16:
79 // The displacement is then divided by 4 to give us an 18 bit
80 // address range. Forcing a signed division because Value can be negative.
81 Value = (int64_t)Value / 4;
82 // We now check if Value can be encoded as a 16-bit signed immediate.
83 if (!isInt<16>(x: Value)) {
84 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC16 fixup");
85 return 0;
86 }
87 break;
88 case Mips::fixup_MIPS_PC19_S2:
89 case Mips::fixup_MICROMIPS_PC19_S2:
90 // Forcing a signed division because Value can be negative.
91 Value = (int64_t)Value / 4;
92 // We now check if Value can be encoded as a 19-bit signed immediate.
93 if (!isInt<19>(x: Value)) {
94 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC19 fixup");
95 return 0;
96 }
97 break;
98 case Mips::fixup_Mips_26:
99 // So far we are only using this type for jumps.
100 // The displacement is then divided by 4 to give us an 28 bit
101 // address range.
102 Value >>= 2;
103 break;
104 case Mips::fixup_Mips_HI16:
105 case Mips::fixup_Mips_GOT:
106 case Mips::fixup_MICROMIPS_GOT16:
107 case Mips::fixup_Mips_GOT_HI16:
108 case Mips::fixup_Mips_CALL_HI16:
109 case Mips::fixup_MICROMIPS_HI16:
110 case Mips::fixup_MIPS_PCHI16:
111 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
112 Value = ((Value + 0x8000) >> 16) & 0xffff;
113 break;
114 case Mips::fixup_Mips_HIGHER:
115 case Mips::fixup_MICROMIPS_HIGHER:
116 // Get the 3rd 16-bits.
117 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
118 break;
119 case Mips::fixup_Mips_HIGHEST:
120 case Mips::fixup_MICROMIPS_HIGHEST:
121 // Get the 4th 16-bits.
122 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
123 break;
124 case Mips::fixup_MICROMIPS_26_S1:
125 Value >>= 1;
126 break;
127 case Mips::fixup_MICROMIPS_PC7_S1:
128 Value -= 4;
129 // Forcing a signed division because Value can be negative.
130 Value = (int64_t) Value / 2;
131 // We now check if Value can be encoded as a 7-bit signed immediate.
132 if (!isInt<7>(x: Value)) {
133 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC7 fixup");
134 return 0;
135 }
136 break;
137 case Mips::fixup_MICROMIPS_PC10_S1:
138 Value -= 2;
139 // Forcing a signed division because Value can be negative.
140 Value = (int64_t) Value / 2;
141 // We now check if Value can be encoded as a 10-bit signed immediate.
142 if (!isInt<10>(x: Value)) {
143 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC10 fixup");
144 return 0;
145 }
146 break;
147 case Mips::fixup_MICROMIPS_PC16_S1:
148 Value -= 4;
149 // Forcing a signed division because Value can be negative.
150 Value = (int64_t)Value / 2;
151 // We now check if Value can be encoded as a 16-bit signed immediate.
152 if (!isInt<16>(x: Value)) {
153 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC16 fixup");
154 return 0;
155 }
156 break;
157 case Mips::fixup_MIPS_PC18_S3:
158 // Forcing a signed division because Value can be negative.
159 Value = (int64_t)Value / 8;
160 // We now check if Value can be encoded as a 18-bit signed immediate.
161 if (!isInt<18>(x: Value)) {
162 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup");
163 return 0;
164 }
165 break;
166 case Mips::fixup_MICROMIPS_PC18_S3:
167 // Check alignment.
168 if ((Value & 7)) {
169 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup");
170 }
171 // Forcing a signed division because Value can be negative.
172 Value = (int64_t)Value / 8;
173 // We now check if Value can be encoded as a 18-bit signed immediate.
174 if (!isInt<18>(x: Value)) {
175 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup");
176 return 0;
177 }
178 break;
179 case Mips::fixup_MIPS_PC21_S2:
180 // Forcing a signed division because Value can be negative.
181 Value = (int64_t) Value / 4;
182 // We now check if Value can be encoded as a 21-bit signed immediate.
183 if (!isInt<21>(x: Value)) {
184 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC21 fixup");
185 return 0;
186 }
187 break;
188 case Mips::fixup_MIPS_PC26_S2:
189 // Forcing a signed division because Value can be negative.
190 Value = (int64_t) Value / 4;
191 // We now check if Value can be encoded as a 26-bit signed immediate.
192 if (!isInt<26>(x: Value)) {
193 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC26 fixup");
194 return 0;
195 }
196 break;
197 case Mips::fixup_MICROMIPS_PC26_S1:
198 // Forcing a signed division because Value can be negative.
199 Value = (int64_t)Value / 2;
200 // We now check if Value can be encoded as a 26-bit signed immediate.
201 if (!isInt<26>(x: Value)) {
202 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC26 fixup");
203 return 0;
204 }
205 break;
206 case Mips::fixup_MICROMIPS_PC21_S1:
207 // Forcing a signed division because Value can be negative.
208 Value = (int64_t)Value / 2;
209 // We now check if Value can be encoded as a 21-bit signed immediate.
210 if (!isInt<21>(x: Value)) {
211 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC21 fixup");
212 return 0;
213 }
214 break;
215 }
216
217 return Value;
218}
219
220std::unique_ptr<MCObjectTargetWriter>
221MipsAsmBackend::createObjectTargetWriter() const {
222 return createMipsELFObjectWriter(TT: TheTriple, IsN32);
223}
224
225// Little-endian fixup data byte ordering:
226// mips32r2: a | b | x | x
227// microMIPS: x | x | a | b
228
229static bool needsMMLEByteOrder(unsigned Kind) {
230 return Kind != Mips::fixup_MICROMIPS_PC10_S1 &&
231 Kind >= Mips::fixup_MICROMIPS_26_S1 &&
232 Kind < Mips::LastTargetFixupKind;
233}
234
235// Calculate index for microMIPS specific little endian byte order
236static unsigned calculateMMLEIndex(unsigned i) {
237 assert(i <= 3 && "Index out of range!");
238
239 return (1 - i / 2) * 2 + i % 2;
240}
241
242static bool shouldForceRelocation(const MCFixup &Fixup) {
243 const unsigned FixupKind = Fixup.getKind();
244 switch (FixupKind) {
245 default:
246 return false;
247 // All these relocations require special processing
248 // at linking time. Delegate this work to a linker.
249 case Mips::fixup_Mips_CALL_HI16:
250 case Mips::fixup_Mips_CALL_LO16:
251 case Mips::fixup_Mips_CALL16:
252 case Mips::fixup_Mips_GOT:
253 case Mips::fixup_Mips_GOT_PAGE:
254 case Mips::fixup_Mips_GOT_OFST:
255 case Mips::fixup_Mips_GOT_DISP:
256 case Mips::fixup_Mips_GOT_HI16:
257 case Mips::fixup_Mips_GOT_LO16:
258 case Mips::fixup_Mips_GOTTPREL:
259 case Mips::fixup_Mips_DTPREL_HI:
260 case Mips::fixup_Mips_DTPREL_LO:
261 case Mips::fixup_Mips_TLSGD:
262 case Mips::fixup_Mips_TLSLDM:
263 case Mips::fixup_Mips_TPREL_HI:
264 case Mips::fixup_Mips_TPREL_LO:
265 case Mips::fixup_Mips_JALR:
266 case Mips::fixup_MICROMIPS_CALL16:
267 case Mips::fixup_MICROMIPS_GOT_DISP:
268 case Mips::fixup_MICROMIPS_GOT_PAGE:
269 case Mips::fixup_MICROMIPS_GOT_OFST:
270 case Mips::fixup_MICROMIPS_GOT16:
271 case Mips::fixup_MICROMIPS_GOTTPREL:
272 case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16:
273 case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16:
274 case Mips::fixup_MICROMIPS_TLS_GD:
275 case Mips::fixup_MICROMIPS_TLS_LDM:
276 case Mips::fixup_MICROMIPS_TLS_TPREL_HI16:
277 case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
278 case Mips::fixup_MICROMIPS_JALR:
279 return true;
280 }
281}
282
283/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
284/// data fragment, at the offset specified by the fixup and following the
285/// fixup kind as appropriate.
286void MipsAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
287 const MCValue &Target, uint8_t *Data,
288 uint64_t Value, bool IsResolved) {
289 if (shouldForceRelocation(Fixup))
290 IsResolved = false;
291 maybeAddReloc(F, Fixup, Target, Value, IsResolved);
292 MCFixupKind Kind = Fixup.getKind();
293 MCContext &Ctx = getContext();
294 Value = adjustFixupValue(Fixup, Value, Ctx);
295
296 if (!Value)
297 return; // Doesn't change encoding.
298
299 // Where do we start in the object
300 // Number of bytes we need to fixup
301 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
302 // Used to point to big endian bytes
303 unsigned FullSize;
304
305 switch ((unsigned)Kind) {
306 case FK_Data_2:
307 case Mips::fixup_Mips_16:
308 case Mips::fixup_MICROMIPS_PC10_S1:
309 FullSize = 2;
310 break;
311 case FK_Data_8:
312 case Mips::fixup_Mips_64:
313 FullSize = 8;
314 break;
315 case FK_Data_4:
316 default:
317 FullSize = 4;
318 break;
319 }
320
321 // Grab current value, if any, from bits.
322 uint64_t CurVal = 0;
323
324 bool microMipsLEByteOrder = needsMMLEByteOrder(Kind: (unsigned) Kind);
325
326 for (unsigned i = 0; i != NumBytes; ++i) {
327 unsigned Idx = Endian == llvm::endianness::little
328 ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i)
329 : (FullSize - 1 - i);
330 CurVal |= (uint64_t)((uint8_t)Data[Idx]) << (i * 8);
331 }
332
333 uint64_t Mask = ((uint64_t)(-1) >>
334 (64 - getFixupKindInfo(Kind).TargetSize));
335 CurVal |= Value & Mask;
336
337 // Write out the fixed up bytes back to the code/data bits.
338 for (unsigned i = 0; i != NumBytes; ++i) {
339 unsigned Idx = Endian == llvm::endianness::little
340 ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i)
341 : (FullSize - 1 - i);
342 Data[Idx] = (uint8_t)((CurVal >> (i * 8)) & 0xff);
343 }
344}
345
346std::optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
347 unsigned Type = llvm::StringSwitch<unsigned>(Name)
348 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_MIPS_NONE)
349 .Case(S: "BFD_RELOC_16", Value: ELF::R_MIPS_16)
350 .Case(S: "BFD_RELOC_32", Value: ELF::R_MIPS_32)
351 .Case(S: "BFD_RELOC_64", Value: ELF::R_MIPS_64)
352 .Default(Value: -1u);
353 if (Type != -1u)
354 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
355
356 return StringSwitch<std::optional<MCFixupKind>>(Name)
357 .Case(S: "R_MIPS_NONE", Value: FK_NONE)
358 .Case(S: "R_MIPS_32", Value: FK_Data_4)
359 .Case(S: "R_MIPS_CALL_HI16", Value: Mips::fixup_Mips_CALL_HI16)
360 .Case(S: "R_MIPS_CALL_LO16", Value: Mips::fixup_Mips_CALL_LO16)
361 .Case(S: "R_MIPS_CALL16", Value: Mips::fixup_Mips_CALL16)
362 .Case(S: "R_MIPS_GOT16", Value: Mips::fixup_Mips_GOT)
363 .Case(S: "R_MIPS_GOT_PAGE", Value: Mips::fixup_Mips_GOT_PAGE)
364 .Case(S: "R_MIPS_GOT_OFST", Value: Mips::fixup_Mips_GOT_OFST)
365 .Case(S: "R_MIPS_GOT_DISP", Value: Mips::fixup_Mips_GOT_DISP)
366 .Case(S: "R_MIPS_GOT_HI16", Value: Mips::fixup_Mips_GOT_HI16)
367 .Case(S: "R_MIPS_GOT_LO16", Value: Mips::fixup_Mips_GOT_LO16)
368 .Case(S: "R_MIPS_TLS_GOTTPREL", Value: Mips::fixup_Mips_GOTTPREL)
369 .Case(S: "R_MIPS_TLS_DTPREL_HI16", Value: Mips::fixup_Mips_DTPREL_HI)
370 .Case(S: "R_MIPS_TLS_DTPREL_LO16", Value: Mips::fixup_Mips_DTPREL_LO)
371 .Case(S: "R_MIPS_TLS_GD", Value: Mips::fixup_Mips_TLSGD)
372 .Case(S: "R_MIPS_TLS_LDM", Value: Mips::fixup_Mips_TLSLDM)
373 .Case(S: "R_MIPS_TLS_TPREL_HI16", Value: Mips::fixup_Mips_TPREL_HI)
374 .Case(S: "R_MIPS_TLS_TPREL_LO16", Value: Mips::fixup_Mips_TPREL_LO)
375 .Case(S: "R_MICROMIPS_CALL16", Value: Mips::fixup_MICROMIPS_CALL16)
376 .Case(S: "R_MICROMIPS_GOT_DISP", Value: Mips::fixup_MICROMIPS_GOT_DISP)
377 .Case(S: "R_MICROMIPS_GOT_PAGE", Value: Mips::fixup_MICROMIPS_GOT_PAGE)
378 .Case(S: "R_MICROMIPS_GOT_OFST", Value: Mips::fixup_MICROMIPS_GOT_OFST)
379 .Case(S: "R_MICROMIPS_GOT16", Value: Mips::fixup_MICROMIPS_GOT16)
380 .Case(S: "R_MICROMIPS_TLS_GOTTPREL", Value: Mips::fixup_MICROMIPS_GOTTPREL)
381 .Case(S: "R_MICROMIPS_TLS_DTPREL_HI16",
382 Value: Mips::fixup_MICROMIPS_TLS_DTPREL_HI16)
383 .Case(S: "R_MICROMIPS_TLS_DTPREL_LO16",
384 Value: Mips::fixup_MICROMIPS_TLS_DTPREL_LO16)
385 .Case(S: "R_MICROMIPS_TLS_GD", Value: Mips::fixup_MICROMIPS_TLS_GD)
386 .Case(S: "R_MICROMIPS_TLS_LDM", Value: Mips::fixup_MICROMIPS_TLS_LDM)
387 .Case(S: "R_MICROMIPS_TLS_TPREL_HI16", Value: Mips::fixup_MICROMIPS_TLS_TPREL_HI16)
388 .Case(S: "R_MICROMIPS_TLS_TPREL_LO16", Value: Mips::fixup_MICROMIPS_TLS_TPREL_LO16)
389 .Case(S: "R_MIPS_JALR", Value: Mips::fixup_Mips_JALR)
390 .Case(S: "R_MICROMIPS_JALR", Value: Mips::fixup_MICROMIPS_JALR)
391 .Default(Value: MCAsmBackend::getFixupKind(Name));
392}
393
394MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
395 const static MCFixupKindInfo LittleEndianInfos[] = {
396 // This table *must* be in same the order of fixup_* kinds in
397 // MipsFixupKinds.h.
398 //
399 // name offset bits flags
400 // clang-format off
401 { .Name: "fixup_Mips_16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
402 { .Name: "fixup_Mips_32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
403 { .Name: "fixup_Mips_REL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
404 { .Name: "fixup_Mips_GPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
405 { .Name: "fixup_Mips_DTPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
406 { .Name: "fixup_Mips_DTPREL64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
407 { .Name: "fixup_Mips_TPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
408 { .Name: "fixup_Mips_TPREL64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
409 { .Name: "fixup_Mips_26", .TargetOffset: 0, .TargetSize: 26, .Flags: 0 },
410 { .Name: "fixup_Mips_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
411 { .Name: "fixup_Mips_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
412 { .Name: "fixup_Mips_AnyImm16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
413 { .Name: "fixup_Mips_GPREL16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
414 { .Name: "fixup_Mips_LITERAL", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
415 { .Name: "fixup_Mips_GOT", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
416 { .Name: "fixup_Mips_PC16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
417 { .Name: "fixup_Mips_CALL16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
418 { .Name: "fixup_Mips_SHIFT5", .TargetOffset: 6, .TargetSize: 5, .Flags: 0 },
419 { .Name: "fixup_Mips_SHIFT6", .TargetOffset: 6, .TargetSize: 5, .Flags: 0 },
420 { .Name: "fixup_Mips_64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
421 { .Name: "fixup_Mips_TLSGD", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
422 { .Name: "fixup_Mips_GOTTPREL", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
423 { .Name: "fixup_Mips_TPREL_HI", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
424 { .Name: "fixup_Mips_TPREL_LO", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
425 { .Name: "fixup_Mips_TLSLDM", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
426 { .Name: "fixup_Mips_DTPREL_HI", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
427 { .Name: "fixup_Mips_DTPREL_LO", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
428 { .Name: "fixup_Mips_Branch_PCRel", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
429 { .Name: "fixup_Mips_GPOFF_HI", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
430 { .Name: "fixup_MICROMIPS_GPOFF_HI",.TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
431 { .Name: "fixup_Mips_GPOFF_LO", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
432 { .Name: "fixup_MICROMIPS_GPOFF_LO",.TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
433 { .Name: "fixup_Mips_GOT_PAGE", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
434 { .Name: "fixup_Mips_GOT_OFST", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
435 { .Name: "fixup_Mips_GOT_DISP", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
436 { .Name: "fixup_Mips_HIGHER", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
437 { .Name: "fixup_MICROMIPS_HIGHER", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
438 { .Name: "fixup_Mips_HIGHEST", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
439 { .Name: "fixup_MICROMIPS_HIGHEST", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
440 { .Name: "fixup_Mips_GOT_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
441 { .Name: "fixup_Mips_GOT_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
442 { .Name: "fixup_Mips_CALL_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
443 { .Name: "fixup_Mips_CALL_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
444 { .Name: "fixup_Mips_PC18_S3", .TargetOffset: 0, .TargetSize: 18, .Flags: 0 },
445 { .Name: "fixup_MIPS_PC19_S2", .TargetOffset: 0, .TargetSize: 19, .Flags: 0 },
446 { .Name: "fixup_MIPS_PC21_S2", .TargetOffset: 0, .TargetSize: 21, .Flags: 0 },
447 { .Name: "fixup_MIPS_PC26_S2", .TargetOffset: 0, .TargetSize: 26, .Flags: 0 },
448 { .Name: "fixup_MIPS_PCHI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
449 { .Name: "fixup_MIPS_PCLO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
450 { .Name: "fixup_MICROMIPS_26_S1", .TargetOffset: 0, .TargetSize: 26, .Flags: 0 },
451 { .Name: "fixup_MICROMIPS_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
452 { .Name: "fixup_MICROMIPS_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
453 { .Name: "fixup_MICROMIPS_GOT16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
454 { .Name: "fixup_MICROMIPS_PC7_S1", .TargetOffset: 0, .TargetSize: 7, .Flags: 0 },
455 { .Name: "fixup_MICROMIPS_PC10_S1", .TargetOffset: 0, .TargetSize: 10, .Flags: 0 },
456 { .Name: "fixup_MICROMIPS_PC16_S1", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
457 { .Name: "fixup_MICROMIPS_PC26_S1", .TargetOffset: 0, .TargetSize: 26, .Flags: 0 },
458 { .Name: "fixup_MICROMIPS_PC19_S2", .TargetOffset: 0, .TargetSize: 19, .Flags: 0 },
459 { .Name: "fixup_MICROMIPS_PC18_S3", .TargetOffset: 0, .TargetSize: 18, .Flags: 0 },
460 { .Name: "fixup_MICROMIPS_PC21_S1", .TargetOffset: 0, .TargetSize: 21, .Flags: 0 },
461 { .Name: "fixup_MICROMIPS_CALL16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
462 { .Name: "fixup_MICROMIPS_GOT_DISP", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
463 { .Name: "fixup_MICROMIPS_GOT_PAGE", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
464 { .Name: "fixup_MICROMIPS_GOT_OFST", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
465 { .Name: "fixup_MICROMIPS_TLS_GD", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
466 { .Name: "fixup_MICROMIPS_TLS_LDM", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
467 { .Name: "fixup_MICROMIPS_TLS_DTPREL_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
468 { .Name: "fixup_MICROMIPS_TLS_DTPREL_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
469 { .Name: "fixup_MICROMIPS_GOTTPREL", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
470 { .Name: "fixup_MICROMIPS_TLS_TPREL_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
471 { .Name: "fixup_MICROMIPS_TLS_TPREL_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
472 { .Name: "fixup_Mips_SUB", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
473 { .Name: "fixup_MICROMIPS_SUB", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
474 { .Name: "fixup_Mips_JALR", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
475 { .Name: "fixup_MICROMIPS_JALR", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
476 // clang-format on
477 };
478 static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds,
479 "Not all MIPS little endian fixup kinds added!");
480
481 const static MCFixupKindInfo BigEndianInfos[] = {
482 // This table *must* be in same the order of fixup_* kinds in
483 // MipsFixupKinds.h.
484 //
485 // name offset bits flags
486 // clang-format off
487 { .Name: "fixup_Mips_16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
488 { .Name: "fixup_Mips_32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
489 { .Name: "fixup_Mips_REL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
490 { .Name: "fixup_Mips_GPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
491 { .Name: "fixup_Mips_DTPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
492 { .Name: "fixup_Mips_DTPREL64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
493 { .Name: "fixup_Mips_TPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
494 { .Name: "fixup_Mips_TPREL64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
495 { .Name: "fixup_Mips_26", .TargetOffset: 6, .TargetSize: 26, .Flags: 0 },
496 { .Name: "fixup_Mips_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
497 { .Name: "fixup_Mips_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
498 { .Name: "fixup_Mips_AnyImm16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
499 { .Name: "fixup_Mips_GPREL16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
500 { .Name: "fixup_Mips_LITERAL", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
501 { .Name: "fixup_Mips_GOT", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
502 { .Name: "fixup_Mips_PC16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
503 { .Name: "fixup_Mips_CALL16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
504 { .Name: "fixup_Mips_SHIFT5", .TargetOffset: 21, .TargetSize: 5, .Flags: 0 },
505 { .Name: "fixup_Mips_SHIFT6", .TargetOffset: 21, .TargetSize: 5, .Flags: 0 },
506 { .Name: "fixup_Mips_64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
507 { .Name: "fixup_Mips_TLSGD", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
508 { .Name: "fixup_Mips_GOTTPREL", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
509 { .Name: "fixup_Mips_TPREL_HI", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
510 { .Name: "fixup_Mips_TPREL_LO", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
511 { .Name: "fixup_Mips_TLSLDM", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
512 { .Name: "fixup_Mips_DTPREL_HI", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
513 { .Name: "fixup_Mips_DTPREL_LO", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
514 { .Name: "fixup_Mips_Branch_PCRel",.TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
515 { .Name: "fixup_Mips_GPOFF_HI", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
516 { .Name: "fixup_MICROMIPS_GPOFF_HI", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
517 { .Name: "fixup_Mips_GPOFF_LO", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
518 { .Name: "fixup_MICROMIPS_GPOFF_LO", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
519 { .Name: "fixup_Mips_GOT_PAGE", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
520 { .Name: "fixup_Mips_GOT_OFST", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
521 { .Name: "fixup_Mips_GOT_DISP", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
522 { .Name: "fixup_Mips_HIGHER", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
523 { .Name: "fixup_MICROMIPS_HIGHER", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
524 { .Name: "fixup_Mips_HIGHEST", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
525 { .Name: "fixup_MICROMIPS_HIGHEST",.TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
526 { .Name: "fixup_Mips_GOT_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
527 { .Name: "fixup_Mips_GOT_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
528 { .Name: "fixup_Mips_CALL_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
529 { .Name: "fixup_Mips_CALL_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
530 { .Name: "fixup_Mips_PC18_S3", .TargetOffset: 14, .TargetSize: 18, .Flags: 0 },
531 { .Name: "fixup_MIPS_PC19_S2", .TargetOffset: 13, .TargetSize: 19, .Flags: 0 },
532 { .Name: "fixup_MIPS_PC21_S2", .TargetOffset: 11, .TargetSize: 21, .Flags: 0 },
533 { .Name: "fixup_MIPS_PC26_S2", .TargetOffset: 6, .TargetSize: 26, .Flags: 0 },
534 { .Name: "fixup_MIPS_PCHI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
535 { .Name: "fixup_MIPS_PCLO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
536 { .Name: "fixup_MICROMIPS_26_S1", .TargetOffset: 6, .TargetSize: 26, .Flags: 0 },
537 { .Name: "fixup_MICROMIPS_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
538 { .Name: "fixup_MICROMIPS_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
539 { .Name: "fixup_MICROMIPS_GOT16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
540 { .Name: "fixup_MICROMIPS_PC7_S1", .TargetOffset: 9, .TargetSize: 7, .Flags: 0 },
541 { .Name: "fixup_MICROMIPS_PC10_S1", .TargetOffset: 6, .TargetSize: 10, .Flags: 0 },
542 { .Name: "fixup_MICROMIPS_PC16_S1",.TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
543 { .Name: "fixup_MICROMIPS_PC26_S1", .TargetOffset: 6, .TargetSize: 26, .Flags: 0 },
544 { .Name: "fixup_MICROMIPS_PC19_S2",.TargetOffset: 13, .TargetSize: 19, .Flags: 0 },
545 { .Name: "fixup_MICROMIPS_PC18_S3",.TargetOffset: 14, .TargetSize: 18, .Flags: 0 },
546 { .Name: "fixup_MICROMIPS_PC21_S1",.TargetOffset: 11, .TargetSize: 21, .Flags: 0 },
547 { .Name: "fixup_MICROMIPS_CALL16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
548 { .Name: "fixup_MICROMIPS_GOT_DISP", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
549 { .Name: "fixup_MICROMIPS_GOT_PAGE", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
550 { .Name: "fixup_MICROMIPS_GOT_OFST", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
551 { .Name: "fixup_MICROMIPS_TLS_GD", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
552 { .Name: "fixup_MICROMIPS_TLS_LDM", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
553 { .Name: "fixup_MICROMIPS_TLS_DTPREL_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
554 { .Name: "fixup_MICROMIPS_TLS_DTPREL_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
555 { .Name: "fixup_MICROMIPS_GOTTPREL", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
556 { .Name: "fixup_MICROMIPS_TLS_TPREL_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
557 { .Name: "fixup_MICROMIPS_TLS_TPREL_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
558 { .Name: "fixup_Mips_SUB", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
559 { .Name: "fixup_MICROMIPS_SUB", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
560 { .Name: "fixup_Mips_JALR", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
561 { .Name: "fixup_MICROMIPS_JALR", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
562 // clang-format on
563 };
564 static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds,
565 "Not all MIPS big endian fixup kinds added!");
566
567 if (mc::isRelocation(FixupKind: Kind))
568 return {};
569 if (Kind < FirstTargetFixupKind)
570 return MCAsmBackend::getFixupKindInfo(Kind);
571
572 assert(unsigned(Kind - FirstTargetFixupKind) < Mips::NumTargetFixupKinds &&
573 "Invalid kind!");
574
575 if (Endian == llvm::endianness::little)
576 return LittleEndianInfos[Kind - FirstTargetFixupKind];
577 return BigEndianInfos[Kind - FirstTargetFixupKind];
578}
579
580/// WriteNopData - Write an (optimal) nop sequence of Count bytes
581/// to the given output. If the target cannot generate such a sequence,
582/// it should return an error.
583///
584/// \return - True on success.
585bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
586 const MCSubtargetInfo *STI) const {
587 // We mostly follow binutils' convention here: align to an even boundary with
588 // zero-fill padding, then emit up to one 2-byte NOP. Use move $zero, $zero
589 // for microMIPS, or zero-fill for standard MIPS. Pad the remainder with
590 // 4-byte NOPs.
591
592 // An odd byte is data padding. Align to an instruction boundary first.
593 if (Count % 2) {
594 OS.write_zeros(NumZeros: 1);
595 Count -= 1;
596 }
597
598 if (Count % 4 == 2) {
599 // Use move $zero, $zero for a microMIPS 16-bit NOP. For standard MIPS,
600 // this halfword is data padding.
601 uint16_t Nop = STI && STI->hasFeature(Feature: Mips::FeatureMicroMips) ? 0x0c00 : 0;
602 support::endian::write<uint16_t>(os&: OS, value: Nop, endian: Endian);
603 Count -= 2;
604 }
605
606 // Zero encodes a 32-bit NOP in both standard MIPS and microMIPS.
607 OS.write_zeros(NumZeros: Count);
608 return true;
609}
610
611namespace {
612
613class WindowsMipsAsmBackend : public MipsAsmBackend {
614public:
615 WindowsMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI,
616 const MCSubtargetInfo &STI)
617 : MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), false) {}
618
619 std::unique_ptr<MCObjectTargetWriter>
620 createObjectTargetWriter() const override {
621 return createMipsWinCOFFObjectWriter();
622 }
623};
624
625} // end anonymous namespace
626
627MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
628 const MCSubtargetInfo &STI,
629 const MCRegisterInfo &MRI,
630 const MCTargetOptions &Options) {
631 const Triple &TheTriple = STI.getTargetTriple();
632 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
633 return new WindowsMipsAsmBackend(T, MRI, STI);
634
635 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT: STI.getTargetTriple(),
636 ABIName: Options.getABIName());
637 return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
638 ABI.IsN32());
639}
640