1//===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the MipsAsmBackend class.
10//
11//===----------------------------------------------------------------------===//
12//
13
14#include "MCTargetDesc/MipsAsmBackend.h"
15#include "MCTargetDesc/MipsABIInfo.h"
16#include "MCTargetDesc/MipsFixupKinds.h"
17#include "MCTargetDesc/MipsMCTargetDesc.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/MC/MCAsmBackend.h"
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCELFObjectWriter.h"
23#include "llvm/MC/MCObjectWriter.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/MCTargetOptions.h"
26#include "llvm/MC/MCValue.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/MathExtras.h"
29#include "llvm/Support/raw_ostream.h"
30
31using namespace llvm;
32
33// Prepare value for the target space for it
34static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
35 MCContext &Ctx) {
36
37 unsigned Kind = Fixup.getKind();
38
39 // Add/subtract and shift
40 switch (Kind) {
41 default:
42 return 0;
43 case FK_Data_2:
44 case Mips::fixup_Mips_LO16:
45 case Mips::fixup_Mips_GPREL16:
46 case Mips::fixup_Mips_GPOFF_HI:
47 case Mips::fixup_Mips_GPOFF_LO:
48 case Mips::fixup_Mips_GOT_PAGE:
49 case Mips::fixup_Mips_GOT_OFST:
50 case Mips::fixup_Mips_GOT_DISP:
51 case Mips::fixup_Mips_GOT_LO16:
52 case Mips::fixup_Mips_CALL_LO16:
53 case Mips::fixup_MICROMIPS_GPOFF_HI:
54 case Mips::fixup_MICROMIPS_GPOFF_LO:
55 case Mips::fixup_MICROMIPS_LO16:
56 case Mips::fixup_MICROMIPS_GOT_PAGE:
57 case Mips::fixup_MICROMIPS_GOT_OFST:
58 case Mips::fixup_MICROMIPS_GOT_DISP:
59 case Mips::fixup_MIPS_PCLO16:
60 Value &= 0xffff;
61 break;
62 case Mips::fixup_Mips_AnyImm16:
63 if (!isInt<16>(x: Value) && !isUInt<16>(x: Value))
64 Ctx.reportError(L: Fixup.getLoc(),
65 Msg: "fixup value out of range [-32768, 65535]");
66 break;
67 case Mips::fixup_Mips_GPREL32:
68 case Mips::fixup_Mips_DTPREL32:
69 case Mips::fixup_Mips_DTPREL64:
70 case Mips::fixup_Mips_TPREL32:
71 case Mips::fixup_Mips_TPREL64:
72 case FK_Data_4:
73 case FK_Data_8:
74 case Mips::fixup_Mips_SUB:
75 case Mips::fixup_MICROMIPS_SUB:
76 break;
77 case Mips::fixup_Mips_PC16:
78 // The displacement is then divided by 4 to give us an 18 bit
79 // address range. Forcing a signed division because Value can be negative.
80 Value = (int64_t)Value / 4;
81 // We now check if Value can be encoded as a 16-bit signed immediate.
82 if (!isInt<16>(x: Value)) {
83 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC16 fixup");
84 return 0;
85 }
86 break;
87 case Mips::fixup_MIPS_PC19_S2:
88 case Mips::fixup_MICROMIPS_PC19_S2:
89 // Forcing a signed division because Value can be negative.
90 Value = (int64_t)Value / 4;
91 // We now check if Value can be encoded as a 19-bit signed immediate.
92 if (!isInt<19>(x: Value)) {
93 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC19 fixup");
94 return 0;
95 }
96 break;
97 case Mips::fixup_Mips_26:
98 // So far we are only using this type for jumps.
99 // The displacement is then divided by 4 to give us an 28 bit
100 // address range.
101 Value >>= 2;
102 break;
103 case Mips::fixup_Mips_HI16:
104 case Mips::fixup_Mips_GOT:
105 case Mips::fixup_MICROMIPS_GOT16:
106 case Mips::fixup_Mips_GOT_HI16:
107 case Mips::fixup_Mips_CALL_HI16:
108 case Mips::fixup_MICROMIPS_HI16:
109 case Mips::fixup_MIPS_PCHI16:
110 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
111 Value = ((Value + 0x8000) >> 16) & 0xffff;
112 break;
113 case Mips::fixup_Mips_HIGHER:
114 case Mips::fixup_MICROMIPS_HIGHER:
115 // Get the 3rd 16-bits.
116 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
117 break;
118 case Mips::fixup_Mips_HIGHEST:
119 case Mips::fixup_MICROMIPS_HIGHEST:
120 // Get the 4th 16-bits.
121 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
122 break;
123 case Mips::fixup_MICROMIPS_26_S1:
124 Value >>= 1;
125 break;
126 case Mips::fixup_MICROMIPS_PC7_S1:
127 Value -= 4;
128 // Forcing a signed division because Value can be negative.
129 Value = (int64_t) Value / 2;
130 // We now check if Value can be encoded as a 7-bit signed immediate.
131 if (!isInt<7>(x: Value)) {
132 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC7 fixup");
133 return 0;
134 }
135 break;
136 case Mips::fixup_MICROMIPS_PC10_S1:
137 Value -= 2;
138 // Forcing a signed division because Value can be negative.
139 Value = (int64_t) Value / 2;
140 // We now check if Value can be encoded as a 10-bit signed immediate.
141 if (!isInt<10>(x: Value)) {
142 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC10 fixup");
143 return 0;
144 }
145 break;
146 case Mips::fixup_MICROMIPS_PC16_S1:
147 Value -= 4;
148 // Forcing a signed division because Value can be negative.
149 Value = (int64_t)Value / 2;
150 // We now check if Value can be encoded as a 16-bit signed immediate.
151 if (!isInt<16>(x: Value)) {
152 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC16 fixup");
153 return 0;
154 }
155 break;
156 case Mips::fixup_MIPS_PC18_S3:
157 // Forcing a signed division because Value can be negative.
158 Value = (int64_t)Value / 8;
159 // We now check if Value can be encoded as a 18-bit signed immediate.
160 if (!isInt<18>(x: Value)) {
161 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup");
162 return 0;
163 }
164 break;
165 case Mips::fixup_MICROMIPS_PC18_S3:
166 // Check alignment.
167 if ((Value & 7)) {
168 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup");
169 }
170 // Forcing a signed division because Value can be negative.
171 Value = (int64_t)Value / 8;
172 // We now check if Value can be encoded as a 18-bit signed immediate.
173 if (!isInt<18>(x: Value)) {
174 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup");
175 return 0;
176 }
177 break;
178 case Mips::fixup_MIPS_PC21_S2:
179 // Forcing a signed division because Value can be negative.
180 Value = (int64_t) Value / 4;
181 // We now check if Value can be encoded as a 21-bit signed immediate.
182 if (!isInt<21>(x: Value)) {
183 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC21 fixup");
184 return 0;
185 }
186 break;
187 case Mips::fixup_MIPS_PC26_S2:
188 // Forcing a signed division because Value can be negative.
189 Value = (int64_t) Value / 4;
190 // We now check if Value can be encoded as a 26-bit signed immediate.
191 if (!isInt<26>(x: Value)) {
192 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC26 fixup");
193 return 0;
194 }
195 break;
196 case Mips::fixup_MICROMIPS_PC26_S1:
197 // Forcing a signed division because Value can be negative.
198 Value = (int64_t)Value / 2;
199 // We now check if Value can be encoded as a 26-bit signed immediate.
200 if (!isInt<26>(x: Value)) {
201 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC26 fixup");
202 return 0;
203 }
204 break;
205 case Mips::fixup_MICROMIPS_PC21_S1:
206 // Forcing a signed division because Value can be negative.
207 Value = (int64_t)Value / 2;
208 // We now check if Value can be encoded as a 21-bit signed immediate.
209 if (!isInt<21>(x: Value)) {
210 Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC21 fixup");
211 return 0;
212 }
213 break;
214 }
215
216 return Value;
217}
218
219std::unique_ptr<MCObjectTargetWriter>
220MipsAsmBackend::createObjectTargetWriter() const {
221 return createMipsELFObjectWriter(TT: TheTriple, IsN32);
222}
223
224// Little-endian fixup data byte ordering:
225// mips32r2: a | b | x | x
226// microMIPS: x | x | a | b
227
228static bool needsMMLEByteOrder(unsigned Kind) {
229 return Kind != Mips::fixup_MICROMIPS_PC10_S1 &&
230 Kind >= Mips::fixup_MICROMIPS_26_S1 &&
231 Kind < Mips::LastTargetFixupKind;
232}
233
234// Calculate index for microMIPS specific little endian byte order
235static unsigned calculateMMLEIndex(unsigned i) {
236 assert(i <= 3 && "Index out of range!");
237
238 return (1 - i / 2) * 2 + i % 2;
239}
240
241static bool shouldForceRelocation(const MCFixup &Fixup) {
242 const unsigned FixupKind = Fixup.getKind();
243 switch (FixupKind) {
244 default:
245 return false;
246 // All these relocations require special processing
247 // at linking time. Delegate this work to a linker.
248 case Mips::fixup_Mips_CALL_HI16:
249 case Mips::fixup_Mips_CALL_LO16:
250 case Mips::fixup_Mips_CALL16:
251 case Mips::fixup_Mips_GOT:
252 case Mips::fixup_Mips_GOT_PAGE:
253 case Mips::fixup_Mips_GOT_OFST:
254 case Mips::fixup_Mips_GOT_DISP:
255 case Mips::fixup_Mips_GOT_HI16:
256 case Mips::fixup_Mips_GOT_LO16:
257 case Mips::fixup_Mips_GOTTPREL:
258 case Mips::fixup_Mips_DTPREL_HI:
259 case Mips::fixup_Mips_DTPREL_LO:
260 case Mips::fixup_Mips_TLSGD:
261 case Mips::fixup_Mips_TLSLDM:
262 case Mips::fixup_Mips_TPREL_HI:
263 case Mips::fixup_Mips_TPREL_LO:
264 case Mips::fixup_Mips_JALR:
265 case Mips::fixup_MICROMIPS_CALL16:
266 case Mips::fixup_MICROMIPS_GOT_DISP:
267 case Mips::fixup_MICROMIPS_GOT_PAGE:
268 case Mips::fixup_MICROMIPS_GOT_OFST:
269 case Mips::fixup_MICROMIPS_GOT16:
270 case Mips::fixup_MICROMIPS_GOTTPREL:
271 case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16:
272 case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16:
273 case Mips::fixup_MICROMIPS_TLS_GD:
274 case Mips::fixup_MICROMIPS_TLS_LDM:
275 case Mips::fixup_MICROMIPS_TLS_TPREL_HI16:
276 case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
277 case Mips::fixup_MICROMIPS_JALR:
278 return true;
279 }
280}
281
282/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
283/// data fragment, at the offset specified by the fixup and following the
284/// fixup kind as appropriate.
285void MipsAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
286 const MCValue &Target, uint8_t *Data,
287 uint64_t Value, bool IsResolved) {
288 if (shouldForceRelocation(Fixup))
289 IsResolved = false;
290 maybeAddReloc(F, Fixup, Target, Value, IsResolved);
291 MCFixupKind Kind = Fixup.getKind();
292 MCContext &Ctx = getContext();
293 Value = adjustFixupValue(Fixup, Value, Ctx);
294
295 if (!Value)
296 return; // Doesn't change encoding.
297
298 // Where do we start in the object
299 // Number of bytes we need to fixup
300 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
301 // Used to point to big endian bytes
302 unsigned FullSize;
303
304 switch ((unsigned)Kind) {
305 case FK_Data_2:
306 case Mips::fixup_Mips_16:
307 case Mips::fixup_MICROMIPS_PC10_S1:
308 FullSize = 2;
309 break;
310 case FK_Data_8:
311 case Mips::fixup_Mips_64:
312 FullSize = 8;
313 break;
314 case FK_Data_4:
315 default:
316 FullSize = 4;
317 break;
318 }
319
320 // Grab current value, if any, from bits.
321 uint64_t CurVal = 0;
322
323 bool microMipsLEByteOrder = needsMMLEByteOrder(Kind: (unsigned) Kind);
324
325 for (unsigned i = 0; i != NumBytes; ++i) {
326 unsigned Idx = Endian == llvm::endianness::little
327 ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i)
328 : (FullSize - 1 - i);
329 CurVal |= (uint64_t)((uint8_t)Data[Idx]) << (i * 8);
330 }
331
332 uint64_t Mask = ((uint64_t)(-1) >>
333 (64 - getFixupKindInfo(Kind).TargetSize));
334 CurVal |= Value & Mask;
335
336 // Write out the fixed up bytes back to the code/data bits.
337 for (unsigned i = 0; i != NumBytes; ++i) {
338 unsigned Idx = Endian == llvm::endianness::little
339 ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i)
340 : (FullSize - 1 - i);
341 Data[Idx] = (uint8_t)((CurVal >> (i * 8)) & 0xff);
342 }
343}
344
345std::optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
346 unsigned Type = llvm::StringSwitch<unsigned>(Name)
347 .Case(S: "BFD_RELOC_NONE", Value: ELF::R_MIPS_NONE)
348 .Case(S: "BFD_RELOC_16", Value: ELF::R_MIPS_16)
349 .Case(S: "BFD_RELOC_32", Value: ELF::R_MIPS_32)
350 .Case(S: "BFD_RELOC_64", Value: ELF::R_MIPS_64)
351 .Default(Value: -1u);
352 if (Type != -1u)
353 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
354
355 return StringSwitch<std::optional<MCFixupKind>>(Name)
356 .Case(S: "R_MIPS_NONE", Value: FK_NONE)
357 .Case(S: "R_MIPS_32", Value: FK_Data_4)
358 .Case(S: "R_MIPS_CALL_HI16", Value: Mips::fixup_Mips_CALL_HI16)
359 .Case(S: "R_MIPS_CALL_LO16", Value: Mips::fixup_Mips_CALL_LO16)
360 .Case(S: "R_MIPS_CALL16", Value: Mips::fixup_Mips_CALL16)
361 .Case(S: "R_MIPS_GOT16", Value: Mips::fixup_Mips_GOT)
362 .Case(S: "R_MIPS_GOT_PAGE", Value: Mips::fixup_Mips_GOT_PAGE)
363 .Case(S: "R_MIPS_GOT_OFST", Value: Mips::fixup_Mips_GOT_OFST)
364 .Case(S: "R_MIPS_GOT_DISP", Value: Mips::fixup_Mips_GOT_DISP)
365 .Case(S: "R_MIPS_GOT_HI16", Value: Mips::fixup_Mips_GOT_HI16)
366 .Case(S: "R_MIPS_GOT_LO16", Value: Mips::fixup_Mips_GOT_LO16)
367 .Case(S: "R_MIPS_TLS_GOTTPREL", Value: Mips::fixup_Mips_GOTTPREL)
368 .Case(S: "R_MIPS_TLS_DTPREL_HI16", Value: Mips::fixup_Mips_DTPREL_HI)
369 .Case(S: "R_MIPS_TLS_DTPREL_LO16", Value: Mips::fixup_Mips_DTPREL_LO)
370 .Case(S: "R_MIPS_TLS_GD", Value: Mips::fixup_Mips_TLSGD)
371 .Case(S: "R_MIPS_TLS_LDM", Value: Mips::fixup_Mips_TLSLDM)
372 .Case(S: "R_MIPS_TLS_TPREL_HI16", Value: Mips::fixup_Mips_TPREL_HI)
373 .Case(S: "R_MIPS_TLS_TPREL_LO16", Value: Mips::fixup_Mips_TPREL_LO)
374 .Case(S: "R_MICROMIPS_CALL16", Value: Mips::fixup_MICROMIPS_CALL16)
375 .Case(S: "R_MICROMIPS_GOT_DISP", Value: Mips::fixup_MICROMIPS_GOT_DISP)
376 .Case(S: "R_MICROMIPS_GOT_PAGE", Value: Mips::fixup_MICROMIPS_GOT_PAGE)
377 .Case(S: "R_MICROMIPS_GOT_OFST", Value: Mips::fixup_MICROMIPS_GOT_OFST)
378 .Case(S: "R_MICROMIPS_GOT16", Value: Mips::fixup_MICROMIPS_GOT16)
379 .Case(S: "R_MICROMIPS_TLS_GOTTPREL", Value: Mips::fixup_MICROMIPS_GOTTPREL)
380 .Case(S: "R_MICROMIPS_TLS_DTPREL_HI16",
381 Value: Mips::fixup_MICROMIPS_TLS_DTPREL_HI16)
382 .Case(S: "R_MICROMIPS_TLS_DTPREL_LO16",
383 Value: Mips::fixup_MICROMIPS_TLS_DTPREL_LO16)
384 .Case(S: "R_MICROMIPS_TLS_GD", Value: Mips::fixup_MICROMIPS_TLS_GD)
385 .Case(S: "R_MICROMIPS_TLS_LDM", Value: Mips::fixup_MICROMIPS_TLS_LDM)
386 .Case(S: "R_MICROMIPS_TLS_TPREL_HI16", Value: Mips::fixup_MICROMIPS_TLS_TPREL_HI16)
387 .Case(S: "R_MICROMIPS_TLS_TPREL_LO16", Value: Mips::fixup_MICROMIPS_TLS_TPREL_LO16)
388 .Case(S: "R_MIPS_JALR", Value: Mips::fixup_Mips_JALR)
389 .Case(S: "R_MICROMIPS_JALR", Value: Mips::fixup_MICROMIPS_JALR)
390 .Default(Value: MCAsmBackend::getFixupKind(Name));
391}
392
393MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
394 const static MCFixupKindInfo LittleEndianInfos[] = {
395 // This table *must* be in same the order of fixup_* kinds in
396 // MipsFixupKinds.h.
397 //
398 // name offset bits flags
399 // clang-format off
400 { .Name: "fixup_Mips_16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
401 { .Name: "fixup_Mips_32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
402 { .Name: "fixup_Mips_REL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
403 { .Name: "fixup_Mips_GPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
404 { .Name: "fixup_Mips_DTPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
405 { .Name: "fixup_Mips_DTPREL64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
406 { .Name: "fixup_Mips_TPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
407 { .Name: "fixup_Mips_TPREL64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
408 { .Name: "fixup_Mips_26", .TargetOffset: 0, .TargetSize: 26, .Flags: 0 },
409 { .Name: "fixup_Mips_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
410 { .Name: "fixup_Mips_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
411 { .Name: "fixup_Mips_AnyImm16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
412 { .Name: "fixup_Mips_GPREL16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
413 { .Name: "fixup_Mips_LITERAL", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
414 { .Name: "fixup_Mips_GOT", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
415 { .Name: "fixup_Mips_PC16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
416 { .Name: "fixup_Mips_CALL16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
417 { .Name: "fixup_Mips_SHIFT5", .TargetOffset: 6, .TargetSize: 5, .Flags: 0 },
418 { .Name: "fixup_Mips_SHIFT6", .TargetOffset: 6, .TargetSize: 5, .Flags: 0 },
419 { .Name: "fixup_Mips_64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
420 { .Name: "fixup_Mips_TLSGD", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
421 { .Name: "fixup_Mips_GOTTPREL", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
422 { .Name: "fixup_Mips_TPREL_HI", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
423 { .Name: "fixup_Mips_TPREL_LO", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
424 { .Name: "fixup_Mips_TLSLDM", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
425 { .Name: "fixup_Mips_DTPREL_HI", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
426 { .Name: "fixup_Mips_DTPREL_LO", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
427 { .Name: "fixup_Mips_Branch_PCRel", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
428 { .Name: "fixup_Mips_GPOFF_HI", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
429 { .Name: "fixup_MICROMIPS_GPOFF_HI",.TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
430 { .Name: "fixup_Mips_GPOFF_LO", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
431 { .Name: "fixup_MICROMIPS_GPOFF_LO",.TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
432 { .Name: "fixup_Mips_GOT_PAGE", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
433 { .Name: "fixup_Mips_GOT_OFST", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
434 { .Name: "fixup_Mips_GOT_DISP", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
435 { .Name: "fixup_Mips_HIGHER", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
436 { .Name: "fixup_MICROMIPS_HIGHER", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
437 { .Name: "fixup_Mips_HIGHEST", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
438 { .Name: "fixup_MICROMIPS_HIGHEST", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
439 { .Name: "fixup_Mips_GOT_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
440 { .Name: "fixup_Mips_GOT_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
441 { .Name: "fixup_Mips_CALL_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
442 { .Name: "fixup_Mips_CALL_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
443 { .Name: "fixup_Mips_PC18_S3", .TargetOffset: 0, .TargetSize: 18, .Flags: 0 },
444 { .Name: "fixup_MIPS_PC19_S2", .TargetOffset: 0, .TargetSize: 19, .Flags: 0 },
445 { .Name: "fixup_MIPS_PC21_S2", .TargetOffset: 0, .TargetSize: 21, .Flags: 0 },
446 { .Name: "fixup_MIPS_PC26_S2", .TargetOffset: 0, .TargetSize: 26, .Flags: 0 },
447 { .Name: "fixup_MIPS_PCHI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
448 { .Name: "fixup_MIPS_PCLO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
449 { .Name: "fixup_MICROMIPS_26_S1", .TargetOffset: 0, .TargetSize: 26, .Flags: 0 },
450 { .Name: "fixup_MICROMIPS_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
451 { .Name: "fixup_MICROMIPS_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
452 { .Name: "fixup_MICROMIPS_GOT16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
453 { .Name: "fixup_MICROMIPS_PC7_S1", .TargetOffset: 0, .TargetSize: 7, .Flags: 0 },
454 { .Name: "fixup_MICROMIPS_PC10_S1", .TargetOffset: 0, .TargetSize: 10, .Flags: 0 },
455 { .Name: "fixup_MICROMIPS_PC16_S1", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
456 { .Name: "fixup_MICROMIPS_PC26_S1", .TargetOffset: 0, .TargetSize: 26, .Flags: 0 },
457 { .Name: "fixup_MICROMIPS_PC19_S2", .TargetOffset: 0, .TargetSize: 19, .Flags: 0 },
458 { .Name: "fixup_MICROMIPS_PC18_S3", .TargetOffset: 0, .TargetSize: 18, .Flags: 0 },
459 { .Name: "fixup_MICROMIPS_PC21_S1", .TargetOffset: 0, .TargetSize: 21, .Flags: 0 },
460 { .Name: "fixup_MICROMIPS_CALL16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
461 { .Name: "fixup_MICROMIPS_GOT_DISP", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
462 { .Name: "fixup_MICROMIPS_GOT_PAGE", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
463 { .Name: "fixup_MICROMIPS_GOT_OFST", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
464 { .Name: "fixup_MICROMIPS_TLS_GD", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
465 { .Name: "fixup_MICROMIPS_TLS_LDM", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
466 { .Name: "fixup_MICROMIPS_TLS_DTPREL_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
467 { .Name: "fixup_MICROMIPS_TLS_DTPREL_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
468 { .Name: "fixup_MICROMIPS_GOTTPREL", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
469 { .Name: "fixup_MICROMIPS_TLS_TPREL_HI16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
470 { .Name: "fixup_MICROMIPS_TLS_TPREL_LO16", .TargetOffset: 0, .TargetSize: 16, .Flags: 0 },
471 { .Name: "fixup_Mips_SUB", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
472 { .Name: "fixup_MICROMIPS_SUB", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
473 { .Name: "fixup_Mips_JALR", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
474 { .Name: "fixup_MICROMIPS_JALR", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
475 // clang-format on
476 };
477 static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds,
478 "Not all MIPS little endian fixup kinds added!");
479
480 const static MCFixupKindInfo BigEndianInfos[] = {
481 // This table *must* be in same the order of fixup_* kinds in
482 // MipsFixupKinds.h.
483 //
484 // name offset bits flags
485 // clang-format off
486 { .Name: "fixup_Mips_16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
487 { .Name: "fixup_Mips_32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
488 { .Name: "fixup_Mips_REL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
489 { .Name: "fixup_Mips_GPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
490 { .Name: "fixup_Mips_DTPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
491 { .Name: "fixup_Mips_DTPREL64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
492 { .Name: "fixup_Mips_TPREL32", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
493 { .Name: "fixup_Mips_TPREL64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
494 { .Name: "fixup_Mips_26", .TargetOffset: 6, .TargetSize: 26, .Flags: 0 },
495 { .Name: "fixup_Mips_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
496 { .Name: "fixup_Mips_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
497 { .Name: "fixup_Mips_AnyImm16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
498 { .Name: "fixup_Mips_GPREL16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
499 { .Name: "fixup_Mips_LITERAL", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
500 { .Name: "fixup_Mips_GOT", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
501 { .Name: "fixup_Mips_PC16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
502 { .Name: "fixup_Mips_CALL16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
503 { .Name: "fixup_Mips_SHIFT5", .TargetOffset: 21, .TargetSize: 5, .Flags: 0 },
504 { .Name: "fixup_Mips_SHIFT6", .TargetOffset: 21, .TargetSize: 5, .Flags: 0 },
505 { .Name: "fixup_Mips_64", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
506 { .Name: "fixup_Mips_TLSGD", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
507 { .Name: "fixup_Mips_GOTTPREL", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
508 { .Name: "fixup_Mips_TPREL_HI", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
509 { .Name: "fixup_Mips_TPREL_LO", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
510 { .Name: "fixup_Mips_TLSLDM", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
511 { .Name: "fixup_Mips_DTPREL_HI", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
512 { .Name: "fixup_Mips_DTPREL_LO", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
513 { .Name: "fixup_Mips_Branch_PCRel",.TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
514 { .Name: "fixup_Mips_GPOFF_HI", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
515 { .Name: "fixup_MICROMIPS_GPOFF_HI", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
516 { .Name: "fixup_Mips_GPOFF_LO", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
517 { .Name: "fixup_MICROMIPS_GPOFF_LO", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
518 { .Name: "fixup_Mips_GOT_PAGE", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
519 { .Name: "fixup_Mips_GOT_OFST", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
520 { .Name: "fixup_Mips_GOT_DISP", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
521 { .Name: "fixup_Mips_HIGHER", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
522 { .Name: "fixup_MICROMIPS_HIGHER", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
523 { .Name: "fixup_Mips_HIGHEST", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
524 { .Name: "fixup_MICROMIPS_HIGHEST",.TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
525 { .Name: "fixup_Mips_GOT_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
526 { .Name: "fixup_Mips_GOT_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
527 { .Name: "fixup_Mips_CALL_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
528 { .Name: "fixup_Mips_CALL_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
529 { .Name: "fixup_Mips_PC18_S3", .TargetOffset: 14, .TargetSize: 18, .Flags: 0 },
530 { .Name: "fixup_MIPS_PC19_S2", .TargetOffset: 13, .TargetSize: 19, .Flags: 0 },
531 { .Name: "fixup_MIPS_PC21_S2", .TargetOffset: 11, .TargetSize: 21, .Flags: 0 },
532 { .Name: "fixup_MIPS_PC26_S2", .TargetOffset: 6, .TargetSize: 26, .Flags: 0 },
533 { .Name: "fixup_MIPS_PCHI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
534 { .Name: "fixup_MIPS_PCLO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
535 { .Name: "fixup_MICROMIPS_26_S1", .TargetOffset: 6, .TargetSize: 26, .Flags: 0 },
536 { .Name: "fixup_MICROMIPS_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
537 { .Name: "fixup_MICROMIPS_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
538 { .Name: "fixup_MICROMIPS_GOT16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
539 { .Name: "fixup_MICROMIPS_PC7_S1", .TargetOffset: 9, .TargetSize: 7, .Flags: 0 },
540 { .Name: "fixup_MICROMIPS_PC10_S1", .TargetOffset: 6, .TargetSize: 10, .Flags: 0 },
541 { .Name: "fixup_MICROMIPS_PC16_S1",.TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
542 { .Name: "fixup_MICROMIPS_PC26_S1", .TargetOffset: 6, .TargetSize: 26, .Flags: 0 },
543 { .Name: "fixup_MICROMIPS_PC19_S2",.TargetOffset: 13, .TargetSize: 19, .Flags: 0 },
544 { .Name: "fixup_MICROMIPS_PC18_S3",.TargetOffset: 14, .TargetSize: 18, .Flags: 0 },
545 { .Name: "fixup_MICROMIPS_PC21_S1",.TargetOffset: 11, .TargetSize: 21, .Flags: 0 },
546 { .Name: "fixup_MICROMIPS_CALL16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
547 { .Name: "fixup_MICROMIPS_GOT_DISP", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
548 { .Name: "fixup_MICROMIPS_GOT_PAGE", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
549 { .Name: "fixup_MICROMIPS_GOT_OFST", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
550 { .Name: "fixup_MICROMIPS_TLS_GD", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
551 { .Name: "fixup_MICROMIPS_TLS_LDM", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
552 { .Name: "fixup_MICROMIPS_TLS_DTPREL_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
553 { .Name: "fixup_MICROMIPS_TLS_DTPREL_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
554 { .Name: "fixup_MICROMIPS_GOTTPREL", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
555 { .Name: "fixup_MICROMIPS_TLS_TPREL_HI16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
556 { .Name: "fixup_MICROMIPS_TLS_TPREL_LO16", .TargetOffset: 16, .TargetSize: 16, .Flags: 0 },
557 { .Name: "fixup_Mips_SUB", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
558 { .Name: "fixup_MICROMIPS_SUB", .TargetOffset: 0, .TargetSize: 64, .Flags: 0 },
559 { .Name: "fixup_Mips_JALR", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
560 { .Name: "fixup_MICROMIPS_JALR", .TargetOffset: 0, .TargetSize: 32, .Flags: 0 },
561 // clang-format on
562 };
563 static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds,
564 "Not all MIPS big endian fixup kinds added!");
565
566 if (mc::isRelocation(FixupKind: Kind))
567 return {};
568 if (Kind < FirstTargetFixupKind)
569 return MCAsmBackend::getFixupKindInfo(Kind);
570
571 assert(unsigned(Kind - FirstTargetFixupKind) < Mips::NumTargetFixupKinds &&
572 "Invalid kind!");
573
574 if (Endian == llvm::endianness::little)
575 return LittleEndianInfos[Kind - FirstTargetFixupKind];
576 return BigEndianInfos[Kind - FirstTargetFixupKind];
577}
578
579/// WriteNopData - Write an (optimal) nop sequence of Count bytes
580/// to the given output. If the target cannot generate such a sequence,
581/// it should return an error.
582///
583/// \return - True on success.
584bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
585 const MCSubtargetInfo *STI) const {
586 // Check for a less than instruction size number of bytes
587 // FIXME: 16 bit instructions are not handled yet here.
588 // We shouldn't be using a hard coded number for instruction size.
589
590 // If the count is not 4-byte aligned, we must be writing data into the text
591 // section (otherwise we have unaligned instructions, and thus have far
592 // bigger problems), so just write zeros instead.
593 OS.write_zeros(NumZeros: Count);
594 return true;
595}
596
597namespace {
598
599class WindowsMipsAsmBackend : public MipsAsmBackend {
600public:
601 WindowsMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI,
602 const MCSubtargetInfo &STI)
603 : MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), false) {}
604
605 std::unique_ptr<MCObjectTargetWriter>
606 createObjectTargetWriter() const override {
607 return createMipsWinCOFFObjectWriter();
608 }
609};
610
611} // end anonymous namespace
612
613MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
614 const MCSubtargetInfo &STI,
615 const MCRegisterInfo &MRI,
616 const MCTargetOptions &Options) {
617 const Triple &TheTriple = STI.getTargetTriple();
618 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
619 return new WindowsMipsAsmBackend(T, MRI, STI);
620
621 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT: STI.getTargetTriple(),
622 ABIName: Options.getABIName());
623 return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
624 ABI.IsN32());
625}
626