1//===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Subclass of MipsTargetLowering specialized for mips32/64.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
15
16#include "MipsISelLowering.h"
17#include "llvm/CodeGen/SelectionDAGNodes.h"
18#include "llvm/CodeGenTypes/MachineValueType.h"
19
20namespace llvm {
21
22class MachineBasicBlock;
23class MachineInstr;
24class MipsSubtarget;
25class MipsTargetMachine;
26class SelectionDAG;
27class MCRegisterClass;
28using TargetRegisterClass = MCRegisterClass;
29
30 class MipsSETargetLowering : public MipsTargetLowering {
31 public:
32 explicit MipsSETargetLowering(const MipsTargetMachine &TM,
33 const MipsSubtarget &STI);
34
35 /// Enable MSA support for the given integer type and Register
36 /// class.
37 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
38
39 /// Enable MSA support for the given floating-point type and
40 /// Register class.
41 void addMSAFloatType(MVT::SimpleValueType Ty,
42 const TargetRegisterClass *RC);
43
44 bool allowsMisalignedMemoryAccesses(
45 EVT VT, unsigned AS = 0, Align Alignment = Align(1),
46 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
47 unsigned *Fast = nullptr) const override;
48
49 TargetLoweringBase::LegalizeTypeAction
50 getPreferredVectorAction(MVT VT) const override;
51
52 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
53
54 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
55
56 MachineBasicBlock *
57 EmitInstrWithCustomInserter(MachineInstr &MI,
58 MachineBasicBlock *MBB) const override;
59
60 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
61 return false;
62 }
63
64 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
65
66 private:
67 bool isEligibleForTailCallOptimization(
68 const CCState &CCInfo, unsigned NextStackOffset,
69 const MipsFunctionInfo &FI) const override;
70
71 void getOpndList(SmallVectorImpl<SDValue> &Ops,
72 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
73 bool IsPICCall, bool GlobalOrExternal, bool LocalLinkage,
74 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
75 SDValue Chain) const override;
76
77 SDValue lowerR5900FPOp(SDValue Op, SelectionDAG &DAG,
78 RTLIB::Libcall LC) const;
79 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
80 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
81 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
82
83 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
84 SelectionDAG &DAG) const;
85
86 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
87 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
88 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
89 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
90 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
91 /// Lower VECTOR_SHUFFLE into one of a number of instructions
92 /// depending on the indices in the shuffle.
93 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
94 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
95 SDValue lowerFP16_TO_FP(SDValue Op, SelectionDAG &DAG) const;
96 SDValue lowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
97
98 MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
99 MachineBasicBlock *BB) const;
100 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
101 MachineBasicBlock *BB,
102 unsigned BranchOp) const;
103 /// Emit the COPY_FW pseudo instruction
104 MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
105 MachineBasicBlock *BB) const;
106 /// Emit the COPY_FD pseudo instruction
107 MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
108 MachineBasicBlock *BB) const;
109 /// Emit the INSERT_FW pseudo instruction
110 MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
111 MachineBasicBlock *BB) const;
112 /// Emit the INSERT_FD pseudo instruction
113 MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
114 MachineBasicBlock *BB) const;
115 /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
116 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
117 MachineBasicBlock *BB,
118 unsigned EltSizeInBytes,
119 bool IsFP) const;
120 /// Emit the FILL_FW pseudo instruction
121 MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
122 MachineBasicBlock *BB) const;
123 /// Emit the FILL_FD pseudo instruction
124 MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
125 MachineBasicBlock *BB) const;
126 /// Emit the FEXP2_W_1 pseudo instructions.
127 MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
128 MachineBasicBlock *BB) const;
129 /// Emit the FEXP2_D_1 pseudo instructions.
130 MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
131 MachineBasicBlock *BB) const;
132 };
133
134} // end namespace llvm
135
136#endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
137