1//===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Subclass of MipsTargetLowering specialized for mips32/64.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
15
16#include "MipsISelLowering.h"
17#include "llvm/CodeGen/SelectionDAGNodes.h"
18#include "llvm/CodeGenTypes/MachineValueType.h"
19
20namespace llvm {
21
22class MachineBasicBlock;
23class MachineInstr;
24class MipsSubtarget;
25class MipsTargetMachine;
26class SelectionDAG;
27class TargetRegisterClass;
28
29 class MipsSETargetLowering : public MipsTargetLowering {
30 public:
31 explicit MipsSETargetLowering(const MipsTargetMachine &TM,
32 const MipsSubtarget &STI);
33
34 /// Enable MSA support for the given integer type and Register
35 /// class.
36 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
37
38 /// Enable MSA support for the given floating-point type and
39 /// Register class.
40 void addMSAFloatType(MVT::SimpleValueType Ty,
41 const TargetRegisterClass *RC);
42
43 bool allowsMisalignedMemoryAccesses(
44 EVT VT, unsigned AS = 0, Align Alignment = Align(1),
45 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
46 unsigned *Fast = nullptr) const override;
47
48 TargetLoweringBase::LegalizeTypeAction
49 getPreferredVectorAction(MVT VT) const override;
50
51 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
52
53 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
54
55 MachineBasicBlock *
56 EmitInstrWithCustomInserter(MachineInstr &MI,
57 MachineBasicBlock *MBB) const override;
58
59 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
60 return false;
61 }
62
63 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
64
65 private:
66 bool isEligibleForTailCallOptimization(
67 const CCState &CCInfo, unsigned NextStackOffset,
68 const MipsFunctionInfo &FI) const override;
69
70 void
71 getOpndList(SmallVectorImpl<SDValue> &Ops,
72 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
73 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
74 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
75 SDValue Chain) const override;
76
77 SDValue lowerR5900FPOp(SDValue Op, SelectionDAG &DAG,
78 RTLIB::Libcall LC) const;
79 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
80 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
81 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
82
83 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
84 SelectionDAG &DAG) const;
85
86 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
87 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
88 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
89 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
90 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
91 /// Lower VECTOR_SHUFFLE into one of a number of instructions
92 /// depending on the indices in the shuffle.
93 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
94 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
95
96 MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
97 MachineBasicBlock *BB) const;
98 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
99 MachineBasicBlock *BB,
100 unsigned BranchOp) const;
101 /// Emit the COPY_FW pseudo instruction
102 MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
103 MachineBasicBlock *BB) const;
104 /// Emit the COPY_FD pseudo instruction
105 MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
106 MachineBasicBlock *BB) const;
107 /// Emit the INSERT_FW pseudo instruction
108 MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
109 MachineBasicBlock *BB) const;
110 /// Emit the INSERT_FD pseudo instruction
111 MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
112 MachineBasicBlock *BB) const;
113 /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
114 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
115 MachineBasicBlock *BB,
116 unsigned EltSizeInBytes,
117 bool IsFP) const;
118 /// Emit the FILL_FW pseudo instruction
119 MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
120 MachineBasicBlock *BB) const;
121 /// Emit the FILL_FD pseudo instruction
122 MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
123 MachineBasicBlock *BB) const;
124 /// Emit the FEXP2_W_1 pseudo instructions.
125 MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
126 MachineBasicBlock *BB) const;
127 /// Emit the FEXP2_D_1 pseudo instructions.
128 MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
129 MachineBasicBlock *BB) const;
130 /// Emit the FILL_FW pseudo instruction
131 MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
132 MachineBasicBlock *BB) const;
133 /// Emit the FILL_FD pseudo instruction
134 MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
135 MachineBasicBlock *BB) const;
136 /// Emit the FEXP2_W_1 pseudo instructions.
137 MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
138 MachineBasicBlock *BB,
139 bool IsFGR64) const;
140 /// Emit the FEXP2_D_1 pseudo instructions.
141 MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
142 MachineBasicBlock *BBi,
143 bool IsFGR64) const;
144 };
145
146} // end namespace llvm
147
148#endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
149