1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MipsFrameLowering.h"
18#include "MipsISelLowering.h"
19#include "MipsInstrInfo.h"
20#include "llvm/CodeGen/GlobalISel/CallLowering.h"
21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23#include "llvm/CodeGen/RegisterBankInfo.h"
24#include "llvm/CodeGen/TargetSubtargetInfo.h"
25#include "llvm/IR/DataLayout.h"
26#include "llvm/Support/ErrorHandling.h"
27#include <bitset>
28
29#define GET_SUBTARGETINFO_HEADER
30#include "MipsGenSubtargetInfo.inc"
31
32namespace llvm {
33class StringRef;
34
35enum CompactBranchPolicy {
36 CB_Never, ///< The policy 'never' may in some circumstances or for some
37 ///< ISAs not be absolutely adhered to.
38 CB_Optimal, ///< Optimal is the default and will produce compact branches
39 ///< when appropriate.
40 CB_Always ///< 'always' may in some circumstances may not be
41 ///< absolutely adhered to, there may not be a corresponding
42 ///< compact form of a branch.
43};
44
45class MipsTargetMachine;
46
47class MipsSubtarget : public MipsGenSubtargetInfo {
48 virtual void anchor();
49
50 enum MipsArchEnum {
51 MipsDefault,
52 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
53 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
54 };
55
56 enum class CPU { Others, P5600, I6400, I6500 };
57
58 // Used to avoid printing dsp warnings multiple times.
59 static bool DspWarningPrinted;
60
61 // Used to avoid printing msa warnings multiple times.
62 static bool MSAWarningPrinted;
63
64 // Used to avoid printing crc warnings multiple times.
65 static bool CRCWarningPrinted;
66
67 // Used to avoid printing ginv warnings multiple times.
68 static bool GINVWarningPrinted;
69
70 // Used to avoid printing Mips1 warnings multiple times.
71 static bool MIPS1WarningPrinted;
72
73 // Used to avoid printing virt warnings multiple times.
74 static bool VirtWarningPrinted;
75
76 // Mips architecture version
77 MipsArchEnum MipsArchVersion;
78
79 // Processor implementation
80 CPU ProcImpl = CPU::Others;
81
82 // IsLittle - The target is Little Endian
83 bool IsLittle;
84
85 // IsSoftFloat - The target does not support any floating point instructions.
86 bool IsSoftFloat;
87
88 // IsSingleFloat - The target only supports single precision float
89 // point operations. This enable the target to use all 32 32-bit
90 // floating point registers instead of only using even ones.
91 bool IsSingleFloat;
92
93 // IsFPXX - MIPS O32 modeless ABI.
94 bool IsFPXX;
95
96 // NoABICalls - Disable SVR4-style position-independent code.
97 bool NoABICalls;
98
99 // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
100 bool Abs2008;
101
102 // IsFP64bit - The target processor has 64-bit floating point registers.
103 bool IsFP64bit;
104
105 /// Are odd single-precision registers permitted?
106 /// This corresponds to -modd-spreg and -mno-odd-spreg
107 bool UseOddSPReg;
108
109 // IsNan2008 - IEEE 754-2008 NaN encoding.
110 bool IsNaN2008bit;
111
112 // IsGP64bit - General-purpose registers are 64 bits wide
113 bool IsGP64bit;
114
115 // MIPS GPRs explicitly reserved through -ffixed-REG.
116 std::bitset<32> UserReservedGPR;
117
118 // IsPTR64bit - Pointers are 64 bit wide
119 bool IsPTR64bit;
120
121 // HasVFPU - Processor has a vector floating point unit.
122 bool HasVFPU;
123
124 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
125 bool HasCnMips;
126
127 // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
128 bool HasCnMipsP;
129
130 // IsR5900 - CPU is R5900 (PlayStation 2 Emotion Engine).
131 bool IsR5900;
132
133 // FixR5900 - Enable R5900 short loop erratum fix.
134 bool FixR5900;
135
136 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
137 bool IsLinux;
138
139 // UseSmallSection - Small section is used.
140 bool UseSmallSection;
141
142 /// Features related to the presence of specific instructions.
143
144 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
145 bool HasMips3_32;
146
147 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
148 bool HasMips3_32r2;
149
150 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
151 bool HasMips4_32;
152
153 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
154 bool HasMips4_32r2;
155
156 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
157 bool HasMips5_32r2;
158
159 // InMips16 -- can process Mips16 instructions
160 bool InMips16Mode;
161
162 // Mips16 hard float
163 bool InMips16HardFloat;
164
165 // InMicroMips -- can process MicroMips instructions
166 bool InMicroMipsMode;
167
168 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
169 bool HasDSP, HasDSPR2, HasDSPR3;
170
171 // Has3D -- Supports Mips3D ASE.
172 bool Has3D;
173
174 // Allow mixed Mips16 and Mips32 in one source file
175 bool AllowMixed16_32;
176
177 // Optimize for space by compiling all functions as Mips 16 unless
178 // it needs floating point. Functions needing floating point are
179 // compiled as Mips32
180 bool Os16;
181
182 // HasMSA -- supports MSA ASE.
183 bool HasMSA;
184
185 // UseTCCInDIV -- Enables the use of trapping in the assembler.
186 bool UseTCCInDIV;
187
188 // Sym32 -- On Mips64 symbols are 32 bits.
189 bool HasSym32;
190
191 // HasEVA -- supports EVA ASE.
192 bool HasEVA;
193
194 // nomadd4 - disables generation of 4-operand madd.s, madd.d and
195 // related instructions.
196 bool DisableMadd4;
197
198 // HasMT -- support MT ASE.
199 bool HasMT;
200
201 // HasCRC -- supports R6 CRC ASE
202 bool HasCRC;
203
204 // HasVirt -- supports Virtualization ASE
205 bool HasVirt;
206
207 // HasGINV -- supports R6 Global INValidate ASE
208 bool HasGINV;
209
210 // Use hazard variants of the jump register instructions for indirect
211 // function calls and jump tables.
212 bool UseIndirectJumpsHazard;
213
214 // Disable use of the `jal` instruction.
215 bool UseLongCalls = false;
216
217 // Assume 32-bit GOT.
218 bool UseXGOT = false;
219
220 // Disable unaligned load store for r6.
221 bool StrictAlign;
222
223 // Use compact branch instructions for R6.
224 bool UseCompactBranches = true;
225
226 /// The minimum alignment known to hold of the stack frame on
227 /// entry to the function and which must be maintained by every function.
228 Align stackAlignment;
229
230 /// The overridden stack alignment.
231 MaybeAlign StackAlignOverride;
232
233 // We can override the determination of whether we are in mips16 mode
234 // as from the command line
235 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
236
237 const MipsTargetMachine &TM;
238
239 Triple TargetTriple;
240
241 std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
242 std::unique_ptr<const MipsInstrInfo> InstrInfo;
243 std::unique_ptr<const MipsFrameLowering> FrameLowering;
244 std::unique_ptr<const MipsTargetLowering> TLInfo;
245
246public:
247 bool isPositionIndependent() const;
248 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
249 bool enablePostRAScheduler() const override;
250 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
251 CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override;
252
253 bool isABI_N64() const;
254 bool isABI_N32() const;
255 bool isABI_O32() const;
256 const MipsABIInfo &getABI() const;
257 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
258
259 bool isGPRReservedByUser(unsigned GPR) const {
260 assert(GPR < UserReservedGPR.size() && "GPR number out of range");
261 return UserReservedGPR[GPR];
262 }
263
264 /// This constructor initializes the data members to match that
265 /// of the specified triple.
266 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
267 const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
268
269 ~MipsSubtarget() override;
270
271 /// ParseSubtargetFeatures - Parses features string setting specified
272 /// subtarget options. Definition of function is auto generated by tblgen.
273 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
274
275 static const RTLIB::LibcallImpl HardFloatLibCalls[34];
276
277 bool hasMips1() const { return MipsArchVersion >= Mips1; }
278 bool hasMips2() const { return MipsArchVersion >= Mips2; }
279 bool hasMips3() const { return MipsArchVersion >= Mips3; }
280 bool hasMips4() const { return MipsArchVersion >= Mips4; }
281 bool hasMips5() const { return MipsArchVersion >= Mips5; }
282 bool hasMips4_32() const { return HasMips4_32; }
283 bool hasMips4_32r2() const { return HasMips4_32r2; }
284 bool hasMips32() const {
285 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
286 hasMips64();
287 }
288 bool hasMips32r2() const {
289 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
290 hasMips64r2();
291 }
292 bool hasMips32r3() const {
293 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
294 hasMips64r2();
295 }
296 bool hasMips32r5() const {
297 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
298 hasMips64r5();
299 }
300 bool hasMips32r6() const {
301 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
302 hasMips64r6();
303 }
304 bool hasMips64() const { return MipsArchVersion >= Mips64; }
305 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
306 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
307 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
308 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
309
310 bool hasCnMips() const { return HasCnMips; }
311 bool hasCnMipsP() const { return HasCnMipsP; }
312 bool isR5900() const { return IsR5900; }
313 bool fixR5900() const { return FixR5900; }
314
315 bool isLittle() const { return IsLittle; }
316 bool isABICalls() const { return !NoABICalls; }
317 bool isFPXX() const { return IsFPXX; }
318 bool isFP64bit() const { return IsFP64bit; }
319 bool useOddSPReg() const { return UseOddSPReg; }
320 bool noOddSPReg() const { return !UseOddSPReg; }
321 bool isNaN2008() const { return IsNaN2008bit; }
322 bool inAbs2008Mode() const { return Abs2008; }
323 bool isGP64bit() const { return IsGP64bit; }
324 bool isGP32bit() const { return !IsGP64bit; }
325 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
326 bool isPTR64bit() const { return IsPTR64bit; }
327 bool isPTR32bit() const { return !IsPTR64bit; }
328 bool hasSym32() const {
329 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
330 }
331 bool isSingleFloat() const { return IsSingleFloat; }
332 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
333 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
334 bool hasVFPU() const { return HasVFPU; }
335 bool inMips16Mode() const { return InMips16Mode; }
336 bool inMips16ModeDefault() const {
337 return InMips16Mode;
338 }
339 // Hard float for mips16 means essentially to compile as soft float
340 // but to use a runtime library for soft float that is written with
341 // native mips32 floating point instructions (those runtime routines
342 // run in mips32 hard float mode).
343 bool inMips16HardFloat() const {
344 return inMips16Mode() && InMips16HardFloat;
345 }
346 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
347 bool inMicroMips32r6Mode() const {
348 return inMicroMipsMode() && hasMips32r6();
349 }
350 bool hasDSP() const { return HasDSP; }
351 bool hasDSPR2() const { return HasDSPR2; }
352 bool hasDSPR3() const { return HasDSPR3; }
353 bool has3D() const { return Has3D; }
354 bool hasMSA() const { return HasMSA; }
355 bool disableMadd4() const { return DisableMadd4; }
356 bool hasEVA() const { return HasEVA; }
357 bool hasMT() const { return HasMT; }
358 bool hasCRC() const { return HasCRC; }
359 bool hasVirt() const { return HasVirt; }
360 bool hasGINV() const { return HasGINV; }
361 bool useIndirectJumpsHazard() const {
362 return UseIndirectJumpsHazard && hasMips32r2();
363 }
364 bool useSmallSection() const { return UseSmallSection; }
365
366 bool useCompactBranches() const {
367 return UseCompactBranches && hasMips32r6();
368 }
369
370 bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
371
372 bool useSoftFloat() const { return IsSoftFloat; }
373
374 bool useLongCalls() const { return UseLongCalls; }
375
376 bool useXGOT() const { return UseXGOT; }
377
378 bool enableLongBranchPass() const {
379 return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32();
380 }
381
382 /// Features related to the presence of specific instructions.
383 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
384 bool hasMTHC1() const { return hasMips32r2(); }
385
386 bool allowMixed16_32() const { return inMips16ModeDefault() |
387 AllowMixed16_32; }
388
389 bool os16() const { return Os16; }
390
391 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
392
393 bool isXRaySupported() const override { return true; }
394
395 // for now constant islands are on for the whole compilation unit but we only
396 // really use them if in addition we are in mips16 mode
397 static bool useConstantIslands();
398
399 Align getStackAlignment() const { return stackAlignment; }
400
401 // Grab relocation model
402 Reloc::Model getRelocationModel() const;
403
404 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
405 const TargetMachine &TM);
406
407 /// Does the system support unaligned memory access.
408 ///
409 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
410 /// specify which component of the system provides it. Hardware, software, and
411 /// hybrid implementations are all valid.
412 bool systemSupportsUnalignedAccess() const {
413 return hasMips32r6() && !StrictAlign;
414 }
415
416 // Set helper classes
417 void setHelperClassesMips16();
418 void setHelperClassesMipsSE();
419
420 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
421
422 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
423 const TargetFrameLowering *getFrameLowering() const override {
424 return FrameLowering.get();
425 }
426 const MipsRegisterInfo *getRegisterInfo() const override {
427 return &InstrInfo->getRegisterInfo();
428 }
429 const MipsTargetLowering *getTargetLowering() const override {
430 return TLInfo.get();
431 }
432 void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override;
433
434protected:
435 // GlobalISel related APIs.
436 std::unique_ptr<CallLowering> CallLoweringInfo;
437 std::unique_ptr<LegalizerInfo> Legalizer;
438 std::unique_ptr<RegisterBankInfo> RegBankInfo;
439 std::unique_ptr<InstructionSelector> InstSelector;
440
441public:
442 const CallLowering *getCallLowering() const override;
443 const LegalizerInfo *getLegalizerInfo() const override;
444 const RegisterBankInfo *getRegBankInfo() const override;
445 InstructionSelector *getInstructionSelector() const override;
446};
447} // End llvm namespace
448
449#endif
450