1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MipsFrameLowering.h"
18#include "MipsISelLowering.h"
19#include "MipsInstrInfo.h"
20#include "llvm/CodeGen/GlobalISel/CallLowering.h"
21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23#include "llvm/CodeGen/RegisterBankInfo.h"
24#include "llvm/CodeGen/TargetSubtargetInfo.h"
25#include "llvm/IR/DataLayout.h"
26#include "llvm/Support/ErrorHandling.h"
27#include <bitset>
28
29#define GET_SUBTARGETINFO_HEADER
30#include "MipsGenSubtargetInfo.inc"
31
32namespace llvm {
33class StringRef;
34
35enum CompactBranchPolicy {
36 CB_Never, ///< The policy 'never' may in some circumstances or for some
37 ///< ISAs not be absolutely adhered to.
38 CB_Optimal, ///< Optimal is the default and will produce compact branches
39 ///< when appropriate.
40 CB_Always ///< 'always' may in some circumstances may not be
41 ///< absolutely adhered to, there may not be a corresponding
42 ///< compact form of a branch.
43};
44
45class MipsTargetMachine;
46
47class MipsSubtarget : public MipsGenSubtargetInfo {
48 virtual void anchor();
49
50 enum MipsArchEnum {
51 MipsDefault,
52 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
53 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
54 };
55
56 enum class CPU { Others, P5600, I6400, I6500 };
57
58 // Used to avoid printing dsp warnings multiple times.
59 static bool DspWarningPrinted;
60
61 // Used to avoid printing msa warnings multiple times.
62 static bool MSAWarningPrinted;
63
64 // Used to avoid printing crc warnings multiple times.
65 static bool CRCWarningPrinted;
66
67 // Used to avoid printing ginv warnings multiple times.
68 static bool GINVWarningPrinted;
69
70 // Used to avoid printing Mips1 warnings multiple times.
71 static bool MIPS1WarningPrinted;
72
73 // Used to avoid printing virt warnings multiple times.
74 static bool VirtWarningPrinted;
75
76 // Mips architecture version
77 MipsArchEnum MipsArchVersion;
78
79 // Processor implementation
80 CPU ProcImpl = CPU::Others;
81
82 // IsLittle - The target is Little Endian
83 bool IsLittle;
84
85 // IsSoftFloat - The target does not support any floating point instructions.
86 bool IsSoftFloat;
87
88 // IsSingleFloat - The target only supports single precision float
89 // point operations. This enable the target to use all 32 32-bit
90 // floating point registers instead of only using even ones.
91 bool IsSingleFloat;
92
93 // IsFPXX - MIPS O32 modeless ABI.
94 bool IsFPXX;
95
96 // NoABICalls - Disable SVR4-style position-independent code.
97 bool NoABICalls;
98
99 // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
100 bool Abs2008;
101
102 // IsFP64bit - The target processor has 64-bit floating point registers.
103 bool IsFP64bit;
104
105 /// Are odd single-precision registers permitted?
106 /// This corresponds to -modd-spreg and -mno-odd-spreg
107 bool UseOddSPReg;
108
109 // IsNan2008 - IEEE 754-2008 NaN encoding.
110 bool IsNaN2008bit;
111
112 // IsGP64bit - General-purpose registers are 64 bits wide
113 bool IsGP64bit;
114
115 // MIPS GPRs explicitly reserved through -ffixed-REG.
116 std::bitset<32> UserReservedGPR;
117
118 // IsPTR64bit - Pointers are 64 bit wide
119 bool IsPTR64bit;
120
121 // HasVFPU - Processor has a vector floating point unit.
122 bool HasVFPU;
123
124 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
125 bool HasCnMips;
126
127 // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
128 bool HasCnMipsP;
129
130 // IsR5900 - CPU is R5900 (PlayStation 2 Emotion Engine).
131 bool IsR5900;
132
133 // FixR5900 - Enable R5900 short loop erratum fix.
134 bool FixR5900;
135
136 // UseSmallSection - Small section is used.
137 bool UseSmallSection;
138
139 /// Features related to the presence of specific instructions.
140
141 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
142 bool HasMips3_32;
143
144 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
145 bool HasMips3_32r2;
146
147 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
148 bool HasMips4_32;
149
150 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
151 bool HasMips4_32r2;
152
153 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
154 bool HasMips5_32r2;
155
156 // InMips16 -- can process Mips16 instructions
157 bool InMips16Mode;
158
159 // Mips16 hard float
160 bool InMips16HardFloat;
161
162 // InMicroMips -- can process MicroMips instructions
163 bool InMicroMipsMode;
164
165 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
166 bool HasDSP, HasDSPR2, HasDSPR3;
167
168 // Has3D -- Supports Mips3D ASE.
169 bool Has3D;
170
171 // HasMSA -- supports MSA ASE.
172 bool HasMSA;
173
174 // UseTCCInDIV -- Enables the use of trapping in the assembler.
175 bool UseTCCInDIV;
176
177 // Sym32 -- On Mips64 symbols are 32 bits.
178 bool HasSym32;
179
180 // HasEVA -- supports EVA ASE.
181 bool HasEVA;
182
183 // nomadd4 - disables generation of 4-operand madd.s, madd.d and
184 // related instructions.
185 bool DisableMadd4;
186
187 // HasMT -- support MT ASE.
188 bool HasMT;
189
190 // HasCRC -- supports R6 CRC ASE
191 bool HasCRC;
192
193 // HasVirt -- supports Virtualization ASE
194 bool HasVirt;
195
196 // HasGINV -- supports R6 Global INValidate ASE
197 bool HasGINV;
198
199 // Use hazard variants of the jump register instructions for indirect
200 // function calls and jump tables.
201 bool UseIndirectJumpsHazard;
202
203 // Disable use of the `jal` instruction.
204 bool UseLongCalls = false;
205
206 // Assume 32-bit GOT.
207 bool UseXGOT = false;
208
209 // Disable unaligned load store for r6.
210 bool StrictAlign;
211
212 // Use compact branch instructions for R6.
213 bool UseCompactBranches = true;
214
215 /// The minimum alignment known to hold of the stack frame on
216 /// entry to the function and which must be maintained by every function.
217 Align stackAlignment;
218
219 /// The overridden stack alignment.
220 MaybeAlign StackAlignOverride;
221
222 const MipsTargetMachine &TM;
223
224 MipsABIInfo ABI;
225
226 std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
227 std::unique_ptr<const MipsInstrInfo> InstrInfo;
228 std::unique_ptr<const MipsFrameLowering> FrameLowering;
229 std::unique_ptr<const MipsTargetLowering> TLInfo;
230
231public:
232 bool isPositionIndependent() const;
233 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
234 bool enablePostRAScheduler() const override;
235 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
236 CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override;
237
238 bool isABI_N64() const;
239 bool isABI_N32() const;
240 bool isABI_O32() const;
241 const MipsABIInfo &getABI() const { return ABI; }
242 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
243
244 bool isGPRReservedByUser(unsigned GPR) const {
245 assert(GPR < UserReservedGPR.size() && "GPR number out of range");
246 return UserReservedGPR[GPR];
247 }
248
249 /// This constructor initializes the data members to match that
250 /// of the specified triple.
251 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
252 StringRef ABIName, bool little, const MipsTargetMachine &TM,
253 MaybeAlign StackAlignOverride);
254
255 ~MipsSubtarget() override;
256
257 /// ParseSubtargetFeatures - Parses features string setting specified
258 /// subtarget options. Definition of function is auto generated by tblgen.
259 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
260
261 static const RTLIB::LibcallImpl HardFloatLibCalls[34];
262
263 bool hasMips1() const { return MipsArchVersion >= Mips1; }
264 bool hasMips2() const { return MipsArchVersion >= Mips2; }
265 bool hasMips3() const { return MipsArchVersion >= Mips3; }
266 bool hasMips4() const { return MipsArchVersion >= Mips4; }
267 bool hasMips5() const { return MipsArchVersion >= Mips5; }
268 bool hasMips4_32() const { return HasMips4_32; }
269 bool hasMips4_32r2() const { return HasMips4_32r2; }
270 bool hasMips32() const {
271 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
272 hasMips64();
273 }
274 bool hasMips32r2() const {
275 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
276 hasMips64r2();
277 }
278 bool hasMips32r3() const {
279 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
280 hasMips64r2();
281 }
282 bool hasMips32r5() const {
283 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
284 hasMips64r5();
285 }
286 bool hasMips32r6() const {
287 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
288 hasMips64r6();
289 }
290 bool hasMips64() const { return MipsArchVersion >= Mips64; }
291 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
292 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
293 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
294 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
295
296 bool hasCnMips() const { return HasCnMips; }
297 bool hasCnMipsP() const { return HasCnMipsP; }
298 bool isR5900() const { return IsR5900; }
299 bool fixR5900() const { return FixR5900; }
300
301 bool isLittle() const { return IsLittle; }
302 bool isABICalls() const { return !NoABICalls; }
303 bool isFPXX() const { return IsFPXX; }
304 bool isFP64bit() const { return IsFP64bit; }
305 bool useOddSPReg() const { return UseOddSPReg; }
306 bool noOddSPReg() const { return !UseOddSPReg; }
307 bool isNaN2008() const { return IsNaN2008bit; }
308 bool inAbs2008Mode() const { return Abs2008; }
309 bool isGP64bit() const { return IsGP64bit; }
310 bool isGP32bit() const { return !IsGP64bit; }
311 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
312 bool isPTR64bit() const { return IsPTR64bit; }
313 bool isPTR32bit() const { return !IsPTR64bit; }
314 bool hasSym32() const {
315 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
316 }
317 bool isSingleFloat() const { return IsSingleFloat; }
318 bool isTargetCOFF() const { return getTargetTriple().isOSBinFormatCOFF(); }
319 bool isTargetELF() const { return getTargetTriple().isOSBinFormatELF(); }
320 bool hasVFPU() const { return HasVFPU; }
321 bool inMips16Mode() const { return InMips16Mode; }
322 // Hard float for mips16 means essentially to compile as soft float
323 // but to use a runtime library for soft float that is written with
324 // native mips32 floating point instructions (those runtime routines
325 // run in mips32 hard float mode).
326 bool inMips16HardFloat() const {
327 return inMips16Mode() && InMips16HardFloat;
328 }
329 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
330 bool inMicroMips32r6Mode() const {
331 return inMicroMipsMode() && hasMips32r6();
332 }
333 bool hasDSP() const { return HasDSP; }
334 bool hasDSPR2() const { return HasDSPR2; }
335 bool hasDSPR3() const { return HasDSPR3; }
336 bool has3D() const { return Has3D; }
337 bool hasMSA() const { return HasMSA; }
338 bool disableMadd4() const { return DisableMadd4; }
339 bool hasEVA() const { return HasEVA; }
340 bool hasMT() const { return HasMT; }
341 bool hasCRC() const { return HasCRC; }
342 bool hasVirt() const { return HasVirt; }
343 bool hasGINV() const { return HasGINV; }
344 bool useIndirectJumpsHazard() const {
345 return UseIndirectJumpsHazard && hasMips32r2();
346 }
347 bool useSmallSection() const { return UseSmallSection; }
348
349 bool useCompactBranches() const {
350 return UseCompactBranches && hasMips32r6();
351 }
352
353 bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
354
355 bool useSoftFloat() const { return IsSoftFloat; }
356
357 bool useLongCalls() const { return UseLongCalls; }
358
359 bool useXGOT() const { return UseXGOT; }
360
361 /// Features related to the presence of specific instructions.
362 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
363 bool hasMTHC1() const { return hasMips32r2(); }
364
365 bool isTargetWindows() const { return getTargetTriple().isOSWindows(); }
366
367 bool isXRaySupported() const override { return true; }
368
369 // for now constant islands are on for the whole compilation unit but we only
370 // really use them if in addition we are in mips16 mode
371 static bool useConstantIslands();
372
373 Align getStackAlignment() const { return stackAlignment; }
374
375 // Grab relocation model
376 Reloc::Model getRelocationModel() const;
377
378 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
379 const TargetMachine &TM);
380
381 /// Does the system support unaligned memory access.
382 ///
383 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
384 /// specify which component of the system provides it. Hardware, software, and
385 /// hybrid implementations are all valid.
386 bool systemSupportsUnalignedAccess() const {
387 return hasMips32r6() && !StrictAlign;
388 }
389
390 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
391
392 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
393 const TargetFrameLowering *getFrameLowering() const override {
394 return FrameLowering.get();
395 }
396 const MipsRegisterInfo *getRegisterInfo() const override {
397 return &InstrInfo->getRegisterInfo();
398 }
399 const MipsTargetLowering *getTargetLowering() const override {
400 return TLInfo.get();
401 }
402 void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override;
403
404protected:
405 // GlobalISel related APIs.
406 std::unique_ptr<CallLowering> CallLoweringInfo;
407 std::unique_ptr<LegalizerInfo> Legalizer;
408 std::unique_ptr<RegisterBankInfo> RegBankInfo;
409 std::unique_ptr<InstructionSelector> InstSelector;
410
411public:
412 const CallLowering *getCallLowering() const override;
413 const LegalizerInfo *getLegalizerInfo() const override;
414 const RegisterBankInfo *getRegBankInfo() const override;
415 InstructionSelector *getInstructionSelector() const override;
416};
417} // End llvm namespace
418
419#endif
420