1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MCTargetDesc/MipsMCOptions.h"
18#include "MipsFrameLowering.h"
19#include "MipsISelLowering.h"
20#include "MipsInstrInfo.h"
21#include "llvm/CodeGen/GlobalISel/CallLowering.h"
22#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
23#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
24#include "llvm/CodeGen/RegisterBankInfo.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/Support/ErrorHandling.h"
28#include <bitset>
29
30#define GET_SUBTARGETINFO_HEADER
31#include "MipsGenSubtargetInfo.inc"
32
33namespace llvm {
34class StringRef;
35
36enum class CompactBranchPolicy {
37 Never, ///< The policy 'never' may in some circumstances or for some
38 ///< ISAs not be absolutely adhered to.
39 Optimal, ///< Optimal is the default and will produce compact branches
40 ///< when appropriate.
41 Always ///< 'always' may in some circumstances may not be
42 ///< absolutely adhered to, there may not be a corresponding
43 ///< compact form of a branch.
44};
45} // namespace llvm
46
47#define OPTIONS_STRUCT_DECL
48#include "MipsOptions.inc"
49
50namespace llvm {
51class MipsTargetMachine;
52
53class MipsSubtarget : public MipsGenSubtargetInfo {
54 const MipsOptions &CLOpts;
55 const MipsMCOptions &MCCLOpts;
56
57 virtual void anchor();
58
59 enum MipsArchEnum {
60 MipsDefault,
61 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
62 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
63 };
64
65 enum class CPU { Others, P5600, I6400, I6500 };
66
67 // Used to avoid printing dsp warnings multiple times.
68 static bool DspWarningPrinted;
69
70 // Used to avoid printing msa warnings multiple times.
71 static bool MSAWarningPrinted;
72
73 // Used to avoid printing crc warnings multiple times.
74 static bool CRCWarningPrinted;
75
76 // Used to avoid printing ginv warnings multiple times.
77 static bool GINVWarningPrinted;
78
79 // Used to avoid printing Mips1 warnings multiple times.
80 static bool MIPS1WarningPrinted;
81
82 // Used to avoid printing virt warnings multiple times.
83 static bool VirtWarningPrinted;
84
85 // Mips architecture version
86 MipsArchEnum MipsArchVersion;
87
88 // Processor implementation
89 CPU ProcImpl = CPU::Others;
90
91 // IsLittle - The target is Little Endian
92 bool IsLittle;
93
94 // IsSoftFloat - The target does not support any floating point instructions.
95 bool IsSoftFloat;
96
97 // IsSingleFloat - The target only supports single precision float
98 // point operations. This enable the target to use all 32 32-bit
99 // floating point registers instead of only using even ones.
100 bool IsSingleFloat;
101
102 // IsFPXX - MIPS O32 modeless ABI.
103 bool IsFPXX;
104
105 // NoABICalls - Disable SVR4-style position-independent code.
106 bool NoABICalls;
107
108 // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
109 bool Abs2008;
110
111 // IsFP64bit - The target processor has 64-bit floating point registers.
112 bool IsFP64bit;
113
114 /// Are odd single-precision registers permitted?
115 /// This corresponds to -modd-spreg and -mno-odd-spreg
116 bool UseOddSPReg;
117
118 // IsNan2008 - IEEE 754-2008 NaN encoding.
119 bool IsNaN2008bit;
120
121 // IsGP64bit - General-purpose registers are 64 bits wide
122 bool IsGP64bit;
123
124 // MIPS GPRs explicitly reserved through -ffixed-REG.
125 std::bitset<32> UserReservedGPR;
126
127 // IsPTR64bit - Pointers are 64 bit wide
128 bool IsPTR64bit;
129
130 // HasVFPU - Processor has a vector floating point unit.
131 bool HasVFPU;
132
133 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
134 bool HasCnMips;
135
136 // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
137 bool HasCnMipsP;
138
139 // IsR5900 - CPU is R5900 (PlayStation 2 Emotion Engine).
140 bool IsR5900;
141
142 // FixR5900 - Enable R5900 short loop erratum fix.
143 bool FixR5900;
144
145 // UseSmallSection - Small section is used.
146 bool UseSmallSection;
147
148 /// Features related to the presence of specific instructions.
149
150 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
151 bool HasMips3_32;
152
153 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
154 bool HasMips3_32r2;
155
156 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
157 bool HasMips4_32;
158
159 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
160 bool HasMips4_32r2;
161
162 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
163 bool HasMips5_32r2;
164
165 // InMips16 -- can process Mips16 instructions
166 bool InMips16Mode;
167
168 // Mips16 hard float
169 bool InMips16HardFloat;
170
171 // InMicroMips -- can process MicroMips instructions
172 bool InMicroMipsMode;
173
174 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
175 bool HasDSP, HasDSPR2, HasDSPR3;
176
177 // Has3D -- Supports Mips3D ASE.
178 bool Has3D;
179
180 // HasMSA -- supports MSA ASE.
181 bool HasMSA;
182
183 // UseTCCInDIV -- Enables the use of trapping in the assembler.
184 bool UseTCCInDIV;
185
186 // Sym32 -- On Mips64 symbols are 32 bits.
187 bool HasSym32;
188
189 // HasEVA -- supports EVA ASE.
190 bool HasEVA;
191
192 // nomadd4 - disables generation of 4-operand madd.s, madd.d and
193 // related instructions.
194 bool DisableMadd4;
195
196 // HasMT -- support MT ASE.
197 bool HasMT;
198
199 // HasCRC -- supports R6 CRC ASE
200 bool HasCRC;
201
202 // HasVirt -- supports Virtualization ASE
203 bool HasVirt;
204
205 // HasGINV -- supports R6 Global INValidate ASE
206 bool HasGINV;
207
208 // Use hazard variants of the jump register instructions for indirect
209 // function calls and jump tables.
210 bool UseIndirectJumpsHazard;
211
212 // Disable use of the `jal` instruction.
213 bool UseLongCalls = false;
214
215 // Assume 32-bit GOT.
216 bool UseXGOT = false;
217
218 // Disable unaligned load store for r6.
219 bool StrictAlign;
220
221 // Use compact branch instructions for R6.
222 bool UseCompactBranches = true;
223
224 /// The minimum alignment known to hold of the stack frame on
225 /// entry to the function and which must be maintained by every function.
226 Align stackAlignment;
227
228 /// The overridden stack alignment.
229 MaybeAlign StackAlignOverride;
230
231 const MipsTargetMachine &TM;
232
233 MipsABIInfo ABI;
234
235 std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
236 std::unique_ptr<const MipsInstrInfo> InstrInfo;
237 std::unique_ptr<const MipsFrameLowering> FrameLowering;
238 std::unique_ptr<const MipsTargetLowering> TLInfo;
239
240public:
241 bool isPositionIndependent() const;
242 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
243 bool enablePostRAScheduler() const override;
244 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
245 CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override;
246
247 bool isABI_N64() const;
248 bool isABI_N32() const;
249 bool isABI_O32() const;
250 const MipsABIInfo &getABI() const { return ABI; }
251 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
252
253 bool isGPRReservedByUser(unsigned GPR) const {
254 assert(GPR < UserReservedGPR.size() && "GPR number out of range");
255 return UserReservedGPR[GPR];
256 }
257
258 /// This constructor initializes the data members to match that
259 /// of the specified triple.
260 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
261 StringRef ABIName, bool little, const MipsTargetMachine &TM,
262 MaybeAlign StackAlignOverride);
263
264 ~MipsSubtarget() override;
265
266 /// ParseSubtargetFeatures - Parses features string setting specified
267 /// subtarget options. Definition of function is auto generated by tblgen.
268 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
269
270 static const RTLIB::LibcallImpl HardFloatLibCalls[34];
271
272 bool hasMips1() const { return MipsArchVersion >= Mips1; }
273 bool hasMips2() const { return MipsArchVersion >= Mips2; }
274 bool hasMips3() const { return MipsArchVersion >= Mips3; }
275 bool hasMips4() const { return MipsArchVersion >= Mips4; }
276 bool hasMips5() const { return MipsArchVersion >= Mips5; }
277 bool hasMips4_32() const { return HasMips4_32; }
278 bool hasMips4_32r2() const { return HasMips4_32r2; }
279 bool hasMips32() const {
280 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
281 hasMips64();
282 }
283 bool hasMips32r2() const {
284 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
285 hasMips64r2();
286 }
287 bool hasMips32r3() const {
288 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
289 hasMips64r2();
290 }
291 bool hasMips32r5() const {
292 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
293 hasMips64r5();
294 }
295 bool hasMips32r6() const {
296 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
297 hasMips64r6();
298 }
299 bool hasMips64() const { return MipsArchVersion >= Mips64; }
300 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
301 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
302 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
303 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
304
305 bool hasCnMips() const { return HasCnMips; }
306 bool hasCnMipsP() const { return HasCnMipsP; }
307 bool isR5900() const { return IsR5900; }
308 bool fixR5900() const { return FixR5900; }
309
310 bool isLittle() const { return IsLittle; }
311 bool isABICalls() const { return !NoABICalls; }
312 bool isFPXX() const { return IsFPXX; }
313 bool isFP64bit() const { return IsFP64bit; }
314 bool useOddSPReg() const { return UseOddSPReg; }
315 bool noOddSPReg() const { return !UseOddSPReg; }
316 bool isNaN2008() const { return IsNaN2008bit; }
317 bool inAbs2008Mode() const { return Abs2008; }
318 bool isGP64bit() const { return IsGP64bit; }
319 bool isGP32bit() const { return !IsGP64bit; }
320 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
321 bool isPTR64bit() const { return IsPTR64bit; }
322 bool isPTR32bit() const { return !IsPTR64bit; }
323 bool hasSym32() const {
324 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
325 }
326 bool isSingleFloat() const { return IsSingleFloat; }
327 bool isTargetCOFF() const { return getTargetTriple().isOSBinFormatCOFF(); }
328 bool isTargetELF() const { return getTargetTriple().isOSBinFormatELF(); }
329 bool hasVFPU() const { return HasVFPU; }
330 bool inMips16Mode() const { return InMips16Mode; }
331 // Hard float for mips16 means essentially to compile as soft float
332 // but to use a runtime library for soft float that is written with
333 // native mips32 floating point instructions (those runtime routines
334 // run in mips32 hard float mode).
335 bool inMips16HardFloat() const {
336 return inMips16Mode() && InMips16HardFloat;
337 }
338 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
339 bool inMicroMips32r6Mode() const {
340 return inMicroMipsMode() && hasMips32r6();
341 }
342 bool hasDSP() const { return HasDSP; }
343 bool hasDSPR2() const { return HasDSPR2; }
344 bool hasDSPR3() const { return HasDSPR3; }
345 bool has3D() const { return Has3D; }
346 bool hasMSA() const { return HasMSA; }
347 bool disableMadd4() const { return DisableMadd4; }
348 bool hasEVA() const { return HasEVA; }
349 bool hasMT() const { return HasMT; }
350 bool hasCRC() const { return HasCRC; }
351 bool hasVirt() const { return HasVirt; }
352 bool hasGINV() const { return HasGINV; }
353 bool useIndirectJumpsHazard() const {
354 return UseIndirectJumpsHazard && hasMips32r2();
355 }
356 bool useSmallSection() const { return UseSmallSection; }
357
358 bool useCompactBranches() const {
359 return UseCompactBranches && hasMips32r6();
360 }
361
362 bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
363
364 bool useSoftFloat() const { return IsSoftFloat; }
365
366 bool useLongCalls() const { return UseLongCalls; }
367
368 bool useXGOT() const { return UseXGOT; }
369
370 /// Features related to the presence of specific instructions.
371 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
372 bool hasMTHC1() const { return hasMips32r2(); }
373
374 bool isTargetWindows() const { return getTargetTriple().isOSWindows(); }
375
376 bool isXRaySupported() const override { return true; }
377
378 // for now constant islands are on for the whole compilation unit but we only
379 // really use them if in addition we are in mips16 mode
380 bool useConstantIslands() const;
381
382 Align getStackAlignment() const { return stackAlignment; }
383
384 // Grab relocation model
385 Reloc::Model getRelocationModel() const;
386
387 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
388 const TargetMachine &TM);
389
390 /// Does the system support unaligned memory access.
391 ///
392 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
393 /// specify which component of the system provides it. Hardware, software, and
394 /// hybrid implementations are all valid.
395 bool systemSupportsUnalignedAccess() const {
396 return hasMips32r6() && !StrictAlign;
397 }
398
399 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
400
401 const MipsOptions &getCLOpts() const { return CLOpts; }
402 const MipsMCOptions &getMCCLOpts() const { return MCCLOpts; }
403 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
404 const TargetFrameLowering *getFrameLowering() const override {
405 return FrameLowering.get();
406 }
407 const MipsRegisterInfo *getRegisterInfo() const override {
408 return &InstrInfo->getRegisterInfo();
409 }
410 const MipsTargetLowering *getTargetLowering() const override {
411 return TLInfo.get();
412 }
413 void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override;
414
415protected:
416 // GlobalISel related APIs.
417 std::unique_ptr<CallLowering> CallLoweringInfo;
418 std::unique_ptr<LegalizerInfo> Legalizer;
419 std::unique_ptr<RegisterBankInfo> RegBankInfo;
420 std::unique_ptr<InstructionSelector> InstSelector;
421
422public:
423 const CallLowering *getCallLowering() const override;
424 const LegalizerInfo *getLegalizerInfo() const override;
425 const RegisterBankInfo *getRegBankInfo() const override;
426 InstructionSelector *getInstructionSelector() const override;
427};
428} // namespace llvm
429
430#endif
431