1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MipsFrameLowering.h"
18#include "MipsISelLowering.h"
19#include "MipsInstrInfo.h"
20#include "llvm/CodeGen/GlobalISel/CallLowering.h"
21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23#include "llvm/CodeGen/RegisterBankInfo.h"
24#include "llvm/CodeGen/TargetSubtargetInfo.h"
25#include "llvm/IR/DataLayout.h"
26#include "llvm/Support/ErrorHandling.h"
27
28#define GET_SUBTARGETINFO_HEADER
29#include "MipsGenSubtargetInfo.inc"
30
31namespace llvm {
32class StringRef;
33
34enum CompactBranchPolicy {
35 CB_Never, ///< The policy 'never' may in some circumstances or for some
36 ///< ISAs not be absolutely adhered to.
37 CB_Optimal, ///< Optimal is the default and will produce compact branches
38 ///< when appropriate.
39 CB_Always ///< 'always' may in some circumstances may not be
40 ///< absolutely adhered to, there may not be a corresponding
41 ///< compact form of a branch.
42};
43
44class MipsTargetMachine;
45
46class MipsSubtarget : public MipsGenSubtargetInfo {
47 virtual void anchor();
48
49 enum MipsArchEnum {
50 MipsDefault,
51 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
52 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
53 };
54
55 enum class CPU { Others, P5600, I6400, I6500 };
56
57 // Used to avoid printing dsp warnings multiple times.
58 static bool DspWarningPrinted;
59
60 // Used to avoid printing msa warnings multiple times.
61 static bool MSAWarningPrinted;
62
63 // Used to avoid printing crc warnings multiple times.
64 static bool CRCWarningPrinted;
65
66 // Used to avoid printing ginv warnings multiple times.
67 static bool GINVWarningPrinted;
68
69 // Used to avoid printing Mips1 warnings multiple times.
70 static bool MIPS1WarningPrinted;
71
72 // Used to avoid printing virt warnings multiple times.
73 static bool VirtWarningPrinted;
74
75 // Mips architecture version
76 MipsArchEnum MipsArchVersion;
77
78 // Processor implementation
79 CPU ProcImpl = CPU::Others;
80
81 // IsLittle - The target is Little Endian
82 bool IsLittle;
83
84 // IsSoftFloat - The target does not support any floating point instructions.
85 bool IsSoftFloat;
86
87 // IsSingleFloat - The target only supports single precision float
88 // point operations. This enable the target to use all 32 32-bit
89 // floating point registers instead of only using even ones.
90 bool IsSingleFloat;
91
92 // IsFPXX - MIPS O32 modeless ABI.
93 bool IsFPXX;
94
95 // NoABICalls - Disable SVR4-style position-independent code.
96 bool NoABICalls;
97
98 // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
99 bool Abs2008;
100
101 // IsFP64bit - The target processor has 64-bit floating point registers.
102 bool IsFP64bit;
103
104 /// Are odd single-precision registers permitted?
105 /// This corresponds to -modd-spreg and -mno-odd-spreg
106 bool UseOddSPReg;
107
108 // IsNan2008 - IEEE 754-2008 NaN encoding.
109 bool IsNaN2008bit;
110
111 // IsGP64bit - General-purpose registers are 64 bits wide
112 bool IsGP64bit;
113
114 // IsPTR64bit - Pointers are 64 bit wide
115 bool IsPTR64bit;
116
117 // HasVFPU - Processor has a vector floating point unit.
118 bool HasVFPU;
119
120 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
121 bool HasCnMips;
122
123 // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
124 bool HasCnMipsP;
125
126 // IsR5900 - CPU is R5900 (PlayStation 2 Emotion Engine).
127 bool IsR5900;
128
129 // FixR5900 - Enable R5900 short loop erratum fix.
130 bool FixR5900;
131
132 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
133 bool IsLinux;
134
135 // UseSmallSection - Small section is used.
136 bool UseSmallSection;
137
138 /// Features related to the presence of specific instructions.
139
140 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
141 bool HasMips3_32;
142
143 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
144 bool HasMips3_32r2;
145
146 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
147 bool HasMips4_32;
148
149 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
150 bool HasMips4_32r2;
151
152 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
153 bool HasMips5_32r2;
154
155 // InMips16 -- can process Mips16 instructions
156 bool InMips16Mode;
157
158 // Mips16 hard float
159 bool InMips16HardFloat;
160
161 // InMicroMips -- can process MicroMips instructions
162 bool InMicroMipsMode;
163
164 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
165 bool HasDSP, HasDSPR2, HasDSPR3;
166
167 // Has3D -- Supports Mips3D ASE.
168 bool Has3D;
169
170 // Allow mixed Mips16 and Mips32 in one source file
171 bool AllowMixed16_32;
172
173 // Optimize for space by compiling all functions as Mips 16 unless
174 // it needs floating point. Functions needing floating point are
175 // compiled as Mips32
176 bool Os16;
177
178 // HasMSA -- supports MSA ASE.
179 bool HasMSA;
180
181 // UseTCCInDIV -- Enables the use of trapping in the assembler.
182 bool UseTCCInDIV;
183
184 // Sym32 -- On Mips64 symbols are 32 bits.
185 bool HasSym32;
186
187 // HasEVA -- supports EVA ASE.
188 bool HasEVA;
189
190 // nomadd4 - disables generation of 4-operand madd.s, madd.d and
191 // related instructions.
192 bool DisableMadd4;
193
194 // HasMT -- support MT ASE.
195 bool HasMT;
196
197 // HasCRC -- supports R6 CRC ASE
198 bool HasCRC;
199
200 // HasVirt -- supports Virtualization ASE
201 bool HasVirt;
202
203 // HasGINV -- supports R6 Global INValidate ASE
204 bool HasGINV;
205
206 // Use hazard variants of the jump register instructions for indirect
207 // function calls and jump tables.
208 bool UseIndirectJumpsHazard;
209
210 // Disable use of the `jal` instruction.
211 bool UseLongCalls = false;
212
213 // Assume 32-bit GOT.
214 bool UseXGOT = false;
215
216 // Disable unaligned load store for r6.
217 bool StrictAlign;
218
219 // Use compact branch instructions for R6.
220 bool UseCompactBranches = true;
221
222 /// The minimum alignment known to hold of the stack frame on
223 /// entry to the function and which must be maintained by every function.
224 Align stackAlignment;
225
226 /// The overridden stack alignment.
227 MaybeAlign StackAlignOverride;
228
229 // We can override the determination of whether we are in mips16 mode
230 // as from the command line
231 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
232
233 const MipsTargetMachine &TM;
234
235 Triple TargetTriple;
236
237 std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
238 std::unique_ptr<const MipsInstrInfo> InstrInfo;
239 std::unique_ptr<const MipsFrameLowering> FrameLowering;
240 std::unique_ptr<const MipsTargetLowering> TLInfo;
241
242public:
243 bool isPositionIndependent() const;
244 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
245 bool enablePostRAScheduler() const override;
246 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
247 CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override;
248
249 bool isABI_N64() const;
250 bool isABI_N32() const;
251 bool isABI_O32() const;
252 const MipsABIInfo &getABI() const;
253 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
254
255 /// This constructor initializes the data members to match that
256 /// of the specified triple.
257 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
258 const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
259
260 ~MipsSubtarget() override;
261
262 /// ParseSubtargetFeatures - Parses features string setting specified
263 /// subtarget options. Definition of function is auto generated by tblgen.
264 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
265
266 static const RTLIB::LibcallImpl HardFloatLibCalls[34];
267
268 bool hasMips1() const { return MipsArchVersion >= Mips1; }
269 bool hasMips2() const { return MipsArchVersion >= Mips2; }
270 bool hasMips3() const { return MipsArchVersion >= Mips3; }
271 bool hasMips4() const { return MipsArchVersion >= Mips4; }
272 bool hasMips5() const { return MipsArchVersion >= Mips5; }
273 bool hasMips4_32() const { return HasMips4_32; }
274 bool hasMips4_32r2() const { return HasMips4_32r2; }
275 bool hasMips32() const {
276 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
277 hasMips64();
278 }
279 bool hasMips32r2() const {
280 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
281 hasMips64r2();
282 }
283 bool hasMips32r3() const {
284 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
285 hasMips64r2();
286 }
287 bool hasMips32r5() const {
288 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
289 hasMips64r5();
290 }
291 bool hasMips32r6() const {
292 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
293 hasMips64r6();
294 }
295 bool hasMips64() const { return MipsArchVersion >= Mips64; }
296 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
297 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
298 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
299 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
300
301 bool hasCnMips() const { return HasCnMips; }
302 bool hasCnMipsP() const { return HasCnMipsP; }
303 bool isR5900() const { return IsR5900; }
304 bool fixR5900() const { return FixR5900; }
305
306 bool isLittle() const { return IsLittle; }
307 bool isABICalls() const { return !NoABICalls; }
308 bool isFPXX() const { return IsFPXX; }
309 bool isFP64bit() const { return IsFP64bit; }
310 bool useOddSPReg() const { return UseOddSPReg; }
311 bool noOddSPReg() const { return !UseOddSPReg; }
312 bool isNaN2008() const { return IsNaN2008bit; }
313 bool inAbs2008Mode() const { return Abs2008; }
314 bool isGP64bit() const { return IsGP64bit; }
315 bool isGP32bit() const { return !IsGP64bit; }
316 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
317 bool isPTR64bit() const { return IsPTR64bit; }
318 bool isPTR32bit() const { return !IsPTR64bit; }
319 bool hasSym32() const {
320 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
321 }
322 bool isSingleFloat() const { return IsSingleFloat; }
323 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
324 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
325 bool hasVFPU() const { return HasVFPU; }
326 bool inMips16Mode() const { return InMips16Mode; }
327 bool inMips16ModeDefault() const {
328 return InMips16Mode;
329 }
330 // Hard float for mips16 means essentially to compile as soft float
331 // but to use a runtime library for soft float that is written with
332 // native mips32 floating point instructions (those runtime routines
333 // run in mips32 hard float mode).
334 bool inMips16HardFloat() const {
335 return inMips16Mode() && InMips16HardFloat;
336 }
337 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
338 bool inMicroMips32r6Mode() const {
339 return inMicroMipsMode() && hasMips32r6();
340 }
341 bool hasDSP() const { return HasDSP; }
342 bool hasDSPR2() const { return HasDSPR2; }
343 bool hasDSPR3() const { return HasDSPR3; }
344 bool has3D() const { return Has3D; }
345 bool hasMSA() const { return HasMSA; }
346 bool disableMadd4() const { return DisableMadd4; }
347 bool hasEVA() const { return HasEVA; }
348 bool hasMT() const { return HasMT; }
349 bool hasCRC() const { return HasCRC; }
350 bool hasVirt() const { return HasVirt; }
351 bool hasGINV() const { return HasGINV; }
352 bool useIndirectJumpsHazard() const {
353 return UseIndirectJumpsHazard && hasMips32r2();
354 }
355 bool useSmallSection() const { return UseSmallSection; }
356
357 bool useCompactBranches() const {
358 return UseCompactBranches && hasMips32r6();
359 }
360
361 bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
362
363 bool useSoftFloat() const { return IsSoftFloat; }
364
365 bool useLongCalls() const { return UseLongCalls; }
366
367 bool useXGOT() const { return UseXGOT; }
368
369 bool enableLongBranchPass() const {
370 return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32();
371 }
372
373 /// Features related to the presence of specific instructions.
374 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
375 bool hasMTHC1() const { return hasMips32r2(); }
376
377 bool allowMixed16_32() const { return inMips16ModeDefault() |
378 AllowMixed16_32; }
379
380 bool os16() const { return Os16; }
381
382 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
383
384 bool isXRaySupported() const override { return true; }
385
386 // for now constant islands are on for the whole compilation unit but we only
387 // really use them if in addition we are in mips16 mode
388 static bool useConstantIslands();
389
390 Align getStackAlignment() const { return stackAlignment; }
391
392 // Grab relocation model
393 Reloc::Model getRelocationModel() const;
394
395 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
396 const TargetMachine &TM);
397
398 /// Does the system support unaligned memory access.
399 ///
400 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
401 /// specify which component of the system provides it. Hardware, software, and
402 /// hybrid implementations are all valid.
403 bool systemSupportsUnalignedAccess() const {
404 return hasMips32r6() && !StrictAlign;
405 }
406
407 // Set helper classes
408 void setHelperClassesMips16();
409 void setHelperClassesMipsSE();
410
411 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
412
413 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
414 const TargetFrameLowering *getFrameLowering() const override {
415 return FrameLowering.get();
416 }
417 const MipsRegisterInfo *getRegisterInfo() const override {
418 return &InstrInfo->getRegisterInfo();
419 }
420 const MipsTargetLowering *getTargetLowering() const override {
421 return TLInfo.get();
422 }
423 void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override;
424
425protected:
426 // GlobalISel related APIs.
427 std::unique_ptr<CallLowering> CallLoweringInfo;
428 std::unique_ptr<LegalizerInfo> Legalizer;
429 std::unique_ptr<RegisterBankInfo> RegBankInfo;
430 std::unique_ptr<InstructionSelector> InstSelector;
431
432public:
433 const CallLowering *getCallLowering() const override;
434 const LegalizerInfo *getLegalizerInfo() const override;
435 const RegisterBankInfo *getRegBankInfo() const override;
436 InstructionSelector *getInstructionSelector() const override;
437};
438} // End llvm namespace
439
440#endif
441