1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips implementation of the TargetInstrInfo class.
10//
11// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
12// order for MipsLongBranch pass to work correctly when the code has inline
13// assembly. The returned value doesn't have to be the asm instruction's exact
14// size in bytes; MipsLongBranch only expects it to be the correct upper bound.
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
18#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19
20#include "MCTargetDesc/MipsMCTargetDesc.h"
21#include "Mips.h"
22#include "MipsRegisterInfo.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include <cstdint>
29
30#define GET_INSTRINFO_HEADER
31#include "MipsGenInstrInfo.inc"
32
33namespace llvm {
34
35class MachineInstr;
36class MachineOperand;
37class MipsSubtarget;
38class MCRegisterClass;
39using TargetRegisterClass = MCRegisterClass;
40class TargetRegisterInfo;
41
42class MipsInstrInfo : public MipsGenInstrInfo {
43 virtual void anchor();
44
45protected:
46 const MipsSubtarget &Subtarget;
47 unsigned UncondBrOpc;
48
49public:
50 enum BranchType {
51 BT_None, // Couldn't analyze branch.
52 BT_NoBranch, // No branches found.
53 BT_Uncond, // One unconditional branch.
54 BT_Cond, // One conditional branch.
55 BT_CondUncond, // A conditional branch followed by an unconditional branch.
56 BT_Indirect // One indirct branch.
57 };
58
59 explicit MipsInstrInfo(const MipsSubtarget &STI, const MipsRegisterInfo &RI,
60 unsigned UncondBrOpc);
61
62 MCInst getNop() const override;
63
64 static const MipsInstrInfo *create(MipsSubtarget &STI);
65
66 /// Branch Analysis
67 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
68 MachineBasicBlock *&FBB,
69 SmallVectorImpl<MachineOperand> &Cond,
70 bool AllowModify) const override;
71
72 unsigned removeBranch(MachineBasicBlock &MBB,
73 int *BytesRemoved = nullptr) const override;
74
75 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
76 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77 const DebugLoc &DL,
78 int *BytesAdded = nullptr) const override;
79
80 bool
81 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
82
83 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
84 MachineBasicBlock *&FBB,
85 SmallVectorImpl<MachineOperand> &Cond,
86 bool AllowModify,
87 SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
88
89 /// Determine the opcode of a non-delay slot form for a branch if one exists.
90 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
91
92 /// Determine if the branch target is in range.
93 bool isBranchOffsetInRange(unsigned BranchOpc,
94 int64_t BrOffset) const override;
95
96 bool SafeAfterMflo(const MachineInstr &MI) const;
97
98 /// Predicate to determine if an instruction can go in a forbidden slot.
99 bool SafeInForbiddenSlot(const MachineInstr &MI) const;
100
101 /// Predicate to determine if an instruction can go in an FPU delay slot.
102 bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
103 const MachineInstr &FPUMI) const;
104
105 /// Predicate to determine if an instruction can go in a load delay slot.
106 bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
107 const MachineInstr &LoadMI) const;
108
109 bool IsMfloOrMfhi(const MachineInstr &MI) const;
110
111 /// Predicate to determine if an instruction has a forbidden slot.
112 bool HasForbiddenSlot(const MachineInstr &MI) const;
113
114 /// Predicate to determine if an instruction has an FPU delay slot.
115 bool HasFPUDelaySlot(const MachineInstr &MI) const;
116
117 /// Predicate to determine if an instruction has a load delay slot.
118 bool HasLoadDelaySlot(const MachineInstr &MI) const;
119
120 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
121
122 /// Insert nop instruction when hazard condition is found
123 void insertNoop(MachineBasicBlock &MBB,
124 MachineBasicBlock::iterator MI) const override;
125
126 /// Insert an ISA appropriate `nop`.
127 // FIXME: Add support for MIPS16e.
128 MachineInstrBuilder insertNop(MachineBasicBlock &MBB,
129 MachineBasicBlock::iterator MI,
130 DebugLoc DL) const;
131
132 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
133 /// such, whenever a client has an instance of instruction info, it should
134 /// always be able to get register info as well (through this method).
135 const MipsRegisterInfo &getRegisterInfo() const {
136 return static_cast<const MipsRegisterInfo &>(
137 TargetInstrInfo::getRegisterInfo());
138 }
139
140 const TargetRegisterClass *
141 getInlineAsmMemoryOperandRegClass(InlineAsm::ConstraintCode C) const override;
142
143 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
144
145 virtual bool isBranchWithImm(unsigned Opc) const {
146 return false;
147 }
148
149 /// Return the number of bytes of code the specified instruction may be.
150 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
151
152 void storeRegToStackSlot(
153 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
154 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
155 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override {
156 storeRegToStack(MBB, MI: MBBI, SrcReg, isKill, FrameIndex, RC, Offset: 0, Flags);
157 }
158
159 void loadRegFromStackSlot(
160 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
161 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
162 Register VReg, unsigned SubReg = 0,
163 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override {
164 loadRegFromStack(MBB, MI: MBBI, DestReg, FrameIndex, RC, Offset: 0, Flags);
165 }
166
167 virtual void
168 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
169 Register SrcReg, bool isKill, int FrameIndex,
170 const TargetRegisterClass *RC, int64_t Offset,
171 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0;
172
173 virtual void loadRegFromStack(
174 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
175 int FrameIndex, const TargetRegisterClass *RC, int64_t Offset,
176 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0;
177
178 virtual void adjustStackPtr(unsigned SP, int64_t Amount,
179 MachineBasicBlock &MBB,
180 MachineBasicBlock::iterator I) const = 0;
181
182 /// Create an instruction which has the same operands and memory operands
183 /// as MI but has a new opcode.
184 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
185 MachineBasicBlock::iterator I) const;
186
187 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
188 unsigned &SrcOpIdx2) const override;
189
190 /// Perform target specific instruction verification.
191 bool verifyInstruction(const MachineInstr &MI,
192 StringRef &ErrInfo) const override;
193
194 std::pair<unsigned, unsigned>
195 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
196
197 ArrayRef<std::pair<unsigned, const char *>>
198 getSerializableDirectMachineOperandTargetFlags() const override;
199
200 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
201 Register Reg) const override;
202
203 std::optional<ParamLoadedValue>
204 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
205
206protected:
207 bool isZeroImm(const MachineOperand &op) const;
208
209 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
210 MachineMemOperand::Flags Flags) const;
211
212private:
213 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
214
215 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
216 MachineBasicBlock *&BB,
217 SmallVectorImpl<MachineOperand> &Cond) const;
218
219 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
220 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
221};
222
223/// Create MipsInstrInfo objects.
224const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
225const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
226
227namespace Mips {
228// Mask assignments for floating-point.
229enum FClassMask {
230 FClassMaskSignalingNaN = 1 << 0,
231 FClassMaskQuietNaN = 1 << 1,
232 FClassMaskNegativeInfinity = 1 << 2,
233 FClassMaskNegativeNormal = 1 << 3,
234 FClassMaskNegativeSubnormal = 1 << 4,
235 FClassMaskNegativeZero = 1 << 5,
236 FClassMaskPositiveInfinity = 1 << 6,
237 FClassMaskPositiveNormal = 1 << 7,
238 FClassMaskPositiveSubnormal = 1 << 8,
239 FClassMaskPositiveZero = 1 << 9
240};
241
242} // namespace Mips
243
244} // end namespace llvm
245
246#endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
247