1//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the NVPTX implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
14#define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
15
16#include "NVPTX.h"
17#include "NVPTXRegisterInfo.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "NVPTXGenInstrInfo.inc"
22
23namespace llvm {
24class NVPTXSubtarget;
25
26class NVPTXInstrInfo : public NVPTXGenInstrInfo {
27 const NVPTXRegisterInfo RegInfo;
28 virtual void anchor();
29public:
30 explicit NVPTXInstrInfo(const NVPTXSubtarget &STI);
31
32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
33
34 /* The following virtual functions are used in register allocation.
35 * They are not implemented because the existing interface and the logic
36 * at the caller side do not work for the elementized vector load and store.
37 *
38 * virtual Register isLoadFromStackSlot(const MachineInstr *MI,
39 * int &FrameIndex) const;
40 * virtual Register isStoreToStackSlot(const MachineInstr *MI,
41 * int &FrameIndex) const;
42 * virtual void storeRegToStackSlot(
43 * MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
44 * unsigned SrcReg, bool isKill, int FrameIndex,
45 * const TargetRegisterClass *RC, Register VReg,
46 * MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const;
47 * virtual void loadRegFromStackSlot(
48 * MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
49 * unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC,
50 * const TargetRegisterInfo *TRI, Register VReg, unsigned SubReg = 0,
51 * MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const;
52 */
53
54 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
55 const DebugLoc &DL, Register DestReg, Register SrcReg,
56 bool KillSrc, bool RenamableDest = false,
57 bool RenamableSrc = false) const override;
58
59 // Branch analysis.
60 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
61 MachineBasicBlock *&FBB,
62 SmallVectorImpl<MachineOperand> &Cond,
63 bool AllowModify) const override;
64 unsigned removeBranch(MachineBasicBlock &MBB,
65 int *BytesRemoved = nullptr) const override;
66 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
68 const DebugLoc &DL,
69 int *BytesAdded = nullptr) const override;
70};
71
72} // namespace llvm
73
74#endif
75