1//===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides PowerPC specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/PPCMCTargetDesc.h"
14#include "MCTargetDesc/PPCInstPrinter.h"
15#include "MCTargetDesc/PPCMCAsmInfo.h"
16#include "PPCELFStreamer.h"
17#include "PPCMCAsmInfo.h"
18#include "PPCTargetStreamer.h"
19#include "PPCXCOFFStreamer.h"
20#include "TargetInfo/PowerPCTargetInfo.h"
21#include "llvm/ADT/SmallPtrSet.h"
22#include "llvm/ADT/StringRef.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/MC/MCAsmBackend.h"
25#include "llvm/MC/MCAssembler.h"
26#include "llvm/MC/MCCodeEmitter.h"
27#include "llvm/MC/MCContext.h"
28#include "llvm/MC/MCDwarf.h"
29#include "llvm/MC/MCELFObjectWriter.h"
30#include "llvm/MC/MCELFStreamer.h"
31#include "llvm/MC/MCExpr.h"
32#include "llvm/MC/MCInstrAnalysis.h"
33#include "llvm/MC/MCInstrInfo.h"
34#include "llvm/MC/MCRegisterInfo.h"
35#include "llvm/MC/MCSectionXCOFF.h"
36#include "llvm/MC/MCStreamer.h"
37#include "llvm/MC/MCSubtargetInfo.h"
38#include "llvm/MC/MCSymbol.h"
39#include "llvm/MC/MCSymbolELF.h"
40#include "llvm/MC/MCSymbolXCOFF.h"
41#include "llvm/MC/MCXCOFFObjectWriter.h"
42#include "llvm/MC/TargetRegistry.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/Compiler.h"
45#include "llvm/Support/ErrorHandling.h"
46#include "llvm/Support/FormattedStream.h"
47#include "llvm/Support/raw_ostream.h"
48#include "llvm/TargetParser/Triple.h"
49
50using namespace llvm;
51
52#define GET_INSTRINFO_MC_DESC
53#define ENABLE_INSTR_PREDICATE_VERIFIER
54#include "PPCGenInstrInfo.inc"
55
56#define GET_SUBTARGETINFO_MC_DESC
57#include "PPCGenSubtargetInfo.inc"
58
59#define GET_REGINFO_MC_DESC
60#include "PPCGenRegisterInfo.inc"
61
62/// stripRegisterPrefix - This method strips the character prefix from a
63/// register name so that only the number is left. Used by for linux asm.
64const char *PPC::stripRegisterPrefix(const char *RegName) {
65 switch (RegName[0]) {
66 case 'a':
67 if (RegName[1] == 'c' && RegName[2] == 'c')
68 return RegName + 3;
69 break;
70 case 'f':
71 if (RegName[1] == 'p')
72 return RegName + 2;
73 [[fallthrough]];
74 case 'r':
75 case 'v':
76 if (RegName[1] == 's') {
77 if (RegName[2] == 'p')
78 return RegName + 3;
79 return RegName + 2;
80 }
81 return RegName + 1;
82 case 'c':
83 if (RegName[1] == 'r')
84 return RegName + 2;
85 break;
86 case 'w':
87 // For wacc and wacc_hi
88 if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') {
89 if (RegName[4] == '_')
90 return RegName + 7;
91 else
92 return RegName + 4;
93 }
94 break;
95 case 'd':
96 // For dmr, dmrp, dmrrow, dmrrowp
97 if (RegName[1] == 'm' && RegName[2] == 'r') {
98 if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' &&
99 RegName[6] == 'p')
100 return RegName + 7;
101 else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w')
102 return RegName + 6;
103 else if (RegName[3] == 'p')
104 return RegName + 4;
105 else
106 return RegName + 3;
107 }
108 break;
109 }
110
111 return RegName;
112}
113
114/// getRegNumForOperand - some operands use different numbering schemes
115/// for the same registers. For example, a VSX instruction may have any of
116/// vs0-vs63 allocated whereas an Altivec instruction could only have
117/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
118/// register number needed for the opcode/operand number combination.
119/// The operand number argument will be useful when we need to extend this
120/// to instructions that use both Altivec and VSX numbering (for different
121/// operands).
122MCRegister PPC::getRegNumForOperand(const MCInstrDesc &Desc, MCRegister Reg,
123 unsigned OpNo) {
124 int16_t regClass = Desc.operands()[OpNo].RegClass;
125 switch (regClass) {
126 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
127 // VSX32-VSX63 during encoding/disassembling
128 case PPC::VSSRCRegClassID:
129 case PPC::VSFRCRegClassID:
130 if (PPC::isVFRegister(Reg))
131 return PPC::VSX32 + (Reg - PPC::VF0);
132 break;
133 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
134 // VSX32-VSX63 during encoding/disassembling
135 case PPC::VSRCRegClassID:
136 if (PPC::isVRRegister(Reg))
137 return PPC::VSX32 + (Reg - PPC::V0);
138 break;
139 // Other RegClass doesn't need mapping
140 default:
141 break;
142 }
143 return Reg;
144}
145
146PPCTargetStreamer::PPCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
147
148// Pin the vtable to this file.
149PPCTargetStreamer::~PPCTargetStreamer() = default;
150
151static MCInstrInfo *createPPCMCInstrInfo() {
152 MCInstrInfo *X = new MCInstrInfo();
153 InitPPCMCInstrInfo(II: X);
154 return X;
155}
156
157static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
158 bool isPPC64 = TT.isPPC64();
159 unsigned Flavour = isPPC64 ? 0 : 1;
160 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
161
162 MCRegisterInfo *X = new MCRegisterInfo();
163 InitPPCMCRegisterInfo(RI: X, RA, DwarfFlavour: Flavour, EHFlavour: Flavour);
164 return X;
165}
166
167static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
168 StringRef CPU, StringRef FS) {
169 // Set some default feature to MC layer.
170 std::string FullFS = std::string(FS);
171
172 if (TT.isOSAIX()) {
173 if (!FullFS.empty())
174 FullFS = "+aix," + FullFS;
175 else
176 FullFS = "+aix";
177 }
178
179 return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS: FullFS);
180}
181
182static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
183 const Triple &TheTriple,
184 const MCTargetOptions &Options) {
185 bool isPPC64 = TheTriple.isPPC64();
186
187 MCAsmInfo *MAI;
188 if (TheTriple.isOSBinFormatXCOFF())
189 MAI = new PPCXCOFFMCAsmInfo(isPPC64, TheTriple, Options);
190 else
191 MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple, Options);
192
193 // Initial state of the frame pointer is R1.
194 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
195 MCCFIInstruction Inst =
196 MCCFIInstruction::cfiDefCfa(L: nullptr, Register: MRI.getDwarfRegNum(Reg, isEH: true), Offset: 0);
197 MAI->addInitialFrameState(Inst);
198
199 return MAI;
200}
201
202namespace {
203
204class PPCTargetAsmStreamer : public PPCTargetStreamer {
205 formatted_raw_ostream &OS;
206
207public:
208 PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
209 : PPCTargetStreamer(S), OS(OS) {}
210
211 void emitTCEntry(const MCSymbol &S, PPCMCExpr::Specifier Kind) override {
212 if (getContext().isXCOFF()) {
213 MCSymbolXCOFF *TCSym =
214 static_cast<const MCSectionXCOFF *>(Streamer.getCurrentSectionOnly())
215 ->getQualNameSymbol();
216 // On AIX, we have TLS variable offsets (symbol@({gd|ie|le|ld}) depending
217 // on the TLS access method (or model). For the general-dynamic access
218 // method, we also have region handle (symbol@m) for each variable. For
219 // local-dynamic, there is a module handle (_$TLSML[TC]@ml) for all
220 // variables. Finally for local-exec and initial-exec, we have a thread
221 // pointer, in r13 for 64-bit mode and returned by .__get_tpointer for
222 // 32-bit mode.
223 if (Kind == PPC::S_AIX_TLSGD || Kind == PPC::S_AIX_TLSGDM ||
224 Kind == PPC::S_AIX_TLSIE || Kind == PPC::S_AIX_TLSLE ||
225 Kind == PPC::S_AIX_TLSLD || Kind == PPC::S_AIX_TLSML)
226 OS << "\t.tc " << TCSym->getName() << "," << S.getName() << "@"
227 << getContext().getAsmInfo().getSpecifierName(S: Kind) << '\n';
228 else
229 OS << "\t.tc " << TCSym->getName() << "," << S.getName() << '\n';
230
231 if (TCSym->hasRename())
232 Streamer.emitXCOFFRenameDirective(Name: TCSym, Rename: TCSym->getSymbolTableName());
233 return;
234 }
235
236 OS << "\t.tc " << S.getName() << "[TC]," << S.getName() << '\n';
237 }
238
239 void emitMachine(StringRef CPU) override {
240 const Triple &TT = Streamer.getContext().getTargetTriple();
241 if (TT.isOSBinFormatXCOFF())
242 OS << "\t.machine\t" << '\"' << CPU << '\"' << '\n';
243 else
244 OS << "\t.machine " << CPU << '\n';
245 }
246
247 void emitAbiVersion(int AbiVersion) override {
248 OS << "\t.abiversion " << AbiVersion << '\n';
249 }
250
251 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
252 const MCAsmInfo &MAI = Streamer.getContext().getAsmInfo();
253
254 OS << "\t.localentry\t";
255 S->print(OS, MAI);
256 OS << ", ";
257 MAI.printExpr(OS, *LocalOffset);
258 OS << '\n';
259 }
260};
261
262class PPCTargetELFStreamer : public PPCTargetStreamer {
263public:
264 PPCTargetELFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
265
266 MCELFStreamer &getStreamer() {
267 return static_cast<MCELFStreamer &>(Streamer);
268 }
269
270 void emitTCEntry(const MCSymbol &S, PPCMCExpr::Specifier Kind) override {
271 // Creates a R_PPC64_TOC relocation
272 Streamer.emitValueToAlignment(Alignment: Align(8));
273 Streamer.emitSymbolValue(Sym: &S, Size: 8);
274 }
275
276 void emitMachine(StringRef CPU) override {
277 // FIXME: Is there anything to do in here or does this directive only
278 // limit the parser?
279 }
280
281 void emitAbiVersion(int AbiVersion) override {
282 ELFObjectWriter &W = getStreamer().getWriter();
283 unsigned Flags = W.getELFHeaderEFlags();
284 Flags &= ~ELF::EF_PPC64_ABI;
285 Flags |= (AbiVersion & ELF::EF_PPC64_ABI);
286 W.setELFHeaderEFlags(Flags);
287 }
288
289 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
290
291 // encodePPC64LocalEntryOffset will report an error if it cannot
292 // encode LocalOffset.
293 unsigned Encoded = encodePPC64LocalEntryOffset(LocalOffset);
294
295 unsigned Other = S->getOther();
296 Other &= ~ELF::STO_PPC64_LOCAL_MASK;
297 Other |= Encoded;
298 S->setOther(Other);
299
300 // For GAS compatibility, unless we already saw a .abiversion directive,
301 // set e_flags to indicate ELFv2 ABI.
302 ELFObjectWriter &W = getStreamer().getWriter();
303 unsigned Flags = W.getELFHeaderEFlags();
304 if ((Flags & ELF::EF_PPC64_ABI) == 0)
305 W.setELFHeaderEFlags(Flags | 2);
306 }
307
308 void emitAssignment(MCSymbol *S, const MCExpr *Value) override {
309 auto *Symbol = static_cast<MCSymbolELF *>(S);
310
311 // When encoding an assignment to set symbol A to symbol B, also copy
312 // the st_other bits encoding the local entry point offset.
313 if (copyLocalEntry(D: Symbol, S: Value))
314 UpdateOther.insert(Ptr: Symbol);
315 else
316 UpdateOther.erase(Ptr: Symbol);
317 }
318
319 void finish() override {
320 for (auto *Sym : UpdateOther)
321 if (Sym->isVariable())
322 copyLocalEntry(D: Sym, S: Sym->getVariableValue());
323
324 // Clear the set of symbols that needs to be updated so the streamer can
325 // be reused without issues.
326 UpdateOther.clear();
327 }
328
329private:
330 SmallPtrSet<MCSymbolELF *, 32> UpdateOther;
331
332 bool copyLocalEntry(MCSymbolELF *D, const MCExpr *S) {
333 auto *Ref = dyn_cast<const MCSymbolRefExpr>(Val: S);
334 if (!Ref)
335 return false;
336 auto &RhsSym = static_cast<const MCSymbolELF &>(Ref->getSymbol());
337 unsigned Other = D->getOther();
338 Other &= ~ELF::STO_PPC64_LOCAL_MASK;
339 Other |= RhsSym.getOther() & ELF::STO_PPC64_LOCAL_MASK;
340 D->setOther(Other);
341 return true;
342 }
343
344 unsigned encodePPC64LocalEntryOffset(const MCExpr *LocalOffset) {
345 MCAssembler &MCA = getStreamer().getAssembler();
346 int64_t Offset;
347 if (!LocalOffset->evaluateAsAbsolute(Res&: Offset, Asm: MCA))
348 MCA.getContext().reportError(L: LocalOffset->getLoc(),
349 Msg: ".localentry expression must be absolute");
350
351 switch (Offset) {
352 default:
353 MCA.getContext().reportError(
354 L: LocalOffset->getLoc(), Msg: ".localentry expression must be a power of 2");
355 return 0;
356 case 0:
357 return 0;
358 case 1:
359 return 1 << ELF::STO_PPC64_LOCAL_BIT;
360 case 4:
361 case 8:
362 case 16:
363 case 32:
364 case 64:
365 return Log2_32(Value: Offset) << ELF::STO_PPC64_LOCAL_BIT;
366 }
367 }
368};
369
370class PPCTargetMachOStreamer : public PPCTargetStreamer {
371public:
372 PPCTargetMachOStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
373
374 void emitTCEntry(const MCSymbol &S, PPCMCExpr::Specifier Kind) override {
375 llvm_unreachable("Unknown pseudo-op: .tc");
376 }
377
378 void emitMachine(StringRef CPU) override {
379 // FIXME: We should update the CPUType, CPUSubType in the Object file if
380 // the new values are different from the defaults.
381 }
382
383 void emitAbiVersion(int AbiVersion) override {
384 llvm_unreachable("Unknown pseudo-op: .abiversion");
385 }
386
387 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
388 llvm_unreachable("Unknown pseudo-op: .localentry");
389 }
390};
391
392class PPCTargetXCOFFStreamer : public PPCTargetStreamer {
393public:
394 PPCTargetXCOFFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
395
396 void emitTCEntry(const MCSymbol &S, PPCMCExpr::Specifier Kind) override {
397 const MCAsmInfo &MAI = Streamer.getContext().getAsmInfo();
398 const unsigned PointerSize = MAI.getCodePointerSize();
399 Streamer.emitValueToAlignment(Alignment: Align(PointerSize));
400 Streamer.emitValue(Value: MCSymbolRefExpr::create(Symbol: &S, specifier: Kind, Ctx&: Streamer.getContext()),
401 Size: PointerSize);
402 }
403
404 void emitMachine(StringRef CPU) override {
405 static_cast<XCOFFObjectWriter &>(Streamer.getAssemblerPtr()->getWriter())
406 .setCPU(CPU);
407 }
408
409 void emitAbiVersion(int AbiVersion) override {
410 llvm_unreachable("ABI-version pseudo-ops are invalid for XCOFF.");
411 }
412
413 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
414 llvm_unreachable("Local-entry pseudo-ops are invalid for XCOFF.");
415 }
416};
417
418} // end anonymous namespace
419
420static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
421 formatted_raw_ostream &OS,
422 MCInstPrinter *InstPrint) {
423 return new PPCTargetAsmStreamer(S, OS);
424}
425
426static MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) {
427 return new PPCTargetStreamer(S);
428}
429
430static MCTargetStreamer *
431createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
432 const Triple &TT = STI.getTargetTriple();
433 if (TT.isOSBinFormatELF())
434 return new PPCTargetELFStreamer(S);
435 if (TT.isOSBinFormatXCOFF())
436 return new PPCTargetXCOFFStreamer(S);
437 return new PPCTargetMachOStreamer(S);
438}
439
440static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
441 unsigned SyntaxVariant,
442 const MCAsmInfo &MAI,
443 const MCInstrInfo &MII,
444 const MCRegisterInfo &MRI) {
445 return new PPCInstPrinter(MAI, MII, MRI, T);
446}
447
448namespace {
449
450class PPCMCInstrAnalysis : public MCInstrAnalysis {
451public:
452 explicit PPCMCInstrAnalysis(const MCInstrInfo *Info)
453 : MCInstrAnalysis(Info) {}
454
455 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
456 uint64_t &Target) const override {
457 unsigned NumOps = Inst.getNumOperands();
458 if (NumOps == 0 ||
459 Info->get(Opcode: Inst.getOpcode()).operands()[NumOps - 1].OperandType !=
460 MCOI::OPERAND_PCREL)
461 return false;
462 Target = Addr + Inst.getOperand(i: NumOps - 1).getImm() * Size;
463 return true;
464 }
465};
466
467} // end anonymous namespace
468
469static MCInstrAnalysis *createPPCMCInstrAnalysis(const MCInstrInfo *Info) {
470 return new PPCMCInstrAnalysis(Info);
471}
472
473extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
474LLVMInitializePowerPCTargetMC() {
475 for (Target *T : {&getThePPC32Target(), &getThePPC32LETarget(),
476 &getThePPC64Target(), &getThePPC64LETarget()}) {
477 // Register the MC asm info.
478 RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
479
480 // Register the MC instruction info.
481 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createPPCMCInstrInfo);
482
483 // Register the MC register info.
484 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createPPCMCRegisterInfo);
485
486 // Register the MC subtarget info.
487 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createPPCMCSubtargetInfo);
488
489 // Register the MC instruction analyzer.
490 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createPPCMCInstrAnalysis);
491
492 // Register the MC Code Emitter
493 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createPPCMCCodeEmitter);
494
495 // Register the asm backend.
496 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createPPCAsmBackend);
497
498 // Register the elf streamer.
499 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createPPCELFStreamer);
500
501 // Register the XCOFF streamer.
502 TargetRegistry::RegisterXCOFFStreamer(T&: *T, Fn: createPPCXCOFFStreamer);
503
504 // Register the object target streamer.
505 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
506 Fn: createObjectTargetStreamer);
507
508 // Register the asm target streamer.
509 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createAsmTargetStreamer);
510
511 // Register the null target streamer.
512 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createNullTargetStreamer);
513
514 // Register the MCInstPrinter.
515 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createPPCMCInstPrinter);
516 }
517}
518