1//===- PPCMachineScheduler.cpp - MI Scheduler for PowerPC -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "PPCMachineScheduler.h"
10#include "MCTargetDesc/PPCMCTargetDesc.h"
11
12using namespace llvm;
13
14static cl::opt<bool>
15DisableAddiLoadHeuristic("disable-ppc-sched-addi-load",
16 cl::desc("Disable scheduling addi instruction before"
17 "load for ppc"), cl::Hidden);
18static cl::opt<bool>
19 EnableAddiHeuristic("ppc-postra-bias-addi",
20 cl::desc("Enable scheduling addi instruction as early"
21 "as possible post ra"),
22 cl::Hidden, cl::init(Val: true));
23
24static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand) {
25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8;
27}
28
29bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,
30 SchedCandidate &TryCand,
31 SchedBoundary &Zone) const {
32 if (DisableAddiLoadHeuristic)
33 return false;
34
35 SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand;
36 SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand;
37 if (isADDIInstr(Cand: FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {
38 TryCand.Reason = Stall;
39 return true;
40 }
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(Cand: SecondCand)) {
42 TryCand.Reason = NoCand;
43 return true;
44 }
45
46 return false;
47}
48
49bool PPCPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
50 SchedCandidate &TryCand,
51 SchedBoundary *Zone) const {
52 // From GenericScheduler::tryCandidate
53
54 // Initialize the candidate if needed.
55 if (!Cand.isValid()) {
56 TryCand.Reason = NodeOrder;
57 return true;
58 }
59
60 // Bias PhysReg Defs and copies to their uses and defined respectively.
61 if (tryGreater(TryVal: biasPhysReg(SU: TryCand.SU, isTop: TryCand.AtTop),
62 CandVal: biasPhysReg(SU: Cand.SU, isTop: Cand.AtTop), TryCand, Cand, Reason: PhysReg))
63 return TryCand.Reason != NoCand;
64
65 // Avoid exceeding the target's limit.
66 if (DAG->isTrackingPressure() &&
67 tryPressure(TryP: TryCand.RPDelta.Excess, CandP: Cand.RPDelta.Excess, TryCand, Cand,
68 Reason: RegExcess, TRI, MF: DAG->MF))
69 return TryCand.Reason != NoCand;
70
71 // Avoid increasing the max critical pressure in the scheduled region.
72 if (DAG->isTrackingPressure() &&
73 tryPressure(TryP: TryCand.RPDelta.CriticalMax, CandP: Cand.RPDelta.CriticalMax,
74 TryCand, Cand, Reason: RegCritical, TRI, MF: DAG->MF))
75 return TryCand.Reason != NoCand;
76
77 // We only compare a subset of features when comparing nodes between
78 // Top and Bottom boundary. Some properties are simply incomparable, in many
79 // other instances we should only override the other boundary if something
80 // is a clear good pick on one boundary. Skip heuristics that are more
81 // "tie-breaking" in nature.
82 bool SameBoundary = Zone != nullptr;
83 if (SameBoundary) {
84 // For loops that are acyclic path limited, aggressively schedule for
85 // latency. Within an single cycle, whenever CurrMOps > 0, allow normal
86 // heuristics to take precedence.
87 if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() &&
88 tryLatency(TryCand, Cand, Zone&: *Zone))
89 return TryCand.Reason != NoCand;
90
91 // Prioritize instructions that read unbuffered resources by stall cycles.
92 if (tryLess(TryVal: Zone->getLatencyStallCycles(SU: TryCand.SU),
93 CandVal: Zone->getLatencyStallCycles(SU: Cand.SU), TryCand, Cand, Reason: Stall))
94 return TryCand.Reason != NoCand;
95 }
96
97 // Keep clustered nodes together to encourage downstream peephole
98 // optimizations which may reduce resource requirements.
99 //
100 // This is a best effort to set things up for a post-RA pass. Optimizations
101 // like generating loads of multiple registers should ideally be done within
102 // the scheduler pass by combining the loads during DAG postprocessing.
103 unsigned CandZoneCluster = Cand.AtTop ? TopClusterID : BotClusterID;
104 unsigned TryCandZoneCluster = TryCand.AtTop ? TopClusterID : BotClusterID;
105 bool CandIsClusterSucc =
106 isTheSameCluster(A: CandZoneCluster, B: Cand.SU->ParentClusterIdx);
107 bool TryCandIsClusterSucc =
108 isTheSameCluster(A: TryCandZoneCluster, B: TryCand.SU->ParentClusterIdx);
109
110 if (tryGreater(TryVal: TryCandIsClusterSucc, CandVal: CandIsClusterSucc, TryCand, Cand,
111 Reason: Cluster))
112 return TryCand.Reason != NoCand;
113
114 if (SameBoundary) {
115 // Weak edges are for clustering and other constraints.
116 if (tryLess(TryVal: getWeakLeft(SU: TryCand.SU, isTop: TryCand.AtTop),
117 CandVal: getWeakLeft(SU: Cand.SU, isTop: Cand.AtTop), TryCand, Cand, Reason: Weak))
118 return TryCand.Reason != NoCand;
119 }
120
121 // Avoid increasing the max pressure of the entire region.
122 if (DAG->isTrackingPressure() &&
123 tryPressure(TryP: TryCand.RPDelta.CurrentMax, CandP: Cand.RPDelta.CurrentMax, TryCand,
124 Cand, Reason: RegMax, TRI, MF: DAG->MF))
125 return TryCand.Reason != NoCand;
126
127 if (SameBoundary) {
128 // Avoid critical resource consumption and balance the schedule.
129 TryCand.initResourceDelta(DAG, SchedModel);
130 if (tryLess(TryVal: TryCand.ResDelta.CritResources, CandVal: Cand.ResDelta.CritResources,
131 TryCand, Cand, Reason: ResourceReduce))
132 return TryCand.Reason != NoCand;
133 if (tryGreater(TryVal: TryCand.ResDelta.DemandedResources,
134 CandVal: Cand.ResDelta.DemandedResources, TryCand, Cand,
135 Reason: ResourceDemand))
136 return TryCand.Reason != NoCand;
137
138 // Avoid serializing long latency dependence chains.
139 // For acyclic path limited loops, latency was already checked above.
140 if (!RegionPolicy.DisableLatencyHeuristic && TryCand.Policy.ReduceLatency &&
141 !Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone&: *Zone))
142 return TryCand.Reason != NoCand;
143
144 // Fall through to original instruction order.
145 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) ||
146 (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
147 TryCand.Reason = NodeOrder;
148 }
149 }
150
151 // GenericScheduler::tryCandidate end
152
153 // Add powerpc specific heuristic only when TryCand isn't selected or
154 // selected as node order.
155 if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
156 return true;
157
158 // There are some benefits to schedule the ADDI before the load to hide the
159 // latency, as RA may create a true dependency between the load and addi.
160 if (SameBoundary) {
161 if (biasAddiLoadCandidate(Cand, TryCand, Zone&: *Zone))
162 return TryCand.Reason != NoCand;
163 }
164
165 return TryCand.Reason != NoCand;
166}
167
168bool PPCPostRASchedStrategy::biasAddiCandidate(SchedCandidate &Cand,
169 SchedCandidate &TryCand) const {
170 if (!EnableAddiHeuristic)
171 return false;
172
173 if (isADDIInstr(Cand: TryCand) && !isADDIInstr(Cand)) {
174 TryCand.Reason = Stall;
175 return true;
176 }
177 return false;
178}
179
180bool PPCPostRASchedStrategy::tryCandidate(SchedCandidate &Cand,
181 SchedCandidate &TryCand) {
182 // From PostGenericScheduler::tryCandidate
183
184 // Initialize the candidate if needed.
185 if (!Cand.isValid()) {
186 TryCand.Reason = NodeOrder;
187 return true;
188 }
189
190 // Prioritize instructions that read unbuffered resources by stall cycles.
191 if (tryLess(TryVal: Top.getLatencyStallCycles(SU: TryCand.SU),
192 CandVal: Top.getLatencyStallCycles(SU: Cand.SU), TryCand, Cand, Reason: Stall))
193 return TryCand.Reason != NoCand;
194
195 // Keep clustered nodes together.
196 unsigned CandZoneCluster = Cand.AtTop ? TopClusterID : BotClusterID;
197 unsigned TryCandZoneCluster = TryCand.AtTop ? TopClusterID : BotClusterID;
198 bool CandIsClusterSucc =
199 isTheSameCluster(A: CandZoneCluster, B: Cand.SU->ParentClusterIdx);
200 bool TryCandIsClusterSucc =
201 isTheSameCluster(A: TryCandZoneCluster, B: TryCand.SU->ParentClusterIdx);
202
203 if (tryGreater(TryVal: TryCandIsClusterSucc, CandVal: CandIsClusterSucc, TryCand, Cand,
204 Reason: Cluster))
205 return TryCand.Reason != NoCand;
206
207 // Avoid critical resource consumption and balance the schedule.
208 if (tryLess(TryVal: TryCand.ResDelta.CritResources, CandVal: Cand.ResDelta.CritResources,
209 TryCand, Cand, Reason: ResourceReduce))
210 return TryCand.Reason != NoCand;
211 if (tryGreater(TryVal: TryCand.ResDelta.DemandedResources,
212 CandVal: Cand.ResDelta.DemandedResources, TryCand, Cand,
213 Reason: ResourceDemand))
214 return TryCand.Reason != NoCand;
215
216 // Avoid serializing long latency dependence chains.
217 if (Cand.Policy.ReduceLatency && tryLatency(TryCand, Cand, Zone&: Top)) {
218 return TryCand.Reason != NoCand;
219 }
220
221 // Fall through to original instruction order.
222 if (TryCand.SU->NodeNum < Cand.SU->NodeNum)
223 TryCand.Reason = NodeOrder;
224
225 // PostGenericScheduler::tryCandidate end
226
227 // Add powerpc post ra specific heuristic only when TryCand isn't selected or
228 // selected as node order.
229 if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
230 return true;
231
232 // There are some benefits to schedule the ADDI as early as possible post ra
233 // to avoid stalled by vector instructions which take up all the hw units.
234 // And ADDI is usually used to post inc the loop indvar, which matters the
235 // performance.
236 if (biasAddiCandidate(Cand, TryCand))
237 return TryCand.Reason != NoCand;
238
239 return TryCand.Reason != NoCand;
240}
241
242void PPCPostRASchedStrategy::enterMBB(MachineBasicBlock *MBB) {
243 // Custom PPC PostRA specific behavior here.
244 PostGenericScheduler::enterMBB(MBB);
245}
246
247void PPCPostRASchedStrategy::leaveMBB() {
248 // Custom PPC PostRA specific behavior here.
249 PostGenericScheduler::leaveMBB();
250}
251
252void PPCPostRASchedStrategy::initialize(ScheduleDAGMI *Dag) {
253 // Custom PPC PostRA specific initialization here.
254 PostGenericScheduler::initialize(Dag);
255}
256
257SUnit *PPCPostRASchedStrategy::pickNode(bool &IsTopNode) {
258 // Custom PPC PostRA specific scheduling here.
259 return PostGenericScheduler::pickNode(IsTopNode);
260}
261
262