1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_POWERPC_PPCSELECTIONDAGINFO_H
10#define LLVM_LIB_TARGET_POWERPC_PPCSELECTIONDAGINFO_H
11
12#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
13
14#define GET_SDNODE_ENUM
15#include "PPCGenSDNodeInfo.inc"
16
17namespace llvm {
18namespace PPCISD {
19
20enum NodeType : unsigned {
21 /// The result of the mflr at function entry, used for PIC code.
22 GlobalBaseReg = GENERATED_OPCODE_END,
23
24 /// The combination of sra[wd]i and addze used to implemented signed
25 /// integer division by a power of 2. The first operand is the dividend,
26 /// and the second is the constant shift amount (representing the
27 /// divisor).
28 SRA_ADDZE,
29
30 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
31 /// This copies the bits corresponding to the specified CRREG into the
32 /// resultant GPR. Bits corresponding to other CR regs are undefined.
33 MFOCRF,
34
35 // FIXME: Remove these once the ANDI glue bug is fixed:
36 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
37 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
38 /// implement truncation of i32 or i64 to i1.
39 ANDI_rec_1_EQ_BIT,
40 ANDI_rec_1_GT_BIT,
41
42 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
43 // target (returns (Lo, Hi)). It takes a chain operand.
44 READ_TIME_BASE,
45
46 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
47 /// loops.
48 BDNZ,
49 BDZ,
50
51 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
52 /// local dynamic TLS and position indendepent code on PPC32.
53 PPC32_PICGOT,
54
55 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
56 /// during instruction selection to optimize a BUILD_VECTOR into
57 /// operations on splats. This is necessary to avoid losing these
58 /// optimizations due to constant folding.
59 VADD_SPLAT,
60};
61
62} // namespace PPCISD
63
64class PPCSelectionDAGInfo : public SelectionDAGGenTargetInfo {
65public:
66 PPCSelectionDAGInfo();
67
68 ~PPCSelectionDAGInfo() override;
69
70 const char *getTargetNodeName(unsigned Opcode) const override;
71
72 void verifyTargetNode(const SelectionDAG &DAG,
73 const SDNode *N) const override;
74
75 std::pair<SDValue, SDValue>
76 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
77 SDValue Op1, SDValue Op2, SDValue Op3,
78 const CallInst *CI) const override;
79 std::pair<SDValue, SDValue> EmitTargetCodeForStrcmp(
80 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1,
81 SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo,
82 const CallInst *CI) const override;
83 std::pair<SDValue, SDValue>
84 EmitTargetCodeForStrcpy(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
85 SDValue Dest, SDValue Src,
86 MachinePointerInfo DestPtrInfo,
87 MachinePointerInfo SrcPtrInfo, bool isStpcpy,
88 const CallInst *CI) const override;
89
90 std::pair<SDValue, SDValue>
91 EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
92 SDValue Src, const CallInst *CI) const override;
93
94 std::pair<SDValue, SDValue>
95 EmitTargetCodeForStrstr(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
96 SDValue Op1, SDValue Op2,
97 const CallInst *CI) const override;
98};
99
100} // namespace llvm
101
102#endif // LLVM_LIB_TARGET_POWERPC_PPCSELECTIONDAGINFO_H
103