1//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an RISC-V MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVInstPrinter.h"
14#include "RISCVBaseInfo.h"
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCInstPrinter.h"
19#include "llvm/MC/MCInstrAnalysis.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/MC/MCSymbol.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Support/ErrorHandling.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "asm-printer"
27
28// Include the auto-generated portion of the assembly writer.
29#define PRINT_ALIAS_INSTR
30#include "RISCVGenAsmWriter.inc"
31
32static cl::opt<bool>
33 NoAliases("riscv-no-aliases",
34 cl::desc("Disable the emission of assembler pseudo instructions"),
35 cl::init(Val: false), cl::Hidden);
36
37static cl::opt<bool> EmitX8AsFP("riscv-emit-x8-as-fp",
38 cl::desc("Emit x8 as fp instead of s0"),
39 cl::init(Val: false), cl::Hidden);
40
41// Print architectural register names rather than the ABI names (such as x2
42// instead of sp).
43// TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
44// member.
45static bool ArchRegNames;
46
47// The command-line flags above are used by llvm-mc and llc. They can be used by
48// `llvm-objdump`, but we override their values here to handle options passed to
49// `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
50// be an easier way to allow these options in all these tools, without doing it
51// this way.
52bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
53 if (Opt == "no-aliases") {
54 PrintAliases = false;
55 return true;
56 }
57 if (Opt == "numeric") {
58 ArchRegNames = true;
59 return true;
60 }
61 if (Opt == "emit-x8-as-fp") {
62 if (!ArchRegNames)
63 EmitX8AsFP = true;
64 return true;
65 }
66
67 return false;
68}
69
70void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
71 StringRef Annot, const MCSubtargetInfo &STI,
72 raw_ostream &O) {
73 bool Res = false;
74 const MCInst *NewMI = MI;
75 MCInst UncompressedMI;
76 if (PrintAliases && !NoAliases)
77 Res = RISCVRVC::uncompress(OutInst&: UncompressedMI, MI: *MI, STI);
78 if (Res)
79 NewMI = &UncompressedMI;
80 if (!PrintAliases || NoAliases || !printAliasInstr(MI: NewMI, Address, STI, OS&: O))
81 printInstruction(MI: NewMI, Address, STI, O);
82 printAnnotation(OS&: O, Annot);
83}
84
85void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) {
86 markup(OS&: O, M: Markup::Register) << getRegisterName(Reg);
87}
88
89void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
90 const MCSubtargetInfo &STI,
91 raw_ostream &O) {
92 const MCOperand &MO = MI->getOperand(i: OpNo);
93
94 if (MO.isReg()) {
95 printRegName(O, Reg: MO.getReg());
96 return;
97 }
98
99 if (MO.isImm()) {
100 printImm(MI, OpNo, STI, O);
101 return;
102 }
103
104 assert(MO.isExpr() && "Unknown operand kind in printOperand");
105 MAI.printExpr(O, *MO.getExpr());
106}
107
108void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
109 unsigned OpNo,
110 const MCSubtargetInfo &STI,
111 raw_ostream &O) {
112 // Do not print the numeric target address when symbolizing.
113 if (SymbolizeOperands)
114 return;
115
116 const MCOperand &MO = MI->getOperand(i: OpNo);
117 if (!MO.isImm())
118 return printOperand(MI, OpNo, STI, O);
119
120 if (PrintBranchImmAsAddress) {
121 uint64_t Target = Address + MO.getImm();
122 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
123 Target &= 0xffffffff;
124 markup(OS&: O, M: Markup::Target) << formatHex(Value: Target);
125 } else {
126 markup(OS&: O, M: Markup::Target) << formatImm(Value: MO.getImm());
127 }
128}
129
130void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
131 const MCSubtargetInfo &STI,
132 raw_ostream &O) {
133 unsigned Imm = MI->getOperand(i: OpNo).getImm();
134 auto Range = RISCVSysReg::lookupSysRegByEncoding(Encoding: Imm);
135 for (auto &Reg : Range) {
136 if (Reg.IsAltName || Reg.IsDeprecatedName)
137 continue;
138 if (Reg.haveRequiredFeatures(ActiveFeatures: STI.getFeatureBits())) {
139 markup(OS&: O, M: Markup::Register) << Reg.Name;
140 return;
141 }
142 }
143 markup(OS&: O, M: Markup::Register) << formatImm(Value: Imm);
144}
145
146void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
147 const MCSubtargetInfo &STI,
148 raw_ostream &O) {
149 unsigned FenceArg = MI->getOperand(i: OpNo).getImm();
150 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
151
152 if ((FenceArg & RISCVFenceField::I) != 0)
153 O << 'i';
154 if ((FenceArg & RISCVFenceField::O) != 0)
155 O << 'o';
156 if ((FenceArg & RISCVFenceField::R) != 0)
157 O << 'r';
158 if ((FenceArg & RISCVFenceField::W) != 0)
159 O << 'w';
160 if (FenceArg == 0)
161 O << "0";
162}
163
164void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
165 const MCSubtargetInfo &STI, raw_ostream &O) {
166 auto FRMArg =
167 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
168 if (PrintAliases && !NoAliases && FRMArg == RISCVFPRndMode::RoundingMode::DYN)
169 return;
170 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
171}
172
173void RISCVInstPrinter::printFRMArgLegacy(const MCInst *MI, unsigned OpNo,
174 const MCSubtargetInfo &STI,
175 raw_ostream &O) {
176 auto FRMArg =
177 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
178 // Never print rounding mode if it's the default 'rne'. This ensures the
179 // output can still be parsed by older tools that erroneously failed to
180 // accept a rounding mode.
181 if (FRMArg == RISCVFPRndMode::RoundingMode::RNE)
182 return;
183 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
184}
185
186void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
187 const MCSubtargetInfo &STI,
188 raw_ostream &O) {
189 unsigned Imm = MI->getOperand(i: OpNo).getImm();
190 if (Imm == 1) {
191 markup(OS&: O, M: Markup::Immediate) << "min";
192 } else if (Imm == 30) {
193 markup(OS&: O, M: Markup::Immediate) << "inf";
194 } else if (Imm == 31) {
195 markup(OS&: O, M: Markup::Immediate) << "nan";
196 } else {
197 float FPVal = RISCVLoadFPImm::getFPImm(Imm);
198 // If the value is an integer, print a .0 fraction. Otherwise, use %g to
199 // which will not print trailing zeros and will use scientific notation
200 // if it is shorter than printing as a decimal. The smallest value requires
201 // 12 digits of precision including the decimal.
202 if (FPVal == (int)(FPVal))
203 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.1f", Vals: FPVal);
204 else
205 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.12g", Vals: FPVal);
206 }
207}
208
209void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
210 const MCSubtargetInfo &STI,
211 raw_ostream &O) {
212 const MCOperand &MO = MI->getOperand(i: OpNo);
213
214 assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
215 O << "(";
216 printRegName(O, Reg: MO.getReg());
217 O << ")";
218}
219
220void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
221 const MCSubtargetInfo &STI, raw_ostream &O) {
222 unsigned Imm = MI->getOperand(i: OpNo).getImm();
223 // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
224 // altfmt=1 without zvfbfa or zvfofp8min extension, or non-zero in bits 9 and
225 // above.
226 if (RISCVVType::getVLMUL(VType: Imm) == RISCVVType::VLMUL::LMUL_RESERVED ||
227 RISCVVType::getSEW(VType: Imm) > 64 ||
228 (RISCVVType::isAltFmt(VType: Imm) &&
229 !(STI.hasFeature(Feature: RISCV::FeatureStdExtZvfbfa) ||
230 STI.hasFeature(Feature: RISCV::FeatureStdExtZvfofp8min) ||
231 STI.hasFeature(Feature: RISCV::FeatureVendorXSfvfbfexp16e))) ||
232 (Imm >> 9) != 0) {
233 O << formatImm(Value: Imm);
234 return;
235 }
236 // Print the text form.
237 RISCVVType::printVType(VType: Imm, OS&: O);
238}
239
240void RISCVInstPrinter::printXSfmmVType(const MCInst *MI, unsigned OpNo,
241 const MCSubtargetInfo &STI,
242 raw_ostream &O) {
243 unsigned Imm = MI->getOperand(i: OpNo).getImm();
244 assert(RISCVVType::isValidXSfmmVType(Imm));
245 unsigned SEW = RISCVVType::getSEW(VType: Imm);
246 O << "e" << SEW;
247 bool AltFmt = RISCVVType::isAltFmt(VType: Imm);
248 if (AltFmt)
249 O << "alt";
250 unsigned Widen = RISCVVType::getXSfmmWiden(VType: Imm);
251 O << ", w" << Widen;
252}
253
254// Print a Zcmp RList. If we are printing architectural register names rather
255// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
256// registers. Otherwise, we print "{ra, s0-s11}".
257void RISCVInstPrinter::printRegList(const MCInst *MI, unsigned OpNo,
258 const MCSubtargetInfo &STI, raw_ostream &O) {
259 unsigned Imm = MI->getOperand(i: OpNo).getImm();
260
261 assert(Imm >= RISCVZC::RLISTENCODE::RA &&
262 Imm <= RISCVZC::RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
263
264 O << "{";
265 printRegName(O, Reg: RISCV::X1);
266
267 if (Imm >= RISCVZC::RLISTENCODE::RA_S0) {
268 O << ", ";
269 printRegName(O, Reg: RISCV::X8);
270 }
271
272 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S1) {
273 O << '-';
274 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S1 || ArchRegNames)
275 printRegName(O, Reg: RISCV::X9);
276 }
277
278 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S2) {
279 if (ArchRegNames)
280 O << ", ";
281 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S2 || ArchRegNames)
282 printRegName(O, Reg: RISCV::X18);
283 }
284
285 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S3) {
286 if (ArchRegNames)
287 O << '-';
288 unsigned Offset = (Imm - RISCVZC::RLISTENCODE::RA_S0_S3);
289 // Encodings for S3-S9 are contiguous. There is no encoding for S10, so we
290 // must skip to S11(X27).
291 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S11)
292 ++Offset;
293 printRegName(O, Reg: RISCV::X19 + Offset);
294 }
295
296 O << "}";
297}
298
299void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
300 const MCSubtargetInfo &STI, raw_ostream &O) {
301 const MCOperand &OffsetMO = MI->getOperand(i: OpNo + 1);
302
303 assert(OffsetMO.isReg() && "printRegReg can only print register operands");
304 printRegName(O, Reg: OffsetMO.getReg());
305
306 O << "(";
307 const MCOperand &BaseMO = MI->getOperand(i: OpNo);
308 assert(BaseMO.isReg() && "printRegReg can only print register operands");
309 printRegName(O, Reg: BaseMO.getReg());
310 O << ")";
311}
312
313void RISCVInstPrinter::printStackAdj(const MCInst *MI, unsigned OpNo,
314 const MCSubtargetInfo &STI, raw_ostream &O,
315 bool Negate) {
316 int64_t Imm = MI->getOperand(i: OpNo).getImm();
317 bool IsRV64 = STI.hasFeature(Feature: RISCV::Feature64Bit);
318 int64_t StackAdj = 0;
319 auto RlistVal = MI->getOperand(i: 0).getImm();
320 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64);
321 StackAdj = Imm + Base;
322 assert((StackAdj >= Base && StackAdj <= Base + 48) &&
323 "Incorrect stack adjust");
324 if (Negate)
325 StackAdj = -StackAdj;
326
327 // RAII guard for ANSI color escape sequences
328 WithMarkup ScopedMarkup = markup(OS&: O, M: Markup::Immediate);
329 O << StackAdj;
330}
331
332void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
333 const MCSubtargetInfo &STI,
334 raw_ostream &O) {
335 const MCOperand &MO = MI->getOperand(i: OpNo);
336
337 assert(MO.isReg() && "printVMaskReg can only print register operands");
338 if (MO.getReg() == RISCV::NoRegister)
339 return;
340 O << ", ";
341 printRegName(O, Reg: MO.getReg());
342 O << ".t";
343}
344
345void RISCVInstPrinter::printImm(const MCInst *MI, unsigned OpNo,
346 const MCSubtargetInfo &STI, raw_ostream &O) {
347 const MCOperand &Op = MI->getOperand(i: OpNo);
348 const unsigned Opcode = MI->getOpcode();
349 uint64_t Imm = Op.getImm();
350 if (STI.getTargetTriple().isOSBinFormatMachO() &&
351 (Opcode == RISCV::ANDI || Opcode == RISCV::ORI || Opcode == RISCV::XORI ||
352 Opcode == RISCV::C_ANDI || Opcode == RISCV::AUIPC ||
353 Opcode == RISCV::LUI)) {
354 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
355 Imm &= 0xffffffff;
356 markup(OS&: O, M: Markup::Immediate) << formatHex(Value: Imm);
357 } else
358 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Imm);
359}
360
361const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
362 // When PrintAliases is enabled, and EmitX8AsFP is enabled, x8 will be printed
363 // as fp instead of s0. Note that these similar registers are not replaced:
364 // - X8_H: used for f16 register in zhinx
365 // - X8_W: used for f32 register in zfinx
366 // - X8_X9: used for GPR Pair
367 if (!ArchRegNames && EmitX8AsFP && Reg == RISCV::X8)
368 return "fp";
369 return getRegisterName(Reg, AltIdx: ArchRegNames ? RISCV::NoRegAltName
370 : RISCV::ABIRegAltName);
371}
372