1//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an RISC-V MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVInstPrinter.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCAsmInfo.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstPrinter.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MC/MCSymbol.h"
23#include "llvm/Support/ErrorHandling.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "asm-printer"
27
28// Include the auto-generated portion of the assembly writer.
29#define PRINT_ALIAS_INSTR
30#include "RISCVGenAsmWriter.inc"
31
32// Print architectural register names rather than the ABI names (such as x2
33// instead of sp).
34// TODO: Make RISCVInstPrinter::getRegisterName non-static so that this and
35// EmitX8AsFP can be members.
36static bool ArchRegNames;
37static bool EmitX8AsFP;
38
39RISCVInstPrinter::RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
40 const MCRegisterInfo &MRI)
41 : MCInstPrinter(MAI, MII, MRI),
42 CLOpts(RISCV_MC::getCLOpts(Options: MAI.getTargetOptions())) {}
43
44// -riscv-no-aliases and -riscv-emit-x8-as-fp are used by llvm-mc and llc. They
45// can be used by `llvm-objdump`, but we override their values here to handle
46// options passed to `llvm-objdump` with `-M` (which matches GNU objdump). There
47// did not seem to be an easier way to allow these options in all these tools,
48// without doing it this way.
49bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
50 if (Opt == "no-aliases") {
51 PrintAliases = false;
52 return true;
53 }
54 if (Opt == "numeric") {
55 ArchRegNames = true;
56 return true;
57 }
58 if (Opt == "emit-x8-as-fp") {
59 if (!ArchRegNames)
60 EmitX8AsFP = true;
61 return true;
62 }
63
64 return false;
65}
66
67void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
68 StringRef Annot, const MCSubtargetInfo &STI,
69 raw_ostream &O) {
70 bool Res = false;
71 const MCInst *NewMI = MI;
72 MCInst UncompressedMI;
73 if (PrintAliases && !CLOpts.no_aliases)
74 Res = RISCVRVC::uncompress(OutInst&: UncompressedMI, MI: *MI, STI);
75 if (Res)
76 NewMI = &UncompressedMI;
77 if (!PrintAliases || CLOpts.no_aliases ||
78 !printAliasInstr(MI: NewMI, Address, STI, OS&: O))
79 printInstruction(MI: NewMI, Address, STI, O);
80 printAnnotation(OS&: O, Annot);
81}
82
83void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) {
84 markup(OS&: O, M: Markup::Register) << getRegisterName(CLOpts, Reg);
85}
86
87void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
88 const MCSubtargetInfo &STI,
89 raw_ostream &O) {
90 const MCOperand &MO = MI->getOperand(i: OpNo);
91
92 if (MO.isReg()) {
93 printRegName(O, Reg: MO.getReg());
94 return;
95 }
96
97 if (MO.isImm()) {
98 printImm(MI, OpNo, STI, O);
99 return;
100 }
101
102 assert(MO.isExpr() && "Unknown operand kind in printOperand");
103 MAI.printExpr(O, *MO.getExpr());
104}
105
106void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
107 unsigned OpNo,
108 const MCSubtargetInfo &STI,
109 raw_ostream &O) {
110 // Do not print the numeric target address when symbolizing.
111 if (SymbolizeOperands)
112 return;
113
114 const MCOperand &MO = MI->getOperand(i: OpNo);
115 if (!MO.isImm())
116 return printOperand(MI, OpNo, STI, O);
117
118 if (PrintBranchImmAsAddress) {
119 uint64_t Target = Address + MO.getImm();
120 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
121 Target &= 0xffffffff;
122 markup(OS&: O, M: Markup::Target) << formatHex(Value: Target);
123 } else {
124 markup(OS&: O, M: Markup::Target) << formatImm(Value: MO.getImm());
125 }
126}
127
128void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
129 const MCSubtargetInfo &STI,
130 raw_ostream &O) {
131 unsigned Imm = MI->getOperand(i: OpNo).getImm();
132 auto Range = RISCVSysReg::lookupSysRegByEncoding(Encoding: Imm);
133 bool PreferFeatureSpecific = llvm::any_of(Range, P: [&](const auto &Reg) {
134 return !Reg.IsAltName && !Reg.IsDeprecatedName &&
135 Reg.FeaturesRequired.any() &&
136 Reg.haveRequiredFeatures(STI.getFeatureBits());
137 });
138 for (auto &Reg : Range) {
139 if (Reg.IsAltName || Reg.IsDeprecatedName)
140 continue;
141 if (Reg.haveRequiredFeatures(ActiveFeatures: STI.getFeatureBits()) &&
142 (!PreferFeatureSpecific || Reg.FeaturesRequired.any())) {
143 markup(OS&: O, M: Markup::Register) << RISCVSysReg::getSysRegStr(Reg.Name);
144 return;
145 }
146 }
147 markup(OS&: O, M: Markup::Register) << formatImm(Value: Imm);
148}
149
150void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
151 const MCSubtargetInfo &STI,
152 raw_ostream &O) {
153 unsigned FenceArg = MI->getOperand(i: OpNo).getImm();
154 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
155
156 if ((FenceArg & RISCVFenceField::I) != 0)
157 O << 'i';
158 if ((FenceArg & RISCVFenceField::O) != 0)
159 O << 'o';
160 if ((FenceArg & RISCVFenceField::R) != 0)
161 O << 'r';
162 if ((FenceArg & RISCVFenceField::W) != 0)
163 O << 'w';
164 if (FenceArg == 0)
165 O << "0";
166}
167
168void RISCVInstPrinter::printSMTVType(const MCInst *MI, unsigned OpNo,
169 const MCSubtargetInfo &STI,
170 raw_ostream &O) {
171 auto VType =
172 static_cast<XSMTVTypeMode::SMTVTypeMode>(MI->getOperand(i: OpNo).getImm());
173 assert(XSMTVTypeMode::isValidSMTVTypeMode(VType) &&
174 "SpacemiT's Integer Matrix only supports [i4|i8] mode");
175 O << ", " << XSMTVTypeMode::SMTVTypeModeToString(TypeMode: VType);
176}
177
178void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
179 const MCSubtargetInfo &STI, raw_ostream &O) {
180 auto FRMArg =
181 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
182 if (PrintAliases && !CLOpts.no_aliases &&
183 FRMArg == RISCVFPRndMode::RoundingMode::DYN)
184 return;
185 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
186}
187
188void RISCVInstPrinter::printFRMArgLegacy(const MCInst *MI, unsigned OpNo,
189 const MCSubtargetInfo &STI,
190 raw_ostream &O) {
191 auto FRMArg =
192 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
193 // Never print rounding mode if it's the default 'rne'. This ensures the
194 // output can still be parsed by older tools that erroneously failed to
195 // accept a rounding mode.
196 if (FRMArg == RISCVFPRndMode::RoundingMode::RNE)
197 return;
198 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
199}
200
201void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
202 const MCSubtargetInfo &STI,
203 raw_ostream &O) {
204 unsigned Imm = MI->getOperand(i: OpNo).getImm();
205 if (Imm == 1) {
206 markup(OS&: O, M: Markup::Immediate) << "min";
207 } else if (Imm == 30) {
208 markup(OS&: O, M: Markup::Immediate) << "inf";
209 } else if (Imm == 31) {
210 markup(OS&: O, M: Markup::Immediate) << "nan";
211 } else {
212 float FPVal = RISCVLoadFPImm::getFPImm(Imm);
213 // If the value is an integer, print a .0 fraction. Otherwise, use %g to
214 // which will not print trailing zeros and will use scientific notation
215 // if it is shorter than printing as a decimal. The smallest value requires
216 // 12 digits of precision including the decimal.
217 if (FPVal == (int)(FPVal))
218 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.1f", Vals: FPVal);
219 else
220 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.12g", Vals: FPVal);
221 }
222}
223
224void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
225 const MCSubtargetInfo &STI,
226 raw_ostream &O) {
227 const MCOperand &MO = MI->getOperand(i: OpNo);
228
229 assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
230 O << "(";
231 printRegName(O, Reg: MO.getReg());
232 O << ")";
233}
234
235void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
236 const MCSubtargetInfo &STI, raw_ostream &O) {
237 unsigned Imm = MI->getOperand(i: OpNo).getImm();
238 // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
239 // altfmt=1 without sew=8 or sew=16, or non-zero in bits 9 and above.
240 if (!RISCVVType::isValidVType(VType: Imm) || (Imm >> 9) != 0) {
241 O << formatImm(Value: Imm);
242 return;
243 }
244 // Print the text form.
245 RISCVVType::printVType(VType: Imm, OS&: O);
246}
247
248void RISCVInstPrinter::printXSfmmVType(const MCInst *MI, unsigned OpNo,
249 const MCSubtargetInfo &STI,
250 raw_ostream &O) {
251 unsigned Imm = MI->getOperand(i: OpNo).getImm();
252 assert(RISCVVType::isValidXSfmmVType(Imm));
253 unsigned SEW = RISCVVType::getSEW(VType: Imm);
254 O << "e" << SEW;
255 bool AltFmt = RISCVVType::isAltFmt(VType: Imm);
256 if (AltFmt)
257 O << "alt";
258 unsigned Widen = RISCVVType::getXSfmmWiden(VType: Imm);
259 O << ", w" << Widen;
260}
261
262// Print a Zcmp RList. If we are printing architectural register names rather
263// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
264// registers. Otherwise, we print "{ra, s0-s11}".
265void RISCVInstPrinter::printRegList(const MCInst *MI, unsigned OpNo,
266 const MCSubtargetInfo &STI, raw_ostream &O) {
267 unsigned Imm = MI->getOperand(i: OpNo).getImm();
268
269 assert(Imm >= RISCVZC::RLISTENCODE::RA &&
270 Imm <= RISCVZC::RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
271
272 O << "{";
273 printRegName(O, Reg: RISCV::X1);
274
275 if (Imm >= RISCVZC::RLISTENCODE::RA_S0) {
276 O << ", ";
277 printRegName(O, Reg: RISCV::X8);
278 }
279
280 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S1) {
281 O << '-';
282 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S1 || ArchRegNames)
283 printRegName(O, Reg: RISCV::X9);
284 }
285
286 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S2) {
287 if (ArchRegNames)
288 O << ", ";
289 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S2 || ArchRegNames)
290 printRegName(O, Reg: RISCV::X18);
291 }
292
293 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S3) {
294 if (ArchRegNames)
295 O << '-';
296 unsigned Offset = (Imm - RISCVZC::RLISTENCODE::RA_S0_S3);
297 // Encodings for S3-S9 are contiguous. There is no encoding for S10, so we
298 // must skip to S11(X27).
299 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S11)
300 ++Offset;
301 printRegName(O, Reg: RISCV::X19 + Offset);
302 }
303
304 O << "}";
305}
306
307void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
308 const MCSubtargetInfo &STI, raw_ostream &O) {
309 const MCOperand &OffsetMO = MI->getOperand(i: OpNo + 1);
310
311 assert(OffsetMO.isReg() && "printRegReg can only print register operands");
312 printRegName(O, Reg: OffsetMO.getReg());
313
314 O << "(";
315 const MCOperand &BaseMO = MI->getOperand(i: OpNo);
316 assert(BaseMO.isReg() && "printRegReg can only print register operands");
317 printRegName(O, Reg: BaseMO.getReg());
318 O << ")";
319}
320
321void RISCVInstPrinter::printStackAdj(const MCInst *MI, unsigned OpNo,
322 const MCSubtargetInfo &STI, raw_ostream &O,
323 bool Negate) {
324 int64_t Imm = MI->getOperand(i: OpNo).getImm();
325 bool IsRV64 = STI.hasFeature(Feature: RISCV::Feature64Bit);
326 int64_t StackAdj = 0;
327 auto RlistVal = MI->getOperand(i: 0).getImm();
328 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64);
329 StackAdj = Imm + Base;
330 assert((StackAdj >= Base && StackAdj <= Base + 48) &&
331 "Incorrect stack adjust");
332 if (Negate)
333 StackAdj = -StackAdj;
334
335 // RAII guard for ANSI color escape sequences
336 WithMarkup ScopedMarkup = markup(OS&: O, M: Markup::Immediate);
337 O << StackAdj;
338}
339
340void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
341 const MCSubtargetInfo &STI,
342 raw_ostream &O) {
343 const MCOperand &MO = MI->getOperand(i: OpNo);
344
345 assert(MO.isReg() && "printVMaskReg can only print register operands");
346 if (MO.getReg() == RISCV::NoRegister)
347 return;
348 O << ", ";
349 printRegName(O, Reg: MO.getReg());
350 O << ".t";
351}
352
353void RISCVInstPrinter::printVScaleReg(const MCInst *MI, unsigned OpNo,
354 const MCSubtargetInfo &STI,
355 raw_ostream &O) {
356 const MCOperand &MO = MI->getOperand(i: OpNo);
357
358 assert(MO.isReg() && "printVScaleReg can only print register operands");
359 O << ", ";
360 printRegName(O, Reg: MO.getReg());
361 O << ".scale";
362}
363
364void RISCVInstPrinter::printTileLambda(const MCInst *MI, unsigned OpNo,
365 const MCSubtargetInfo &STI,
366 raw_ostream &O) {
367 const MCOperand &MO = MI->getOperand(i: OpNo);
368
369 assert(MO.isImm() && "printTileLambda can only print immediate operands");
370 unsigned Lambda = MO.getImm();
371 if (Lambda == 0)
372 return;
373
374 assert(Lambda <= 7 && "Unexpected tile lambda encoding");
375 O << ", L" << (1U << (Lambda - 1));
376}
377
378void RISCVInstPrinter::printImm(const MCInst *MI, unsigned OpNo,
379 const MCSubtargetInfo &STI, raw_ostream &O) {
380 const MCOperand &Op = MI->getOperand(i: OpNo);
381 const unsigned Opcode = MI->getOpcode();
382 uint64_t Imm = Op.getImm();
383 if (STI.getTargetTriple().isOSBinFormatMachO() &&
384 (Opcode == RISCV::ANDI || Opcode == RISCV::ORI || Opcode == RISCV::XORI ||
385 Opcode == RISCV::C_ANDI || Opcode == RISCV::AUIPC ||
386 Opcode == RISCV::LUI)) {
387 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
388 Imm &= 0xffffffff;
389 markup(OS&: O, M: Markup::Immediate) << formatHex(Value: Imm);
390 } else
391 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Imm);
392}
393
394const char *RISCVInstPrinter::getRegisterName(const RISCVMCOptions &CLOpts,
395 MCRegister Reg) {
396 // When PrintAliases is enabled, and EmitX8AsFP is enabled, x8 will be printed
397 // as fp instead of s0. Note that these similar registers are not replaced:
398 // - X8_H: used for f16 register in zhinx
399 // - X8_W: used for f32 register in zfinx
400 // - X8_X9: used for GPR Pair
401 if (!ArchRegNames && (EmitX8AsFP || CLOpts.emit_x8_as_fp) && Reg == RISCV::X8)
402 return "fp";
403 return getRegisterName(Reg, AltIdx: ArchRegNames ? RISCV::NoRegAltName
404 : RISCV::ABIRegAltName);
405}
406