1//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an RISC-V MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVInstPrinter.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCAsmInfo.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstPrinter.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MC/MCSymbol.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ErrorHandling.h"
25using namespace llvm;
26
27#define DEBUG_TYPE "asm-printer"
28
29// Include the auto-generated portion of the assembly writer.
30#define PRINT_ALIAS_INSTR
31#include "RISCVGenAsmWriter.inc"
32
33static cl::opt<bool>
34 NoAliases("riscv-no-aliases",
35 cl::desc("Disable the emission of assembler pseudo instructions"),
36 cl::init(Val: false), cl::Hidden);
37
38static cl::opt<bool> EmitX8AsFP("riscv-emit-x8-as-fp",
39 cl::desc("Emit x8 as fp instead of s0"),
40 cl::init(Val: false), cl::Hidden);
41
42// Print architectural register names rather than the ABI names (such as x2
43// instead of sp).
44// TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
45// member.
46static bool ArchRegNames;
47
48// The command-line flags above are used by llvm-mc and llc. They can be used by
49// `llvm-objdump`, but we override their values here to handle options passed to
50// `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
51// be an easier way to allow these options in all these tools, without doing it
52// this way.
53bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
54 if (Opt == "no-aliases") {
55 PrintAliases = false;
56 return true;
57 }
58 if (Opt == "numeric") {
59 ArchRegNames = true;
60 return true;
61 }
62 if (Opt == "emit-x8-as-fp") {
63 if (!ArchRegNames)
64 EmitX8AsFP = true;
65 return true;
66 }
67
68 return false;
69}
70
71void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
72 StringRef Annot, const MCSubtargetInfo &STI,
73 raw_ostream &O) {
74 bool Res = false;
75 const MCInst *NewMI = MI;
76 MCInst UncompressedMI;
77 if (PrintAliases && !NoAliases)
78 Res = RISCVRVC::uncompress(OutInst&: UncompressedMI, MI: *MI, STI);
79 if (Res)
80 NewMI = &UncompressedMI;
81 if (!PrintAliases || NoAliases || !printAliasInstr(MI: NewMI, Address, STI, OS&: O))
82 printInstruction(MI: NewMI, Address, STI, O);
83 printAnnotation(OS&: O, Annot);
84}
85
86void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) {
87 markup(OS&: O, M: Markup::Register) << getRegisterName(Reg);
88}
89
90void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
91 const MCSubtargetInfo &STI,
92 raw_ostream &O) {
93 const MCOperand &MO = MI->getOperand(i: OpNo);
94
95 if (MO.isReg()) {
96 printRegName(O, Reg: MO.getReg());
97 return;
98 }
99
100 if (MO.isImm()) {
101 printImm(MI, OpNo, STI, O);
102 return;
103 }
104
105 assert(MO.isExpr() && "Unknown operand kind in printOperand");
106 MAI.printExpr(O, *MO.getExpr());
107}
108
109void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
110 unsigned OpNo,
111 const MCSubtargetInfo &STI,
112 raw_ostream &O) {
113 // Do not print the numeric target address when symbolizing.
114 if (SymbolizeOperands)
115 return;
116
117 const MCOperand &MO = MI->getOperand(i: OpNo);
118 if (!MO.isImm())
119 return printOperand(MI, OpNo, STI, O);
120
121 if (PrintBranchImmAsAddress) {
122 uint64_t Target = Address + MO.getImm();
123 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
124 Target &= 0xffffffff;
125 markup(OS&: O, M: Markup::Target) << formatHex(Value: Target);
126 } else {
127 markup(OS&: O, M: Markup::Target) << formatImm(Value: MO.getImm());
128 }
129}
130
131void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
132 const MCSubtargetInfo &STI,
133 raw_ostream &O) {
134 unsigned Imm = MI->getOperand(i: OpNo).getImm();
135 auto Range = RISCVSysReg::lookupSysRegByEncoding(Encoding: Imm);
136 for (auto &Reg : Range) {
137 if (Reg.IsAltName || Reg.IsDeprecatedName)
138 continue;
139 if (Reg.haveRequiredFeatures(ActiveFeatures: STI.getFeatureBits())) {
140 markup(OS&: O, M: Markup::Register) << RISCVSysReg::getSysRegStr(Reg.Name);
141 return;
142 }
143 }
144 markup(OS&: O, M: Markup::Register) << formatImm(Value: Imm);
145}
146
147void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
148 const MCSubtargetInfo &STI,
149 raw_ostream &O) {
150 unsigned FenceArg = MI->getOperand(i: OpNo).getImm();
151 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
152
153 if ((FenceArg & RISCVFenceField::I) != 0)
154 O << 'i';
155 if ((FenceArg & RISCVFenceField::O) != 0)
156 O << 'o';
157 if ((FenceArg & RISCVFenceField::R) != 0)
158 O << 'r';
159 if ((FenceArg & RISCVFenceField::W) != 0)
160 O << 'w';
161 if (FenceArg == 0)
162 O << "0";
163}
164
165void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
166 const MCSubtargetInfo &STI, raw_ostream &O) {
167 auto FRMArg =
168 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
169 if (PrintAliases && !NoAliases && FRMArg == RISCVFPRndMode::RoundingMode::DYN)
170 return;
171 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
172}
173
174void RISCVInstPrinter::printFRMArgLegacy(const MCInst *MI, unsigned OpNo,
175 const MCSubtargetInfo &STI,
176 raw_ostream &O) {
177 auto FRMArg =
178 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
179 // Never print rounding mode if it's the default 'rne'. This ensures the
180 // output can still be parsed by older tools that erroneously failed to
181 // accept a rounding mode.
182 if (FRMArg == RISCVFPRndMode::RoundingMode::RNE)
183 return;
184 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
185}
186
187void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
188 const MCSubtargetInfo &STI,
189 raw_ostream &O) {
190 unsigned Imm = MI->getOperand(i: OpNo).getImm();
191 if (Imm == 1) {
192 markup(OS&: O, M: Markup::Immediate) << "min";
193 } else if (Imm == 30) {
194 markup(OS&: O, M: Markup::Immediate) << "inf";
195 } else if (Imm == 31) {
196 markup(OS&: O, M: Markup::Immediate) << "nan";
197 } else {
198 float FPVal = RISCVLoadFPImm::getFPImm(Imm);
199 // If the value is an integer, print a .0 fraction. Otherwise, use %g to
200 // which will not print trailing zeros and will use scientific notation
201 // if it is shorter than printing as a decimal. The smallest value requires
202 // 12 digits of precision including the decimal.
203 if (FPVal == (int)(FPVal))
204 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.1f", Vals: FPVal);
205 else
206 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.12g", Vals: FPVal);
207 }
208}
209
210void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
211 const MCSubtargetInfo &STI,
212 raw_ostream &O) {
213 const MCOperand &MO = MI->getOperand(i: OpNo);
214
215 assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
216 O << "(";
217 printRegName(O, Reg: MO.getReg());
218 O << ")";
219}
220
221void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
222 const MCSubtargetInfo &STI, raw_ostream &O) {
223 unsigned Imm = MI->getOperand(i: OpNo).getImm();
224 // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
225 // altfmt=1 without sew=8 or sew=16, or non-zero in bits 9 and above.
226 if (!RISCVVType::isValidVType(VType: Imm) || (Imm >> 9) != 0) {
227 O << formatImm(Value: Imm);
228 return;
229 }
230 // Print the text form.
231 RISCVVType::printVType(VType: Imm, OS&: O);
232}
233
234void RISCVInstPrinter::printXSfmmVType(const MCInst *MI, unsigned OpNo,
235 const MCSubtargetInfo &STI,
236 raw_ostream &O) {
237 unsigned Imm = MI->getOperand(i: OpNo).getImm();
238 assert(RISCVVType::isValidXSfmmVType(Imm));
239 unsigned SEW = RISCVVType::getSEW(VType: Imm);
240 O << "e" << SEW;
241 bool AltFmt = RISCVVType::isAltFmt(VType: Imm);
242 if (AltFmt)
243 O << "alt";
244 unsigned Widen = RISCVVType::getXSfmmWiden(VType: Imm);
245 O << ", w" << Widen;
246}
247
248// Print a Zcmp RList. If we are printing architectural register names rather
249// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
250// registers. Otherwise, we print "{ra, s0-s11}".
251void RISCVInstPrinter::printRegList(const MCInst *MI, unsigned OpNo,
252 const MCSubtargetInfo &STI, raw_ostream &O) {
253 unsigned Imm = MI->getOperand(i: OpNo).getImm();
254
255 assert(Imm >= RISCVZC::RLISTENCODE::RA &&
256 Imm <= RISCVZC::RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
257
258 O << "{";
259 printRegName(O, Reg: RISCV::X1);
260
261 if (Imm >= RISCVZC::RLISTENCODE::RA_S0) {
262 O << ", ";
263 printRegName(O, Reg: RISCV::X8);
264 }
265
266 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S1) {
267 O << '-';
268 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S1 || ArchRegNames)
269 printRegName(O, Reg: RISCV::X9);
270 }
271
272 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S2) {
273 if (ArchRegNames)
274 O << ", ";
275 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S2 || ArchRegNames)
276 printRegName(O, Reg: RISCV::X18);
277 }
278
279 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S3) {
280 if (ArchRegNames)
281 O << '-';
282 unsigned Offset = (Imm - RISCVZC::RLISTENCODE::RA_S0_S3);
283 // Encodings for S3-S9 are contiguous. There is no encoding for S10, so we
284 // must skip to S11(X27).
285 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S11)
286 ++Offset;
287 printRegName(O, Reg: RISCV::X19 + Offset);
288 }
289
290 O << "}";
291}
292
293void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
294 const MCSubtargetInfo &STI, raw_ostream &O) {
295 const MCOperand &OffsetMO = MI->getOperand(i: OpNo + 1);
296
297 assert(OffsetMO.isReg() && "printRegReg can only print register operands");
298 printRegName(O, Reg: OffsetMO.getReg());
299
300 O << "(";
301 const MCOperand &BaseMO = MI->getOperand(i: OpNo);
302 assert(BaseMO.isReg() && "printRegReg can only print register operands");
303 printRegName(O, Reg: BaseMO.getReg());
304 O << ")";
305}
306
307void RISCVInstPrinter::printStackAdj(const MCInst *MI, unsigned OpNo,
308 const MCSubtargetInfo &STI, raw_ostream &O,
309 bool Negate) {
310 int64_t Imm = MI->getOperand(i: OpNo).getImm();
311 bool IsRV64 = STI.hasFeature(Feature: RISCV::Feature64Bit);
312 int64_t StackAdj = 0;
313 auto RlistVal = MI->getOperand(i: 0).getImm();
314 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64);
315 StackAdj = Imm + Base;
316 assert((StackAdj >= Base && StackAdj <= Base + 48) &&
317 "Incorrect stack adjust");
318 if (Negate)
319 StackAdj = -StackAdj;
320
321 // RAII guard for ANSI color escape sequences
322 WithMarkup ScopedMarkup = markup(OS&: O, M: Markup::Immediate);
323 O << StackAdj;
324}
325
326void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
327 const MCSubtargetInfo &STI,
328 raw_ostream &O) {
329 const MCOperand &MO = MI->getOperand(i: OpNo);
330
331 assert(MO.isReg() && "printVMaskReg can only print register operands");
332 if (MO.getReg() == RISCV::NoRegister)
333 return;
334 O << ", ";
335 printRegName(O, Reg: MO.getReg());
336 O << ".t";
337}
338
339void RISCVInstPrinter::printVScaleReg(const MCInst *MI, unsigned OpNo,
340 const MCSubtargetInfo &STI,
341 raw_ostream &O) {
342 const MCOperand &MO = MI->getOperand(i: OpNo);
343
344 assert(MO.isReg() && "printVScaleReg can only print register operands");
345 O << ", ";
346 printRegName(O, Reg: MO.getReg());
347 O << ".scale";
348}
349
350void RISCVInstPrinter::printTileLambda(const MCInst *MI, unsigned OpNo,
351 const MCSubtargetInfo &STI,
352 raw_ostream &O) {
353 const MCOperand &MO = MI->getOperand(i: OpNo);
354
355 assert(MO.isImm() && "printTileLambda can only print immediate operands");
356 unsigned Lambda = MO.getImm();
357 if (Lambda == 0)
358 return;
359
360 assert(Lambda <= 7 && "Unexpected tile lambda encoding");
361 O << ", L" << (1U << (Lambda - 1));
362}
363
364void RISCVInstPrinter::printImm(const MCInst *MI, unsigned OpNo,
365 const MCSubtargetInfo &STI, raw_ostream &O) {
366 const MCOperand &Op = MI->getOperand(i: OpNo);
367 const unsigned Opcode = MI->getOpcode();
368 uint64_t Imm = Op.getImm();
369 if (STI.getTargetTriple().isOSBinFormatMachO() &&
370 (Opcode == RISCV::ANDI || Opcode == RISCV::ORI || Opcode == RISCV::XORI ||
371 Opcode == RISCV::C_ANDI || Opcode == RISCV::AUIPC ||
372 Opcode == RISCV::LUI)) {
373 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
374 Imm &= 0xffffffff;
375 markup(OS&: O, M: Markup::Immediate) << formatHex(Value: Imm);
376 } else
377 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Imm);
378}
379
380const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
381 // When PrintAliases is enabled, and EmitX8AsFP is enabled, x8 will be printed
382 // as fp instead of s0. Note that these similar registers are not replaced:
383 // - X8_H: used for f16 register in zhinx
384 // - X8_W: used for f32 register in zfinx
385 // - X8_X9: used for GPR Pair
386 if (!ArchRegNames && EmitX8AsFP && Reg == RISCV::X8)
387 return "fp";
388 return getRegisterName(Reg, AltIdx: ArchRegNames ? RISCV::NoRegAltName
389 : RISCV::ABIRegAltName);
390}
391