1//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an RISC-V MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVInstPrinter.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCAsmInfo.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstPrinter.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MC/MCSymbol.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ErrorHandling.h"
25using namespace llvm;
26
27#define DEBUG_TYPE "asm-printer"
28
29// Include the auto-generated portion of the assembly writer.
30#define PRINT_ALIAS_INSTR
31#include "RISCVGenAsmWriter.inc"
32
33static cl::opt<bool>
34 NoAliases("riscv-no-aliases",
35 cl::desc("Disable the emission of assembler pseudo instructions"),
36 cl::init(Val: false), cl::Hidden);
37
38static cl::opt<bool> EmitX8AsFP("riscv-emit-x8-as-fp",
39 cl::desc("Emit x8 as fp instead of s0"),
40 cl::init(Val: false), cl::Hidden);
41
42// Print architectural register names rather than the ABI names (such as x2
43// instead of sp).
44// TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
45// member.
46static bool ArchRegNames;
47
48// The command-line flags above are used by llvm-mc and llc. They can be used by
49// `llvm-objdump`, but we override their values here to handle options passed to
50// `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
51// be an easier way to allow these options in all these tools, without doing it
52// this way.
53bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
54 if (Opt == "no-aliases") {
55 PrintAliases = false;
56 return true;
57 }
58 if (Opt == "numeric") {
59 ArchRegNames = true;
60 return true;
61 }
62 if (Opt == "emit-x8-as-fp") {
63 if (!ArchRegNames)
64 EmitX8AsFP = true;
65 return true;
66 }
67
68 return false;
69}
70
71void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
72 StringRef Annot, const MCSubtargetInfo &STI,
73 raw_ostream &O) {
74 bool Res = false;
75 const MCInst *NewMI = MI;
76 MCInst UncompressedMI;
77 if (PrintAliases && !NoAliases)
78 Res = RISCVRVC::uncompress(OutInst&: UncompressedMI, MI: *MI, STI);
79 if (Res)
80 NewMI = &UncompressedMI;
81 if (!PrintAliases || NoAliases || !printAliasInstr(MI: NewMI, Address, STI, OS&: O))
82 printInstruction(MI: NewMI, Address, STI, O);
83 printAnnotation(OS&: O, Annot);
84}
85
86void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) {
87 markup(OS&: O, M: Markup::Register) << getRegisterName(Reg);
88}
89
90void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
91 const MCSubtargetInfo &STI,
92 raw_ostream &O) {
93 const MCOperand &MO = MI->getOperand(i: OpNo);
94
95 if (MO.isReg()) {
96 printRegName(O, Reg: MO.getReg());
97 return;
98 }
99
100 if (MO.isImm()) {
101 printImm(MI, OpNo, STI, O);
102 return;
103 }
104
105 assert(MO.isExpr() && "Unknown operand kind in printOperand");
106 MAI.printExpr(O, *MO.getExpr());
107}
108
109void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
110 unsigned OpNo,
111 const MCSubtargetInfo &STI,
112 raw_ostream &O) {
113 // Do not print the numeric target address when symbolizing.
114 if (SymbolizeOperands)
115 return;
116
117 const MCOperand &MO = MI->getOperand(i: OpNo);
118 if (!MO.isImm())
119 return printOperand(MI, OpNo, STI, O);
120
121 if (PrintBranchImmAsAddress) {
122 uint64_t Target = Address + MO.getImm();
123 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
124 Target &= 0xffffffff;
125 markup(OS&: O, M: Markup::Target) << formatHex(Value: Target);
126 } else {
127 markup(OS&: O, M: Markup::Target) << formatImm(Value: MO.getImm());
128 }
129}
130
131void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
132 const MCSubtargetInfo &STI,
133 raw_ostream &O) {
134 unsigned Imm = MI->getOperand(i: OpNo).getImm();
135 auto Range = RISCVSysReg::lookupSysRegByEncoding(Encoding: Imm);
136 bool PreferFeatureSpecific = llvm::any_of(Range, P: [&](const auto &Reg) {
137 return !Reg.IsAltName && !Reg.IsDeprecatedName &&
138 Reg.FeaturesRequired.any() &&
139 Reg.haveRequiredFeatures(STI.getFeatureBits());
140 });
141 for (auto &Reg : Range) {
142 if (Reg.IsAltName || Reg.IsDeprecatedName)
143 continue;
144 if (Reg.haveRequiredFeatures(ActiveFeatures: STI.getFeatureBits()) &&
145 (!PreferFeatureSpecific || Reg.FeaturesRequired.any())) {
146 markup(OS&: O, M: Markup::Register) << RISCVSysReg::getSysRegStr(Reg.Name);
147 return;
148 }
149 }
150 markup(OS&: O, M: Markup::Register) << formatImm(Value: Imm);
151}
152
153void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
154 const MCSubtargetInfo &STI,
155 raw_ostream &O) {
156 unsigned FenceArg = MI->getOperand(i: OpNo).getImm();
157 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
158
159 if ((FenceArg & RISCVFenceField::I) != 0)
160 O << 'i';
161 if ((FenceArg & RISCVFenceField::O) != 0)
162 O << 'o';
163 if ((FenceArg & RISCVFenceField::R) != 0)
164 O << 'r';
165 if ((FenceArg & RISCVFenceField::W) != 0)
166 O << 'w';
167 if (FenceArg == 0)
168 O << "0";
169}
170
171void RISCVInstPrinter::printSMTVType(const MCInst *MI, unsigned OpNo,
172 const MCSubtargetInfo &STI,
173 raw_ostream &O) {
174 auto VType =
175 static_cast<XSMTVTypeMode::SMTVTypeMode>(MI->getOperand(i: OpNo).getImm());
176 assert(XSMTVTypeMode::isValidSMTVTypeMode(VType) &&
177 "SpacemiT's Integer Matrix only supports [i4|i8] mode");
178 O << ", " << XSMTVTypeMode::SMTVTypeModeToString(TypeMode: VType);
179}
180
181void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
182 const MCSubtargetInfo &STI, raw_ostream &O) {
183 auto FRMArg =
184 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
185 if (PrintAliases && !NoAliases && FRMArg == RISCVFPRndMode::RoundingMode::DYN)
186 return;
187 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
188}
189
190void RISCVInstPrinter::printFRMArgLegacy(const MCInst *MI, unsigned OpNo,
191 const MCSubtargetInfo &STI,
192 raw_ostream &O) {
193 auto FRMArg =
194 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
195 // Never print rounding mode if it's the default 'rne'. This ensures the
196 // output can still be parsed by older tools that erroneously failed to
197 // accept a rounding mode.
198 if (FRMArg == RISCVFPRndMode::RoundingMode::RNE)
199 return;
200 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
201}
202
203void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
204 const MCSubtargetInfo &STI,
205 raw_ostream &O) {
206 unsigned Imm = MI->getOperand(i: OpNo).getImm();
207 if (Imm == 1) {
208 markup(OS&: O, M: Markup::Immediate) << "min";
209 } else if (Imm == 30) {
210 markup(OS&: O, M: Markup::Immediate) << "inf";
211 } else if (Imm == 31) {
212 markup(OS&: O, M: Markup::Immediate) << "nan";
213 } else {
214 float FPVal = RISCVLoadFPImm::getFPImm(Imm);
215 // If the value is an integer, print a .0 fraction. Otherwise, use %g to
216 // which will not print trailing zeros and will use scientific notation
217 // if it is shorter than printing as a decimal. The smallest value requires
218 // 12 digits of precision including the decimal.
219 if (FPVal == (int)(FPVal))
220 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.1f", Vals: FPVal);
221 else
222 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.12g", Vals: FPVal);
223 }
224}
225
226void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
227 const MCSubtargetInfo &STI,
228 raw_ostream &O) {
229 const MCOperand &MO = MI->getOperand(i: OpNo);
230
231 assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
232 O << "(";
233 printRegName(O, Reg: MO.getReg());
234 O << ")";
235}
236
237void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
238 const MCSubtargetInfo &STI, raw_ostream &O) {
239 unsigned Imm = MI->getOperand(i: OpNo).getImm();
240 // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
241 // altfmt=1 without sew=8 or sew=16, or non-zero in bits 9 and above.
242 if (!RISCVVType::isValidVType(VType: Imm) || (Imm >> 9) != 0) {
243 O << formatImm(Value: Imm);
244 return;
245 }
246 // Print the text form.
247 RISCVVType::printVType(VType: Imm, OS&: O);
248}
249
250void RISCVInstPrinter::printXSfmmVType(const MCInst *MI, unsigned OpNo,
251 const MCSubtargetInfo &STI,
252 raw_ostream &O) {
253 unsigned Imm = MI->getOperand(i: OpNo).getImm();
254 assert(RISCVVType::isValidXSfmmVType(Imm));
255 unsigned SEW = RISCVVType::getSEW(VType: Imm);
256 O << "e" << SEW;
257 bool AltFmt = RISCVVType::isAltFmt(VType: Imm);
258 if (AltFmt)
259 O << "alt";
260 unsigned Widen = RISCVVType::getXSfmmWiden(VType: Imm);
261 O << ", w" << Widen;
262}
263
264// Print a Zcmp RList. If we are printing architectural register names rather
265// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
266// registers. Otherwise, we print "{ra, s0-s11}".
267void RISCVInstPrinter::printRegList(const MCInst *MI, unsigned OpNo,
268 const MCSubtargetInfo &STI, raw_ostream &O) {
269 unsigned Imm = MI->getOperand(i: OpNo).getImm();
270
271 assert(Imm >= RISCVZC::RLISTENCODE::RA &&
272 Imm <= RISCVZC::RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
273
274 O << "{";
275 printRegName(O, Reg: RISCV::X1);
276
277 if (Imm >= RISCVZC::RLISTENCODE::RA_S0) {
278 O << ", ";
279 printRegName(O, Reg: RISCV::X8);
280 }
281
282 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S1) {
283 O << '-';
284 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S1 || ArchRegNames)
285 printRegName(O, Reg: RISCV::X9);
286 }
287
288 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S2) {
289 if (ArchRegNames)
290 O << ", ";
291 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S2 || ArchRegNames)
292 printRegName(O, Reg: RISCV::X18);
293 }
294
295 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S3) {
296 if (ArchRegNames)
297 O << '-';
298 unsigned Offset = (Imm - RISCVZC::RLISTENCODE::RA_S0_S3);
299 // Encodings for S3-S9 are contiguous. There is no encoding for S10, so we
300 // must skip to S11(X27).
301 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S11)
302 ++Offset;
303 printRegName(O, Reg: RISCV::X19 + Offset);
304 }
305
306 O << "}";
307}
308
309void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
310 const MCSubtargetInfo &STI, raw_ostream &O) {
311 const MCOperand &OffsetMO = MI->getOperand(i: OpNo + 1);
312
313 assert(OffsetMO.isReg() && "printRegReg can only print register operands");
314 printRegName(O, Reg: OffsetMO.getReg());
315
316 O << "(";
317 const MCOperand &BaseMO = MI->getOperand(i: OpNo);
318 assert(BaseMO.isReg() && "printRegReg can only print register operands");
319 printRegName(O, Reg: BaseMO.getReg());
320 O << ")";
321}
322
323void RISCVInstPrinter::printStackAdj(const MCInst *MI, unsigned OpNo,
324 const MCSubtargetInfo &STI, raw_ostream &O,
325 bool Negate) {
326 int64_t Imm = MI->getOperand(i: OpNo).getImm();
327 bool IsRV64 = STI.hasFeature(Feature: RISCV::Feature64Bit);
328 int64_t StackAdj = 0;
329 auto RlistVal = MI->getOperand(i: 0).getImm();
330 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64);
331 StackAdj = Imm + Base;
332 assert((StackAdj >= Base && StackAdj <= Base + 48) &&
333 "Incorrect stack adjust");
334 if (Negate)
335 StackAdj = -StackAdj;
336
337 // RAII guard for ANSI color escape sequences
338 WithMarkup ScopedMarkup = markup(OS&: O, M: Markup::Immediate);
339 O << StackAdj;
340}
341
342void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
343 const MCSubtargetInfo &STI,
344 raw_ostream &O) {
345 const MCOperand &MO = MI->getOperand(i: OpNo);
346
347 assert(MO.isReg() && "printVMaskReg can only print register operands");
348 if (MO.getReg() == RISCV::NoRegister)
349 return;
350 O << ", ";
351 printRegName(O, Reg: MO.getReg());
352 O << ".t";
353}
354
355void RISCVInstPrinter::printVScaleReg(const MCInst *MI, unsigned OpNo,
356 const MCSubtargetInfo &STI,
357 raw_ostream &O) {
358 const MCOperand &MO = MI->getOperand(i: OpNo);
359
360 assert(MO.isReg() && "printVScaleReg can only print register operands");
361 O << ", ";
362 printRegName(O, Reg: MO.getReg());
363 O << ".scale";
364}
365
366void RISCVInstPrinter::printTileLambda(const MCInst *MI, unsigned OpNo,
367 const MCSubtargetInfo &STI,
368 raw_ostream &O) {
369 const MCOperand &MO = MI->getOperand(i: OpNo);
370
371 assert(MO.isImm() && "printTileLambda can only print immediate operands");
372 unsigned Lambda = MO.getImm();
373 if (Lambda == 0)
374 return;
375
376 assert(Lambda <= 7 && "Unexpected tile lambda encoding");
377 O << ", L" << (1U << (Lambda - 1));
378}
379
380void RISCVInstPrinter::printImm(const MCInst *MI, unsigned OpNo,
381 const MCSubtargetInfo &STI, raw_ostream &O) {
382 const MCOperand &Op = MI->getOperand(i: OpNo);
383 const unsigned Opcode = MI->getOpcode();
384 uint64_t Imm = Op.getImm();
385 if (STI.getTargetTriple().isOSBinFormatMachO() &&
386 (Opcode == RISCV::ANDI || Opcode == RISCV::ORI || Opcode == RISCV::XORI ||
387 Opcode == RISCV::C_ANDI || Opcode == RISCV::AUIPC ||
388 Opcode == RISCV::LUI)) {
389 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
390 Imm &= 0xffffffff;
391 markup(OS&: O, M: Markup::Immediate) << formatHex(Value: Imm);
392 } else
393 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Imm);
394}
395
396const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
397 // When PrintAliases is enabled, and EmitX8AsFP is enabled, x8 will be printed
398 // as fp instead of s0. Note that these similar registers are not replaced:
399 // - X8_H: used for f16 register in zhinx
400 // - X8_W: used for f32 register in zfinx
401 // - X8_X9: used for GPR Pair
402 if (!ArchRegNames && EmitX8AsFP && Reg == RISCV::X8)
403 return "fp";
404 return getRegisterName(Reg, AltIdx: ArchRegNames ? RISCV::NoRegAltName
405 : RISCV::ABIRegAltName);
406}
407