1//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an RISC-V MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVInstPrinter.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCAsmInfo.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstPrinter.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MC/MCSymbol.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ErrorHandling.h"
25using namespace llvm;
26
27#define DEBUG_TYPE "asm-printer"
28
29// Include the auto-generated portion of the assembly writer.
30#define PRINT_ALIAS_INSTR
31#include "RISCVGenAsmWriter.inc"
32
33static cl::opt<bool>
34 NoAliases("riscv-no-aliases",
35 cl::desc("Disable the emission of assembler pseudo instructions"),
36 cl::init(Val: false), cl::Hidden);
37
38static cl::opt<bool> EmitX8AsFP("riscv-emit-x8-as-fp",
39 cl::desc("Emit x8 as fp instead of s0"),
40 cl::init(Val: false), cl::Hidden);
41
42// Print architectural register names rather than the ABI names (such as x2
43// instead of sp).
44// TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
45// member.
46static bool ArchRegNames;
47
48// The command-line flags above are used by llvm-mc and llc. They can be used by
49// `llvm-objdump`, but we override their values here to handle options passed to
50// `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
51// be an easier way to allow these options in all these tools, without doing it
52// this way.
53bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
54 if (Opt == "no-aliases") {
55 PrintAliases = false;
56 return true;
57 }
58 if (Opt == "numeric") {
59 ArchRegNames = true;
60 return true;
61 }
62 if (Opt == "emit-x8-as-fp") {
63 if (!ArchRegNames)
64 EmitX8AsFP = true;
65 return true;
66 }
67
68 return false;
69}
70
71void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
72 StringRef Annot, const MCSubtargetInfo &STI,
73 raw_ostream &O) {
74 bool Res = false;
75 const MCInst *NewMI = MI;
76 MCInst UncompressedMI;
77 if (PrintAliases && !NoAliases)
78 Res = RISCVRVC::uncompress(OutInst&: UncompressedMI, MI: *MI, STI);
79 if (Res)
80 NewMI = &UncompressedMI;
81 if (!PrintAliases || NoAliases || !printAliasInstr(MI: NewMI, Address, STI, OS&: O))
82 printInstruction(MI: NewMI, Address, STI, O);
83 printAnnotation(OS&: O, Annot);
84}
85
86void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) {
87 markup(OS&: O, M: Markup::Register) << getRegisterName(Reg);
88}
89
90void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
91 const MCSubtargetInfo &STI,
92 raw_ostream &O) {
93 const MCOperand &MO = MI->getOperand(i: OpNo);
94
95 if (MO.isReg()) {
96 printRegName(O, Reg: MO.getReg());
97 return;
98 }
99
100 if (MO.isImm()) {
101 printImm(MI, OpNo, STI, O);
102 return;
103 }
104
105 assert(MO.isExpr() && "Unknown operand kind in printOperand");
106 MAI.printExpr(O, *MO.getExpr());
107}
108
109void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
110 unsigned OpNo,
111 const MCSubtargetInfo &STI,
112 raw_ostream &O) {
113 // Do not print the numeric target address when symbolizing.
114 if (SymbolizeOperands)
115 return;
116
117 const MCOperand &MO = MI->getOperand(i: OpNo);
118 if (!MO.isImm())
119 return printOperand(MI, OpNo, STI, O);
120
121 if (PrintBranchImmAsAddress) {
122 uint64_t Target = Address + MO.getImm();
123 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
124 Target &= 0xffffffff;
125 markup(OS&: O, M: Markup::Target) << formatHex(Value: Target);
126 } else {
127 markup(OS&: O, M: Markup::Target) << formatImm(Value: MO.getImm());
128 }
129}
130
131void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
132 const MCSubtargetInfo &STI,
133 raw_ostream &O) {
134 unsigned Imm = MI->getOperand(i: OpNo).getImm();
135 auto Range = RISCVSysReg::lookupSysRegByEncoding(Encoding: Imm);
136 for (auto &Reg : Range) {
137 if (Reg.IsAltName || Reg.IsDeprecatedName)
138 continue;
139 if (Reg.haveRequiredFeatures(ActiveFeatures: STI.getFeatureBits())) {
140 markup(OS&: O, M: Markup::Register) << RISCVSysReg::getSysRegStr(Reg.Name);
141 return;
142 }
143 }
144 markup(OS&: O, M: Markup::Register) << formatImm(Value: Imm);
145}
146
147void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
148 const MCSubtargetInfo &STI,
149 raw_ostream &O) {
150 unsigned FenceArg = MI->getOperand(i: OpNo).getImm();
151 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
152
153 if ((FenceArg & RISCVFenceField::I) != 0)
154 O << 'i';
155 if ((FenceArg & RISCVFenceField::O) != 0)
156 O << 'o';
157 if ((FenceArg & RISCVFenceField::R) != 0)
158 O << 'r';
159 if ((FenceArg & RISCVFenceField::W) != 0)
160 O << 'w';
161 if (FenceArg == 0)
162 O << "0";
163}
164
165void RISCVInstPrinter::printSMTVType(const MCInst *MI, unsigned OpNo,
166 const MCSubtargetInfo &STI,
167 raw_ostream &O) {
168 auto VType =
169 static_cast<XSMTVTypeMode::SMTVTypeMode>(MI->getOperand(i: OpNo).getImm());
170 assert(XSMTVTypeMode::isValidSMTVTypeMode(VType) &&
171 "SpacemiT's Integer Matrix only supports [i4|i8] mode");
172 O << ", " << XSMTVTypeMode::SMTVTypeModeToString(TypeMode: VType);
173}
174
175void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
176 const MCSubtargetInfo &STI, raw_ostream &O) {
177 auto FRMArg =
178 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
179 if (PrintAliases && !NoAliases && FRMArg == RISCVFPRndMode::RoundingMode::DYN)
180 return;
181 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
182}
183
184void RISCVInstPrinter::printFRMArgLegacy(const MCInst *MI, unsigned OpNo,
185 const MCSubtargetInfo &STI,
186 raw_ostream &O) {
187 auto FRMArg =
188 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(i: OpNo).getImm());
189 // Never print rounding mode if it's the default 'rne'. This ensures the
190 // output can still be parsed by older tools that erroneously failed to
191 // accept a rounding mode.
192 if (FRMArg == RISCVFPRndMode::RoundingMode::RNE)
193 return;
194 O << ", " << RISCVFPRndMode::roundingModeToString(RndMode: FRMArg);
195}
196
197void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
198 const MCSubtargetInfo &STI,
199 raw_ostream &O) {
200 unsigned Imm = MI->getOperand(i: OpNo).getImm();
201 if (Imm == 1) {
202 markup(OS&: O, M: Markup::Immediate) << "min";
203 } else if (Imm == 30) {
204 markup(OS&: O, M: Markup::Immediate) << "inf";
205 } else if (Imm == 31) {
206 markup(OS&: O, M: Markup::Immediate) << "nan";
207 } else {
208 float FPVal = RISCVLoadFPImm::getFPImm(Imm);
209 // If the value is an integer, print a .0 fraction. Otherwise, use %g to
210 // which will not print trailing zeros and will use scientific notation
211 // if it is shorter than printing as a decimal. The smallest value requires
212 // 12 digits of precision including the decimal.
213 if (FPVal == (int)(FPVal))
214 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.1f", Vals: FPVal);
215 else
216 markup(OS&: O, M: Markup::Immediate) << format(Fmt: "%.12g", Vals: FPVal);
217 }
218}
219
220void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
221 const MCSubtargetInfo &STI,
222 raw_ostream &O) {
223 const MCOperand &MO = MI->getOperand(i: OpNo);
224
225 assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
226 O << "(";
227 printRegName(O, Reg: MO.getReg());
228 O << ")";
229}
230
231void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
232 const MCSubtargetInfo &STI, raw_ostream &O) {
233 unsigned Imm = MI->getOperand(i: OpNo).getImm();
234 // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
235 // altfmt=1 without sew=8 or sew=16, or non-zero in bits 9 and above.
236 if (!RISCVVType::isValidVType(VType: Imm) || (Imm >> 9) != 0) {
237 O << formatImm(Value: Imm);
238 return;
239 }
240 // Print the text form.
241 RISCVVType::printVType(VType: Imm, OS&: O);
242}
243
244void RISCVInstPrinter::printXSfmmVType(const MCInst *MI, unsigned OpNo,
245 const MCSubtargetInfo &STI,
246 raw_ostream &O) {
247 unsigned Imm = MI->getOperand(i: OpNo).getImm();
248 assert(RISCVVType::isValidXSfmmVType(Imm));
249 unsigned SEW = RISCVVType::getSEW(VType: Imm);
250 O << "e" << SEW;
251 bool AltFmt = RISCVVType::isAltFmt(VType: Imm);
252 if (AltFmt)
253 O << "alt";
254 unsigned Widen = RISCVVType::getXSfmmWiden(VType: Imm);
255 O << ", w" << Widen;
256}
257
258// Print a Zcmp RList. If we are printing architectural register names rather
259// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
260// registers. Otherwise, we print "{ra, s0-s11}".
261void RISCVInstPrinter::printRegList(const MCInst *MI, unsigned OpNo,
262 const MCSubtargetInfo &STI, raw_ostream &O) {
263 unsigned Imm = MI->getOperand(i: OpNo).getImm();
264
265 assert(Imm >= RISCVZC::RLISTENCODE::RA &&
266 Imm <= RISCVZC::RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
267
268 O << "{";
269 printRegName(O, Reg: RISCV::X1);
270
271 if (Imm >= RISCVZC::RLISTENCODE::RA_S0) {
272 O << ", ";
273 printRegName(O, Reg: RISCV::X8);
274 }
275
276 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S1) {
277 O << '-';
278 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S1 || ArchRegNames)
279 printRegName(O, Reg: RISCV::X9);
280 }
281
282 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S2) {
283 if (ArchRegNames)
284 O << ", ";
285 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S2 || ArchRegNames)
286 printRegName(O, Reg: RISCV::X18);
287 }
288
289 if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S3) {
290 if (ArchRegNames)
291 O << '-';
292 unsigned Offset = (Imm - RISCVZC::RLISTENCODE::RA_S0_S3);
293 // Encodings for S3-S9 are contiguous. There is no encoding for S10, so we
294 // must skip to S11(X27).
295 if (Imm == RISCVZC::RLISTENCODE::RA_S0_S11)
296 ++Offset;
297 printRegName(O, Reg: RISCV::X19 + Offset);
298 }
299
300 O << "}";
301}
302
303void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
304 const MCSubtargetInfo &STI, raw_ostream &O) {
305 const MCOperand &OffsetMO = MI->getOperand(i: OpNo + 1);
306
307 assert(OffsetMO.isReg() && "printRegReg can only print register operands");
308 printRegName(O, Reg: OffsetMO.getReg());
309
310 O << "(";
311 const MCOperand &BaseMO = MI->getOperand(i: OpNo);
312 assert(BaseMO.isReg() && "printRegReg can only print register operands");
313 printRegName(O, Reg: BaseMO.getReg());
314 O << ")";
315}
316
317void RISCVInstPrinter::printStackAdj(const MCInst *MI, unsigned OpNo,
318 const MCSubtargetInfo &STI, raw_ostream &O,
319 bool Negate) {
320 int64_t Imm = MI->getOperand(i: OpNo).getImm();
321 bool IsRV64 = STI.hasFeature(Feature: RISCV::Feature64Bit);
322 int64_t StackAdj = 0;
323 auto RlistVal = MI->getOperand(i: 0).getImm();
324 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64);
325 StackAdj = Imm + Base;
326 assert((StackAdj >= Base && StackAdj <= Base + 48) &&
327 "Incorrect stack adjust");
328 if (Negate)
329 StackAdj = -StackAdj;
330
331 // RAII guard for ANSI color escape sequences
332 WithMarkup ScopedMarkup = markup(OS&: O, M: Markup::Immediate);
333 O << StackAdj;
334}
335
336void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
337 const MCSubtargetInfo &STI,
338 raw_ostream &O) {
339 const MCOperand &MO = MI->getOperand(i: OpNo);
340
341 assert(MO.isReg() && "printVMaskReg can only print register operands");
342 if (MO.getReg() == RISCV::NoRegister)
343 return;
344 O << ", ";
345 printRegName(O, Reg: MO.getReg());
346 O << ".t";
347}
348
349void RISCVInstPrinter::printVScaleReg(const MCInst *MI, unsigned OpNo,
350 const MCSubtargetInfo &STI,
351 raw_ostream &O) {
352 const MCOperand &MO = MI->getOperand(i: OpNo);
353
354 assert(MO.isReg() && "printVScaleReg can only print register operands");
355 O << ", ";
356 printRegName(O, Reg: MO.getReg());
357 O << ".scale";
358}
359
360void RISCVInstPrinter::printTileLambda(const MCInst *MI, unsigned OpNo,
361 const MCSubtargetInfo &STI,
362 raw_ostream &O) {
363 const MCOperand &MO = MI->getOperand(i: OpNo);
364
365 assert(MO.isImm() && "printTileLambda can only print immediate operands");
366 unsigned Lambda = MO.getImm();
367 if (Lambda == 0)
368 return;
369
370 assert(Lambda <= 7 && "Unexpected tile lambda encoding");
371 O << ", L" << (1U << (Lambda - 1));
372}
373
374void RISCVInstPrinter::printImm(const MCInst *MI, unsigned OpNo,
375 const MCSubtargetInfo &STI, raw_ostream &O) {
376 const MCOperand &Op = MI->getOperand(i: OpNo);
377 const unsigned Opcode = MI->getOpcode();
378 uint64_t Imm = Op.getImm();
379 if (STI.getTargetTriple().isOSBinFormatMachO() &&
380 (Opcode == RISCV::ANDI || Opcode == RISCV::ORI || Opcode == RISCV::XORI ||
381 Opcode == RISCV::C_ANDI || Opcode == RISCV::AUIPC ||
382 Opcode == RISCV::LUI)) {
383 if (!STI.hasFeature(Feature: RISCV::Feature64Bit))
384 Imm &= 0xffffffff;
385 markup(OS&: O, M: Markup::Immediate) << formatHex(Value: Imm);
386 } else
387 markup(OS&: O, M: Markup::Immediate) << formatImm(Value: Imm);
388}
389
390const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
391 // When PrintAliases is enabled, and EmitX8AsFP is enabled, x8 will be printed
392 // as fp instead of s0. Note that these similar registers are not replaced:
393 // - X8_H: used for f16 register in zhinx
394 // - X8_W: used for f32 register in zfinx
395 // - X8_X9: used for GPR Pair
396 if (!ArchRegNames && EmitX8AsFP && Reg == RISCV::X8)
397 return "fp";
398 return getRegisterName(Reg, AltIdx: ArchRegNames ? RISCV::NoRegAltName
399 : RISCV::ABIRegAltName);
400}
401