1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains one of the several passes that expand pseudo instructions
10// into target instructions. This pass is run after register allocation and
11// before post RA scheduling.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVExpandPseudoBase.h"
17#include "RISCVInstrInfo.h"
18#include "RISCVSubtarget.h"
19#include "llvm/CodeGen/MachineFunctionPass.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21
22using namespace llvm;
23
24#define RISCV_EXPAND_PSEUDO_POST_RA_NAME \
25 "RISC-V Pseudo Instruction Expansion - Post-RA"
26
27namespace {
28
29class RISCVExpandPseudoPostRAImpl final : public RISCVExpandPseudoImplBase {
30 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
31 MachineBasicBlock::iterator &NextMBBI) const override;
32
33 bool expandMovImm(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MBBI) const;
35
36 bool expandMovAddr(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator MBBI) const;
38
39 bool expandMERGE(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MBBI) const;
41
42 bool expandAddUpperImm(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator MBBI) const;
44};
45
46class RISCVExpandPseudoPostRALegacy : public MachineFunctionPass {
47public:
48 static char ID;
49
50 RISCVExpandPseudoPostRALegacy() : MachineFunctionPass(ID) {}
51
52 bool runOnMachineFunction(MachineFunction &MF) override {
53 return RISCVExpandPseudoPostRAImpl().run(MF);
54 }
55
56 void getAnalysisUsage(AnalysisUsage &AU) const override {
57 AU.setPreservesCFG();
58 MachineFunctionPass::getAnalysisUsage(AU);
59 }
60
61 StringRef getPassName() const override {
62 return RISCV_EXPAND_PSEUDO_POST_RA_NAME;
63 }
64};
65
66} // anonymous namespace
67
68bool RISCVExpandPseudoPostRAImpl::expandMI(
69 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
70 MachineBasicBlock::iterator &NextMBBI) const {
71 switch (MBBI->getOpcode()) {
72 case RISCV::PseudoMovImm:
73 return expandMovImm(MBB, MBBI);
74 case RISCV::PseudoMovAddr:
75 return expandMovAddr(MBB, MBBI);
76 case RISCV::PseudoAddUpperImm:
77 return expandAddUpperImm(MBB, MBBI);
78 case RISCV::PseudoMERGE:
79 return expandMERGE(MBB, MBBI);
80 }
81
82 return false;
83}
84
85bool RISCVExpandPseudoPostRAImpl::expandMovImm(
86 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
87 DebugLoc DL = MBBI->getDebugLoc();
88
89 int64_t Val = MBBI->getOperand(i: 1).getImm();
90
91 Register DstReg = MBBI->getOperand(i: 0).getReg();
92 bool DstIsDead = MBBI->getOperand(i: 0).isDead();
93 bool Renamable = MBBI->getOperand(i: 0).isRenamable();
94
95 TII->movImm(MBB, MBBI, DL, DstReg, Val, Flag: MachineInstr::NoFlags, DstRenamable: Renamable,
96 DstIsDead);
97
98 MBBI->eraseFromParent();
99 return true;
100}
101
102bool RISCVExpandPseudoPostRAImpl::expandMovAddr(
103 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
104 DebugLoc DL = MBBI->getDebugLoc();
105
106 Register DstReg = MBBI->getOperand(i: 0).getReg();
107 bool DstIsDead = MBBI->getOperand(i: 0).isDead();
108 bool Renamable = MBBI->getOperand(i: 0).isRenamable();
109
110 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::LUI))
111 .addReg(RegNo: DstReg, Flags: RegState::Define | getRenamableRegState(B: Renamable))
112 .add(MO: MBBI->getOperand(i: 1));
113 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI))
114 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead) |
115 getRenamableRegState(B: Renamable))
116 .addReg(RegNo: DstReg, Flags: RegState::Kill | getRenamableRegState(B: Renamable))
117 .add(MO: MBBI->getOperand(i: 2));
118 MBBI->eraseFromParent();
119 return true;
120}
121
122bool RISCVExpandPseudoPostRAImpl::expandAddUpperImm(
123 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
124 DebugLoc DL = MBBI->getDebugLoc();
125
126 Register DstReg = MBBI->getOperand(i: 0).getReg();
127 bool DstIsDead = MBBI->getOperand(i: 0).isDead();
128 bool Renamable = MBBI->getOperand(i: 0).isRenamable();
129 Register BaseReg = MBBI->getOperand(i: 1).getReg();
130 int64_t Hi = MBBI->getOperand(i: 2).getImm();
131
132 // Expand to LUI+ADD: the immediate is already the upper 20-bit value.
133 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::LUI))
134 .addReg(RegNo: DstReg, Flags: RegState::Define | getRenamableRegState(B: Renamable))
135 .addImm(Val: Hi);
136 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADD))
137 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead) |
138 getRenamableRegState(B: Renamable))
139 .addReg(RegNo: BaseReg)
140 .addReg(RegNo: DstReg, Flags: RegState::Kill | getRenamableRegState(B: Renamable));
141
142 MBBI->eraseFromParent();
143 return true;
144}
145
146/// Transfer implicit operands on the pseudo instruction to the
147/// instructions created from the expansion.
148static void transferImpOps(const MachineInstr &OldMI, MachineInstrBuilder &MI) {
149 const MCInstrDesc &Desc = OldMI.getDesc();
150 for (const MachineOperand &MO :
151 llvm::drop_begin(RangeOrContainer: OldMI.operands(), N: Desc.getNumOperands())) {
152 assert(MO.isReg() && MO.getReg());
153 MI.add(MO);
154 }
155}
156
157// Expand PseudoMERGE to MERGE, MVM, or MVMN.
158bool RISCVExpandPseudoPostRAImpl::expandMERGE(
159 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
160 MachineInstr &MI = *MBBI;
161 DebugLoc DL = MI.getDebugLoc();
162
163 Register DstReg = MI.getOperand(i: 0).getReg();
164 if (DstReg == MI.getOperand(i: 3).getReg()) {
165 // Expand to MVMN
166 auto I = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::MVMN))
167 .add(MO: MI.getOperand(i: 0))
168 .add(MO: MI.getOperand(i: 3))
169 .add(MO: MI.getOperand(i: 2))
170 .add(MO: MI.getOperand(i: 1));
171 transferImpOps(OldMI: *MBBI, MI&: I);
172 } else if (DstReg == MBBI->getOperand(i: 2).getReg()) {
173 // Expand to MVM
174 auto I = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::MVM))
175 .add(MO: MI.getOperand(i: 0))
176 .add(MO: MI.getOperand(i: 2))
177 .add(MO: MI.getOperand(i: 3))
178 .add(MO: MI.getOperand(i: 1));
179 transferImpOps(OldMI: *MBBI, MI&: I);
180 } else if (DstReg == MI.getOperand(i: 1).getReg()) {
181 // Expand to MERGE
182 auto I = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::MERGE))
183 .add(MO: MI.getOperand(i: 0))
184 .add(MO: MI.getOperand(i: 1))
185 .add(MO: MI.getOperand(i: 2))
186 .add(MO: MI.getOperand(i: 3));
187 transferImpOps(OldMI: *MBBI, MI&: I);
188 } else {
189 // Use an additional move.
190 RegState RegState =
191 getRenamableRegState(B: MI.getOperand(i: 1).isRenamable()) |
192 getKillRegState(B: MI.getOperand(i: 1).isKill() &&
193 MI.getOperand(i: 1).getReg() !=
194 MI.getOperand(i: 2).getReg() &&
195 MI.getOperand(i: 1).getReg() != MI.getOperand(i: 3).getReg());
196 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: RISCV::ADDI))
197 .addDef(RegNo: DstReg, Flags: getRenamableRegState(B: MI.getOperand(i: 0).isRenamable()))
198 .addReg(RegNo: MI.getOperand(i: 1).getReg(), Flags: RegState)
199 .addImm(Val: 0);
200 auto I = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: RISCV::MERGE))
201 .add(MO: MI.getOperand(i: 0))
202 .addReg(RegNo: DstReg,
203 Flags: RegState::Kill | getRenamableRegState(
204 B: MI.getOperand(i: 0).isRenamable()))
205 .add(MO: MI.getOperand(i: 2))
206 .add(MO: MI.getOperand(i: 3));
207 transferImpOps(OldMI: *MBBI, MI&: I);
208 }
209 MI.eraseFromParent();
210 return true;
211}
212
213char RISCVExpandPseudoPostRALegacy::ID = 0;
214
215INITIALIZE_PASS(RISCVExpandPseudoPostRALegacy, "riscv-expand-pseudo-post-ra",
216 RISCV_EXPAND_PSEUDO_POST_RA_NAME, false, false)
217
218FunctionPass *llvm::createRISCVExpandPseudoPostRALegacyPass() {
219 return new RISCVExpandPseudoPostRALegacy();
220}
221
222PreservedAnalyses
223RISCVExpandPseudoPostRAPass::run(MachineFunction &MF,
224 MachineFunctionAnalysisManager &MFAM) {
225 bool Changed = RISCVExpandPseudoPostRAImpl().run(MF);
226 if (!Changed)
227 return PreservedAnalyses::all();
228
229 PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
230 PA.preserveSet<CFGAnalyses>();
231 return PA;
232}
233