1//===--- RISCVMachineScheduler.h - Custom RISC-V MI scheduler ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Custom RISC-V MI scheduler.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINESCHEDULER_H
14#define LLVM_LIB_TARGET_RISCV_RISCVMACHINESCHEDULER_H
15
16#include "RISCVSubtarget.h"
17#include "RISCVVSETVLIInfoAnalysis.h"
18#include "llvm/CodeGen/MachineScheduler.h"
19
20namespace llvm {
21
22/// A GenericScheduler implementation for RISCV pre RA scheduling.
23class RISCVPreRAMachineSchedStrategy : public GenericScheduler {
24 const RISCVSubtarget *ST;
25 RISCV::RISCVVSETVLIInfoAnalysis VIA;
26 RISCV::VSETVLIInfo TopInfo;
27 RISCV::VSETVLIInfo BottomInfo;
28
29 RISCV::VSETVLIInfo getVSETVLIInfo(const MachineInstr *MI) const;
30 bool tryVSETVLIInfo(const RISCV::VSETVLIInfo &TryInfo,
31 const RISCV::VSETVLIInfo &CandInfo,
32 SchedCandidate &TryCand, SchedCandidate &Cand,
33 CandReason Reason) const;
34
35public:
36 RISCVPreRAMachineSchedStrategy(const MachineSchedContext *C)
37 : GenericScheduler(C), ST(&C->MF->getSubtarget<RISCVSubtarget>()),
38 VIA(ST, C->LIS) {}
39
40protected:
41 bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand,
42 SchedBoundary *Zone) const override;
43 void enterMBB(MachineBasicBlock *MBB) override;
44 void leaveMBB() override;
45 void schedNode(SUnit *SU, bool IsTopNode) override;
46};
47
48} // end namespace llvm
49
50#endif
51