1//===- RISCVMachineScheduler.cpp - MI Scheduler for RISC-V ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCVMachineScheduler.h"
10#include "llvm/CodeGen/ScheduleDAG.h"
11
12using namespace llvm;
13
14#define DEBUG_TYPE "riscv-prera-sched-strategy"
15
16RISCV::VSETVLIInfo
17RISCVPreRAMachineSchedStrategy::getVSETVLIInfo(const MachineInstr *MI) const {
18 unsigned TSFlags = MI->getDesc().TSFlags;
19 if (!RISCVII::hasSEWOp(TSFlags))
20 return RISCV::VSETVLIInfo();
21 return VIA.computeInfoForInstr(MI: *MI);
22}
23
24bool RISCVPreRAMachineSchedStrategy::tryVSETVLIInfo(
25 const RISCV::VSETVLIInfo &TryInfo, const RISCV::VSETVLIInfo &CandInfo,
26 SchedCandidate &TryCand, SchedCandidate &Cand, CandReason Reason) const {
27 // Do not compare the vsetvli info changes between top and bottom
28 // boundary.
29 if (Cand.AtTop != TryCand.AtTop)
30 return false;
31
32 auto IsCompatible = [&](const RISCV::VSETVLIInfo &FirstInfo,
33 const RISCV::VSETVLIInfo &SecondInfo) {
34 return FirstInfo.isValid() && SecondInfo.isValid() &&
35 FirstInfo.isCompatible(Used: RISCV::DemandedFields::all(), Require: SecondInfo,
36 LIS: Context->LIS);
37 };
38
39 // Try Cand first.
40 // We prefer the top node as it is straightforward from the perspective of
41 // vsetvli dataflow.
42 if (Cand.AtTop && IsCompatible(CandInfo, TopInfo))
43 return true;
44
45 if (!Cand.AtTop && IsCompatible(CandInfo, BottomInfo))
46 return true;
47
48 // Then try TryCand.
49 if (TryCand.AtTop && IsCompatible(TryInfo, TopInfo)) {
50 TryCand.Reason = Reason;
51 return true;
52 }
53
54 if (!TryCand.AtTop && IsCompatible(TryInfo, BottomInfo)) {
55 TryCand.Reason = Reason;
56 return true;
57 }
58
59 return false;
60}
61
62bool RISCVPreRAMachineSchedStrategy::tryCandidate(SchedCandidate &Cand,
63 SchedCandidate &TryCand,
64 SchedBoundary *Zone) const {
65 //-------------------------------------------------------------------------//
66 // Below is copied from `GenericScheduler::tryCandidate`.
67 // FIXME: Is there a way to not replicate this?
68 //-------------------------------------------------------------------------//
69 // Initialize the candidate if needed.
70 if (!Cand.isValid()) {
71 TryCand.Reason = FirstValid;
72 return true;
73 }
74
75 // Bias PhysReg Defs and copies to their uses and defined respectively.
76 if (tryGreater(TryVal: biasPhysReg(SU: TryCand.SU, isTop: TryCand.AtTop),
77 CandVal: biasPhysReg(SU: Cand.SU, isTop: Cand.AtTop), TryCand, Cand, Reason: PhysReg))
78 return TryCand.Reason != NoCand;
79
80 // Avoid exceeding the target's limit.
81 if (DAG->isTrackingPressure() &&
82 tryPressure(TryP: TryCand.RPDelta.Excess, CandP: Cand.RPDelta.Excess, TryCand, Cand,
83 Reason: RegExcess, TRI, MF: DAG->MF))
84 return TryCand.Reason != NoCand;
85
86 // Avoid increasing the max critical pressure in the scheduled region.
87 if (DAG->isTrackingPressure() &&
88 tryPressure(TryP: TryCand.RPDelta.CriticalMax, CandP: Cand.RPDelta.CriticalMax,
89 TryCand, Cand, Reason: RegCritical, TRI, MF: DAG->MF))
90 return TryCand.Reason != NoCand;
91
92 // We only compare a subset of features when comparing nodes between
93 // Top and Bottom boundary. Some properties are simply incomparable, in many
94 // other instances we should only override the other boundary if something
95 // is a clear good pick on one boundary. Skip heuristics that are more
96 // "tie-breaking" in nature.
97 bool SameBoundary = Zone != nullptr;
98 if (SameBoundary) {
99 // For loops that are acyclic path limited, aggressively schedule for
100 // latency. Within an single cycle, whenever CurrMOps > 0, allow normal
101 // heuristics to take precedence.
102 if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() &&
103 tryLatency(TryCand, Cand, Zone&: *Zone))
104 return TryCand.Reason != NoCand;
105
106 // Prioritize instructions that read unbuffered resources by stall cycles.
107 if (tryLess(TryVal: Zone->getLatencyStallCycles(SU: TryCand.SU),
108 CandVal: Zone->getLatencyStallCycles(SU: Cand.SU), TryCand, Cand, Reason: Stall))
109 return TryCand.Reason != NoCand;
110 }
111
112 // Keep clustered nodes together to encourage downstream peephole
113 // optimizations which may reduce resource requirements.
114 //
115 // This is a best effort to set things up for a post-RA pass. Optimizations
116 // like generating loads of multiple registers should ideally be done within
117 // the scheduler pass by combining the loads during DAG postprocessing.
118 unsigned CandZoneCluster = Cand.AtTop ? TopClusterID : BotClusterID;
119 unsigned TryCandZoneCluster = TryCand.AtTop ? TopClusterID : BotClusterID;
120 bool CandIsClusterSucc =
121 isTheSameCluster(A: CandZoneCluster, B: Cand.SU->ParentClusterIdx);
122 bool TryCandIsClusterSucc =
123 isTheSameCluster(A: TryCandZoneCluster, B: TryCand.SU->ParentClusterIdx);
124
125 if (tryGreater(TryVal: TryCandIsClusterSucc, CandVal: CandIsClusterSucc, TryCand, Cand,
126 Reason: Cluster))
127 return TryCand.Reason != NoCand;
128
129 if (SameBoundary) {
130 // Weak edges are for clustering and other constraints.
131 if (tryLess(TryVal: getWeakLeft(SU: TryCand.SU, isTop: TryCand.AtTop),
132 CandVal: getWeakLeft(SU: Cand.SU, isTop: Cand.AtTop), TryCand, Cand, Reason: Weak))
133 return TryCand.Reason != NoCand;
134 }
135
136 // Avoid increasing the max pressure of the entire region.
137 if (DAG->isTrackingPressure() &&
138 tryPressure(TryP: TryCand.RPDelta.CurrentMax, CandP: Cand.RPDelta.CurrentMax, TryCand,
139 Cand, Reason: RegMax, TRI, MF: DAG->MF))
140 return TryCand.Reason != NoCand;
141
142 if (SameBoundary) {
143 // Avoid critical resource consumption and balance the schedule.
144 TryCand.initResourceDelta(DAG, SchedModel);
145 if (tryLess(TryVal: TryCand.ResDelta.CritResources, CandVal: Cand.ResDelta.CritResources,
146 TryCand, Cand, Reason: ResourceReduce))
147 return TryCand.Reason != NoCand;
148 if (tryGreater(TryVal: TryCand.ResDelta.DemandedResources,
149 CandVal: Cand.ResDelta.DemandedResources, TryCand, Cand,
150 Reason: ResourceDemand))
151 return TryCand.Reason != NoCand;
152
153 // Avoid serializing long latency dependence chains.
154 // For acyclic path limited loops, latency was already checked above.
155 if (!RegionPolicy.DisableLatencyHeuristic && TryCand.Policy.ReduceLatency &&
156 !Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone&: *Zone))
157 return TryCand.Reason != NoCand;
158
159 // Fall through to original instruction order.
160 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) ||
161 (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum))
162 TryCand.Reason = NodeOrder;
163 }
164
165 //-------------------------------------------------------------------------//
166 // Below is RISC-V specific scheduling heuristics.
167 //-------------------------------------------------------------------------//
168
169 // Add RISC-V specific heuristic only when TryCand isn't selected or
170 // selected as node order.
171 if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
172 return true;
173
174 // TODO: We should not use `CandReason::Cluster` here, but is there a
175 // mechanism to extend this enum?
176 if (ST->enableVsetvliSchedHeuristic() &&
177 tryVSETVLIInfo(TryInfo: getVSETVLIInfo(MI: TryCand.SU->getInstr()),
178 CandInfo: getVSETVLIInfo(MI: Cand.SU->getInstr()), TryCand, Cand,
179 Reason: Cluster))
180 return TryCand.Reason != NoCand;
181
182 return TryCand.Reason != NoCand;
183}
184
185void RISCVPreRAMachineSchedStrategy::enterMBB(MachineBasicBlock *MBB) {
186 TopInfo = RISCV::VSETVLIInfo();
187 BottomInfo = RISCV::VSETVLIInfo();
188}
189
190void RISCVPreRAMachineSchedStrategy::leaveMBB() {
191 TopInfo = RISCV::VSETVLIInfo();
192 BottomInfo = RISCV::VSETVLIInfo();
193}
194
195void RISCVPreRAMachineSchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
196 GenericScheduler::schedNode(SU, IsTopNode);
197 if (ST->enableVsetvliSchedHeuristic()) {
198 MachineInstr *MI = SU->getInstr();
199 const RISCV::VSETVLIInfo &Info = getVSETVLIInfo(MI);
200 if (Info.isValid()) {
201 if (IsTopNode)
202 TopInfo = Info;
203 else
204 BottomInfo = Info;
205 LLVM_DEBUG({
206 dbgs() << "Previous scheduled Unit: \n";
207 dbgs() << " IsTop: " << IsTopNode << "\n";
208 dbgs() << " SU(" << SU->NodeNum << ") - ";
209 MI->dump();
210 dbgs() << " \n";
211 Info.dump();
212 dbgs() << " \n";
213 });
214 }
215 }
216}
217