1//===-- RISCVPostRAExpandPseudoInsts.cpp - Expand pseudo instrs ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands the pseudo instruction pseudolisimm32
10// into target instructions. This pass should be run during the post-regalloc
11// passes, before post RA scheduling.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19
20using namespace llvm;
21
22#define RISCV_POST_RA_EXPAND_PSEUDO_NAME \
23 "RISC-V post-regalloc pseudo instruction expansion pass"
24
25namespace {
26
27class RISCVPostRAExpandPseudo : public MachineFunctionPass {
28public:
29 const RISCVInstrInfo *TII;
30 static char ID;
31
32 RISCVPostRAExpandPseudo() : MachineFunctionPass(ID) {}
33
34 bool runOnMachineFunction(MachineFunction &MF) override;
35
36 StringRef getPassName() const override {
37 return RISCV_POST_RA_EXPAND_PSEUDO_NAME;
38 }
39
40private:
41 bool expandMBB(MachineBasicBlock &MBB);
42 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
43 MachineBasicBlock::iterator &NextMBBI);
44 bool expandMovImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
45 bool expandMovAddr(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
46 bool expandMERGE(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
47};
48
49char RISCVPostRAExpandPseudo::ID = 0;
50
51bool RISCVPostRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
52 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
53 bool Modified = false;
54 for (auto &MBB : MF)
55 Modified |= expandMBB(MBB);
56 return Modified;
57}
58
59bool RISCVPostRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
60 bool Modified = false;
61
62 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
63 while (MBBI != E) {
64 MachineBasicBlock::iterator NMBBI = std::next(x: MBBI);
65 Modified |= expandMI(MBB, MBBI, NextMBBI&: NMBBI);
66 MBBI = NMBBI;
67 }
68
69 return Modified;
70}
71
72bool RISCVPostRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MBBI,
74 MachineBasicBlock::iterator &NextMBBI) {
75 switch (MBBI->getOpcode()) {
76 case RISCV::PseudoMovImm:
77 return expandMovImm(MBB, MBBI);
78 case RISCV::PseudoMovAddr:
79 return expandMovAddr(MBB, MBBI);
80 case RISCV::PseudoMERGE:
81 return expandMERGE(MBB, MBBI);
82 default:
83 return false;
84 }
85}
86
87bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MBBI) {
89 DebugLoc DL = MBBI->getDebugLoc();
90
91 int64_t Val = MBBI->getOperand(i: 1).getImm();
92
93 Register DstReg = MBBI->getOperand(i: 0).getReg();
94 bool DstIsDead = MBBI->getOperand(i: 0).isDead();
95 bool Renamable = MBBI->getOperand(i: 0).isRenamable();
96
97 TII->movImm(MBB, MBBI, DL, DstReg, Val, Flag: MachineInstr::NoFlags, DstRenamable: Renamable,
98 DstIsDead);
99
100 MBBI->eraseFromParent();
101 return true;
102}
103
104bool RISCVPostRAExpandPseudo::expandMovAddr(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MBBI) {
106 DebugLoc DL = MBBI->getDebugLoc();
107
108 Register DstReg = MBBI->getOperand(i: 0).getReg();
109 bool DstIsDead = MBBI->getOperand(i: 0).isDead();
110 bool Renamable = MBBI->getOperand(i: 0).isRenamable();
111
112 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::LUI))
113 .addReg(RegNo: DstReg, Flags: RegState::Define | getRenamableRegState(B: Renamable))
114 .add(MO: MBBI->getOperand(i: 1));
115 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI))
116 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead) |
117 getRenamableRegState(B: Renamable))
118 .addReg(RegNo: DstReg, Flags: RegState::Kill | getRenamableRegState(B: Renamable))
119 .add(MO: MBBI->getOperand(i: 2));
120 MBBI->eraseFromParent();
121 return true;
122}
123
124/// Transfer implicit operands on the pseudo instruction to the
125/// instructions created from the expansion.
126static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &MI) {
127 const MCInstrDesc &Desc = OldMI.getDesc();
128 for (const MachineOperand &MO :
129 llvm::drop_begin(RangeOrContainer: OldMI.operands(), N: Desc.getNumOperands())) {
130 assert(MO.isReg() && MO.getReg());
131 MI.add(MO);
132 }
133}
134
135// Expand PseudoMERGE to MERGE, MVM, or MVMN.
136bool RISCVPostRAExpandPseudo::expandMERGE(MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator MBBI) {
138 MachineInstr &MI = *MBBI;
139 DebugLoc DL = MI.getDebugLoc();
140
141 Register DstReg = MI.getOperand(i: 0).getReg();
142 if (DstReg == MI.getOperand(i: 3).getReg()) {
143 // Expand to MVMN
144 auto I = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::MVMN))
145 .add(MO: MI.getOperand(i: 0))
146 .add(MO: MI.getOperand(i: 3))
147 .add(MO: MI.getOperand(i: 2))
148 .add(MO: MI.getOperand(i: 1));
149 transferImpOps(OldMI&: *MBBI, MI&: I);
150 } else if (DstReg == MBBI->getOperand(i: 2).getReg()) {
151 // Expand to MVM
152 auto I = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::MVM))
153 .add(MO: MI.getOperand(i: 0))
154 .add(MO: MI.getOperand(i: 2))
155 .add(MO: MI.getOperand(i: 3))
156 .add(MO: MI.getOperand(i: 1));
157 transferImpOps(OldMI&: *MBBI, MI&: I);
158 } else if (DstReg == MI.getOperand(i: 1).getReg()) {
159 // Expand to MERGE
160 auto I = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::MERGE))
161 .add(MO: MI.getOperand(i: 0))
162 .add(MO: MI.getOperand(i: 1))
163 .add(MO: MI.getOperand(i: 2))
164 .add(MO: MI.getOperand(i: 3));
165 transferImpOps(OldMI&: *MBBI, MI&: I);
166 } else {
167 // Use an additional move.
168 RegState RegState =
169 getRenamableRegState(B: MI.getOperand(i: 1).isRenamable()) |
170 getKillRegState(B: MI.getOperand(i: 1).isKill() &&
171 MI.getOperand(i: 1).getReg() !=
172 MI.getOperand(i: 2).getReg() &&
173 MI.getOperand(i: 1).getReg() != MI.getOperand(i: 3).getReg());
174 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: RISCV::ADDI))
175 .addDef(RegNo: DstReg, Flags: getRenamableRegState(B: MI.getOperand(i: 0).isRenamable()))
176 .addReg(RegNo: MI.getOperand(i: 1).getReg(), Flags: RegState)
177 .addImm(Val: 0);
178 auto I = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: RISCV::MERGE))
179 .add(MO: MI.getOperand(i: 0))
180 .addReg(RegNo: DstReg,
181 Flags: RegState::Kill | getRenamableRegState(
182 B: MI.getOperand(i: 0).isRenamable()))
183 .add(MO: MI.getOperand(i: 2))
184 .add(MO: MI.getOperand(i: 3));
185 transferImpOps(OldMI&: *MBBI, MI&: I);
186 }
187 MI.eraseFromParent();
188 return true;
189}
190
191} // end of anonymous namespace
192
193INITIALIZE_PASS(RISCVPostRAExpandPseudo, "riscv-post-ra-expand-pseudo",
194 RISCV_POST_RA_EXPAND_PSEUDO_NAME, false, false)
195namespace llvm {
196
197FunctionPass *createRISCVPostRAExpandPseudoPass() {
198 return new RISCVPostRAExpandPseudo();
199}
200
201} // end of namespace llvm
202