1//===--- SPIRVUtils.h ---- SPIR-V Utility Functions -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains miscellaneous utility functions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
14#define LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
15
16#include "MCTargetDesc/SPIRVBaseInfo.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallPtrSet.h"
19#include "llvm/ADT/StringMap.h"
20#include "llvm/Analysis/LoopInfo.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/IR/Dominators.h"
23#include "llvm/IR/GlobalVariable.h"
24#include "llvm/IR/IRBuilder.h"
25#include "llvm/IR/TypedPointerType.h"
26#include <queue>
27#include <set>
28#include <string>
29
30#include "SPIRVTypeInst.h"
31
32namespace llvm {
33class MCInst;
34class MachineFunction;
35class MachineInstrBuilder;
36class MachineIRBuilder;
37class MachineRegisterInfo;
38class Register;
39class StringRef;
40class Triple;
41class SPIRVInstrInfo;
42class SPIRVSubtarget;
43class SPIRVGlobalRegistry;
44
45// This class implements a partial ordering visitor, which visits a cyclic graph
46// in natural topological-like ordering. Topological ordering is not defined for
47// directed graphs with cycles, so this assumes cycles are a single node, and
48// ignores back-edges. The cycle is visited from the entry in the same
49// topological-like ordering.
50//
51// Note: this visitor REQUIRES a reducible graph.
52//
53// This means once we visit a node, we know all the possible ancestors have been
54// visited.
55//
56// clang-format off
57//
58// Given this graph:
59//
60// ,-> B -\
61// A -+ +---> D ----> E -> F -> G -> H
62// `-> C -/ ^ |
63// +-----------------+
64//
65// Visit order is:
66// A, [B, C in any order], D, E, F, G, H
67//
68// clang-format on
69//
70// Changing the function CFG between the construction of the visitor and
71// visiting is undefined. The visitor can be reused, but if the CFG is updated,
72// the visitor must be rebuilt.
73class PartialOrderingVisitor {
74 DomTreeBuilder::BBDomTree DT;
75 LoopInfo LI;
76
77 SmallPtrSet<BasicBlock *, 0> Queued;
78 std::queue<BasicBlock *> ToVisit;
79
80 struct OrderInfo {
81 size_t Rank;
82 size_t TraversalIndex;
83 };
84
85 using BlockToOrderInfoMap = DenseMap<BasicBlock *, OrderInfo>;
86 BlockToOrderInfoMap BlockToOrder;
87 std::vector<BasicBlock *> Order;
88
89 // Get all basic-blocks reachable from Start.
90 SmallPtrSet<BasicBlock *, 0> getReachableFrom(BasicBlock *Start);
91
92 // Internal function used to determine the partial ordering.
93 // Visits |BB| with the current rank being |Rank|.
94 size_t visit(BasicBlock *BB, size_t Rank);
95
96 bool CanBeVisited(BasicBlock *BB) const;
97
98public:
99 size_t GetNodeRank(BasicBlock *BB) const;
100
101 // Build the visitor to operate on the function F.
102 PartialOrderingVisitor(Function &F);
103
104 // Returns the dominator tree computed for the function this visitor
105 // operates on.
106 const DomTreeBuilder::BBDomTree &getDominatorTree() const { return DT; }
107
108 // Returns true is |LHS| comes before |RHS| in the partial ordering.
109 // If |LHS| and |RHS| have the same rank, the traversal order determines the
110 // order (order is stable).
111 bool compare(const BasicBlock *LHS, const BasicBlock *RHS) const;
112
113 // Visit the function starting from the basic block |Start|, and calling |Op|
114 // on each visited BB. This traversal ignores back-edges, meaning this won't
115 // visit a node to which |Start| is not an ancestor.
116 // If Op returns |true|, the visitor continues. If |Op| returns false, the
117 // visitor will stop at that rank. This means if 2 nodes share the same rank,
118 // and Op returns false when visiting the first, the second will be visited
119 // afterwards. But none of their successors will.
120 void partialOrderVisit(BasicBlock &Start,
121 std::function<bool(BasicBlock *)> Op);
122};
123
124namespace SPIRV {
125struct FPFastMathDefaultInfo {
126 const Type *Ty = nullptr;
127 unsigned FastMathFlags = 0;
128 // When SPV_KHR_float_controls2 ContractionOff and SignzeroInfNanPreserve are
129 // deprecated, and we replace them with FPFastMathDefault appropriate flags
130 // instead. However, we have no guarantee about the order in which we will
131 // process execution modes. Therefore it could happen that we first process
132 // ContractionOff, setting AllowContraction bit to 0, and then we process
133 // FPFastMathDefault enabling AllowContraction bit, effectively invalidating
134 // ContractionOff. Because of that, it's best to keep separate bits for the
135 // different execution modes, and we will try and combine them later when we
136 // emit OpExecutionMode instructions.
137 bool ContractionOff = false;
138 bool SignedZeroInfNanPreserve = false;
139 bool FPFastMathDefault = false;
140
141 FPFastMathDefaultInfo() = default;
142 FPFastMathDefaultInfo(const Type *Ty, unsigned FastMathFlags)
143 : Ty(Ty), FastMathFlags(FastMathFlags) {}
144 bool operator==(const FPFastMathDefaultInfo &Other) const {
145 return Ty == Other.Ty && FastMathFlags == Other.FastMathFlags &&
146 ContractionOff == Other.ContractionOff &&
147 SignedZeroInfNanPreserve == Other.SignedZeroInfNanPreserve &&
148 FPFastMathDefault == Other.FPFastMathDefault;
149 }
150};
151
152struct FPFastMathDefaultInfoVector
153 : public SmallVector<SPIRV::FPFastMathDefaultInfo, 3> {
154 static size_t computeFPFastMathDefaultInfoVecIndex(size_t BitWidth) {
155 switch (BitWidth) {
156 case 16: // half
157 return 0;
158 case 32: // float
159 return 1;
160 case 64: // double
161 return 2;
162 default:
163 report_fatal_error(reason: "Expected BitWidth to be 16, 32, 64", gen_crash_diag: false);
164 }
165 llvm_unreachable(
166 "Unreachable code in computeFPFastMathDefaultInfoVecIndex");
167 }
168};
169
170// This code restores function args/retvalue types for composite cases
171// because the final types should still be aggregate whereas they're i32
172// during the translation to cope with aggregate flattening etc.
173FunctionType *getOriginalFunctionType(const Function &F);
174FunctionType *getOriginalFunctionType(const CallBase &CB);
175// This handles retrieving the original ASM constraints, which we had to spoof
176// into having a single output.
177StringRef getOriginalAsmConstraints(const CallBase &CB);
178} // namespace SPIRV
179
180// Add the given string as a series of integer operand, inserting null
181// terminators and padding to make sure the operands all have 32-bit
182// little-endian words.
183void addStringImm(StringRef Str, MCInst &Inst);
184void addStringImm(StringRef Str, MachineInstrBuilder &MIB);
185
186// Read the series of integer operands back as a null-terminated string using
187// the reverse of the logic in addStringImm.
188std::string getStringImm(const MachineInstr &MI, unsigned StartIndex);
189
190// Returns the string constant that the register refers to. It is assumed that
191// Reg is a global value that contains a string.
192std::string getStringValueFromReg(Register Reg, MachineRegisterInfo &MRI);
193
194// Add the given numerical immediate to MIB.
195void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB);
196
197// Add an OpName instruction for the given target register.
198void buildOpName(Register Target, StringRef Name, MachineIRBuilder &MIRBuilder);
199
200// Add an OpDecorate instruction for the given Reg.
201void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
202 SPIRV::Decoration::Decoration Dec,
203 ArrayRef<uint32_t> DecArgs, StringRef StrImm = "");
204void buildOpDecorate(Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII,
205 SPIRV::Decoration::Decoration Dec,
206 ArrayRef<uint32_t> DecArgs, StringRef StrImm = "");
207
208// Add an OpDecorate instruction for the given Reg.
209void buildOpMemberDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
210 SPIRV::Decoration::Decoration Dec, uint32_t Member,
211 ArrayRef<uint32_t> DecArgs, StringRef StrImm = "");
212
213// Add an OpDecorate instruction by "spirv.Decorations" metadata node.
214void buildOpSpirvDecorations(Register Reg, MachineIRBuilder &MIRBuilder,
215 const MDNode *GVarMD, const SPIRVSubtarget &ST);
216
217// Return a valid position for the OpVariable instruction inside a function,
218// i.e., at the beginning of the first block of the function.
219MachineBasicBlock::iterator getOpVariableMBBIt(MachineFunction &MF);
220
221// Return a valid position for the instruction at the end of the block before
222// terminators and debug instructions.
223MachineBasicBlock::iterator getInsertPtValidEnd(MachineBasicBlock *MBB);
224
225// Returns true if a pointer to the storage class can be casted to/from a
226// pointer to the Generic storage class.
227constexpr bool isGenericCastablePtr(SPIRV::StorageClass::StorageClass SC) {
228 switch (SC) {
229 case SPIRV::StorageClass::Workgroup:
230 case SPIRV::StorageClass::CrossWorkgroup:
231 case SPIRV::StorageClass::Function:
232 case SPIRV::StorageClass::CodeSectionINTEL:
233 return true;
234 default:
235 return false;
236 }
237}
238
239// Convert a SPIR-V storage class to the corresponding LLVM IR address space.
240// TODO: maybe the following two functions should be handled in the subtarget
241// to allow for different OpenCL vs Vulkan handling.
242constexpr unsigned
243storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC) {
244 switch (SC) {
245 case SPIRV::StorageClass::Function:
246 return 0;
247 case SPIRV::StorageClass::CrossWorkgroup:
248 return 1;
249 case SPIRV::StorageClass::UniformConstant:
250 return 2;
251 case SPIRV::StorageClass::Workgroup:
252 return 3;
253 case SPIRV::StorageClass::Generic:
254 return 4;
255 case SPIRV::StorageClass::DeviceOnlyINTEL:
256 return 5;
257 case SPIRV::StorageClass::HostOnlyINTEL:
258 return 6;
259 case SPIRV::StorageClass::Input:
260 return 7;
261 case SPIRV::StorageClass::Output:
262 return 8;
263 case SPIRV::StorageClass::CodeSectionINTEL:
264 return 9;
265 case SPIRV::StorageClass::Private:
266 return 10;
267 case SPIRV::StorageClass::StorageBuffer:
268 return 11;
269 case SPIRV::StorageClass::Uniform:
270 return 12;
271 case SPIRV::StorageClass::PushConstant:
272 return 13;
273 default:
274 report_fatal_error(reason: "Unable to get address space id");
275 }
276}
277
278// Convert an LLVM IR address space to a SPIR-V storage class.
279SPIRV::StorageClass::StorageClass
280addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI);
281
282SPIRV::MemorySemantics::MemorySemantics
283getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC);
284
285SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord);
286
287uint32_t getMemSemanticsWithStorageClass(const Triple &TT, uint32_t OrderSem,
288 uint32_t StorageClassSem);
289
290SPIRV::Scope::Scope getMemScope(const Triple &TT, LLVMContext &Ctx,
291 SyncScope::ID Id);
292
293// Find def instruction for the given ConstReg, walking through
294// spv_track_constant and ASSIGN_TYPE instructions. Updates ConstReg by def
295// of OpConstant instruction.
296MachineInstr *getDefInstrMaybeConstant(Register &ConstReg,
297 const MachineRegisterInfo *MRI);
298
299// Get constant integer value of the given ConstReg.
300uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI);
301
302// Get constant integer value of the given ConstReg, sign-extended.
303int64_t getIConstValSext(Register ConstReg, const MachineRegisterInfo *MRI);
304
305// Check if MI is a SPIR-V specific intrinsic call.
306bool isSpvIntrinsic(const MachineInstr &MI, Intrinsic::ID IntrinsicID);
307// Check if it's a SPIR-V specific intrinsic call.
308bool isSpvIntrinsic(const Value *Arg);
309
310// Get type of i-th operand of the metadata node.
311Type *getMDOperandAsType(const MDNode *N, unsigned I);
312
313// Get the i-th operand of the metadata node as a ConstantInt, or nullptr if it
314// is out of range or not a ConstantInt.
315ConstantInt *getMDOperandAsConstInt(const MDNode *N, unsigned I);
316
317// If OpenCL or SPIR-V builtin function name is recognized, return a demangled
318// name, otherwise return an empty string.
319std::string getOclOrSpirvBuiltinDemangledName(StringRef Name);
320
321// Check if a string contains a builtin prefix.
322bool hasBuiltinTypePrefix(StringRef Name);
323
324// Check if given LLVM type is a special opaque builtin type.
325bool isSpecialOpaqueType(const Type *Ty);
326
327// Check if the function is an SPIR-V entry point
328bool isEntryPoint(const Function &F);
329
330// Parse basic scalar type name, substring TypeName, and return LLVM type.
331Type *parseBasicTypeName(StringRef &TypeName, LLVMContext &Ctx);
332
333// Sort blocks in a partial ordering, so each block is after all its
334// dominators. This should match both the SPIR-V and the MIR requirements.
335// Returns true if the function was changed.
336bool sortBlocks(Function &F);
337
338// Create a stack slot in the entry block of F for a value of the given type.
339AllocaInst *createVariable(Function &F, Type *Type);
340
341// Create a value in BB set to the value associated with the branch the block
342// terminator will take.
343Value *
344createExitVariable(BasicBlock *BB,
345 const DenseMap<BasicBlock *, ConstantInt *> &TargetToValue);
346
347// Check for peeled array structs and recursively reconstitute them. In HLSL
348// CBuffers, arrays may have padding between the elements, but not after the
349// last element. To represent this in LLVM IR an array [N x T] will be
350// represented as {[N-1 x {T, spirv.Padding}], T}. The function
351// matchPeeledArrayPattern recognizes this pattern retrieving the type {T,
352// spirv.Padding}, and the size N.
353bool matchPeeledArrayPattern(const StructType *Ty, Type *&OriginalElementType,
354 uint64_t &TotalSize);
355
356// This function will turn the type {[N-1 x {T, spirv.Padding}], T} back into
357// [N x {T, spirv.Padding}]. So it can be translated into SPIR-V. The offset
358// decorations will be such that there will be no padding after the array when
359// relevant.
360Type *reconstitutePeeledArrayType(Type *Ty);
361
362inline bool hasInitializer(const GlobalVariable *GV) {
363 if (!GV->hasInitializer())
364 return false;
365 if (const auto *Init = GV->getInitializer(); isa<UndefValue>(Val: Init))
366 return GV->isConstant() && Init->getType()->isAggregateType();
367 return true;
368}
369
370// True if this is an instance of TypedPointerType.
371inline bool isTypedPointerTy(const Type *T) {
372 return T && T->getTypeID() == Type::TypedPointerTyID;
373}
374
375// True if this is an instance of PointerType.
376inline bool isUntypedPointerTy(const Type *T) {
377 return T && T->getTypeID() == Type::PointerTyID;
378}
379
380// True if this is an instance of PointerType or TypedPointerType.
381inline bool isPointerTy(const Type *T) {
382 return isUntypedPointerTy(T) || isTypedPointerTy(T);
383}
384
385// True if this is a vector whose element type is an (untyped) PointerType.
386inline bool isUntypedPointerVectorTy(const Type *T) {
387 return isa_and_nonnull<VectorType>(Val: T) &&
388 isUntypedPointerTy(T: T->getScalarType());
389}
390
391// Get the address space of this pointer or pointer vector type for instances of
392// PointerType or TypedPointerType.
393inline unsigned getPointerAddressSpace(const Type *T) {
394 Type *SubT = T->getScalarType();
395 return SubT->getTypeID() == Type::PointerTyID
396 ? cast<PointerType>(Val: SubT)->getAddressSpace()
397 : cast<TypedPointerType>(Val: SubT)->getAddressSpace();
398}
399
400// Return true if the Argument is decorated with a pointee type
401inline bool hasPointeeTypeAttr(Argument *Arg) {
402 return Arg->hasByValAttr() || Arg->hasByRefAttr() || Arg->hasStructRetAttr();
403}
404
405// Return the pointee type of the argument or nullptr otherwise
406inline Type *getPointeeTypeByAttr(Argument *Arg) {
407 if (Arg->hasByValAttr())
408 return Arg->getParamByValType();
409 if (Arg->hasStructRetAttr())
410 return Arg->getParamStructRetType();
411 if (Arg->hasByRefAttr())
412 return Arg->getParamByRefType();
413 return nullptr;
414}
415
416#define TYPED_PTR_TARGET_EXT_NAME "spirv.$TypedPointerType"
417inline Type *getTypedPointerWrapper(Type *ElemTy, unsigned AS) {
418 return TargetExtType::get(Context&: ElemTy->getContext(), TYPED_PTR_TARGET_EXT_NAME,
419 Types: {ElemTy}, Ints: {AS});
420}
421
422inline bool isTypedPointerWrapper(const TargetExtType *ExtTy) {
423 return ExtTy->getName() == TYPED_PTR_TARGET_EXT_NAME &&
424 ExtTy->getNumIntParameters() == 1 &&
425 ExtTy->getNumTypeParameters() == 1;
426}
427
428// True if this is an instance of PointerType or TypedPointerType.
429inline bool isPointerTyOrWrapper(const Type *Ty) {
430 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty))
431 return isTypedPointerWrapper(ExtTy);
432 return isPointerTy(T: Ty);
433}
434
435inline Type *applyWrappers(Type *Ty) {
436 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty)) {
437 if (isTypedPointerWrapper(ExtTy))
438 return TypedPointerType::get(ElementType: applyWrappers(Ty: ExtTy->getTypeParameter(i: 0)),
439 AddressSpace: ExtTy->getIntParameter(i: 0));
440 } else if (auto *VecTy = dyn_cast<VectorType>(Val: Ty)) {
441 Type *ElemTy = VecTy->getElementType();
442 Type *NewElemTy = ElemTy->isTargetExtTy() ? applyWrappers(Ty: ElemTy) : ElemTy;
443 if (NewElemTy != ElemTy)
444 return VectorType::get(ElementType: NewElemTy, EC: VecTy->getElementCount());
445 }
446 return Ty;
447}
448
449inline Type *getPointeeType(const Type *Ty) {
450 if (Ty) {
451 if (auto PType = dyn_cast<TypedPointerType>(Val: Ty))
452 return PType->getElementType();
453 else if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty))
454 if (isTypedPointerWrapper(ExtTy))
455 return ExtTy->getTypeParameter(i: 0);
456 }
457 return nullptr;
458}
459
460inline bool isUntypedEquivalentToTyExt(Type *Ty1, Type *Ty2) {
461 if (!isUntypedPointerTy(T: Ty1) || !Ty2)
462 return false;
463 if (auto *ExtTy = dyn_cast<TargetExtType>(Val: Ty2))
464 if (isTypedPointerWrapper(ExtTy) &&
465 ExtTy->getTypeParameter(i: 0) ==
466 IntegerType::getInt8Ty(C&: Ty1->getContext()) &&
467 ExtTy->getIntParameter(i: 0) == cast<PointerType>(Val: Ty1)->getAddressSpace())
468 return true;
469 return false;
470}
471
472inline bool isEquivalentTypes(Type *Ty1, Type *Ty2) {
473 return isUntypedEquivalentToTyExt(Ty1, Ty2) ||
474 isUntypedEquivalentToTyExt(Ty1: Ty2, Ty2: Ty1);
475}
476
477inline Type *toTypedPointer(Type *Ty) {
478 if (Type *NewTy = applyWrappers(Ty); NewTy != Ty)
479 return NewTy;
480 return isUntypedPointerTy(T: Ty)
481 ? TypedPointerType::get(ElementType: IntegerType::getInt8Ty(C&: Ty->getContext()),
482 AddressSpace: getPointerAddressSpace(T: Ty))
483 : Ty;
484}
485
486inline Type *toTypedFunPointer(FunctionType *FTy) {
487 Type *OrigRetTy = FTy->getReturnType();
488 Type *RetTy = toTypedPointer(Ty: OrigRetTy);
489 bool IsUntypedPtr = false;
490 for (Type *PTy : FTy->params()) {
491 if (isUntypedPointerTy(T: PTy)) {
492 IsUntypedPtr = true;
493 break;
494 }
495 }
496 if (!IsUntypedPtr && RetTy == OrigRetTy)
497 return FTy;
498 SmallVector<Type *> ParamTys;
499 for (Type *PTy : FTy->params())
500 ParamTys.push_back(Elt: toTypedPointer(Ty: PTy));
501 return FunctionType::get(Result: RetTy, Params: ParamTys, isVarArg: FTy->isVarArg());
502}
503
504inline const Type *unifyPtrType(const Type *Ty) {
505 if (auto FTy = dyn_cast<FunctionType>(Val: Ty))
506 return toTypedFunPointer(FTy: const_cast<FunctionType *>(FTy));
507 return toTypedPointer(Ty: const_cast<Type *>(Ty));
508}
509
510inline bool isVector1(Type *Ty) {
511 auto *FVTy = dyn_cast<FixedVectorType>(Val: Ty);
512 return FVTy && FVTy->getNumElements() == 1;
513}
514
515// We define this predicate out of line to avoid having to include all OpTypes.
516bool isVectorType(SPIRVTypeInst SPVTy);
517
518// Per spec: "Vector types must be parameterized only with 2, 3, or
519// 4 components, plus any additional sizes enabled by capabilities.", and
520// we always enable the Vector16 capability.
521inline bool requiresLongVectorEXT(unsigned NumComponents) {
522 return NumComponents != 2 && NumComponents != 3 && NumComponents != 4 &&
523 NumComponents != 8 && NumComponents != 16;
524}
525
526inline bool isLongVectorEXT(const Type *Ty) {
527 if (auto *FVTy = dyn_cast<FixedVectorType>(Val: Ty))
528 return requiresLongVectorEXT(NumComponents: FVTy->getNumElements());
529 return false;
530}
531
532// Modify an LLVM type to conform with future transformations in IRTranslator.
533// At the moment use cases comprise only a <1 x Type> vector. To extend when/if
534// needed.
535inline Type *normalizeType(Type *Ty, bool CanUseAnyVectorRank) {
536 if (CanUseAnyVectorRank)
537 return Ty;
538
539 auto *FVTy = dyn_cast<FixedVectorType>(Val: Ty);
540 if (!FVTy || FVTy->getNumElements() != 1)
541 return Ty;
542 // If it's a <1 x Type> vector type, replace it by the element type, because
543 // it's not a legal vector type in LLT and IRTranslator will represent it as
544 // the scalar eventually.
545 return normalizeType(Ty: FVTy->getElementType(), CanUseAnyVectorRank);
546}
547
548inline PoisonValue *getNormalizedPoisonValue(Type *Ty,
549 bool CanUseAnyVectorRank) {
550 return PoisonValue::get(T: normalizeType(Ty, CanUseAnyVectorRank));
551}
552
553inline MetadataAsValue *buildMD(Value *Arg) {
554 LLVMContext &Ctx = Arg->getContext();
555 return MetadataAsValue::get(
556 Context&: Ctx, MD: MDNode::get(Context&: Ctx, MDs: ValueAsMetadata::getConstant(C: Arg)));
557}
558
559CallInst *buildIntrWithMD(Intrinsic::ID IntrID, ArrayRef<Type *> Types,
560 Value *Arg, Value *Arg2, ArrayRef<Constant *> Imms,
561 IRBuilder<> &B);
562
563MachineInstr *getVRegDef(MachineRegisterInfo &MRI, Register Reg);
564
565#define SPIRV_BACKEND_SERVICE_FUN_NAME "__spirv_backend_service_fun"
566#define SPIRV_WAS_AVAILABLE_EXTERNALLY_ATTR "spv.was-available-externally"
567
568void setRegClassType(Register Reg, const Type *Ty, SPIRVGlobalRegistry *GR,
569 MachineIRBuilder &MIRBuilder,
570 SPIRV::AccessQualifier::AccessQualifier AccessQual,
571 bool EmitIR, bool Force = false);
572void setRegClassType(Register Reg, SPIRVTypeInst SpvType,
573 SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI,
574 const MachineFunction &MF, bool Force = false);
575Register createVirtualRegister(SPIRVTypeInst SpvType, SPIRVGlobalRegistry *GR,
576 MachineRegisterInfo *MRI,
577 const MachineFunction &MF);
578Register createVirtualRegister(SPIRVTypeInst SpvType, SPIRVGlobalRegistry *GR,
579 MachineIRBuilder &MIRBuilder);
580Register createVirtualRegister(
581 const Type *Ty, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIRBuilder,
582 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR);
583
584// Return true if there is an opaque pointer type nested in the argument.
585bool isNestedPointer(const Type *Ty);
586
587enum FPDecorationId { NONE, RTE, RTZ, RTP, RTN, SAT };
588
589inline FPDecorationId demangledPostfixToDecorationId(const std::string &S) {
590 static const StringMap<FPDecorationId> Mapping = {
591 {"rte", FPDecorationId::RTE},
592 {"rtz", FPDecorationId::RTZ},
593 {"rtp", FPDecorationId::RTP},
594 {"rtn", FPDecorationId::RTN},
595 {"sat", FPDecorationId::SAT}};
596 auto It = Mapping.find(Key: S);
597 return It == Mapping.end() ? FPDecorationId::NONE : It->second;
598}
599
600SmallVector<MachineInstr *, 4>
601createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode,
602 unsigned MinWC, unsigned ContinuedOpcode,
603 ArrayRef<Register> Args, Register ReturnRegister,
604 Register TypeID);
605
606// Instruction selection directed by type folding.
607const std::set<unsigned> &getTypeFoldingSupportedOpcodes();
608bool isTypeFoldingSupported(unsigned Opcode);
609
610// Get loop controls from llvm.loop. metadata.
611SmallVector<unsigned, 1> getSpirvLoopControlOperandsFromLoopMetadata(Loop *L);
612SmallVector<unsigned, 1>
613getSpirvLoopControlOperandsFromLoopMetadata(MDNode *LoopMD);
614
615// Traversing [g]MIR accounting for pseudo-instructions.
616MachineInstr *passCopy(MachineInstr *Def, const MachineRegisterInfo *MRI);
617MachineInstr *getDef(const MachineOperand &MO, const MachineRegisterInfo *MRI);
618MachineInstr *getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI);
619int64_t foldImm(const MachineOperand &MO, const MachineRegisterInfo *MRI);
620unsigned getArrayComponentCount(const MachineRegisterInfo *MRI,
621 const MachineInstr *ResType);
622
623std::optional<SPIRV::LinkageType::LinkageType>
624getSpirvLinkageTypeFor(const SPIRVSubtarget &ST, const GlobalValue &GV);
625Function *getOrCreateBackendServiceFunction(Module &M);
626} // namespace llvm
627#endif // LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
628