1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
15#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16
17#include "Sparc.h"
18#include "llvm/CodeGen/TargetLowering.h"
19
20namespace llvm {
21 class SparcSubtarget;
22
23 class SparcTargetLowering : public TargetLowering {
24 const SparcSubtarget *Subtarget;
25 public:
26 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
27 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
28
29 bool useSoftFloat() const override;
30
31 /// computeKnownBitsForTargetNode - Determine which of the bits specified
32 /// in Mask are known to be either zero or one and return them in the
33 /// KnownZero/KnownOne bitsets.
34 void computeKnownBitsForTargetNode(const SDValue Op,
35 KnownBits &Known,
36 const APInt &DemandedElts,
37 const SelectionDAG &DAG,
38 unsigned Depth = 0) const override;
39
40 MachineBasicBlock *
41 EmitInstrWithCustomInserter(MachineInstr &MI,
42 MachineBasicBlock *MBB) const override;
43
44 ConstraintType getConstraintType(StringRef Constraint) const override;
45 ConstraintWeight
46 getSingleConstraintMatchWeight(AsmOperandInfo &info,
47 const char *constraint) const override;
48 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
49 std::vector<SDValue> &Ops,
50 SelectionDAG &DAG) const override;
51
52 std::pair<unsigned, const TargetRegisterClass *>
53 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
54 StringRef Constraint, MVT VT) const override;
55
56 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
57 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
58 return MVT::i32;
59 }
60
61 Register getRegisterByName(const char* RegName, LLT VT,
62 const MachineFunction &MF) const override;
63
64 /// If a physical register, this returns the register that receives the
65 /// exception address on entry to an EH pad.
66 Register
67 getExceptionPointerRegister(ExceptionHandling EH,
68 const Constant *PersonalityFn) const override {
69 return SP::I0;
70 }
71
72 /// If a physical register, this returns the register that receives the
73 /// exception typeid on entry to a landing pad.
74 Register
75 getExceptionSelectorRegister(ExceptionHandling EH,
76 const Constant *PersonalityFn) const override {
77 return SP::I1;
78 }
79
80 /// Override to support customized stack guard loading.
81 bool useLoadStackGuardNode(const Module &M) const override;
82
83 /// getSetCCResultType - Return the ISD::SETCC ValueType
84 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
85 EVT VT) const override;
86
87 SDValue
88 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
89 const SmallVectorImpl<ISD::InputArg> &Ins,
90 const SDLoc &dl, SelectionDAG &DAG,
91 SmallVectorImpl<SDValue> &InVals) const override;
92 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
93 bool isVarArg,
94 const SmallVectorImpl<ISD::InputArg> &Ins,
95 const SDLoc &dl, SelectionDAG &DAG,
96 SmallVectorImpl<SDValue> &InVals) const;
97 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
98 bool isVarArg,
99 const SmallVectorImpl<ISD::InputArg> &Ins,
100 const SDLoc &dl, SelectionDAG &DAG,
101 SmallVectorImpl<SDValue> &InVals) const;
102
103 SDValue
104 LowerCall(TargetLowering::CallLoweringInfo &CLI,
105 SmallVectorImpl<SDValue> &InVals) const override;
106 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
107 SmallVectorImpl<SDValue> &InVals) const;
108 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
109 SmallVectorImpl<SDValue> &InVals) const;
110
111 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
112 bool isVarArg,
113 const SmallVectorImpl<ISD::OutputArg> &Outs,
114 LLVMContext &Context, const Type *RetTy) const override;
115
116 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
117 const SmallVectorImpl<ISD::OutputArg> &Outs,
118 const SmallVectorImpl<SDValue> &OutVals,
119 const SDLoc &dl, SelectionDAG &DAG) const override;
120 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
121 bool IsVarArg,
122 const SmallVectorImpl<ISD::OutputArg> &Outs,
123 const SmallVectorImpl<SDValue> &OutVals,
124 const SDLoc &DL, SelectionDAG &DAG) const;
125 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
126 bool IsVarArg,
127 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<SDValue> &OutVals,
129 const SDLoc &DL, SelectionDAG &DAG) const;
130
131 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
135
136 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
137 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
138 SelectionDAG &DAG) const;
139 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
140
141 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
142 const SDLoc &DL, SelectionDAG &DAG) const;
143 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall LibFunc,
144 unsigned numArgs) const;
145 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
146 const SDLoc &DL, SelectionDAG &DAG) const;
147
148 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
149
150 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
151
152 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
153 SDValue PerformBSWAPCombine(SDNode *N, DAGCombinerInfo &DCI) const;
154 SDValue PerformSTORECombine(SDNode *N, DAGCombinerInfo &DCI) const;
155
156 SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
157 SelectionDAG &DAG) const;
158
159 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
160
161 bool IsEligibleForTailCallOptimization(CCState &CCInfo,
162 CallLoweringInfo &CLI,
163 MachineFunction &MF) const;
164
165 bool ShouldShrinkFPConstant(EVT VT) const override {
166 // Do not shrink FP constpool if VT == MVT::f128.
167 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
168 return VT != MVT::f128;
169 }
170
171 bool isFNegFree(EVT VT) const override;
172
173 bool isFPImmLegal(const APFloat &Imm, EVT VT,
174 bool ForCodeSize) const override;
175
176 bool isCtlzFast() const override;
177
178 bool isCheapToSpeculateCtlz(Type *Ty) const override {
179 return isCtlzFast();
180 }
181
182 bool isCheapToSpeculateCttz(Type *Ty) const override;
183
184 bool enableAggressiveFMAFusion(EVT VT) const override { return true; };
185
186 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
187 EVT VT) const override;
188
189 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
190 AtomicOrdering Ord) const override;
191 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
192 AtomicOrdering Ord) const override;
193
194 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
195 // FIXME: We insert fences for each atomics and generate
196 // sub-optimal code for PSO/TSO. (Approximately nobody uses any
197 // mode but TSO, which makes this even more silly)
198 return true;
199 }
200
201 AtomicExpansionKind
202 shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override;
203
204 void ReplaceNodeResults(SDNode *N,
205 SmallVectorImpl<SDValue>& Results,
206 SelectionDAG &DAG) const override;
207
208 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
209 unsigned BROpcode) const;
210
211 void AdjustInstrPostInstrSelection(MachineInstr &MI,
212 SDNode *Node) const override;
213 };
214} // end namespace llvm
215
216#endif // LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
217