1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
15#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16
17#include "Sparc.h"
18#include "llvm/CodeGen/TargetLowering.h"
19
20namespace llvm {
21 class SparcSubtarget;
22
23 class SparcTargetLowering : public TargetLowering {
24 const SparcSubtarget *Subtarget;
25 public:
26 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
27 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
28
29 bool useSoftFloat() const override;
30
31 /// computeKnownBitsForTargetNode - Determine which of the bits specified
32 /// in Mask are known to be either zero or one and return them in the
33 /// KnownZero/KnownOne bitsets.
34 void computeKnownBitsForTargetNode(const SDValue Op,
35 KnownBits &Known,
36 const APInt &DemandedElts,
37 const SelectionDAG &DAG,
38 unsigned Depth = 0) const override;
39
40 MachineBasicBlock *
41 EmitInstrWithCustomInserter(MachineInstr &MI,
42 MachineBasicBlock *MBB) const override;
43
44 ConstraintType getConstraintType(StringRef Constraint) const override;
45 ConstraintWeight
46 getSingleConstraintMatchWeight(AsmOperandInfo &info,
47 const char *constraint) const override;
48 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
49 std::vector<SDValue> &Ops,
50 SelectionDAG &DAG) const override;
51
52 std::pair<unsigned, const TargetRegisterClass *>
53 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
54 StringRef Constraint, MVT VT) const override;
55
56 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
57 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
58 return MVT::i32;
59 }
60
61 Register getRegisterByName(const char* RegName, LLT VT,
62 const MachineFunction &MF) const override;
63
64 /// If a physical register, this returns the register that receives the
65 /// exception address on entry to an EH pad.
66 Register
67 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
68 return SP::I0;
69 }
70
71 /// If a physical register, this returns the register that receives the
72 /// exception typeid on entry to a landing pad.
73 Register
74 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
75 return SP::I1;
76 }
77
78 /// Override to support customized stack guard loading.
79 bool useLoadStackGuardNode(const Module &M) const override;
80
81 /// getSetCCResultType - Return the ISD::SETCC ValueType
82 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
83 EVT VT) const override;
84
85 SDValue
86 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
87 const SmallVectorImpl<ISD::InputArg> &Ins,
88 const SDLoc &dl, SelectionDAG &DAG,
89 SmallVectorImpl<SDValue> &InVals) const override;
90 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
91 bool isVarArg,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
93 const SDLoc &dl, SelectionDAG &DAG,
94 SmallVectorImpl<SDValue> &InVals) const;
95 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
96 bool isVarArg,
97 const SmallVectorImpl<ISD::InputArg> &Ins,
98 const SDLoc &dl, SelectionDAG &DAG,
99 SmallVectorImpl<SDValue> &InVals) const;
100
101 SDValue
102 LowerCall(TargetLowering::CallLoweringInfo &CLI,
103 SmallVectorImpl<SDValue> &InVals) const override;
104 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
105 SmallVectorImpl<SDValue> &InVals) const;
106 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
107 SmallVectorImpl<SDValue> &InVals) const;
108
109 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
110 bool isVarArg,
111 const SmallVectorImpl<ISD::OutputArg> &Outs,
112 LLVMContext &Context, const Type *RetTy) const override;
113
114 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
115 const SmallVectorImpl<ISD::OutputArg> &Outs,
116 const SmallVectorImpl<SDValue> &OutVals,
117 const SDLoc &dl, SelectionDAG &DAG) const override;
118 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
119 bool IsVarArg,
120 const SmallVectorImpl<ISD::OutputArg> &Outs,
121 const SmallVectorImpl<SDValue> &OutVals,
122 const SDLoc &DL, SelectionDAG &DAG) const;
123 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
124 bool IsVarArg,
125 const SmallVectorImpl<ISD::OutputArg> &Outs,
126 const SmallVectorImpl<SDValue> &OutVals,
127 const SDLoc &DL, SelectionDAG &DAG) const;
128
129 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
133
134 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
135 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
136 SelectionDAG &DAG) const;
137 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
138
139 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
140 const SDLoc &DL, SelectionDAG &DAG) const;
141 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall LibFunc,
142 unsigned numArgs) const;
143 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
144 const SDLoc &DL, SelectionDAG &DAG) const;
145
146 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
147
148 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
149
150 SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
151 SelectionDAG &DAG) const;
152
153 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
154
155 bool IsEligibleForTailCallOptimization(CCState &CCInfo,
156 CallLoweringInfo &CLI,
157 MachineFunction &MF) const;
158
159 bool ShouldShrinkFPConstant(EVT VT) const override {
160 // Do not shrink FP constpool if VT == MVT::f128.
161 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
162 return VT != MVT::f128;
163 }
164
165 bool isFNegFree(EVT VT) const override;
166
167 bool isFPImmLegal(const APFloat &Imm, EVT VT,
168 bool ForCodeSize) const override;
169
170 bool isCtlzFast() const override;
171
172 bool isCheapToSpeculateCtlz(Type *Ty) const override {
173 return isCtlzFast();
174 }
175
176 bool isCheapToSpeculateCttz(Type *Ty) const override;
177
178 bool enableAggressiveFMAFusion(EVT VT) const override { return true; };
179
180 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
181 EVT VT) const override;
182
183 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
184 AtomicOrdering Ord) const override;
185 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
186 AtomicOrdering Ord) const override;
187
188 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
189 // FIXME: We insert fences for each atomics and generate
190 // sub-optimal code for PSO/TSO. (Approximately nobody uses any
191 // mode but TSO, which makes this even more silly)
192 return true;
193 }
194
195 AtomicExpansionKind
196 shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override;
197
198 void ReplaceNodeResults(SDNode *N,
199 SmallVectorImpl<SDValue>& Results,
200 SelectionDAG &DAG) const override;
201
202 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
203 unsigned BROpcode) const;
204
205 void AdjustInstrPostInstrSelection(MachineInstr &MI,
206 SDNode *Node) const override;
207 };
208} // end namespace llvm
209
210#endif // LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
211