1//===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Sparc implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
14#define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
15
16#include "SparcRegisterInfo.h"
17#include "llvm/CodeGen/TargetInstrInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "SparcGenInstrInfo.inc"
21
22namespace llvm {
23
24class SparcSubtarget;
25
26/// SPII - This namespace holds all of the target specific flags that
27/// instruction info tracks.
28///
29namespace SPII {
30 enum {
31 Pseudo = (1<<0),
32 Load = (1<<1),
33 Store = (1<<2),
34 DelaySlot = (1<<3)
35 };
36}
37
38class SparcInstrInfo : public SparcGenInstrInfo {
39 const SparcRegisterInfo RI;
40 const SparcSubtarget& Subtarget;
41 virtual void anchor();
42public:
43 explicit SparcInstrInfo(const SparcSubtarget &ST);
44
45 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
46 /// such, whenever a client has an instance of instruction info, it should
47 /// always be able to get register info as well (through this method).
48 ///
49 const SparcRegisterInfo &getRegisterInfo() const { return RI; }
50
51 const TargetRegisterClass *
52 getInlineAsmMemoryOperandRegClass(InlineAsm::ConstraintCode C) const override;
53
54 /// isLoadFromStackSlot - If the specified machine instruction is a direct
55 /// load from a stack slot, return the virtual or physical register number of
56 /// the destination along with the FrameIndex of the loaded stack slot. If
57 /// not, return 0. This predicate must return 0 if the instruction has
58 /// any side effects other than loading from the stack slot.
59 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
60 TypeSize &MemBytes) const override;
61
62 /// isStoreToStackSlot - If the specified machine instruction is a direct
63 /// store to a stack slot, return the virtual or physical register number of
64 /// the source reg along with the FrameIndex of the loaded stack slot. If
65 /// not, return 0. This predicate must return 0 if the instruction has
66 /// any side effects other than storing to the stack slot.
67 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
68 TypeSize &MemBytes) const override;
69
70 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
71
72 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
73 MachineBasicBlock *&FBB,
74 SmallVectorImpl<MachineOperand> &Cond,
75 bool AllowModify = false) const override;
76
77 unsigned removeBranch(MachineBasicBlock &MBB,
78 int *BytesRemoved = nullptr) const override;
79
80 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
81 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
82 const DebugLoc &DL,
83 int *BytesAdded = nullptr) const override;
84
85 bool
86 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
87
88 /// Determine if the branch target is in range.
89 bool isBranchOffsetInRange(unsigned BranchOpc, int64_t Offset) const override;
90
91 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
92 const DebugLoc &DL, Register DestReg, Register SrcReg,
93 bool KillSrc, bool RenamableDest = false,
94 bool RenamableSrc = false) const override;
95
96 void storeRegToStackSlot(
97 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
98 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
99 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
100
101 void loadRegFromStackSlot(
102 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
103 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
104 Register VReg, unsigned SubReg = 0,
105 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
106
107 Register getGlobalBaseReg(MachineFunction *MF) const;
108
109 /// GetInstSize - Return the number of bytes of code the specified
110 /// instruction may be. This returns the maximum number of bytes.
111 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
112
113 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
114 Register &SrcReg2, int64_t &CmpMask,
115 int64_t &CmpValue) const override;
116
117 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
118 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
119 const MachineRegisterInfo *MRI) const override;
120
121 // Lower pseudo instructions after register allocation.
122 bool expandPostRAPseudo(MachineInstr &MI) const override;
123
124 // Whether this is a call that needs unimp. Populates \p StructSize with
125 // the size of the returned struct.
126 bool needsUnimp(const MachineInstr &MI, unsigned &StructSize) const;
127};
128
129}
130
131#endif
132