1//===-- SparcTargetTransformInfo.cpp - SPARC specific TTI -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "SparcTargetTransformInfo.h"
10#include "llvm/Support/MathExtras.h"
11
12using namespace llvm;
13
14#define DEBUG_TYPE "sparctti"
15
16TargetTransformInfo::PopcntSupportKind
17SparcTTIImpl::getPopcntSupport(unsigned TyWidth) const {
18 assert(isPowerOf2_32(TyWidth) && "Type width must be power of 2");
19 if (ST->usePopc())
20 return TTI::PSK_FastHardware;
21 return TTI::PSK_Software;
22}
23
24unsigned SparcTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const {
25 if (Vector)
26 return VRRC;
27 if (Ty &&
28 (Ty->getScalarType()->isFloatTy() || Ty->getScalarType()->isDoubleTy()))
29 return FPRRC;
30 if (Ty && (Ty->getScalarType()->isFP128Ty()))
31 return FP128RRC;
32 return GPRRC;
33}
34
35unsigned SparcTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
36 switch (ClassID) {
37 case GPRRC:
38 // %g0, %g6, %g7, %o6, %i6, and %i7 are used for special purposes so we
39 // discount them here.
40 return 26;
41 case FPRRC:
42 return 32;
43 case FP128RRC:
44 return 16;
45 case VRRC:
46 // TODO We have vector capabilities as part of the VIS extensions, but the
47 // codegen doesn't currently use it. Revisit this when vector codegen is
48 // ready.
49 return 0;
50 }
51
52 llvm_unreachable("Unsupported register class");
53}
54
55TypeSize
56SparcTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
57 switch (K) {
58 case TargetTransformInfo::RGK_Scalar:
59 // TODO When targeting V8+ ABI, G and O registers are 64-bit.
60 return TypeSize::getFixed(ExactSize: ST->is64Bit() ? 64 : 32);
61 case TargetTransformInfo::RGK_FixedWidthVector:
62 // TODO We have vector capabilities as part of the VIS extensions, but the
63 // codegen doesn't currently use it. Revisit this when vector codegen is
64 // ready.
65 return TypeSize::getFixed(ExactSize: 0);
66 case TargetTransformInfo::RGK_ScalableVector:
67 return TypeSize::getScalable(MinimumSize: 0);
68 }
69
70 llvm_unreachable("Unsupported register kind");
71}
72