1//===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "SystemZTargetMachine.h"
10#include "MCTargetDesc/SystemZMCTargetDesc.h"
11#include "SystemZ.h"
12#include "SystemZMachineFunctionInfo.h"
13#include "SystemZMachineScheduler.h"
14#include "SystemZTargetObjectFile.h"
15#include "SystemZTargetTransformInfo.h"
16#include "TargetInfo/SystemZTargetInfo.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/Analysis/TargetTransformInfo.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
21#include "llvm/CodeGen/TargetPassConfig.h"
22#include "llvm/IR/DataLayout.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/CodeGen.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Target/TargetLoweringObjectFile.h"
27#include "llvm/Transforms/Scalar.h"
28#include <memory>
29#include <optional>
30#include <string>
31
32using namespace llvm;
33
34static cl::opt<bool> EnableMachineCombinerPass(
35 "systemz-machine-combiner",
36 cl::desc("Enable the machine combiner pass"),
37 cl::init(Val: true), cl::Hidden);
38
39static cl::opt<bool> GenericSched(
40 "generic-sched", cl::Hidden, cl::init(Val: false),
41 cl::desc("Run the generic pre-ra scheduler instead of the SystemZ "
42 "scheduler."));
43
44// NOLINTNEXTLINE(readability-identifier-naming)
45extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
46LLVMInitializeSystemZTarget() {
47 // Register the target.
48 RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
49 auto &PR = *PassRegistry::getPassRegistry();
50 initializeSystemZAsmPrinterPass(PR);
51 initializeSystemZElimComparePass(PR);
52 initializeSystemZShortenInstPass(PR);
53 initializeSystemZLongBranchPass(PR);
54 initializeSystemZLDCleanupPass(PR);
55 initializeSystemZShortenInstPass(PR);
56 initializeSystemZPostRewritePass(PR);
57 initializeSystemZTDCPassPass(PR);
58 initializeSystemZDAGToDAGISelLegacyPass(PR);
59 initializeSystemZCopyPhysRegsPass(PR);
60}
61
62static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
63 if (TT.isOSzOS())
64 return std::make_unique<TargetLoweringObjectFileGOFF>();
65
66 // Note: Some times run with -triple s390x-unknown.
67 // In this case, default to ELF unless z/OS specifically provided.
68 return std::make_unique<SystemZELFTargetObjectFile>();
69}
70
71static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
72 // Static code is suitable for use in a dynamic executable; there is no
73 // separate DynamicNoPIC model.
74 if (!RM || *RM == Reloc::DynamicNoPIC)
75 return Reloc::Static;
76 return *RM;
77}
78
79// For SystemZ we define the models as follows:
80//
81// Small: BRASL can call any function and will use a stub if necessary.
82// Locally-binding symbols will always be in range of LARL.
83//
84// Medium: BRASL can call any function and will use a stub if necessary.
85// GOT slots and locally-defined text will always be in range
86// of LARL, but other symbols might not be.
87//
88// Large: Equivalent to Medium for now.
89//
90// Kernel: Equivalent to Medium for now.
91//
92// This means that any PIC module smaller than 4GB meets the
93// requirements of Small, so Small seems like the best default there.
94//
95// All symbols bind locally in a non-PIC module, so the choice is less
96// obvious. There are two cases:
97//
98// - When creating an executable, PLTs and copy relocations allow
99// us to treat external symbols as part of the executable.
100// Any executable smaller than 4GB meets the requirements of Small,
101// so that seems like the best default.
102//
103// - When creating JIT code, stubs will be in range of BRASL if the
104// image is less than 4GB in size. GOT entries will likewise be
105// in range of LARL. However, the JIT environment has no equivalent
106// of copy relocs, so locally-binding data symbols might not be in
107// the range of LARL. We need the Medium model in that case.
108static CodeModel::Model
109getEffectiveSystemZCodeModel(std::optional<CodeModel::Model> CM,
110 Reloc::Model RM, bool JIT) {
111 if (CM) {
112 if (*CM == CodeModel::Tiny)
113 report_fatal_error(reason: "Target does not support the tiny CodeModel", gen_crash_diag: false);
114 if (*CM == CodeModel::Kernel)
115 report_fatal_error(reason: "Target does not support the kernel CodeModel", gen_crash_diag: false);
116 return *CM;
117 }
118 if (JIT)
119 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
120 return CodeModel::Small;
121}
122
123SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
124 StringRef CPU, StringRef FS,
125 const TargetOptions &Options,
126 std::optional<Reloc::Model> RM,
127 std::optional<CodeModel::Model> CM,
128 CodeGenOptLevel OL, bool JIT)
129 : CodeGenTargetMachineImpl(
130 T, TT.computeDataLayout(), TT, CPU, FS, Options,
131 getEffectiveRelocModel(RM),
132 getEffectiveSystemZCodeModel(CM, RM: getEffectiveRelocModel(RM), JIT),
133 OL),
134 TLOF(createTLOF(TT: getTargetTriple())) {
135 initAsmInfo();
136}
137
138SystemZTargetMachine::~SystemZTargetMachine() = default;
139
140const SystemZSubtarget *
141SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
142 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
143 Attribute TuneAttr = F.getFnAttribute(Kind: "tune-cpu");
144 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
145
146 std::string CPU =
147 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
148 std::string TuneCPU =
149 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
150 std::string FS =
151 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
152
153 // FIXME: This is related to the code below to reset the target options,
154 // we need to know whether the soft float and backchain flags are set on the
155 // function, so we can enable them as subtarget features.
156 bool SoftFloat = F.getFnAttribute(Kind: "use-soft-float").getValueAsBool();
157 if (SoftFloat)
158 FS += FS.empty() ? "+soft-float" : ",+soft-float";
159 bool BackChain = F.hasFnAttribute(Kind: "backchain");
160 if (BackChain)
161 FS += FS.empty() ? "+backchain" : ",+backchain";
162
163 auto &I = SubtargetMap[CPU + TuneCPU + FS];
164 if (!I) {
165 I = std::make_unique<SystemZSubtarget>(args: TargetTriple, args&: CPU, args&: TuneCPU, args&: FS,
166 args: *this);
167 }
168
169 return I.get();
170}
171
172ScheduleDAGInstrs *
173SystemZTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
174 // Use GenericScheduler if requested on CL or for Z10 which has no sched
175 // model.
176 if (GenericSched ||
177 !C->MF->getSubtarget().getSchedModel().hasInstrSchedModel())
178 return nullptr;
179
180 return createSchedLive<SystemZPreRASchedStrategy>(C);
181}
182
183ScheduleDAGInstrs *
184SystemZTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
185 return createSchedPostRA<SystemZPostRASchedStrategy>(C);
186}
187
188namespace {
189
190/// SystemZ Code Generator Pass Configuration Options.
191class SystemZPassConfig : public TargetPassConfig {
192public:
193 SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
194 : TargetPassConfig(TM, PM) {}
195
196 SystemZTargetMachine &getSystemZTargetMachine() const {
197 return getTM<SystemZTargetMachine>();
198 }
199
200 void addIRPasses() override;
201 bool addInstSelector() override;
202 bool addILPOpts() override;
203 void addPreRegAlloc() override;
204 void addPostRewrite() override;
205 void addPostRegAlloc() override;
206 void addPreSched2() override;
207 void addPreEmitPass() override;
208};
209
210} // end anonymous namespace
211
212void SystemZPassConfig::addIRPasses() {
213 if (getOptLevel() != CodeGenOptLevel::None) {
214 addPass(P: createSystemZTDCPass());
215 addPass(P: createLoopDataPrefetchPass());
216 }
217
218 addPass(P: createAtomicExpandLegacyPass());
219
220 TargetPassConfig::addIRPasses();
221}
222
223bool SystemZPassConfig::addInstSelector() {
224 addPass(P: createSystemZISelDag(TM&: getSystemZTargetMachine(), OptLevel: getOptLevel()));
225
226 if (getOptLevel() != CodeGenOptLevel::None)
227 addPass(P: createSystemZLDCleanupPass(TM&: getSystemZTargetMachine()));
228
229 return false;
230}
231
232bool SystemZPassConfig::addILPOpts() {
233 addPass(PassID: &EarlyIfConverterLegacyID);
234
235 if (EnableMachineCombinerPass)
236 addPass(PassID: &MachineCombinerID);
237
238 return true;
239}
240
241void SystemZPassConfig::addPreRegAlloc() {
242 addPass(P: createSystemZCopyPhysRegsPass(TM&: getSystemZTargetMachine()));
243}
244
245void SystemZPassConfig::addPostRewrite() {
246 addPass(P: createSystemZPostRewritePass(TM&: getSystemZTargetMachine()));
247}
248
249void SystemZPassConfig::addPostRegAlloc() {
250 // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
251 // is not called).
252 if (getOptLevel() == CodeGenOptLevel::None)
253 addPass(P: createSystemZPostRewritePass(TM&: getSystemZTargetMachine()));
254}
255
256void SystemZPassConfig::addPreSched2() {
257 if (getOptLevel() != CodeGenOptLevel::None)
258 addPass(PassID: &IfConverterID);
259}
260
261void SystemZPassConfig::addPreEmitPass() {
262 // Do instruction shortening before compare elimination because some
263 // vector instructions will be shortened into opcodes that compare
264 // elimination recognizes.
265 if (getOptLevel() != CodeGenOptLevel::None)
266 addPass(P: createSystemZShortenInstPass(TM&: getSystemZTargetMachine()));
267
268 // We eliminate comparisons here rather than earlier because some
269 // transformations can change the set of available CC values and we
270 // generally want those transformations to have priority. This is
271 // especially true in the commonest case where the result of the comparison
272 // is used by a single in-range branch instruction, since we will then
273 // be able to fuse the compare and the branch instead.
274 //
275 // For example, two-address NILF can sometimes be converted into
276 // three-address RISBLG. NILF produces a CC value that indicates whether
277 // the low word is zero, but RISBLG does not modify CC at all. On the
278 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
279 // The CC value produced by NILL isn't useful for our purposes, but the
280 // value produced by RISBG can be used for any comparison with zero
281 // (not just equality). So there are some transformations that lose
282 // CC values (while still being worthwhile) and others that happen to make
283 // the CC result more useful than it was originally.
284 //
285 // Another reason is that we only want to use BRANCH ON COUNT in cases
286 // where we know that the count register is not going to be spilled.
287 //
288 // Doing it so late makes it more likely that a register will be reused
289 // between the comparison and the branch, but it isn't clear whether
290 // preventing that would be a win or not.
291 if (getOptLevel() != CodeGenOptLevel::None)
292 addPass(P: createSystemZElimComparePass(TM&: getSystemZTargetMachine()));
293 addPass(P: createSystemZLongBranchPass(TM&: getSystemZTargetMachine()));
294
295 // Do final scheduling after all other optimizations, to get an
296 // optimal input for the decoder (branch relaxation must happen
297 // after block placement).
298 if (getOptLevel() != CodeGenOptLevel::None)
299 addPass(PassID: &PostMachineSchedulerID);
300}
301
302TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
303 return new SystemZPassConfig(*this, PM);
304}
305
306TargetTransformInfo
307SystemZTargetMachine::getTargetTransformInfo(const Function &F) const {
308 return TargetTransformInfo(std::make_unique<SystemZTTIImpl>(args: this, args: F));
309}
310
311MachineFunctionInfo *SystemZTargetMachine::createMachineFunctionInfo(
312 BumpPtrAllocator &Allocator, const Function &F,
313 const TargetSubtargetInfo *STI) const {
314 return SystemZMachineFunctionInfo::create<SystemZMachineFunctionInfo>(
315 Allocator, F, STI);
316}
317