1//===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "SystemZTargetMachine.h"
10#include "MCTargetDesc/SystemZMCTargetDesc.h"
11#include "SystemZ.h"
12#include "SystemZMachineFunctionInfo.h"
13#include "SystemZMachineScheduler.h"
14#include "SystemZTargetObjectFile.h"
15#include "SystemZTargetTransformInfo.h"
16#include "TargetInfo/SystemZTargetInfo.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/Analysis/TargetTransformInfo.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
21#include "llvm/CodeGen/TargetPassConfig.h"
22#include "llvm/IR/DataLayout.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/CodeGen.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Target/TargetLoweringObjectFile.h"
27#include "llvm/Transforms/Scalar.h"
28#include <memory>
29#include <optional>
30#include <string>
31
32using namespace llvm;
33
34static cl::opt<bool> EnableMachineCombinerPass(
35 "systemz-machine-combiner",
36 cl::desc("Enable the machine combiner pass"),
37 cl::init(Val: true), cl::Hidden);
38
39static cl::opt<bool> GenericSched(
40 "generic-sched", cl::Hidden, cl::init(Val: false),
41 cl::desc("Run the generic pre-ra scheduler instead of the SystemZ "
42 "scheduler."));
43
44// NOLINTNEXTLINE(readability-identifier-naming)
45extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
46LLVMInitializeSystemZTarget() {
47 // Register the target.
48 RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
49 auto &PR = *PassRegistry::getPassRegistry();
50 initializeSystemZAsmPrinterPass(PR);
51 initializeSystemZElimComparePass(PR);
52 initializeSystemZShortenInstPass(PR);
53 initializeSystemZLongBranchPass(PR);
54 initializeSystemZLDCleanupPass(PR);
55 initializeSystemZShortenInstPass(PR);
56 initializeSystemZPostRewritePass(PR);
57 initializeSystemZTDCPassPass(PR);
58 initializeSystemZDAGToDAGISelLegacyPass(PR);
59 initializeSystemZCopyPhysRegsPass(PR);
60}
61
62static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
63 if (TT.isOSzOS())
64 return std::make_unique<TargetLoweringObjectFileGOFF>();
65
66 // Note: Some times run with -triple s390x-unknown.
67 // In this case, default to ELF unless z/OS specifically provided.
68 return std::make_unique<SystemZELFTargetObjectFile>();
69}
70
71static Reloc::Model getEffectiveRelocModel(const Triple &TT,
72 std::optional<Reloc::Model> RM) {
73 if (TT.isOSzOS()) {
74 // On z/OS, constant globals whose initializers contain pointer relocations
75 // (e.g. vtables) must be placed in a writable section (C_WSA64) so the
76 // GOFF binder can apply them at link time. Using DynamicNoPIC causes
77 // getKindForGlobal() to classify such globals as ReadOnlyWithRel instead
78 // of ReadOnly, which routes them to C_WSA64 rather than C_CODE64.
79 if (!RM || *RM == Reloc::DynamicNoPIC)
80 return Reloc::DynamicNoPIC;
81 return *RM;
82 }
83 // For ELF/Linux, static code is suitable for use in a dynamic executable;
84 // there is no separate DynamicNoPIC model.
85 if (!RM || *RM == Reloc::DynamicNoPIC)
86 return Reloc::Static;
87 return *RM;
88}
89
90// For SystemZ we define the models as follows:
91//
92// Small: BRASL can call any function and will use a stub if necessary.
93// Locally-binding symbols will always be in range of LARL.
94//
95// Medium: BRASL can call any function and will use a stub if necessary.
96// GOT slots and locally-defined text will always be in range
97// of LARL, but other symbols might not be.
98//
99// Large: Equivalent to Medium for now.
100//
101// Kernel: Equivalent to Medium for now.
102//
103// This means that any PIC module smaller than 4GB meets the
104// requirements of Small, so Small seems like the best default there.
105//
106// All symbols bind locally in a non-PIC module, so the choice is less
107// obvious. There are two cases:
108//
109// - When creating an executable, PLTs and copy relocations allow
110// us to treat external symbols as part of the executable.
111// Any executable smaller than 4GB meets the requirements of Small,
112// so that seems like the best default.
113//
114// - When creating JIT code, stubs will be in range of BRASL if the
115// image is less than 4GB in size. GOT entries will likewise be
116// in range of LARL. However, the JIT environment has no equivalent
117// of copy relocs, so locally-binding data symbols might not be in
118// the range of LARL. We need the Medium model in that case.
119static CodeModel::Model
120getEffectiveSystemZCodeModel(std::optional<CodeModel::Model> CM,
121 Reloc::Model RM, bool JIT) {
122 if (CM) {
123 if (*CM == CodeModel::Tiny)
124 report_fatal_error(reason: "Target does not support the tiny CodeModel", gen_crash_diag: false);
125 if (*CM == CodeModel::Kernel)
126 report_fatal_error(reason: "Target does not support the kernel CodeModel", gen_crash_diag: false);
127 return *CM;
128 }
129 if (JIT)
130 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
131 return CodeModel::Small;
132}
133
134SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
135 StringRef CPU, StringRef FS,
136 const TargetOptions &Options,
137 std::optional<Reloc::Model> RM,
138 std::optional<CodeModel::Model> CM,
139 CodeGenOptLevel OL, bool JIT)
140 : CodeGenTargetMachineImpl(
141 T, TT.computeDataLayout(), TT, CPU, FS, Options,
142 getEffectiveRelocModel(TT, RM),
143 getEffectiveSystemZCodeModel(CM, RM: getEffectiveRelocModel(TT, RM), JIT),
144 OL),
145 TLOF(createTLOF(TT: getTargetTriple())) {
146 initAsmInfo();
147}
148
149SystemZTargetMachine::~SystemZTargetMachine() = default;
150
151const SystemZSubtarget *
152SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
153 Attribute CPUAttr = F.getFnAttribute(Kind: "target-cpu");
154 Attribute TuneAttr = F.getFnAttribute(Kind: "tune-cpu");
155 Attribute FSAttr = F.getFnAttribute(Kind: "target-features");
156
157 std::string CPU =
158 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
159 std::string TuneCPU =
160 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
161 std::string FS =
162 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
163
164 // FIXME: This is related to the code below to reset the target options,
165 // we need to know whether the soft float and backchain flags are set on the
166 // function, so we can enable them as subtarget features.
167 bool SoftFloat = F.getFnAttribute(Kind: "use-soft-float").getValueAsBool();
168 if (SoftFloat)
169 FS += FS.empty() ? "+soft-float" : ",+soft-float";
170 bool BackChain = F.hasFnAttribute(Kind: "backchain");
171 if (BackChain)
172 FS += FS.empty() ? "+backchain" : ",+backchain";
173
174 auto &I = SubtargetMap[CPU + TuneCPU + FS];
175 if (!I) {
176 I = std::make_unique<SystemZSubtarget>(args: TargetTriple, args&: CPU, args&: TuneCPU, args&: FS,
177 args: *this);
178 }
179
180 return I.get();
181}
182
183ScheduleDAGInstrs *
184SystemZTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
185 // Use GenericScheduler if requested on CL or for Z10 which has no sched
186 // model.
187 if (GenericSched ||
188 !C->MF->getSubtarget().getSchedModel().hasInstrSchedModel())
189 return nullptr;
190
191 return createSchedLive<SystemZPreRASchedStrategy>(C);
192}
193
194ScheduleDAGInstrs *
195SystemZTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
196 return createSchedPostRA<SystemZPostRASchedStrategy>(C);
197}
198
199namespace {
200
201/// SystemZ Code Generator Pass Configuration Options.
202class SystemZPassConfig : public TargetPassConfig {
203public:
204 SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
205 : TargetPassConfig(TM, PM) {}
206
207 SystemZTargetMachine &getSystemZTargetMachine() const {
208 return getTM<SystemZTargetMachine>();
209 }
210
211 void addIRPasses() override;
212 bool addInstSelector() override;
213 bool addILPOpts() override;
214 void addPreRegAlloc() override;
215 void addPostRewrite() override;
216 void addPostRegAlloc() override;
217 void addPreSched2() override;
218 void addPreEmitPass() override;
219};
220
221} // end anonymous namespace
222
223void SystemZPassConfig::addIRPasses() {
224 if (getOptLevel() != CodeGenOptLevel::None) {
225 addPass(P: createSystemZTDCPass());
226 addPass(P: createLoopDataPrefetchPass());
227 }
228
229 addPass(P: createAtomicExpandLegacyPass());
230
231 TargetPassConfig::addIRPasses();
232}
233
234bool SystemZPassConfig::addInstSelector() {
235 addPass(P: createSystemZISelDag(TM&: getSystemZTargetMachine(), OptLevel: getOptLevel()));
236
237 if (getOptLevel() != CodeGenOptLevel::None)
238 addPass(P: createSystemZLDCleanupPass(TM&: getSystemZTargetMachine()));
239
240 return false;
241}
242
243bool SystemZPassConfig::addILPOpts() {
244 addPass(PassID: &EarlyIfConverterLegacyID);
245
246 if (EnableMachineCombinerPass)
247 addPass(PassID: &MachineCombinerID);
248
249 return true;
250}
251
252void SystemZPassConfig::addPreRegAlloc() {
253 addPass(P: createSystemZCopyPhysRegsPass(TM&: getSystemZTargetMachine()));
254}
255
256void SystemZPassConfig::addPostRewrite() {
257 addPass(P: createSystemZPostRewritePass(TM&: getSystemZTargetMachine()));
258}
259
260void SystemZPassConfig::addPostRegAlloc() {
261 // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
262 // is not called).
263 if (getOptLevel() == CodeGenOptLevel::None)
264 addPass(P: createSystemZPostRewritePass(TM&: getSystemZTargetMachine()));
265}
266
267void SystemZPassConfig::addPreSched2() {
268 if (getOptLevel() != CodeGenOptLevel::None)
269 addPass(PassID: &IfConverterID);
270}
271
272void SystemZPassConfig::addPreEmitPass() {
273 // Do instruction shortening before compare elimination because some
274 // vector instructions will be shortened into opcodes that compare
275 // elimination recognizes.
276 if (getOptLevel() != CodeGenOptLevel::None)
277 addPass(P: createSystemZShortenInstPass(TM&: getSystemZTargetMachine()));
278
279 // We eliminate comparisons here rather than earlier because some
280 // transformations can change the set of available CC values and we
281 // generally want those transformations to have priority. This is
282 // especially true in the commonest case where the result of the comparison
283 // is used by a single in-range branch instruction, since we will then
284 // be able to fuse the compare and the branch instead.
285 //
286 // For example, two-address NILF can sometimes be converted into
287 // three-address RISBLG. NILF produces a CC value that indicates whether
288 // the low word is zero, but RISBLG does not modify CC at all. On the
289 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
290 // The CC value produced by NILL isn't useful for our purposes, but the
291 // value produced by RISBG can be used for any comparison with zero
292 // (not just equality). So there are some transformations that lose
293 // CC values (while still being worthwhile) and others that happen to make
294 // the CC result more useful than it was originally.
295 //
296 // Another reason is that we only want to use BRANCH ON COUNT in cases
297 // where we know that the count register is not going to be spilled.
298 //
299 // Doing it so late makes it more likely that a register will be reused
300 // between the comparison and the branch, but it isn't clear whether
301 // preventing that would be a win or not.
302 if (getOptLevel() != CodeGenOptLevel::None)
303 addPass(P: createSystemZElimComparePass(TM&: getSystemZTargetMachine()));
304 addPass(P: createSystemZLongBranchPass(TM&: getSystemZTargetMachine()));
305
306 // Do final scheduling after all other optimizations, to get an
307 // optimal input for the decoder (branch relaxation must happen
308 // after block placement).
309 if (getOptLevel() != CodeGenOptLevel::None)
310 addPass(PassID: &PostMachineSchedulerID);
311}
312
313TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
314 return new SystemZPassConfig(*this, PM);
315}
316
317TargetTransformInfo
318SystemZTargetMachine::getTargetTransformInfo(const Function &F) const {
319 return TargetTransformInfo(std::make_unique<SystemZTTIImpl>(args: this, args: F));
320}
321
322MachineFunctionInfo *SystemZTargetMachine::createMachineFunctionInfo(
323 BumpPtrAllocator &Allocator, const Function &F,
324 const TargetSubtargetInfo *STI) const {
325 return SystemZMachineFunctionInfo::create<SystemZMachineFunctionInfo>(
326 Allocator, F, STI);
327}
328