1//=- WebAssemblyInstrInfo.h - WebAssembly Instruction Information -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file contains the WebAssembly implementation of the
11/// TargetInstrInfo class.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
16#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
17
18#include "WebAssemblyRegisterInfo.h"
19#include "llvm/ADT/ArrayRef.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21
22#define GET_INSTRINFO_HEADER
23#include "WebAssemblyGenInstrInfo.inc"
24
25#define GET_INSTRINFO_OPERAND_ENUM
26#include "WebAssemblyGenInstrInfo.inc"
27
28namespace llvm {
29
30class WebAssemblySubtarget;
31
32class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
33 const WebAssemblyRegisterInfo RI;
34
35public:
36 explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
37
38 const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
39
40 const TargetRegisterClass *
41 getInlineAsmMemoryOperandRegClass(InlineAsm::ConstraintCode C) const override;
42
43 bool isReMaterializableImpl(const MachineInstr &MI) const override;
44
45 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
46 const DebugLoc &DL, Register DestReg, Register SrcReg,
47 bool KillSrc, bool RenamableDest = false,
48 bool RenamableSrc = false) const override;
49 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
50 unsigned OpIdx1,
51 unsigned OpIdx2) const override;
52
53 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
54 MachineBasicBlock *&FBB,
55 SmallVectorImpl<MachineOperand> &Cond,
56 bool AllowModify = false) const override;
57 unsigned removeBranch(MachineBasicBlock &MBB,
58 int *BytesRemoved = nullptr) const override;
59 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
60 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
61 const DebugLoc &DL,
62 int *BytesAdded = nullptr) const override;
63 bool
64 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
65
66 ArrayRef<std::pair<int, const char *>>
67 getSerializableTargetIndices() const override;
68
69 const MachineOperand &getCalleeOperand(const MachineInstr &MI) const override;
70
71 bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index,
72 int64_t &Offset) const override;
73};
74
75} // end namespace llvm
76
77#endif
78