1//===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in the x86
10// target library, as used by the LLVM JIT.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_X86_X86_H
15#define LLVM_LIB_TARGET_X86_X86_H
16
17#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
18#include "llvm/CodeGen/SelectionDAGISel.h"
19#include "llvm/IR/Analysis.h"
20#include "llvm/IR/Module.h"
21#include "llvm/IR/PassManager.h"
22#include "llvm/PassInfo.h"
23#include "llvm/Support/CodeGen.h"
24#include "llvm/Target/TargetMachine.h"
25
26namespace llvm {
27
28class FunctionPass;
29class InstructionSelector;
30class MachineFunction;
31class PassRegistry;
32class X86RegisterBankInfo;
33class X86Subtarget;
34class X86TargetMachine;
35
36/// This pass converts a legalized DAG into a X86-specific DAG, ready for
37/// instruction scheduling.
38class X86ISelDAGToDAGPass : public SelectionDAGISelPass {
39public:
40 X86ISelDAGToDAGPass(X86TargetMachine &TM);
41};
42
43FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel);
44
45/// This pass initializes a global base register for PIC on x86-32.
46class X86GlobalBaseRegPass
47 : public OptionalPassInfoMixin<X86GlobalBaseRegPass> {
48public:
49 PreservedAnalyses run(MachineFunction &MF,
50 MachineFunctionAnalysisManager &MFAM);
51};
52
53FunctionPass *createX86GlobalBaseRegLegacyPass();
54
55/// This pass combines multiple accesses to local-dynamic TLS variables so that
56/// the TLS base address for the module is only fetched once per execution path
57/// through the function.
58class X86CleanupLocalDynamicTLSPass
59 : public OptionalPassInfoMixin<X86CleanupLocalDynamicTLSPass> {
60public:
61 PreservedAnalyses run(MachineFunction &MF,
62 MachineFunctionAnalysisManager &MFAM);
63};
64
65FunctionPass *createCleanupLocalDynamicTLSLegacyPass();
66
67/// This function returns a pass which converts floating-point register
68/// references and pseudo instructions into floating-point stack references and
69/// physical instructions.
70class X86FPStackifierPass : public OptionalPassInfoMixin<X86FPStackifierPass> {
71public:
72 PreservedAnalyses run(MachineFunction &MF,
73 MachineFunctionAnalysisManager &MFAM);
74};
75
76FunctionPass *createX86FPStackifierLegacyPass();
77
78/// This pass aligns the code so that it conforms to the LFI sandboxing rules.
79class X86LFIRewritePass : public RequiredPassInfoMixin<X86LFIRewritePass> {
80public:
81 PreservedAnalyses run(MachineFunction &MF,
82 MachineFunctionAnalysisManager &MFAM);
83};
84
85FunctionPass *createX86LFIRewritePass();
86
87/// This pass inserts AVX vzeroupper instructions before each call to avoid
88/// transition penalty between functions encoded with AVX and SSE.
89class X86InsertVZeroUpperPass
90 : public OptionalPassInfoMixin<X86InsertVZeroUpperPass> {
91public:
92 PreservedAnalyses run(MachineFunction &MF,
93 MachineFunctionAnalysisManager &MFAM);
94};
95
96FunctionPass *createX86InsertVZeroUpperLegacyPass();
97/// This pass inserts ENDBR instructions before indirect jump/call
98/// destinations as part of CET IBT mechanism.
99class X86IndirectBranchTrackingPass
100 : public OptionalPassInfoMixin<X86IndirectBranchTrackingPass> {
101public:
102 PreservedAnalyses run(MachineFunction &MF,
103 MachineFunctionAnalysisManager &MFAM);
104};
105
106FunctionPass *createX86IndirectBranchTrackingLegacyPass();
107
108/// Return a pass that pads short functions with NOOPs.
109/// This will prevent a stall when returning on the Atom.
110FunctionPass *createX86PadShortFunctions();
111
112/// Return a pass that selectively replaces certain instructions (like add,
113/// sub, inc, dec, some shifts, and some multiplies) by equivalent LEA
114/// instructions, in order to eliminate execution delays in some processors.
115class X86FixupLEAsPass : public OptionalPassInfoMixin<X86FixupLEAsPass> {
116public:
117 PreservedAnalyses run(MachineFunction &MF,
118 MachineFunctionAnalysisManager &MFAM);
119};
120
121FunctionPass *createX86FixupLEAsLegacyPass();
122
123/// Return a pass that replaces equivalent slower instructions with faster
124/// ones.
125class X86FixupInstTuningPass
126 : public OptionalPassInfoMixin<X86FixupInstTuningPass> {
127public:
128 PreservedAnalyses run(MachineFunction &MF,
129 MachineFunctionAnalysisManager &MFAM);
130};
131
132FunctionPass *createX86FixupInstTuningLegacyPass();
133
134/// Return a pass that reduces the size of vector constant pool loads.
135class X86FixupVectorConstantsPass
136 : public OptionalPassInfoMixin<X86FixupVectorConstantsPass> {
137public:
138 PreservedAnalyses run(MachineFunction &MF,
139 MachineFunctionAnalysisManager &MFAM);
140};
141
142FunctionPass *createX86FixupVectorConstantsLegacyPass();
143
144/// Return a pass that removes redundant LEA instructions and redundant address
145/// recalculations.
146class X86OptimizeLEAsPass : public OptionalPassInfoMixin<X86OptimizeLEAsPass> {
147public:
148 PreservedAnalyses run(MachineFunction &MF,
149 MachineFunctionAnalysisManager &MFAM);
150};
151
152FunctionPass *createX86OptimizeLEAsLegacyPass();
153
154/// Return a pass that transforms setcc + movzx pairs into xor + setcc.
155class X86FixupSetCCPass : public OptionalPassInfoMixin<X86FixupSetCCPass> {
156public:
157 PreservedAnalyses run(MachineFunction &MF,
158 MachineFunctionAnalysisManager &MFAM);
159};
160
161FunctionPass *createX86FixupSetCCLegacyPass();
162
163/// Return a pass that avoids creating store forward block issues in the
164/// hardware.
165class X86AvoidStoreForwardingBlocksPass
166 : public OptionalPassInfoMixin<X86AvoidStoreForwardingBlocksPass> {
167public:
168 PreservedAnalyses run(MachineFunction &MF,
169 MachineFunctionAnalysisManager &MFAM);
170};
171
172FunctionPass *createX86AvoidStoreForwardingBlocksLegacyPass();
173
174/// Return a pass that lowers EFLAGS copy pseudo instructions.
175class X86FlagsCopyLoweringPass
176 : public OptionalPassInfoMixin<X86FlagsCopyLoweringPass> {
177public:
178 PreservedAnalyses run(MachineFunction &MF,
179 MachineFunctionAnalysisManager &MFAM);
180};
181
182FunctionPass *createX86FlagsCopyLoweringLegacyPass();
183
184/// Return a pass that expands DynAlloca pseudo-instructions.
185class X86DynAllocaExpanderPass
186 : public OptionalPassInfoMixin<X86DynAllocaExpanderPass> {
187public:
188 PreservedAnalyses run(MachineFunction &MF,
189 MachineFunctionAnalysisManager &MFAM);
190};
191
192FunctionPass *createX86DynAllocaExpanderLegacyPass();
193
194/// Return a pass that config the tile registers.
195class X86TileConfigPass : public OptionalPassInfoMixin<X86TileConfigPass> {
196public:
197 PreservedAnalyses run(MachineFunction &MF,
198 MachineFunctionAnalysisManager &MFAM);
199};
200
201FunctionPass *createX86TileConfigLegacyPass();
202
203/// Return a pass that preconfig the tile registers before fast reg allocation.
204class X86FastPreTileConfigPass
205 : public OptionalPassInfoMixin<X86FastPreTileConfigPass> {
206public:
207 PreservedAnalyses run(MachineFunction &MF,
208 MachineFunctionAnalysisManager &MFAM);
209};
210
211FunctionPass *createX86FastPreTileConfigLegacyPass();
212
213/// Return a pass that config the tile registers after fast reg allocation.
214class X86FastTileConfigPass
215 : public OptionalPassInfoMixin<X86FastTileConfigPass> {
216public:
217 PreservedAnalyses run(MachineFunction &MF,
218 MachineFunctionAnalysisManager &MFAM);
219};
220
221FunctionPass *createX86FastTileConfigLegacyPass();
222
223/// Return a pass that insert pseudo tile config instruction.
224class X86PreTileConfigPass
225 : public OptionalPassInfoMixin<X86PreTileConfigPass> {
226public:
227 PreservedAnalyses run(MachineFunction &MF,
228 MachineFunctionAnalysisManager &MFAM);
229};
230
231FunctionPass *createX86PreTileConfigLegacyPass();
232
233/// Return a pass that lower the tile copy instruction.
234class X86LowerTileCopyPass
235 : public OptionalPassInfoMixin<X86LowerTileCopyPass> {
236public:
237 PreservedAnalyses run(MachineFunction &MF,
238 MachineFunctionAnalysisManager &MFAM);
239};
240
241FunctionPass *createX86LowerTileCopyLegacyPass();
242
243/// Return a pass that inserts int3 at the end of the function if it ends with a
244/// CALL instruction. The pass does the same for each funclet as well. This
245/// ensures that the open interval of function start and end PCs contains all
246/// return addresses for the benefit of the Windows x64 unwinder.
247class X86AvoidTrailingCallPass
248 : public RequiredPassInfoMixin<X86AvoidTrailingCallPass> {
249public:
250 PreservedAnalyses run(MachineFunction &MF,
251 MachineFunctionAnalysisManager &MFAM);
252};
253
254FunctionPass *createX86AvoidTrailingCallLegacyPass();
255
256/// Return a pass that optimizes the code-size of x86 call sequences. This is
257/// done by replacing esp-relative movs with pushes.
258class X86CallFrameOptimizationPass
259 : public OptionalPassInfoMixin<X86CallFrameOptimizationPass> {
260public:
261 PreservedAnalyses run(MachineFunction &MF,
262 MachineFunctionAnalysisManager &MFAM);
263};
264
265FunctionPass *createX86CallFrameOptimizationLegacyPass();
266
267/// Return an IR pass that inserts EH registration stack objects and explicit
268/// EH state updates. This pass must run after EH preparation, which does
269/// Windows-specific but architecture-neutral preparation.
270class X86WinEHStatePass : public OptionalPassInfoMixin<X86WinEHStatePass> {
271public:
272 X86WinEHStatePass() = default;
273 PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM);
274};
275
276FunctionPass *createX86WinEHStateLegacyPass();
277
278/// Return a Machine IR pass that expands X86-specific pseudo
279/// instructions into a sequence of actual instructions. This pass
280/// must run after prologue/epilogue insertion and before lowering
281/// the MachineInstr to MC.
282class X86ExpandPseudoPass : public OptionalPassInfoMixin<X86ExpandPseudoPass> {
283public:
284 PreservedAnalyses run(MachineFunction &MF,
285 MachineFunctionAnalysisManager &MFAM);
286};
287
288FunctionPass *createX86ExpandPseudoLegacyPass();
289
290/// This pass converts X86 cmov instructions into branch when profitable.
291class X86CmovConversionPass
292 : public OptionalPassInfoMixin<X86CmovConversionPass> {
293public:
294 PreservedAnalyses run(MachineFunction &MF,
295 MachineFunctionAnalysisManager &MFAM);
296};
297
298FunctionPass *createX86CmovConversionLegacyPass();
299
300/// Return a Machine IR pass that selectively replaces
301/// certain byte and word instructions by equivalent 32 bit instructions,
302/// in order to eliminate partial register usage, false dependences on
303/// the upper portions of registers, and to save code size.
304class X86FixupBWInstsPass : public OptionalPassInfoMixin<X86FixupBWInstsPass> {
305public:
306 PreservedAnalyses run(MachineFunction &MF,
307 MachineFunctionAnalysisManager &MFAM);
308};
309
310FunctionPass *createX86FixupBWInstsLegacyPass();
311
312/// Return a Machine IR pass that reassigns instruction chains from one domain
313/// to another, when profitable.
314class X86DomainReassignmentPass
315 : public OptionalPassInfoMixin<X86DomainReassignmentPass> {
316public:
317 PreservedAnalyses run(MachineFunction &MF,
318 MachineFunctionAnalysisManager &MFAM);
319};
320
321FunctionPass *createX86DomainReassignmentLegacyPass();
322
323/// This pass compress instructions from EVEX space to legacy/VEX/EVEX space when
324/// possible in order to reduce code size or facilitate HW decoding.
325class X86CompressEVEXPass : public OptionalPassInfoMixin<X86CompressEVEXPass> {
326public:
327 PreservedAnalyses run(MachineFunction &MF,
328 MachineFunctionAnalysisManager &MFAM);
329};
330
331FunctionPass *createX86CompressEVEXLegacyPass();
332
333/// This pass creates the thunks for the retpoline feature.
334FunctionPass *createX86IndirectThunksPass();
335
336/// This pass replaces ret instructions with jmp's to __x86_return thunk.
337class X86ReturnThunksPass : public OptionalPassInfoMixin<X86ReturnThunksPass> {
338public:
339 PreservedAnalyses run(MachineFunction &MF,
340 MachineFunctionAnalysisManager &MFAM);
341};
342
343FunctionPass *createX86ReturnThunksLegacyPass();
344
345/// This pass insert wait instruction after X87 instructions which could raise
346/// fp exceptions when strict-fp enabled.
347class X86InsertX87WaitPass
348 : public OptionalPassInfoMixin<X86InsertX87WaitPass> {
349public:
350 PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &);
351};
352
353FunctionPass *createX86InsertX87WaitLegacyPass();
354
355/// This pass optimizes arithmetic based on knowledge that is only used by
356/// a reduction sequence and is therefore safe to reassociate in interesting
357/// ways.
358class X86PartialReductionPass
359 : public OptionalPassInfoMixin<X86PartialReductionPass> {
360private:
361 const X86TargetMachine *TM;
362
363public:
364 X86PartialReductionPass(const X86TargetMachine *TM) : TM(TM) {}
365 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
366};
367
368FunctionPass *createX86PartialReductionLegacyPass();
369
370/// // Analyzes and emits pseudos to support Win x64 Unwind V2.
371class X86WinEHUnwindV2Pass
372 : public OptionalPassInfoMixin<X86WinEHUnwindV2Pass> {
373public:
374 X86WinEHUnwindV2Pass() = default;
375 PreservedAnalyses run(MachineFunction &MF,
376 MachineFunctionAnalysisManager &MFAM);
377};
378
379FunctionPass *createX86WinEHUnwindV2LegacyPass();
380
381/// The pass transforms load/store <256 x i32> to AMX load/store intrinsics
382/// or split the data to two <128 x i32>.
383class X86LowerAMXTypePass : public RequiredPassInfoMixin<X86LowerAMXTypePass> {
384private:
385 const TargetMachine *TM;
386
387public:
388 X86LowerAMXTypePass(const TargetMachine *TM) : TM(TM) {}
389 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
390};
391
392FunctionPass *createX86LowerAMXTypeLegacyPass();
393
394// Suppresses APX features for relocations for supporting older linkers.
395class X86SuppressAPXForRelocationPass
396 : public OptionalPassInfoMixin<X86SuppressAPXForRelocationPass> {
397public:
398 PreservedAnalyses run(MachineFunction &MF,
399 MachineFunctionAnalysisManager &MFAM);
400};
401
402FunctionPass *createX86SuppressAPXForRelocationLegacyPass();
403
404/// The pass transforms amx intrinsics to scalar operation if the function has
405/// optnone attribute or it is O0.
406class X86LowerAMXIntrinsicsPass
407 : public RequiredPassInfoMixin<X86LowerAMXIntrinsicsPass> {
408private:
409 const TargetMachine *TM;
410
411public:
412 X86LowerAMXIntrinsicsPass(const TargetMachine *TM) : TM(TM) {}
413 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
414};
415
416FunctionPass *createX86LowerAMXIntrinsicsLegacyPass();
417
418/// Capacity check and sub-fragment splitting for Win x64 Unwind V3.
419FunctionPass *createX86WinEHUnwindV3Pass();
420
421/// Returns true when \p MF must use Windows x64 Unwind V3: the module is in V3
422/// mode, or the function needs an unwind table and may use EGPR (R16-R31),
423/// which V1/V2 cannot encode. Shared by frame lowering and the WinEH Unwind
424/// V2/V3 passes so their decisions cannot disagree.
425bool requireWinX64UnwindV3(const MachineFunction &MF);
426
427InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
428 const X86Subtarget &,
429 const X86RegisterBankInfo &);
430
431class X86PostLegalizerCombinerPass
432 : public OptionalPassInfoMixin<X86PostLegalizerCombinerPass> {
433public:
434 PreservedAnalyses run(MachineFunction &MF,
435 MachineFunctionAnalysisManager &MFAM);
436};
437
438FunctionPass *createX86PostLegalizerCombinerLegacy();
439
440class X86PreLegalizerCombinerPass
441 : public RequiredPassInfoMixin<X86PreLegalizerCombinerPass> {
442public:
443 PreservedAnalyses run(MachineFunction &MF,
444 MachineFunctionAnalysisManager &MFAM);
445};
446
447FunctionPass *createX86PreLegalizerCombinerLegacy();
448
449class X86LoadValueInjectionLoadHardeningPass
450 : public OptionalPassInfoMixin<X86LoadValueInjectionLoadHardeningPass> {
451public:
452 PreservedAnalyses run(MachineFunction &MF,
453 MachineFunctionAnalysisManager &MFAM);
454};
455
456FunctionPass *createX86LoadValueInjectionLoadHardeningLegacyPass();
457
458class X86LoadValueInjectionRetHardeningPass
459 : public OptionalPassInfoMixin<X86LoadValueInjectionRetHardeningPass> {
460public:
461 PreservedAnalyses run(MachineFunction &MF,
462 MachineFunctionAnalysisManager &MFAM);
463};
464
465FunctionPass *createX86LoadValueInjectionRetHardeningLegacyPass();
466
467class X86SpeculativeExecutionSideEffectSuppressionPass
468 : public OptionalPassInfoMixin<
469 X86SpeculativeExecutionSideEffectSuppressionPass> {
470public:
471 PreservedAnalyses run(MachineFunction &MF,
472 MachineFunctionAnalysisManager &MFAM);
473};
474
475FunctionPass *createX86SpeculativeExecutionSideEffectSuppressionLegacyPass();
476
477class X86SpeculativeLoadHardeningPass
478 : public OptionalPassInfoMixin<X86SpeculativeLoadHardeningPass> {
479public:
480 PreservedAnalyses run(MachineFunction &MF,
481 MachineFunctionAnalysisManager &MFAM);
482};
483
484FunctionPass *createX86SpeculativeLoadHardeningLegacyPass();
485
486class X86ArgumentStackSlotPass
487 : public OptionalPassInfoMixin<X86ArgumentStackSlotPass> {
488public:
489 PreservedAnalyses run(MachineFunction &MF,
490 MachineFunctionAnalysisManager &MFAM);
491};
492
493FunctionPass *createX86ArgumentStackSlotLegacyPass();
494
495void initializeCompressEVEXLegacyPass(PassRegistry &);
496void initializeX86FixupBWInstLegacyPass(PassRegistry &);
497void initializeFixupLEAsLegacyPass(PassRegistry &);
498void initializeX86ArgumentStackSlotLegacyPass(PassRegistry &);
499void initializeX86AsmPrinterPass(PassRegistry &);
500void initializeX86FixupInstTuningLegacyPass(PassRegistry &);
501void initializeX86FixupVectorConstantsLegacyPass(PassRegistry &);
502void initializeWinEHStateLegacyPass(PassRegistry &);
503void initializeX86AvoidSFBLegacyPass(PassRegistry &);
504void initializeX86AvoidTrailingCallLegacyPassPass(PassRegistry &);
505void initializeX86CallFrameOptimizationLegacyPass(PassRegistry &);
506void initializeX86CmovConversionLegacyPass(PassRegistry &);
507void initializeX86DAGToDAGISelLegacyPass(PassRegistry &);
508void initializeX86DomainReassignmentLegacyPass(PassRegistry &);
509void initializeX86DynAllocaExpanderLegacyPass(PassRegistry &);
510void initializeX86ExecutionDomainFixPass(PassRegistry &);
511void initializeX86ExpandPseudoLegacyPass(PassRegistry &);
512void initializeX86FPStackifierLegacyPass(PassRegistry &);
513void initializeX86FastPreTileConfigLegacyPass(PassRegistry &);
514void initializeX86FastTileConfigLegacyPass(PassRegistry &);
515void initializeX86FixupSetCCLegacyPass(PassRegistry &);
516void initializeX86FlagsCopyLoweringLegacyPass(PassRegistry &);
517void initializeX86IndirectBranchTrackingLegacyPass(PassRegistry &);
518void initializeX86LoadValueInjectionLoadHardeningLegacyPass(PassRegistry &);
519void initializeX86LoadValueInjectionRetHardeningLegacyPass(PassRegistry &);
520void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &);
521void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &);
522void initializeX86LowerTileCopyLegacyPass(PassRegistry &);
523void initializeX86OptimizeLEAsLegacyPass(PassRegistry &);
524void initializeX86PartialReductionLegacyPass(PassRegistry &);
525void initializeX86PreTileConfigLegacyPass(PassRegistry &);
526void initializeX86ReturnThunksLegacyPass(PassRegistry &);
527void initializeX86SpeculativeExecutionSideEffectSuppressionLegacyPass(
528 PassRegistry &);
529void initializeX86SpeculativeLoadHardeningLegacyPass(PassRegistry &);
530void initializeX86SuppressAPXForRelocationLegacyPass(PassRegistry &);
531void initializeX86TileConfigLegacyPass(PassRegistry &);
532void initializeX86WinEHUnwindV2LegacyPass(PassRegistry &);
533void initializeX86PreLegalizerCombinerLegacyPass(PassRegistry &);
534void initializeX86PostLegalizerCombinerLegacyPass(PassRegistry &);
535void initializeX86WinEHUnwindV3Pass(PassRegistry &);
536
537namespace X86AS {
538enum : unsigned {
539 GS = 256,
540 FS = 257,
541 SS = 258,
542 PTR32_SPTR = 270,
543 PTR32_UPTR = 271,
544 PTR64 = 272
545};
546} // End X86AS namespace
547
548} // End llvm namespace
549
550#endif
551