1//===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in the x86
10// target library, as used by the LLVM JIT.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_X86_X86_H
15#define LLVM_LIB_TARGET_X86_X86_H
16
17#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
18#include "llvm/CodeGen/SelectionDAGISel.h"
19#include "llvm/IR/Analysis.h"
20#include "llvm/IR/Module.h"
21#include "llvm/IR/PassManager.h"
22#include "llvm/PassInfo.h"
23#include "llvm/Support/CodeGen.h"
24#include "llvm/Target/TargetMachine.h"
25
26namespace llvm {
27
28class FunctionPass;
29class InstructionSelector;
30class PassRegistry;
31class X86RegisterBankInfo;
32class X86Subtarget;
33class X86TargetMachine;
34
35/// This pass converts a legalized DAG into a X86-specific DAG, ready for
36/// instruction scheduling.
37class X86ISelDAGToDAGPass : public SelectionDAGISelPass {
38public:
39 X86ISelDAGToDAGPass(X86TargetMachine &TM);
40};
41
42FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel);
43
44/// This pass initializes a global base register for PIC on x86-32.
45class X86GlobalBaseRegPass
46 : public OptionalPassInfoMixin<X86GlobalBaseRegPass> {
47public:
48 PreservedAnalyses run(MachineFunction &MF,
49 MachineFunctionAnalysisManager &MFAM);
50};
51
52FunctionPass *createX86GlobalBaseRegLegacyPass();
53
54/// This pass combines multiple accesses to local-dynamic TLS variables so that
55/// the TLS base address for the module is only fetched once per execution path
56/// through the function.
57class X86CleanupLocalDynamicTLSPass
58 : public OptionalPassInfoMixin<X86CleanupLocalDynamicTLSPass> {
59public:
60 PreservedAnalyses run(MachineFunction &MF,
61 MachineFunctionAnalysisManager &MFAM);
62};
63
64FunctionPass *createCleanupLocalDynamicTLSLegacyPass();
65
66/// This function returns a pass which converts floating-point register
67/// references and pseudo instructions into floating-point stack references and
68/// physical instructions.
69class X86FPStackifierPass : public OptionalPassInfoMixin<X86FPStackifierPass> {
70public:
71 PreservedAnalyses run(MachineFunction &MF,
72 MachineFunctionAnalysisManager &MFAM);
73};
74
75FunctionPass *createX86FPStackifierLegacyPass();
76
77/// This pass inserts AVX vzeroupper instructions before each call to avoid
78/// transition penalty between functions encoded with AVX and SSE.
79class X86InsertVZeroUpperPass
80 : public OptionalPassInfoMixin<X86InsertVZeroUpperPass> {
81public:
82 PreservedAnalyses run(MachineFunction &MF,
83 MachineFunctionAnalysisManager &MFAM);
84};
85
86FunctionPass *createX86InsertVZeroUpperLegacyPass();
87/// This pass inserts ENDBR instructions before indirect jump/call
88/// destinations as part of CET IBT mechanism.
89class X86IndirectBranchTrackingPass
90 : public OptionalPassInfoMixin<X86IndirectBranchTrackingPass> {
91public:
92 PreservedAnalyses run(MachineFunction &MF,
93 MachineFunctionAnalysisManager &MFAM);
94};
95
96FunctionPass *createX86IndirectBranchTrackingLegacyPass();
97
98/// Return a pass that pads short functions with NOOPs.
99/// This will prevent a stall when returning on the Atom.
100FunctionPass *createX86PadShortFunctions();
101
102/// Return a pass that selectively replaces certain instructions (like add,
103/// sub, inc, dec, some shifts, and some multiplies) by equivalent LEA
104/// instructions, in order to eliminate execution delays in some processors.
105class X86FixupLEAsPass : public OptionalPassInfoMixin<X86FixupLEAsPass> {
106public:
107 PreservedAnalyses run(MachineFunction &MF,
108 MachineFunctionAnalysisManager &MFAM);
109};
110
111FunctionPass *createX86FixupLEAsLegacyPass();
112
113/// Return a pass that replaces equivalent slower instructions with faster
114/// ones.
115class X86FixupInstTuningPass
116 : public OptionalPassInfoMixin<X86FixupInstTuningPass> {
117public:
118 PreservedAnalyses run(MachineFunction &MF,
119 MachineFunctionAnalysisManager &MFAM);
120};
121
122FunctionPass *createX86FixupInstTuningLegacyPass();
123
124/// Return a pass that reduces the size of vector constant pool loads.
125class X86FixupVectorConstantsPass
126 : public OptionalPassInfoMixin<X86FixupInstTuningPass> {
127public:
128 PreservedAnalyses run(MachineFunction &MF,
129 MachineFunctionAnalysisManager &MFAM);
130};
131
132FunctionPass *createX86FixupVectorConstantsLegacyPass();
133
134/// Return a pass that removes redundant LEA instructions and redundant address
135/// recalculations.
136class X86OptimizeLEAsPass : public OptionalPassInfoMixin<X86OptimizeLEAsPass> {
137public:
138 PreservedAnalyses run(MachineFunction &MF,
139 MachineFunctionAnalysisManager &MFAM);
140};
141
142FunctionPass *createX86OptimizeLEAsLegacyPass();
143
144/// Return a pass that transforms setcc + movzx pairs into xor + setcc.
145class X86FixupSetCCPass : public OptionalPassInfoMixin<X86FixupSetCCPass> {
146public:
147 PreservedAnalyses run(MachineFunction &MF,
148 MachineFunctionAnalysisManager &MFAM);
149};
150
151FunctionPass *createX86FixupSetCCLegacyPass();
152
153/// Return a pass that avoids creating store forward block issues in the
154/// hardware.
155class X86AvoidStoreForwardingBlocksPass
156 : public OptionalPassInfoMixin<X86AvoidStoreForwardingBlocksPass> {
157public:
158 PreservedAnalyses run(MachineFunction &MF,
159 MachineFunctionAnalysisManager &MFAM);
160};
161
162FunctionPass *createX86AvoidStoreForwardingBlocksLegacyPass();
163
164/// Return a pass that lowers EFLAGS copy pseudo instructions.
165class X86FlagsCopyLoweringPass
166 : public OptionalPassInfoMixin<X86FlagsCopyLoweringPass> {
167public:
168 PreservedAnalyses run(MachineFunction &MF,
169 MachineFunctionAnalysisManager &MFAM);
170};
171
172FunctionPass *createX86FlagsCopyLoweringLegacyPass();
173
174/// Return a pass that expands DynAlloca pseudo-instructions.
175class X86DynAllocaExpanderPass
176 : public OptionalPassInfoMixin<X86DynAllocaExpanderPass> {
177public:
178 PreservedAnalyses run(MachineFunction &MF,
179 MachineFunctionAnalysisManager &MFAM);
180};
181
182FunctionPass *createX86DynAllocaExpanderLegacyPass();
183
184/// Return a pass that config the tile registers.
185class X86TileConfigPass : public OptionalPassInfoMixin<X86TileConfigPass> {
186public:
187 PreservedAnalyses run(MachineFunction &MF,
188 MachineFunctionAnalysisManager &MFAM);
189};
190
191FunctionPass *createX86TileConfigLegacyPass();
192
193/// Return a pass that preconfig the tile registers before fast reg allocation.
194class X86FastPreTileConfigPass
195 : public OptionalPassInfoMixin<X86FastPreTileConfigPass> {
196public:
197 PreservedAnalyses run(MachineFunction &MF,
198 MachineFunctionAnalysisManager &MFAM);
199};
200
201FunctionPass *createX86FastPreTileConfigLegacyPass();
202
203/// Return a pass that config the tile registers after fast reg allocation.
204class X86FastTileConfigPass
205 : public OptionalPassInfoMixin<X86FastTileConfigPass> {
206public:
207 PreservedAnalyses run(MachineFunction &MF,
208 MachineFunctionAnalysisManager &MFAM);
209};
210
211FunctionPass *createX86FastTileConfigLegacyPass();
212
213/// Return a pass that insert pseudo tile config instruction.
214class X86PreTileConfigPass
215 : public OptionalPassInfoMixin<X86PreTileConfigPass> {
216public:
217 PreservedAnalyses run(MachineFunction &MF,
218 MachineFunctionAnalysisManager &MFAM);
219};
220
221FunctionPass *createX86PreTileConfigLegacyPass();
222
223/// Return a pass that lower the tile copy instruction.
224class X86LowerTileCopyPass
225 : public OptionalPassInfoMixin<X86LowerTileCopyPass> {
226public:
227 PreservedAnalyses run(MachineFunction &MF,
228 MachineFunctionAnalysisManager &MFAM);
229};
230
231FunctionPass *createX86LowerTileCopyLegacyPass();
232
233/// Return a pass that inserts int3 at the end of the function if it ends with a
234/// CALL instruction. The pass does the same for each funclet as well. This
235/// ensures that the open interval of function start and end PCs contains all
236/// return addresses for the benefit of the Windows x64 unwinder.
237class X86AvoidTrailingCallPass
238 : public RequiredPassInfoMixin<X86AvoidTrailingCallPass> {
239public:
240 PreservedAnalyses run(MachineFunction &MF,
241 MachineFunctionAnalysisManager &MFAM);
242};
243
244FunctionPass *createX86AvoidTrailingCallLegacyPass();
245
246/// Return a pass that optimizes the code-size of x86 call sequences. This is
247/// done by replacing esp-relative movs with pushes.
248class X86CallFrameOptimizationPass
249 : public OptionalPassInfoMixin<X86CallFrameOptimizationPass> {
250public:
251 PreservedAnalyses run(MachineFunction &MF,
252 MachineFunctionAnalysisManager &MFAM);
253};
254
255FunctionPass *createX86CallFrameOptimizationLegacyPass();
256
257/// Return an IR pass that inserts EH registration stack objects and explicit
258/// EH state updates. This pass must run after EH preparation, which does
259/// Windows-specific but architecture-neutral preparation.
260class X86WinEHStatePass : public OptionalPassInfoMixin<X86WinEHStatePass> {
261public:
262 X86WinEHStatePass() = default;
263 PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM);
264};
265
266FunctionPass *createX86WinEHStateLegacyPass();
267
268/// Return a Machine IR pass that expands X86-specific pseudo
269/// instructions into a sequence of actual instructions. This pass
270/// must run after prologue/epilogue insertion and before lowering
271/// the MachineInstr to MC.
272class X86ExpandPseudoPass : public OptionalPassInfoMixin<X86ExpandPseudoPass> {
273public:
274 PreservedAnalyses run(MachineFunction &MF,
275 MachineFunctionAnalysisManager &MFAM);
276};
277
278FunctionPass *createX86ExpandPseudoLegacyPass();
279
280/// This pass converts X86 cmov instructions into branch when profitable.
281class X86CmovConversionPass
282 : public OptionalPassInfoMixin<X86CmovConversionPass> {
283public:
284 PreservedAnalyses run(MachineFunction &MF,
285 MachineFunctionAnalysisManager &MFAM);
286};
287
288FunctionPass *createX86CmovConversionLegacyPass();
289
290/// Return a Machine IR pass that selectively replaces
291/// certain byte and word instructions by equivalent 32 bit instructions,
292/// in order to eliminate partial register usage, false dependences on
293/// the upper portions of registers, and to save code size.
294class X86FixupBWInstsPass : public OptionalPassInfoMixin<X86FixupBWInstsPass> {
295public:
296 PreservedAnalyses run(MachineFunction &MF,
297 MachineFunctionAnalysisManager &MFAM);
298};
299
300FunctionPass *createX86FixupBWInstsLegacyPass();
301
302/// Return a Machine IR pass that reassigns instruction chains from one domain
303/// to another, when profitable.
304class X86DomainReassignmentPass
305 : public OptionalPassInfoMixin<X86DomainReassignmentPass> {
306public:
307 PreservedAnalyses run(MachineFunction &MF,
308 MachineFunctionAnalysisManager &MFAM);
309};
310
311FunctionPass *createX86DomainReassignmentLegacyPass();
312
313/// This pass compress instructions from EVEX space to legacy/VEX/EVEX space when
314/// possible in order to reduce code size or facilitate HW decoding.
315class X86CompressEVEXPass : public OptionalPassInfoMixin<X86CompressEVEXPass> {
316public:
317 PreservedAnalyses run(MachineFunction &MF,
318 MachineFunctionAnalysisManager &MFAM);
319};
320
321FunctionPass *createX86CompressEVEXLegacyPass();
322
323/// This pass creates the thunks for the retpoline feature.
324FunctionPass *createX86IndirectThunksPass();
325
326/// This pass replaces ret instructions with jmp's to __x86_return thunk.
327class X86ReturnThunksPass : public OptionalPassInfoMixin<X86ReturnThunksPass> {
328public:
329 PreservedAnalyses run(MachineFunction &MF,
330 MachineFunctionAnalysisManager &MFAM);
331};
332
333FunctionPass *createX86ReturnThunksLegacyPass();
334
335/// This pass insert wait instruction after X87 instructions which could raise
336/// fp exceptions when strict-fp enabled.
337class X86InsertX87WaitPass
338 : public OptionalPassInfoMixin<X86InsertX87WaitPass> {
339public:
340 PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &);
341};
342
343FunctionPass *createX86InsertX87WaitLegacyPass();
344
345/// This pass optimizes arithmetic based on knowledge that is only used by
346/// a reduction sequence and is therefore safe to reassociate in interesting
347/// ways.
348class X86PartialReductionPass
349 : public OptionalPassInfoMixin<X86PartialReductionPass> {
350private:
351 const X86TargetMachine *TM;
352
353public:
354 X86PartialReductionPass(const X86TargetMachine *TM) : TM(TM) {}
355 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
356};
357
358FunctionPass *createX86PartialReductionLegacyPass();
359
360/// // Analyzes and emits pseudos to support Win x64 Unwind V2.
361class X86WinEHUnwindV2Pass
362 : public OptionalPassInfoMixin<X86WinEHUnwindV2Pass> {
363public:
364 X86WinEHUnwindV2Pass() = default;
365 PreservedAnalyses run(MachineFunction &MF,
366 MachineFunctionAnalysisManager &MFAM);
367};
368
369FunctionPass *createX86WinEHUnwindV2LegacyPass();
370
371/// The pass transforms load/store <256 x i32> to AMX load/store intrinsics
372/// or split the data to two <128 x i32>.
373class X86LowerAMXTypePass : public RequiredPassInfoMixin<X86LowerAMXTypePass> {
374private:
375 const TargetMachine *TM;
376
377public:
378 X86LowerAMXTypePass(const TargetMachine *TM) : TM(TM) {}
379 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
380};
381
382FunctionPass *createX86LowerAMXTypeLegacyPass();
383
384// Suppresses APX features for relocations for supporting older linkers.
385class X86SuppressAPXForRelocationPass
386 : public OptionalPassInfoMixin<X86SuppressAPXForRelocationPass> {
387public:
388 PreservedAnalyses run(MachineFunction &MF,
389 MachineFunctionAnalysisManager &MFAM);
390};
391
392FunctionPass *createX86SuppressAPXForRelocationLegacyPass();
393
394/// The pass transforms amx intrinsics to scalar operation if the function has
395/// optnone attribute or it is O0.
396class X86LowerAMXIntrinsicsPass
397 : public RequiredPassInfoMixin<X86LowerAMXIntrinsicsPass> {
398private:
399 const TargetMachine *TM;
400
401public:
402 X86LowerAMXIntrinsicsPass(const TargetMachine *TM) : TM(TM) {}
403 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
404};
405
406FunctionPass *createX86LowerAMXIntrinsicsLegacyPass();
407
408/// Capacity check and sub-fragment splitting for Win x64 Unwind V3.
409FunctionPass *createX86WinEHUnwindV3Pass();
410
411InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
412 const X86Subtarget &,
413 const X86RegisterBankInfo &);
414
415class X86PostLegalizerCombinerPass
416 : public OptionalPassInfoMixin<X86PostLegalizerCombinerPass> {
417public:
418 PreservedAnalyses run(MachineFunction &MF,
419 MachineFunctionAnalysisManager &MFAM);
420};
421
422FunctionPass *createX86PostLegalizerCombinerLegacy();
423
424class X86PreLegalizerCombinerPass
425 : public PassInfoMixin<X86PreLegalizerCombinerPass> {
426public:
427 PreservedAnalyses run(MachineFunction &MF,
428 MachineFunctionAnalysisManager &MFAM);
429};
430
431FunctionPass *createX86PreLegalizerCombinerLegacy();
432
433class X86LoadValueInjectionLoadHardeningPass
434 : public OptionalPassInfoMixin<X86LoadValueInjectionLoadHardeningPass> {
435public:
436 PreservedAnalyses run(MachineFunction &MF,
437 MachineFunctionAnalysisManager &MFAM);
438};
439
440FunctionPass *createX86LoadValueInjectionLoadHardeningLegacyPass();
441
442class X86LoadValueInjectionRetHardeningPass
443 : public OptionalPassInfoMixin<X86LoadValueInjectionRetHardeningPass> {
444public:
445 PreservedAnalyses run(MachineFunction &MF,
446 MachineFunctionAnalysisManager &MFAM);
447};
448
449FunctionPass *createX86LoadValueInjectionRetHardeningLegacyPass();
450
451class X86SpeculativeExecutionSideEffectSuppressionPass
452 : public OptionalPassInfoMixin<
453 X86SpeculativeExecutionSideEffectSuppressionPass> {
454public:
455 PreservedAnalyses run(MachineFunction &MF,
456 MachineFunctionAnalysisManager &MFAM);
457};
458
459FunctionPass *createX86SpeculativeExecutionSideEffectSuppressionLegacyPass();
460
461class X86SpeculativeLoadHardeningPass
462 : public OptionalPassInfoMixin<X86SpeculativeLoadHardeningPass> {
463public:
464 PreservedAnalyses run(MachineFunction &MF,
465 MachineFunctionAnalysisManager &MFAM);
466};
467
468FunctionPass *createX86SpeculativeLoadHardeningLegacyPass();
469
470class X86ArgumentStackSlotPass
471 : public OptionalPassInfoMixin<X86ArgumentStackSlotPass> {
472public:
473 PreservedAnalyses run(MachineFunction &MF,
474 MachineFunctionAnalysisManager &MFAM);
475};
476
477FunctionPass *createX86ArgumentStackSlotLegacyPass();
478
479void initializeCompressEVEXLegacyPass(PassRegistry &);
480void initializeX86FixupBWInstLegacyPass(PassRegistry &);
481void initializeFixupLEAsLegacyPass(PassRegistry &);
482void initializeX86ArgumentStackSlotLegacyPass(PassRegistry &);
483void initializeX86AsmPrinterPass(PassRegistry &);
484void initializeX86FixupInstTuningLegacyPass(PassRegistry &);
485void initializeX86FixupVectorConstantsLegacyPass(PassRegistry &);
486void initializeWinEHStateLegacyPass(PassRegistry &);
487void initializeX86AvoidSFBLegacyPass(PassRegistry &);
488void initializeX86AvoidTrailingCallLegacyPassPass(PassRegistry &);
489void initializeX86CallFrameOptimizationLegacyPass(PassRegistry &);
490void initializeX86CmovConversionLegacyPass(PassRegistry &);
491void initializeX86DAGToDAGISelLegacyPass(PassRegistry &);
492void initializeX86DomainReassignmentLegacyPass(PassRegistry &);
493void initializeX86DynAllocaExpanderLegacyPass(PassRegistry &);
494void initializeX86ExecutionDomainFixPass(PassRegistry &);
495void initializeX86ExpandPseudoLegacyPass(PassRegistry &);
496void initializeX86FPStackifierLegacyPass(PassRegistry &);
497void initializeX86FastPreTileConfigLegacyPass(PassRegistry &);
498void initializeX86FastTileConfigLegacyPass(PassRegistry &);
499void initializeX86FixupSetCCLegacyPass(PassRegistry &);
500void initializeX86FlagsCopyLoweringLegacyPass(PassRegistry &);
501void initializeX86IndirectBranchTrackingLegacyPass(PassRegistry &);
502void initializeX86LoadValueInjectionLoadHardeningLegacyPass(PassRegistry &);
503void initializeX86LoadValueInjectionRetHardeningLegacyPass(PassRegistry &);
504void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &);
505void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &);
506void initializeX86LowerTileCopyLegacyPass(PassRegistry &);
507void initializeX86OptimizeLEAsLegacyPass(PassRegistry &);
508void initializeX86PartialReductionLegacyPass(PassRegistry &);
509void initializeX86PreTileConfigLegacyPass(PassRegistry &);
510void initializeX86ReturnThunksLegacyPass(PassRegistry &);
511void initializeX86SpeculativeExecutionSideEffectSuppressionLegacyPass(
512 PassRegistry &);
513void initializeX86SpeculativeLoadHardeningLegacyPass(PassRegistry &);
514void initializeX86SuppressAPXForRelocationLegacyPass(PassRegistry &);
515void initializeX86TileConfigLegacyPass(PassRegistry &);
516void initializeX86WinEHUnwindV2LegacyPass(PassRegistry &);
517void initializeX86PreLegalizerCombinerLegacyPass(PassRegistry &);
518void initializeX86PostLegalizerCombinerLegacyPass(PassRegistry &);
519void initializeX86WinEHUnwindV3Pass(PassRegistry &);
520
521namespace X86AS {
522enum : unsigned {
523 GS = 256,
524 FS = 257,
525 SS = 258,
526 PTR32_SPTR = 270,
527 PTR32_UPTR = 271,
528 PTR64 = 272
529};
530} // End X86AS namespace
531
532} // End llvm namespace
533
534#endif
535