1//===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in the x86
10// target library, as used by the LLVM JIT.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_X86_X86_H
15#define LLVM_LIB_TARGET_X86_X86_H
16
17#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
18#include "llvm/IR/Analysis.h"
19#include "llvm/IR/PassManager.h"
20#include "llvm/PassInfo.h"
21#include "llvm/Support/CodeGen.h"
22#include "llvm/Target/TargetMachine.h"
23
24namespace llvm {
25
26class FunctionPass;
27class InstructionSelector;
28class PassRegistry;
29class X86RegisterBankInfo;
30class X86Subtarget;
31class X86TargetMachine;
32
33/// This pass converts a legalized DAG into a X86-specific DAG, ready for
34/// instruction scheduling.
35FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel);
36
37/// This pass initializes a global base register for PIC on x86-32.
38FunctionPass *createX86GlobalBaseRegPass();
39
40/// This pass combines multiple accesses to local-dynamic TLS variables so that
41/// the TLS base address for the module is only fetched once per execution path
42/// through the function.
43FunctionPass *createCleanupLocalDynamicTLSPass();
44
45/// This function returns a pass which converts floating-point register
46/// references and pseudo instructions into floating-point stack references and
47/// physical instructions.
48class X86FPStackifierPass : public PassInfoMixin<X86FPStackifierPass> {
49public:
50 PreservedAnalyses run(MachineFunction &MF,
51 MachineFunctionAnalysisManager &MFAM);
52};
53
54FunctionPass *createX86FPStackifierLegacyPass();
55
56/// This pass inserts AVX vzeroupper instructions before each call to avoid
57/// transition penalty between functions encoded with AVX and SSE.
58FunctionPass *createX86IssueVZeroUpperPass();
59
60/// This pass inserts ENDBR instructions before indirect jump/call
61/// destinations as part of CET IBT mechanism.
62FunctionPass *createX86IndirectBranchTrackingPass();
63
64/// Return a pass that pads short functions with NOOPs.
65/// This will prevent a stall when returning on the Atom.
66FunctionPass *createX86PadShortFunctions();
67
68/// Return a pass that selectively replaces certain instructions (like add,
69/// sub, inc, dec, some shifts, and some multiplies) by equivalent LEA
70/// instructions, in order to eliminate execution delays in some processors.
71class X86FixupLEAsPass : public PassInfoMixin<X86FixupLEAsPass> {
72public:
73 PreservedAnalyses run(MachineFunction &MF,
74 MachineFunctionAnalysisManager &MFAM);
75};
76
77FunctionPass *createX86FixupLEAsLegacyPass();
78
79/// Return a pass that replaces equivalent slower instructions with faster
80/// ones.
81class X86FixupInstTuningPass : public PassInfoMixin<X86FixupInstTuningPass> {
82public:
83 PreservedAnalyses run(MachineFunction &MF,
84 MachineFunctionAnalysisManager &MFAM);
85};
86
87FunctionPass *createX86FixupInstTuningLegacyPass();
88
89/// Return a pass that reduces the size of vector constant pool loads.
90class X86FixupVectorConstantsPass
91 : public PassInfoMixin<X86FixupInstTuningPass> {
92public:
93 PreservedAnalyses run(MachineFunction &MF,
94 MachineFunctionAnalysisManager &MFAM);
95};
96
97FunctionPass *createX86FixupVectorConstantsLegacyPass();
98
99/// Return a pass that removes redundant LEA instructions and redundant address
100/// recalculations.
101class X86OptimizeLEAsPass : public PassInfoMixin<X86OptimizeLEAsPass> {
102public:
103 PreservedAnalyses run(MachineFunction &MF,
104 MachineFunctionAnalysisManager &MFAM);
105};
106
107FunctionPass *createX86OptimizeLEAsLegacyPass();
108
109/// Return a pass that transforms setcc + movzx pairs into xor + setcc.
110class X86FixupSetCCPass : public PassInfoMixin<X86FixupSetCCPass> {
111public:
112 PreservedAnalyses run(MachineFunction &MF,
113 MachineFunctionAnalysisManager &MFAM);
114};
115
116FunctionPass *createX86FixupSetCCLegacyPass();
117
118/// Return a pass that avoids creating store forward block issues in the
119/// hardware.
120class X86AvoidStoreForwardingBlocksPass
121 : public PassInfoMixin<X86AvoidStoreForwardingBlocksPass> {
122public:
123 PreservedAnalyses run(MachineFunction &MF,
124 MachineFunctionAnalysisManager &MFAM);
125};
126
127FunctionPass *createX86AvoidStoreForwardingBlocksLegacyPass();
128
129/// Return a pass that lowers EFLAGS copy pseudo instructions.
130class X86FlagsCopyLoweringPass
131 : public PassInfoMixin<X86FlagsCopyLoweringPass> {
132public:
133 PreservedAnalyses run(MachineFunction &MF,
134 MachineFunctionAnalysisManager &MFAM);
135};
136
137FunctionPass *createX86FlagsCopyLoweringLegacyPass();
138
139/// Return a pass that expands DynAlloca pseudo-instructions.
140class X86DynAllocaExpanderPass
141 : public PassInfoMixin<X86DynAllocaExpanderPass> {
142public:
143 PreservedAnalyses run(MachineFunction &MF,
144 MachineFunctionAnalysisManager &MFAM);
145};
146
147FunctionPass *createX86DynAllocaExpanderLegacyPass();
148
149/// Return a pass that config the tile registers.
150class X86TileConfigPass : public PassInfoMixin<X86TileConfigPass> {
151public:
152 PreservedAnalyses run(MachineFunction &MF,
153 MachineFunctionAnalysisManager &MFAM);
154};
155
156FunctionPass *createX86TileConfigLegacyPass();
157
158/// Return a pass that preconfig the tile registers before fast reg allocation.
159class X86FastPreTileConfigPass
160 : public PassInfoMixin<X86FastPreTileConfigPass> {
161public:
162 PreservedAnalyses run(MachineFunction &MF,
163 MachineFunctionAnalysisManager &MFAM);
164};
165
166FunctionPass *createX86FastPreTileConfigLegacyPass();
167
168/// Return a pass that config the tile registers after fast reg allocation.
169class X86FastTileConfigPass : public PassInfoMixin<X86FastTileConfigPass> {
170public:
171 PreservedAnalyses run(MachineFunction &MF,
172 MachineFunctionAnalysisManager &MFAM);
173};
174
175FunctionPass *createX86FastTileConfigLegacyPass();
176
177/// Return a pass that insert pseudo tile config instruction.
178class X86PreTileConfigPass : public PassInfoMixin<X86PreTileConfigPass> {
179public:
180 PreservedAnalyses run(MachineFunction &MF,
181 MachineFunctionAnalysisManager &MFAM);
182};
183
184FunctionPass *createX86PreTileConfigLegacyPass();
185
186/// Return a pass that lower the tile copy instruction.
187class X86LowerTileCopyPass : public PassInfoMixin<X86LowerTileCopyPass> {
188public:
189 PreservedAnalyses run(MachineFunction &MF,
190 MachineFunctionAnalysisManager &MFAM);
191};
192
193FunctionPass *createX86LowerTileCopyLegacyPass();
194
195/// Return a pass that inserts int3 at the end of the function if it ends with a
196/// CALL instruction. The pass does the same for each funclet as well. This
197/// ensures that the open interval of function start and end PCs contains all
198/// return addresses for the benefit of the Windows x64 unwinder.
199class X86AvoidTrailingCallPass
200 : public PassInfoMixin<X86AvoidTrailingCallPass> {
201public:
202 PreservedAnalyses run(MachineFunction &MF,
203 MachineFunctionAnalysisManager &MFAM);
204 static bool isRequired() { return true; }
205};
206
207FunctionPass *createX86AvoidTrailingCallLegacyPass();
208
209/// Return a pass that optimizes the code-size of x86 call sequences. This is
210/// done by replacing esp-relative movs with pushes.
211class X86CallFrameOptimizationPass
212 : public PassInfoMixin<X86CallFrameOptimizationPass> {
213public:
214 PreservedAnalyses run(MachineFunction &MF,
215 MachineFunctionAnalysisManager &MFAM);
216};
217
218FunctionPass *createX86CallFrameOptimizationLegacyPass();
219
220/// Return an IR pass that inserts EH registration stack objects and explicit
221/// EH state updates. This pass must run after EH preparation, which does
222/// Windows-specific but architecture-neutral preparation.
223FunctionPass *createX86WinEHStatePass();
224
225/// Return a Machine IR pass that expands X86-specific pseudo
226/// instructions into a sequence of actual instructions. This pass
227/// must run after prologue/epilogue insertion and before lowering
228/// the MachineInstr to MC.
229class X86ExpandPseudoPass : public PassInfoMixin<X86ExpandPseudoPass> {
230public:
231 PreservedAnalyses run(MachineFunction &MF,
232 MachineFunctionAnalysisManager &MFAM);
233};
234
235FunctionPass *createX86ExpandPseudoLegacyPass();
236
237/// This pass converts X86 cmov instructions into branch when profitable.
238class X86CmovConversionPass : public PassInfoMixin<X86CmovConversionPass> {
239public:
240 PreservedAnalyses run(MachineFunction &MF,
241 MachineFunctionAnalysisManager &MFAM);
242};
243
244FunctionPass *createX86CmovConversionLegacyPass();
245
246/// Return a Machine IR pass that selectively replaces
247/// certain byte and word instructions by equivalent 32 bit instructions,
248/// in order to eliminate partial register usage, false dependences on
249/// the upper portions of registers, and to save code size.
250class X86FixupBWInstsPass : public PassInfoMixin<X86FixupBWInstsPass> {
251public:
252 PreservedAnalyses run(MachineFunction &MF,
253 MachineFunctionAnalysisManager &MFAM);
254};
255
256FunctionPass *createX86FixupBWInstsLegacyPass();
257
258/// Return a Machine IR pass that reassigns instruction chains from one domain
259/// to another, when profitable.
260class X86DomainReassignmentPass
261 : public PassInfoMixin<X86DomainReassignmentPass> {
262public:
263 PreservedAnalyses run(MachineFunction &MF,
264 MachineFunctionAnalysisManager &MFAM);
265};
266
267FunctionPass *createX86DomainReassignmentLegacyPass();
268
269/// This pass compress instructions from EVEX space to legacy/VEX/EVEX space when
270/// possible in order to reduce code size or facilitate HW decoding.
271class X86CompressEVEXPass : public PassInfoMixin<X86CompressEVEXPass> {
272public:
273 PreservedAnalyses run(MachineFunction &MF,
274 MachineFunctionAnalysisManager &MFAM);
275};
276
277FunctionPass *createX86CompressEVEXLegacyPass();
278
279/// This pass creates the thunks for the retpoline feature.
280FunctionPass *createX86IndirectThunksPass();
281
282/// This pass replaces ret instructions with jmp's to __x86_return thunk.
283class X86ReturnThunksPass : public PassInfoMixin<X86ReturnThunksPass> {
284public:
285 PreservedAnalyses run(MachineFunction &MF,
286 MachineFunctionAnalysisManager &MFAM);
287};
288
289FunctionPass *createX86ReturnThunksLegacyPass();
290
291/// This pass insert wait instruction after X87 instructions which could raise
292/// fp exceptions when strict-fp enabled.
293FunctionPass *createX86InsertX87waitPass();
294
295/// This pass optimizes arithmetic based on knowledge that is only used by
296/// a reduction sequence and is therefore safe to reassociate in interesting
297/// ways.
298class X86PartialReductionPass : public PassInfoMixin<X86PartialReductionPass> {
299private:
300 const X86TargetMachine *TM;
301
302public:
303 X86PartialReductionPass(const X86TargetMachine *TM) : TM(TM) {}
304 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
305};
306
307FunctionPass *createX86PartialReductionLegacyPass();
308
309/// // Analyzes and emits pseudos to support Win x64 Unwind V2.
310class X86WinEHUnwindV2Pass : public PassInfoMixin<X86WinEHUnwindV2Pass> {
311public:
312 X86WinEHUnwindV2Pass() = default;
313 PreservedAnalyses run(MachineFunction &MF,
314 MachineFunctionAnalysisManager &MFAM);
315};
316
317FunctionPass *createX86WinEHUnwindV2LegacyPass();
318
319/// The pass transforms load/store <256 x i32> to AMX load/store intrinsics
320/// or split the data to two <128 x i32>.
321class X86LowerAMXTypePass : public PassInfoMixin<X86LowerAMXTypePass> {
322private:
323 const TargetMachine *TM;
324
325public:
326 X86LowerAMXTypePass(const TargetMachine *TM) : TM(TM) {}
327 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
328 static bool isRequired() { return true; }
329};
330
331FunctionPass *createX86LowerAMXTypeLegacyPass();
332
333// Suppresses APX features for relocations for supporting older linkers.
334class X86SuppressAPXForRelocationPass
335 : public PassInfoMixin<X86SuppressAPXForRelocationPass> {
336public:
337 PreservedAnalyses run(MachineFunction &MF,
338 MachineFunctionAnalysisManager &MFAM);
339};
340
341FunctionPass *createX86SuppressAPXForRelocationLegacyPass();
342
343/// The pass transforms amx intrinsics to scalar operation if the function has
344/// optnone attribute or it is O0.
345class X86LowerAMXIntrinsicsPass
346 : public PassInfoMixin<X86LowerAMXIntrinsicsPass> {
347private:
348 const TargetMachine *TM;
349
350public:
351 X86LowerAMXIntrinsicsPass(const TargetMachine *TM) : TM(TM) {}
352 PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
353 static bool isRequired() { return true; }
354};
355
356FunctionPass *createX86LowerAMXIntrinsicsLegacyPass();
357
358InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
359 const X86Subtarget &,
360 const X86RegisterBankInfo &);
361
362FunctionPass *createX86PostLegalizerCombiner();
363FunctionPass *createX86PreLegalizerCombiner();
364FunctionPass *createX86LoadValueInjectionLoadHardeningPass();
365
366class X86LoadValueInjectionRetHardeningPass
367 : public PassInfoMixin<X86LoadValueInjectionRetHardeningPass> {
368public:
369 PreservedAnalyses run(MachineFunction &MF,
370 MachineFunctionAnalysisManager &MFAM);
371};
372
373FunctionPass *createX86LoadValueInjectionRetHardeningLegacyPass();
374
375class X86SpeculativeExecutionSideEffectSuppressionPass
376 : public PassInfoMixin<X86SpeculativeExecutionSideEffectSuppressionPass> {
377public:
378 PreservedAnalyses run(MachineFunction &MF,
379 MachineFunctionAnalysisManager &MFAM);
380};
381
382FunctionPass *createX86SpeculativeExecutionSideEffectSuppressionLegacyPass();
383
384class X86SpeculativeLoadHardeningPass
385 : public PassInfoMixin<X86SpeculativeLoadHardeningPass> {
386public:
387 PreservedAnalyses run(MachineFunction &MF,
388 MachineFunctionAnalysisManager &MFAM);
389};
390
391FunctionPass *createX86SpeculativeLoadHardeningLegacyPass();
392
393class X86ArgumentStackSlotPass
394 : public PassInfoMixin<X86ArgumentStackSlotPass> {
395public:
396 PreservedAnalyses run(MachineFunction &MF,
397 MachineFunctionAnalysisManager &MFAM);
398};
399
400FunctionPass *createX86ArgumentStackSlotLegacyPass();
401
402void initializeCompressEVEXLegacyPass(PassRegistry &);
403void initializeX86FixupBWInstLegacyPass(PassRegistry &);
404void initializeFixupLEAsLegacyPass(PassRegistry &);
405void initializeX86ArgumentStackSlotLegacyPass(PassRegistry &);
406void initializeX86AsmPrinterPass(PassRegistry &);
407void initializeX86FixupInstTuningLegacyPass(PassRegistry &);
408void initializeX86FixupVectorConstantsLegacyPass(PassRegistry &);
409void initializeWinEHStatePassPass(PassRegistry &);
410void initializeX86AvoidSFBLegacyPass(PassRegistry &);
411void initializeX86AvoidTrailingCallLegacyPassPass(PassRegistry &);
412void initializeX86CallFrameOptimizationLegacyPass(PassRegistry &);
413void initializeX86CmovConversionLegacyPass(PassRegistry &);
414void initializeX86DAGToDAGISelLegacyPass(PassRegistry &);
415void initializeX86DomainReassignmentLegacyPass(PassRegistry &);
416void initializeX86DynAllocaExpanderLegacyPass(PassRegistry &);
417void initializeX86ExecutionDomainFixPass(PassRegistry &);
418void initializeX86ExpandPseudoLegacyPass(PassRegistry &);
419void initializeX86FPStackifierLegacyPass(PassRegistry &);
420void initializeX86FastPreTileConfigLegacyPass(PassRegistry &);
421void initializeX86FastTileConfigLegacyPass(PassRegistry &);
422void initializeX86FixupSetCCLegacyPass(PassRegistry &);
423void initializeX86FlagsCopyLoweringLegacyPass(PassRegistry &);
424void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &);
425void initializeX86LoadValueInjectionRetHardeningLegacyPass(PassRegistry &);
426void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &);
427void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &);
428void initializeX86LowerTileCopyLegacyPass(PassRegistry &);
429void initializeX86OptimizeLEAsLegacyPass(PassRegistry &);
430void initializeX86PartialReductionLegacyPass(PassRegistry &);
431void initializeX86PreTileConfigLegacyPass(PassRegistry &);
432void initializeX86ReturnThunksLegacyPass(PassRegistry &);
433void initializeX86SpeculativeExecutionSideEffectSuppressionLegacyPass(
434 PassRegistry &);
435void initializeX86SpeculativeLoadHardeningLegacyPass(PassRegistry &);
436void initializeX86SuppressAPXForRelocationLegacyPass(PassRegistry &);
437void initializeX86TileConfigLegacyPass(PassRegistry &);
438void initializeX86WinEHUnwindV2LegacyPass(PassRegistry &);
439void initializeX86PreLegalizerCombinerPass(PassRegistry &);
440void initializeX86PostLegalizerCombinerPass(PassRegistry &);
441
442namespace X86AS {
443enum : unsigned {
444 GS = 256,
445 FS = 257,
446 SS = 258,
447 PTR32_SPTR = 270,
448 PTR32_UPTR = 271,
449 PTR64 = 272
450};
451} // End X86AS namespace
452
453} // End llvm namespace
454
455#endif
456