1//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the X86 specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15
16#include "X86FrameLowering.h"
17#include "X86ISelLowering.h"
18#include "X86InstrInfo.h"
19#include "X86SelectionDAGInfo.h"
20#include "llvm/CodeGen/TargetSubtargetInfo.h"
21#include "llvm/IR/CallingConv.h"
22#include "llvm/TargetParser/Triple.h"
23#include <bitset>
24#include <climits>
25#include <memory>
26
27#define GET_SUBTARGETINFO_HEADER
28#include "X86GenSubtargetInfo.inc"
29
30namespace llvm {
31
32class CallLowering;
33class GlobalValue;
34class InstructionSelector;
35class LegalizerInfo;
36class RegisterBankInfo;
37class StringRef;
38class TargetMachine;
39
40/// The X86 backend supports a number of different styles of PIC.
41///
42namespace PICStyles {
43
44enum class Style {
45 StubPIC, // Used on i386-darwin in pic mode.
46 GOT, // Used on 32 bit elf on when in pic mode.
47 RIPRel, // Used on X86-64 when in pic mode.
48 None // Set when not in pic mode.
49};
50
51} // end namespace PICStyles
52
53class X86Subtarget final : public X86GenSubtargetInfo {
54 enum X86SSEEnum {
55 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512
56 };
57
58 /// Which PIC style to use
59 PICStyles::Style PICStyle;
60
61 const TargetMachine &TM;
62
63 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
64 X86SSEEnum X86SSELevel = NoSSE;
65
66#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
67 bool ATTRIBUTE = DEFAULT;
68#include "X86GenSubtargetInfo.inc"
69 /// ReservedRReg R#i is not available as a general purpose register.
70 std::bitset<X86::NUM_TARGET_REGS> ReservedRReg;
71
72 /// The minimum alignment known to hold of the stack frame on
73 /// entry to the function and which must be maintained by every function.
74 Align stackAlignment = Align(4);
75
76 Align TileConfigAlignment = Align(4);
77
78 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
79 ///
80 // FIXME: this is a known good value for Yonah. How about others?
81 unsigned MaxInlineSizeThreshold = 128;
82
83 /// What processor and OS we're targeting.
84 Triple TargetTriple;
85
86 /// GlobalISel related APIs.
87 std::unique_ptr<CallLowering> CallLoweringInfo;
88 std::unique_ptr<LegalizerInfo> Legalizer;
89 std::unique_ptr<RegisterBankInfo> RegBankInfo;
90 std::unique_ptr<InstructionSelector> InstSelector;
91
92 /// Override the stack alignment.
93 MaybeAlign StackAlignOverride;
94
95 /// Preferred vector width from function attribute.
96 unsigned PreferVectorWidthOverride;
97
98 /// Resolved preferred vector width from function attribute and subtarget
99 /// features.
100 unsigned PreferVectorWidth = UINT32_MAX;
101
102 /// Required vector width from function attribute.
103 unsigned RequiredVectorWidth;
104
105 bool HasUserReservedRegisters;
106
107 X86SelectionDAGInfo TSInfo;
108 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
109 // X86TargetLowering needs.
110 X86InstrInfo InstrInfo;
111 X86TargetLowering TLInfo;
112 X86FrameLowering FrameLowering;
113
114public:
115 /// This constructor initializes the data members to match that
116 /// of the specified triple.
117 ///
118 X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
119 const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
120 unsigned PreferVectorWidthOverride,
121 unsigned RequiredVectorWidth);
122 ~X86Subtarget() override;
123
124 const X86TargetLowering *getTargetLowering() const override {
125 return &TLInfo;
126 }
127
128 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
129
130 const X86FrameLowering *getFrameLowering() const override {
131 return &FrameLowering;
132 }
133
134 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
135 return &TSInfo;
136 }
137
138 const X86RegisterInfo *getRegisterInfo() const override {
139 return &getInstrInfo()->getRegisterInfo();
140 }
141
142 unsigned getTileConfigSize() const { return 64; }
143 Align getTileConfigAlignment() const { return TileConfigAlignment; }
144
145 /// Returns the minimum alignment known to hold of the
146 /// stack frame on entry to the function and which must be maintained by every
147 /// function for this subtarget.
148 Align getStackAlignment() const { return stackAlignment; }
149
150 /// Returns the maximum memset / memcpy size
151 /// that still makes it profitable to inline the call.
152 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
153
154 /// ParseSubtargetFeatures - Parses features string setting specified
155 /// subtarget options. Definition of function is auto generated by tblgen.
156 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
157
158 /// Methods used by Global ISel
159 const CallLowering *getCallLowering() const override;
160 InstructionSelector *getInstructionSelector() const override;
161 const LegalizerInfo *getLegalizerInfo() const override;
162 const RegisterBankInfo *getRegBankInfo() const override;
163
164 bool isRegisterReservedByUser(Register i) const override {
165 return ReservedRReg[i.id()];
166 }
167 bool hasUserReservedRegisters() const { return HasUserReservedRegisters; }
168
169private:
170 /// Initialize the full set of dependencies so we can use an initializer
171 /// list for X86Subtarget.
172 X86Subtarget &initializeSubtargetDependencies(StringRef CPU,
173 StringRef TuneCPU,
174 StringRef FS);
175 void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
176
177public:
178
179#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
180 bool GETTER() const { return ATTRIBUTE; }
181#include "X86GenSubtargetInfo.inc"
182
183 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
184 bool isTarget64BitILP32() const { return Is64Bit && IsX32; }
185
186 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
187 bool isTarget64BitLP64() const { return Is64Bit && !IsX32; }
188
189 PICStyles::Style getPICStyle() const { return PICStyle; }
190 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
191
192 bool canUseCMPXCHG8B() const { return hasCX8(); }
193 bool canUseCMPXCHG16B() const {
194 // CX16 is just the CPUID bit, instruction requires 64-bit mode too.
195 return hasCX16() && is64Bit();
196 }
197 // SSE codegen depends on cmovs, and all SSE1+ processors support them.
198 // All 64-bit processors support cmov.
199 bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); }
200 bool hasSSE1() const { return X86SSELevel >= SSE1; }
201 bool hasSSE2() const { return X86SSELevel >= SSE2; }
202 bool hasSSE3() const { return X86SSELevel >= SSE3; }
203 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
204 bool hasSSE41() const { return X86SSELevel >= SSE41; }
205 bool hasSSE42() const { return X86SSELevel >= SSE42; }
206 bool hasAVX() const { return X86SSELevel >= AVX; }
207 bool hasAVX2() const { return X86SSELevel >= AVX2; }
208 bool hasAVX512() const { return X86SSELevel >= AVX512; }
209 bool hasInt256() const { return hasAVX2(); }
210 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
211 bool hasPrefetchW() const {
212 // The PREFETCHW instruction was added with 3DNow but later CPUs gave it
213 // its own CPUID bit as part of deprecating 3DNow.
214 return hasPRFCHW();
215 }
216 bool hasSSEPrefetch() const {
217 // We also implicitly enable these when we have a write prefix supporting
218 // cache level OR if we have prfchw.
219 return hasSSE1() || hasPRFCHW() || hasPREFETCHI();
220 }
221 bool canUseLAHFSAHF() const { return hasLAHFSAHF64() || !is64Bit(); }
222 // These are generic getters that OR together all of the thunk types
223 // supported by the subtarget. Therefore useIndirectThunk*() will return true
224 // if any respective thunk feature is enabled.
225 bool useIndirectThunkCalls() const {
226 return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity();
227 }
228 bool useIndirectThunkBranches() const {
229 return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity();
230 }
231
232 unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
233 unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
234
235 // Helper functions to determine when we should allow widening to 512-bit
236 // during codegen.
237 // TODO: Currently we're always allowing widening on CPUs without VLX,
238 // because for many cases we don't have a better option.
239 bool canExtendTo512DQ() const {
240 return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
241 }
242 bool canExtendTo512BW() const {
243 return hasBWI() && canExtendTo512DQ();
244 }
245
246 bool hasNoDomainDelay() const { return NoDomainDelay; }
247 bool hasNoDomainDelayMov() const {
248 return hasNoDomainDelay() || NoDomainDelayMov;
249 }
250 bool hasNoDomainDelayBlend() const {
251 return hasNoDomainDelay() || NoDomainDelayBlend;
252 }
253 bool hasNoDomainDelayShuffle() const {
254 return hasNoDomainDelay() || NoDomainDelayShuffle;
255 }
256
257 // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
258 // disable them in the legalizer.
259 bool useAVX512Regs() const {
260 return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
261 }
262
263 bool useLight256BitInstructions() const {
264 return getPreferVectorWidth() >= 256 || AllowLight256Bit;
265 }
266
267 bool useBWIRegs() const {
268 return hasBWI() && useAVX512Regs();
269 }
270
271 // Returns true if the destination register of a BSF/BSR instruction is
272 // not touched if the source register is zero.
273 // NOTE: i32->i64 implicit zext isn't guaranteed by BSR/BSF pass through.
274 bool hasBitScanPassThrough() const { return is64Bit(); }
275
276 bool isXRaySupported() const override { return is64Bit(); }
277
278 /// Use clflush if we have SSE2 or we're on x86-64 (even if we asked for
279 /// no-sse2). There isn't any reason to disable it if the target processor
280 /// supports it.
281 bool hasCLFLUSH() const { return hasSSE2() || is64Bit(); }
282
283 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
284 /// no-sse2). There isn't any reason to disable it if the target processor
285 /// supports it.
286 bool hasMFence() const { return hasSSE2() || is64Bit(); }
287
288 /// Avoid use of `mfence` for`fence seq_cst`, and instead use `lock or`.
289 bool avoidMFence() const { return is64Bit(); }
290
291 const Triple &getTargetTriple() const { return TargetTriple; }
292
293 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
294 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
295 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
296 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
297 bool isTargetPS() const { return TargetTriple.isPS(); }
298
299 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
300 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
301 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
302
303 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
304 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
305 bool isTargetHurd() const { return TargetTriple.isOSHurd(); }
306 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
307 bool isTargetMusl() const { return TargetTriple.isMusl(); }
308 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
309 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
310 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
311
312 bool isTargetWindowsMSVC() const {
313 return TargetTriple.isWindowsMSVCEnvironment();
314 }
315
316 bool isTargetWindowsCoreCLR() const {
317 return TargetTriple.isWindowsCoreCLREnvironment();
318 }
319
320 bool isTargetWindowsCygwin() const {
321 return TargetTriple.isWindowsCygwinEnvironment();
322 }
323
324 bool isTargetWindowsGNU() const {
325 return TargetTriple.isWindowsGNUEnvironment();
326 }
327
328 bool isTargetWindowsItanium() const {
329 return TargetTriple.isWindowsItaniumEnvironment();
330 }
331
332 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
333
334 bool isUEFI() const { return TargetTriple.isUEFI(); }
335
336 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
337
338 bool isTargetUEFI64() const { return Is64Bit && isUEFI(); }
339
340 bool isTargetWin64() const { return Is64Bit && isOSWindows(); }
341
342 bool isTargetWin32() const { return !Is64Bit && isOSWindows(); }
343
344 bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; }
345 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }
346
347 bool isPICStyleStubPIC() const {
348 return PICStyle == PICStyles::Style::StubPIC;
349 }
350
351 bool isPositionIndependent() const;
352
353 bool isCallingConvWin64(CallingConv::ID CC) const {
354 switch (CC) {
355 // On Win64, all these conventions just use the default convention.
356 case CallingConv::C:
357 case CallingConv::Fast:
358 case CallingConv::Tail:
359 return isTargetWin64() || isTargetUEFI64();
360 case CallingConv::Swift:
361 case CallingConv::SwiftTail:
362 case CallingConv::X86_FastCall:
363 case CallingConv::X86_StdCall:
364 case CallingConv::X86_ThisCall:
365 case CallingConv::X86_VectorCall:
366 case CallingConv::Intel_OCL_BI:
367 return isTargetWin64();
368 // This convention allows using the Win64 convention on other targets.
369 case CallingConv::Win64:
370 return true;
371 // This convention allows using the SysV convention on Windows targets.
372 case CallingConv::X86_64_SysV:
373 return false;
374 // Otherwise, who knows what this is.
375 default:
376 return false;
377 }
378 }
379
380 /// Classify a global variable reference for the current subtarget according
381 /// to how we should reference it in a non-pcrel context.
382 unsigned char classifyLocalReference(const GlobalValue *GV) const;
383
384 unsigned char classifyGlobalReference(const GlobalValue *GV,
385 const Module &M) const;
386 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
387
388 /// Classify a global function reference for the current subtarget.
389 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
390 const Module &M) const;
391 unsigned char
392 classifyGlobalFunctionReference(const GlobalValue *GV) const override;
393
394 /// Classify a blockaddress reference for the current subtarget according to
395 /// how we should reference it in a non-pcrel context.
396 unsigned char classifyBlockAddressReference() const;
397
398 /// Return true if the subtarget allows calls to immediate address.
399 bool isLegalToCallImmediateAddr() const;
400
401 /// Return whether FrameLowering should always set the "extended frame
402 /// present" bit in FP, or set it based on a symbol in the runtime.
403 bool swiftAsyncContextIsDynamicallySet() const {
404 // Older OS versions (particularly system unwinders) are confused by the
405 // Swift extended frame, so when building code that might be run on them we
406 // must dynamically query the concurrency library to determine whether
407 // extended frames should be flagged as present.
408 const Triple &TT = getTargetTriple();
409
410 unsigned Major = TT.getOSVersion().getMajor();
411 switch(TT.getOS()) {
412 default:
413 return false;
414 case Triple::IOS:
415 case Triple::TvOS:
416 return Major < 15;
417 case Triple::WatchOS:
418 return Major < 8;
419 case Triple::MacOSX:
420 case Triple::Darwin:
421 return Major < 12;
422 }
423 }
424
425 /// If we are using indirect thunks, we need to expand indirectbr to avoid it
426 /// lowering to an actual indirect jump.
427 bool enableIndirectBrExpand() const override {
428 return useIndirectThunkBranches();
429 }
430
431 /// Enable the MachineScheduler pass for all X86 subtargets.
432 bool enableMachineScheduler() const override { return true; }
433
434 bool enableEarlyIfConversion() const override;
435
436 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
437 &Mutations) const override;
438
439 AntiDepBreakMode getAntiDepBreakMode() const override {
440 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
441 }
442};
443
444} // end namespace llvm
445
446#endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
447