1//===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86CallLowering.h"
16#include "X86CallingConv.h"
17#include "X86ISelLowering.h"
18#include "X86InstrInfo.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86RegisterInfo.h"
21#include "X86Subtarget.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/CodeGen/Analysis.h"
25#include "llvm/CodeGen/CallingConvLower.h"
26#include "llvm/CodeGen/FunctionLoweringInfo.h"
27#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
28#include "llvm/CodeGen/GlobalISel/Utils.h"
29#include "llvm/CodeGen/LowLevelTypeUtils.h"
30#include "llvm/CodeGen/MachineBasicBlock.h"
31#include "llvm/CodeGen/MachineFrameInfo.h"
32#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineInstrBuilder.h"
34#include "llvm/CodeGen/MachineMemOperand.h"
35#include "llvm/CodeGen/MachineOperand.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetSubtargetInfo.h"
39#include "llvm/CodeGen/ValueTypes.h"
40#include "llvm/CodeGenTypes/LowLevelType.h"
41#include "llvm/CodeGenTypes/MachineValueType.h"
42#include "llvm/IR/Attributes.h"
43#include "llvm/IR/DataLayout.h"
44#include "llvm/IR/Function.h"
45#include "llvm/IR/Value.h"
46#include <cassert>
47#include <cstdint>
48
49using namespace llvm;
50
51X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
52 : CallLowering(&TLI) {}
53
54namespace {
55
56struct X86OutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
57private:
58 uint64_t StackSize = 0;
59 unsigned NumXMMRegs = 0;
60
61public:
62 uint64_t getStackSize() { return StackSize; }
63 unsigned getNumXmmRegs() { return NumXMMRegs; }
64
65 X86OutgoingValueAssigner(CCAssignFn *AssignFn_)
66 : CallLowering::OutgoingValueAssigner(AssignFn_) {}
67
68 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
69 CCValAssign::LocInfo LocInfo,
70 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
71 CCState &State) override {
72 bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, Info.Ty, State);
73 StackSize = State.getStackSize();
74
75 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
76 X86::XMM3, X86::XMM4, X86::XMM5,
77 X86::XMM6, X86::XMM7};
78 if (Flags.isVarArg())
79 NumXMMRegs = State.getFirstUnallocated(Regs: XMMArgRegs);
80
81 return Res;
82 }
83};
84
85struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
86 X86OutgoingValueHandler(MachineIRBuilder &MIRBuilder,
87 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
88 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
89 DL(MIRBuilder.getMF().getDataLayout()),
90 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
91
92 Register getStackAddress(uint64_t Size, int64_t Offset,
93 MachinePointerInfo &MPO,
94 ISD::ArgFlagsTy Flags) override {
95 LLT p0 = LLT::pointer(AddressSpace: 0, SizeInBits: DL.getPointerSizeInBits(AS: 0));
96 LLT SType = LLT::scalar(SizeInBits: DL.getPointerSizeInBits(AS: 0));
97 auto SPReg =
98 MIRBuilder.buildCopy(Res: p0, Op: STI.getRegisterInfo()->getStackRegister());
99
100 auto OffsetReg = MIRBuilder.buildConstant(Res: SType, Val: Offset);
101
102 auto AddrReg = MIRBuilder.buildPtrAdd(Res: p0, Op0: SPReg, Op1: OffsetReg);
103
104 MPO = MachinePointerInfo::getStack(MF&: MIRBuilder.getMF(), Offset);
105 return AddrReg.getReg(Idx: 0);
106 }
107
108 void assignValueToReg(Register ValVReg, Register PhysReg,
109 const CCValAssign &VA,
110 ISD::ArgFlagsTy Flags = {}) override {
111 MIB.addUse(RegNo: PhysReg, Flags: RegState::Implicit);
112 Register ExtReg = extendRegister(ValReg: ValVReg, VA);
113 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
114 STI.getTargetLowering()->isScalarFPTypeInSSEReg(VT: VA.getValVT()))
115 ExtReg = MIRBuilder.buildFPExt(Res: LLT::scalar(SizeInBits: 80), Op: ExtReg).getReg(Idx: 0);
116 MIRBuilder.buildCopy(Res: PhysReg, Op: ExtReg);
117 }
118
119 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
120 const MachinePointerInfo &MPO,
121 const CCValAssign &VA) override {
122 MachineFunction &MF = MIRBuilder.getMF();
123 Register ExtReg = extendRegister(ValReg: ValVReg, VA);
124
125 auto *MMO = MF.getMachineMemOperand(PtrInfo: MPO, f: MachineMemOperand::MOStore, MemTy,
126 base_alignment: inferAlignFromPtrInfo(MF, MPO));
127 MIRBuilder.buildStore(Val: ExtReg, Addr, MMO&: *MMO);
128 }
129
130protected:
131 MachineInstrBuilder &MIB;
132 const DataLayout &DL;
133 const X86Subtarget &STI;
134};
135
136} // end anonymous namespace
137
138bool X86CallLowering::canLowerReturn(
139 MachineFunction &MF, CallingConv::ID CallConv,
140 SmallVectorImpl<CallLowering::BaseArgInfo> &Outs, bool IsVarArg) const {
141 LLVMContext &Context = MF.getFunction().getContext();
142 SmallVector<CCValAssign, 16> RVLocs;
143 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
144 return checkReturn(CCInfo, Outs, Fn: RetCC_X86);
145}
146
147bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
148 const Value *Val, ArrayRef<Register> VRegs,
149 FunctionLoweringInfo &FLI) const {
150 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
151 "Return value without a vreg");
152 MachineFunction &MF = MIRBuilder.getMF();
153 auto MIB = MIRBuilder.buildInstrNoInsert(Opcode: X86::RET).addImm(Val: 0);
154 auto FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
155 const auto &STI = MF.getSubtarget<X86Subtarget>();
156 Register RetReg = STI.is64Bit() ? X86::RAX : X86::EAX;
157
158 if (!FLI.CanLowerReturn) {
159 insertSRetStores(MIRBuilder, RetTy: Val->getType(), VRegs, DemoteReg: FLI.DemoteRegister);
160 MIRBuilder.buildCopy(Res: RetReg, Op: FLI.DemoteRegister);
161 MIB.addReg(RegNo: RetReg);
162 } else if (Register Reg = FuncInfo->getSRetReturnReg()) {
163 MIRBuilder.buildCopy(Res: RetReg, Op: Reg);
164 MIB.addReg(RegNo: RetReg);
165 } else if (!VRegs.empty()) {
166 const Function &F = MF.getFunction();
167 MachineRegisterInfo &MRI = MF.getRegInfo();
168 const DataLayout &DL = MF.getDataLayout();
169
170 ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
171 setArgFlags(Arg&: OrigRetInfo, OpIdx: AttributeList::ReturnIndex, DL, FuncInfo: F);
172
173 SmallVector<ArgInfo, 4> SplitRetInfos;
174 splitToValueTypes(OrigArgInfo: OrigRetInfo, SplitArgs&: SplitRetInfos, DL, CallConv: F.getCallingConv());
175
176 X86OutgoingValueAssigner Assigner(RetCC_X86);
177 X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
178 if (!determineAndHandleAssignments(Handler, Assigner, Args&: SplitRetInfos,
179 MIRBuilder, CallConv: F.getCallingConv(),
180 IsVarArg: F.isVarArg()))
181 return false;
182 }
183
184 MIRBuilder.insertInstr(MIB);
185 return true;
186}
187
188namespace {
189
190struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
191 X86IncomingValueHandler(MachineIRBuilder &MIRBuilder,
192 MachineRegisterInfo &MRI)
193 : IncomingValueHandler(MIRBuilder, MRI),
194 DL(MIRBuilder.getMF().getDataLayout()) {}
195
196 Register getStackAddress(uint64_t Size, int64_t Offset,
197 MachinePointerInfo &MPO,
198 ISD::ArgFlagsTy Flags) override {
199 auto &MFI = MIRBuilder.getMF().getFrameInfo();
200
201 // Byval is assumed to be writable memory, but other stack passed arguments
202 // are not.
203 const bool IsImmutable = !Flags.isByVal();
204
205 int FI = MFI.CreateFixedObject(Size, SPOffset: Offset, IsImmutable);
206 MPO = MachinePointerInfo::getFixedStack(MF&: MIRBuilder.getMF(), FI);
207
208 return MIRBuilder
209 .buildFrameIndex(Res: LLT::pointer(AddressSpace: 0, SizeInBits: DL.getPointerSizeInBits(AS: 0)), Idx: FI)
210 .getReg(Idx: 0);
211 }
212
213 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
214 const MachinePointerInfo &MPO,
215 const CCValAssign &VA) override {
216 MachineFunction &MF = MIRBuilder.getMF();
217 auto *MMO = MF.getMachineMemOperand(
218 PtrInfo: MPO, f: MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemTy,
219 base_alignment: inferAlignFromPtrInfo(MF, MPO));
220 MIRBuilder.buildLoad(Res: ValVReg, Addr, MMO&: *MMO);
221 }
222
223 void assignValueToReg(Register ValVReg, Register PhysReg,
224 const CCValAssign &VA,
225 ISD::ArgFlagsTy Flags = {}) override {
226 markPhysRegUsed(PhysReg: PhysReg.asMCReg());
227 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
228 }
229
230 /// How the physical register gets marked varies between formal
231 /// parameters (it's a basic-block live-in), and a call instruction
232 /// (it's an implicit-def of the BL).
233 virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
234
235protected:
236 const DataLayout &DL;
237};
238
239struct FormalArgHandler : public X86IncomingValueHandler {
240 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
241 : X86IncomingValueHandler(MIRBuilder, MRI) {}
242
243 void markPhysRegUsed(MCRegister PhysReg) override {
244 MIRBuilder.getMRI()->addLiveIn(Reg: PhysReg);
245 MIRBuilder.getMBB().addLiveIn(PhysReg);
246 }
247};
248
249struct CallReturnHandler : public X86IncomingValueHandler {
250 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
251 MachineInstrBuilder &MIB)
252 : X86IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
253
254 void markPhysRegUsed(MCRegister PhysReg) override {
255 MIB.addDef(RegNo: PhysReg, Flags: RegState::Implicit);
256 }
257
258protected:
259 MachineInstrBuilder &MIB;
260};
261
262} // end anonymous namespace
263
264bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
265 const Function &F,
266 ArrayRef<ArrayRef<Register>> VRegs,
267 FunctionLoweringInfo &FLI) const {
268 MachineFunction &MF = MIRBuilder.getMF();
269 MachineRegisterInfo &MRI = MF.getRegInfo();
270 auto DL = MF.getDataLayout();
271 auto FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
272
273 SmallVector<ArgInfo, 8> SplitArgs;
274
275 if (!FLI.CanLowerReturn)
276 insertSRetIncomingArgument(F, SplitArgs, DemoteReg&: FLI.DemoteRegister, MRI, DL);
277
278 // TODO: handle variadic function
279 if (F.isVarArg())
280 return false;
281
282 unsigned Idx = 0;
283 for (const auto &Arg : F.args()) {
284 // TODO: handle not simple cases.
285 if (Arg.hasAttribute(Kind: Attribute::ByVal) ||
286 Arg.hasAttribute(Kind: Attribute::InReg) ||
287 Arg.hasAttribute(Kind: Attribute::SwiftSelf) ||
288 Arg.hasAttribute(Kind: Attribute::SwiftError) || VRegs[Idx].size() > 1)
289 return false;
290
291 if (Arg.hasAttribute(Kind: Attribute::StructRet)) {
292 assert(VRegs[Idx].size() == 1 &&
293 "Unexpected amount of registers for sret argument.");
294 FuncInfo->setSRetReturnReg(VRegs[Idx][0]);
295 }
296
297 ArgInfo OrigArg(VRegs[Idx], Arg.getType(), Idx);
298 setArgFlags(Arg&: OrigArg, OpIdx: Idx + AttributeList::FirstArgIndex, DL, FuncInfo: F);
299 splitToValueTypes(OrigArgInfo: OrigArg, SplitArgs, DL, CallConv: F.getCallingConv());
300 Idx++;
301 }
302
303 if (SplitArgs.empty())
304 return true;
305
306 MachineBasicBlock &MBB = MIRBuilder.getMBB();
307 if (!MBB.empty())
308 MIRBuilder.setInstr(*MBB.begin());
309
310 X86OutgoingValueAssigner Assigner(CC_X86);
311 FormalArgHandler Handler(MIRBuilder, MRI);
312 if (!determineAndHandleAssignments(Handler, Assigner, Args&: SplitArgs, MIRBuilder,
313 CallConv: F.getCallingConv(), IsVarArg: F.isVarArg()))
314 return false;
315
316 // Move back to the end of the basic block.
317 MIRBuilder.setMBB(MBB);
318
319 return true;
320}
321
322bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
323 CallLoweringInfo &Info) const {
324 MachineFunction &MF = MIRBuilder.getMF();
325 const Function &F = MF.getFunction();
326 MachineRegisterInfo &MRI = MF.getRegInfo();
327 const DataLayout &DL = F.getDataLayout();
328 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
329 const TargetInstrInfo &TII = *STI.getInstrInfo();
330 const X86RegisterInfo *TRI = STI.getRegisterInfo();
331
332 // Handle only Linux C, X86_64_SysV calling conventions for now.
333 if (!STI.isTargetLinux() || !(Info.CallConv == CallingConv::C ||
334 Info.CallConv == CallingConv::X86_64_SysV))
335 return false;
336
337 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
338 auto CallSeqStart = MIRBuilder.buildInstr(Opcode: AdjStackDown);
339
340 // Create a temporarily-floating call instruction so we can add the implicit
341 // uses of arg registers.
342 bool Is64Bit = STI.is64Bit();
343 unsigned CallOpc = Info.Callee.isReg()
344 ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
345 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
346
347 auto MIB = MIRBuilder.buildInstrNoInsert(Opcode: CallOpc)
348 .add(MO: Info.Callee)
349 .addRegMask(Mask: TRI->getCallPreservedMask(MF, Info.CallConv));
350
351 SmallVector<ArgInfo, 8> SplitArgs;
352 for (const auto &OrigArg : Info.OrigArgs) {
353
354 // TODO: handle not simple cases.
355 if (OrigArg.Flags[0].isByVal())
356 return false;
357
358 if (OrigArg.Regs.size() > 1)
359 return false;
360
361 splitToValueTypes(OrigArgInfo: OrigArg, SplitArgs, DL, CallConv: Info.CallConv);
362 }
363 // Do the actual argument marshalling.
364 X86OutgoingValueAssigner Assigner(CC_X86);
365 X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
366 if (!determineAndHandleAssignments(Handler, Assigner, Args&: SplitArgs, MIRBuilder,
367 CallConv: Info.CallConv, IsVarArg: Info.IsVarArg))
368 return false;
369
370 bool IsFixed =
371 Info.OrigArgs.empty() ? true : !Info.OrigArgs.back().Flags[0].isVarArg();
372 if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CC: Info.CallConv)) {
373 // From AMD64 ABI document:
374 // For calls that may call functions that use varargs or stdargs
375 // (prototype-less calls or calls to functions containing ellipsis (...) in
376 // the declaration) %al is used as hidden argument to specify the number
377 // of SSE registers used. The contents of %al do not need to match exactly
378 // the number of registers, but must be an ubound on the number of SSE
379 // registers used and is in the range 0 - 8 inclusive.
380
381 MIRBuilder.buildInstr(Opcode: X86::MOV8ri)
382 .addDef(RegNo: X86::AL)
383 .addImm(Val: Assigner.getNumXmmRegs());
384 MIB.addUse(RegNo: X86::AL, Flags: RegState::Implicit);
385 }
386
387 // Now we can add the actual call instruction to the correct basic block.
388 MIRBuilder.insertInstr(MIB);
389
390 // If Callee is a reg, since it is used by a target specific
391 // instruction, it must have a register class matching the
392 // constraint of that instruction.
393 if (Info.Callee.isReg())
394 MIB->getOperand(i: 0).setReg(constrainOperandRegClass(
395 MF, TRI: *TRI, MRI, TII: *MF.getSubtarget().getInstrInfo(),
396 RBI: *MF.getSubtarget().getRegBankInfo(), InsertPt&: *MIB, II: MIB->getDesc(), RegMO&: Info.Callee,
397 OpIdx: 0));
398
399 // Finally we can copy the returned value back into its virtual-register. In
400 // symmetry with the arguments, the physical register must be an
401 // implicit-define of the call instruction.
402
403 if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
404 if (Info.OrigRet.Regs.size() > 1)
405 return false;
406
407 SplitArgs.clear();
408 SmallVector<Register, 8> NewRegs;
409
410 splitToValueTypes(OrigArgInfo: Info.OrigRet, SplitArgs, DL, CallConv: Info.CallConv);
411
412 X86OutgoingValueAssigner Assigner(RetCC_X86);
413 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
414 if (!determineAndHandleAssignments(Handler, Assigner, Args&: SplitArgs, MIRBuilder,
415 CallConv: Info.CallConv, IsVarArg: Info.IsVarArg))
416 return false;
417
418 if (!NewRegs.empty())
419 MIRBuilder.buildMergeLikeInstr(Res: Info.OrigRet.Regs[0], Ops: NewRegs);
420 }
421
422 CallSeqStart.addImm(Val: Assigner.getStackSize())
423 .addImm(Val: 0 /* see getFrameTotalSize */)
424 .addImm(Val: 0 /* see getFrameAdjustment */);
425
426 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
427 MIRBuilder.buildInstr(Opcode: AdjStackUp)
428 .addImm(Val: Assigner.getStackSize())
429 .addImm(Val: 0 /* NumBytesForCalleeToPop */);
430
431 if (!Info.CanLowerReturn)
432 insertSRetLoads(MIRBuilder, RetTy: Info.OrigRet.Ty, VRegs: Info.OrigRet.Regs,
433 DemoteReg: Info.DemoteRegister, FI: Info.DemoteStackIndex);
434
435 return true;
436}
437