1//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15
16#include "MCTargetDesc/X86BaseInfo.h"
17#include "X86InstrFMA3Info.h"
18#include "X86RegisterInfo.h"
19#include "llvm/CodeGen/ISDOpcodes.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include <vector>
22
23#define GET_INSTRINFO_HEADER
24#include "X86GenInstrInfo.inc"
25
26namespace llvm {
27class X86Subtarget;
28
29// X86 MachineCombiner patterns
30enum X86MachineCombinerPattern : unsigned {
31 // X86 VNNI
32 DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START,
33};
34
35namespace X86 {
36
37enum AsmComments : MachineInstr::AsmPrinterFlagTy {
38 // For instr that was compressed from EVEX to LEGACY.
39 AC_EVEX_2_LEGACY = MachineInstr::TAsmComments,
40 // For instr that was compressed from EVEX to VEX.
41 AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1,
42 // For instr that was compressed from EVEX to EVEX.
43 AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1
44};
45
46/// Return a pair of condition code for the given predicate and whether
47/// the instruction operands should be swaped to match the condition code.
48std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
49
50/// Return a cmov opcode for the given register size in bytes, and operand type.
51unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,
52 bool HasNDD = false);
53
54/// Return the source operand # for condition code by \p MCID. If the
55/// instruction doesn't have a condition code, return -1.
56int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
57
58/// Return the condition code of the instruction. If the instruction doesn't
59/// have a condition code, return X86::COND_INVALID.
60CondCode getCondFromMI(const MachineInstr &MI);
61
62// Turn JCC instruction into condition code.
63CondCode getCondFromBranch(const MachineInstr &MI);
64
65// Turn SETCC instruction into condition code.
66CondCode getCondFromSETCC(const MachineInstr &MI);
67
68// Turn CMOV instruction into condition code.
69CondCode getCondFromCMov(const MachineInstr &MI);
70
71// Turn CFCMOV instruction into condition code.
72CondCode getCondFromCFCMov(const MachineInstr &MI);
73
74// Turn CCMP instruction into condition code.
75CondCode getCondFromCCMP(const MachineInstr &MI);
76
77// Turn condition code into condition flags for CCMP/CTEST.
78int getCCMPCondFlagsFromCondCode(CondCode CC);
79
80// Get the opcode of corresponding NF variant.
81unsigned getNFVariant(unsigned Opc);
82
83// Get the opcode of corresponding NonND variant.
84unsigned getNonNDVariant(unsigned Opc);
85
86/// GetOppositeBranchCondition - Return the inverse of the specified cond,
87/// e.g. turning COND_E to COND_NE.
88CondCode GetOppositeBranchCondition(CondCode CC);
89
90/// Get the VPCMP immediate for the given condition.
91unsigned getVPCMPImmForCond(ISD::CondCode CC);
92
93/// Get the VPCMP immediate if the opcodes are swapped.
94unsigned getSwappedVPCMPImm(unsigned Imm);
95
96/// Get the VPCOM immediate if the opcodes are swapped.
97unsigned getSwappedVPCOMImm(unsigned Imm);
98
99/// Get the VCMP immediate if the opcodes are swapped.
100unsigned getSwappedVCMPImm(unsigned Imm);
101
102/// Get the width of the vector register operand.
103unsigned getVectorRegisterWidth(const MCOperandInfo &Info);
104
105/// Check if the instruction is X87 instruction.
106bool isX87Instruction(MachineInstr &MI);
107
108/// Return the index of the instruction's first address operand, if it has a
109/// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(),
110/// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as
111/// real instructions (e.g., JMP64m).
112int getFirstAddrOperandIdx(const MachineInstr &MI);
113
114/// Find any constant pool entry associated with a specific instruction operand.
115const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo);
116
117} // namespace X86
118
119/// isGlobalStubReference - Return true if the specified TargetFlag operand is
120/// a reference to a stub for a global, not the global itself.
121inline static bool isGlobalStubReference(unsigned char TargetFlag) {
122 switch (TargetFlag) {
123 case X86II::MO_DLLIMPORT: // dllimport stub.
124 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
125 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
126 case X86II::MO_GOT: // normal GOT reference.
127 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
128 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
129 case X86II::MO_COFFSTUB: // COFF .refptr stub.
130 return true;
131 default:
132 return false;
133 }
134}
135
136/// isGlobalRelativeToPICBase - Return true if the specified global value
137/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
138/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
139inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
140 switch (TargetFlag) {
141 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
142 case X86II::MO_GOT: // isPICStyleGOT: other global.
143 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
144 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
145 case X86II::MO_TLVP: // ??? Pretty sure..
146 return true;
147 default:
148 return false;
149 }
150}
151
152inline static bool isScale(const MachineOperand &MO) {
153 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
154 MO.getImm() == 4 || MO.getImm() == 8);
155}
156
157inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
158 if (MI.getOperand(i: Op).isFI())
159 return true;
160 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
161 MI.getOperand(i: Op + X86::AddrBaseReg).isReg() &&
162 isScale(MO: MI.getOperand(i: Op + X86::AddrScaleAmt)) &&
163 MI.getOperand(i: Op + X86::AddrIndexReg).isReg() &&
164 (MI.getOperand(i: Op + X86::AddrDisp).isImm() ||
165 MI.getOperand(i: Op + X86::AddrDisp).isGlobal() ||
166 MI.getOperand(i: Op + X86::AddrDisp).isCPI() ||
167 MI.getOperand(i: Op + X86::AddrDisp).isJTI());
168}
169
170inline static bool isMem(const MachineInstr &MI, unsigned Op) {
171 if (MI.getOperand(i: Op).isFI())
172 return true;
173 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
174 MI.getOperand(i: Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
175}
176
177inline static bool isAddMemInstrWithRelocation(const MachineInstr &MI) {
178 unsigned Op = MI.getOpcode();
179 if (Op == X86::ADD64rm || Op == X86::ADD64mr_ND || Op == X86::ADD64rm_ND) {
180 int MemOpNo = X86II::getMemoryOperandNo(TSFlags: MI.getDesc().TSFlags) +
181 X86II::getOperandBias(Desc: MI.getDesc());
182 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
183 if (MO.getTargetFlags() == X86II::MO_GOTTPOFF)
184 return true;
185 }
186
187 return false;
188}
189
190inline static bool isMemInstrWithGOTPCREL(const MachineInstr &MI) {
191 unsigned Op = MI.getOpcode();
192 switch (Op) {
193 case X86::TEST32mr:
194 case X86::TEST64mr:
195 case X86::CMP32rm:
196 case X86::CMP64rm:
197 case X86::MOV32rm:
198 case X86::MOV64rm:
199 case X86::ADC32rm:
200 case X86::ADD32rm:
201 case X86::AND32rm:
202 case X86::OR32rm:
203 case X86::SBB32rm:
204 case X86::SUB32rm:
205 case X86::XOR32rm:
206 case X86::ADC64rm:
207 case X86::ADD64rm:
208 case X86::AND64rm:
209 case X86::OR64rm:
210 case X86::SBB64rm:
211 case X86::SUB64rm:
212 case X86::XOR64rm: {
213 int MemOpNo = X86II::getMemoryOperandNo(TSFlags: MI.getDesc().TSFlags) +
214 X86II::getOperandBias(Desc: MI.getDesc());
215 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
216 if (MO.getTargetFlags() == X86II::MO_GOTPCREL)
217 return true;
218 break;
219 }
220 }
221 return false;
222}
223
224class X86InstrInfo final : public X86GenInstrInfo {
225 const X86Subtarget &Subtarget;
226 const X86RegisterInfo RI;
227
228 LLVM_DECLARE_VIRTUAL_ANCHOR_FUNCTION();
229
230 bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
231 MachineBasicBlock *&FBB,
232 SmallVectorImpl<MachineOperand> &Cond,
233 SmallVectorImpl<MachineInstr *> &CondBranches,
234 bool AllowModify) const;
235
236 bool foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg,
237 int64_t ImmVal, MachineRegisterInfo *MRI,
238 bool MakeChange) const;
239
240public:
241 explicit X86InstrInfo(const X86Subtarget &STI);
242
243 /// Given a machine instruction descriptor, returns the register
244 /// class constraint for OpNum, or NULL. Returned register class
245 /// may be different from the definition in the TD file, e.g.
246 /// GR*RegClass (definition in TD file)
247 /// ->
248 /// GR*_NOREX2RegClass (Returned register class)
249 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID,
250 unsigned OpNum) const override;
251
252 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
253 /// such, whenever a client has an instance of instruction info, it should
254 /// always be able to get register info as well (through this method).
255 ///
256 const X86RegisterInfo &getRegisterInfo() const { return RI; }
257
258 /// Returns the stack pointer adjustment that happens inside the frame
259 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
260 int64_t getFrameAdjustment(const MachineInstr &I) const {
261 assert(isFrameInstr(I));
262 if (isFrameSetup(I))
263 return I.getOperand(i: 2).getImm();
264 return I.getOperand(i: 1).getImm();
265 }
266
267 /// Sets the stack pointer adjustment made inside the frame made up by this
268 /// instruction.
269 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
270 assert(isFrameInstr(I));
271 if (isFrameSetup(I))
272 I.getOperand(i: 2).setImm(V);
273 else
274 I.getOperand(i: 1).setImm(V);
275 }
276
277 /// getSPAdjust - This returns the stack pointer adjustment made by
278 /// this instruction. For x86, we need to handle more complex call
279 /// sequences involving PUSHes.
280 int getSPAdjust(const MachineInstr &MI) const override;
281
282 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
283 /// extension instruction. That is, it's like a copy where it's legal for the
284 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
285 /// true, then it's expected the pre-extension value is available as a subreg
286 /// of the result register. This also returns the sub-register index in
287 /// SubIdx.
288 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
289 Register &DstReg, unsigned &SubIdx) const override;
290
291 /// Returns true if the instruction has no behavior (specified or otherwise)
292 /// that is based on the value of any of its register operands
293 ///
294 /// Instructions are considered data invariant even if they set EFLAGS.
295 ///
296 /// A classical example of something that is inherently not data invariant is
297 /// an indirect jump -- the destination is loaded into icache based on the
298 /// bits set in the jump destination register.
299 ///
300 /// FIXME: This should become part of our instruction tables.
301 static bool isDataInvariant(MachineInstr &MI);
302
303 /// Returns true if the instruction has no behavior (specified or otherwise)
304 /// that is based on the value loaded from memory or the value of any
305 /// non-address register operands.
306 ///
307 /// For example, if the latency of the instruction is dependent on the
308 /// particular bits set in any of the registers *or* any of the bits loaded
309 /// from memory.
310 ///
311 /// Instructions are considered data invariant even if they set EFLAGS.
312 ///
313 /// A classical example of something that is inherently not data invariant is
314 /// an indirect jump -- the destination is loaded into icache based on the
315 /// bits set in the jump destination register.
316 ///
317 /// FIXME: This should become part of our instruction tables.
318 static bool isDataInvariantLoad(MachineInstr &MI);
319
320 Register isLoadFromStackSlot(const MachineInstr &MI,
321 int &FrameIndex) const override;
322 Register isLoadFromStackSlot(const MachineInstr &MI,
323 int &FrameIndex,
324 TypeSize &MemBytes) const override;
325 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
326 /// stack locations as well. This uses a heuristic so it isn't
327 /// reliable for correctness.
328 Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
329 int &FrameIndex) const override;
330
331 Register isStoreToStackSlot(const MachineInstr &MI,
332 int &FrameIndex) const override;
333 Register isStoreToStackSlot(const MachineInstr &MI,
334 int &FrameIndex,
335 TypeSize &MemBytes) const override;
336 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
337 /// stack locations as well. This uses a heuristic so it isn't
338 /// reliable for correctness.
339 Register isStoreToStackSlotPostFE(const MachineInstr &MI,
340 int &FrameIndex) const override;
341
342 bool isReMaterializableImpl(const MachineInstr &MI) const override;
343 void
344 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
345 Register DestReg, unsigned SubIdx, const MachineInstr &Orig,
346 LaneBitmask UsedLanes = LaneBitmask::getAll()) const override;
347
348 /// Given an operand within a MachineInstr, insert preceding code to put it
349 /// into the right format for a particular kind of LEA instruction. This may
350 /// involve using an appropriate super-register instead (with an implicit use
351 /// of the original) or creating a new virtual register and inserting COPY
352 /// instructions to get the data into the right class.
353 ///
354 /// Reference parameters are set to indicate how caller should add this
355 /// operand to the LEA instruction.
356 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
357 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
358 unsigned &NewSrcSubReg, bool &isKill,
359 MachineOperand &ImplicitOp, LiveVariables *LV,
360 LiveIntervals *LIS) const;
361
362 /// convertToThreeAddress - This method must be implemented by targets that
363 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
364 /// may be able to convert a two-address instruction into a true
365 /// three-address instruction on demand. This allows the X86 target (for
366 /// example) to convert ADD and SHL instructions into LEA instructions if they
367 /// would require register copies due to two-addressness.
368 ///
369 /// This method returns a null pointer if the transformation cannot be
370 /// performed, otherwise it returns the new instruction.
371 ///
372 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
373 LiveIntervals *LIS) const override;
374
375 /// Returns true iff the routine could find two commutable operands in the
376 /// given machine instruction.
377 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
378 /// input values can be re-defined in this method only if the input values
379 /// are not pre-defined, which is designated by the special value
380 /// 'CommuteAnyOperandIndex' assigned to it.
381 /// If both of indices are pre-defined and refer to some operands, then the
382 /// method simply returns true if the corresponding operands are commutable
383 /// and returns false otherwise.
384 ///
385 /// For example, calling this method this way:
386 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
387 /// findCommutedOpIndices(MI, Op1, Op2);
388 /// can be interpreted as a query asking to find an operand that would be
389 /// commutable with the operand#1.
390 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
391 unsigned &SrcOpIdx2) const override;
392
393 /// Returns true if we have preference on the operands order in MI, the
394 /// commute decision is returned in Commute.
395 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
396
397 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
398 /// performs the same computations as the given \p MI but which has the
399 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
400 /// It may return 0 if it is unsafe to commute the operands.
401 /// Note that a machine instruction (instead of its opcode) is passed as the
402 /// first parameter to make it possible to analyze the instruction's uses and
403 /// commute the first operand of FMA even when it seems unsafe when you look
404 /// at the opcode. For example, it is Ok to commute the first operand of
405 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
406 ///
407 /// The returned FMA opcode may differ from the opcode in the given \p MI.
408 /// For example, commuting the operands #1 and #3 in the following FMA
409 /// FMA213 #1, #2, #3
410 /// results into instruction with adjusted opcode:
411 /// FMA231 #3, #2, #1
412 unsigned
413 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
414 unsigned SrcOpIdx2,
415 const X86InstrFMA3Group &FMA3Group) const;
416
417 // Branch analysis.
418 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
419 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
420 const MachineInstr &TailCall) const override;
421 void replaceBranchWithTailCall(MachineBasicBlock &MBB,
422 SmallVectorImpl<MachineOperand> &Cond,
423 const MachineInstr &TailCall) const override;
424
425 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
426 MachineBasicBlock *&FBB,
427 SmallVectorImpl<MachineOperand> &Cond,
428 bool AllowModify) const override;
429
430 int getJumpTableIndex(const MachineInstr &MI) const override;
431
432 std::optional<ExtAddrMode>
433 getAddrModeFromMemoryOp(const MachineInstr &MemI,
434 const TargetRegisterInfo *TRI) const override;
435
436 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
437 int64_t &ImmVal) const override;
438
439 bool preservesZeroValueInReg(const MachineInstr *MI,
440 const Register NullValueReg,
441 const TargetRegisterInfo *TRI) const override;
442
443 bool getMemOperandsWithOffsetWidth(
444 const MachineInstr &LdSt,
445 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
446 bool &OffsetIsScalable, LocationSize &Width,
447 const TargetRegisterInfo *TRI) const override;
448 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
449 TargetInstrInfo::MachineBranchPredicate &MBP,
450 bool AllowModify = false) const override;
451
452 unsigned removeBranch(MachineBasicBlock &MBB,
453 int *BytesRemoved = nullptr) const override;
454 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
455 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
456 const DebugLoc &DL,
457 int *BytesAdded = nullptr) const override;
458 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
459 Register, Register, Register, int &, int &,
460 int &) const override;
461 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
462 const DebugLoc &DL, Register DstReg,
463 ArrayRef<MachineOperand> Cond, Register TrueReg,
464 Register FalseReg) const override;
465 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
466 const DebugLoc &DL, Register DestReg, Register SrcReg,
467 bool KillSrc, bool RenamableDest = false,
468 bool RenamableSrc = false) const override;
469 void storeRegToStackSlot(
470 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
471 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
472 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
473
474 void loadRegFromStackSlot(
475 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
476 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
477 unsigned SubReg = 0,
478 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
479
480 void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
481 unsigned Opc, Register Reg, int FrameIdx,
482 bool isKill = false) const;
483
484 bool expandPostRAPseudo(MachineInstr &MI) const override;
485
486 /// Check whether the target can fold a load that feeds a subreg operand
487 /// (or a subreg operand that feeds a store).
488 bool isSubregFoldable() const override { return true; }
489
490 /// Fold a load or store of the specified stack slot into the specified
491 /// machine instruction for the specified operand(s). If folding happens, it
492 /// is likely that the referenced instruction has been changed.
493 ///
494 /// \returns true on success.
495 MachineInstr *
496 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
497 ArrayRef<unsigned> Ops,
498 MachineBasicBlock::iterator InsertPt, int FrameIndex,
499 LiveIntervals *LIS = nullptr,
500 VirtRegMap *VRM = nullptr) const override;
501
502 /// Same as the previous version except it allows folding of any load and
503 /// store from / to any address, not just from a specific stack slot.
504 MachineInstr *foldMemoryOperandImpl(
505 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
506 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
507 LiveIntervals *LIS = nullptr) const override;
508
509 bool
510 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, Register Reg,
511 bool UnfoldLoad, bool UnfoldStore,
512 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
513
514 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
515 SmallVectorImpl<SDNode *> &NewNodes) const override;
516
517 unsigned
518 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
519 unsigned *LoadRegIndex = nullptr) const override;
520
521 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
522 int64_t &Offset2) const override;
523
524 /// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to
525 /// make it capable of identifying ENDBR intructions and prevent it from being
526 /// re-scheduled.
527 bool isSchedulingBoundary(const MachineInstr &MI,
528 const MachineBasicBlock *MBB,
529 const MachineFunction &MF) const override;
530
531 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
532 /// with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On
533 /// some targets if two loads are loading from addresses in the same cache
534 /// line, it's better if they are scheduled together. This function takes two
535 /// integers that represent the load offsets from the common base address. It
536 /// returns true if it decides it's desirable to schedule the two loads
537 /// together. "NumLoads" is the number of loads that have already been
538 /// scheduled after Load1.
539 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
540 int64_t Offset2,
541 unsigned NumLoads) const override;
542
543 void insertNoop(MachineBasicBlock &MBB,
544 MachineBasicBlock::iterator MI) const override;
545
546 MCInst getNop() const override;
547
548 bool
549 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
550
551 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
552
553 /// True if MI has a condition code def, e.g. EFLAGS, that is
554 /// not marked dead.
555 bool hasLiveCondCodeDef(MachineInstr &MI) const;
556
557 /// getGlobalBaseReg - Return a virtual register initialized with the
558 /// the global base register value. Output instructions required to
559 /// initialize the register in the function entry block, if necessary.
560 ///
561 Register getGlobalBaseReg(MachineFunction *MF) const;
562
563 std::pair<uint16_t, uint16_t>
564 getExecutionDomain(const MachineInstr &MI) const override;
565
566 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
567
568 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
569
570 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
571
572 unsigned
573 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
574 const TargetRegisterInfo *TRI) const override;
575 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
576 const TargetRegisterInfo *TRI) const override;
577 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
578 const TargetRegisterInfo *TRI) const override;
579
580 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
581 unsigned OpNum,
582 ArrayRef<MachineOperand> MOs,
583 MachineBasicBlock::iterator InsertPt,
584 unsigned Size, Align Alignment,
585 bool AllowCommute) const;
586
587 bool isHighLatencyDef(int opc) const override;
588
589 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
590 const MachineRegisterInfo *MRI,
591 const MachineInstr &DefMI, unsigned DefIdx,
592 const MachineInstr &UseMI,
593 unsigned UseIdx) const override;
594
595 bool useMachineCombiner() const override { return true; }
596
597 bool isAssociativeAndCommutative(const MachineInstr &Inst,
598 bool Invert) const override;
599
600 bool hasReassociableOperands(const MachineInstr &Inst,
601 const MachineBasicBlock *MBB) const override;
602
603 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
604 MachineInstr &NewMI1,
605 MachineInstr &NewMI2) const override;
606
607 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
608 Register &SrcReg2, int64_t &CmpMask,
609 int64_t &CmpValue) const override;
610
611 /// Check if there exists an earlier instruction that operates on the same
612 /// source operands and sets eflags in the same way as CMP and remove CMP if
613 /// possible.
614 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
615 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
616 const MachineRegisterInfo *MRI) const override;
617
618 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
619 MachineRegisterInfo *MRI) const override;
620
621 std::pair<unsigned, unsigned>
622 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
623
624 ArrayRef<std::pair<unsigned, const char *>>
625 getSerializableDirectMachineOperandTargetFlags() const override;
626
627 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
628 getOutliningCandidateInfo(
629 const MachineModuleInfo &MMI,
630 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
631 unsigned MinRepeats) const override;
632
633 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
634 bool OutlineFromLinkOnceODRs) const override;
635
636 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
637 MachineBasicBlock::iterator &MIT,
638 unsigned Flags) const override;
639
640 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
641 const outliner::OutlinedFunction &OF) const override;
642
643 MachineBasicBlock::iterator
644 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
645 MachineBasicBlock::iterator &It, MachineFunction &MF,
646 outliner::Candidate &C) const override;
647
648 void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
649 MachineBasicBlock::iterator Iter, DebugLoc &DL,
650 bool AllowSideEffects = true) const override;
651
652 bool verifyInstruction(const MachineInstr &MI,
653 StringRef &ErrInfo) const override;
654#define GET_INSTRINFO_HELPER_DECLS
655#include "X86GenInstrInfo.inc"
656
657 static bool hasLockPrefix(const MachineInstr &MI) {
658 return MI.getDesc().TSFlags & X86II::LOCK;
659 }
660
661 std::optional<ParamLoadedValue>
662 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
663
664protected:
665 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
666 unsigned CommuteOpIdx1,
667 unsigned CommuteOpIdx2) const override;
668
669 std::optional<DestSourcePair>
670 isCopyInstrImpl(const MachineInstr &MI) const override;
671
672 bool getMachineCombinerPatterns(MachineInstr &Root,
673 SmallVectorImpl<unsigned> &Patterns,
674 bool DoRegPressureReduce) const override;
675
676 /// When getMachineCombinerPatterns() finds potential patterns,
677 /// this function generates the instructions that could replace the
678 /// original code sequence.
679 void genAlternativeCodeSequence(
680 MachineInstr &Root, unsigned Pattern,
681 SmallVectorImpl<MachineInstr *> &InsInstrs,
682 SmallVectorImpl<MachineInstr *> &DelInstrs,
683 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
684
685 /// When calculate the latency of the root instruction, accumulate the
686 /// latency of the sequence to the root latency.
687 /// \param Root - Instruction that could be combined with one of its operands
688 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd
689 /// is not in the critical path, so the root latency only include vpmaddwd.
690 bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override {
691 return false;
692 }
693
694 void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
695 int FI) const override;
696
697private:
698 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
699 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
700 /// super-register and then truncating back down to a 8/16-bit sub-register.
701 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
702 LiveVariables *LV,
703 LiveIntervals *LIS,
704 bool Is8BitOp) const;
705
706 /// Handles memory folding for special case instructions, for instance those
707 /// requiring custom manipulation of the address.
708 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
709 unsigned OpNum,
710 ArrayRef<MachineOperand> MOs,
711 MachineBasicBlock::iterator InsertPt,
712 unsigned Size, Align Alignment) const;
713
714 MachineInstr *foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
715 unsigned OpNum,
716 ArrayRef<MachineOperand> MOs,
717 MachineBasicBlock::iterator InsertPt,
718 unsigned BitsSize, bool AllowCommute) const;
719
720 /// isFrameOperand - Return true and the FrameIndex if the specified
721 /// operand and follow operands form a reference to the stack frame.
722 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
723 int &FrameIndex) const;
724
725 /// Returns true iff the routine could find two commutable operands in the
726 /// given machine instruction with 3 vector inputs.
727 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
728 /// input values can be re-defined in this method only if the input values
729 /// are not pre-defined, which is designated by the special value
730 /// 'CommuteAnyOperandIndex' assigned to it.
731 /// If both of indices are pre-defined and refer to some operands, then the
732 /// method simply returns true if the corresponding operands are commutable
733 /// and returns false otherwise.
734 ///
735 /// For example, calling this method this way:
736 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
737 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
738 /// can be interpreted as a query asking to find an operand that would be
739 /// commutable with the operand#1.
740 ///
741 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
742 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
743 unsigned &SrcOpIdx1,
744 unsigned &SrcOpIdx2,
745 bool IsIntrinsic = false) const;
746
747 /// Returns true when instruction \p FlagI produces the same flags as \p OI.
748 /// The caller should pass in the results of calling analyzeCompare on \p OI:
749 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
750 /// If the flags match \p OI as if it had the input operands swapped then the
751 /// function succeeds and sets \p IsSwapped to true.
752 ///
753 /// Examples of OI, FlagI pairs returning true:
754 /// CMP %1, 42 and CMP %1, 42
755 /// CMP %1, %2 and %3 = SUB %1, %2
756 /// TEST %1, %1 and %2 = SUB %1, 0
757 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
758 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
759 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
760 const MachineInstr &OI, bool *IsSwapped,
761 int64_t *ImmDelta) const;
762
763 /// Commute operands of \p MI for memory fold.
764 ///
765 /// \param Idx1 the index of operand to be commuted.
766 ///
767 /// \returns the index of operand that is commuted with \p Idx1. If the method
768 /// fails to commute the operands, it will return \p Idx1.
769 unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const;
770};
771} // namespace llvm
772
773#endif
774