1//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15
16#include "MCTargetDesc/X86BaseInfo.h"
17#include "X86InstrFMA3Info.h"
18#include "X86RegisterInfo.h"
19#include "llvm/CodeGen/ISDOpcodes.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include <vector>
22
23#define GET_INSTRINFO_HEADER
24#include "X86GenInstrInfo.inc"
25
26namespace llvm {
27class X86Subtarget;
28
29// X86 MachineCombiner patterns
30enum X86MachineCombinerPattern : unsigned {
31 // X86 VNNI
32 DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START,
33};
34
35namespace X86 {
36
37enum AsmComments : MachineInstr::AsmPrinterFlagTy {
38 // For instr that was compressed from EVEX to LEGACY.
39 AC_EVEX_2_LEGACY = MachineInstr::TAsmComments,
40 // For instr that was compressed from EVEX to VEX.
41 AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1,
42 // For instr that was compressed from EVEX to EVEX.
43 AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1
44};
45
46/// Return a pair of condition code for the given predicate and whether
47/// the instruction operands should be swaped to match the condition code.
48std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
49
50/// Return a cmov opcode for the given register size in bytes, and operand type.
51unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,
52 bool HasNDD = false);
53
54/// Return a MOVri opcode for materializing \p Imm into a 32- or 64-bit GPR.
55unsigned getMOVriOpcode(bool Use64BitReg, int64_t Imm);
56
57/// Return the source operand # for condition code by \p MCID. If the
58/// instruction doesn't have a condition code, return -1.
59int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
60
61/// Return the condition code of the instruction. If the instruction doesn't
62/// have a condition code, return X86::COND_INVALID.
63CondCode getCondFromMI(const MachineInstr &MI);
64
65// Turn JCC instruction into condition code.
66CondCode getCondFromBranch(const MachineInstr &MI);
67
68// Turn SETCC instruction into condition code.
69CondCode getCondFromSETCC(const MachineInstr &MI);
70
71// Turn CMOV instruction into condition code.
72CondCode getCondFromCMov(const MachineInstr &MI);
73
74// Turn CFCMOV instruction into condition code.
75CondCode getCondFromCFCMov(const MachineInstr &MI);
76
77// Turn CCMP instruction into condition code.
78CondCode getCondFromCCMP(const MachineInstr &MI);
79
80// Turn condition code into condition flags for CCMP/CTEST.
81int getCCMPCondFlagsFromCondCode(CondCode CC);
82
83// Get the opcode of corresponding NF variant.
84unsigned getNFVariant(unsigned Opc);
85
86// Get the opcode of corresponding NonND variant.
87unsigned getNonNDVariant(unsigned Opc);
88
89/// GetOppositeBranchCondition - Return the inverse of the specified cond,
90/// e.g. turning COND_E to COND_NE.
91CondCode GetOppositeBranchCondition(CondCode CC);
92
93/// Get the VPCMP immediate for the given condition.
94unsigned getVPCMPImmForCond(ISD::CondCode CC);
95
96/// Get the VPCMP immediate if the opcodes are swapped.
97unsigned getSwappedVPCMPImm(unsigned Imm);
98
99/// Get the VPCOM immediate if the opcodes are swapped.
100unsigned getSwappedVPCOMImm(unsigned Imm);
101
102/// Get the VCMP immediate if the opcodes are swapped.
103unsigned getSwappedVCMPImm(unsigned Imm);
104
105/// Get the width of the vector register operand.
106unsigned getVectorRegisterWidth(const MCOperandInfo &Info);
107
108/// Check if the instruction is X87 instruction.
109bool isX87Instruction(MachineInstr &MI);
110
111/// Return the index of the instruction's first address operand, if it has a
112/// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(),
113/// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as
114/// real instructions (e.g., JMP64m).
115int getFirstAddrOperandIdx(const MachineInstr &MI);
116
117/// Find any constant pool entry associated with a specific instruction operand.
118const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo);
119
120} // namespace X86
121
122/// isGlobalStubReference - Return true if the specified TargetFlag operand is
123/// a reference to a stub for a global, not the global itself.
124inline static bool isGlobalStubReference(unsigned char TargetFlag) {
125 switch (TargetFlag) {
126 case X86II::MO_DLLIMPORT: // dllimport stub.
127 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
128 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
129 case X86II::MO_GOT: // normal GOT reference.
130 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
131 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
132 case X86II::MO_COFFSTUB: // COFF .refptr stub.
133 return true;
134 default:
135 return false;
136 }
137}
138
139/// isGlobalRelativeToPICBase - Return true if the specified global value
140/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
141/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
142inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
143 switch (TargetFlag) {
144 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
145 case X86II::MO_GOT: // isPICStyleGOT: other global.
146 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
147 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
148 case X86II::MO_TLVP: // ??? Pretty sure..
149 return true;
150 default:
151 return false;
152 }
153}
154
155inline static bool isScale(const MachineOperand &MO) {
156 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
157 MO.getImm() == 4 || MO.getImm() == 8);
158}
159
160inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
161 if (MI.getOperand(i: Op).isFI())
162 return true;
163 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
164 MI.getOperand(i: Op + X86::AddrBaseReg).isReg() &&
165 isScale(MO: MI.getOperand(i: Op + X86::AddrScaleAmt)) &&
166 MI.getOperand(i: Op + X86::AddrIndexReg).isReg() &&
167 (MI.getOperand(i: Op + X86::AddrDisp).isImm() ||
168 MI.getOperand(i: Op + X86::AddrDisp).isGlobal() ||
169 MI.getOperand(i: Op + X86::AddrDisp).isCPI() ||
170 MI.getOperand(i: Op + X86::AddrDisp).isJTI());
171}
172
173inline static bool isMem(const MachineInstr &MI, unsigned Op) {
174 if (MI.getOperand(i: Op).isFI())
175 return true;
176 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
177 MI.getOperand(i: Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
178}
179
180inline static bool isAddMemInstrWithRelocation(const MachineInstr &MI) {
181 unsigned Op = MI.getOpcode();
182 if (Op == X86::ADD64rm || Op == X86::ADD64mr_ND || Op == X86::ADD64rm_ND) {
183 int MemOpNo = X86II::getMemoryOperandNo(TSFlags: MI.getDesc().TSFlags) +
184 X86II::getOperandBias(Desc: MI.getDesc());
185 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
186 if (MO.getTargetFlags() == X86II::MO_GOTTPOFF)
187 return true;
188 }
189
190 return false;
191}
192
193inline static bool isMemInstrWithGOTPCREL(const MachineInstr &MI) {
194 unsigned Op = MI.getOpcode();
195 switch (Op) {
196 case X86::TEST32mr:
197 case X86::TEST64mr:
198 case X86::CMP32rm:
199 case X86::CMP64rm:
200 case X86::MOV32rm:
201 case X86::MOV64rm:
202 case X86::ADC32rm:
203 case X86::ADD32rm:
204 case X86::AND32rm:
205 case X86::OR32rm:
206 case X86::SBB32rm:
207 case X86::SUB32rm:
208 case X86::XOR32rm:
209 case X86::ADC64rm:
210 case X86::ADD64rm:
211 case X86::AND64rm:
212 case X86::OR64rm:
213 case X86::SBB64rm:
214 case X86::SUB64rm:
215 case X86::XOR64rm: {
216 int MemOpNo = X86II::getMemoryOperandNo(TSFlags: MI.getDesc().TSFlags) +
217 X86II::getOperandBias(Desc: MI.getDesc());
218 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
219 if (MO.getTargetFlags() == X86II::MO_GOTPCREL)
220 return true;
221 break;
222 }
223 }
224 return false;
225}
226
227class X86InstrInfo final : public X86GenInstrInfo {
228 const X86Subtarget &Subtarget;
229 const X86RegisterInfo RI;
230
231 LLVM_DECLARE_VIRTUAL_ANCHOR_FUNCTION();
232
233 bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
234 MachineBasicBlock *&FBB,
235 SmallVectorImpl<MachineOperand> &Cond,
236 SmallVectorImpl<MachineInstr *> &CondBranches,
237 bool AllowModify) const;
238
239 bool foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg,
240 int64_t ImmVal, MachineRegisterInfo *MRI,
241 bool MakeChange) const;
242
243public:
244 explicit X86InstrInfo(const X86Subtarget &STI);
245
246 /// Given a machine instruction descriptor, returns the register
247 /// class constraint for OpNum, or NULL. Returned register class
248 /// may be different from the definition in the TD file, e.g.
249 /// GR*RegClass (definition in TD file)
250 /// ->
251 /// GR*_NOREX2RegClass (Returned register class)
252 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID,
253 unsigned OpNum) const override;
254
255 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
256 /// such, whenever a client has an instance of instruction info, it should
257 /// always be able to get register info as well (through this method).
258 ///
259 const X86RegisterInfo &getRegisterInfo() const { return RI; }
260
261 /// Returns the stack pointer adjustment that happens inside the frame
262 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
263 int64_t getFrameAdjustment(const MachineInstr &I) const {
264 assert(isFrameInstr(I));
265 if (isFrameSetup(I))
266 return I.getOperand(i: 2).getImm();
267 return I.getOperand(i: 1).getImm();
268 }
269
270 /// Sets the stack pointer adjustment made inside the frame made up by this
271 /// instruction.
272 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
273 assert(isFrameInstr(I));
274 if (isFrameSetup(I))
275 I.getOperand(i: 2).setImm(V);
276 else
277 I.getOperand(i: 1).setImm(V);
278 }
279
280 /// getSPAdjust - This returns the stack pointer adjustment made by
281 /// this instruction. For x86, we need to handle more complex call
282 /// sequences involving PUSHes.
283 int getSPAdjust(const MachineInstr &MI) const override;
284
285 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
286 /// extension instruction. That is, it's like a copy where it's legal for the
287 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
288 /// true, then it's expected the pre-extension value is available as a subreg
289 /// of the result register. This also returns the sub-register index in
290 /// SubIdx.
291 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
292 Register &DstReg, unsigned &SubIdx) const override;
293
294 /// Returns true if the instruction has no behavior (specified or otherwise)
295 /// that is based on the value of any of its register operands
296 ///
297 /// Instructions are considered data invariant even if they set EFLAGS.
298 ///
299 /// A classical example of something that is inherently not data invariant is
300 /// an indirect jump -- the destination is loaded into icache based on the
301 /// bits set in the jump destination register.
302 ///
303 /// FIXME: This should become part of our instruction tables.
304 static bool isDataInvariant(MachineInstr &MI);
305
306 /// Returns true if the instruction has no behavior (specified or otherwise)
307 /// that is based on the value loaded from memory or the value of any
308 /// non-address register operands.
309 ///
310 /// For example, if the latency of the instruction is dependent on the
311 /// particular bits set in any of the registers *or* any of the bits loaded
312 /// from memory.
313 ///
314 /// Instructions are considered data invariant even if they set EFLAGS.
315 ///
316 /// A classical example of something that is inherently not data invariant is
317 /// an indirect jump -- the destination is loaded into icache based on the
318 /// bits set in the jump destination register.
319 ///
320 /// FIXME: This should become part of our instruction tables.
321 static bool isDataInvariantLoad(MachineInstr &MI);
322
323 Register isLoadFromStackSlot(const MachineInstr &MI,
324 int &FrameIndex) const override;
325 Register isLoadFromStackSlot(const MachineInstr &MI,
326 int &FrameIndex,
327 TypeSize &MemBytes) const override;
328 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
329 /// stack locations as well. This uses a heuristic so it isn't
330 /// reliable for correctness.
331 Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
332 int &FrameIndex) const override;
333
334 Register isStoreToStackSlot(const MachineInstr &MI,
335 int &FrameIndex) const override;
336 Register isStoreToStackSlot(const MachineInstr &MI,
337 int &FrameIndex,
338 TypeSize &MemBytes) const override;
339 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
340 /// stack locations as well. This uses a heuristic so it isn't
341 /// reliable for correctness.
342 Register isStoreToStackSlotPostFE(const MachineInstr &MI,
343 int &FrameIndex) const override;
344
345 bool isReMaterializableImpl(const MachineInstr &MI) const override;
346 void
347 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
348 Register DestReg, unsigned SubIdx, const MachineInstr &Orig,
349 LaneBitmask UsedLanes = LaneBitmask::getAll()) const override;
350
351 /// Given an operand within a MachineInstr, insert preceding code to put it
352 /// into the right format for a particular kind of LEA instruction. This may
353 /// involve using an appropriate super-register instead (with an implicit use
354 /// of the original) or creating a new virtual register and inserting COPY
355 /// instructions to get the data into the right class.
356 ///
357 /// Reference parameters are set to indicate how caller should add this
358 /// operand to the LEA instruction.
359 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
360 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
361 unsigned &NewSrcSubReg, bool &isKill,
362 MachineOperand &ImplicitOp, LiveVariables *LV,
363 LiveIntervals *LIS) const;
364
365 /// convertToThreeAddress - This method must be implemented by targets that
366 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
367 /// may be able to convert a two-address instruction into a true
368 /// three-address instruction on demand. This allows the X86 target (for
369 /// example) to convert ADD and SHL instructions into LEA instructions if they
370 /// would require register copies due to two-addressness.
371 ///
372 /// This method returns a null pointer if the transformation cannot be
373 /// performed, otherwise it returns the new instruction.
374 ///
375 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
376 LiveIntervals *LIS) const override;
377
378 /// Returns true iff the routine could find two commutable operands in the
379 /// given machine instruction.
380 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
381 /// input values can be re-defined in this method only if the input values
382 /// are not pre-defined, which is designated by the special value
383 /// 'CommuteAnyOperandIndex' assigned to it.
384 /// If both of indices are pre-defined and refer to some operands, then the
385 /// method simply returns true if the corresponding operands are commutable
386 /// and returns false otherwise.
387 ///
388 /// For example, calling this method this way:
389 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
390 /// findCommutedOpIndices(MI, Op1, Op2);
391 /// can be interpreted as a query asking to find an operand that would be
392 /// commutable with the operand#1.
393 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
394 unsigned &SrcOpIdx2) const override;
395
396 /// Returns true if we have preference on the operands order in MI, the
397 /// commute decision is returned in Commute.
398 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
399
400 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
401 /// performs the same computations as the given \p MI but which has the
402 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
403 /// It may return 0 if it is unsafe to commute the operands.
404 /// Note that a machine instruction (instead of its opcode) is passed as the
405 /// first parameter to make it possible to analyze the instruction's uses and
406 /// commute the first operand of FMA even when it seems unsafe when you look
407 /// at the opcode. For example, it is Ok to commute the first operand of
408 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
409 ///
410 /// The returned FMA opcode may differ from the opcode in the given \p MI.
411 /// For example, commuting the operands #1 and #3 in the following FMA
412 /// FMA213 #1, #2, #3
413 /// results into instruction with adjusted opcode:
414 /// FMA231 #3, #2, #1
415 unsigned
416 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
417 unsigned SrcOpIdx2,
418 const X86InstrFMA3Group &FMA3Group) const;
419
420 // Branch analysis.
421 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
422 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
423 const MachineInstr &TailCall) const override;
424 void replaceBranchWithTailCall(MachineBasicBlock &MBB,
425 SmallVectorImpl<MachineOperand> &Cond,
426 const MachineInstr &TailCall) const override;
427
428 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
429 MachineBasicBlock *&FBB,
430 SmallVectorImpl<MachineOperand> &Cond,
431 bool AllowModify) const override;
432
433 int getJumpTableIndex(const MachineInstr &MI) const override;
434
435 std::optional<ExtAddrMode>
436 getAddrModeFromMemoryOp(const MachineInstr &MemI,
437 const TargetRegisterInfo *TRI) const override;
438
439 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
440 int64_t &ImmVal) const override;
441
442 bool preservesZeroValueInReg(const MachineInstr *MI,
443 const Register NullValueReg,
444 const TargetRegisterInfo *TRI) const override;
445
446 bool getMemOperandsWithOffsetWidth(
447 const MachineInstr &LdSt,
448 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
449 bool &OffsetIsScalable, LocationSize &Width,
450 const TargetRegisterInfo *TRI) const override;
451 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
452 TargetInstrInfo::MachineBranchPredicate &MBP,
453 bool AllowModify = false) const override;
454
455 unsigned removeBranch(MachineBasicBlock &MBB,
456 int *BytesRemoved = nullptr) const override;
457 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
458 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
459 const DebugLoc &DL,
460 int *BytesAdded = nullptr) const override;
461 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
462 Register, Register, Register, int &, int &,
463 int &) const override;
464 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
465 const DebugLoc &DL, Register DstReg,
466 ArrayRef<MachineOperand> Cond, Register TrueReg,
467 Register FalseReg) const override;
468 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
469 const DebugLoc &DL, Register DestReg, Register SrcReg,
470 bool KillSrc, bool RenamableDest = false,
471 bool RenamableSrc = false) const override;
472 void storeRegToStackSlot(
473 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
474 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
475 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
476
477 void loadRegFromStackSlot(
478 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
479 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
480 unsigned SubReg = 0,
481 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
482
483 void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
484 unsigned Opc, Register Reg, int FrameIdx,
485 bool isKill = false) const;
486
487 bool expandPostRAPseudo(MachineInstr &MI) const override;
488
489 /// Check whether the target can fold a load that feeds a subreg operand
490 /// (or a subreg operand that feeds a store).
491 bool isSubregFoldable() const override { return true; }
492
493 /// Fold a load or store of the specified stack slot into the specified
494 /// machine instruction for the specified operand(s). If folding happens, it
495 /// is likely that the referenced instruction has been changed.
496 ///
497 /// \returns true on success.
498 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
499 ArrayRef<unsigned> Ops, int FrameIndex,
500 MachineInstr *&CopyMI,
501 LiveIntervals *LIS = nullptr,
502 VirtRegMap *VRM = nullptr) const override;
503
504 /// Same as the previous version except it allows folding of any load and
505 /// store from / to any address, not just from a specific stack slot.
506 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
507 ArrayRef<unsigned> Ops,
508 MachineInstr &LoadMI,
509 MachineInstr *&CopyMI,
510 LiveIntervals *LIS = nullptr,
511 VirtRegMap *VRM = nullptr) const override;
512
513 bool
514 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, Register Reg,
515 bool UnfoldLoad, bool UnfoldStore,
516 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
517
518 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
519 SmallVectorImpl<SDNode *> &NewNodes) const override;
520
521 unsigned
522 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
523 unsigned *LoadRegIndex = nullptr) const override;
524
525 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
526 int64_t &Offset2) const override;
527
528 /// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to
529 /// make it capable of identifying ENDBR intructions and prevent it from being
530 /// re-scheduled.
531 bool isSchedulingBoundary(const MachineInstr &MI,
532 const MachineBasicBlock *MBB,
533 const MachineFunction &MF) const override;
534
535 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
536 /// with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On
537 /// some targets if two loads are loading from addresses in the same cache
538 /// line, it's better if they are scheduled together. This function takes two
539 /// integers that represent the load offsets from the common base address. It
540 /// returns true if it decides it's desirable to schedule the two loads
541 /// together. "NumLoads" is the number of loads that have already been
542 /// scheduled after Load1.
543 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
544 int64_t Offset2,
545 unsigned NumLoads) const override;
546
547 void insertNoop(MachineBasicBlock &MBB,
548 MachineBasicBlock::iterator MI) const override;
549
550 MCInst getNop() const override;
551
552 bool
553 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
554
555 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
556
557 /// True if MI has a condition code def, e.g. EFLAGS, that is
558 /// not marked dead.
559 bool hasLiveCondCodeDef(MachineInstr &MI) const;
560
561 /// getGlobalBaseReg - Return a virtual register initialized with the
562 /// the global base register value. Output instructions required to
563 /// initialize the register in the function entry block, if necessary.
564 ///
565 Register getGlobalBaseReg(MachineFunction *MF) const;
566
567 std::pair<uint16_t, uint16_t>
568 getExecutionDomain(const MachineInstr &MI) const override;
569
570 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
571
572 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
573
574 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
575
576 unsigned
577 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
578 const TargetRegisterInfo *TRI) const override;
579 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
580 const TargetRegisterInfo *TRI) const override;
581 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
582 const TargetRegisterInfo *TRI) const override;
583
584 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
585 unsigned OpNum,
586 ArrayRef<MachineOperand> MOs,
587 MachineBasicBlock::iterator InsertPt,
588 unsigned Size, Align Alignment,
589 bool AllowCommute, MachineInstr *&CopyMI,
590 VirtRegMap *VRM = nullptr) const;
591
592 bool isHighLatencyDef(int opc) const override;
593
594 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
595 const MachineRegisterInfo *MRI,
596 const MachineInstr &DefMI, unsigned DefIdx,
597 const MachineInstr &UseMI,
598 unsigned UseIdx) const override;
599
600 bool useMachineCombiner() const override { return true; }
601
602 bool isAssociativeAndCommutative(const MachineInstr &Inst,
603 bool Invert) const override;
604
605 bool hasReassociableOperands(const MachineInstr &Inst,
606 const MachineBasicBlock *MBB) const override;
607
608 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
609 MachineInstr &NewMI1,
610 MachineInstr &NewMI2) const override;
611
612 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
613 Register &SrcReg2, int64_t &CmpMask,
614 int64_t &CmpValue) const override;
615
616 /// Check if there exists an earlier instruction that operates on the same
617 /// source operands and sets eflags in the same way as CMP and remove CMP if
618 /// possible.
619 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
620 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
621 const MachineRegisterInfo *MRI) const override;
622
623 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
624 MachineRegisterInfo *MRI) const override;
625
626 std::pair<unsigned, unsigned>
627 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
628
629 ArrayRef<std::pair<unsigned, const char *>>
630 getSerializableDirectMachineOperandTargetFlags() const override;
631
632 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
633 getOutliningCandidateInfo(
634 const MachineModuleInfo &MMI,
635 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
636 unsigned MinRepeats) const override;
637
638 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
639 bool OutlineFromLinkOnceODRs) const override;
640
641 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
642 MachineBasicBlock::iterator &MIT,
643 unsigned Flags) const override;
644
645 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
646 const outliner::OutlinedFunction &OF) const override;
647
648 MachineBasicBlock::iterator
649 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
650 MachineBasicBlock::iterator &It, MachineFunction &MF,
651 outliner::Candidate &C) const override;
652
653 void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
654 MachineBasicBlock::iterator Iter, DebugLoc &DL,
655 bool AllowSideEffects = true) const override;
656
657 bool verifyInstruction(const MachineInstr &MI,
658 StringRef &ErrInfo) const override;
659#define GET_INSTRINFO_HELPER_DECLS
660#include "X86GenInstrInfo.inc"
661
662 static bool hasLockPrefix(const MachineInstr &MI) {
663 return MI.getDesc().TSFlags & X86II::LOCK;
664 }
665
666 std::optional<ParamLoadedValue>
667 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
668
669protected:
670 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
671 unsigned CommuteOpIdx1,
672 unsigned CommuteOpIdx2) const override;
673
674 std::optional<DestSourcePair>
675 isCopyInstrImpl(const MachineInstr &MI) const override;
676
677 bool getMachineCombinerPatterns(MachineInstr &Root,
678 SmallVectorImpl<unsigned> &Patterns,
679 bool DoRegPressureReduce) const override;
680
681 /// When getMachineCombinerPatterns() finds potential patterns,
682 /// this function generates the instructions that could replace the
683 /// original code sequence.
684 void genAlternativeCodeSequence(
685 MachineInstr &Root, unsigned Pattern,
686 SmallVectorImpl<MachineInstr *> &InsInstrs,
687 SmallVectorImpl<MachineInstr *> &DelInstrs,
688 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
689
690 /// When calculate the latency of the root instruction, accumulate the
691 /// latency of the sequence to the root latency.
692 /// \param Root - Instruction that could be combined with one of its operands
693 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd
694 /// is not in the critical path, so the root latency only include vpmaddwd.
695 bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override {
696 return false;
697 }
698
699 void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
700 int FI) const override;
701
702private:
703 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
704 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
705 /// super-register and then truncating back down to a 8/16-bit sub-register.
706 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
707 LiveVariables *LV,
708 LiveIntervals *LIS,
709 bool Is8BitOp) const;
710
711 /// Handles memory folding for special case instructions, for instance those
712 /// requiring custom manipulation of the address.
713 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
714 unsigned OpNum,
715 ArrayRef<MachineOperand> MOs,
716 MachineBasicBlock::iterator InsertPt,
717 unsigned Size, Align Alignment) const;
718
719 MachineInstr *foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
720 unsigned OpNum,
721 ArrayRef<MachineOperand> MOs,
722 MachineBasicBlock::iterator InsertPt,
723 unsigned BitsSize, bool AllowCommute) const;
724
725 /// isFrameOperand - Return true and the FrameIndex if the specified
726 /// operand and follow operands form a reference to the stack frame.
727 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
728 int &FrameIndex) const;
729
730 /// Returns true iff the routine could find two commutable operands in the
731 /// given machine instruction with 3 vector inputs.
732 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
733 /// input values can be re-defined in this method only if the input values
734 /// are not pre-defined, which is designated by the special value
735 /// 'CommuteAnyOperandIndex' assigned to it.
736 /// If both of indices are pre-defined and refer to some operands, then the
737 /// method simply returns true if the corresponding operands are commutable
738 /// and returns false otherwise.
739 ///
740 /// For example, calling this method this way:
741 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
742 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
743 /// can be interpreted as a query asking to find an operand that would be
744 /// commutable with the operand#1.
745 ///
746 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
747 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
748 unsigned &SrcOpIdx1,
749 unsigned &SrcOpIdx2,
750 bool IsIntrinsic = false) const;
751
752 /// Returns true when instruction \p FlagI produces the same flags as \p OI.
753 /// The caller should pass in the results of calling analyzeCompare on \p OI:
754 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
755 /// If the flags match \p OI as if it had the input operands swapped then the
756 /// function succeeds and sets \p IsSwapped to true.
757 ///
758 /// Examples of OI, FlagI pairs returning true:
759 /// CMP %1, 42 and CMP %1, 42
760 /// CMP %1, %2 and %3 = SUB %1, %2
761 /// TEST %1, %1 and %2 = SUB %1, 0
762 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
763 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
764 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
765 const MachineInstr &OI, bool *IsSwapped,
766 int64_t *ImmDelta) const;
767
768 /// Commute operands of \p MI for memory fold.
769 ///
770 /// \param Idx1 the index of operand to be commuted.
771 ///
772 /// \returns the index of operand that is commuted with \p Idx1. If the method
773 /// fails to commute the operands, it will return \p Idx1.
774 unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const;
775
776 MachineInstr *
777 insertCodePrefetchInstr(MachineBasicBlock &MBB,
778 MachineBasicBlock::iterator InsertBefore,
779 const GlobalValue *GV) const override;
780};
781} // namespace llvm
782
783#endif
784