1//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15
16#include "MCTargetDesc/X86BaseInfo.h"
17#include "X86InstrFMA3Info.h"
18#include "X86RegisterInfo.h"
19#include "llvm/CodeGen/ISDOpcodes.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include <vector>
22
23#define GET_INSTRINFO_HEADER
24#include "X86GenInstrInfo.inc"
25
26namespace llvm {
27class X86Subtarget;
28
29// X86 MachineCombiner patterns
30enum X86MachineCombinerPattern : unsigned {
31 // X86 VNNI
32 DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START,
33};
34
35namespace X86 {
36
37enum AsmComments {
38 // For instr that was compressed from EVEX to LEGACY.
39 AC_EVEX_2_LEGACY = MachineInstr::TAsmComments,
40 // For instr that was compressed from EVEX to VEX.
41 AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1,
42 // For instr that was compressed from EVEX to EVEX.
43 AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1
44};
45
46/// Return a pair of condition code for the given predicate and whether
47/// the instruction operands should be swaped to match the condition code.
48std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
49
50/// Return a cmov opcode for the given register size in bytes, and operand type.
51unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,
52 bool HasNDD = false);
53
54/// Return the source operand # for condition code by \p MCID. If the
55/// instruction doesn't have a condition code, return -1.
56int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
57
58/// Return the condition code of the instruction. If the instruction doesn't
59/// have a condition code, return X86::COND_INVALID.
60CondCode getCondFromMI(const MachineInstr &MI);
61
62// Turn JCC instruction into condition code.
63CondCode getCondFromBranch(const MachineInstr &MI);
64
65// Turn SETCC instruction into condition code.
66CondCode getCondFromSETCC(const MachineInstr &MI);
67
68// Turn CMOV instruction into condition code.
69CondCode getCondFromCMov(const MachineInstr &MI);
70
71// Turn CFCMOV instruction into condition code.
72CondCode getCondFromCFCMov(const MachineInstr &MI);
73
74// Turn CCMP instruction into condition code.
75CondCode getCondFromCCMP(const MachineInstr &MI);
76
77// Turn condition code into condition flags for CCMP/CTEST.
78int getCCMPCondFlagsFromCondCode(CondCode CC);
79
80// Get the opcode of corresponding NF variant.
81unsigned getNFVariant(unsigned Opc);
82
83// Get the opcode of corresponding NonND variant.
84unsigned getNonNDVariant(unsigned Opc);
85
86/// GetOppositeBranchCondition - Return the inverse of the specified cond,
87/// e.g. turning COND_E to COND_NE.
88CondCode GetOppositeBranchCondition(CondCode CC);
89
90/// Get the VPCMP immediate for the given condition.
91unsigned getVPCMPImmForCond(ISD::CondCode CC);
92
93/// Get the VPCMP immediate if the opcodes are swapped.
94unsigned getSwappedVPCMPImm(unsigned Imm);
95
96/// Get the VPCOM immediate if the opcodes are swapped.
97unsigned getSwappedVPCOMImm(unsigned Imm);
98
99/// Get the VCMP immediate if the opcodes are swapped.
100unsigned getSwappedVCMPImm(unsigned Imm);
101
102/// Get the width of the vector register operand.
103unsigned getVectorRegisterWidth(const MCOperandInfo &Info);
104
105/// Check if the instruction is X87 instruction.
106bool isX87Instruction(MachineInstr &MI);
107
108/// Return the index of the instruction's first address operand, if it has a
109/// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(),
110/// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as
111/// real instructions (e.g., JMP64m).
112int getFirstAddrOperandIdx(const MachineInstr &MI);
113
114/// Find any constant pool entry associated with a specific instruction operand.
115const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo);
116
117} // namespace X86
118
119/// isGlobalStubReference - Return true if the specified TargetFlag operand is
120/// a reference to a stub for a global, not the global itself.
121inline static bool isGlobalStubReference(unsigned char TargetFlag) {
122 switch (TargetFlag) {
123 case X86II::MO_DLLIMPORT: // dllimport stub.
124 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
125 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
126 case X86II::MO_GOT: // normal GOT reference.
127 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
128 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
129 case X86II::MO_COFFSTUB: // COFF .refptr stub.
130 return true;
131 default:
132 return false;
133 }
134}
135
136/// isGlobalRelativeToPICBase - Return true if the specified global value
137/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
138/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
139inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
140 switch (TargetFlag) {
141 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
142 case X86II::MO_GOT: // isPICStyleGOT: other global.
143 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
144 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
145 case X86II::MO_TLVP: // ??? Pretty sure..
146 return true;
147 default:
148 return false;
149 }
150}
151
152inline static bool isScale(const MachineOperand &MO) {
153 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
154 MO.getImm() == 4 || MO.getImm() == 8);
155}
156
157inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
158 if (MI.getOperand(i: Op).isFI())
159 return true;
160 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
161 MI.getOperand(i: Op + X86::AddrBaseReg).isReg() &&
162 isScale(MO: MI.getOperand(i: Op + X86::AddrScaleAmt)) &&
163 MI.getOperand(i: Op + X86::AddrIndexReg).isReg() &&
164 (MI.getOperand(i: Op + X86::AddrDisp).isImm() ||
165 MI.getOperand(i: Op + X86::AddrDisp).isGlobal() ||
166 MI.getOperand(i: Op + X86::AddrDisp).isCPI() ||
167 MI.getOperand(i: Op + X86::AddrDisp).isJTI());
168}
169
170inline static bool isMem(const MachineInstr &MI, unsigned Op) {
171 if (MI.getOperand(i: Op).isFI())
172 return true;
173 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
174 MI.getOperand(i: Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
175}
176
177inline static bool isAddMemInstrWithRelocation(const MachineInstr &MI) {
178 unsigned Op = MI.getOpcode();
179 if (Op == X86::ADD64rm || Op == X86::ADD64mr_ND || Op == X86::ADD64rm_ND) {
180 int MemOpNo = X86II::getMemoryOperandNo(TSFlags: MI.getDesc().TSFlags) +
181 X86II::getOperandBias(Desc: MI.getDesc());
182 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
183 if (MO.getTargetFlags() == X86II::MO_GOTTPOFF)
184 return true;
185 }
186
187 return false;
188}
189
190inline static bool isMemInstrWithGOTPCREL(const MachineInstr &MI) {
191 unsigned Op = MI.getOpcode();
192 switch (Op) {
193 case X86::TEST32mr:
194 case X86::TEST64mr:
195 case X86::CMP32rm:
196 case X86::CMP64rm:
197 case X86::MOV32rm:
198 case X86::MOV64rm:
199 case X86::ADC32rm:
200 case X86::ADD32rm:
201 case X86::AND32rm:
202 case X86::OR32rm:
203 case X86::SBB32rm:
204 case X86::SUB32rm:
205 case X86::XOR32rm:
206 case X86::ADC64rm:
207 case X86::ADD64rm:
208 case X86::AND64rm:
209 case X86::OR64rm:
210 case X86::SBB64rm:
211 case X86::SUB64rm:
212 case X86::XOR64rm: {
213 int MemOpNo = X86II::getMemoryOperandNo(TSFlags: MI.getDesc().TSFlags) +
214 X86II::getOperandBias(Desc: MI.getDesc());
215 const MachineOperand &MO = MI.getOperand(i: X86::AddrDisp + MemOpNo);
216 if (MO.getTargetFlags() == X86II::MO_GOTPCREL)
217 return true;
218 break;
219 }
220 }
221 return false;
222}
223
224class X86InstrInfo final : public X86GenInstrInfo {
225 const X86Subtarget &Subtarget;
226 const X86RegisterInfo RI;
227
228 LLVM_DECLARE_VIRTUAL_ANCHOR_FUNCTION();
229
230 bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
231 MachineBasicBlock *&FBB,
232 SmallVectorImpl<MachineOperand> &Cond,
233 SmallVectorImpl<MachineInstr *> &CondBranches,
234 bool AllowModify) const;
235
236 bool foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg,
237 int64_t ImmVal, MachineRegisterInfo *MRI,
238 bool MakeChange) const;
239
240public:
241 explicit X86InstrInfo(const X86Subtarget &STI);
242
243 /// Given a machine instruction descriptor, returns the register
244 /// class constraint for OpNum, or NULL. Returned register class
245 /// may be different from the definition in the TD file, e.g.
246 /// GR*RegClass (definition in TD file)
247 /// ->
248 /// GR*_NOREX2RegClass (Returned register class)
249 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID,
250 unsigned OpNum) const override;
251
252 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
253 /// such, whenever a client has an instance of instruction info, it should
254 /// always be able to get register info as well (through this method).
255 ///
256 const X86RegisterInfo &getRegisterInfo() const { return RI; }
257
258 /// Returns the stack pointer adjustment that happens inside the frame
259 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
260 int64_t getFrameAdjustment(const MachineInstr &I) const {
261 assert(isFrameInstr(I));
262 if (isFrameSetup(I))
263 return I.getOperand(i: 2).getImm();
264 return I.getOperand(i: 1).getImm();
265 }
266
267 /// Sets the stack pointer adjustment made inside the frame made up by this
268 /// instruction.
269 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
270 assert(isFrameInstr(I));
271 if (isFrameSetup(I))
272 I.getOperand(i: 2).setImm(V);
273 else
274 I.getOperand(i: 1).setImm(V);
275 }
276
277 /// getSPAdjust - This returns the stack pointer adjustment made by
278 /// this instruction. For x86, we need to handle more complex call
279 /// sequences involving PUSHes.
280 int getSPAdjust(const MachineInstr &MI) const override;
281
282 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
283 /// extension instruction. That is, it's like a copy where it's legal for the
284 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
285 /// true, then it's expected the pre-extension value is available as a subreg
286 /// of the result register. This also returns the sub-register index in
287 /// SubIdx.
288 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
289 Register &DstReg, unsigned &SubIdx) const override;
290
291 /// Returns true if the instruction has no behavior (specified or otherwise)
292 /// that is based on the value of any of its register operands
293 ///
294 /// Instructions are considered data invariant even if they set EFLAGS.
295 ///
296 /// A classical example of something that is inherently not data invariant is
297 /// an indirect jump -- the destination is loaded into icache based on the
298 /// bits set in the jump destination register.
299 ///
300 /// FIXME: This should become part of our instruction tables.
301 static bool isDataInvariant(MachineInstr &MI);
302
303 /// Returns true if the instruction has no behavior (specified or otherwise)
304 /// that is based on the value loaded from memory or the value of any
305 /// non-address register operands.
306 ///
307 /// For example, if the latency of the instruction is dependent on the
308 /// particular bits set in any of the registers *or* any of the bits loaded
309 /// from memory.
310 ///
311 /// Instructions are considered data invariant even if they set EFLAGS.
312 ///
313 /// A classical example of something that is inherently not data invariant is
314 /// an indirect jump -- the destination is loaded into icache based on the
315 /// bits set in the jump destination register.
316 ///
317 /// FIXME: This should become part of our instruction tables.
318 static bool isDataInvariantLoad(MachineInstr &MI);
319
320 Register isLoadFromStackSlot(const MachineInstr &MI,
321 int &FrameIndex) const override;
322 Register isLoadFromStackSlot(const MachineInstr &MI,
323 int &FrameIndex,
324 TypeSize &MemBytes) const override;
325 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
326 /// stack locations as well. This uses a heuristic so it isn't
327 /// reliable for correctness.
328 Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
329 int &FrameIndex) const override;
330
331 Register isStoreToStackSlot(const MachineInstr &MI,
332 int &FrameIndex) const override;
333 Register isStoreToStackSlot(const MachineInstr &MI,
334 int &FrameIndex,
335 TypeSize &MemBytes) const override;
336 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
337 /// stack locations as well. This uses a heuristic so it isn't
338 /// reliable for correctness.
339 Register isStoreToStackSlotPostFE(const MachineInstr &MI,
340 int &FrameIndex) const override;
341
342 bool isReMaterializableImpl(const MachineInstr &MI) const override;
343 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
344 Register DestReg, unsigned SubIdx,
345 const MachineInstr &Orig) const override;
346
347 /// Given an operand within a MachineInstr, insert preceding code to put it
348 /// into the right format for a particular kind of LEA instruction. This may
349 /// involve using an appropriate super-register instead (with an implicit use
350 /// of the original) or creating a new virtual register and inserting COPY
351 /// instructions to get the data into the right class.
352 ///
353 /// Reference parameters are set to indicate how caller should add this
354 /// operand to the LEA instruction.
355 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
356 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
357 unsigned &NewSrcSubReg, bool &isKill,
358 MachineOperand &ImplicitOp, LiveVariables *LV,
359 LiveIntervals *LIS) const;
360
361 /// convertToThreeAddress - This method must be implemented by targets that
362 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
363 /// may be able to convert a two-address instruction into a true
364 /// three-address instruction on demand. This allows the X86 target (for
365 /// example) to convert ADD and SHL instructions into LEA instructions if they
366 /// would require register copies due to two-addressness.
367 ///
368 /// This method returns a null pointer if the transformation cannot be
369 /// performed, otherwise it returns the new instruction.
370 ///
371 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
372 LiveIntervals *LIS) const override;
373
374 /// Returns true iff the routine could find two commutable operands in the
375 /// given machine instruction.
376 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
377 /// input values can be re-defined in this method only if the input values
378 /// are not pre-defined, which is designated by the special value
379 /// 'CommuteAnyOperandIndex' assigned to it.
380 /// If both of indices are pre-defined and refer to some operands, then the
381 /// method simply returns true if the corresponding operands are commutable
382 /// and returns false otherwise.
383 ///
384 /// For example, calling this method this way:
385 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
386 /// findCommutedOpIndices(MI, Op1, Op2);
387 /// can be interpreted as a query asking to find an operand that would be
388 /// commutable with the operand#1.
389 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
390 unsigned &SrcOpIdx2) const override;
391
392 /// Returns true if we have preference on the operands order in MI, the
393 /// commute decision is returned in Commute.
394 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
395
396 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
397 /// performs the same computations as the given \p MI but which has the
398 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
399 /// It may return 0 if it is unsafe to commute the operands.
400 /// Note that a machine instruction (instead of its opcode) is passed as the
401 /// first parameter to make it possible to analyze the instruction's uses and
402 /// commute the first operand of FMA even when it seems unsafe when you look
403 /// at the opcode. For example, it is Ok to commute the first operand of
404 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
405 ///
406 /// The returned FMA opcode may differ from the opcode in the given \p MI.
407 /// For example, commuting the operands #1 and #3 in the following FMA
408 /// FMA213 #1, #2, #3
409 /// results into instruction with adjusted opcode:
410 /// FMA231 #3, #2, #1
411 unsigned
412 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
413 unsigned SrcOpIdx2,
414 const X86InstrFMA3Group &FMA3Group) const;
415
416 // Branch analysis.
417 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
418 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
419 const MachineInstr &TailCall) const override;
420 void replaceBranchWithTailCall(MachineBasicBlock &MBB,
421 SmallVectorImpl<MachineOperand> &Cond,
422 const MachineInstr &TailCall) const override;
423
424 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
425 MachineBasicBlock *&FBB,
426 SmallVectorImpl<MachineOperand> &Cond,
427 bool AllowModify) const override;
428
429 int getJumpTableIndex(const MachineInstr &MI) const override;
430
431 std::optional<ExtAddrMode>
432 getAddrModeFromMemoryOp(const MachineInstr &MemI,
433 const TargetRegisterInfo *TRI) const override;
434
435 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
436 int64_t &ImmVal) const override;
437
438 bool preservesZeroValueInReg(const MachineInstr *MI,
439 const Register NullValueReg,
440 const TargetRegisterInfo *TRI) const override;
441
442 bool getMemOperandsWithOffsetWidth(
443 const MachineInstr &LdSt,
444 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
445 bool &OffsetIsScalable, LocationSize &Width,
446 const TargetRegisterInfo *TRI) const override;
447 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
448 TargetInstrInfo::MachineBranchPredicate &MBP,
449 bool AllowModify = false) const override;
450
451 unsigned removeBranch(MachineBasicBlock &MBB,
452 int *BytesRemoved = nullptr) const override;
453 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
454 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
455 const DebugLoc &DL,
456 int *BytesAdded = nullptr) const override;
457 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
458 Register, Register, Register, int &, int &,
459 int &) const override;
460 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
461 const DebugLoc &DL, Register DstReg,
462 ArrayRef<MachineOperand> Cond, Register TrueReg,
463 Register FalseReg) const override;
464 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
465 const DebugLoc &DL, Register DestReg, Register SrcReg,
466 bool KillSrc, bool RenamableDest = false,
467 bool RenamableSrc = false) const override;
468 void storeRegToStackSlot(
469 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
470 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
471 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
472
473 void loadRegFromStackSlot(
474 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
475 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
476 unsigned SubReg = 0,
477 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
478
479 void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
480 unsigned Opc, Register Reg, int FrameIdx,
481 bool isKill = false) const;
482
483 bool expandPostRAPseudo(MachineInstr &MI) const override;
484
485 /// Check whether the target can fold a load that feeds a subreg operand
486 /// (or a subreg operand that feeds a store).
487 bool isSubregFoldable() const override { return true; }
488
489 /// Fold a load or store of the specified stack slot into the specified
490 /// machine instruction for the specified operand(s). If folding happens, it
491 /// is likely that the referenced instruction has been changed.
492 ///
493 /// \returns true on success.
494 MachineInstr *
495 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
496 ArrayRef<unsigned> Ops,
497 MachineBasicBlock::iterator InsertPt, int FrameIndex,
498 LiveIntervals *LIS = nullptr,
499 VirtRegMap *VRM = nullptr) const override;
500
501 /// Same as the previous version except it allows folding of any load and
502 /// store from / to any address, not just from a specific stack slot.
503 MachineInstr *foldMemoryOperandImpl(
504 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
505 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
506 LiveIntervals *LIS = nullptr) const override;
507
508 bool
509 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, Register Reg,
510 bool UnfoldLoad, bool UnfoldStore,
511 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
512
513 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
514 SmallVectorImpl<SDNode *> &NewNodes) const override;
515
516 unsigned
517 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
518 unsigned *LoadRegIndex = nullptr) const override;
519
520 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
521 int64_t &Offset2) const override;
522
523 /// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to
524 /// make it capable of identifying ENDBR intructions and prevent it from being
525 /// re-scheduled.
526 bool isSchedulingBoundary(const MachineInstr &MI,
527 const MachineBasicBlock *MBB,
528 const MachineFunction &MF) const override;
529
530 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
531 /// with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On
532 /// some targets if two loads are loading from addresses in the same cache
533 /// line, it's better if they are scheduled together. This function takes two
534 /// integers that represent the load offsets from the common base address. It
535 /// returns true if it decides it's desirable to schedule the two loads
536 /// together. "NumLoads" is the number of loads that have already been
537 /// scheduled after Load1.
538 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
539 int64_t Offset2,
540 unsigned NumLoads) const override;
541
542 void insertNoop(MachineBasicBlock &MBB,
543 MachineBasicBlock::iterator MI) const override;
544
545 MCInst getNop() const override;
546
547 bool
548 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
549
550 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
551
552 /// True if MI has a condition code def, e.g. EFLAGS, that is
553 /// not marked dead.
554 bool hasLiveCondCodeDef(MachineInstr &MI) const;
555
556 /// getGlobalBaseReg - Return a virtual register initialized with the
557 /// the global base register value. Output instructions required to
558 /// initialize the register in the function entry block, if necessary.
559 ///
560 Register getGlobalBaseReg(MachineFunction *MF) const;
561
562 std::pair<uint16_t, uint16_t>
563 getExecutionDomain(const MachineInstr &MI) const override;
564
565 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
566
567 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
568
569 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
570
571 unsigned
572 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
573 const TargetRegisterInfo *TRI) const override;
574 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
575 const TargetRegisterInfo *TRI) const override;
576 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
577 const TargetRegisterInfo *TRI) const override;
578
579 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
580 unsigned OpNum,
581 ArrayRef<MachineOperand> MOs,
582 MachineBasicBlock::iterator InsertPt,
583 unsigned Size, Align Alignment,
584 bool AllowCommute) const;
585
586 bool isHighLatencyDef(int opc) const override;
587
588 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
589 const MachineRegisterInfo *MRI,
590 const MachineInstr &DefMI, unsigned DefIdx,
591 const MachineInstr &UseMI,
592 unsigned UseIdx) const override;
593
594 bool useMachineCombiner() const override { return true; }
595
596 bool isAssociativeAndCommutative(const MachineInstr &Inst,
597 bool Invert) const override;
598
599 bool hasReassociableOperands(const MachineInstr &Inst,
600 const MachineBasicBlock *MBB) const override;
601
602 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
603 MachineInstr &NewMI1,
604 MachineInstr &NewMI2) const override;
605
606 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
607 Register &SrcReg2, int64_t &CmpMask,
608 int64_t &CmpValue) const override;
609
610 /// Check if there exists an earlier instruction that operates on the same
611 /// source operands and sets eflags in the same way as CMP and remove CMP if
612 /// possible.
613 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
614 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
615 const MachineRegisterInfo *MRI) const override;
616
617 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
618 MachineRegisterInfo *MRI) const override;
619
620 std::pair<unsigned, unsigned>
621 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
622
623 ArrayRef<std::pair<unsigned, const char *>>
624 getSerializableDirectMachineOperandTargetFlags() const override;
625
626 std::optional<std::unique_ptr<outliner::OutlinedFunction>>
627 getOutliningCandidateInfo(
628 const MachineModuleInfo &MMI,
629 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
630 unsigned MinRepeats) const override;
631
632 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
633 bool OutlineFromLinkOnceODRs) const override;
634
635 outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
636 MachineBasicBlock::iterator &MIT,
637 unsigned Flags) const override;
638
639 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
640 const outliner::OutlinedFunction &OF) const override;
641
642 MachineBasicBlock::iterator
643 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
644 MachineBasicBlock::iterator &It, MachineFunction &MF,
645 outliner::Candidate &C) const override;
646
647 void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
648 MachineBasicBlock::iterator Iter, DebugLoc &DL,
649 bool AllowSideEffects = true) const override;
650
651 bool verifyInstruction(const MachineInstr &MI,
652 StringRef &ErrInfo) const override;
653#define GET_INSTRINFO_HELPER_DECLS
654#include "X86GenInstrInfo.inc"
655
656 static bool hasLockPrefix(const MachineInstr &MI) {
657 return MI.getDesc().TSFlags & X86II::LOCK;
658 }
659
660 std::optional<ParamLoadedValue>
661 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
662
663protected:
664 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
665 unsigned CommuteOpIdx1,
666 unsigned CommuteOpIdx2) const override;
667
668 std::optional<DestSourcePair>
669 isCopyInstrImpl(const MachineInstr &MI) const override;
670
671 bool getMachineCombinerPatterns(MachineInstr &Root,
672 SmallVectorImpl<unsigned> &Patterns,
673 bool DoRegPressureReduce) const override;
674
675 /// When getMachineCombinerPatterns() finds potential patterns,
676 /// this function generates the instructions that could replace the
677 /// original code sequence.
678 void genAlternativeCodeSequence(
679 MachineInstr &Root, unsigned Pattern,
680 SmallVectorImpl<MachineInstr *> &InsInstrs,
681 SmallVectorImpl<MachineInstr *> &DelInstrs,
682 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
683
684 /// When calculate the latency of the root instruction, accumulate the
685 /// latency of the sequence to the root latency.
686 /// \param Root - Instruction that could be combined with one of its operands
687 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd
688 /// is not in the critical path, so the root latency only include vpmaddwd.
689 bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override {
690 return false;
691 }
692
693 void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
694 int FI) const override;
695
696private:
697 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
698 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
699 /// super-register and then truncating back down to a 8/16-bit sub-register.
700 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
701 LiveVariables *LV,
702 LiveIntervals *LIS,
703 bool Is8BitOp) const;
704
705 /// Handles memory folding for special case instructions, for instance those
706 /// requiring custom manipulation of the address.
707 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
708 unsigned OpNum,
709 ArrayRef<MachineOperand> MOs,
710 MachineBasicBlock::iterator InsertPt,
711 unsigned Size, Align Alignment) const;
712
713 MachineInstr *foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
714 unsigned OpNum,
715 ArrayRef<MachineOperand> MOs,
716 MachineBasicBlock::iterator InsertPt,
717 unsigned BitsSize, bool AllowCommute) const;
718
719 /// isFrameOperand - Return true and the FrameIndex if the specified
720 /// operand and follow operands form a reference to the stack frame.
721 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
722 int &FrameIndex) const;
723
724 /// Returns true iff the routine could find two commutable operands in the
725 /// given machine instruction with 3 vector inputs.
726 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
727 /// input values can be re-defined in this method only if the input values
728 /// are not pre-defined, which is designated by the special value
729 /// 'CommuteAnyOperandIndex' assigned to it.
730 /// If both of indices are pre-defined and refer to some operands, then the
731 /// method simply returns true if the corresponding operands are commutable
732 /// and returns false otherwise.
733 ///
734 /// For example, calling this method this way:
735 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
736 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
737 /// can be interpreted as a query asking to find an operand that would be
738 /// commutable with the operand#1.
739 ///
740 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
741 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
742 unsigned &SrcOpIdx1,
743 unsigned &SrcOpIdx2,
744 bool IsIntrinsic = false) const;
745
746 /// Returns true when instruction \p FlagI produces the same flags as \p OI.
747 /// The caller should pass in the results of calling analyzeCompare on \p OI:
748 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
749 /// If the flags match \p OI as if it had the input operands swapped then the
750 /// function succeeds and sets \p IsSwapped to true.
751 ///
752 /// Examples of OI, FlagI pairs returning true:
753 /// CMP %1, 42 and CMP %1, 42
754 /// CMP %1, %2 and %3 = SUB %1, %2
755 /// TEST %1, %1 and %2 = SUB %1, 0
756 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
757 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
758 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
759 const MachineInstr &OI, bool *IsSwapped,
760 int64_t *ImmDelta) const;
761
762 /// Commute operands of \p MI for memory fold.
763 ///
764 /// \param Idx1 the index of operand to be commuted.
765 ///
766 /// \returns the index of operand that is commuted with \p Idx1. If the method
767 /// fails to commute the operands, it will return \p Idx1.
768 unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const;
769};
770} // namespace llvm
771
772#endif
773