1//===-- X86SelectionDAGInfo.h - X86 SelectionDAG Info -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the X86 subclass for SelectionDAGTargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86SELECTIONDAGINFO_H
14#define LLVM_LIB_TARGET_X86_X86SELECTIONDAGINFO_H
15
16#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
17
18#define GET_SDNODE_ENUM
19#include "X86GenSDNodeInfo.inc"
20
21namespace llvm {
22namespace X86ISD {
23
24enum NodeType : unsigned {
25 /// The same as ISD::CopyFromReg except that this node makes it explicit
26 /// that it may lower to an x87 FPU stack pop. Optimizations should be more
27 /// cautious when handling this node than a normal CopyFromReg to avoid
28 /// removing a required FPU stack pop. A key requirement is optimizations
29 /// should not optimize any users of a chain that contains a
30 /// POP_FROM_X87_REG to use a chain from a point earlier than the
31 /// POP_FROM_X87_REG (which may remove a required FPU stack pop).
32 POP_FROM_X87_REG = X86ISD::GENERATED_OPCODE_END,
33
34 /// On Darwin, this node represents the result of the popl
35 /// at function entry, used for PIC code.
36 GlobalBaseReg,
37
38 // SSE42 string comparisons.
39 // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
40 // will emit one or two instructions based on which results are used. If
41 // flags and index/mask this allows us to use a single instruction since
42 // we won't have to pick and opcode for flags. Instead we can rely on the
43 // DAG to CSE everything and decide at isel.
44 PCMPISTR,
45 PCMPESTR,
46
47 // Compare and swap.
48 FIRST_MEMORY_OPCODE,
49 LCMPXCHG16_SAVE_RBX_DAG = FIRST_MEMORY_OPCODE,
50
51 // X86 specific gather and scatter
52 MGATHER,
53 MSCATTER,
54
55 // Key locker nodes that produce flags.
56 AESENCWIDE128KL,
57 AESDECWIDE128KL,
58 AESENCWIDE256KL,
59 AESDECWIDE256KL,
60 LAST_MEMORY_OPCODE = AESDECWIDE256KL,
61};
62
63} // namespace X86ISD
64
65class X86SelectionDAGInfo : public SelectionDAGGenTargetInfo {
66 /// Returns true if it is possible for the base register to conflict with the
67 /// given set of clobbers for a memory intrinsic.
68 bool isBaseRegConflictPossible(SelectionDAG &DAG,
69 ArrayRef<MCPhysReg> ClobberSet) const;
70
71public:
72 X86SelectionDAGInfo();
73
74 const char *getTargetNodeName(unsigned Opcode) const override;
75
76 bool isTargetMemoryOpcode(unsigned Opcode) const override;
77
78 void verifyTargetNode(const SelectionDAG &DAG,
79 const SDNode *N) const override;
80
81 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
82 SDValue Chain, SDValue Dst, SDValue Src,
83 SDValue Size, Align Alignment,
84 bool isVolatile, bool AlwaysInline,
85 MachinePointerInfo DstPtrInfo) const override;
86
87 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
88 SDValue Chain, SDValue Dst, SDValue Src,
89 SDValue Size, Align Alignment,
90 bool isVolatile, bool AlwaysInline,
91 MachinePointerInfo DstPtrInfo,
92 MachinePointerInfo SrcPtrInfo) const override;
93};
94
95} // namespace llvm
96
97#endif
98