1//===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file a TargetTransformInfoImplBase conforming object specific to the
10/// X86 target machine. It uses the target's detailed information to
11/// provide more precise answers to certain TTI queries, while letting the
12/// target independent and default TTI implementations handle the rest.
13///
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
17#define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
18
19#include "X86TargetMachine.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/CodeGen/BasicTTIImpl.h"
22#include <optional>
23
24namespace llvm {
25
26class InstCombiner;
27
28class X86TTIImpl final : public BasicTTIImplBase<X86TTIImpl> {
29 typedef BasicTTIImplBase<X86TTIImpl> BaseT;
30 typedef TargetTransformInfo TTI;
31 friend BaseT;
32
33 const X86Subtarget *ST;
34 const X86TargetLowering *TLI;
35
36 const X86Subtarget *getST() const { return ST; }
37 const X86TargetLowering *getTLI() const { return TLI; }
38
39 const FeatureBitset InlineFeatureIgnoreList = {
40 // This indicates the CPU is 64 bit capable not that we are in 64-bit
41 // mode.
42 X86::FeatureX86_64,
43
44 // These features don't have any intrinsics or ABI effect.
45 X86::FeatureNOPL,
46 X86::FeatureCX16,
47 X86::FeatureLAHFSAHF64,
48
49 // Some older targets can be setup to fold unaligned loads.
50 X86::FeatureSSEUnalignedMem,
51
52 // Codegen control options.
53 X86::TuningFast11ByteNOP,
54 X86::TuningFast15ByteNOP,
55 X86::TuningFastBEXTR,
56 X86::TuningFastHorizontalOps,
57 X86::TuningFastLZCNT,
58 X86::TuningFastScalarFSQRT,
59 X86::TuningFastSHLDRotate,
60 X86::TuningFastScalarShiftMasks,
61 X86::TuningFastVectorShiftMasks,
62 X86::TuningFastVariableCrossLaneShuffle,
63 X86::TuningFastVariablePerLaneShuffle,
64 X86::TuningFastVectorFSQRT,
65 X86::TuningLEAForSP,
66 X86::TuningLEAUsesAG,
67 X86::TuningLZCNTFalseDeps,
68 X86::TuningBranchFusion,
69 X86::TuningMacroFusion,
70 X86::TuningPadShortFunctions,
71 X86::TuningPOPCNTFalseDeps,
72 X86::TuningMULCFalseDeps,
73 X86::TuningPERMFalseDeps,
74 X86::TuningRANGEFalseDeps,
75 X86::TuningGETMANTFalseDeps,
76 X86::TuningMULLQFalseDeps,
77 X86::TuningSlow3OpsLEA,
78 X86::TuningSlowDivide32,
79 X86::TuningSlowDivide64,
80 X86::TuningSlowIncDec,
81 X86::TuningSlowLEA,
82 X86::TuningSlowPMADDWD,
83 X86::TuningSlowPMULLD,
84 X86::TuningSlowSHLD,
85 X86::TuningSlowTwoMemOps,
86 X86::TuningSlowUAMem16,
87 X86::TuningPreferMaskRegisters,
88 X86::TuningInsertVZEROUPPER,
89 X86::TuningUseSLMArithCosts,
90 X86::TuningUseGLMDivSqrtCosts,
91 X86::TuningNoDomainDelay,
92 X86::TuningNoDomainDelayMov,
93 X86::TuningNoDomainDelayShuffle,
94 X86::TuningNoDomainDelayBlend,
95 X86::TuningPreferShiftShuffle,
96 X86::TuningFastImmVectorShift,
97 X86::TuningFastDPWSSD,
98
99 // Perf-tuning flags.
100 X86::TuningFastGather,
101 X86::TuningSlowUAMem32,
102 X86::TuningAllowLight256Bit,
103
104 // Based on whether user set the -mprefer-vector-width command line.
105 X86::TuningPrefer128Bit,
106 X86::TuningPrefer256Bit,
107
108 // CPU name enums. These just follow CPU string.
109 X86::ProcIntelAtom
110 };
111
112public:
113 explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
114 : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
115 TLI(ST->getTargetLowering()) {}
116
117 /// \name Scalar TTI Implementations
118 /// @{
119 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override;
120
121 /// @}
122
123 /// \name Cache TTI Implementation
124 /// @{
125 std::optional<unsigned> getCacheSize(
126 TargetTransformInfo::CacheLevel Level) const override;
127 std::optional<unsigned> getCacheAssociativity(
128 TargetTransformInfo::CacheLevel Level) const override;
129 /// @}
130
131 /// \name Vector TTI Implementations
132 /// @{
133
134 unsigned getNumberOfRegisters(unsigned ClassID) const override;
135 unsigned getRegisterClassForType(bool Vector, Type *Ty) const override;
136 bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const override;
137 TypeSize
138 getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override;
139 unsigned getLoadStoreVecRegBitWidth(unsigned AS) const override;
140 unsigned getMaxInterleaveFactor(ElementCount VF) const override;
141 InstructionCost getArithmeticInstrCost(
142 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
143 TTI::OperandValueInfo Op1Info = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None},
144 TTI::OperandValueInfo Op2Info = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None},
145 ArrayRef<const Value *> Args = {},
146 const Instruction *CxtI = nullptr) const override;
147 InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
148 unsigned Opcode1,
149 const SmallBitVector &OpcodeMask,
150 TTI::TargetCostKind CostKind) const override;
151
152 InstructionCost
153 getShuffleCost(TTI::ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
154 ArrayRef<int> Mask, TTI::TargetCostKind CostKind, int Index,
155 VectorType *SubTp, ArrayRef<const Value *> Args = {},
156 const Instruction *CxtI = nullptr) const override;
157 InstructionCost
158 getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
159 TTI::CastContextHint CCH, TTI::TargetCostKind CostKind,
160 const Instruction *I = nullptr) const override;
161 InstructionCost getCmpSelInstrCost(
162 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
163 TTI::TargetCostKind CostKind,
164 TTI::OperandValueInfo Op1Info = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None},
165 TTI::OperandValueInfo Op2Info = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None},
166 const Instruction *I = nullptr) const override;
167 using BaseT::getVectorInstrCost;
168 InstructionCost
169 getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind,
170 unsigned Index, const Value *Op0, const Value *Op1,
171 TTI::VectorInstrContext VIC =
172 TTI::VectorInstrContext::None) const override;
173 InstructionCost
174 getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
175 bool Insert, bool Extract,
176 TTI::TargetCostKind CostKind,
177 bool ForPoisonSrc = true, ArrayRef<Value *> VL = {},
178 TTI::VectorInstrContext VIC =
179 TTI::VectorInstrContext::None) const override;
180 InstructionCost
181 getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
182 const APInt &DemandedDstElts,
183 TTI::TargetCostKind CostKind) const override;
184 InstructionCost getMemoryOpCost(
185 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
186 TTI::TargetCostKind CostKind,
187 TTI::OperandValueInfo OpInfo = {.Kind: TTI::OK_AnyValue, .Properties: TTI::OP_None},
188 const Instruction *I = nullptr) const override;
189 InstructionCost
190 getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA,
191 TTI::TargetCostKind CostKind) const override;
192 InstructionCost getMaskedMemoryOpCost(const MemIntrinsicCostAttributes &MICA,
193 TTI::TargetCostKind CostKind) const;
194 InstructionCost getGatherScatterOpCost(const MemIntrinsicCostAttributes &MICA,
195 TTI::TargetCostKind CostKind) const;
196 InstructionCost
197 getPointersChainCost(ArrayRef<const Value *> Ptrs, const Value *Base,
198 const TTI::PointersChainInfo &Info, Type *AccessTy,
199 TTI::TargetCostKind CostKind) const override;
200 InstructionCost
201 getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr,
202 TTI::TargetCostKind CostKind) const override;
203
204 std::optional<Instruction *>
205 instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override;
206 std::optional<Value *>
207 simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
208 APInt DemandedMask, KnownBits &Known,
209 bool &KnownBitsComputed) const override;
210 std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
211 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
212 APInt &UndefElts2, APInt &UndefElts3,
213 std::function<void(Instruction *, unsigned, APInt, APInt &)>
214 SimplifyAndSetOp) const override;
215
216 unsigned getAtomicMemIntrinsicMaxElementSize() const override;
217
218 InstructionCost
219 getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
220 TTI::TargetCostKind CostKind) const override;
221
222 InstructionCost
223 getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
224 std::optional<FastMathFlags> FMF,
225 TTI::TargetCostKind CostKind) const override;
226
227 InstructionCost getMinMaxCost(Intrinsic::ID IID, Type *Ty,
228 TTI::TargetCostKind CostKind,
229 FastMathFlags FMF) const;
230
231 InstructionCost
232 getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
233 TTI::TargetCostKind CostKind) const override;
234
235 InstructionCost getInterleavedMemoryOpCost(
236 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
237 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
238 bool UseMaskForCond = false, bool UseMaskForGaps = false) const override;
239 InstructionCost getInterleavedMemoryOpCostAVX512(
240 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
241 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
242 TTI::TargetCostKind CostKind, bool UseMaskForCond = false,
243 bool UseMaskForGaps = false) const;
244
245 InstructionCost getIntImmCost(int64_t) const;
246
247 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
248 TTI::TargetCostKind CostKind) const override;
249
250 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
251 const Instruction *I = nullptr) const override;
252
253 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
254 const APInt &Imm, Type *Ty,
255 TTI::TargetCostKind CostKind,
256 Instruction *Inst = nullptr) const override;
257 InstructionCost
258 getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
259 Type *Ty, TTI::TargetCostKind CostKind) const override;
260 /// Return the cost of the scaling factor used in the addressing
261 /// mode represented by AM for this target, for a load/store
262 /// of the specified type.
263 /// If the AM is supported, the return value must be >= 0.
264 /// If the AM is not supported, it returns an invalid cost.
265 InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
266 StackOffset BaseOffset, bool HasBaseReg,
267 int64_t Scale,
268 unsigned AddrSpace) const override;
269
270 bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
271 const TargetTransformInfo::LSRCost &C2) const override;
272 bool canMacroFuseCmp() const override;
273 bool
274 isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned AddressSpace,
275 TTI::MaskKind MaskKind =
276 TTI::MaskKind::VariableOrConstantMask) const override;
277 bool
278 isLegalMaskedStore(Type *DataType, Align Alignment, unsigned AddressSpace,
279 TTI::MaskKind MaskKind =
280 TTI::MaskKind::VariableOrConstantMask) const override;
281 bool isLegalNTLoad(Type *DataType, Align Alignment) const override;
282 bool isLegalNTStore(Type *DataType, Align Alignment) const override;
283 bool isLegalBroadcastLoad(Type *ElementTy,
284 ElementCount NumElements) const override;
285 bool forceScalarizeMaskedGather(VectorType *VTy,
286 Align Alignment) const override;
287 bool forceScalarizeMaskedScatter(VectorType *VTy,
288 Align Alignment) const override {
289 return forceScalarizeMaskedGather(VTy, Alignment);
290 }
291 bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment) const;
292 bool isLegalMaskedGather(Type *DataType, Align Alignment) const override;
293 bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override;
294 bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const override;
295 bool isLegalMaskedCompressStore(Type *DataType,
296 Align Alignment) const override;
297 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
298 const SmallBitVector &OpcodeMask) const override;
299 bool hasDivRemOp(Type *DataType, bool IsSigned) const override;
300 bool isExpensiveToSpeculativelyExecute(const Instruction *I) const override;
301 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const override;
302 bool areInlineCompatible(const Function *Caller,
303 const Function *Callee) const override;
304 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
305 ArrayRef<Type *> Type) const override;
306
307 uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override {
308 return ST->getMaxInlineSizeThreshold();
309 }
310
311 TTI::MemCmpExpansionOptions
312 enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override;
313 bool preferAlternateOpcodeVectorization() const override { return false; }
314 bool prefersVectorizedAddressing() const override;
315 bool supportsEfficientVectorElementLoadStore() const override;
316 bool enableInterleavedAccessVectorization() const override;
317
318 InstructionCost getBranchMispredictPenalty() const override;
319
320 bool isProfitableToSinkOperands(Instruction *I,
321 SmallVectorImpl<Use *> &Ops) const override;
322
323 bool isVectorShiftByScalarCheap(Type *Ty) const override;
324
325 unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
326 Type *ScalarValTy) const override;
327
328 bool useFastCCForInternalCall(Function &F) const override;
329
330private:
331 bool supportsGather() const;
332 InstructionCost getGSVectorCost(unsigned Opcode, TTI::TargetCostKind CostKind,
333 Type *DataTy, const Value *Ptr,
334 Align Alignment, unsigned AddressSpace) const;
335
336 int getGatherOverhead() const;
337 int getScatterOverhead() const;
338
339 /// @}
340};
341
342} // end namespace llvm
343
344#endif
345