1//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that XCore uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
15#define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
16
17#include "XCore.h"
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/CodeGen/TargetLowering.h"
20
21namespace llvm {
22
23 // Forward delcarations
24 class XCoreSubtarget;
25
26 //===--------------------------------------------------------------------===//
27 // TargetLowering Implementation
28 //===--------------------------------------------------------------------===//
29 class XCoreTargetLowering : public TargetLowering
30 {
31 public:
32 explicit XCoreTargetLowering(const TargetMachine &TM,
33 const XCoreSubtarget &Subtarget);
34
35 using TargetLowering::isZExtFree;
36 bool isZExtFree(SDValue Val, EVT VT2) const override;
37
38
39 unsigned getJumpTableEncoding() const override;
40 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override {
41 return MVT::i32;
42 }
43
44 /// LowerOperation - Provide custom lowering hooks for some operations.
45 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
46
47 /// ReplaceNodeResults - Replace the results of node with an illegal result
48 /// type with new values built out of custom code.
49 ///
50 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
51 SelectionDAG &DAG) const override;
52
53 MachineBasicBlock *
54 EmitInstrWithCustomInserter(MachineInstr &MI,
55 MachineBasicBlock *MBB) const override;
56
57 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
58 Type *Ty, unsigned AS,
59 Instruction *I = nullptr) const override;
60
61 /// If a physical register, this returns the register that receives the
62 /// exception address on entry to an EH pad.
63 Register
64 getExceptionPointerRegister(ExceptionHandling EH,
65 const Constant *PersonalityFn) const override {
66 return XCore::R0;
67 }
68
69 /// If a physical register, this returns the register that receives the
70 /// exception typeid on entry to a landing pad.
71 Register
72 getExceptionSelectorRegister(ExceptionHandling EH,
73 const Constant *PersonalityFn) const override {
74 return XCore::R1;
75 }
76
77 private:
78 const TargetMachine &TM;
79 const XCoreSubtarget &Subtarget;
80
81 // Lower Operand helpers
82 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
83 bool isVarArg,
84 const SmallVectorImpl<ISD::InputArg> &Ins,
85 const SDLoc &dl, SelectionDAG &DAG,
86 SmallVectorImpl<SDValue> &InVals) const;
87 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
88 CallingConv::ID CallConv, bool isVarArg,
89 bool isTailCall,
90 const SmallVectorImpl<ISD::OutputArg> &Outs,
91 const SmallVectorImpl<SDValue> &OutVals,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
93 const SDLoc &dl, SelectionDAG &DAG,
94 SmallVectorImpl<SDValue> &InVals) const;
95 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
96 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
97 SelectionDAG &DAG) const;
98 SDValue lowerLoadWordFromAlignedBasePlusOffset(const SDLoc &DL,
99 SDValue Chain, SDValue Base,
100 int64_t Offset,
101 SelectionDAG &DAG) const;
102
103 // Lower Operand specifics
104 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
123
124 // Inline asm support
125 std::pair<unsigned, const TargetRegisterClass *>
126 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
127 StringRef Constraint, MVT VT) const override;
128
129 // Expand specifics
130 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
131 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
132
133 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
134
135 void computeKnownBitsForTargetNode(const SDValue Op,
136 KnownBits &Known,
137 const APInt &DemandedElts,
138 const SelectionDAG &DAG,
139 unsigned Depth = 0) const override;
140
141 SDValue
142 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
143 const SmallVectorImpl<ISD::InputArg> &Ins,
144 const SDLoc &dl, SelectionDAG &DAG,
145 SmallVectorImpl<SDValue> &InVals) const override;
146
147 SDValue
148 LowerCall(TargetLowering::CallLoweringInfo &CLI,
149 SmallVectorImpl<SDValue> &InVals) const override;
150
151 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
152 const SmallVectorImpl<ISD::OutputArg> &Outs,
153 const SmallVectorImpl<SDValue> &OutVals,
154 const SDLoc &dl, SelectionDAG &DAG) const override;
155
156 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
157 bool isVarArg,
158 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
159 LLVMContext &Context, const Type *RetTy) const override;
160 };
161}
162
163#endif
164