1//===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the XCore implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
14#define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
15
16#include "XCoreRegisterInfo.h"
17#include "llvm/CodeGen/TargetInstrInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "XCoreGenInstrInfo.inc"
21
22namespace llvm {
23class XCoreSubtarget;
24
25class XCoreInstrInfo : public XCoreGenInstrInfo {
26 const XCoreRegisterInfo RI;
27 virtual void anchor();
28public:
29 explicit XCoreInstrInfo(const XCoreSubtarget &ST);
30
31 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
32 /// such, whenever a client has an instance of instruction info, it should
33 /// always be able to get register info as well (through this method).
34 ///
35 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
36
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
38 /// load from a stack slot, return the virtual or physical register number of
39 /// the destination along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than loading from the stack slot.
42 Register isLoadFromStackSlot(const MachineInstr &MI,
43 int &FrameIndex) const override;
44
45 /// isStoreToStackSlot - If the specified machine instruction is a direct
46 /// store to a stack slot, return the virtual or physical register number of
47 /// the source reg along with the FrameIndex of the loaded stack slot. If
48 /// not, return 0. This predicate must return 0 if the instruction has
49 /// any side effects other than storing to the stack slot.
50 Register isStoreToStackSlot(const MachineInstr &MI,
51 int &FrameIndex) const override;
52
53 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
54 MachineBasicBlock *&FBB,
55 SmallVectorImpl<MachineOperand> &Cond,
56 bool AllowModify) const override;
57
58 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
60 const DebugLoc &DL,
61 int *BytesAdded = nullptr) const override;
62
63 unsigned removeBranch(MachineBasicBlock &MBB,
64 int *BytesRemoved = nullptr) const override;
65
66 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
67 const DebugLoc &DL, Register DestReg, Register SrcReg,
68 bool KillSrc, bool RenamableDest = false,
69 bool RenamableSrc = false) const override;
70
71 void storeRegToStackSlot(
72 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
73 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
74
75 Register VReg,
76 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
77
78 void loadRegFromStackSlot(
79 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
80 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
81 unsigned SubReg = 0,
82 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
83
84 bool reverseBranchCondition(
85 SmallVectorImpl<MachineOperand> &Cond) const override;
86
87 // Emit code before MBBI to load immediate value into physical register Reg.
88 // Returns an iterator to the new instruction.
89 MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator MI,
91 unsigned Reg, uint64_t Value) const;
92};
93
94}
95
96#endif
97