1//===-- XCoreTargetMachine.cpp - Define TargetMachine for XCore -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "XCoreTargetMachine.h"
13#include "TargetInfo/XCoreTargetInfo.h"
14#include "XCore.h"
15#include "XCoreMachineFunctionInfo.h"
16#include "XCoreTargetObjectFile.h"
17#include "XCoreTargetTransformInfo.h"
18#include "llvm/Analysis/TargetTransformInfo.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/TargetPassConfig.h"
21#include "llvm/MC/TargetRegistry.h"
22#include "llvm/Support/CodeGen.h"
23#include "llvm/Support/Compiler.h"
24#include <optional>
25
26using namespace llvm;
27
28static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
29 return RM.value_or(u: Reloc::Static);
30}
31
32static CodeModel::Model
33getEffectiveXCoreCodeModel(std::optional<CodeModel::Model> CM) {
34 if (CM) {
35 if (*CM != CodeModel::Small && *CM != CodeModel::Large)
36 report_fatal_error(reason: "Target only supports CodeModel Small or Large");
37 return *CM;
38 }
39 return CodeModel::Small;
40}
41
42/// Create an ILP32 architecture model
43///
44XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
45 StringRef CPU, StringRef FS,
46 const TargetOptions &Options,
47 std::optional<Reloc::Model> RM,
48 std::optional<CodeModel::Model> CM,
49 CodeGenOptLevel OL, bool JIT)
50 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
51 getEffectiveRelocModel(RM),
52 getEffectiveXCoreCodeModel(CM), OL),
53 TLOF(std::make_unique<XCoreTargetObjectFile>()),
54 Subtarget(TT, std::string(CPU), std::string(FS), *this) {
55 initAsmInfo();
56}
57
58XCoreTargetMachine::~XCoreTargetMachine() = default;
59
60namespace {
61
62/// XCore Code Generator Pass Configuration Options.
63class XCorePassConfig : public TargetPassConfig {
64public:
65 XCorePassConfig(XCoreTargetMachine &TM, PassManagerBase &PM)
66 : TargetPassConfig(TM, PM) {}
67
68 XCoreTargetMachine &getXCoreTargetMachine() const {
69 return getTM<XCoreTargetMachine>();
70 }
71
72 void addIRPasses() override;
73 bool addPreISel() override;
74 bool addInstSelector() override;
75 void addPreEmitPass() override;
76};
77
78} // end anonymous namespace
79
80TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
81 return new XCorePassConfig(*this, PM);
82}
83
84void XCorePassConfig::addIRPasses() {
85 addPass(P: createAtomicExpandLegacyPass());
86
87 TargetPassConfig::addIRPasses();
88}
89
90bool XCorePassConfig::addPreISel() {
91 addPass(P: createXCoreLowerThreadLocalPass());
92 return false;
93}
94
95bool XCorePassConfig::addInstSelector() {
96 addPass(P: createXCoreISelDag(TM&: getXCoreTargetMachine(), OptLevel: getOptLevel()));
97 return false;
98}
99
100void XCorePassConfig::addPreEmitPass() {
101 addPass(P: createXCoreFrameToArgsOffsetEliminationPass());
102}
103
104// Force static initialization.
105extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() {
106 RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget());
107 PassRegistry &PR = *PassRegistry::getPassRegistry();
108 initializeXCoreAsmPrinterPass(PR);
109 initializeXCoreDAGToDAGISelLegacyPass(PR);
110 initializeXCoreLowerThreadLocalPass(p&: PR);
111}
112
113TargetTransformInfo
114XCoreTargetMachine::getTargetTransformInfo(const Function &F) const {
115 return TargetTransformInfo(std::make_unique<XCoreTTIImpl>(args: this, args: F));
116}
117
118MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo(
119 BumpPtrAllocator &Allocator, const Function &F,
120 const TargetSubtargetInfo *STI) const {
121 return XCoreFunctionInfo::create<XCoreFunctionInfo>(Allocator, F, STI);
122}
123