1//===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend emits a target specifier matcher for converting parsed
10// assembly operands in the MCInst structures. It also emits a matcher for
11// custom operand parsing.
12//
13// Converting assembly operands into MCInst structures
14// ---------------------------------------------------
15//
16// The input to the target specific matcher is a list of literal tokens and
17// operands. The target specific parser should generally eliminate any syntax
18// which is not relevant for matching; for example, comma tokens should have
19// already been consumed and eliminated by the parser. Most instructions will
20// end up with a single literal token (the instruction name) and some number of
21// operands.
22//
23// Some example inputs, for X86:
24// 'addl' (immediate ...) (register ...)
25// 'add' (immediate ...) (memory ...)
26// 'call' '*' %epc
27//
28// The assembly matcher is responsible for converting this input into a precise
29// machine instruction (i.e., an instruction with a well defined encoding). This
30// mapping has several properties which complicate matching:
31//
32// - It may be ambiguous; many architectures can legally encode particular
33// variants of an instruction in different ways (for example, using a smaller
34// encoding for small immediates). Such ambiguities should never be
35// arbitrarily resolved by the assembler, the assembler is always responsible
36// for choosing the "best" available instruction.
37//
38// - It may depend on the subtarget or the assembler context. Instructions
39// which are invalid for the current mode, but otherwise unambiguous (e.g.,
40// an SSE instruction in a file being assembled for i486) should be accepted
41// and rejected by the assembler front end. However, if the proper encoding
42// for an instruction is dependent on the assembler context then the matcher
43// is responsible for selecting the correct machine instruction for the
44// current mode.
45//
46// The core matching algorithm attempts to exploit the regularity in most
47// instruction sets to quickly determine the set of possibly matching
48// instructions, and the simplify the generated code. Additionally, this helps
49// to ensure that the ambiguities are intentionally resolved by the user.
50//
51// The matching is divided into two distinct phases:
52//
53// 1. Classification: Each operand is mapped to the unique set which (a)
54// contains it, and (b) is the largest such subset for which a single
55// instruction could match all members.
56//
57// For register classes, we can generate these subgroups automatically. For
58// arbitrary operands, we expect the user to define the classes and their
59// relations to one another (for example, 8-bit signed immediates as a
60// subset of 32-bit immediates).
61//
62// By partitioning the operands in this way, we guarantee that for any
63// tuple of classes, any single instruction must match either all or none
64// of the sets of operands which could classify to that tuple.
65//
66// In addition, the subset relation amongst classes induces a partial order
67// on such tuples, which we use to resolve ambiguities.
68//
69// 2. The input can now be treated as a tuple of classes (static tokens are
70// simple singleton sets). Each such tuple should generally map to a single
71// instruction (we currently ignore cases where this isn't true, whee!!!),
72// which we can emit a simple matcher for.
73//
74// Custom Operand Parsing
75// ----------------------
76//
77// Some targets need a custom way to parse operands, some specific instructions
78// can contain arguments that can represent processor flags and other kinds of
79// identifiers that need to be mapped to specific values in the final encoded
80// instructions. The target specific custom operand parsing works in the
81// following way:
82//
83// 1. A operand match table is built, each entry contains a mnemonic, an
84// operand class, a mask for all operand positions for that same
85// class/mnemonic and target features to be checked while trying to match.
86//
87// 2. The operand matcher will try every possible entry with the same
88// mnemonic and will check if the target feature for this mnemonic also
89// matches. After that, if the operand to be matched has its index
90// present in the mask, a successful match occurs. Otherwise, fallback
91// to the regular operand parsing.
92//
93// 3. For a match success, each operand class that has a 'ParserMethod'
94// becomes part of a switch from where the custom method is called.
95//
96//===----------------------------------------------------------------------===//
97
98#include "Common/CodeGenInstAlias.h"
99#include "Common/CodeGenInstruction.h"
100#include "Common/CodeGenRegisters.h"
101#include "Common/CodeGenTarget.h"
102#include "Common/SubtargetFeatureInfo.h"
103#include "Common/Types.h"
104#include "llvm/ADT/CachedHashString.h"
105#include "llvm/ADT/PointerUnion.h"
106#include "llvm/ADT/STLExtras.h"
107#include "llvm/ADT/SmallPtrSet.h"
108#include "llvm/ADT/SmallVector.h"
109#include "llvm/ADT/StringExtras.h"
110#include "llvm/Support/CommandLine.h"
111#include "llvm/Support/Debug.h"
112#include "llvm/Support/ErrorHandling.h"
113#include "llvm/Support/FormatVariadic.h"
114#include "llvm/TableGen/Error.h"
115#include "llvm/TableGen/Record.h"
116#include "llvm/TableGen/StringMatcher.h"
117#include "llvm/TableGen/StringToOffsetTable.h"
118#include "llvm/TableGen/TableGenBackend.h"
119#include <cassert>
120#include <cctype>
121#include <forward_list>
122#include <map>
123#include <set>
124
125using namespace llvm;
126
127#define DEBUG_TYPE "asm-matcher-emitter"
128
129static cl::OptionCategory AsmMatcherEmitterCat("Options for -gen-asm-matcher");
130
131static cl::opt<std::string>
132 MatchPrefix("match-prefix", cl::init(Val: ""),
133 cl::desc("Only match instructions with the given prefix"),
134 cl::cat(AsmMatcherEmitterCat));
135
136namespace {
137class AsmMatcherInfo;
138
139// Register sets are used as keys in some second-order sets TableGen creates
140// when generating its data structures. This means that the order of two
141// RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
142// can even affect compiler output (at least seen in diagnostics produced when
143// all matches fail). So they must be sorted consistently (see LessRegisterSet).
144// Each bit in the BitVector represents the presence of a physical register.
145using RegisterSet = BitVector;
146
147class AsmMatcherEmitter {
148 const RecordKeeper &Records;
149
150public:
151 AsmMatcherEmitter(const RecordKeeper &R) : Records(R) {}
152
153 void run(raw_ostream &o);
154};
155
156/// ClassInfo - Helper class for storing the information about a particular
157/// class of operands which can be matched.
158struct ClassInfo {
159 enum ClassInfoKind {
160 /// Invalid kind, for use as a sentinel value.
161 Invalid = 0,
162
163 /// The class for a particular token.
164 Token,
165
166 /// The (first) register class, subsequent register classes are
167 /// RegisterClass0+1, and so on.
168 RegisterClass0,
169
170 /// The (first) register class by hwmode, subsequent register classes by
171 /// hwmode are RegisterClassByHwMode0+1, and so on.
172 RegisterClassByHwMode0 = 1 << 12,
173
174 /// The (first) user defined class, subsequent user defined classes are
175 /// UserClass0+1, and so on.
176 UserClass0 = 1 << 24
177 };
178
179 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
180 /// N) for the Nth user defined class.
181 unsigned Kind = 0;
182
183 /// SuperClasses - The super classes of this class. Note that for simplicities
184 /// sake user operands only record their immediate super class, while register
185 /// operands include all superclasses.
186 std::vector<ClassInfo *> SuperClasses;
187
188 /// Name - The full class name, suitable for use in an enum.
189 std::string Name;
190
191 /// ClassName - The unadorned generic name for this class (e.g., Token).
192 std::string ClassName;
193
194 /// ValueName - The name of the value this class represents; for a token this
195 /// is the literal token string, for an operand it is the TableGen class (or
196 /// empty if this is a derived class).
197 std::string ValueName;
198
199 /// PredicateMethod - The name of the operand method to test whether the
200 /// operand matches this class; this is not valid for Token or register kinds.
201 std::string PredicateMethod;
202
203 /// RenderMethod - The name of the operand method to add this operand to an
204 /// MCInst; this is not valid for Token or register kinds.
205 std::string RenderMethod;
206
207 /// ParserMethod - The name of the operand method to do a target specific
208 /// parsing on the operand.
209 std::string ParserMethod;
210
211 /// For register classes: the records for all the registers in this class.
212 RegisterSet Registers;
213
214 /// For custom match classes: the diagnostic kind for when the predicate
215 /// fails.
216 std::string DiagnosticType;
217
218 /// For custom match classes: the diagnostic string for when the predicate
219 /// fails.
220 std::string DiagnosticString;
221
222 /// Is this operand optional and not always required.
223 bool IsOptional = false;
224
225 /// DefaultMethod - The name of the method that returns the default operand
226 /// for optional operand
227 std::string DefaultMethod;
228
229public:
230 /// isRegisterClass() - Check if this is a register class.
231 bool isRegisterClass() const {
232 return Kind >= RegisterClass0 && Kind < RegisterClassByHwMode0;
233 }
234
235 bool isRegisterClassByHwMode() const {
236 return Kind >= RegisterClassByHwMode0 && Kind < UserClass0;
237 }
238
239 /// isUserClass() - Check if this is a user defined class.
240 bool isUserClass() const { return Kind >= UserClass0; }
241
242 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
243 /// are related if they are in the same class hierarchy.
244 bool isRelatedTo(const ClassInfo &RHS) const {
245 // Tokens are only related to tokens.
246 if (Kind == Token || RHS.Kind == Token)
247 return Kind == Token && RHS.Kind == Token;
248
249 // Registers classes are only related to registers classes, and only if
250 // their intersection is non-empty.
251 if (isRegisterClass() || RHS.isRegisterClass()) {
252 if (!isRegisterClass() || !RHS.isRegisterClass())
253 return false;
254
255 return Registers.anyCommon(RHS: RHS.Registers);
256 }
257
258 if (isRegisterClassByHwMode() || RHS.isRegisterClassByHwMode())
259 return isRegisterClassByHwMode() == RHS.isRegisterClassByHwMode();
260
261 // Otherwise we have two users operands; they are related if they are in the
262 // same class hierarchy.
263 //
264 // FIXME: This is an oversimplification, they should only be related if they
265 // intersect, however we don't have that information.
266 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
267 const ClassInfo *Root = this;
268 while (!Root->SuperClasses.empty())
269 Root = Root->SuperClasses.front();
270
271 const ClassInfo *RHSRoot = &RHS;
272 while (!RHSRoot->SuperClasses.empty())
273 RHSRoot = RHSRoot->SuperClasses.front();
274
275 return Root == RHSRoot;
276 }
277
278 /// isSubsetOf - Test whether this class is a subset of \p RHS.
279 bool isSubsetOf(const ClassInfo &RHS) const {
280 // This is a subset of RHS if it is the same class...
281 if (this == &RHS)
282 return true;
283
284 // ... or if any of its super classes are a subset of RHS.
285 SmallVector<const ClassInfo *, 16> Worklist(SuperClasses.begin(),
286 SuperClasses.end());
287 SmallPtrSet<const ClassInfo *, 16> Visited;
288 while (!Worklist.empty()) {
289 auto *CI = Worklist.pop_back_val();
290 if (CI == &RHS)
291 return true;
292 for (auto *Super : CI->SuperClasses)
293 if (Visited.insert(Ptr: Super).second)
294 Worklist.push_back(Elt: Super);
295 }
296
297 return false;
298 }
299
300 int getTreeDepth() const {
301 int Depth = 0;
302 const ClassInfo *Root = this;
303 while (!Root->SuperClasses.empty()) {
304 Depth++;
305 Root = Root->SuperClasses.front();
306 }
307 return Depth;
308 }
309
310 const ClassInfo *findRoot() const {
311 const ClassInfo *Root = this;
312 while (!Root->SuperClasses.empty())
313 Root = Root->SuperClasses.front();
314 return Root;
315 }
316
317 /// Compare two classes. This does not produce a total ordering, but does
318 /// guarantee that subclasses are sorted before their parents, and that the
319 /// ordering is transitive.
320 bool operator<(const ClassInfo &RHS) const {
321 if (this == &RHS)
322 return false;
323
324 // First, enforce the ordering between the three different types of class.
325 // Tokens sort before registers, which sort before regclass by hwmode, which
326 // sort before user classes.
327 if (Kind == Token) {
328 if (RHS.Kind != Token)
329 return true;
330 assert(RHS.Kind == Token);
331 } else if (isRegisterClass()) {
332 if (RHS.Kind == Token)
333 return false;
334 else if (RHS.isUserClass() || RHS.isRegisterClassByHwMode())
335 return true;
336 assert(RHS.isRegisterClass());
337 } else if (isRegisterClassByHwMode()) {
338 if (RHS.Kind == Token || RHS.isRegisterClass())
339 return false;
340 else if (RHS.isUserClass())
341 return true;
342 assert(RHS.isRegisterClassByHwMode());
343 } else if (isUserClass()) {
344 if (!RHS.isUserClass())
345 return false;
346 assert(RHS.isUserClass());
347 } else {
348 llvm_unreachable("Unknown ClassInfoKind");
349 }
350
351 if (Kind == Token || isUserClass()) {
352 // Related tokens and user classes get sorted by depth in the inheritence
353 // tree (so that subclasses are before their parents).
354 if (isRelatedTo(RHS)) {
355 if (getTreeDepth() > RHS.getTreeDepth())
356 return true;
357 if (getTreeDepth() < RHS.getTreeDepth())
358 return false;
359 } else {
360 // Unrelated tokens and user classes are ordered by the name of their
361 // root nodes, so that there is a consistent ordering between
362 // unconnected trees.
363 return findRoot()->ValueName < RHS.findRoot()->ValueName;
364 }
365 } else if (isRegisterClass()) {
366 // For register sets, sort by number of registers. This guarantees that
367 // a set will always sort before all of it's strict supersets.
368 if (Registers.count() != RHS.Registers.count())
369 return Registers.count() < RHS.Registers.count();
370 } else if (isRegisterClassByHwMode()) {
371 // Ensure the MCK enum entries are in the same order as RegClassIDs. The
372 // lookup table to from RegByHwMode to concrete class relies on it.
373 return Kind < RHS.Kind;
374 } else {
375 llvm_unreachable("Unknown ClassInfoKind");
376 }
377
378 // FIXME: We should be able to just return false here, as we only need a
379 // partial order (we use stable sorts, so this is deterministic) and the
380 // name of a class shouldn't be significant. However, some of the backends
381 // accidentally rely on this behaviour, so it will have to stay like this
382 // until they are fixed.
383 return ValueName < RHS.ValueName;
384 }
385};
386
387class AsmVariantInfo {
388public:
389 StringRef RegisterPrefix;
390 StringRef TokenizingCharacters;
391 StringRef SeparatorCharacters;
392 StringRef BreakCharacters;
393 StringRef Name;
394 int AsmVariantNo;
395};
396
397bool getPreferSmallerInstructions(CodeGenTarget const &Target) {
398 return Target.getAsmParser()->getValueAsBit(FieldName: "PreferSmallerInstructions");
399}
400
401/// MatchableInfo - Helper class for storing the necessary information for an
402/// instruction or alias which is capable of being matched.
403struct MatchableInfo {
404 struct AsmOperand {
405 /// Token - This is the token that the operand came from.
406 StringRef Token;
407
408 /// The unique class instance this operand should match.
409 ClassInfo *Class = nullptr;
410
411 /// The operand name this is, if anything.
412 StringRef SrcOpName;
413
414 /// The operand name this is, before renaming for tied operands.
415 StringRef OrigSrcOpName;
416
417 /// The suboperand index within SrcOpName, or -1 for the entire operand.
418 int SubOpIdx = -1;
419
420 /// Whether the token is "isolated", i.e., it is preceded and followed
421 /// by separators.
422 bool IsIsolatedToken;
423
424 /// Register record if this token is singleton register.
425 const Record *SingletonReg = nullptr;
426
427 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
428 : Token(T), IsIsolatedToken(IsIsolatedToken) {}
429 };
430
431 /// ResOperand - This represents a single operand in the result instruction
432 /// generated by the match. In cases (like addressing modes) where a single
433 /// assembler operand expands to multiple MCOperands, this represents the
434 /// single assembler operand, not the MCOperand.
435 struct ResOperand {
436 enum {
437 /// RenderAsmOperand - This represents an operand result that is
438 /// generated by calling the render method on the assembly operand. The
439 /// corresponding AsmOperand is specified by AsmOperandNum.
440 RenderAsmOperand,
441
442 /// TiedOperand - This represents a result operand that is a duplicate of
443 /// a previous result operand.
444 TiedOperand,
445
446 /// ImmOperand - This represents an immediate value that is dumped into
447 /// the operand.
448 ImmOperand,
449
450 /// RegOperand - This represents a fixed register (potentially depending
451 /// on the HwMode) that is dumped in.
452 RegOperand,
453 } Kind;
454
455 /// Tuple containing the index of the (earlier) result operand that should
456 /// be copied from, as well as the indices of the corresponding (parsed)
457 /// operands in the asm string.
458 struct TiedOperandsTuple {
459 unsigned ResOpnd;
460 unsigned SrcOpnd1Idx;
461 unsigned SrcOpnd2Idx;
462 };
463
464 union {
465 /// This is the operand # in the AsmOperands list that this should be
466 /// copied from.
467 unsigned AsmOperandNum;
468
469 /// Description of tied operands.
470 TiedOperandsTuple TiedOperands;
471
472 /// ImmVal - This is the immediate value added to the instruction.
473 int64_t ImmVal;
474
475 /// Register - This is the register record.
476 const Record *Register;
477 };
478
479 /// MINumOperands - The number of MCInst operands populated by this
480 /// operand.
481 unsigned MINumOperands;
482
483 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
484 ResOperand X;
485 X.Kind = RenderAsmOperand;
486 X.AsmOperandNum = AsmOpNum;
487 X.MINumOperands = NumOperands;
488 return X;
489 }
490
491 static ResOperand getTiedOp(unsigned TiedOperandNum, unsigned SrcOperand1,
492 unsigned SrcOperand2) {
493 ResOperand X;
494 X.Kind = TiedOperand;
495 X.TiedOperands = {.ResOpnd: TiedOperandNum, .SrcOpnd1Idx: SrcOperand1, .SrcOpnd2Idx: SrcOperand2};
496 X.MINumOperands = 1;
497 return X;
498 }
499
500 static ResOperand getImmOp(int64_t Val) {
501 ResOperand X;
502 X.Kind = ImmOperand;
503 X.ImmVal = Val;
504 X.MINumOperands = 1;
505 return X;
506 }
507
508 static ResOperand getRegOp(const Record *Reg) {
509 ResOperand X;
510 X.Kind = RegOperand;
511 X.Register = Reg;
512 X.MINumOperands = 1;
513 return X;
514 }
515 };
516
517 /// AsmVariantID - Target's assembly syntax variant no.
518 int AsmVariantID;
519
520 /// AsmString - The assembly string for this instruction (with variants
521 /// removed), e.g. "movsx $src, $dst".
522 std::string AsmString;
523
524 /// TheDef - This is the definition of the instruction or InstAlias that this
525 /// matchable came from.
526 const Record *const TheDef;
527
528 // ResInstSize - The size of the resulting instruction for this matchable.
529 unsigned ResInstSize;
530
531 /// DefRec - This is the definition that it came from.
532 PointerUnion<const CodeGenInstruction *, const CodeGenInstAlias *> DefRec;
533
534 const CodeGenInstruction *getResultInst() const {
535 if (isa<const CodeGenInstruction *>(Val: DefRec))
536 return cast<const CodeGenInstruction *>(Val: DefRec);
537 return cast<const CodeGenInstAlias *>(Val: DefRec)->ResultInst;
538 }
539
540 /// ResOperands - This is the operand list that should be built for the result
541 /// MCInst.
542 SmallVector<ResOperand, 8> ResOperands;
543
544 /// Mnemonic - This is the first token of the matched instruction, its
545 /// mnemonic.
546 StringRef Mnemonic;
547
548 /// AsmOperands - The textual operands that this instruction matches,
549 /// annotated with a class and where in the OperandList they were defined.
550 /// This directly corresponds to the tokenized AsmString after the mnemonic is
551 /// removed.
552 SmallVector<AsmOperand, 8> AsmOperands;
553
554 /// Predicates - The required subtarget features to match this instruction.
555 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
556
557 /// ConversionFnKind - The enum value which is passed to the generated
558 /// convertToMCInst to convert parsed operands into an MCInst for this
559 /// function.
560 std::string ConversionFnKind;
561
562 /// If this instruction is deprecated in some form.
563 bool HasDeprecation = false;
564
565 /// If this is an alias, this is use to determine whether or not to using
566 /// the conversion function defined by the instruction's AsmMatchConverter
567 /// or to use the function generated by the alias.
568 bool UseInstAsmMatchConverter;
569
570 MatchableInfo(const CodeGenInstruction &CGI)
571 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef),
572 ResInstSize(TheDef->getValueAsInt(FieldName: "Size")), DefRec(&CGI),
573 UseInstAsmMatchConverter(true) {}
574
575 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
576 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
577 ResInstSize(Alias->ResultInst->TheDef->getValueAsInt(FieldName: "Size")),
578 DefRec(Alias.release()), UseInstAsmMatchConverter(TheDef->getValueAsBit(
579 FieldName: "UseInstAsmMatchConverter")) {}
580
581 // Could remove this and the dtor if PointerUnion supported unique_ptr
582 // elements with a dynamic failure/assertion (like the one below) in the case
583 // where it was copied while being in an owning state.
584 MatchableInfo(const MatchableInfo &RHS)
585 : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
586 TheDef(RHS.TheDef), ResInstSize(RHS.ResInstSize), DefRec(RHS.DefRec),
587 ResOperands(RHS.ResOperands), Mnemonic(RHS.Mnemonic),
588 AsmOperands(RHS.AsmOperands), RequiredFeatures(RHS.RequiredFeatures),
589 ConversionFnKind(RHS.ConversionFnKind),
590 HasDeprecation(RHS.HasDeprecation),
591 UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
592 assert(!isa<const CodeGenInstAlias *>(DefRec));
593 }
594
595 ~MatchableInfo() {
596 delete dyn_cast_if_present<const CodeGenInstAlias *>(Val&: DefRec);
597 }
598
599 // Two-operand aliases clone from the main matchable, but mark the second
600 // operand as a tied operand of the first for purposes of the assembler.
601 void formTwoOperandAlias(StringRef Constraint);
602
603 void initialize(const AsmMatcherInfo &Info,
604 SmallPtrSetImpl<const Record *> &SingletonRegisters,
605 AsmVariantInfo const &Variant, bool HasMnemonicFirst);
606
607 /// validate - Return true if this matchable is a valid thing to match against
608 /// and perform a bunch of validity checking.
609 bool validate(StringRef CommentDelimiter, bool IsAlias) const;
610
611 /// findAsmOperand - Find the AsmOperand with the specified name and
612 /// suboperand index.
613 int findAsmOperand(StringRef N, int SubOpIdx) const {
614 auto I = find_if(Range: AsmOperands, P: [&](const AsmOperand &Op) {
615 return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;
616 });
617 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
618 }
619
620 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
621 /// This does not check the suboperand index.
622 int findAsmOperandNamed(StringRef N, int LastIdx = -1) const {
623 auto I =
624 llvm::find_if(Range: llvm::drop_begin(RangeOrContainer: AsmOperands, N: LastIdx + 1),
625 P: [&](const AsmOperand &Op) { return Op.SrcOpName == N; });
626 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
627 }
628
629 int findAsmOperandOriginallyNamed(StringRef N) const {
630 auto I = find_if(Range: AsmOperands, P: [&](const AsmOperand &Op) {
631 return Op.OrigSrcOpName == N;
632 });
633 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
634 }
635
636 void buildInstructionResultOperands();
637 void buildAliasResultOperands(bool AliasConstraintsAreChecked);
638
639 /// shouldBeMatchedBefore - Compare two matchables for ordering.
640 bool shouldBeMatchedBefore(const MatchableInfo &RHS,
641 bool PreferSmallerInstructions) const {
642 // The primary comparator is the instruction mnemonic.
643 if (int Cmp = Mnemonic.compare_insensitive(RHS: RHS.Mnemonic))
644 return Cmp == -1;
645
646 // (Optionally) Order by the resultant instuctions size.
647 // eg. for ARM thumb instructions smaller encodings should be preferred.
648 if (PreferSmallerInstructions && ResInstSize != RHS.ResInstSize)
649 return ResInstSize < RHS.ResInstSize;
650
651 if (AsmOperands.size() != RHS.AsmOperands.size())
652 return AsmOperands.size() < RHS.AsmOperands.size();
653
654 // Compare lexicographically by operand. The matcher validates that other
655 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
656 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
657 if (*LHSOp.Class < *RHSOp.Class)
658 return true;
659 if (*RHSOp.Class < *LHSOp.Class)
660 return false;
661 }
662
663 // For X86 AVX/AVX512 instructions, we prefer vex encoding because the
664 // vex encoding size is smaller. Since X86InstrSSE.td is included ahead
665 // of X86InstrAVX512.td, the AVX instruction ID is less than AVX512 ID.
666 // We use the ID to sort AVX instruction before AVX512 instruction in
667 // matching table. As well as InstAlias.
668 if (getResultInst()->TheDef->isSubClassOf(Name: "Instruction") &&
669 getResultInst()->TheDef->getValueAsBit(FieldName: "HasPositionOrder") &&
670 RHS.getResultInst()->TheDef->isSubClassOf(Name: "Instruction") &&
671 RHS.getResultInst()->TheDef->getValueAsBit(FieldName: "HasPositionOrder"))
672 return getResultInst()->TheDef->getID() <
673 RHS.getResultInst()->TheDef->getID();
674
675 // Give matches that require more features higher precedence. This is useful
676 // because we cannot define AssemblerPredicates with the negation of
677 // processor features. For example, ARM v6 "nop" may be either a HINT or
678 // MOV. With v6, we want to match HINT. The assembler has no way to
679 // predicate MOV under "NoV6", but HINT will always match first because it
680 // requires V6 while MOV does not.
681 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
682 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
683
684 return false;
685 }
686
687 /// couldMatchAmbiguouslyWith - Check whether this matchable could
688 /// ambiguously match the same set of operands as \p RHS (without being a
689 /// strictly superior match).
690 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS,
691 bool PreferSmallerInstructions) const {
692 // The primary comparator is the instruction mnemonic.
693 if (Mnemonic != RHS.Mnemonic)
694 return false;
695
696 // Different variants can't conflict.
697 if (AsmVariantID != RHS.AsmVariantID)
698 return false;
699
700 // The size of instruction is unambiguous.
701 if (PreferSmallerInstructions && ResInstSize != RHS.ResInstSize)
702 return false;
703
704 // The number of operands is unambiguous.
705 if (AsmOperands.size() != RHS.AsmOperands.size())
706 return false;
707
708 // Otherwise, make sure the ordering of the two instructions is unambiguous
709 // by checking that either (a) a token or operand kind discriminates them,
710 // or (b) the ordering among equivalent kinds is consistent.
711
712 // Tokens and operand kinds are unambiguous (assuming a correct target
713 // specific parser).
714 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
715 if (LHSOp.Class->Kind != RHSOp.Class->Kind ||
716 LHSOp.Class->Kind == ClassInfo::Token)
717 if (*LHSOp.Class < *RHSOp.Class || *RHSOp.Class < *LHSOp.Class)
718 return false;
719 }
720
721 // Otherwise, this operand could commute if all operands are equivalent, or
722 // there is a pair of operands that compare less than and a pair that
723 // compare greater than.
724 bool HasLT = false, HasGT = false;
725 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
726 if (*LHSOp.Class < *RHSOp.Class)
727 HasLT = true;
728 if (*RHSOp.Class < *LHSOp.Class)
729 HasGT = true;
730 }
731
732 return HasLT == HasGT;
733 }
734
735 void dump() const;
736
737private:
738 void tokenizeAsmString(AsmMatcherInfo const &Info,
739 AsmVariantInfo const &Variant);
740 void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);
741};
742
743struct OperandMatchEntry {
744 unsigned OperandMask;
745 const MatchableInfo *MI;
746 ClassInfo *CI;
747
748 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
749 unsigned opMask) {
750 OperandMatchEntry X;
751 X.OperandMask = opMask;
752 X.CI = ci;
753 X.MI = mi;
754 return X;
755 }
756};
757
758class AsmMatcherInfo {
759public:
760 /// Tracked Records
761 const RecordKeeper &Records;
762
763 /// The tablegen AsmParser record.
764 const Record *AsmParser;
765
766 /// Target - The target information.
767 const CodeGenTarget &Target;
768
769 /// The classes which are needed for matching.
770 std::forward_list<ClassInfo> Classes;
771
772 /// The information on the matchables to match.
773 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
774
775 /// Info for custom matching operands by user defined methods.
776 std::vector<OperandMatchEntry> OperandMatchInfo;
777
778 /// Map of Register records to their class information.
779 using RegisterClassesTy =
780 std::map<const Record *, ClassInfo *, LessRecordByID>;
781 RegisterClassesTy RegisterClasses;
782
783 /// Map of Predicate records to their subtarget information.
784 SubtargetFeatureInfoMap SubtargetFeatures;
785
786 /// Map of AsmOperandClass records to their class information.
787 std::map<const Record *, ClassInfo *> AsmOperandClasses;
788
789 /// Map of RegisterClass records to their class information.
790 std::map<const Record *, ClassInfo *> RegisterClassClasses;
791
792private:
793 /// Map of token to class information which has already been constructed.
794 std::map<std::string, ClassInfo *> TokenClasses;
795
796private:
797 /// getTokenClass - Lookup or create the class for the given token.
798 ClassInfo *getTokenClass(StringRef Token, bool WantDiagnostic = false);
799
800 /// getOperandClass - Lookup or create the class for the given operand.
801 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
802 int SubOpIdx);
803 ClassInfo *getOperandClass(const Record *Rec, int SubOpIdx);
804
805 /// buildRegisterClasses - Build the ClassInfo* instances for register
806 /// classes.
807 void
808 buildRegisterClasses(SmallPtrSetImpl<const Record *> &SingletonRegisters);
809
810 /// buildOperandClasses - Build the ClassInfo* instances for user defined
811 /// operand classes.
812 void buildOperandClasses();
813
814 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
815 unsigned AsmOpIdx);
816 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
817 MatchableInfo::AsmOperand &Op);
818
819public:
820 AsmMatcherInfo(const Record *AsmParser, const CodeGenTarget &Target,
821 const RecordKeeper &Records);
822
823 /// Construct the various tables used during matching.
824 void buildInfo();
825
826 /// buildOperandMatchInfo - Build the necessary information to handle user
827 /// defined operand parsing methods.
828 void buildOperandMatchInfo();
829
830 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
831 /// given operand.
832 const SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const {
833 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
834 const auto &I = SubtargetFeatures.find(x: Def);
835 return I == SubtargetFeatures.end() ? nullptr : &I->second;
836 }
837
838 const RecordKeeper &getRecords() const { return Records; }
839
840 bool hasOptionalOperands() const {
841 return any_of(Range: Classes,
842 P: [](const ClassInfo &Class) { return Class.IsOptional; });
843 }
844};
845
846} // end anonymous namespace
847
848#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
849LLVM_DUMP_METHOD void MatchableInfo::dump() const {
850 errs() << TheDef->getName() << " -- "
851 << "flattened:\"" << AsmString << "\"\n";
852
853 errs() << " variant: " << AsmVariantID << "\n";
854
855 for (const auto &[Idx, Op] : enumerate(AsmOperands)) {
856 errs() << " op[" << Idx << "] = " << Op.Class->ClassName << " - ";
857 errs() << '\"' << Op.Token << "\"\n";
858 }
859}
860#endif
861
862static std::pair<StringRef, StringRef>
863parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
864 // Trim whitespace and the leading '$' on the operand names.
865 auto TrimWSDollar = [Loc](StringRef OpName) {
866 OpName = OpName.trim(Chars: " \t");
867 if (!OpName.consume_front(Prefix: "$"))
868 PrintFatalError(ErrorLoc: Loc, Msg: "expected '$' prefix on asm operand name");
869 return OpName;
870 };
871
872 // Split via the '='.
873 auto [Src, Dst] = S.split(Separator: '=');
874 if (Dst == "")
875 PrintFatalError(ErrorLoc: Loc, Msg: "missing '=' in two-operand alias constraint");
876 return {TrimWSDollar(Src), TrimWSDollar(Dst)};
877}
878
879void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
880 // Figure out which operands are aliased and mark them as tied.
881 auto [Src, Dst] = parseTwoOperandConstraint(S: Constraint, Loc: TheDef->getLoc());
882
883 // Find the AsmOperands that refer to the operands we're aliasing.
884 int SrcAsmOperand = findAsmOperandNamed(N: Src);
885 int DstAsmOperand = findAsmOperandNamed(N: Dst);
886 if (SrcAsmOperand == -1)
887 PrintFatalError(ErrorLoc: TheDef->getLoc(),
888 Msg: "unknown source two-operand alias operand '" + Src + "'.");
889 if (DstAsmOperand == -1)
890 PrintFatalError(ErrorLoc: TheDef->getLoc(),
891 Msg: "unknown destination two-operand alias operand '" + Dst +
892 "'.");
893
894 // Find the ResOperand that refers to the operand we're aliasing away
895 // and update it to refer to the combined operand instead.
896 for (ResOperand &Op : ResOperands) {
897 if (Op.Kind == ResOperand::RenderAsmOperand &&
898 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
899 Op.AsmOperandNum = DstAsmOperand;
900 break;
901 }
902 }
903 // Remove the AsmOperand for the alias operand.
904 AsmOperands.erase(CI: AsmOperands.begin() + SrcAsmOperand);
905 // Adjust the ResOperand references to any AsmOperands that followed
906 // the one we just deleted.
907 for (ResOperand &Op : ResOperands) {
908 if (Op.Kind == ResOperand::RenderAsmOperand &&
909 Op.AsmOperandNum > (unsigned)SrcAsmOperand)
910 --Op.AsmOperandNum;
911 }
912}
913
914/// extractSingletonRegisterForAsmOperand - Extract singleton register,
915/// if present, from specified token.
916static void extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
917 const AsmMatcherInfo &Info,
918 StringRef RegisterPrefix) {
919 StringRef Tok = Op.Token;
920
921 // If this token is not an isolated token, i.e., it isn't separated from
922 // other tokens (e.g. with whitespace), don't interpret it as a register name.
923 if (!Op.IsIsolatedToken)
924 return;
925
926 if (RegisterPrefix.empty()) {
927 std::string LoweredTok = Tok.lower();
928 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(Name: LoweredTok))
929 Op.SingletonReg = Reg->TheDef;
930 return;
931 }
932
933 if (!Tok.consume_front(Prefix: RegisterPrefix))
934 return;
935
936 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(Name: Tok))
937 Op.SingletonReg = Reg->TheDef;
938
939 // If there is no register prefix (i.e. "%" in "%eax"), then this may
940 // be some random non-register token, just ignore it.
941}
942
943void MatchableInfo::initialize(
944 const AsmMatcherInfo &Info,
945 SmallPtrSetImpl<const Record *> &SingletonRegisters,
946 AsmVariantInfo const &Variant, bool HasMnemonicFirst) {
947 AsmVariantID = Variant.AsmVariantNo;
948 AsmString = CodeGenInstruction::FlattenAsmStringVariants(
949 AsmString, Variant: Variant.AsmVariantNo);
950
951 tokenizeAsmString(Info, Variant);
952
953 // The first token of the instruction is the mnemonic, which must be a
954 // simple string, not a $foo variable or a singleton register.
955 if (AsmOperands.empty())
956 PrintFatalError(ErrorLoc: TheDef->getLoc(),
957 Msg: "Instruction '" + TheDef->getName() + "' has no tokens");
958
959 assert(!AsmOperands[0].Token.empty());
960 if (HasMnemonicFirst) {
961 Mnemonic = AsmOperands[0].Token;
962 if (Mnemonic[0] == '$')
963 PrintFatalError(ErrorLoc: TheDef->getLoc(),
964 Msg: "Invalid instruction mnemonic '" + Mnemonic + "'!");
965
966 // Remove the first operand, it is tracked in the mnemonic field.
967 AsmOperands.erase(CI: AsmOperands.begin());
968 } else if (AsmOperands[0].Token[0] != '$')
969 Mnemonic = AsmOperands[0].Token;
970
971 // Compute the require features.
972 for (const Record *Predicate : TheDef->getValueAsListOfDefs(FieldName: "Predicates"))
973 if (const SubtargetFeatureInfo *Feature =
974 Info.getSubtargetFeature(Def: Predicate))
975 RequiredFeatures.push_back(Elt: Feature);
976
977 // Collect singleton registers, if used.
978 for (MatchableInfo::AsmOperand &Op : AsmOperands) {
979 extractSingletonRegisterForAsmOperand(Op, Info, RegisterPrefix: Variant.RegisterPrefix);
980 if (Op.SingletonReg)
981 SingletonRegisters.insert(Ptr: Op.SingletonReg);
982 }
983
984 const RecordVal *DepMask = TheDef->getValue(Name: "DeprecatedFeatureMask");
985 if (!DepMask)
986 DepMask = TheDef->getValue(Name: "ComplexDeprecationPredicate");
987
988 HasDeprecation =
989 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
990}
991
992/// Append an AsmOperand for the given substring of AsmString.
993void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {
994 AsmOperands.push_back(Elt: AsmOperand(IsIsolatedToken, Token));
995}
996
997/// tokenizeAsmString - Tokenize a simplified assembly string.
998void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
999 AsmVariantInfo const &Variant) {
1000 StringRef String = AsmString;
1001 size_t Prev = 0;
1002 bool InTok = false;
1003 bool IsIsolatedToken = true;
1004 for (size_t i = 0, e = String.size(); i != e; ++i) {
1005 char Char = String[i];
1006 if (Variant.BreakCharacters.contains(C: Char)) {
1007 if (InTok) {
1008 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken: false);
1009 Prev = i;
1010 IsIsolatedToken = false;
1011 }
1012 InTok = true;
1013 continue;
1014 }
1015 if (Variant.TokenizingCharacters.contains(C: Char)) {
1016 if (InTok) {
1017 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1018 InTok = false;
1019 IsIsolatedToken = false;
1020 }
1021 addAsmOperand(Token: String.substr(Start: i, N: 1), IsIsolatedToken);
1022 Prev = i + 1;
1023 IsIsolatedToken = true;
1024 continue;
1025 }
1026 if (Variant.SeparatorCharacters.contains(C: Char)) {
1027 if (InTok) {
1028 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1029 InTok = false;
1030 }
1031 Prev = i + 1;
1032 IsIsolatedToken = true;
1033 continue;
1034 }
1035
1036 switch (Char) {
1037 case '\\':
1038 if (InTok) {
1039 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken: false);
1040 InTok = false;
1041 IsIsolatedToken = false;
1042 }
1043 ++i;
1044 assert(i != String.size() && "Invalid quoted character");
1045 addAsmOperand(Token: String.substr(Start: i, N: 1), IsIsolatedToken);
1046 Prev = i + 1;
1047 IsIsolatedToken = false;
1048 break;
1049
1050 case '$': {
1051 if (InTok) {
1052 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1053 InTok = false;
1054 IsIsolatedToken = false;
1055 }
1056
1057 // If this isn't "${", start new identifier looking like "$xxx"
1058 if (i + 1 == String.size() || String[i + 1] != '{') {
1059 Prev = i;
1060 break;
1061 }
1062
1063 size_t EndPos = String.find(C: '}', From: i);
1064 assert(EndPos != StringRef::npos &&
1065 "Missing brace in operand reference!");
1066 addAsmOperand(Token: String.substr(Start: i, N: EndPos + 1 - i), IsIsolatedToken);
1067 Prev = EndPos + 1;
1068 i = EndPos;
1069 IsIsolatedToken = false;
1070 break;
1071 }
1072
1073 default:
1074 InTok = true;
1075 break;
1076 }
1077 }
1078 if (InTok && Prev != String.size())
1079 addAsmOperand(Token: String.substr(Start: Prev), IsIsolatedToken);
1080}
1081
1082bool MatchableInfo::validate(StringRef CommentDelimiter, bool IsAlias) const {
1083 // Reject matchables with no .s string.
1084 if (AsmString.empty())
1085 PrintFatalError(ErrorLoc: TheDef->getLoc(), Msg: "instruction with empty asm string");
1086
1087 // Reject any matchables with a newline in them, they should be marked
1088 // isCodeGenOnly if they are pseudo instructions.
1089 if (AsmString.find(c: '\n') != std::string::npos)
1090 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1091 Msg: "multiline instruction is not valid for the asmparser, "
1092 "mark it isCodeGenOnly");
1093
1094 // Remove comments from the asm string. We know that the asmstring only
1095 // has one line.
1096 if (!CommentDelimiter.empty() &&
1097 StringRef(AsmString).contains(Other: CommentDelimiter))
1098 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1099 Msg: "asmstring for instruction has comment character in it, "
1100 "mark it isCodeGenOnly");
1101
1102 // Reject matchables with operand modifiers, these aren't something we can
1103 // handle, the target should be refactored to use operands instead of
1104 // modifiers.
1105 //
1106 // Also, check for instructions which reference the operand multiple times,
1107 // if they don't define a custom AsmMatcher: this implies a constraint that
1108 // the built-in matching code would not honor.
1109 std::set<std::string> OperandNames;
1110 for (const AsmOperand &Op : AsmOperands) {
1111 StringRef Tok = Op.Token;
1112 if (Tok[0] == '$' && Tok.contains(C: ':'))
1113 PrintFatalError(
1114 ErrorLoc: TheDef->getLoc(),
1115 Msg: "matchable with operand modifier '" + Tok +
1116 "' not supported by asm matcher. Mark isCodeGenOnly!");
1117 // Verify that any operand is only mentioned once.
1118 // We reject aliases and ignore instructions for now.
1119 if (!IsAlias && TheDef->getValueAsString(FieldName: "AsmMatchConverter").empty() &&
1120 Tok[0] == '$' && !OperandNames.insert(x: Tok.str()).second) {
1121 LLVM_DEBUG({
1122 errs() << "warning: '" << TheDef->getName() << "': "
1123 << "ignoring instruction with tied operand '" << Tok << "'\n";
1124 });
1125 return false;
1126 }
1127 }
1128
1129 return true;
1130}
1131
1132static std::string getEnumNameForToken(StringRef Str) {
1133 std::string Res;
1134
1135 for (char C : Str) {
1136 switch (C) {
1137 case '*':
1138 Res += "_STAR_";
1139 break;
1140 case '%':
1141 Res += "_PCT_";
1142 break;
1143 case ':':
1144 Res += "_COLON_";
1145 break;
1146 case '!':
1147 Res += "_EXCLAIM_";
1148 break;
1149 case '.':
1150 Res += "_DOT_";
1151 break;
1152 case '<':
1153 Res += "_LT_";
1154 break;
1155 case '>':
1156 Res += "_GT_";
1157 break;
1158 case '-':
1159 Res += "_MINUS_";
1160 break;
1161 case '#':
1162 Res += "_HASH_";
1163 break;
1164 default:
1165 if (isAlnum(C))
1166 Res += C;
1167 else
1168 Res += "_" + utostr(X: (unsigned)C) + "_";
1169 }
1170 }
1171
1172 return Res;
1173}
1174
1175ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token, bool WantDiagnostic) {
1176 ClassInfo *&Entry = TokenClasses[Token.str()];
1177
1178 if (!Entry) {
1179 Classes.emplace_front();
1180 Entry = &Classes.front();
1181 Entry->Kind = ClassInfo::Token;
1182 Entry->ClassName = "Token";
1183 Entry->Name = "MCK_" + getEnumNameForToken(Str: Token);
1184 Entry->ValueName = Token.str();
1185 Entry->PredicateMethod = "<invalid>";
1186 Entry->RenderMethod = "<invalid>";
1187 Entry->ParserMethod = "";
1188 Entry->DiagnosticType = "";
1189 Entry->IsOptional = false;
1190 Entry->DefaultMethod = "<invalid>";
1191 }
1192
1193 // Outside the creation block so a later WantDiagnostic=true call can
1194 // update an entry first created with WantDiagnostic=false.
1195 if (WantDiagnostic && Entry->DiagnosticType.empty() &&
1196 AsmParser->getValueAsBit(FieldName: "EmitTokenDiagnosticTypes")) {
1197 Entry->DiagnosticType = "InvalidToken" + getEnumNameForToken(Str: Token);
1198 Entry->DiagnosticString = "expected '" + Token.str() + "'";
1199 }
1200
1201 return Entry;
1202}
1203
1204ClassInfo *
1205AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1206 int SubOpIdx) {
1207 const Record *Rec = OI.Rec;
1208 if (SubOpIdx != -1)
1209 Rec = cast<DefInit>(Val: OI.MIOperandInfo->getArg(Num: SubOpIdx))->getDef();
1210 return getOperandClass(Rec, SubOpIdx);
1211}
1212
1213ClassInfo *AsmMatcherInfo::getOperandClass(const Record *Rec, int SubOpIdx) {
1214 if (Rec->isSubClassOf(Name: "RegisterOperand")) {
1215 // RegisterOperand may have an associated ParserMatchClass. If it does,
1216 // use it, else just fall back to the underlying register class.
1217 const RecordVal *R = Rec->getValue(Name: "ParserMatchClass");
1218 if (!R || !R->getValue())
1219 PrintFatalError(ErrorLoc: Rec->getLoc(),
1220 Msg: "Record `" + Rec->getName() +
1221 "' does not have a ParserMatchClass!\n");
1222
1223 if (const DefInit *DI = dyn_cast<DefInit>(Val: R->getValue())) {
1224 const Record *MatchClass = DI->getDef();
1225 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1226 return CI;
1227 }
1228
1229 // No custom match class. Just use the register class.
1230 const Record *ClassRec = Rec->getValueAsDef(FieldName: "RegClass");
1231 if (!ClassRec)
1232 PrintFatalError(ErrorLoc: Rec->getLoc(),
1233 Msg: "RegisterOperand `" + Rec->getName() +
1234 "' has no associated register class!\n");
1235
1236 if (ClassRec->isSubClassOf(Name: "RegisterClassLike")) {
1237 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1238 return CI;
1239
1240 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1241 }
1242 }
1243
1244 if (Rec->isSubClassOf(Name: "RegisterClass")) {
1245 if (ClassInfo *CI = RegisterClassClasses[Rec])
1246 return CI;
1247 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1248 }
1249
1250 if (Rec->isSubClassOf(Name: "Operand")) {
1251 const Record *MatchClass = Rec->getValueAsDef(FieldName: "ParserMatchClass");
1252 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1253 return CI;
1254 } else if (Rec->isSubClassOf(Name: "RegisterClassLike")) {
1255 if (ClassInfo *CI = RegisterClassClasses[Rec])
1256 return CI;
1257 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1258 } else {
1259 PrintFatalError(ErrorLoc: Rec->getLoc(),
1260 Msg: "Operand `" + Rec->getName() +
1261 "' does not derive from class Operand!\n");
1262 }
1263
1264 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "operand has no match class!");
1265}
1266
1267// Comparator for RegisterSets (BitVectors). Lexicographically compares the
1268// sorted sequence of register IDs present in each set to ensure deterministic
1269// ordering of RegisterSets in std::set and std::map.
1270struct LessRegisterSet {
1271 bool operator()(const RegisterSet &LHS, const RegisterSet &RHS) const {
1272 int L = LHS.find_first();
1273 int R = RHS.find_first();
1274 while (L != -1 && R != -1) {
1275 if (L != R)
1276 return L < R;
1277 L = LHS.find_next(Prev: L);
1278 R = RHS.find_next(Prev: R);
1279 }
1280 return L == -1 && R != -1;
1281 }
1282};
1283
1284// Map each register to a dense bit index ordered by LessRecordByID so that
1285// bit index order matches LessRecordByID order in LessRegisterSet.
1286static DenseMap<const Record *, unsigned>
1287createRegisterIndexMap(const std::deque<CodeGenRegister> &Registers) {
1288 std::vector<const Record *> AllRegDefs;
1289 AllRegDefs.reserve(n: Registers.size());
1290 for (const CodeGenRegister &CGR : Registers)
1291 AllRegDefs.push_back(x: CGR.TheDef);
1292 llvm::sort(C&: AllRegDefs, Comp: LessRecordByID());
1293
1294 DenseMap<const Record *, unsigned> IndexMap;
1295 IndexMap.reserve(NumEntries: AllRegDefs.size());
1296 for (const auto &[I, RegDef] : llvm::enumerate(First&: AllRegDefs))
1297 IndexMap[RegDef] = I;
1298 return IndexMap;
1299}
1300
1301void AsmMatcherInfo::buildRegisterClasses(
1302 SmallPtrSetImpl<const Record *> &SingletonRegisters) {
1303 const auto &Registers = Target.getRegBank().getRegisters();
1304 auto &RegClassList = Target.getRegBank().getRegClasses();
1305
1306 const DenseMap<const Record *, unsigned> RegIndexMap =
1307 createRegisterIndexMap(Registers);
1308
1309 // Helper to build a BitVector representing a set of register records.
1310 unsigned NumRegs = Registers.size();
1311 auto MakeRegisterSet = [&](ArrayRef<const Record *> Regs) {
1312 BitVector BS(NumRegs);
1313 for (const Record *Rec : Regs) {
1314 auto It = RegIndexMap.find(Val: Rec);
1315 assert(It != RegIndexMap.end() && "Unknown register record");
1316 BS.set(It->second);
1317 }
1318 return BS;
1319 };
1320
1321 using RegisterSetSet = std::set<RegisterSet, LessRegisterSet>;
1322
1323 // The register sets used for matching.
1324 RegisterSetSet RegisterSets;
1325
1326 // Gather the defined sets.
1327 for (const CodeGenRegisterClass &RC : RegClassList)
1328 RegisterSets.insert(x: MakeRegisterSet(RC.getOrder()));
1329
1330 // Add any required singleton sets.
1331 for (const Record *Rec : SingletonRegisters)
1332 RegisterSets.insert(x: MakeRegisterSet({Rec}));
1333
1334 // Introduce derived sets where necessary (when a register does not determine
1335 // a unique register set class), and build the mapping of registers to the set
1336 // they should classify to.
1337 std::map<const Record *, RegisterSet> RegisterMap;
1338 for (const CodeGenRegister &CGR : Registers) {
1339 // Compute the intersection of all sets containing this register.
1340 RegisterSet ContainingSet;
1341 unsigned RegIdx = RegIndexMap.lookup(Val: CGR.TheDef);
1342
1343 for (const RegisterSet &RS : RegisterSets) {
1344 if (!RS.test(Idx: RegIdx))
1345 continue;
1346
1347 if (ContainingSet.empty()) {
1348 ContainingSet = RS;
1349 continue;
1350 }
1351
1352 ContainingSet &= RS;
1353 }
1354
1355 if (ContainingSet.any()) {
1356 RegisterSets.insert(x: ContainingSet);
1357 RegisterMap.try_emplace(k: CGR.TheDef, args&: ContainingSet);
1358 }
1359 }
1360
1361 // Construct the register classes.
1362 std::map<RegisterSet, ClassInfo *, LessRegisterSet> RegisterSetClasses;
1363 unsigned Index = 0;
1364 for (const RegisterSet &RS : RegisterSets) {
1365 Classes.emplace_front();
1366 ClassInfo *CI = &Classes.front();
1367 CI->Kind = ClassInfo::RegisterClass0 + Index;
1368 CI->ClassName = "Reg" + utostr(X: Index);
1369 CI->Name = "MCK_Reg" + utostr(X: Index);
1370 CI->ValueName = "";
1371 CI->PredicateMethod = ""; // unused
1372 CI->RenderMethod = "addRegOperands";
1373 CI->Registers = RS;
1374 // FIXME: diagnostic type.
1375 CI->DiagnosticType = "";
1376 CI->IsOptional = false;
1377 CI->DefaultMethod = ""; // unused
1378 RegisterSetClasses.try_emplace(k: RS, args&: CI);
1379 ++Index;
1380 assert(CI->isRegisterClass());
1381 }
1382
1383 // Find the superclasses; we could compute only the subgroup lattice edges,
1384 // but there isn't really a point.
1385 for (const RegisterSet &RS : RegisterSets) {
1386 ClassInfo *CI = RegisterSetClasses[RS];
1387 for (const RegisterSet &RS2 : RegisterSets)
1388 if (RS != RS2 && RS.subsetOf(RHS: RS2))
1389 CI->SuperClasses.push_back(x: RegisterSetClasses[RS2]);
1390 }
1391
1392 // Name the register classes which correspond to a user defined RegisterClass.
1393 for (const CodeGenRegisterClass &RC : RegClassList) {
1394 // Def will be NULL for non-user defined register classes.
1395 const Record *Def = RC.getDef();
1396 if (!Def)
1397 continue;
1398 ClassInfo *CI = RegisterSetClasses[MakeRegisterSet(RC.getOrder())];
1399 if (CI->ValueName.empty()) {
1400 CI->ClassName = RC.getName();
1401 CI->Name = "MCK_" + RC.getName();
1402 CI->ValueName = RC.getName();
1403 } else {
1404 CI->ValueName = CI->ValueName + "," + RC.getName();
1405 }
1406
1407 const Init *DiagnosticType = Def->getValueInit(FieldName: "DiagnosticType");
1408 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticType))
1409 CI->DiagnosticType = SI->getValue().str();
1410
1411 const Init *DiagnosticString = Def->getValueInit(FieldName: "DiagnosticString");
1412 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticString))
1413 CI->DiagnosticString = SI->getValue().str();
1414
1415 // If we have a diagnostic string but the diagnostic type is not specified
1416 // explicitly, create an anonymous diagnostic type.
1417 if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1418 CI->DiagnosticType = RC.getName();
1419
1420 RegisterClassClasses.try_emplace(k: Def, args&: CI);
1421 assert(CI->isRegisterClass());
1422 }
1423
1424 unsigned RegClassByHwModeIndex = 0;
1425 for (const Record *ClassByHwMode : Target.getAllRegClassByHwMode()) {
1426 ClassInfo &CI = Classes.emplace_front();
1427 CI.Kind = ClassInfo::RegisterClassByHwMode0 + RegClassByHwModeIndex;
1428
1429 CI.ClassName = "RegByHwMode_" + ClassByHwMode->getName().str();
1430 CI.Name = "MCK_" + CI.ClassName;
1431 CI.ValueName = ClassByHwMode->getName();
1432 CI.RenderMethod = "addRegOperands";
1433 // FIXME: Set diagnostic type.
1434 ++RegClassByHwModeIndex;
1435
1436 assert(CI.isRegisterClassByHwMode());
1437
1438 RegisterClassClasses.try_emplace(k: ClassByHwMode, args: &CI);
1439 }
1440
1441 // Populate the map for individual registers.
1442 for (auto &It : RegisterMap)
1443 RegisterClasses[It.first] = RegisterSetClasses[It.second];
1444
1445 // Name the register classes which correspond to singleton registers.
1446 for (const Record *Rec : SingletonRegisters) {
1447 ClassInfo *CI = RegisterClasses[Rec];
1448 assert(CI && "Missing singleton register class info!");
1449
1450 if (CI->ValueName.empty()) {
1451 CI->ClassName = Rec->getName().str();
1452 CI->Name = "MCK_" + Rec->getName().str();
1453 CI->ValueName = Rec->getName().str();
1454 } else {
1455 CI->ValueName = CI->ValueName + "," + Rec->getName().str();
1456 }
1457 }
1458}
1459
1460void AsmMatcherInfo::buildOperandClasses() {
1461 ArrayRef<const Record *> AsmOperands =
1462 Records.getAllDerivedDefinitions(ClassName: "AsmOperandClass");
1463
1464 // Pre-populate AsmOperandClasses map.
1465 for (const Record *Rec : AsmOperands) {
1466 Classes.emplace_front();
1467 AsmOperandClasses[Rec] = &Classes.front();
1468 }
1469
1470 unsigned Index = 0;
1471 for (const Record *Rec : AsmOperands) {
1472 ClassInfo *CI = AsmOperandClasses[Rec];
1473 CI->Kind = ClassInfo::UserClass0 + Index;
1474
1475 const ListInit *Supers = Rec->getValueAsListInit(FieldName: "SuperClasses");
1476 for (const Init *I : Supers->getElements()) {
1477 const DefInit *DI = dyn_cast<DefInit>(Val: I);
1478 if (!DI) {
1479 PrintError(ErrorLoc: Rec->getLoc(), Msg: "Invalid super class reference!");
1480 continue;
1481 }
1482
1483 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1484 if (!SC)
1485 PrintError(ErrorLoc: Rec->getLoc(), Msg: "Invalid super class reference!");
1486 else
1487 CI->SuperClasses.push_back(x: SC);
1488 }
1489 CI->ClassName = Rec->getValueAsString(FieldName: "Name").str();
1490 CI->Name = "MCK_" + CI->ClassName;
1491 CI->ValueName = Rec->getName().str();
1492
1493 // Get or construct the predicate method name.
1494 const Init *PMName = Rec->getValueInit(FieldName: "PredicateMethod");
1495 if (const StringInit *SI = dyn_cast<StringInit>(Val: PMName)) {
1496 CI->PredicateMethod = SI->getValue().str();
1497 } else {
1498 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1499 CI->PredicateMethod = "is" + CI->ClassName;
1500 }
1501
1502 // Get or construct the render method name.
1503 const Init *RMName = Rec->getValueInit(FieldName: "RenderMethod");
1504 if (const StringInit *SI = dyn_cast<StringInit>(Val: RMName)) {
1505 CI->RenderMethod = SI->getValue().str();
1506 } else {
1507 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1508 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1509 }
1510
1511 // Get the parse method name or leave it as empty.
1512 const Init *PRMName = Rec->getValueInit(FieldName: "ParserMethod");
1513 if (const StringInit *SI = dyn_cast<StringInit>(Val: PRMName))
1514 CI->ParserMethod = SI->getValue().str();
1515
1516 // Get the diagnostic type and string or leave them as empty.
1517 const Init *DiagnosticType = Rec->getValueInit(FieldName: "DiagnosticType");
1518 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticType))
1519 CI->DiagnosticType = SI->getValue().str();
1520 const Init *DiagnosticString = Rec->getValueInit(FieldName: "DiagnosticString");
1521 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticString))
1522 CI->DiagnosticString = SI->getValue().str();
1523 // If we have a DiagnosticString, we need a DiagnosticType for use within
1524 // the matcher.
1525 if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1526 CI->DiagnosticType = CI->ClassName;
1527
1528 const Init *IsOptional = Rec->getValueInit(FieldName: "IsOptional");
1529 if (const BitInit *BI = dyn_cast<BitInit>(Val: IsOptional))
1530 CI->IsOptional = BI->getValue();
1531
1532 // Get or construct the default method name.
1533 const Init *DMName = Rec->getValueInit(FieldName: "DefaultMethod");
1534 if (const StringInit *SI = dyn_cast<StringInit>(Val: DMName)) {
1535 CI->DefaultMethod = SI->getValue().str();
1536 } else {
1537 assert(isa<UnsetInit>(DMName) && "Unexpected DefaultMethod field!");
1538 CI->DefaultMethod = "default" + CI->ClassName + "Operands";
1539 }
1540
1541 ++Index;
1542 }
1543}
1544
1545AsmMatcherInfo::AsmMatcherInfo(const Record *asmParser,
1546 const CodeGenTarget &target,
1547 const RecordKeeper &records)
1548 : Records(records), AsmParser(asmParser), Target(target) {}
1549
1550/// buildOperandMatchInfo - Build the necessary information to handle user
1551/// defined operand parsing methods.
1552void AsmMatcherInfo::buildOperandMatchInfo() {
1553 /// Map containing a mask with all operands indices that can be found for
1554 /// that class inside a instruction.
1555 using OpClassMaskTy = std::map<ClassInfo *, unsigned, deref<std::less<>>>;
1556 OpClassMaskTy OpClassMask;
1557
1558 bool CallCustomParserForAllOperands =
1559 AsmParser->getValueAsBit(FieldName: "CallCustomParserForAllOperands");
1560 for (const auto &MI : Matchables) {
1561 OpClassMask.clear();
1562
1563 // Keep track of all operands of this instructions which belong to the
1564 // same class.
1565 unsigned NumOptionalOps = 0;
1566 for (const auto &[Idx, Op] : enumerate(First&: MI->AsmOperands)) {
1567 if (CallCustomParserForAllOperands || !Op.Class->ParserMethod.empty()) {
1568 unsigned &OperandMask = OpClassMask[Op.Class];
1569 OperandMask |= maskTrailingOnes<unsigned>(N: NumOptionalOps + 1)
1570 << (Idx - NumOptionalOps);
1571 }
1572 if (Op.Class->IsOptional)
1573 ++NumOptionalOps;
1574 }
1575
1576 // Generate operand match info for each mnemonic/operand class pair.
1577 for (const auto [CI, OpMask] : OpClassMask) {
1578 OperandMatchInfo.push_back(
1579 x: OperandMatchEntry::create(mi: MI.get(), ci: CI, opMask: OpMask));
1580 }
1581 }
1582}
1583
1584void AsmMatcherInfo::buildInfo() {
1585 // Build information about all of the AssemblerPredicates.
1586 SubtargetFeaturesInfoVec SubtargetFeaturePairs =
1587 SubtargetFeatureInfo::getAll(Records);
1588 SubtargetFeatures.insert(first: SubtargetFeaturePairs.begin(),
1589 last: SubtargetFeaturePairs.end());
1590#ifndef NDEBUG
1591 for (const auto &Pair : SubtargetFeatures)
1592 LLVM_DEBUG(Pair.second.dump());
1593#endif // NDEBUG
1594
1595 bool HasMnemonicFirst = AsmParser->getValueAsBit(FieldName: "HasMnemonicFirst");
1596 bool ReportMultipleNearMisses =
1597 AsmParser->getValueAsBit(FieldName: "ReportMultipleNearMisses");
1598
1599 // Parse the instructions; we need to do this first so that we can gather the
1600 // singleton register classes.
1601 SmallPtrSet<const Record *, 16> SingletonRegisters;
1602 unsigned VariantCount = Target.getAsmParserVariantCount();
1603 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1604 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
1605 StringRef CommentDelimiter =
1606 AsmVariant->getValueAsString(FieldName: "CommentDelimiter");
1607 AsmVariantInfo Variant;
1608 Variant.RegisterPrefix = AsmVariant->getValueAsString(FieldName: "RegisterPrefix");
1609 Variant.TokenizingCharacters =
1610 AsmVariant->getValueAsString(FieldName: "TokenizingCharacters");
1611 Variant.SeparatorCharacters =
1612 AsmVariant->getValueAsString(FieldName: "SeparatorCharacters");
1613 Variant.BreakCharacters = AsmVariant->getValueAsString(FieldName: "BreakCharacters");
1614 Variant.Name = AsmVariant->getValueAsString(FieldName: "Name");
1615 Variant.AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
1616
1617 for (const CodeGenInstruction *CGI : Target.getInstructions()) {
1618 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1619 // filter the set of instructions we consider.
1620 if (!CGI->getName().starts_with(Prefix: MatchPrefix))
1621 continue;
1622
1623 // Ignore "codegen only" instructions.
1624 if (CGI->isCodeGenOnly)
1625 continue;
1626
1627 // Ignore instructions for different instructions
1628 StringRef V = CGI->TheDef->getValueAsString(FieldName: "AsmVariantName");
1629 if (!V.empty() && V != Variant.Name)
1630 continue;
1631
1632 auto II = std::make_unique<MatchableInfo>(args: *CGI);
1633
1634 II->initialize(Info: *this, SingletonRegisters, Variant, HasMnemonicFirst);
1635
1636 // Ignore instructions which shouldn't be matched and diagnose invalid
1637 // instruction definitions with an error.
1638 if (!II->validate(CommentDelimiter, IsAlias: false))
1639 continue;
1640
1641 Matchables.push_back(x: std::move(II));
1642 }
1643
1644 // Parse all of the InstAlias definitions and stick them in the list of
1645 // matchables.
1646 for (const Record *InstAlias :
1647 Records.getAllDerivedDefinitions(ClassName: "InstAlias")) {
1648 auto Alias = std::make_unique<CodeGenInstAlias>(args&: InstAlias, args: Target);
1649
1650 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1651 // filter the set of instruction aliases we consider, based on the target
1652 // instruction.
1653 if (!Alias->ResultInst->getName().starts_with(Prefix: MatchPrefix))
1654 continue;
1655
1656 StringRef V = Alias->TheDef->getValueAsString(FieldName: "AsmVariantName");
1657 if (!V.empty() && V != Variant.Name)
1658 continue;
1659
1660 auto II = std::make_unique<MatchableInfo>(args: std::move(Alias));
1661
1662 II->initialize(Info: *this, SingletonRegisters, Variant, HasMnemonicFirst);
1663
1664 // Validate the alias definitions.
1665 II->validate(CommentDelimiter, IsAlias: true);
1666
1667 Matchables.push_back(x: std::move(II));
1668 }
1669 }
1670
1671 // Build info for the register classes.
1672 buildRegisterClasses(SingletonRegisters);
1673
1674 // Build info for the user defined assembly operand classes.
1675 buildOperandClasses();
1676
1677 // Build the information about matchables, now that we have fully formed
1678 // classes.
1679 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1680 for (auto &II : Matchables) {
1681 // Parse the tokens after the mnemonic.
1682 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1683 // don't precompute the loop bound, i.e., cannot use range based for loop
1684 // here.
1685 for (size_t Idx = 0; Idx < II->AsmOperands.size(); ++Idx) {
1686 MatchableInfo::AsmOperand &Op = II->AsmOperands[Idx];
1687 StringRef Token = Op.Token;
1688 // Check for singleton registers.
1689 if (const Record *RegRecord = Op.SingletonReg) {
1690 Op.Class = RegisterClasses[RegRecord];
1691 assert(Op.Class && Op.Class->Registers.count() == 1 &&
1692 "Unexpected class for singleton register");
1693 continue;
1694 }
1695
1696 // Check for simple tokens.
1697 if (Token[0] != '$') {
1698 Op.Class = getTokenClass(Token, /*WantDiagnostic=*/true);
1699 continue;
1700 }
1701
1702 if (Token.size() > 1 && isdigit(Token[1])) {
1703 Op.Class = getTokenClass(Token);
1704 continue;
1705 }
1706
1707 // Otherwise this is an operand reference.
1708 StringRef OperandName;
1709 if (Token[1] == '{')
1710 OperandName = Token.substr(Start: 2, N: Token.size() - 3);
1711 else
1712 OperandName = Token.substr(Start: 1);
1713
1714 if (isa<const CodeGenInstruction *>(Val: II->DefRec))
1715 buildInstructionOperandReference(II: II.get(), OpName: OperandName, AsmOpIdx: Idx);
1716 else
1717 buildAliasOperandReference(II: II.get(), OpName: OperandName, Op);
1718 }
1719
1720 if (isa<const CodeGenInstruction *>(Val: II->DefRec)) {
1721 II->buildInstructionResultOperands();
1722 // If the instruction has a two-operand alias, build up the
1723 // matchable here. We'll add them in bulk at the end to avoid
1724 // confusing this loop.
1725 StringRef Constraint =
1726 II->TheDef->getValueAsString(FieldName: "TwoOperandAliasConstraint");
1727 if (Constraint != "") {
1728 // Start by making a copy of the original matchable.
1729 auto AliasII = std::make_unique<MatchableInfo>(args&: *II);
1730
1731 // Adjust it to be a two-operand alias.
1732 AliasII->formTwoOperandAlias(Constraint);
1733
1734 // Add the alias to the matchables list.
1735 NewMatchables.push_back(x: std::move(AliasII));
1736 }
1737 } else {
1738 // FIXME: The tied operands checking is not yet integrated with the
1739 // framework for reporting multiple near misses. To prevent invalid
1740 // formats from being matched with an alias if a tied-operands check
1741 // would otherwise have disallowed it, we just disallow such constructs
1742 // in TableGen completely.
1743 II->buildAliasResultOperands(AliasConstraintsAreChecked: !ReportMultipleNearMisses);
1744 }
1745 }
1746 if (!NewMatchables.empty())
1747 Matchables.insert(position: Matchables.end(),
1748 first: std::make_move_iterator(i: NewMatchables.begin()),
1749 last: std::make_move_iterator(i: NewMatchables.end()));
1750
1751 // Process token alias definitions and set up the associated superclass
1752 // information.
1753 for (const Record *Rec : Records.getAllDerivedDefinitions(ClassName: "TokenAlias")) {
1754 ClassInfo *FromClass = getTokenClass(Token: Rec->getValueAsString(FieldName: "FromToken"));
1755 ClassInfo *ToClass = getTokenClass(Token: Rec->getValueAsString(FieldName: "ToToken"));
1756 if (FromClass == ToClass)
1757 PrintFatalError(ErrorLoc: Rec->getLoc(),
1758 Msg: "error: Destination value identical to source value.");
1759 FromClass->SuperClasses.push_back(x: ToClass);
1760 }
1761
1762 // Reorder classes so that classes precede super classes.
1763 Classes.sort();
1764
1765#ifdef EXPENSIVE_CHECKS
1766 // Verify that the table is sorted and operator < works transitively.
1767 for (auto I = Classes.begin(), E = Classes.end(); I != E; ++I) {
1768 for (auto J = I; J != E; ++J) {
1769 assert(!(*J < *I));
1770 assert(I == J || !J->isSubsetOf(*I));
1771 }
1772 }
1773#endif
1774}
1775
1776/// buildInstructionOperandReference - The specified operand is a reference to a
1777/// named operand such as $src. Resolve the Class and OperandInfo pointers.
1778void AsmMatcherInfo::buildInstructionOperandReference(MatchableInfo *II,
1779 StringRef OperandName,
1780 unsigned AsmOpIdx) {
1781 const CodeGenInstruction &CGI = *cast<const CodeGenInstruction *>(Val&: II->DefRec);
1782 const CGIOperandList &Operands = CGI.Operands;
1783 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1784
1785 // Map this token to an operand.
1786 std::optional<unsigned> Idx = Operands.findOperandNamed(Name: OperandName);
1787 if (!Idx)
1788 PrintFatalError(ErrorLoc: II->TheDef->getLoc(),
1789 Msg: "error: unable to find operand: '" + OperandName + "'");
1790 // If the instruction operand has multiple suboperands, but the parser
1791 // match class for the asm operand is still the default "ImmAsmOperand",
1792 // then handle each suboperand separately.
1793 if (Op->SubOpIdx == -1 && Operands[*Idx].MINumOperands > 1) {
1794 const Record *Rec = Operands[*Idx].Rec;
1795 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1796 const Record *MatchClass = Rec->getValueAsDef(FieldName: "ParserMatchClass");
1797 if (MatchClass && MatchClass->getValueAsString(FieldName: "Name") == "Imm") {
1798 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1799 StringRef Token = Op->Token; // save this in case Op gets moved
1800 for (unsigned SI = 1, SE = Operands[*Idx].MINumOperands; SI != SE; ++SI) {
1801 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1802 NewAsmOp.SubOpIdx = SI;
1803 II->AsmOperands.insert(I: II->AsmOperands.begin() + AsmOpIdx + SI,
1804 Elt: NewAsmOp);
1805 }
1806 // Replace Op with first suboperand.
1807 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1808 Op->SubOpIdx = 0;
1809 }
1810 }
1811
1812 // Set up the operand class.
1813 Op->Class = getOperandClass(OI: Operands[*Idx], SubOpIdx: Op->SubOpIdx);
1814 Op->OrigSrcOpName = OperandName;
1815
1816 // If the named operand is tied, canonicalize it to the untied operand.
1817 // For example, something like:
1818 // (outs GPR:$dst), (ins GPR:$src)
1819 // with an asmstring of
1820 // "inc $src"
1821 // we want to canonicalize to:
1822 // "inc $dst"
1823 // so that we know how to provide the $dst operand when filling in the result.
1824 int OITied = -1;
1825 if (Operands[*Idx].MINumOperands == 1)
1826 OITied = Operands[*Idx].getTiedRegister();
1827 if (OITied != -1) {
1828 // The tied operand index is an MIOperand index, find the operand that
1829 // contains it.
1830 auto [OpIdx, SubopIdx] = Operands.getSubOperandNumber(Op: OITied);
1831 OperandName = Operands[OpIdx].Name;
1832 Op->SubOpIdx = SubopIdx;
1833 }
1834
1835 Op->SrcOpName = OperandName;
1836}
1837
1838/// buildAliasOperandReference - When parsing an operand reference out of the
1839/// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1840/// operand reference is by looking it up in the result pattern definition.
1841void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1842 StringRef OperandName,
1843 MatchableInfo::AsmOperand &Op) {
1844 const CodeGenInstAlias &CGA = *cast<const CodeGenInstAlias *>(Val&: II->DefRec);
1845
1846 // Set up the operand class.
1847 for (const auto &[ResultOp, SubOpIdx] :
1848 zip_equal(t: CGA.ResultOperands, u: CGA.ResultInstOperandIndex)) {
1849 if (ResultOp.isRecord() && ResultOp.getName() == OperandName) {
1850 // It's safe to go with the first one we find, because CodeGenInstAlias
1851 // validates that all operands with the same name have the same record.
1852 Op.SubOpIdx = SubOpIdx.second;
1853 // Use the match class from the Alias definition, not the
1854 // destination instruction, as we may have an immediate that's
1855 // being munged by the match class.
1856 Op.Class = getOperandClass(Rec: ResultOp.getRecord(), SubOpIdx: Op.SubOpIdx);
1857 Op.SrcOpName = OperandName;
1858 Op.OrigSrcOpName = OperandName;
1859 return;
1860 }
1861 }
1862
1863 PrintFatalError(ErrorLoc: II->TheDef->getLoc(),
1864 Msg: "error: unable to find operand: '" + OperandName + "'");
1865}
1866
1867void MatchableInfo::buildInstructionResultOperands() {
1868 const CodeGenInstruction *ResultInst = getResultInst();
1869
1870 // Loop over all operands of the result instruction, determining how to
1871 // populate them.
1872 for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
1873 // If this is a tied operand, just copy from the previously handled operand.
1874 int TiedOp = -1;
1875 if (OpInfo.MINumOperands == 1)
1876 TiedOp = OpInfo.getTiedRegister();
1877 if (TiedOp != -1) {
1878 int TiedSrcOperand = findAsmOperandOriginallyNamed(N: OpInfo.Name);
1879 if (TiedSrcOperand != -1 &&
1880 ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand)
1881 ResOperands.push_back(Elt: ResOperand::getTiedOp(
1882 TiedOperandNum: TiedOp, SrcOperand1: ResOperands[TiedOp].AsmOperandNum, SrcOperand2: TiedSrcOperand));
1883 else
1884 ResOperands.push_back(Elt: ResOperand::getTiedOp(TiedOperandNum: TiedOp, SrcOperand1: 0, SrcOperand2: 0));
1885 continue;
1886 }
1887
1888 int SrcOperand = findAsmOperandNamed(N: OpInfo.Name);
1889 if (OpInfo.Name.empty() || SrcOperand == -1) {
1890 // This may happen for operands that are tied to a suboperand of a
1891 // complex operand. Simply use a dummy value here; nobody should
1892 // use this operand slot.
1893 // FIXME: The long term goal is for the MCOperand list to not contain
1894 // tied operands at all.
1895 ResOperands.push_back(Elt: ResOperand::getImmOp(Val: 0));
1896 continue;
1897 }
1898
1899 // Check if the one AsmOperand populates the entire operand.
1900 unsigned NumOperands = OpInfo.MINumOperands;
1901 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1902 ResOperands.push_back(Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand, NumOperands));
1903 continue;
1904 }
1905
1906 // Add a separate ResOperand for each suboperand.
1907 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1908 assert(AsmOperands[SrcOperand + AI].SubOpIdx == (int)AI &&
1909 AsmOperands[SrcOperand + AI].SrcOpName == OpInfo.Name &&
1910 "unexpected AsmOperands for suboperands");
1911 ResOperands.push_back(Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand + AI, NumOperands: 1));
1912 }
1913 }
1914}
1915
1916void MatchableInfo::buildAliasResultOperands(bool AliasConstraintsAreChecked) {
1917 const CodeGenInstAlias &CGA = *cast<const CodeGenInstAlias *>(Val&: DefRec);
1918 const CodeGenInstruction *ResultInst = getResultInst();
1919
1920 // Map of: $reg -> #lastref
1921 // where $reg is the name of the operand in the asm string
1922 // where #lastref is the last processed index where $reg was referenced in
1923 // the asm string.
1924 SmallDenseMap<StringRef, int> OperandRefs;
1925
1926 // Loop over all operands of the result instruction, determining how to
1927 // populate them.
1928 unsigned AliasOpNo = 0;
1929 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1930 for (const auto &[Idx, OpInfo] : enumerate(First: ResultInst->Operands)) {
1931 // If this is a tied operand, just copy from the previously handled operand.
1932 int TiedOp = -1;
1933 if (OpInfo.MINumOperands == 1)
1934 TiedOp = OpInfo.getTiedRegister();
1935 if (TiedOp != -1) {
1936 unsigned SrcOp1 = 0;
1937 unsigned SrcOp2 = 0;
1938
1939 // If an operand has been specified twice in the asm string,
1940 // add the two source operand's indices to the TiedOp so that
1941 // at runtime the 'tied' constraint is checked.
1942 if (ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand) {
1943 SrcOp1 = ResOperands[TiedOp].AsmOperandNum;
1944
1945 // Find the next operand (similarly named operand) in the string.
1946 StringRef Name = AsmOperands[SrcOp1].SrcOpName;
1947 auto Insert = OperandRefs.try_emplace(Key: Name, Args&: SrcOp1);
1948 SrcOp2 = findAsmOperandNamed(N: Name, LastIdx: Insert.first->second);
1949
1950 // Not updating the record in OperandRefs will cause TableGen
1951 // to fail with an error at the end of this function.
1952 if (AliasConstraintsAreChecked)
1953 Insert.first->second = SrcOp2;
1954
1955 // In case it only has one reference in the asm string,
1956 // it doesn't need to be checked for tied constraints.
1957 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2;
1958 }
1959
1960 // If the alias operand is of a different operand class, we only want
1961 // to benefit from the tied-operands check and just match the operand
1962 // as a normal, but not copy the original (TiedOp) to the result
1963 // instruction. We do this by passing -1 as the tied operand to copy.
1964 if (OpInfo.Rec->getName() !=
1965 ResultInst->Operands[TiedOp].Rec->getName()) {
1966 SrcOp1 = ResOperands[TiedOp].AsmOperandNum;
1967 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1968 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1969 SrcOp2 = findAsmOperand(N: Name, SubOpIdx: SubIdx);
1970 ResOperands.push_back(
1971 Elt: ResOperand::getTiedOp(TiedOperandNum: (unsigned)-1, SrcOperand1: SrcOp1, SrcOperand2: SrcOp2));
1972 } else {
1973 ResOperands.push_back(Elt: ResOperand::getTiedOp(TiedOperandNum: TiedOp, SrcOperand1: SrcOp1, SrcOperand2: SrcOp2));
1974 continue;
1975 }
1976 }
1977
1978 // Handle all the suboperands for this operand.
1979 StringRef OpName = OpInfo.Name;
1980 for (; AliasOpNo < LastOpNo &&
1981 CGA.ResultInstOperandIndex[AliasOpNo].first == Idx;
1982 ++AliasOpNo) {
1983 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1984
1985 // Find out what operand from the asmparser that this MCInst operand
1986 // comes from.
1987 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1988 case CodeGenInstAlias::ResultOperand::K_Record: {
1989 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1990 int SrcOperand = findAsmOperand(N: Name, SubOpIdx: SubIdx);
1991 if (SrcOperand == -1)
1992 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1993 Msg: "Instruction '" + TheDef->getName() +
1994 "' has operand '" + OpName +
1995 "' that doesn't appear in asm string!");
1996
1997 // Add it to the operand references. If it is added a second time, the
1998 // record won't be updated and it will fail later on.
1999 OperandRefs.try_emplace(Key: Name, Args&: SrcOperand);
2000
2001 unsigned NumOperands = (SubIdx == -1 ? OpInfo.MINumOperands : 1);
2002 ResOperands.push_back(
2003 Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand, NumOperands));
2004 break;
2005 }
2006 case CodeGenInstAlias::ResultOperand::K_Imm: {
2007 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
2008 ResOperands.push_back(Elt: ResOperand::getImmOp(Val: ImmVal));
2009 break;
2010 }
2011 case CodeGenInstAlias::ResultOperand::K_Reg: {
2012 const Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
2013 ResOperands.push_back(Elt: ResOperand::getRegOp(Reg));
2014 break;
2015 }
2016 }
2017 }
2018 }
2019
2020 // Check that operands are not repeated more times than is supported.
2021 for (auto &T : OperandRefs) {
2022 if (T.second != -1 && findAsmOperandNamed(N: T.first, LastIdx: T.second) != -1)
2023 PrintFatalError(ErrorLoc: TheDef->getLoc(),
2024 Msg: "Operand '" + T.first + "' can never be matched");
2025 }
2026}
2027
2028static unsigned
2029getConverterOperandID(const std::string &Name,
2030 SmallSetVector<CachedHashString, 16> &Table,
2031 bool &IsNew) {
2032 IsNew = Table.insert(X: CachedHashString(Name));
2033
2034 unsigned ID = IsNew ? Table.size() - 1 : find(Range&: Table, Val: Name) - Table.begin();
2035
2036 assert(ID < Table.size());
2037
2038 return ID;
2039}
2040
2041static unsigned
2042emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
2043 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
2044 bool HasMnemonicFirst, bool HasOptionalOperands,
2045 raw_ostream &OS) {
2046 SmallSetVector<CachedHashString, 16> OperandConversionKinds;
2047 SmallSetVector<CachedHashString, 16> InstructionConversionKinds;
2048 std::vector<std::vector<uint8_t>> ConversionTable;
2049
2050 // minimum is custom converter plus a operand index in parsed OperandVector
2051 // (0 for custom converter) and terminator (CVT_Done).
2052 size_t MaxRowLength = 3;
2053
2054 // TargetOperandClass - This is the target's operand class, like X86Operand.
2055 std::string TargetOperandClass = Target.getName().str() + "Operand";
2056
2057 // Write the convert function to a separate stream, so we can drop it after
2058 // the enum. We'll build up the conversion handlers for the individual
2059 // operand types opportunistically as we encounter them.
2060 std::string ConvertFnBody;
2061 raw_string_ostream CvtOS(ConvertFnBody);
2062 // Start the unified conversion function.
2063 if (HasOptionalOperands) {
2064 CvtOS << "void " << Target.getName() << ClassName << "::\n"
2065 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
2066 << "unsigned Opcode,\n"
2067 << " const OperandVector &Operands,\n"
2068 << " const SmallBitVector &OptionalOperandsMask,\n"
2069 << " ArrayRef<unsigned> DefaultsOffset) {\n";
2070 } else {
2071 CvtOS << "void " << Target.getName() << ClassName << "::\n"
2072 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
2073 << "unsigned Opcode,\n"
2074 << " const OperandVector &Operands) {\n";
2075 }
2076 CvtOS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
2077 CvtOS << " const uint8_t *Converter = ConversionTable[Kind];\n";
2078 CvtOS << " Inst.setOpcode(Opcode);\n";
2079 CvtOS << " for (const uint8_t *p = Converter; *p; p += 2) {\n";
2080 if (HasOptionalOperands) {
2081 // When optional operands are involved, formal and actual operand indices
2082 // may differ. Map the former to the latter by subtracting the number of
2083 // absent optional operands.
2084 // FIXME: This is not an operand index in the CVT_Tied case
2085 CvtOS << " unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];\n";
2086 } else {
2087 CvtOS << " unsigned OpIdx = *(p + 1);\n";
2088 }
2089 CvtOS << " switch (*p) {\n";
2090 CvtOS << " default: llvm_unreachable(\"invalid conversion entry!\");\n";
2091 CvtOS << " case CVT_Reg:\n";
2092 CvtOS << " static_cast<" << TargetOperandClass
2093 << " &>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";
2094 CvtOS << " break;\n";
2095 CvtOS << " case CVT_Tied: {\n";
2096 CvtOS << " assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -\n";
2097 CvtOS
2098 << " std::begin(TiedAsmOperandTable)) &&\n";
2099 CvtOS << " \"Tied operand not found\");\n";
2100 CvtOS << " unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];\n";
2101 CvtOS << " if (TiedResOpnd != (uint8_t)-1)\n";
2102 CvtOS << " Inst.addOperand(Inst.getOperand(TiedResOpnd));\n";
2103 CvtOS << " break;\n";
2104 CvtOS << " }\n";
2105
2106 std::string OperandFnBody;
2107 raw_string_ostream OpOS(OperandFnBody);
2108 // Start the operand number lookup function.
2109 OpOS << "void " << Target.getName() << ClassName << "::\n"
2110 << "convertToMapAndConstraints(unsigned Kind,\n";
2111 OpOS.indent(NumSpaces: 27);
2112 OpOS << "const OperandVector &Operands) {\n"
2113 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
2114 << " unsigned NumMCOperands = 0;\n"
2115 << " const uint8_t *Converter = ConversionTable[Kind];\n"
2116 << " for (const uint8_t *p = Converter; *p; p += 2) {\n"
2117 << " switch (*p) {\n"
2118 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
2119 << " case CVT_Reg:\n"
2120 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2121 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
2122 << " ++NumMCOperands;\n"
2123 << " break;\n"
2124 << " case CVT_Tied:\n"
2125 << " ++NumMCOperands;\n"
2126 << " break;\n";
2127
2128 // Pre-populate the operand conversion kinds with the standard always
2129 // available entries.
2130 OperandConversionKinds.insert(X: CachedHashString("CVT_Done"));
2131 OperandConversionKinds.insert(X: CachedHashString("CVT_Reg"));
2132 OperandConversionKinds.insert(X: CachedHashString("CVT_Tied"));
2133 enum { CVT_Done, CVT_Reg, CVT_Tied };
2134
2135 // Map of e.g. <0, 2, 3> -> "Tie_0_2_3" enum label.
2136 std::map<std::tuple<uint8_t, uint8_t, uint8_t>, std::string>
2137 TiedOperandsEnumMap;
2138
2139 for (auto &II : Infos) {
2140 // Check if we have a custom match function.
2141 StringRef AsmMatchConverter =
2142 II->getResultInst()->TheDef->getValueAsString(FieldName: "AsmMatchConverter");
2143 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
2144 std::string Signature = ("ConvertCustom_" + AsmMatchConverter).str();
2145 II->ConversionFnKind = Signature;
2146
2147 // Check if we have already generated this signature.
2148 if (!InstructionConversionKinds.insert(X: CachedHashString(Signature)))
2149 continue;
2150
2151 // Remember this converter for the kind enum.
2152 unsigned KindID = OperandConversionKinds.size();
2153 OperandConversionKinds.insert(
2154 X: CachedHashString("CVT_" + getEnumNameForToken(Str: AsmMatchConverter)));
2155
2156 // Add the converter row for this instruction.
2157 ConversionTable.emplace_back();
2158 ConversionTable.back().push_back(x: KindID);
2159 ConversionTable.back().push_back(x: CVT_Done);
2160
2161 // Add the handler to the conversion driver function.
2162 CvtOS << " case CVT_" << getEnumNameForToken(Str: AsmMatchConverter)
2163 << ":\n"
2164 << " " << AsmMatchConverter << "(Inst, Operands);\n"
2165 << " break;\n";
2166
2167 // FIXME: Handle the operand number lookup for custom match functions.
2168 continue;
2169 }
2170
2171 // Build the conversion function signature.
2172 std::string Signature = "Convert";
2173
2174 std::vector<uint8_t> ConversionRow;
2175
2176 // Compute the convert enum and the case body.
2177 MaxRowLength = std::max(a: MaxRowLength, b: II->ResOperands.size() * 2 + 1);
2178
2179 for (const auto &[Idx, OpInfo] : enumerate(First&: II->ResOperands)) {
2180 // Generate code to populate each result operand.
2181 switch (OpInfo.Kind) {
2182 case MatchableInfo::ResOperand::RenderAsmOperand: {
2183 // This comes from something we parsed.
2184 const MatchableInfo::AsmOperand &Op =
2185 II->AsmOperands[OpInfo.AsmOperandNum];
2186
2187 // Registers are always converted the same, don't duplicate the
2188 // conversion function based on them.
2189 Signature += "__";
2190 std::string Class;
2191 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
2192 Signature += Class;
2193 Signature += utostr(X: OpInfo.MINumOperands);
2194 Signature += "_" + itostr(X: OpInfo.AsmOperandNum);
2195
2196 // Add the conversion kind, if necessary, and get the associated ID
2197 // the index of its entry in the vector).
2198 std::string Name =
2199 "CVT_" +
2200 (Op.Class->isRegisterClass() ? "Reg" : Op.Class->RenderMethod);
2201 if (Op.Class->IsOptional) {
2202 // For optional operands we must also care about DefaultMethod
2203 assert(HasOptionalOperands);
2204 Name += "_" + Op.Class->DefaultMethod;
2205 }
2206 Name = getEnumNameForToken(Str: Name);
2207
2208 bool IsNewConverter = false;
2209 unsigned ID =
2210 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2211
2212 // Add the operand entry to the instruction kind conversion row.
2213 ConversionRow.push_back(x: ID);
2214 ConversionRow.push_back(x: OpInfo.AsmOperandNum + HasMnemonicFirst);
2215
2216 if (!IsNewConverter)
2217 break;
2218
2219 // This is a new operand kind. Add a handler for it to the
2220 // converter driver.
2221 CvtOS << " case " << Name << ":\n";
2222 if (Op.Class->IsOptional) {
2223 // If optional operand is not present in actual instruction then we
2224 // should call its DefaultMethod before RenderMethod
2225 assert(HasOptionalOperands);
2226 CvtOS << " if (OptionalOperandsMask[*(p + 1)]) {\n"
2227 << " " << Op.Class->DefaultMethod << "()"
2228 << "->" << Op.Class->RenderMethod << "(Inst, "
2229 << OpInfo.MINumOperands << ");\n"
2230 << " } else {\n"
2231 << " static_cast<" << TargetOperandClass
2232 << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod
2233 << "(Inst, " << OpInfo.MINumOperands << ");\n"
2234 << " }\n";
2235 } else {
2236 CvtOS << " static_cast<" << TargetOperandClass
2237 << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod
2238 << "(Inst, " << OpInfo.MINumOperands << ");\n";
2239 }
2240 CvtOS << " break;\n";
2241
2242 // Add a handler for the operand number lookup.
2243 OpOS << " case " << Name << ":\n"
2244 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
2245
2246 if (Op.Class->isRegisterClass())
2247 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
2248 else
2249 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
2250 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
2251 << " break;\n";
2252 break;
2253 }
2254 case MatchableInfo::ResOperand::TiedOperand: {
2255 // If this operand is tied to a previous one, just copy the MCInst
2256 // operand from the earlier one.We can only tie single MCOperand values.
2257 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
2258 uint8_t TiedOp = OpInfo.TiedOperands.ResOpnd;
2259 uint8_t SrcOp1 = OpInfo.TiedOperands.SrcOpnd1Idx + HasMnemonicFirst;
2260 uint8_t SrcOp2 = OpInfo.TiedOperands.SrcOpnd2Idx + HasMnemonicFirst;
2261 assert((Idx > TiedOp || TiedOp == (uint8_t)-1) &&
2262 "Tied operand precedes its target!");
2263 auto TiedTupleName = std::string("Tie") + utostr(X: TiedOp) + '_' +
2264 utostr(X: SrcOp1) + '_' + utostr(X: SrcOp2);
2265 Signature += "__" + TiedTupleName;
2266 ConversionRow.push_back(x: CVT_Tied);
2267 ConversionRow.push_back(x: TiedOp);
2268 ConversionRow.push_back(x: SrcOp1);
2269 ConversionRow.push_back(x: SrcOp2);
2270
2271 // Also create an 'enum' for this combination of tied operands.
2272 auto Key = std::tuple(TiedOp, SrcOp1, SrcOp2);
2273 TiedOperandsEnumMap.emplace(args&: Key, args&: TiedTupleName);
2274 break;
2275 }
2276 case MatchableInfo::ResOperand::ImmOperand: {
2277 int64_t Val = OpInfo.ImmVal;
2278 std::string Ty = "imm_" + itostr(X: Val);
2279 Ty = getEnumNameForToken(Str: Ty);
2280 Signature += "__" + Ty;
2281
2282 std::string Name = "CVT_" + Ty;
2283 bool IsNewConverter = false;
2284 unsigned ID =
2285 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2286 // Add the operand entry to the instruction kind conversion row.
2287 ConversionRow.push_back(x: ID);
2288 ConversionRow.push_back(x: 0);
2289
2290 if (!IsNewConverter)
2291 break;
2292
2293 CvtOS << " case " << Name << ":\n"
2294 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
2295 << " break;\n";
2296
2297 OpOS << " case " << Name << ":\n"
2298 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2299 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
2300 << " ++NumMCOperands;\n"
2301 << " break;\n";
2302 break;
2303 }
2304 case MatchableInfo::ResOperand::RegOperand: {
2305 std::string Reg, Name;
2306 bool IsRegByHwMode = false;
2307 if (!OpInfo.Register) {
2308 Name = "reg0";
2309 Reg = "0";
2310 } else {
2311 Reg = getQualifiedName(R: OpInfo.Register);
2312 Name = "reg" + OpInfo.Register->getName().str();
2313 IsRegByHwMode = OpInfo.Register->isSubClassOf(Name: "RegisterByHwMode");
2314 }
2315 Signature += "__" + Name;
2316 Name = "CVT_" + Name;
2317 bool IsNewConverter = false;
2318 unsigned ID =
2319 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2320 // Add the operand entry to the instruction kind conversion row.
2321 ConversionRow.push_back(x: ID);
2322 ConversionRow.push_back(x: 0);
2323
2324 if (!IsNewConverter)
2325 break;
2326
2327 CvtOS << indent(4) << "case " << Name << ":\n"
2328 << indent(6) << "Inst.addOperand(MCOperand::createReg(";
2329 if (IsRegByHwMode) {
2330 RegisterByHwMode(OpInfo.Register, Target.getRegBank())
2331 .emitResolverCall(
2332 OS&: CvtOS, HwMode: "STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo)");
2333 } else {
2334 CvtOS << Reg;
2335 }
2336 CvtOS << "));\n" << indent(6) << "break;\n";
2337 OpOS << " case " << Name << ":\n"
2338 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2339 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
2340 << " ++NumMCOperands;\n"
2341 << " break;\n";
2342 }
2343 }
2344 }
2345
2346 // If there were no operands, add to the signature to that effect
2347 if (Signature == "Convert")
2348 Signature += "_NoOperands";
2349
2350 II->ConversionFnKind = Signature;
2351
2352 // Save the signature. If we already have it, don't add a new row
2353 // to the table.
2354 if (!InstructionConversionKinds.insert(X: CachedHashString(Signature)))
2355 continue;
2356
2357 // Add the row to the table.
2358 ConversionTable.push_back(x: std::move(ConversionRow));
2359 }
2360
2361 // Finish up the converter driver function.
2362 CvtOS << " }\n }\n}\n\n";
2363
2364 // Finish up the operand number lookup function.
2365 OpOS << " }\n }\n}\n\n";
2366
2367 // Output a static table for tied operands.
2368 if (TiedOperandsEnumMap.size()) {
2369 // The number of tied operand combinations will be small in practice,
2370 // but just add the assert to be sure.
2371 assert(TiedOperandsEnumMap.size() <= 254 &&
2372 "Too many tied-operand combinations to reference with "
2373 "an 8bit offset from the conversion table, where index "
2374 "'255' is reserved as operand not to be copied.");
2375
2376 OS << "enum {\n";
2377 for (auto &KV : TiedOperandsEnumMap) {
2378 OS << " " << KV.second << ",\n";
2379 }
2380 OS << "};\n\n";
2381
2382 OS << "static const uint8_t TiedAsmOperandTable[][3] = {\n";
2383 for (auto &KV : TiedOperandsEnumMap) {
2384 OS << " /* " << KV.second << " */ { " << utostr(X: std::get<0>(t: KV.first))
2385 << ", " << utostr(X: std::get<1>(t: KV.first)) << ", "
2386 << utostr(X: std::get<2>(t: KV.first)) << " },\n";
2387 }
2388 OS << "};\n\n";
2389 } else {
2390 OS << "static const uint8_t TiedAsmOperandTable[][3] = "
2391 "{ /* empty */ {0, 0, 0} };\n\n";
2392 }
2393
2394 OS << "namespace {\n";
2395
2396 // Output the operand conversion kind enum.
2397 OS << "enum OperatorConversionKind {\n";
2398 for (const auto &Converter : OperandConversionKinds)
2399 OS << " " << Converter << ",\n";
2400 OS << " CVT_NUM_CONVERTERS\n";
2401 OS << "};\n\n";
2402
2403 // Output the instruction conversion kind enum.
2404 OS << "enum InstructionConversionKind {\n";
2405 for (const auto &Signature : InstructionConversionKinds)
2406 OS << " " << Signature << ",\n";
2407 OS << " CVT_NUM_SIGNATURES\n";
2408 OS << "};\n\n";
2409
2410 OS << "} // end anonymous namespace\n\n";
2411
2412 // Output the conversion table.
2413 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2414 << MaxRowLength << "] = {\n";
2415
2416 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2417 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2418 OS << " // " << InstructionConversionKinds[Row] << "\n";
2419 OS << " { ";
2420 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2) {
2421 const auto &OCK = OperandConversionKinds[ConversionTable[Row][i]];
2422 OS << OCK << ", ";
2423 if (OCK != CachedHashString("CVT_Tied")) {
2424 OS << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2425 continue;
2426 }
2427
2428 // For a tied operand, emit a reference to the TiedAsmOperandTable
2429 // that contains the operand to copy, and the parsed operands to
2430 // check for their tied constraints.
2431 auto Key = std::tuple((uint8_t)ConversionTable[Row][i + 1],
2432 (uint8_t)ConversionTable[Row][i + 2],
2433 (uint8_t)ConversionTable[Row][i + 3]);
2434 auto TiedOpndEnum = TiedOperandsEnumMap.find(x: Key);
2435 assert(TiedOpndEnum != TiedOperandsEnumMap.end() &&
2436 "No record for tied operand pair");
2437 OS << TiedOpndEnum->second << ", ";
2438 i += 2;
2439 }
2440 OS << "CVT_Done },\n";
2441 }
2442
2443 OS << "};\n\n";
2444
2445 // Spit out the conversion driver function.
2446 OS << ConvertFnBody;
2447
2448 // Spit out the operand number lookup function.
2449 OS << OperandFnBody;
2450
2451 return ConversionTable.size();
2452}
2453
2454/// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2455static void emitMatchClassEnumeration(CodeGenTarget &Target,
2456 std::forward_list<ClassInfo> &Infos,
2457 raw_ostream &OS) {
2458 OS << "namespace {\n\n";
2459
2460 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2461 << "/// instruction matching.\n";
2462 OS << "enum MatchClassKind {\n";
2463 OS << " InvalidMatchClass = 0,\n";
2464 OS << " OptionalMatchClass = 1,\n";
2465 ClassInfo::ClassInfoKind LastKind = ClassInfo::Token;
2466 StringRef LastName = "OptionalMatchClass";
2467 for (const auto &CI : Infos) {
2468 if (LastKind == ClassInfo::Token && CI.Kind != ClassInfo::Token) {
2469 OS << " MCK_LAST_TOKEN = " << LastName << ",\n";
2470 } else if (LastKind < ClassInfo::RegisterClassByHwMode0 &&
2471 CI.Kind >= ClassInfo::RegisterClassByHwMode0) {
2472 OS << " MCK_LAST_REGISTER = " << LastName << ",\n";
2473 } else if (LastKind < ClassInfo::UserClass0 &&
2474 CI.Kind >= ClassInfo::UserClass0) {
2475 OS << " MCK_LAST_REGCLASS_BY_HWMODE = " << LastName << ",\n";
2476 }
2477
2478 LastKind = (ClassInfo::ClassInfoKind)CI.Kind;
2479 LastName = CI.Name;
2480
2481 OS << " " << CI.Name << ", // ";
2482 if (CI.Kind == ClassInfo::Token) {
2483 OS << "'" << CI.ValueName << "'\n";
2484 } else if (CI.isRegisterClass()) {
2485 if (!CI.ValueName.empty())
2486 OS << "register class '" << CI.ValueName << "'\n";
2487 else
2488 OS << "derived register class\n";
2489 } else if (CI.isRegisterClassByHwMode()) {
2490 OS << "register class by hwmode\n";
2491 } else {
2492 OS << "user defined class '" << CI.ValueName << "'\n";
2493 }
2494 }
2495 OS << " NumMatchClassKinds\n";
2496 OS << "};\n\n";
2497
2498 OS << "} // end anonymous namespace\n\n";
2499}
2500
2501/// emitMatchClassDiagStrings - Emit a function to get the diagnostic text to be
2502/// used when an assembly operand does not match the expected operand class.
2503static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info,
2504 raw_ostream &OS) {
2505 // If the target does not use DiagnosticString for any operands, don't emit
2506 // an unused function.
2507 if (llvm::all_of(Range&: Info.Classes, P: [](const ClassInfo &CI) {
2508 return CI.DiagnosticString.empty();
2509 }))
2510 return;
2511
2512 OS << "static const char *getMatchKindDiag(" << Info.Target.getName()
2513 << "AsmParser::" << Info.Target.getName()
2514 << "MatchResultTy MatchResult) {\n";
2515 OS << " switch (MatchResult) {\n";
2516
2517 for (const auto &CI : Info.Classes) {
2518 if (!CI.DiagnosticString.empty()) {
2519 assert(!CI.DiagnosticType.empty() &&
2520 "DiagnosticString set without DiagnosticType");
2521 OS << " case " << Info.Target.getName() << "AsmParser::Match_"
2522 << CI.DiagnosticType << ":\n";
2523 OS << " return \"" << CI.DiagnosticString << "\";\n";
2524 }
2525 }
2526
2527 OS << " default:\n";
2528 OS << " return nullptr;\n";
2529
2530 OS << " }\n";
2531 OS << "}\n\n";
2532}
2533
2534static void emitRegisterMatchErrorFunc(AsmMatcherInfo &Info, raw_ostream &OS) {
2535 OS << "static unsigned getDiagKindFromRegisterClass(MatchClassKind "
2536 "RegisterClass) {\n";
2537 if (none_of(Range&: Info.Classes, P: [](const ClassInfo &CI) {
2538 return CI.isRegisterClass() && !CI.DiagnosticType.empty();
2539 })) {
2540 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2541 } else {
2542 OS << " switch (RegisterClass) {\n";
2543 for (const auto &CI : Info.Classes) {
2544 if (CI.isRegisterClass() && !CI.DiagnosticType.empty()) {
2545 OS << " case " << CI.Name << ":\n";
2546 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2547 << CI.DiagnosticType << ";\n";
2548 }
2549 }
2550
2551 OS << " default:\n";
2552 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2553
2554 OS << " }\n";
2555 }
2556 OS << "}\n\n";
2557}
2558
2559/// emitTokenDiagFunction - Emit a function mapping token class kinds to
2560/// diagnostics.
2561static void emitTokenDiagFunction(AsmMatcherInfo &Info, raw_ostream &OS) {
2562 OS << "static unsigned getDiagKindFromTokenClass(MatchClassKind Kind) {\n";
2563 OS << " switch (Kind) {\n";
2564 OS << " default:\n";
2565 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2566 for (const auto &CI : Info.Classes) {
2567 if (CI.Kind == ClassInfo::Token && !CI.DiagnosticType.empty()) {
2568 OS << " case " << CI.Name << ":\n";
2569 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2570 << CI.DiagnosticType << ";\n";
2571 }
2572 }
2573 OS << " }\n";
2574 OS << "}\n\n";
2575}
2576
2577// Returns true if ClassName corresponds to a RegisterClass defined in the
2578// target description (and thus has a generated RegClassID), rather than a
2579// singleton register or an anonymous derived register class.
2580static bool isDefinedRegisterClass(const AsmMatcherInfo &Info,
2581 StringRef ClassName) {
2582 for (const auto &RC : Info.Target.getRegBank().getRegClasses()) {
2583 if (RC.getName() == ClassName)
2584 return true;
2585 }
2586 return false;
2587}
2588
2589static void emitGetRegClassFromMatchKindFunc(AsmMatcherInfo &Info,
2590 raw_ostream &OS) {
2591 OS << "[[maybe_unused]] static const MCRegisterClass "
2592 "*getRegClassFromMatchKind(MatchClassKind Kind) {\n";
2593 OS << " switch (Kind) {\n";
2594
2595 // Emit the straightforward RegisterClass mapping.
2596 for (const auto &CI : Info.Classes) {
2597 if (CI.isRegisterClass() && !CI.ValueName.empty() &&
2598 isDefinedRegisterClass(Info, ClassName: CI.ClassName)) {
2599 OS << " case " << CI.Name << ":\n";
2600 OS << " return &get" << Info.Target.getName() << "MCRegisterClass("
2601 << Info.Target.getName() << "::" << CI.ClassName << "RegClassID);\n";
2602 }
2603 }
2604
2605 // Next Collect RegisterOperand MCK_* -> RegisterClass mappings and emit
2606 // it for all non-ambiguous RegisterOperands.
2607 // Many targets reuse the same ParserMatchClass for different register
2608 // classes so we can't emit a these unconditionally.
2609 std::map<const ClassInfo *, const ClassInfo *, deref<std::less<>>>
2610 UserClassToRegClassMap;
2611 for (const Record *RO :
2612 Info.Records.getAllDerivedDefinitions(ClassName: "RegisterOperand")) {
2613 const RecordVal *R = RO->getValue(Name: "ParserMatchClass");
2614 if (!R)
2615 continue;
2616 const DefInit *DI = dyn_cast<DefInit>(Val: R->getValue());
2617 if (!DI)
2618 continue;
2619 const Record *PMC = DI->getDef();
2620 const Record *RC = RO->getValueAsDef(FieldName: "RegClass");
2621 if (!RC || !RC->isSubClassOf(Name: "RegisterClassLike"))
2622 continue;
2623 auto PMC_It = Info.AsmOperandClasses.find(x: PMC);
2624 auto RC_It = Info.RegisterClassClasses.find(x: RC);
2625 if (PMC_It == Info.AsmOperandClasses.end() ||
2626 RC_It == Info.RegisterClassClasses.end())
2627 continue;
2628 const ClassInfo *UserCI = PMC_It->second;
2629 const ClassInfo *RegCI = RC_It->second;
2630
2631 auto It = UserClassToRegClassMap.find(x: UserCI);
2632 if (It == UserClassToRegClassMap.end()) {
2633 UserClassToRegClassMap[UserCI] = RegCI;
2634 } else if (It->second && It->second != RegCI) {
2635 // TODO: Warn about ambiguous ParserMatchClass mapping when we can.
2636 // Many targets currently have ambiguous mappings.
2637 It->second = nullptr; // Mark as ambiguous
2638 }
2639 }
2640 for (const auto [UserCI, RegCI] : UserClassToRegClassMap) {
2641 if (RegCI && isDefinedRegisterClass(Info, ClassName: RegCI->ClassName)) {
2642 OS << " case " << UserCI->Name << ":\n";
2643 OS << " return &get" << Info.Target.getName() << "MCRegisterClass("
2644 << Info.Target.getName() << "::" << RegCI->ClassName
2645 << "RegClassID);\n";
2646 }
2647 }
2648
2649 OS << " default:\n";
2650 OS << " return nullptr;\n";
2651 OS << " }\n";
2652 OS << "}\n\n";
2653}
2654
2655/// emitRegClassByHwModeMatchTable - Emit the RegClassByHwMode match table and
2656/// helper functions for remapping match classes by hardware mode.
2657static void emitRegClassByHwModeMatchTable(const CodeGenTarget &Target,
2658 AsmMatcherInfo &Info,
2659 raw_ostream &OS) {
2660 ArrayRef<const Record *> RegClassesByHwMode = Target.getAllRegClassByHwMode();
2661 if (RegClassesByHwMode.empty())
2662 return;
2663
2664 const CodeGenHwModes &CGH = Target.getHwModes();
2665 const CodeGenRegBank &RegBank = Target.getRegBank();
2666 unsigned NumModes = CGH.getNumModeIds();
2667 unsigned NumClassesByHwMode = RegClassesByHwMode.size();
2668
2669 OS << "static constexpr MatchClassKind RegClassByHwModeMatchTable["
2670 << NumModes << "][" << NumClassesByHwMode << "] = {\n";
2671
2672 // TODO: If the instruction predicates can statically resolve which hwmode,
2673 // directly match the register class
2674 for (unsigned M = 0; M < NumModes; ++M) {
2675 OS << " { // " << CGH.getModeName(Id: M, /*IncludeDefault=*/true) << '\n';
2676 for (unsigned I = 0; I != NumClassesByHwMode; ++I) {
2677 const Record *Class = RegClassesByHwMode[I];
2678 const HwModeSelect &ModeSelect = CGH.getHwModeSelect(R: Class);
2679
2680 auto FoundMode =
2681 find_if(Range: ModeSelect.Items,
2682 P: [=](const HwModeSelect::PairType P) { return P.first == M; });
2683
2684 if (FoundMode == ModeSelect.Items.end()) {
2685 OS << " InvalidMatchClass, // Missing mode entry for "
2686 << Class->getName() << "\n";
2687 } else {
2688 const CodeGenRegisterClass *RegClass =
2689 RegBank.getRegClass(FoundMode->second);
2690 const ClassInfo *CI = Info.RegisterClassClasses.at(k: RegClass->getDef());
2691 OS << " " << CI->Name << ", // " << Class->getName() << "\n";
2692 }
2693 }
2694
2695 OS << " },\n";
2696 }
2697
2698 OS << "};\n\n";
2699
2700 OS << "static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == "
2701 << NumClassesByHwMode << ");\n\n";
2702
2703 OS << "[[maybe_unused]] static inline MatchClassKind\n"
2704 << "remapRegClassByHwMode(unsigned Kind, const MCSubtargetInfo &STI) {\n"
2705 << " if (Kind > MCK_LAST_REGISTER && Kind <= "
2706 "MCK_LAST_REGCLASS_BY_HWMODE) {\n"
2707 << " unsigned HwMode = "
2708 "STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);\n"
2709 << " assert(HwMode < " << NumModes << " && \"Invalid HwMode\");\n"
2710 << " return RegClassByHwModeMatchTable[HwMode][Kind - "
2711 "(MCK_LAST_REGISTER + 1)];\n"
2712 << " }\n"
2713 << " return static_cast<MatchClassKind>(Kind);\n"
2714 << "}\n\n";
2715}
2716
2717/// emitValidateOperandClass - Emit the function to validate an operand class.
2718static void emitValidateOperandClass(const CodeGenTarget &Target,
2719 AsmMatcherInfo &Info, raw_ostream &OS) {
2720 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2721 << "MatchClassKind Kind, const MCSubtargetInfo &STI) {\n";
2722 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2723 << Info.Target.getName() << "Operand &)GOp;\n";
2724
2725 // The InvalidMatchClass is not to match any operand.
2726 OS << " if (Kind == InvalidMatchClass)\n";
2727 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2728
2729 // Check for Token operands first.
2730 OS << " if (Kind <= MCK_LAST_TOKEN) {\n";
2731 OS << " if (Operand.isToken() &&\n"
2732 << " isSubclass(matchTokenString(Operand.getToken()), Kind))\n";
2733 OS << " return MCTargetAsmParser::Match_Success;\n";
2734 if (Info.AsmParser->getValueAsBit(FieldName: "EmitTokenDiagnosticTypes"))
2735 OS << " return getDiagKindFromTokenClass(Kind);\n";
2736 else
2737 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2738 OS << " }\n\n";
2739
2740 // Check the user classes. We don't care what order since we're only
2741 // actually matching against one of them.
2742 OS << " switch (Kind) {\n"
2743 " default: break;\n";
2744 for (const auto &CI : Info.Classes) {
2745 if (!CI.isUserClass())
2746 continue;
2747
2748 OS << " case " << CI.Name << ": {\n";
2749 OS << " DiagnosticPredicate DP(Operand." << CI.PredicateMethod
2750 << "());\n";
2751 OS << " if (DP.isMatch())\n";
2752 OS << " return MCTargetAsmParser::Match_Success;\n";
2753 if (!CI.DiagnosticType.empty()) {
2754 OS << " if (DP.isNearMatch())\n";
2755 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2756 << CI.DiagnosticType << ";\n";
2757 OS << " break;\n";
2758 } else {
2759 OS << " break;\n";
2760 }
2761 OS << " }\n";
2762 }
2763 OS << " } // end switch (Kind)\n\n";
2764
2765 ArrayRef<const Record *> RegClassesByHwMode = Target.getAllRegClassByHwMode();
2766 if (!RegClassesByHwMode.empty()) {
2767 // Resolve RegClassByHwMode kinds to their concrete class regardless of
2768 // whether Operand is actually a register, so that the diagnostic
2769 // fallback paths below (for both register and non-register operands)
2770 // see a concrete class rather than an unresolved by-hwmode one.
2771 OS << " Kind = remapRegClassByHwMode(Kind, STI);\n\n";
2772 }
2773
2774 const CodeGenRegBank &RegBank = Target.getRegBank();
2775
2776 // Check for register operands, including sub-classes.
2777 const auto &Regs = RegBank.getRegisters();
2778 StringRef Namespace = Regs.front().TheDef->getValueAsString(FieldName: "Namespace");
2779 SmallVector<StringRef> Table(1 + Regs.size(), "InvalidMatchClass");
2780 for (const auto &RC : Info.RegisterClasses) {
2781 const auto &Reg = Target.getRegBank().getReg(RC.first);
2782 Table[Reg->EnumValue] = RC.second->Name;
2783 }
2784 OS << " if (Operand.isReg()) {\n";
2785 OS << " static constexpr uint16_t Table[" << Namespace
2786 << "::NUM_TARGET_REGS] = {\n";
2787 for (auto &MatchClassName : Table)
2788 OS << " " << MatchClassName << ",\n";
2789 OS << " };\n\n";
2790 OS << " MCRegister Reg = Operand.getReg();\n";
2791 OS << " MatchClassKind OpKind = Reg.isPhysical() ? "
2792 "(MatchClassKind)Table[Reg.id()] : InvalidMatchClass;\n";
2793 OS << " return isSubclass(OpKind, Kind) ? "
2794 << "(unsigned)MCTargetAsmParser::Match_Success :\n "
2795 << " getDiagKindFromRegisterClass(Kind);\n }\n\n";
2796
2797 // Expected operand is a register, but actual is not.
2798 OS << " if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)\n";
2799 OS << " return getDiagKindFromRegisterClass(Kind);\n\n";
2800
2801 // Generic fallthrough match failure case for operands that don't have
2802 // specialized diagnostic types.
2803 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2804 OS << "}\n\n";
2805}
2806
2807/// emitIsSubclass - Emit the subclass predicate function.
2808static void emitIsSubclass(CodeGenTarget &Target,
2809 std::forward_list<ClassInfo> &Infos,
2810 raw_ostream &OS) {
2811 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2812 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2813 OS << " if (A == B)\n";
2814 OS << " return true;\n\n";
2815
2816 // TODO: Use something like SequenceToOffsetTable to allow sequences to
2817 // overlap in this table.
2818 SmallVector<bool> SuperClassData;
2819
2820 OS << " [[maybe_unused]] static constexpr struct {\n";
2821 OS << " uint32_t Offset;\n";
2822 OS << " uint16_t Start;\n";
2823 OS << " uint16_t Length;\n";
2824 OS << " } Table[] = {\n";
2825 OS << " {0, 0, 0},\n"; // InvalidMatchClass
2826 OS << " {0, 0, 0},\n"; // OptionalMatchClass
2827 for (const auto &A : Infos) {
2828 SmallVector<bool> SuperClasses;
2829 SuperClasses.push_back(Elt: false); // InvalidMatchClass
2830 SuperClasses.push_back(Elt: A.IsOptional); // OptionalMatchClass
2831 for (const auto &B : Infos)
2832 SuperClasses.push_back(Elt: &A != &B && A.isSubsetOf(RHS: B));
2833
2834 // Trim leading and trailing zeros.
2835 auto End = find_if(Range: reverse(C&: SuperClasses), P: [](bool B) { return B; }).base();
2836 auto Start =
2837 std::find_if(first: SuperClasses.begin(), last: End, pred: [](bool B) { return B; });
2838
2839 unsigned Offset = SuperClassData.size();
2840 SuperClassData.append(in_start: Start, in_end: End);
2841
2842 OS << " {" << Offset << ", " << (Start - SuperClasses.begin()) << ", "
2843 << (End - Start) << "},\n";
2844 }
2845 OS << " };\n\n";
2846
2847 if (SuperClassData.empty()) {
2848 OS << " return false;\n";
2849 } else {
2850 // Dump the boolean data packed into bytes.
2851 SuperClassData.append(NumInputs: -SuperClassData.size() % 8, Elt: false);
2852 OS << " static constexpr uint8_t Data[] = {\n";
2853 for (unsigned I = 0, E = SuperClassData.size(); I < E; I += 8) {
2854 unsigned Byte = 0;
2855 for (unsigned J = 0; J < 8; ++J)
2856 Byte |= (unsigned)SuperClassData[I + J] << J;
2857 OS << formatv(Fmt: " {:X2},\n", Vals&: Byte);
2858 }
2859 OS << " };\n\n";
2860
2861 OS << " auto &Entry = Table[A];\n";
2862 OS << " unsigned Idx = B - Entry.Start;\n";
2863 OS << " if (Idx >= Entry.Length)\n";
2864 OS << " return false;\n";
2865 OS << " Idx += Entry.Offset;\n";
2866 OS << " return (Data[Idx / 8] >> (Idx % 8)) & 1;\n";
2867 }
2868 OS << "}\n\n";
2869}
2870
2871/// emitMatchTokenString - Emit the function to match a token string to the
2872/// appropriate match class value.
2873static void emitMatchTokenString(CodeGenTarget &Target,
2874 std::forward_list<ClassInfo> &Infos,
2875 raw_ostream &OS) {
2876 // Construct the match list.
2877 std::vector<StringMatcher::StringPair> Matches;
2878 for (const auto &CI : Infos) {
2879 if (CI.Kind == ClassInfo::Token)
2880 Matches.emplace_back(args: CI.ValueName, args: "return " + CI.Name + ";");
2881 }
2882
2883 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2884
2885 StringMatcher("Name", Matches, OS).Emit();
2886
2887 OS << " return InvalidMatchClass;\n";
2888 OS << "}\n\n";
2889}
2890
2891/// emitMatchRegisterName - Emit the function to match a string to the target
2892/// specific register enum.
2893static void emitMatchRegisterName(const CodeGenTarget &Target,
2894 const Record *AsmParser, raw_ostream &OS) {
2895 // Construct the match list.
2896 std::vector<StringMatcher::StringPair> Matches;
2897 const auto &Regs = Target.getRegBank().getRegisters();
2898 std::string Namespace =
2899 Regs.front().TheDef->getValueAsString(FieldName: "Namespace").str();
2900 for (const CodeGenRegister &Reg : Regs) {
2901 StringRef AsmName = Reg.TheDef->getValueAsString(FieldName: "AsmName");
2902 if (AsmName.empty())
2903 continue;
2904
2905 Matches.emplace_back(args: AsmName.str(), args: "return " + Namespace +
2906 "::" + Reg.getName().str() + ';');
2907 }
2908
2909 OS << "static MCRegister MatchRegisterName(StringRef Name) {\n";
2910
2911 bool IgnoreDuplicates =
2912 AsmParser->getValueAsBit(FieldName: "AllowDuplicateRegisterNames");
2913 StringMatcher("Name", Matches, OS).Emit(Indent: 0, IgnoreDuplicates);
2914
2915 OS << " return " << Namespace << "::NoRegister;\n";
2916 OS << "}\n\n";
2917}
2918
2919/// Emit the function to match a string to the target
2920/// specific register enum.
2921static void emitMatchRegisterAltName(const CodeGenTarget &Target,
2922 const Record *AsmParser, raw_ostream &OS) {
2923 // Construct the match list.
2924 std::vector<StringMatcher::StringPair> Matches;
2925 const auto &Regs = Target.getRegBank().getRegisters();
2926 std::string Namespace =
2927 Regs.front().TheDef->getValueAsString(FieldName: "Namespace").str();
2928 for (const CodeGenRegister &Reg : Regs) {
2929 for (StringRef AltName : Reg.TheDef->getValueAsListOfStrings(FieldName: "AltNames")) {
2930 AltName = AltName.trim();
2931
2932 // don't handle empty alternative names
2933 if (AltName.empty())
2934 continue;
2935
2936 Matches.emplace_back(args: AltName.str(), args: "return " + Namespace +
2937 "::" + Reg.getName().str() + ';');
2938 }
2939 }
2940
2941 OS << "static MCRegister MatchRegisterAltName(StringRef Name) {\n";
2942
2943 bool IgnoreDuplicates =
2944 AsmParser->getValueAsBit(FieldName: "AllowDuplicateRegisterNames");
2945 StringMatcher("Name", Matches, OS).Emit(Indent: 0, IgnoreDuplicates);
2946
2947 OS << " return " << Namespace << "::NoRegister;\n";
2948 OS << "}\n\n";
2949}
2950
2951/// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2952static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2953 // Get the set of diagnostic types from all of the operand classes.
2954 std::set<StringRef> Types;
2955 for (const auto &CI : Info.Classes) {
2956 if (!CI.DiagnosticType.empty())
2957 Types.insert(x: CI.DiagnosticType);
2958 }
2959
2960 if (Types.empty())
2961 return;
2962
2963 // Now emit the enum entries.
2964 for (StringRef Type : Types)
2965 OS << " Match_" << Type << ",\n";
2966 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2967}
2968
2969/// emitGetSubtargetFeatureName - Emit the helper function to get the
2970/// user-level name for a subtarget feature.
2971static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2972 OS << "// User-level names for subtarget features that participate in\n"
2973 << "// instruction matching.\n"
2974 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2975 if (!Info.SubtargetFeatures.empty()) {
2976 OS << " switch(Val) {\n";
2977 for (const SubtargetFeatureInfo &SFI :
2978 make_second_range(c&: Info.SubtargetFeatures)) {
2979 // FIXME: Totally just a placeholder name to get the algorithm working.
2980 OS << " case " << SFI.getEnumBitName() << ": return \""
2981 << SFI.TheDef->getValueAsString(FieldName: "PredicateName") << "\";\n";
2982 }
2983 OS << " default: return \"(unknown)\";\n";
2984 OS << " }\n";
2985 } else {
2986 // Nothing to emit, so skip the switch
2987 OS << " return \"(unknown)\";\n";
2988 }
2989 OS << "}\n\n";
2990}
2991
2992static std::string GetAliasRequiredFeatures(const Record *R,
2993 const AsmMatcherInfo &Info) {
2994 std::string Result;
2995
2996 ListSeparator LS(" && ");
2997 for (const Record *RF : R->getValueAsListOfDefs(FieldName: "Predicates")) {
2998 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(Def: RF);
2999 if (!F)
3000 PrintFatalError(ErrorLoc: R->getLoc(),
3001 Msg: "Predicate '" + RF->getName() +
3002 "' is not marked as an AssemblerPredicate!");
3003 Result += LS;
3004 Result += "Features.test(" + F->getEnumBitName() + ')';
3005 }
3006
3007 return Result;
3008}
3009
3010static void
3011emitMnemonicAliasVariant(raw_ostream &OS, const AsmMatcherInfo &Info,
3012 ArrayRef<const Record *> Aliases, unsigned Indent = 0,
3013 StringRef AsmParserVariantName = StringRef()) {
3014 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
3015 // iteration order of the map is stable.
3016 std::map<std::string, std::vector<const Record *>> AliasesFromMnemonic;
3017
3018 for (const Record *R : Aliases) {
3019 // FIXME: Allow AssemblerVariantName to be a comma separated list.
3020 StringRef AsmVariantName = R->getValueAsString(FieldName: "AsmVariantName");
3021 if (AsmVariantName != AsmParserVariantName)
3022 continue;
3023 AliasesFromMnemonic[R->getValueAsString(FieldName: "FromMnemonic").lower()].push_back(
3024 x: R);
3025 }
3026 if (AliasesFromMnemonic.empty())
3027 return;
3028
3029 // Process each alias a "from" mnemonic at a time, building the code executed
3030 // by the string remapper.
3031 std::vector<StringMatcher::StringPair> Cases;
3032 for (const auto &AliasEntry : AliasesFromMnemonic) {
3033 // Loop through each alias and emit code that handles each case. If there
3034 // are two instructions without predicates, emit an error. If there is one,
3035 // emit it last.
3036 std::string MatchCode;
3037 int AliasWithNoPredicate = -1;
3038
3039 ArrayRef<const Record *> ToVec = AliasEntry.second;
3040 for (const auto &[Idx, R] : enumerate(First&: ToVec)) {
3041 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
3042
3043 // If this unconditionally matches, remember it for later and diagnose
3044 // duplicates.
3045 if (FeatureMask.empty()) {
3046 if (AliasWithNoPredicate != -1 &&
3047 R->getValueAsString(FieldName: "ToMnemonic") !=
3048 ToVec[AliasWithNoPredicate]->getValueAsString(FieldName: "ToMnemonic")) {
3049 // We can't have two different aliases from the same mnemonic with no
3050 // predicate.
3051 PrintError(
3052 ErrorLoc: ToVec[AliasWithNoPredicate]->getLoc(),
3053 Msg: "two different MnemonicAliases with the same 'from' mnemonic!");
3054 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "this is the other MnemonicAlias.");
3055 }
3056
3057 AliasWithNoPredicate = Idx;
3058 continue;
3059 }
3060 if (R->getValueAsString(FieldName: "ToMnemonic") == AliasEntry.first)
3061 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "MnemonicAlias to the same string");
3062
3063 if (!MatchCode.empty())
3064 MatchCode += "else ";
3065 MatchCode += "if (" + FeatureMask + ")\n";
3066 MatchCode += " Mnemonic = \"";
3067 MatchCode += R->getValueAsString(FieldName: "ToMnemonic").lower();
3068 MatchCode += "\";\n";
3069 }
3070
3071 if (AliasWithNoPredicate != -1) {
3072 const Record *R = ToVec[AliasWithNoPredicate];
3073 if (!MatchCode.empty())
3074 MatchCode += "else\n ";
3075 MatchCode += "Mnemonic = \"";
3076 MatchCode += R->getValueAsString(FieldName: "ToMnemonic").lower();
3077 MatchCode += "\";\n";
3078 }
3079
3080 MatchCode += "return;";
3081
3082 Cases.emplace_back(args: AliasEntry.first, args&: MatchCode);
3083 }
3084 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
3085}
3086
3087/// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
3088/// emit a function for them and return true, otherwise return false.
3089static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
3090 CodeGenTarget &Target) {
3091 // Ignore aliases when match-prefix is set.
3092 if (!MatchPrefix.empty())
3093 return false;
3094
3095 ArrayRef<const Record *> Aliases =
3096 Info.getRecords().getAllDerivedDefinitions(ClassName: "MnemonicAlias");
3097 if (Aliases.empty())
3098 return false;
3099
3100 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
3101 "const FeatureBitset &Features, unsigned VariantID) {\n";
3102 unsigned VariantCount = Target.getAsmParserVariantCount();
3103 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3104 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3105 int AsmParserVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3106 StringRef AsmParserVariantName = AsmVariant->getValueAsString(FieldName: "Name");
3107
3108 // If the variant doesn't have a name, defer to the emitMnemonicAliasVariant
3109 // call after the loop.
3110 if (AsmParserVariantName.empty()) {
3111 assert(VariantCount == 1 && "Multiple variants should each be named");
3112 continue;
3113 }
3114
3115 if (VC == 0)
3116 OS << " switch (VariantID) {\n";
3117 OS << " case " << AsmParserVariantNo << ":\n";
3118 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
3119 AsmParserVariantName);
3120 OS << " break;\n";
3121
3122 if (VC == VariantCount - 1)
3123 OS << " }\n";
3124 }
3125
3126 // Emit aliases that apply to all variants.
3127 emitMnemonicAliasVariant(OS, Info, Aliases);
3128
3129 OS << "}\n\n";
3130
3131 return true;
3132}
3133
3134static void
3135emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
3136 const AsmMatcherInfo &Info, StringRef ClassName,
3137 const StringToOffsetTable &StringTable,
3138 unsigned MaxMnemonicIndex, unsigned MaxFeaturesIndex,
3139 bool HasMnemonicFirst, const Record &AsmParser) {
3140 unsigned MaxMask = 0;
3141 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
3142 MaxMask |= OMI.OperandMask;
3143 }
3144
3145 // Emit the static custom operand parsing table;
3146 OS << "namespace {\n";
3147 OS << " struct OperandMatchEntry {\n";
3148 OS << " " << getMinimalTypeForRange(Range: MaxMnemonicIndex) << " Mnemonic;\n";
3149 OS << " " << getMinimalTypeForRange(Range: MaxMask) << " OperandMask;\n";
3150 OS << " "
3151 << getMinimalTypeForRange(
3152 Range: std::distance(first: Info.Classes.begin(), last: Info.Classes.end()) +
3153 2 /* Include 'InvalidMatchClass' and 'OptionalMatchClass' */)
3154 << " Class;\n";
3155 OS << " " << getMinimalTypeForRange(Range: MaxFeaturesIndex)
3156 << " RequiredFeaturesIdx;\n\n";
3157 OS << " StringRef getMnemonic() const {\n";
3158 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
3159 OS << " MnemonicTable[Mnemonic]);\n";
3160 OS << " }\n";
3161 OS << " };\n\n";
3162
3163 OS << " // Predicate for searching for an opcode.\n";
3164 OS << " struct LessOpcodeOperand {\n";
3165 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
3166 OS << " return LHS.getMnemonic() < RHS;\n";
3167 OS << " }\n";
3168 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
3169 OS << " return LHS < RHS.getMnemonic();\n";
3170 OS << " }\n";
3171 OS << " bool operator()(const OperandMatchEntry &LHS,";
3172 OS << " const OperandMatchEntry &RHS) {\n";
3173 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
3174 OS << " }\n";
3175 OS << " };\n";
3176
3177 OS << "} // end anonymous namespace\n\n";
3178
3179 OS << "static const OperandMatchEntry OperandMatchTable["
3180 << Info.OperandMatchInfo.size() << "] = {\n";
3181
3182 OS << " /* Operand List Mnemonic, Mask, Operand Class, Features */\n";
3183 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
3184 const MatchableInfo &II = *OMI.MI;
3185
3186 OS << " { ";
3187
3188 // Store a pascal-style length byte in the mnemonic.
3189 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.lower();
3190 OS << *StringTable.GetStringOffset(Str: LenMnemonic) << " /* " << II.Mnemonic
3191 << " */, ";
3192
3193 OS << OMI.OperandMask;
3194 OS << " /* ";
3195 ListSeparator LS;
3196 for (int i = 0, e = 31; i != e; ++i)
3197 if (OMI.OperandMask & (1 << i))
3198 OS << LS << i;
3199 OS << " */, ";
3200
3201 OS << OMI.CI->Name;
3202
3203 // Write the required features mask.
3204 OS << ", AMFBS";
3205 if (II.RequiredFeatures.empty())
3206 OS << "_None";
3207 else
3208 for (const auto &F : II.RequiredFeatures)
3209 OS << '_' << F->TheDef->getName();
3210
3211 OS << " },\n";
3212 }
3213 OS << "};\n\n";
3214
3215 // Emit the operand class switch to call the correct custom parser for
3216 // the found operand class.
3217 OS << "ParseStatus " << Target.getName() << ClassName << "::\n"
3218 << "tryCustomParseOperand(OperandVector"
3219 << " &Operands,\n unsigned MCK) {\n\n"
3220 << " switch(MCK) {\n";
3221
3222 for (const auto &CI : Info.Classes) {
3223 if (CI.ParserMethod.empty())
3224 continue;
3225 OS << " case " << CI.Name << ":\n"
3226 << " return " << CI.ParserMethod << "(Operands);\n";
3227 }
3228
3229 OS << " default:\n";
3230 OS << " return ParseStatus::NoMatch;\n";
3231 OS << " }\n";
3232 OS << " return ParseStatus::NoMatch;\n";
3233 OS << "}\n\n";
3234
3235 // Emit the static custom operand parser. This code is very similar with
3236 // the other matcher. Also use MatchResultTy here just in case we go for
3237 // a better error handling.
3238 OS << "ParseStatus " << Target.getName() << ClassName << "::\n"
3239 << "MatchOperandParserImpl(OperandVector"
3240 << " &Operands,\n StringRef Mnemonic,\n"
3241 << " bool ParseForAllFeatures) {\n";
3242
3243 // Emit code to get the available features.
3244 OS << " // Get the current feature set.\n";
3245 OS << " const FeatureBitset &AvailableFeatures = "
3246 "getAvailableFeatures();\n\n";
3247
3248 OS << " // Get the next operand index.\n";
3249 OS << " unsigned NextOpNum = Operands.size()"
3250 << (HasMnemonicFirst ? " - 1" : "") << ";\n";
3251
3252 // Emit code to search the table.
3253 OS << " // Search the table.\n";
3254 if (HasMnemonicFirst) {
3255 OS << " auto MnemonicRange =\n";
3256 OS << " std::equal_range(std::begin(OperandMatchTable), "
3257 "std::end(OperandMatchTable),\n";
3258 OS << " Mnemonic, LessOpcodeOperand());\n\n";
3259 } else {
3260 OS << " auto MnemonicRange = std::pair(std::begin(OperandMatchTable),"
3261 " std::end(OperandMatchTable));\n";
3262 OS << " if (!Mnemonic.empty())\n";
3263 OS << " MnemonicRange =\n";
3264 OS << " std::equal_range(std::begin(OperandMatchTable), "
3265 "std::end(OperandMatchTable),\n";
3266 OS << " Mnemonic, LessOpcodeOperand());\n\n";
3267 }
3268
3269 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3270 OS << " return ParseStatus::NoMatch;\n\n";
3271
3272 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
3273 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
3274
3275 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3276 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
3277
3278 // Emit check that the required features are available.
3279 OS << " // check if the available features match\n";
3280 OS << " const FeatureBitset &RequiredFeatures = "
3281 "FeatureBitsets[it->RequiredFeaturesIdx];\n";
3282 OS << " if (!ParseForAllFeatures && (AvailableFeatures & "
3283 "RequiredFeatures) != RequiredFeatures)\n";
3284 OS << " continue;\n\n";
3285
3286 // Emit check to ensure the operand number matches.
3287 OS << " // check if the operand in question has a custom parser.\n";
3288 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
3289 OS << " continue;\n\n";
3290
3291 // Emit call to the custom parser method
3292 StringRef ParserName = AsmParser.getValueAsString(FieldName: "OperandParserMethod");
3293 if (ParserName.empty())
3294 ParserName = "tryCustomParseOperand";
3295 OS << " // call custom parse method to handle the operand\n";
3296 OS << " ParseStatus Result = " << ParserName << "(Operands, it->Class);\n";
3297 OS << " if (!Result.isNoMatch())\n";
3298 OS << " return Result;\n";
3299 OS << " }\n\n";
3300
3301 OS << " // Okay, we had no match.\n";
3302 OS << " return ParseStatus::NoMatch;\n";
3303 OS << "}\n\n";
3304}
3305
3306static void emitAsmTiedOperandConstraints(CodeGenTarget &Target,
3307 AsmMatcherInfo &Info, raw_ostream &OS,
3308 bool HasOptionalOperands) {
3309 std::string AsmParserName =
3310 Info.AsmParser->getValueAsString(FieldName: "AsmParserClassName").str();
3311 OS << "static bool ";
3312 OS << "checkAsmTiedOperandConstraints(const " << Target.getName()
3313 << AsmParserName << "&AsmParser,\n";
3314 OS << " unsigned Kind, const OperandVector "
3315 "&Operands,\n";
3316 if (HasOptionalOperands)
3317 OS << " ArrayRef<unsigned> DefaultsOffset,\n";
3318 OS << " uint64_t &ErrorInfo) {\n";
3319 OS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
3320 OS << " const uint8_t *Converter = ConversionTable[Kind];\n";
3321 OS << " for (const uint8_t *p = Converter; *p; p += 2) {\n";
3322 OS << " switch (*p) {\n";
3323 OS << " case CVT_Tied: {\n";
3324 OS << " unsigned OpIdx = *(p + 1);\n";
3325 OS << " assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";
3326 OS << " std::begin(TiedAsmOperandTable)) &&\n";
3327 OS << " \"Tied operand not found\");\n";
3328 OS << " unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];\n";
3329 OS << " unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];\n";
3330 if (HasOptionalOperands) {
3331 // When optional operands are involved, formal and actual operand indices
3332 // may differ. Map the former to the latter by subtracting the number of
3333 // absent optional operands.
3334 OS << " OpndNum1 = OpndNum1 - DefaultsOffset[OpndNum1];\n";
3335 OS << " OpndNum2 = OpndNum2 - DefaultsOffset[OpndNum2];\n";
3336 }
3337 OS << " if (OpndNum1 != OpndNum2) {\n";
3338 OS << " auto &SrcOp1 = Operands[OpndNum1];\n";
3339 OS << " auto &SrcOp2 = Operands[OpndNum2];\n";
3340 OS << " if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {\n";
3341 OS << " ErrorInfo = OpndNum2;\n";
3342 OS << " return false;\n";
3343 OS << " }\n";
3344 OS << " }\n";
3345 OS << " break;\n";
3346 OS << " }\n";
3347 OS << " default:\n";
3348 OS << " break;\n";
3349 OS << " }\n";
3350 OS << " }\n";
3351 OS << " return true;\n";
3352 OS << "}\n\n";
3353}
3354
3355static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target,
3356 unsigned VariantCount) {
3357 OS << "static std::string " << Target.getName()
3358 << "MnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,"
3359 << " unsigned VariantID) {\n";
3360 if (!VariantCount)
3361 OS << " return \"\";";
3362 else {
3363 OS << " const unsigned MaxEditDist = 2;\n";
3364 OS << " std::vector<StringRef> Candidates;\n";
3365 OS << " StringRef Prev = \"\";\n\n";
3366
3367 OS << " // Find the appropriate table for this asm variant.\n";
3368 OS << " const MatchEntry *Start, *End;\n";
3369 OS << " switch (VariantID) {\n";
3370 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3371 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3372 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3373 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3374 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3375 << "); End = std::end(MatchTable" << VC << "); break;\n";
3376 }
3377 OS << " }\n\n";
3378 OS << " for (auto I = Start; I < End; I++) {\n";
3379 OS << " // Ignore unsupported instructions.\n";
3380 OS << " const FeatureBitset &RequiredFeatures = "
3381 "FeatureBitsets[I->RequiredFeaturesIdx];\n";
3382 OS << " if ((FBS & RequiredFeatures) != RequiredFeatures)\n";
3383 OS << " continue;\n";
3384 OS << "\n";
3385 OS << " StringRef T = I->getMnemonic();\n";
3386 OS << " // Avoid recomputing the edit distance for the same string.\n";
3387 OS << " if (T == Prev)\n";
3388 OS << " continue;\n";
3389 OS << "\n";
3390 OS << " Prev = T;\n";
3391 OS << " unsigned Dist = S.edit_distance(T, false, MaxEditDist);\n";
3392 OS << " if (Dist <= MaxEditDist)\n";
3393 OS << " Candidates.push_back(T);\n";
3394 OS << " }\n";
3395 OS << "\n";
3396 OS << " if (Candidates.empty())\n";
3397 OS << " return \"\";\n";
3398 OS << "\n";
3399 OS << " std::string Res = \", did you mean: \";\n";
3400 OS << " unsigned i = 0;\n";
3401 OS << " for (; i < Candidates.size() - 1; i++)\n";
3402 OS << " Res += Candidates[i].str() + \", \";\n";
3403 OS << " return Res + Candidates[i].str() + \"?\";\n";
3404 }
3405 OS << "}\n";
3406 OS << "\n";
3407}
3408
3409static void emitMnemonicChecker(raw_ostream &OS, CodeGenTarget &Target,
3410 unsigned VariantCount, bool HasMnemonicFirst,
3411 bool HasMnemonicAliases) {
3412 OS << "static bool " << Target.getName()
3413 << "CheckMnemonic(StringRef Mnemonic,\n";
3414 OS << " "
3415 << "const FeatureBitset &AvailableFeatures,\n";
3416 OS << " "
3417 << "unsigned VariantID) {\n";
3418
3419 if (!VariantCount) {
3420 OS << " return false;\n";
3421 } else {
3422 if (HasMnemonicAliases) {
3423 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3424 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);";
3425 OS << "\n\n";
3426 }
3427 OS << " // Find the appropriate table for this asm variant.\n";
3428 OS << " const MatchEntry *Start, *End;\n";
3429 OS << " switch (VariantID) {\n";
3430 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3431 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3432 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3433 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3434 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3435 << "); End = std::end(MatchTable" << VC << "); break;\n";
3436 }
3437 OS << " }\n\n";
3438
3439 OS << " // Search the table.\n";
3440 if (HasMnemonicFirst) {
3441 OS << " auto MnemonicRange = "
3442 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3443 } else {
3444 OS << " auto MnemonicRange = std::pair(Start, End);\n";
3445 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3446 OS << " if (!Mnemonic.empty())\n";
3447 OS << " MnemonicRange = "
3448 << "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3449 }
3450
3451 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3452 OS << " return false;\n\n";
3453
3454 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3455 << "*ie = MnemonicRange.second;\n";
3456 OS << " it != ie; ++it) {\n";
3457 OS << " const FeatureBitset &RequiredFeatures =\n";
3458 OS << " FeatureBitsets[it->RequiredFeaturesIdx];\n";
3459 OS << " if ((AvailableFeatures & RequiredFeatures) == ";
3460 OS << "RequiredFeatures)\n";
3461 OS << " return true;\n";
3462 OS << " }\n";
3463 OS << " return false;\n";
3464 }
3465 OS << "}\n";
3466 OS << "\n";
3467}
3468
3469// Emit a function mapping match classes to strings, for debugging.
3470static void emitMatchClassKindNames(std::forward_list<ClassInfo> &Infos,
3471 raw_ostream &OS) {
3472 OS << "#ifndef NDEBUG\n";
3473 OS << "const char *getMatchClassName(MatchClassKind Kind) {\n";
3474 OS << " switch (Kind) {\n";
3475
3476 OS << " case InvalidMatchClass: return \"InvalidMatchClass\";\n";
3477 OS << " case OptionalMatchClass: return \"OptionalMatchClass\";\n";
3478 for (const auto &CI : Infos) {
3479 OS << " case " << CI.Name << ": return \"" << CI.Name << "\";\n";
3480 }
3481 OS << " case NumMatchClassKinds: return \"NumMatchClassKinds\";\n";
3482
3483 OS << " }\n";
3484 OS << " llvm_unreachable(\"unhandled MatchClassKind!\");\n";
3485 OS << "}\n\n";
3486 OS << "#endif // NDEBUG\n";
3487}
3488
3489static std::string
3490getNameForFeatureBitset(ArrayRef<const Record *> FeatureBitset) {
3491 std::string Name = "AMFBS";
3492 for (const Record *Feature : FeatureBitset)
3493 Name += ("_" + Feature->getName()).str();
3494 return Name;
3495}
3496
3497void AsmMatcherEmitter::run(raw_ostream &OS) {
3498 CodeGenTarget Target(Records);
3499 const Record *AsmParser = Target.getAsmParser();
3500 StringRef ClassName = AsmParser->getValueAsString(FieldName: "AsmParserClassName");
3501
3502 emitSourceFileHeader(Desc: "Assembly Matcher Source Fragment", OS, Record: Records);
3503
3504 // Compute the information on the instructions to match.
3505 AsmMatcherInfo Info(AsmParser, Target, Records);
3506 Info.buildInfo();
3507
3508 bool PreferSmallerInstructions = getPreferSmallerInstructions(Target);
3509 // Sort the instruction table using the partial order on classes. We use
3510 // stable_sort to ensure that ambiguous instructions are still
3511 // deterministically ordered.
3512 llvm::stable_sort(
3513 Range&: Info.Matchables,
3514 C: [PreferSmallerInstructions](const std::unique_ptr<MatchableInfo> &A,
3515 const std::unique_ptr<MatchableInfo> &B) {
3516 return A->shouldBeMatchedBefore(RHS: *B, PreferSmallerInstructions);
3517 });
3518
3519#ifdef EXPENSIVE_CHECKS
3520 // Verify that the table is sorted and operator < works transitively.
3521 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
3522 ++I) {
3523 for (auto J = I; J != E; ++J) {
3524 assert(!(*J)->shouldBeMatchedBefore(**I, PreferSmallerInstructions));
3525 }
3526 }
3527#endif
3528
3529 DEBUG_WITH_TYPE("instruction_info", {
3530 for (const auto &MI : Info.Matchables)
3531 MI->dump();
3532 });
3533
3534 // Check for ambiguous matchables.
3535 DEBUG_WITH_TYPE("ambiguous_instrs", {
3536 unsigned NumAmbiguous = 0;
3537 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
3538 ++I) {
3539 for (auto J = std::next(I); J != E; ++J) {
3540 const MatchableInfo &A = **I;
3541 const MatchableInfo &B = **J;
3542
3543 if (A.couldMatchAmbiguouslyWith(B, PreferSmallerInstructions)) {
3544 errs() << "warning: ambiguous matchables:\n";
3545 A.dump();
3546 errs() << "\nis incomparable with:\n";
3547 B.dump();
3548 errs() << "\n\n";
3549 ++NumAmbiguous;
3550 }
3551 }
3552 }
3553 if (NumAmbiguous)
3554 errs() << "warning: " << NumAmbiguous << " ambiguous matchables!\n";
3555 });
3556
3557 // Compute the information on the custom operand parsing.
3558 Info.buildOperandMatchInfo();
3559
3560 bool HasMnemonicFirst = AsmParser->getValueAsBit(FieldName: "HasMnemonicFirst");
3561 bool HasOptionalOperands = Info.hasOptionalOperands();
3562 bool ReportMultipleNearMisses =
3563 AsmParser->getValueAsBit(FieldName: "ReportMultipleNearMisses");
3564
3565 // Write the output.
3566
3567 // Information for the class declaration.
3568 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
3569 OS << "#undef GET_ASSEMBLER_HEADER\n";
3570 OS << " // This should be included into the middle of the declaration of\n";
3571 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
3572 OS << " FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) "
3573 "const;\n";
3574 if (HasOptionalOperands) {
3575 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
3576 << "unsigned Opcode,\n"
3577 << " const OperandVector &Operands,\n"
3578 << " const SmallBitVector "
3579 "&OptionalOperandsMask,\n"
3580 << " ArrayRef<unsigned> DefaultsOffset);\n";
3581 } else {
3582 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
3583 << "unsigned Opcode,\n"
3584 << " const OperandVector &Operands);\n";
3585 }
3586 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
3587 OS << " const OperandVector &Operands) override;\n";
3588 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
3589 << " MCInst &Inst,\n";
3590 if (ReportMultipleNearMisses)
3591 OS << " SmallVectorImpl<NearMissInfo> "
3592 "*NearMisses,\n";
3593 else
3594 OS << " uint64_t &ErrorInfo,\n"
3595 << " FeatureBitset &MissingFeatures,\n";
3596 OS << " bool matchingInlineAsm,\n"
3597 << " unsigned VariantID = 0);\n";
3598 if (!ReportMultipleNearMisses)
3599 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
3600 << " MCInst &Inst,\n"
3601 << " uint64_t &ErrorInfo,\n"
3602 << " bool matchingInlineAsm,\n"
3603 << " unsigned VariantID = 0) {\n"
3604 << " FeatureBitset MissingFeatures;\n"
3605 << " return MatchInstructionImpl(Operands, Inst, ErrorInfo, "
3606 "MissingFeatures,\n"
3607 << " matchingInlineAsm, VariantID);\n"
3608 << " }\n\n";
3609
3610 if (!Info.OperandMatchInfo.empty()) {
3611 OS << " ParseStatus MatchOperandParserImpl(\n";
3612 OS << " OperandVector &Operands,\n";
3613 OS << " StringRef Mnemonic,\n";
3614 OS << " bool ParseForAllFeatures = false);\n";
3615
3616 OS << " ParseStatus tryCustomParseOperand(\n";
3617 OS << " OperandVector &Operands,\n";
3618 OS << " unsigned MCK);\n\n";
3619 }
3620
3621 OS << "#endif // GET_ASSEMBLER_HEADER\n\n";
3622
3623 // Emit the operand match diagnostic enum names.
3624 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
3625 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3626 emitOperandDiagnosticTypes(Info, OS);
3627 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3628
3629 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
3630 OS << "#undef GET_REGISTER_MATCHER\n\n";
3631
3632 // Emit the subtarget feature enumeration.
3633 SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(
3634 SubtargetFeatures: Info.SubtargetFeatures, OS);
3635
3636 // Emit the function to match a register name to number.
3637 // This should be omitted for Mips target
3638 if (AsmParser->getValueAsBit(FieldName: "ShouldEmitMatchRegisterName"))
3639 emitMatchRegisterName(Target, AsmParser, OS);
3640
3641 if (AsmParser->getValueAsBit(FieldName: "ShouldEmitMatchRegisterAltName"))
3642 emitMatchRegisterAltName(Target, AsmParser, OS);
3643
3644 OS << "#endif // GET_REGISTER_MATCHER\n\n";
3645
3646 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
3647 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
3648
3649 // Generate the helper function to get the names for subtarget features.
3650 emitGetSubtargetFeatureName(Info, OS);
3651
3652 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
3653
3654 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
3655 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
3656
3657 // Generate the function that remaps for mnemonic aliases.
3658 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
3659
3660 // Generate the convertToMCInst function to convert operands into an MCInst.
3661 // Also, generate the convertToMapAndConstraints function for MS-style inline
3662 // assembly. The latter doesn't actually generate a MCInst.
3663 unsigned NumConverters =
3664 emitConvertFuncs(Target, ClassName, Infos&: Info.Matchables, HasMnemonicFirst,
3665 HasOptionalOperands, OS);
3666
3667 // Emit the enumeration for classes which participate in matching.
3668 emitMatchClassEnumeration(Target, Infos&: Info.Classes, OS);
3669
3670 // Emit a function to get the user-visible string to describe an operand
3671 // match failure in diagnostics.
3672 emitOperandMatchErrorDiagStrings(Info, OS);
3673
3674 // Emit a function to map register classes to operand match failure codes.
3675 emitRegisterMatchErrorFunc(Info, OS);
3676
3677 // Emit a function to map MatchClassKind to MCRegisterClass.
3678 emitGetRegClassFromMatchKindFunc(Info, OS);
3679
3680 // Emit the routine to match token strings to their match class.
3681 emitMatchTokenString(Target, Infos&: Info.Classes, OS);
3682
3683 // Emit the subclass predicate routine.
3684 emitIsSubclass(Target, Infos&: Info.Classes, OS);
3685
3686 // Emit the function mapping token class kinds to diagnostic codes.
3687 if (AsmParser->getValueAsBit(FieldName: "EmitTokenDiagnosticTypes"))
3688 emitTokenDiagFunction(Info, OS);
3689
3690 // Emit the RegClassByHwMode match table and remap helper functions.
3691 emitRegClassByHwModeMatchTable(Target, Info, OS);
3692
3693 // Emit the routine to validate an operand against a match class.
3694 emitValidateOperandClass(Target, Info, OS);
3695
3696 emitMatchClassKindNames(Infos&: Info.Classes, OS);
3697
3698 // Emit the available features compute function.
3699 SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
3700 TargetName: Info.Target.getName(), ClassName, FuncName: "ComputeAvailableFeatures",
3701 SubtargetFeatures&: Info.SubtargetFeatures, OS);
3702
3703 if (!ReportMultipleNearMisses)
3704 emitAsmTiedOperandConstraints(Target, Info, OS, HasOptionalOperands);
3705
3706 StringToOffsetTable StringTable(/*AppendZero=*/false);
3707
3708 size_t MaxNumOperands = 0;
3709 unsigned MaxMnemonicIndex = 0;
3710 bool HasDeprecation = false;
3711 for (const auto &MI : Info.Matchables) {
3712 MaxNumOperands = std::max(a: MaxNumOperands, b: MI->AsmOperands.size());
3713 HasDeprecation |= MI->HasDeprecation;
3714
3715 // Store a pascal-style length byte in the mnemonic.
3716 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
3717 MaxMnemonicIndex = std::max(a: MaxMnemonicIndex,
3718 b: StringTable.GetOrAddStringOffset(Str: LenMnemonic));
3719 }
3720
3721 OS << "static const char MnemonicTable[] =\n";
3722 StringTable.EmitString(O&: OS);
3723 OS << ";\n\n";
3724
3725 std::vector<std::vector<const Record *>> FeatureBitsets;
3726 for (const auto &MI : Info.Matchables) {
3727 if (MI->RequiredFeatures.empty())
3728 continue;
3729 FeatureBitsets.emplace_back();
3730 for (const auto *F : MI->RequiredFeatures)
3731 FeatureBitsets.back().push_back(x: F->TheDef);
3732 }
3733
3734 llvm::sort(C&: FeatureBitsets,
3735 Comp: [&](ArrayRef<const Record *> A, ArrayRef<const Record *> B) {
3736 if (A.size() != B.size())
3737 return A.size() < B.size();
3738 for (const auto [ARec, BRec] : zip_equal(t&: A, u&: B)) {
3739 if (ARec->getName() != BRec->getName())
3740 return ARec->getName() < BRec->getName();
3741 }
3742 return false;
3743 });
3744 FeatureBitsets.erase(first: llvm::unique(R&: FeatureBitsets), last: FeatureBitsets.end());
3745 OS << "// Feature bitsets.\n"
3746 << "enum : " << getMinimalTypeForRange(Range: FeatureBitsets.size()) << " {\n"
3747 << " AMFBS_None,\n";
3748 for (const auto &FeatureBitset : FeatureBitsets) {
3749 if (FeatureBitset.empty())
3750 continue;
3751 OS << " " << getNameForFeatureBitset(FeatureBitset) << ",\n";
3752 }
3753 OS << "};\n\n"
3754 << "static constexpr FeatureBitset FeatureBitsets[] = {\n"
3755 << " {}, // AMFBS_None\n";
3756 for (const auto &FeatureBitset : FeatureBitsets) {
3757 if (FeatureBitset.empty())
3758 continue;
3759 OS << " {";
3760 for (const auto &Feature : FeatureBitset) {
3761 const auto &I = Info.SubtargetFeatures.find(x: Feature);
3762 assert(I != Info.SubtargetFeatures.end() && "Didn't import predicate?");
3763 OS << I->second.getEnumBitName() << ", ";
3764 }
3765 OS << "}, // " << getNameForFeatureBitset(FeatureBitset) << "\n";
3766 }
3767 OS << "};\n\n";
3768
3769 // Emit the static match table; unused classes get initialized to 0 which is
3770 // guaranteed to be InvalidMatchClass.
3771 //
3772 // FIXME: We can reduce the size of this table very easily. First, we change
3773 // it so that store the kinds in separate bit-fields for each index, which
3774 // only needs to be the max width used for classes at that index (we also need
3775 // to reject based on this during classification). If we then make sure to
3776 // order the match kinds appropriately (putting mnemonics last), then we
3777 // should only end up using a few bits for each class, especially the ones
3778 // following the mnemonic.
3779 OS << "namespace {\n";
3780 OS << " struct MatchEntry {\n";
3781 OS << " " << getMinimalTypeForRange(Range: MaxMnemonicIndex) << " Mnemonic;\n";
3782 OS << " uint32_t Opcode;\n";
3783 OS << " " << getMinimalTypeForRange(Range: NumConverters) << " ConvertFn;\n";
3784 OS << " " << getMinimalTypeForRange(Range: FeatureBitsets.size())
3785 << " RequiredFeaturesIdx;\n";
3786 OS << " "
3787 << getMinimalTypeForRange(
3788 Range: std::distance(first: Info.Classes.begin(), last: Info.Classes.end()) +
3789 2 /* Include 'InvalidMatchClass' and 'OptionalMatchClass' */)
3790 << " Classes[" << MaxNumOperands << "];\n";
3791 OS << " StringRef getMnemonic() const {\n";
3792 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
3793 OS << " MnemonicTable[Mnemonic]);\n";
3794 OS << " }\n";
3795 OS << " };\n\n";
3796
3797 OS << " // Predicate for searching for an opcode.\n";
3798 OS << " struct LessOpcode {\n";
3799 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
3800 OS << " return LHS.getMnemonic() < RHS;\n";
3801 OS << " }\n";
3802 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
3803 OS << " return LHS < RHS.getMnemonic();\n";
3804 OS << " }\n";
3805 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
3806 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
3807 OS << " }\n";
3808 OS << " };\n";
3809
3810 OS << "} // end anonymous namespace\n\n";
3811
3812 unsigned VariantCount = Target.getAsmParserVariantCount();
3813 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3814 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3815 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3816
3817 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
3818
3819 for (const auto &MI : Info.Matchables) {
3820 if (MI->AsmVariantID != AsmVariantNo)
3821 continue;
3822
3823 // Store a pascal-style length byte in the mnemonic.
3824 std::string LenMnemonic =
3825 char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
3826 OS << " { " << *StringTable.GetStringOffset(Str: LenMnemonic) << " /* "
3827 << MI->Mnemonic << " */, " << Target.getInstNamespace()
3828 << "::" << MI->getResultInst()->getName() << ", "
3829 << MI->ConversionFnKind << ", ";
3830
3831 // Write the required features mask.
3832 OS << "AMFBS";
3833 if (MI->RequiredFeatures.empty())
3834 OS << "_None";
3835 else
3836 for (const auto &F : MI->RequiredFeatures)
3837 OS << '_' << F->TheDef->getName();
3838
3839 OS << ", { ";
3840 ListSeparator LS;
3841 for (const MatchableInfo::AsmOperand &Op : MI->AsmOperands)
3842 OS << LS << Op.Class->Name;
3843 OS << " }, },\n";
3844 }
3845
3846 OS << "};\n\n";
3847 }
3848
3849 OS << "#include \"llvm/Support/Debug.h\"\n";
3850 OS << "#include \"llvm/Support/Format.h\"\n\n";
3851
3852 // Finally, build the match function.
3853 OS << "unsigned " << Target.getName() << ClassName << "::\n"
3854 << "MatchInstructionImpl(const OperandVector &Operands,\n";
3855 OS << " MCInst &Inst,\n";
3856 if (ReportMultipleNearMisses)
3857 OS << " SmallVectorImpl<NearMissInfo> *NearMisses,\n";
3858 else
3859 OS << " uint64_t &ErrorInfo,\n"
3860 << " FeatureBitset &MissingFeatures,\n";
3861 OS << " bool matchingInlineAsm, unsigned VariantID) {\n";
3862
3863 if (!ReportMultipleNearMisses) {
3864 OS << " // Eliminate obvious mismatches.\n";
3865 OS << " if (Operands.size() > " << (MaxNumOperands + HasMnemonicFirst)
3866 << ") {\n";
3867 OS << " ErrorInfo = " << (MaxNumOperands + HasMnemonicFirst) << ";\n";
3868 OS << " return Match_InvalidOperand;\n";
3869 OS << " }\n\n";
3870 }
3871
3872 // Emit code to get the available features.
3873 OS << " // Get the current feature set.\n";
3874 OS << " const FeatureBitset &AvailableFeatures = "
3875 "getAvailableFeatures();\n\n";
3876
3877 OS << " // Get the instruction mnemonic, which is the first token.\n";
3878 if (HasMnemonicFirst) {
3879 OS << " StringRef Mnemonic = ((" << Target.getName()
3880 << "Operand &)*Operands[0]).getToken();\n\n";
3881 } else {
3882 OS << " StringRef Mnemonic;\n";
3883 OS << " if (Operands[0]->isToken())\n";
3884 OS << " Mnemonic = ((" << Target.getName()
3885 << "Operand &)*Operands[0]).getToken();\n\n";
3886 }
3887
3888 if (HasMnemonicAliases) {
3889 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3890 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
3891 }
3892
3893 // Emit code to compute the class list for this operand vector.
3894 if (!ReportMultipleNearMisses) {
3895 OS << " // Some state to try to produce better error messages.\n";
3896 OS << " bool HadMatchOtherThanFeatures = false;\n";
3897 OS << " bool HadMatchOtherThanPredicate = false;\n";
3898 OS << " unsigned RetCode = Match_InvalidOperand;\n";
3899 OS << " MissingFeatures.set();\n";
3900 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
3901 OS << " // wrong for all instances of the instruction.\n";
3902 OS << " ErrorInfo = ~0ULL;\n";
3903 }
3904
3905 if (HasOptionalOperands)
3906 OS << " SmallBitVector OptionalOperandsMask("
3907 << MaxNumOperands + HasMnemonicFirst << ");\n";
3908
3909 // Emit code to search the table.
3910 OS << " // Find the appropriate table for this asm variant.\n";
3911 OS << " const MatchEntry *Start, *End;\n";
3912 OS << " switch (VariantID) {\n";
3913 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3914 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3915 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3916 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3917 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3918 << "); End = std::end(MatchTable" << VC << "); break;\n";
3919 }
3920 OS << " }\n";
3921
3922 OS << " // Search the table.\n";
3923 if (HasMnemonicFirst) {
3924 OS << " auto MnemonicRange = "
3925 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3926 } else {
3927 OS << " auto MnemonicRange = std::pair(Start, End);\n";
3928 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3929 OS << " if (!Mnemonic.empty())\n";
3930 OS << " MnemonicRange = "
3931 "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3932 }
3933
3934 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"AsmMatcher: found \" "
3935 "<<\n"
3936 << " std::distance(MnemonicRange.first, MnemonicRange.second) <<\n"
3937 << " \" encodings with mnemonic '\" << Mnemonic << \"'\\n\");\n\n";
3938
3939 OS << " // Return a more specific error code if no mnemonics match.\n";
3940 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3941 OS << " return Match_MnemonicFail;\n\n";
3942
3943 if (ReportMultipleNearMisses) {
3944 OS << " // First operand near-miss of each opcode that mismatched in\n";
3945 OS << " // more than one operand. Used only if no opcode yields a\n";
3946 OS << " // near-miss of its own (see below).\n";
3947 OS << " SmallVector<NearMissInfo, 4> MultiMismatchFallback;\n\n";
3948 }
3949
3950 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3951 << "*ie = MnemonicRange.second;\n";
3952 OS << " it != ie; ++it) {\n";
3953 OS << " const FeatureBitset &RequiredFeatures = "
3954 "FeatureBitsets[it->RequiredFeaturesIdx];\n";
3955 OS << " bool HasRequiredFeatures =\n";
3956 OS << " (AvailableFeatures & RequiredFeatures) == RequiredFeatures;\n";
3957 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Trying to match "
3958 "opcode \"\n";
3959 OS << " << MII.getName(it->Opcode) "
3960 "<< \"\\n\");\n";
3961
3962 if (ReportMultipleNearMisses) {
3963 OS << " // Some state to record ways in which this instruction did not "
3964 "match.\n";
3965 OS << " NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n";
3966 OS << " NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n";
3967 OS << " NearMissInfo EarlyPredicateNearMiss = "
3968 "NearMissInfo::getSuccess();\n";
3969 OS << " NearMissInfo LatePredicateNearMiss = "
3970 "NearMissInfo::getSuccess();\n";
3971 OS << " bool MultipleInvalidOperands = false;\n";
3972 }
3973
3974 if (HasMnemonicFirst) {
3975 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3976 OS << " assert(Mnemonic == it->getMnemonic());\n";
3977 }
3978
3979 // Emit check that the subclasses match.
3980 if (!ReportMultipleNearMisses)
3981 OS << " bool OperandsValid = true;\n";
3982 if (HasOptionalOperands)
3983 OS << " OptionalOperandsMask.reset(0, "
3984 << MaxNumOperands + HasMnemonicFirst << ");\n";
3985 OS << " unsigned ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")
3986 << ";\n";
3987 OS << " for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")
3988 << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";
3989 OS << " auto Formal = "
3990 << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";
3991 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3992 OS << " dbgs() << \" Matching formal operand class \" "
3993 "<< getMatchClassName(Formal)\n";
3994 OS << " << \" against actual operand at index \" "
3995 "<< ActualIdx);\n";
3996 OS << " if (ActualIdx < Operands.size())\n";
3997 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \" (\";\n";
3998 OS << " Operands[ActualIdx]->print(dbgs(), "
3999 "getContext().getAsmInfo()); dbgs() << "
4000 "\"): \");\n";
4001 OS << " else\n";
4002 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \": \");\n";
4003 OS << " if (ActualIdx >= Operands.size()) {\n";
4004 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"actual operand "
4005 "index out of range\\n\");\n";
4006 if (ReportMultipleNearMisses) {
4007 OS << " bool ThisOperandValid = (Formal == "
4008 << "InvalidMatchClass) || "
4009 "isSubclass(Formal, OptionalMatchClass);\n";
4010 OS << " if (!ThisOperandValid) {\n";
4011 OS << " if (!OperandNearMiss) {\n";
4012 OS << " // Record info about match failure for later use.\n";
4013 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording "
4014 "too-few-operands near miss\\n\");\n";
4015 OS << " OperandNearMiss =\n";
4016 OS << " NearMissInfo::getTooFewOperands(Formal, "
4017 "it->Opcode);\n";
4018 OS << " } else if (OperandNearMiss.getKind() != "
4019 "NearMissInfo::NearMissTooFewOperands) {\n";
4020 OS << " // If more than one operand is invalid, give up on this "
4021 "match entry.\n";
4022 OS << " DEBUG_WITH_TYPE(\n";
4023 OS << " \"asm-matcher\",\n";
4024 OS << " dbgs() << \"second invalid operand, giving up on "
4025 "this opcode\\n\");\n";
4026 OS << " MultipleInvalidOperands = true;\n";
4027 OS << " break;\n";
4028 OS << " }\n";
4029 OS << " } else {\n";
4030 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal "
4031 "operand not required\\n\");\n";
4032 OS << " if (isSubclass(Formal, OptionalMatchClass)) {\n";
4033 OS << " OptionalOperandsMask.set("
4034 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
4035 OS << " }\n";
4036 OS << " }\n";
4037 OS << " continue;\n";
4038 } else {
4039 OS << " if (Formal == InvalidMatchClass) {\n";
4040 if (HasOptionalOperands) {
4041 OS << " OptionalOperandsMask.set("
4042 << (HasMnemonicFirst ? "FormalIdx + 1, " : "FormalIdx, ")
4043 << MaxNumOperands + HasMnemonicFirst << ");\n";
4044 }
4045 OS << " break;\n";
4046 OS << " }\n";
4047 OS << " if (isSubclass(Formal, OptionalMatchClass)) {\n";
4048 if (HasOptionalOperands)
4049 OS << " OptionalOperandsMask.set("
4050 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
4051 OS << " continue;\n";
4052 OS << " }\n";
4053 OS << " OperandsValid = false;\n";
4054 OS << " ErrorInfo = ActualIdx;\n";
4055 OS << " break;\n";
4056 }
4057 OS << " }\n";
4058 OS << " MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";
4059 OS << " unsigned Diag = validateOperandClass(Actual, Formal, *STI);\n";
4060 OS << " if (Diag == Match_Success) {\n";
4061 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
4062 OS << " dbgs() << \"match success using generic "
4063 "matcher\\n\");\n";
4064 OS << " ++ActualIdx;\n";
4065 OS << " continue;\n";
4066 OS << " }\n";
4067 OS << " // If the generic handler indicates an invalid operand\n";
4068 OS << " // failure, check for a special case.\n";
4069 OS << " if (Diag != Match_Success) {\n";
4070 OS << " unsigned TargetDiag = validateTargetOperandClass(Actual, "
4071 "Formal);\n";
4072 OS << " if (TargetDiag == Match_Success) {\n";
4073 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
4074 OS << " dbgs() << \"match success using target "
4075 "matcher\\n\");\n";
4076 OS << " ++ActualIdx;\n";
4077 OS << " continue;\n";
4078 OS << " }\n";
4079 OS << " // If the target matcher returned a specific error code use\n";
4080 OS << " // that, else use the one from the generic matcher.\n";
4081 OS << " if (TargetDiag != Match_InvalidOperand && "
4082 "HasRequiredFeatures)\n";
4083 OS << " Diag = TargetDiag;\n";
4084 OS << " }\n";
4085 OS << " // If current formal operand wasn't matched and it is optional\n"
4086 << " // then try to match next formal operand\n";
4087 OS << " if (Diag == Match_InvalidOperand "
4088 << "&& isSubclass(Formal, OptionalMatchClass)) {\n";
4089 if (HasOptionalOperands)
4090 OS << " OptionalOperandsMask.set("
4091 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
4092 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"ignoring "
4093 "optional operand\\n\");\n";
4094 OS << " continue;\n";
4095 OS << " }\n";
4096
4097 if (ReportMultipleNearMisses) {
4098 OS << " if (!OperandNearMiss) {\n";
4099 OS << " // If this is the first invalid operand we have seen, "
4100 "record some\n";
4101 OS << " // information about it.\n";
4102 OS << " DEBUG_WITH_TYPE(\n";
4103 OS << " \"asm-matcher\",\n";
4104 OS << " dbgs()\n";
4105 OS << " << \"operand match failed, recording near-miss with "
4106 "diag code \"\n";
4107 OS << " << Diag << \"\\n\");\n";
4108 OS << " OperandNearMiss =\n";
4109 OS << " NearMissInfo::getMissedOperand(Diag, Formal, "
4110 "it->Opcode, ActualIdx);\n";
4111 OS << " ++ActualIdx;\n";
4112 OS << " } else {\n";
4113 OS << " // If more than one operand is invalid, give up on this "
4114 "match entry.\n";
4115 OS << " DEBUG_WITH_TYPE(\n";
4116 OS << " \"asm-matcher\",\n";
4117 OS << " dbgs() << \"second operand mismatch, skipping this "
4118 "opcode\\n\");\n";
4119 OS << " MultipleInvalidOperands = true;\n";
4120 OS << " break;\n";
4121 OS << " }\n";
4122 OS << " }\n\n";
4123 OS << " // Reject surplus operands as one more operand mismatch.\n";
4124 OS << " if (!MultipleInvalidOperands && ActualIdx < Operands.size()) "
4125 "{\n";
4126 OS << " if (!OperandNearMiss) {\n";
4127 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"too many "
4128 "operands, recording near-miss at index \"\n";
4129 OS << " << ActualIdx << \"\\n\");\n";
4130 OS << " OperandNearMiss = NearMissInfo::getMissedOperand(\n";
4131 OS << " Match_InvalidOperand, InvalidMatchClass, it->Opcode, "
4132 "ActualIdx);\n";
4133 OS << " } else {\n";
4134 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"too many "
4135 "operands after an earlier mismatch, skipping this opcode\\n\");\n";
4136 OS << " MultipleInvalidOperands = true;\n";
4137 OS << " }\n";
4138 OS << " }\n\n";
4139 } else {
4140 OS << " // If this operand is broken for all of the instances of "
4141 "this\n";
4142 OS << " // mnemonic, keep track of it so we can report loc info.\n";
4143 OS << " // If we already had a match that only failed due to a\n";
4144 OS << " // target predicate, that diagnostic is preferred.\n";
4145 OS << " if (!HadMatchOtherThanPredicate &&\n";
4146 OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) "
4147 "{\n";
4148 OS << " if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag "
4149 "!= Match_InvalidOperand))\n";
4150 OS << " RetCode = Diag;\n";
4151 OS << " ErrorInfo = ActualIdx;\n";
4152 OS << " }\n";
4153 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
4154 OS << " OperandsValid = false;\n";
4155 OS << " break;\n";
4156 OS << " }\n\n";
4157 }
4158
4159 if (ReportMultipleNearMisses)
4160 OS << " if (MultipleInvalidOperands) {\n";
4161 else
4162 OS << " if (!OperandsValid) {\n";
4163 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4164 "multiple \"\n";
4165 OS << " \"operand mismatches, "
4166 "ignoring \"\n";
4167 OS << " \"this opcode\\n\");\n";
4168 if (ReportMultipleNearMisses) {
4169 OS << " // Too many invalid operands to report a single near-miss;\n";
4170 OS << " // keep the first one as a fallback in case no opcode\n";
4171 OS << " // matches more closely.\n";
4172 OS << " if (OperandNearMiss)\n";
4173 OS << " MultiMismatchFallback.push_back(OperandNearMiss);\n";
4174 }
4175 OS << " continue;\n";
4176 OS << " }\n";
4177
4178 // Emit check that the required features are available.
4179 OS << " if (!HasRequiredFeatures) {\n";
4180 if (!ReportMultipleNearMisses)
4181 OS << " HadMatchOtherThanFeatures = true;\n";
4182 OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
4183 "~AvailableFeatures;\n";
4184 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
4185 "features:\";\n";
4186 OS << " for (unsigned I = 0, E = "
4187 "NewMissingFeatures.size(); I != E; ++I)\n";
4188 OS << " if (NewMissingFeatures[I])\n";
4189 OS << " dbgs() << ' ' << I;\n";
4190 OS << " dbgs() << \"\\n\");\n";
4191 if (ReportMultipleNearMisses) {
4192 OS << " FeaturesNearMiss = "
4193 "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
4194 } else {
4195 OS << " if (NewMissingFeatures.count() <=\n"
4196 " MissingFeatures.count())\n";
4197 OS << " MissingFeatures = NewMissingFeatures;\n";
4198 OS << " continue;\n";
4199 }
4200 OS << " }\n";
4201 OS << "\n";
4202 OS << " Inst.clear();\n\n";
4203 OS << " Inst.setOpcode(it->Opcode);\n";
4204 // Verify the instruction with the target-specific match predicate function.
4205 OS << " // We have a potential match but have not rendered the operands.\n"
4206 << " // Check the target predicate to handle any context sensitive\n"
4207 " // constraints.\n"
4208 << " // For example, Ties that are referenced multiple times must be\n"
4209 " // checked here to ensure the input is the same for each match\n"
4210 " // constraints. If we leave it any later the ties will have been\n"
4211 " // canonicalized\n"
4212 << " unsigned MatchResult;\n"
4213 << " if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "
4214 "Operands)) != Match_Success) {\n"
4215 << " Inst.clear();\n";
4216 OS << " DEBUG_WITH_TYPE(\n";
4217 OS << " \"asm-matcher\",\n";
4218 OS << " dbgs() << \"Early target match predicate failed with diag "
4219 "code \"\n";
4220 OS << " << MatchResult << \"\\n\");\n";
4221 if (ReportMultipleNearMisses) {
4222 OS << " EarlyPredicateNearMiss = "
4223 "NearMissInfo::getMissedPredicate(MatchResult);\n";
4224 } else {
4225 OS << " RetCode = MatchResult;\n"
4226 << " HadMatchOtherThanPredicate = true;\n"
4227 << " continue;\n";
4228 }
4229 OS << " }\n\n";
4230
4231 if (ReportMultipleNearMisses) {
4232 OS << " // If we did not successfully match the operands, then we can't "
4233 "convert to\n";
4234 OS << " // an MCInst, so bail out on this instruction variant now.\n";
4235 OS << " if (OperandNearMiss) {\n";
4236 OS << " // If the operand mismatch was the only problem, report it as "
4237 "a near-miss.\n";
4238 OS << " if (NearMisses && !FeaturesNearMiss && "
4239 "!EarlyPredicateNearMiss) {\n";
4240 OS << " DEBUG_WITH_TYPE(\n";
4241 OS << " \"asm-matcher\",\n";
4242 OS << " dbgs()\n";
4243 OS << " << \"Opcode result: one mismatched operand, adding "
4244 "near-miss\\n\");\n";
4245 OS << " NearMisses->push_back(OperandNearMiss);\n";
4246 OS << " } else {\n";
4247 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4248 "multiple \"\n";
4249 OS << " \"types of "
4250 "mismatch, so not \"\n";
4251 OS << " \"reporting "
4252 "near-miss\\n\");\n";
4253 OS << " }\n";
4254 OS << " continue;\n";
4255 OS << " }\n\n";
4256 }
4257
4258 // When converting parsed operands to MCInst we need to know whether optional
4259 // operands were parsed or not so that we can choose the correct converter
4260 // function. We also need to know this when checking tied operand constraints.
4261 // DefaultsOffset is an array of deltas between the formal (MCInst) and the
4262 // actual (parsed operand array) operand indices. When all optional operands
4263 // are present, all elements of the array are zeros. If some of the optional
4264 // operands are absent, the array might look like '0, 0, 1, 1, 1, 2, 2, 3',
4265 // where each increment in value reflects the absence of an optional operand.
4266 if (HasOptionalOperands) {
4267 OS << " unsigned DefaultsOffset[" << (MaxNumOperands + 1)
4268 << "] = { 0 };\n";
4269 OS << " assert(OptionalOperandsMask.size() == "
4270 << (MaxNumOperands + HasMnemonicFirst) << ");\n";
4271 OS << " for (unsigned i = 0, NumDefaults = 0; i < " << (MaxNumOperands)
4272 << "; ++i) {\n";
4273 OS << " NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);\n";
4274 OS << " DefaultsOffset[i + 1] = NumDefaults;\n";
4275 OS << " }\n\n";
4276 }
4277
4278 OS << " if (matchingInlineAsm) {\n";
4279 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
4280 if (!ReportMultipleNearMisses) {
4281 if (HasOptionalOperands) {
4282 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4283 "Operands,\n";
4284 OS << " DefaultsOffset, "
4285 "ErrorInfo))\n";
4286 } else {
4287 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4288 "Operands,\n";
4289 OS << " ErrorInfo))\n";
4290 }
4291 OS << " return Match_InvalidTiedOperand;\n";
4292 OS << "\n";
4293 }
4294 OS << " return Match_Success;\n";
4295 OS << " }\n\n";
4296 OS << " // We have selected a definite instruction, convert the parsed\n"
4297 << " // operands into the appropriate MCInst.\n";
4298 if (HasOptionalOperands) {
4299 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,\n"
4300 << " OptionalOperandsMask, DefaultsOffset);\n";
4301 } else {
4302 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
4303 }
4304 OS << "\n";
4305
4306 // Verify the instruction with the target-specific match predicate function.
4307 OS << " // We have a potential match. Check the target predicate to\n"
4308 << " // handle any context sensitive constraints.\n"
4309 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
4310 << " Match_Success) {\n"
4311 << " DEBUG_WITH_TYPE(\"asm-matcher\",\n"
4312 << " dbgs() << \"Target match predicate failed with "
4313 "diag code \"\n"
4314 << " << MatchResult << \"\\n\");\n"
4315 << " Inst.clear();\n";
4316 if (ReportMultipleNearMisses) {
4317 OS << " LatePredicateNearMiss = "
4318 "NearMissInfo::getMissedPredicate(MatchResult);\n";
4319 } else {
4320 OS << " RetCode = MatchResult;\n"
4321 << " HadMatchOtherThanPredicate = true;\n"
4322 << " continue;\n";
4323 }
4324 OS << " }\n\n";
4325
4326 if (ReportMultipleNearMisses) {
4327 OS << " int NumNearMisses = ((int)(bool)OperandNearMiss +\n";
4328 OS << " (int)(bool)FeaturesNearMiss +\n";
4329 OS << " (int)(bool)EarlyPredicateNearMiss +\n";
4330 OS << " (int)(bool)LatePredicateNearMiss);\n";
4331 OS << " if (NumNearMisses == 1) {\n";
4332 OS << " // We had exactly one type of near-miss, so add that to the "
4333 "list.\n";
4334 OS << " assert(!OperandNearMiss && \"OperandNearMiss was handled "
4335 "earlier\");\n";
4336 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4337 "found one type of \"\n";
4338 OS << " \"mismatch, so "
4339 "reporting a \"\n";
4340 OS << " \"near-miss\\n\");\n";
4341 OS << " if (NearMisses && FeaturesNearMiss)\n";
4342 OS << " NearMisses->push_back(FeaturesNearMiss);\n";
4343 OS << " else if (NearMisses && EarlyPredicateNearMiss)\n";
4344 OS << " NearMisses->push_back(EarlyPredicateNearMiss);\n";
4345 OS << " else if (NearMisses && LatePredicateNearMiss)\n";
4346 OS << " NearMisses->push_back(LatePredicateNearMiss);\n";
4347 OS << "\n";
4348 OS << " continue;\n";
4349 OS << " } else if (NumNearMisses > 1) {\n";
4350 OS << " // This instruction missed in more than one way, so ignore "
4351 "it.\n";
4352 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4353 "multiple \"\n";
4354 OS << " \"types of mismatch, "
4355 "so not \"\n";
4356 OS << " \"reporting "
4357 "near-miss\\n\");\n";
4358 OS << " continue;\n";
4359 OS << " }\n";
4360 }
4361
4362 // Call the post-processing function, if used.
4363 StringRef InsnCleanupFn = AsmParser->getValueAsString(FieldName: "AsmParserInstCleanup");
4364 if (!InsnCleanupFn.empty())
4365 OS << " " << InsnCleanupFn << "(Inst);\n";
4366
4367 if (HasDeprecation) {
4368 OS << " std::string Info;\n";
4369 OS << " if "
4370 "(!getParser().getTargetParser().getTargetOptions()."
4371 "MCNoDeprecatedWarn &&\n";
4372 OS << " MII.getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
4373 OS << " SMLoc Loc = ((" << Target.getName()
4374 << "Operand &)*Operands[0]).getStartLoc();\n";
4375 OS << " getParser().Warning(Loc, Info, {});\n";
4376 OS << " }\n";
4377 }
4378
4379 if (!ReportMultipleNearMisses) {
4380 if (HasOptionalOperands) {
4381 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4382 "Operands,\n";
4383 OS << " DefaultsOffset, "
4384 "ErrorInfo))\n";
4385 } else {
4386 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4387 "Operands,\n";
4388 OS << " ErrorInfo))\n";
4389 }
4390 OS << " return Match_InvalidTiedOperand;\n";
4391 OS << "\n";
4392 }
4393
4394 OS << " DEBUG_WITH_TYPE(\n";
4395 OS << " \"asm-matcher\",\n";
4396 OS << " dbgs() << \"Opcode result: complete match, selecting this "
4397 "opcode\\n\");\n";
4398 OS << " return Match_Success;\n";
4399 OS << " }\n\n";
4400
4401 if (ReportMultipleNearMisses) {
4402 OS << " // No instruction variants matched exactly. If nothing produced\n";
4403 OS << " // a near-miss, fall back to the multi-mismatch list so we can\n";
4404 OS << " // still give a specific diagnostic rather than a generic\n";
4405 OS << " // \"invalid instruction\".\n";
4406 OS << " if (NearMisses && NearMisses->empty())\n";
4407 OS << " NearMisses->append(MultiMismatchFallback.begin(),\n";
4408 OS << " MultiMismatchFallback.end());\n";
4409 OS << " return Match_NearMisses;\n";
4410 } else {
4411 OS << " // Okay, we had no match. Try to return a useful error code.\n";
4412 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
4413 OS << " return RetCode;\n\n";
4414 OS << " ErrorInfo = 0;\n";
4415 OS << " return Match_MissingFeature;\n";
4416 }
4417 OS << "}\n\n";
4418
4419 if (!Info.OperandMatchInfo.empty())
4420 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
4421 MaxMnemonicIndex, MaxFeaturesIndex: FeatureBitsets.size(),
4422 HasMnemonicFirst, AsmParser: *AsmParser);
4423
4424 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
4425
4426 OS << "\n#ifdef GET_MNEMONIC_SPELL_CHECKER\n";
4427 OS << "#undef GET_MNEMONIC_SPELL_CHECKER\n\n";
4428
4429 emitMnemonicSpellChecker(OS, Target, VariantCount);
4430
4431 OS << "#endif // GET_MNEMONIC_SPELL_CHECKER\n\n";
4432
4433 OS << "\n#ifdef GET_MNEMONIC_CHECKER\n";
4434 OS << "#undef GET_MNEMONIC_CHECKER\n\n";
4435
4436 emitMnemonicChecker(OS, Target, VariantCount, HasMnemonicFirst,
4437 HasMnemonicAliases);
4438
4439 OS << "#endif // GET_MNEMONIC_CHECKER\n\n";
4440}
4441
4442static TableGen::Emitter::OptClass<AsmMatcherEmitter>
4443 X("gen-asm-matcher", "Generate assembly instruction matcher");
4444