1//===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend emits a target specifier matcher for converting parsed
10// assembly operands in the MCInst structures. It also emits a matcher for
11// custom operand parsing.
12//
13// Converting assembly operands into MCInst structures
14// ---------------------------------------------------
15//
16// The input to the target specific matcher is a list of literal tokens and
17// operands. The target specific parser should generally eliminate any syntax
18// which is not relevant for matching; for example, comma tokens should have
19// already been consumed and eliminated by the parser. Most instructions will
20// end up with a single literal token (the instruction name) and some number of
21// operands.
22//
23// Some example inputs, for X86:
24// 'addl' (immediate ...) (register ...)
25// 'add' (immediate ...) (memory ...)
26// 'call' '*' %epc
27//
28// The assembly matcher is responsible for converting this input into a precise
29// machine instruction (i.e., an instruction with a well defined encoding). This
30// mapping has several properties which complicate matching:
31//
32// - It may be ambiguous; many architectures can legally encode particular
33// variants of an instruction in different ways (for example, using a smaller
34// encoding for small immediates). Such ambiguities should never be
35// arbitrarily resolved by the assembler, the assembler is always responsible
36// for choosing the "best" available instruction.
37//
38// - It may depend on the subtarget or the assembler context. Instructions
39// which are invalid for the current mode, but otherwise unambiguous (e.g.,
40// an SSE instruction in a file being assembled for i486) should be accepted
41// and rejected by the assembler front end. However, if the proper encoding
42// for an instruction is dependent on the assembler context then the matcher
43// is responsible for selecting the correct machine instruction for the
44// current mode.
45//
46// The core matching algorithm attempts to exploit the regularity in most
47// instruction sets to quickly determine the set of possibly matching
48// instructions, and the simplify the generated code. Additionally, this helps
49// to ensure that the ambiguities are intentionally resolved by the user.
50//
51// The matching is divided into two distinct phases:
52//
53// 1. Classification: Each operand is mapped to the unique set which (a)
54// contains it, and (b) is the largest such subset for which a single
55// instruction could match all members.
56//
57// For register classes, we can generate these subgroups automatically. For
58// arbitrary operands, we expect the user to define the classes and their
59// relations to one another (for example, 8-bit signed immediates as a
60// subset of 32-bit immediates).
61//
62// By partitioning the operands in this way, we guarantee that for any
63// tuple of classes, any single instruction must match either all or none
64// of the sets of operands which could classify to that tuple.
65//
66// In addition, the subset relation amongst classes induces a partial order
67// on such tuples, which we use to resolve ambiguities.
68//
69// 2. The input can now be treated as a tuple of classes (static tokens are
70// simple singleton sets). Each such tuple should generally map to a single
71// instruction (we currently ignore cases where this isn't true, whee!!!),
72// which we can emit a simple matcher for.
73//
74// Custom Operand Parsing
75// ----------------------
76//
77// Some targets need a custom way to parse operands, some specific instructions
78// can contain arguments that can represent processor flags and other kinds of
79// identifiers that need to be mapped to specific values in the final encoded
80// instructions. The target specific custom operand parsing works in the
81// following way:
82//
83// 1. A operand match table is built, each entry contains a mnemonic, an
84// operand class, a mask for all operand positions for that same
85// class/mnemonic and target features to be checked while trying to match.
86//
87// 2. The operand matcher will try every possible entry with the same
88// mnemonic and will check if the target feature for this mnemonic also
89// matches. After that, if the operand to be matched has its index
90// present in the mask, a successful match occurs. Otherwise, fallback
91// to the regular operand parsing.
92//
93// 3. For a match success, each operand class that has a 'ParserMethod'
94// becomes part of a switch from where the custom method is called.
95//
96//===----------------------------------------------------------------------===//
97
98#include "Common/CodeGenInstAlias.h"
99#include "Common/CodeGenInstruction.h"
100#include "Common/CodeGenRegisters.h"
101#include "Common/CodeGenTarget.h"
102#include "Common/SubtargetFeatureInfo.h"
103#include "Common/Types.h"
104#include "llvm/ADT/CachedHashString.h"
105#include "llvm/ADT/PointerUnion.h"
106#include "llvm/ADT/STLExtras.h"
107#include "llvm/ADT/SmallPtrSet.h"
108#include "llvm/ADT/SmallVector.h"
109#include "llvm/ADT/StringExtras.h"
110#include "llvm/Support/CommandLine.h"
111#include "llvm/Support/Debug.h"
112#include "llvm/Support/ErrorHandling.h"
113#include "llvm/Support/FormatVariadic.h"
114#include "llvm/TableGen/Error.h"
115#include "llvm/TableGen/Record.h"
116#include "llvm/TableGen/StringMatcher.h"
117#include "llvm/TableGen/StringToOffsetTable.h"
118#include "llvm/TableGen/TableGenBackend.h"
119#include <cassert>
120#include <cctype>
121#include <forward_list>
122#include <map>
123#include <set>
124
125using namespace llvm;
126
127#define DEBUG_TYPE "asm-matcher-emitter"
128
129static cl::OptionCategory AsmMatcherEmitterCat("Options for -gen-asm-matcher");
130
131static cl::opt<std::string>
132 MatchPrefix("match-prefix", cl::init(Val: ""),
133 cl::desc("Only match instructions with the given prefix"),
134 cl::cat(AsmMatcherEmitterCat));
135
136namespace {
137class AsmMatcherInfo;
138
139// Register sets are used as keys in some second-order sets TableGen creates
140// when generating its data structures. This means that the order of two
141// RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
142// can even affect compiler output (at least seen in diagnostics produced when
143// all matches fail). So we use a type that sorts them consistently.
144using RegisterSet = std::set<const Record *, LessRecordByID>;
145
146class AsmMatcherEmitter {
147 const RecordKeeper &Records;
148
149public:
150 AsmMatcherEmitter(const RecordKeeper &R) : Records(R) {}
151
152 void run(raw_ostream &o);
153};
154
155/// ClassInfo - Helper class for storing the information about a particular
156/// class of operands which can be matched.
157struct ClassInfo {
158 enum ClassInfoKind {
159 /// Invalid kind, for use as a sentinel value.
160 Invalid = 0,
161
162 /// The class for a particular token.
163 Token,
164
165 /// The (first) register class, subsequent register classes are
166 /// RegisterClass0+1, and so on.
167 RegisterClass0,
168
169 /// The (first) register class by hwmode, subsequent register classes by
170 /// hwmode are RegisterClassByHwMode0+1, and so on.
171 RegisterClassByHwMode0 = 1 << 12,
172
173 /// The (first) user defined class, subsequent user defined classes are
174 /// UserClass0+1, and so on.
175 UserClass0 = 1 << 24
176 };
177
178 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
179 /// N) for the Nth user defined class.
180 unsigned Kind = 0;
181
182 /// SuperClasses - The super classes of this class. Note that for simplicities
183 /// sake user operands only record their immediate super class, while register
184 /// operands include all superclasses.
185 std::vector<ClassInfo *> SuperClasses;
186
187 /// Name - The full class name, suitable for use in an enum.
188 std::string Name;
189
190 /// ClassName - The unadorned generic name for this class (e.g., Token).
191 std::string ClassName;
192
193 /// ValueName - The name of the value this class represents; for a token this
194 /// is the literal token string, for an operand it is the TableGen class (or
195 /// empty if this is a derived class).
196 std::string ValueName;
197
198 /// PredicateMethod - The name of the operand method to test whether the
199 /// operand matches this class; this is not valid for Token or register kinds.
200 std::string PredicateMethod;
201
202 /// RenderMethod - The name of the operand method to add this operand to an
203 /// MCInst; this is not valid for Token or register kinds.
204 std::string RenderMethod;
205
206 /// ParserMethod - The name of the operand method to do a target specific
207 /// parsing on the operand.
208 std::string ParserMethod;
209
210 /// For register classes: the records for all the registers in this class.
211 RegisterSet Registers;
212
213 /// For custom match classes: the diagnostic kind for when the predicate
214 /// fails.
215 std::string DiagnosticType;
216
217 /// For custom match classes: the diagnostic string for when the predicate
218 /// fails.
219 std::string DiagnosticString;
220
221 /// Is this operand optional and not always required.
222 bool IsOptional = false;
223
224 /// DefaultMethod - The name of the method that returns the default operand
225 /// for optional operand
226 std::string DefaultMethod;
227
228public:
229 /// isRegisterClass() - Check if this is a register class.
230 bool isRegisterClass() const {
231 return Kind >= RegisterClass0 && Kind < RegisterClassByHwMode0;
232 }
233
234 bool isRegisterClassByHwMode() const {
235 return Kind >= RegisterClassByHwMode0 && Kind < UserClass0;
236 }
237
238 /// isUserClass() - Check if this is a user defined class.
239 bool isUserClass() const { return Kind >= UserClass0; }
240
241 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
242 /// are related if they are in the same class hierarchy.
243 bool isRelatedTo(const ClassInfo &RHS) const {
244 // Tokens are only related to tokens.
245 if (Kind == Token || RHS.Kind == Token)
246 return Kind == Token && RHS.Kind == Token;
247
248 // Registers classes are only related to registers classes, and only if
249 // their intersection is non-empty.
250 if (isRegisterClass() || RHS.isRegisterClass()) {
251 if (!isRegisterClass() || !RHS.isRegisterClass())
252 return false;
253
254 std::vector<const Record *> Tmp;
255 std::set_intersection(first1: Registers.begin(), last1: Registers.end(),
256 first2: RHS.Registers.begin(), last2: RHS.Registers.end(),
257 result: std::back_inserter(x&: Tmp), comp: LessRecordByID());
258
259 return !Tmp.empty();
260 }
261
262 if (isRegisterClassByHwMode() || RHS.isRegisterClassByHwMode())
263 return isRegisterClassByHwMode() == RHS.isRegisterClassByHwMode();
264
265 // Otherwise we have two users operands; they are related if they are in the
266 // same class hierarchy.
267 //
268 // FIXME: This is an oversimplification, they should only be related if they
269 // intersect, however we don't have that information.
270 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
271 const ClassInfo *Root = this;
272 while (!Root->SuperClasses.empty())
273 Root = Root->SuperClasses.front();
274
275 const ClassInfo *RHSRoot = &RHS;
276 while (!RHSRoot->SuperClasses.empty())
277 RHSRoot = RHSRoot->SuperClasses.front();
278
279 return Root == RHSRoot;
280 }
281
282 /// isSubsetOf - Test whether this class is a subset of \p RHS.
283 bool isSubsetOf(const ClassInfo &RHS) const {
284 // This is a subset of RHS if it is the same class...
285 if (this == &RHS)
286 return true;
287
288 // ... or if any of its super classes are a subset of RHS.
289 SmallVector<const ClassInfo *, 16> Worklist(SuperClasses.begin(),
290 SuperClasses.end());
291 SmallPtrSet<const ClassInfo *, 16> Visited;
292 while (!Worklist.empty()) {
293 auto *CI = Worklist.pop_back_val();
294 if (CI == &RHS)
295 return true;
296 for (auto *Super : CI->SuperClasses)
297 if (Visited.insert(Ptr: Super).second)
298 Worklist.push_back(Elt: Super);
299 }
300
301 return false;
302 }
303
304 int getTreeDepth() const {
305 int Depth = 0;
306 const ClassInfo *Root = this;
307 while (!Root->SuperClasses.empty()) {
308 Depth++;
309 Root = Root->SuperClasses.front();
310 }
311 return Depth;
312 }
313
314 const ClassInfo *findRoot() const {
315 const ClassInfo *Root = this;
316 while (!Root->SuperClasses.empty())
317 Root = Root->SuperClasses.front();
318 return Root;
319 }
320
321 /// Compare two classes. This does not produce a total ordering, but does
322 /// guarantee that subclasses are sorted before their parents, and that the
323 /// ordering is transitive.
324 bool operator<(const ClassInfo &RHS) const {
325 if (this == &RHS)
326 return false;
327
328 // First, enforce the ordering between the three different types of class.
329 // Tokens sort before registers, which sort before regclass by hwmode, which
330 // sort before user classes.
331 if (Kind == Token) {
332 if (RHS.Kind != Token)
333 return true;
334 assert(RHS.Kind == Token);
335 } else if (isRegisterClass()) {
336 if (RHS.Kind == Token)
337 return false;
338 else if (RHS.isUserClass() || RHS.isRegisterClassByHwMode())
339 return true;
340 assert(RHS.isRegisterClass());
341 } else if (isRegisterClassByHwMode()) {
342 if (RHS.Kind == Token || RHS.isRegisterClass())
343 return false;
344 else if (RHS.isUserClass())
345 return true;
346 assert(RHS.isRegisterClassByHwMode());
347 } else if (isUserClass()) {
348 if (!RHS.isUserClass())
349 return false;
350 assert(RHS.isUserClass());
351 } else {
352 llvm_unreachable("Unknown ClassInfoKind");
353 }
354
355 if (Kind == Token || isUserClass()) {
356 // Related tokens and user classes get sorted by depth in the inheritence
357 // tree (so that subclasses are before their parents).
358 if (isRelatedTo(RHS)) {
359 if (getTreeDepth() > RHS.getTreeDepth())
360 return true;
361 if (getTreeDepth() < RHS.getTreeDepth())
362 return false;
363 } else {
364 // Unrelated tokens and user classes are ordered by the name of their
365 // root nodes, so that there is a consistent ordering between
366 // unconnected trees.
367 return findRoot()->ValueName < RHS.findRoot()->ValueName;
368 }
369 } else if (isRegisterClass()) {
370 // For register sets, sort by number of registers. This guarantees that
371 // a set will always sort before all of it's strict supersets.
372 if (Registers.size() != RHS.Registers.size())
373 return Registers.size() < RHS.Registers.size();
374 } else if (isRegisterClassByHwMode()) {
375 // Ensure the MCK enum entries are in the same order as RegClassIDs. The
376 // lookup table to from RegByHwMode to concrete class relies on it.
377 return Kind < RHS.Kind;
378 } else {
379 llvm_unreachable("Unknown ClassInfoKind");
380 }
381
382 // FIXME: We should be able to just return false here, as we only need a
383 // partial order (we use stable sorts, so this is deterministic) and the
384 // name of a class shouldn't be significant. However, some of the backends
385 // accidentally rely on this behaviour, so it will have to stay like this
386 // until they are fixed.
387 return ValueName < RHS.ValueName;
388 }
389};
390
391class AsmVariantInfo {
392public:
393 StringRef RegisterPrefix;
394 StringRef TokenizingCharacters;
395 StringRef SeparatorCharacters;
396 StringRef BreakCharacters;
397 StringRef Name;
398 int AsmVariantNo;
399};
400
401bool getPreferSmallerInstructions(CodeGenTarget const &Target) {
402 return Target.getAsmParser()->getValueAsBit(FieldName: "PreferSmallerInstructions");
403}
404
405/// MatchableInfo - Helper class for storing the necessary information for an
406/// instruction or alias which is capable of being matched.
407struct MatchableInfo {
408 struct AsmOperand {
409 /// Token - This is the token that the operand came from.
410 StringRef Token;
411
412 /// The unique class instance this operand should match.
413 ClassInfo *Class = nullptr;
414
415 /// The operand name this is, if anything.
416 StringRef SrcOpName;
417
418 /// The operand name this is, before renaming for tied operands.
419 StringRef OrigSrcOpName;
420
421 /// The suboperand index within SrcOpName, or -1 for the entire operand.
422 int SubOpIdx = -1;
423
424 /// Whether the token is "isolated", i.e., it is preceded and followed
425 /// by separators.
426 bool IsIsolatedToken;
427
428 /// Register record if this token is singleton register.
429 const Record *SingletonReg = nullptr;
430
431 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
432 : Token(T), IsIsolatedToken(IsIsolatedToken) {}
433 };
434
435 /// ResOperand - This represents a single operand in the result instruction
436 /// generated by the match. In cases (like addressing modes) where a single
437 /// assembler operand expands to multiple MCOperands, this represents the
438 /// single assembler operand, not the MCOperand.
439 struct ResOperand {
440 enum {
441 /// RenderAsmOperand - This represents an operand result that is
442 /// generated by calling the render method on the assembly operand. The
443 /// corresponding AsmOperand is specified by AsmOperandNum.
444 RenderAsmOperand,
445
446 /// TiedOperand - This represents a result operand that is a duplicate of
447 /// a previous result operand.
448 TiedOperand,
449
450 /// ImmOperand - This represents an immediate value that is dumped into
451 /// the operand.
452 ImmOperand,
453
454 /// RegOperand - This represents a fixed register (potentially depending
455 /// on the HwMode) that is dumped in.
456 RegOperand,
457 } Kind;
458
459 /// Tuple containing the index of the (earlier) result operand that should
460 /// be copied from, as well as the indices of the corresponding (parsed)
461 /// operands in the asm string.
462 struct TiedOperandsTuple {
463 unsigned ResOpnd;
464 unsigned SrcOpnd1Idx;
465 unsigned SrcOpnd2Idx;
466 };
467
468 union {
469 /// This is the operand # in the AsmOperands list that this should be
470 /// copied from.
471 unsigned AsmOperandNum;
472
473 /// Description of tied operands.
474 TiedOperandsTuple TiedOperands;
475
476 /// ImmVal - This is the immediate value added to the instruction.
477 int64_t ImmVal;
478
479 /// Register - This is the register record.
480 const Record *Register;
481 };
482
483 /// MINumOperands - The number of MCInst operands populated by this
484 /// operand.
485 unsigned MINumOperands;
486
487 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
488 ResOperand X;
489 X.Kind = RenderAsmOperand;
490 X.AsmOperandNum = AsmOpNum;
491 X.MINumOperands = NumOperands;
492 return X;
493 }
494
495 static ResOperand getTiedOp(unsigned TiedOperandNum, unsigned SrcOperand1,
496 unsigned SrcOperand2) {
497 ResOperand X;
498 X.Kind = TiedOperand;
499 X.TiedOperands = {.ResOpnd: TiedOperandNum, .SrcOpnd1Idx: SrcOperand1, .SrcOpnd2Idx: SrcOperand2};
500 X.MINumOperands = 1;
501 return X;
502 }
503
504 static ResOperand getImmOp(int64_t Val) {
505 ResOperand X;
506 X.Kind = ImmOperand;
507 X.ImmVal = Val;
508 X.MINumOperands = 1;
509 return X;
510 }
511
512 static ResOperand getRegOp(const Record *Reg) {
513 ResOperand X;
514 X.Kind = RegOperand;
515 X.Register = Reg;
516 X.MINumOperands = 1;
517 return X;
518 }
519 };
520
521 /// AsmVariantID - Target's assembly syntax variant no.
522 int AsmVariantID;
523
524 /// AsmString - The assembly string for this instruction (with variants
525 /// removed), e.g. "movsx $src, $dst".
526 std::string AsmString;
527
528 /// TheDef - This is the definition of the instruction or InstAlias that this
529 /// matchable came from.
530 const Record *const TheDef;
531
532 // ResInstSize - The size of the resulting instruction for this matchable.
533 unsigned ResInstSize;
534
535 /// DefRec - This is the definition that it came from.
536 PointerUnion<const CodeGenInstruction *, const CodeGenInstAlias *> DefRec;
537
538 const CodeGenInstruction *getResultInst() const {
539 if (isa<const CodeGenInstruction *>(Val: DefRec))
540 return cast<const CodeGenInstruction *>(Val: DefRec);
541 return cast<const CodeGenInstAlias *>(Val: DefRec)->ResultInst;
542 }
543
544 /// ResOperands - This is the operand list that should be built for the result
545 /// MCInst.
546 SmallVector<ResOperand, 8> ResOperands;
547
548 /// Mnemonic - This is the first token of the matched instruction, its
549 /// mnemonic.
550 StringRef Mnemonic;
551
552 /// AsmOperands - The textual operands that this instruction matches,
553 /// annotated with a class and where in the OperandList they were defined.
554 /// This directly corresponds to the tokenized AsmString after the mnemonic is
555 /// removed.
556 SmallVector<AsmOperand, 8> AsmOperands;
557
558 /// Predicates - The required subtarget features to match this instruction.
559 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
560
561 /// ConversionFnKind - The enum value which is passed to the generated
562 /// convertToMCInst to convert parsed operands into an MCInst for this
563 /// function.
564 std::string ConversionFnKind;
565
566 /// If this instruction is deprecated in some form.
567 bool HasDeprecation = false;
568
569 /// If this is an alias, this is use to determine whether or not to using
570 /// the conversion function defined by the instruction's AsmMatchConverter
571 /// or to use the function generated by the alias.
572 bool UseInstAsmMatchConverter;
573
574 MatchableInfo(const CodeGenInstruction &CGI)
575 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef),
576 ResInstSize(TheDef->getValueAsInt(FieldName: "Size")), DefRec(&CGI),
577 UseInstAsmMatchConverter(true) {}
578
579 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
580 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
581 ResInstSize(Alias->ResultInst->TheDef->getValueAsInt(FieldName: "Size")),
582 DefRec(Alias.release()), UseInstAsmMatchConverter(TheDef->getValueAsBit(
583 FieldName: "UseInstAsmMatchConverter")) {}
584
585 // Could remove this and the dtor if PointerUnion supported unique_ptr
586 // elements with a dynamic failure/assertion (like the one below) in the case
587 // where it was copied while being in an owning state.
588 MatchableInfo(const MatchableInfo &RHS)
589 : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
590 TheDef(RHS.TheDef), ResInstSize(RHS.ResInstSize), DefRec(RHS.DefRec),
591 ResOperands(RHS.ResOperands), Mnemonic(RHS.Mnemonic),
592 AsmOperands(RHS.AsmOperands), RequiredFeatures(RHS.RequiredFeatures),
593 ConversionFnKind(RHS.ConversionFnKind),
594 HasDeprecation(RHS.HasDeprecation),
595 UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
596 assert(!isa<const CodeGenInstAlias *>(DefRec));
597 }
598
599 ~MatchableInfo() {
600 delete dyn_cast_if_present<const CodeGenInstAlias *>(Val&: DefRec);
601 }
602
603 // Two-operand aliases clone from the main matchable, but mark the second
604 // operand as a tied operand of the first for purposes of the assembler.
605 void formTwoOperandAlias(StringRef Constraint);
606
607 void initialize(const AsmMatcherInfo &Info,
608 SmallPtrSetImpl<const Record *> &SingletonRegisters,
609 AsmVariantInfo const &Variant, bool HasMnemonicFirst);
610
611 /// validate - Return true if this matchable is a valid thing to match against
612 /// and perform a bunch of validity checking.
613 bool validate(StringRef CommentDelimiter, bool IsAlias) const;
614
615 /// findAsmOperand - Find the AsmOperand with the specified name and
616 /// suboperand index.
617 int findAsmOperand(StringRef N, int SubOpIdx) const {
618 auto I = find_if(Range: AsmOperands, P: [&](const AsmOperand &Op) {
619 return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;
620 });
621 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
622 }
623
624 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
625 /// This does not check the suboperand index.
626 int findAsmOperandNamed(StringRef N, int LastIdx = -1) const {
627 auto I =
628 llvm::find_if(Range: llvm::drop_begin(RangeOrContainer: AsmOperands, N: LastIdx + 1),
629 P: [&](const AsmOperand &Op) { return Op.SrcOpName == N; });
630 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
631 }
632
633 int findAsmOperandOriginallyNamed(StringRef N) const {
634 auto I = find_if(Range: AsmOperands, P: [&](const AsmOperand &Op) {
635 return Op.OrigSrcOpName == N;
636 });
637 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
638 }
639
640 void buildInstructionResultOperands();
641 void buildAliasResultOperands(bool AliasConstraintsAreChecked);
642
643 /// shouldBeMatchedBefore - Compare two matchables for ordering.
644 bool shouldBeMatchedBefore(const MatchableInfo &RHS,
645 bool PreferSmallerInstructions) const {
646 // The primary comparator is the instruction mnemonic.
647 if (int Cmp = Mnemonic.compare_insensitive(RHS: RHS.Mnemonic))
648 return Cmp == -1;
649
650 // (Optionally) Order by the resultant instuctions size.
651 // eg. for ARM thumb instructions smaller encodings should be preferred.
652 if (PreferSmallerInstructions && ResInstSize != RHS.ResInstSize)
653 return ResInstSize < RHS.ResInstSize;
654
655 if (AsmOperands.size() != RHS.AsmOperands.size())
656 return AsmOperands.size() < RHS.AsmOperands.size();
657
658 // Compare lexicographically by operand. The matcher validates that other
659 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
660 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
661 if (*LHSOp.Class < *RHSOp.Class)
662 return true;
663 if (*RHSOp.Class < *LHSOp.Class)
664 return false;
665 }
666
667 // For X86 AVX/AVX512 instructions, we prefer vex encoding because the
668 // vex encoding size is smaller. Since X86InstrSSE.td is included ahead
669 // of X86InstrAVX512.td, the AVX instruction ID is less than AVX512 ID.
670 // We use the ID to sort AVX instruction before AVX512 instruction in
671 // matching table. As well as InstAlias.
672 if (getResultInst()->TheDef->isSubClassOf(Name: "Instruction") &&
673 getResultInst()->TheDef->getValueAsBit(FieldName: "HasPositionOrder") &&
674 RHS.getResultInst()->TheDef->isSubClassOf(Name: "Instruction") &&
675 RHS.getResultInst()->TheDef->getValueAsBit(FieldName: "HasPositionOrder"))
676 return getResultInst()->TheDef->getID() <
677 RHS.getResultInst()->TheDef->getID();
678
679 // Give matches that require more features higher precedence. This is useful
680 // because we cannot define AssemblerPredicates with the negation of
681 // processor features. For example, ARM v6 "nop" may be either a HINT or
682 // MOV. With v6, we want to match HINT. The assembler has no way to
683 // predicate MOV under "NoV6", but HINT will always match first because it
684 // requires V6 while MOV does not.
685 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
686 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
687
688 return false;
689 }
690
691 /// couldMatchAmbiguouslyWith - Check whether this matchable could
692 /// ambiguously match the same set of operands as \p RHS (without being a
693 /// strictly superior match).
694 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS,
695 bool PreferSmallerInstructions) const {
696 // The primary comparator is the instruction mnemonic.
697 if (Mnemonic != RHS.Mnemonic)
698 return false;
699
700 // Different variants can't conflict.
701 if (AsmVariantID != RHS.AsmVariantID)
702 return false;
703
704 // The size of instruction is unambiguous.
705 if (PreferSmallerInstructions && ResInstSize != RHS.ResInstSize)
706 return false;
707
708 // The number of operands is unambiguous.
709 if (AsmOperands.size() != RHS.AsmOperands.size())
710 return false;
711
712 // Otherwise, make sure the ordering of the two instructions is unambiguous
713 // by checking that either (a) a token or operand kind discriminates them,
714 // or (b) the ordering among equivalent kinds is consistent.
715
716 // Tokens and operand kinds are unambiguous (assuming a correct target
717 // specific parser).
718 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
719 if (LHSOp.Class->Kind != RHSOp.Class->Kind ||
720 LHSOp.Class->Kind == ClassInfo::Token)
721 if (*LHSOp.Class < *RHSOp.Class || *RHSOp.Class < *LHSOp.Class)
722 return false;
723 }
724
725 // Otherwise, this operand could commute if all operands are equivalent, or
726 // there is a pair of operands that compare less than and a pair that
727 // compare greater than.
728 bool HasLT = false, HasGT = false;
729 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
730 if (*LHSOp.Class < *RHSOp.Class)
731 HasLT = true;
732 if (*RHSOp.Class < *LHSOp.Class)
733 HasGT = true;
734 }
735
736 return HasLT == HasGT;
737 }
738
739 void dump() const;
740
741private:
742 void tokenizeAsmString(AsmMatcherInfo const &Info,
743 AsmVariantInfo const &Variant);
744 void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);
745};
746
747struct OperandMatchEntry {
748 unsigned OperandMask;
749 const MatchableInfo *MI;
750 ClassInfo *CI;
751
752 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
753 unsigned opMask) {
754 OperandMatchEntry X;
755 X.OperandMask = opMask;
756 X.CI = ci;
757 X.MI = mi;
758 return X;
759 }
760};
761
762class AsmMatcherInfo {
763public:
764 /// Tracked Records
765 const RecordKeeper &Records;
766
767 /// The tablegen AsmParser record.
768 const Record *AsmParser;
769
770 /// Target - The target information.
771 const CodeGenTarget &Target;
772
773 /// The classes which are needed for matching.
774 std::forward_list<ClassInfo> Classes;
775
776 /// The information on the matchables to match.
777 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
778
779 /// Info for custom matching operands by user defined methods.
780 std::vector<OperandMatchEntry> OperandMatchInfo;
781
782 /// Map of Register records to their class information.
783 using RegisterClassesTy =
784 std::map<const Record *, ClassInfo *, LessRecordByID>;
785 RegisterClassesTy RegisterClasses;
786
787 /// Map of Predicate records to their subtarget information.
788 SubtargetFeatureInfoMap SubtargetFeatures;
789
790 /// Map of AsmOperandClass records to their class information.
791 std::map<const Record *, ClassInfo *> AsmOperandClasses;
792
793 /// Map of RegisterClass records to their class information.
794 std::map<const Record *, ClassInfo *> RegisterClassClasses;
795
796private:
797 /// Map of token to class information which has already been constructed.
798 std::map<std::string, ClassInfo *> TokenClasses;
799
800private:
801 /// getTokenClass - Lookup or create the class for the given token.
802 ClassInfo *getTokenClass(StringRef Token, bool WantDiagnostic = false);
803
804 /// getOperandClass - Lookup or create the class for the given operand.
805 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
806 int SubOpIdx);
807 ClassInfo *getOperandClass(const Record *Rec, int SubOpIdx);
808
809 /// buildRegisterClasses - Build the ClassInfo* instances for register
810 /// classes.
811 void
812 buildRegisterClasses(SmallPtrSetImpl<const Record *> &SingletonRegisters);
813
814 /// buildOperandClasses - Build the ClassInfo* instances for user defined
815 /// operand classes.
816 void buildOperandClasses();
817
818 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
819 unsigned AsmOpIdx);
820 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
821 MatchableInfo::AsmOperand &Op);
822
823public:
824 AsmMatcherInfo(const Record *AsmParser, const CodeGenTarget &Target,
825 const RecordKeeper &Records);
826
827 /// Construct the various tables used during matching.
828 void buildInfo();
829
830 /// buildOperandMatchInfo - Build the necessary information to handle user
831 /// defined operand parsing methods.
832 void buildOperandMatchInfo();
833
834 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
835 /// given operand.
836 const SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const {
837 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
838 const auto &I = SubtargetFeatures.find(x: Def);
839 return I == SubtargetFeatures.end() ? nullptr : &I->second;
840 }
841
842 const RecordKeeper &getRecords() const { return Records; }
843
844 bool hasOptionalOperands() const {
845 return any_of(Range: Classes,
846 P: [](const ClassInfo &Class) { return Class.IsOptional; });
847 }
848};
849
850} // end anonymous namespace
851
852#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
853LLVM_DUMP_METHOD void MatchableInfo::dump() const {
854 errs() << TheDef->getName() << " -- "
855 << "flattened:\"" << AsmString << "\"\n";
856
857 errs() << " variant: " << AsmVariantID << "\n";
858
859 for (const auto &[Idx, Op] : enumerate(AsmOperands)) {
860 errs() << " op[" << Idx << "] = " << Op.Class->ClassName << " - ";
861 errs() << '\"' << Op.Token << "\"\n";
862 }
863}
864#endif
865
866static std::pair<StringRef, StringRef>
867parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
868 // Trim whitespace and the leading '$' on the operand names.
869 auto TrimWSDollar = [Loc](StringRef OpName) {
870 OpName = OpName.trim(Chars: " \t");
871 if (!OpName.consume_front(Prefix: "$"))
872 PrintFatalError(ErrorLoc: Loc, Msg: "expected '$' prefix on asm operand name");
873 return OpName;
874 };
875
876 // Split via the '='.
877 auto [Src, Dst] = S.split(Separator: '=');
878 if (Dst == "")
879 PrintFatalError(ErrorLoc: Loc, Msg: "missing '=' in two-operand alias constraint");
880 return {TrimWSDollar(Src), TrimWSDollar(Dst)};
881}
882
883void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
884 // Figure out which operands are aliased and mark them as tied.
885 auto [Src, Dst] = parseTwoOperandConstraint(S: Constraint, Loc: TheDef->getLoc());
886
887 // Find the AsmOperands that refer to the operands we're aliasing.
888 int SrcAsmOperand = findAsmOperandNamed(N: Src);
889 int DstAsmOperand = findAsmOperandNamed(N: Dst);
890 if (SrcAsmOperand == -1)
891 PrintFatalError(ErrorLoc: TheDef->getLoc(),
892 Msg: "unknown source two-operand alias operand '" + Src + "'.");
893 if (DstAsmOperand == -1)
894 PrintFatalError(ErrorLoc: TheDef->getLoc(),
895 Msg: "unknown destination two-operand alias operand '" + Dst +
896 "'.");
897
898 // Find the ResOperand that refers to the operand we're aliasing away
899 // and update it to refer to the combined operand instead.
900 for (ResOperand &Op : ResOperands) {
901 if (Op.Kind == ResOperand::RenderAsmOperand &&
902 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
903 Op.AsmOperandNum = DstAsmOperand;
904 break;
905 }
906 }
907 // Remove the AsmOperand for the alias operand.
908 AsmOperands.erase(CI: AsmOperands.begin() + SrcAsmOperand);
909 // Adjust the ResOperand references to any AsmOperands that followed
910 // the one we just deleted.
911 for (ResOperand &Op : ResOperands) {
912 if (Op.Kind == ResOperand::RenderAsmOperand &&
913 Op.AsmOperandNum > (unsigned)SrcAsmOperand)
914 --Op.AsmOperandNum;
915 }
916}
917
918/// extractSingletonRegisterForAsmOperand - Extract singleton register,
919/// if present, from specified token.
920static void extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
921 const AsmMatcherInfo &Info,
922 StringRef RegisterPrefix) {
923 StringRef Tok = Op.Token;
924
925 // If this token is not an isolated token, i.e., it isn't separated from
926 // other tokens (e.g. with whitespace), don't interpret it as a register name.
927 if (!Op.IsIsolatedToken)
928 return;
929
930 if (RegisterPrefix.empty()) {
931 std::string LoweredTok = Tok.lower();
932 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(Name: LoweredTok))
933 Op.SingletonReg = Reg->TheDef;
934 return;
935 }
936
937 if (!Tok.consume_front(Prefix: RegisterPrefix))
938 return;
939
940 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(Name: Tok))
941 Op.SingletonReg = Reg->TheDef;
942
943 // If there is no register prefix (i.e. "%" in "%eax"), then this may
944 // be some random non-register token, just ignore it.
945}
946
947void MatchableInfo::initialize(
948 const AsmMatcherInfo &Info,
949 SmallPtrSetImpl<const Record *> &SingletonRegisters,
950 AsmVariantInfo const &Variant, bool HasMnemonicFirst) {
951 AsmVariantID = Variant.AsmVariantNo;
952 AsmString = CodeGenInstruction::FlattenAsmStringVariants(
953 AsmString, Variant: Variant.AsmVariantNo);
954
955 tokenizeAsmString(Info, Variant);
956
957 // The first token of the instruction is the mnemonic, which must be a
958 // simple string, not a $foo variable or a singleton register.
959 if (AsmOperands.empty())
960 PrintFatalError(ErrorLoc: TheDef->getLoc(),
961 Msg: "Instruction '" + TheDef->getName() + "' has no tokens");
962
963 assert(!AsmOperands[0].Token.empty());
964 if (HasMnemonicFirst) {
965 Mnemonic = AsmOperands[0].Token;
966 if (Mnemonic[0] == '$')
967 PrintFatalError(ErrorLoc: TheDef->getLoc(),
968 Msg: "Invalid instruction mnemonic '" + Mnemonic + "'!");
969
970 // Remove the first operand, it is tracked in the mnemonic field.
971 AsmOperands.erase(CI: AsmOperands.begin());
972 } else if (AsmOperands[0].Token[0] != '$')
973 Mnemonic = AsmOperands[0].Token;
974
975 // Compute the require features.
976 for (const Record *Predicate : TheDef->getValueAsListOfDefs(FieldName: "Predicates"))
977 if (const SubtargetFeatureInfo *Feature =
978 Info.getSubtargetFeature(Def: Predicate))
979 RequiredFeatures.push_back(Elt: Feature);
980
981 // Collect singleton registers, if used.
982 for (MatchableInfo::AsmOperand &Op : AsmOperands) {
983 extractSingletonRegisterForAsmOperand(Op, Info, RegisterPrefix: Variant.RegisterPrefix);
984 if (Op.SingletonReg)
985 SingletonRegisters.insert(Ptr: Op.SingletonReg);
986 }
987
988 const RecordVal *DepMask = TheDef->getValue(Name: "DeprecatedFeatureMask");
989 if (!DepMask)
990 DepMask = TheDef->getValue(Name: "ComplexDeprecationPredicate");
991
992 HasDeprecation =
993 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
994}
995
996/// Append an AsmOperand for the given substring of AsmString.
997void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {
998 AsmOperands.push_back(Elt: AsmOperand(IsIsolatedToken, Token));
999}
1000
1001/// tokenizeAsmString - Tokenize a simplified assembly string.
1002void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
1003 AsmVariantInfo const &Variant) {
1004 StringRef String = AsmString;
1005 size_t Prev = 0;
1006 bool InTok = false;
1007 bool IsIsolatedToken = true;
1008 for (size_t i = 0, e = String.size(); i != e; ++i) {
1009 char Char = String[i];
1010 if (Variant.BreakCharacters.contains(C: Char)) {
1011 if (InTok) {
1012 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken: false);
1013 Prev = i;
1014 IsIsolatedToken = false;
1015 }
1016 InTok = true;
1017 continue;
1018 }
1019 if (Variant.TokenizingCharacters.contains(C: Char)) {
1020 if (InTok) {
1021 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1022 InTok = false;
1023 IsIsolatedToken = false;
1024 }
1025 addAsmOperand(Token: String.substr(Start: i, N: 1), IsIsolatedToken);
1026 Prev = i + 1;
1027 IsIsolatedToken = true;
1028 continue;
1029 }
1030 if (Variant.SeparatorCharacters.contains(C: Char)) {
1031 if (InTok) {
1032 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1033 InTok = false;
1034 }
1035 Prev = i + 1;
1036 IsIsolatedToken = true;
1037 continue;
1038 }
1039
1040 switch (Char) {
1041 case '\\':
1042 if (InTok) {
1043 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken: false);
1044 InTok = false;
1045 IsIsolatedToken = false;
1046 }
1047 ++i;
1048 assert(i != String.size() && "Invalid quoted character");
1049 addAsmOperand(Token: String.substr(Start: i, N: 1), IsIsolatedToken);
1050 Prev = i + 1;
1051 IsIsolatedToken = false;
1052 break;
1053
1054 case '$': {
1055 if (InTok) {
1056 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1057 InTok = false;
1058 IsIsolatedToken = false;
1059 }
1060
1061 // If this isn't "${", start new identifier looking like "$xxx"
1062 if (i + 1 == String.size() || String[i + 1] != '{') {
1063 Prev = i;
1064 break;
1065 }
1066
1067 size_t EndPos = String.find(C: '}', From: i);
1068 assert(EndPos != StringRef::npos &&
1069 "Missing brace in operand reference!");
1070 addAsmOperand(Token: String.substr(Start: i, N: EndPos + 1 - i), IsIsolatedToken);
1071 Prev = EndPos + 1;
1072 i = EndPos;
1073 IsIsolatedToken = false;
1074 break;
1075 }
1076
1077 default:
1078 InTok = true;
1079 break;
1080 }
1081 }
1082 if (InTok && Prev != String.size())
1083 addAsmOperand(Token: String.substr(Start: Prev), IsIsolatedToken);
1084}
1085
1086bool MatchableInfo::validate(StringRef CommentDelimiter, bool IsAlias) const {
1087 // Reject matchables with no .s string.
1088 if (AsmString.empty())
1089 PrintFatalError(ErrorLoc: TheDef->getLoc(), Msg: "instruction with empty asm string");
1090
1091 // Reject any matchables with a newline in them, they should be marked
1092 // isCodeGenOnly if they are pseudo instructions.
1093 if (AsmString.find(c: '\n') != std::string::npos)
1094 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1095 Msg: "multiline instruction is not valid for the asmparser, "
1096 "mark it isCodeGenOnly");
1097
1098 // Remove comments from the asm string. We know that the asmstring only
1099 // has one line.
1100 if (!CommentDelimiter.empty() &&
1101 StringRef(AsmString).contains(Other: CommentDelimiter))
1102 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1103 Msg: "asmstring for instruction has comment character in it, "
1104 "mark it isCodeGenOnly");
1105
1106 // Reject matchables with operand modifiers, these aren't something we can
1107 // handle, the target should be refactored to use operands instead of
1108 // modifiers.
1109 //
1110 // Also, check for instructions which reference the operand multiple times,
1111 // if they don't define a custom AsmMatcher: this implies a constraint that
1112 // the built-in matching code would not honor.
1113 std::set<std::string> OperandNames;
1114 for (const AsmOperand &Op : AsmOperands) {
1115 StringRef Tok = Op.Token;
1116 if (Tok[0] == '$' && Tok.contains(C: ':'))
1117 PrintFatalError(
1118 ErrorLoc: TheDef->getLoc(),
1119 Msg: "matchable with operand modifier '" + Tok +
1120 "' not supported by asm matcher. Mark isCodeGenOnly!");
1121 // Verify that any operand is only mentioned once.
1122 // We reject aliases and ignore instructions for now.
1123 if (!IsAlias && TheDef->getValueAsString(FieldName: "AsmMatchConverter").empty() &&
1124 Tok[0] == '$' && !OperandNames.insert(x: Tok.str()).second) {
1125 LLVM_DEBUG({
1126 errs() << "warning: '" << TheDef->getName() << "': "
1127 << "ignoring instruction with tied operand '" << Tok << "'\n";
1128 });
1129 return false;
1130 }
1131 }
1132
1133 return true;
1134}
1135
1136static std::string getEnumNameForToken(StringRef Str) {
1137 std::string Res;
1138
1139 for (char C : Str) {
1140 switch (C) {
1141 case '*':
1142 Res += "_STAR_";
1143 break;
1144 case '%':
1145 Res += "_PCT_";
1146 break;
1147 case ':':
1148 Res += "_COLON_";
1149 break;
1150 case '!':
1151 Res += "_EXCLAIM_";
1152 break;
1153 case '.':
1154 Res += "_DOT_";
1155 break;
1156 case '<':
1157 Res += "_LT_";
1158 break;
1159 case '>':
1160 Res += "_GT_";
1161 break;
1162 case '-':
1163 Res += "_MINUS_";
1164 break;
1165 case '#':
1166 Res += "_HASH_";
1167 break;
1168 default:
1169 if (isAlnum(C))
1170 Res += C;
1171 else
1172 Res += "_" + utostr(X: (unsigned)C) + "_";
1173 }
1174 }
1175
1176 return Res;
1177}
1178
1179ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token, bool WantDiagnostic) {
1180 ClassInfo *&Entry = TokenClasses[Token.str()];
1181
1182 if (!Entry) {
1183 Classes.emplace_front();
1184 Entry = &Classes.front();
1185 Entry->Kind = ClassInfo::Token;
1186 Entry->ClassName = "Token";
1187 Entry->Name = "MCK_" + getEnumNameForToken(Str: Token);
1188 Entry->ValueName = Token.str();
1189 Entry->PredicateMethod = "<invalid>";
1190 Entry->RenderMethod = "<invalid>";
1191 Entry->ParserMethod = "";
1192 Entry->DiagnosticType = "";
1193 Entry->IsOptional = false;
1194 Entry->DefaultMethod = "<invalid>";
1195 }
1196
1197 // Outside the creation block so a later WantDiagnostic=true call can
1198 // update an entry first created with WantDiagnostic=false.
1199 if (WantDiagnostic && Entry->DiagnosticType.empty() &&
1200 AsmParser->getValueAsBit(FieldName: "EmitTokenDiagnosticTypes")) {
1201 Entry->DiagnosticType = "InvalidToken" + getEnumNameForToken(Str: Token);
1202 Entry->DiagnosticString = "expected '" + Token.str() + "'";
1203 }
1204
1205 return Entry;
1206}
1207
1208ClassInfo *
1209AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1210 int SubOpIdx) {
1211 const Record *Rec = OI.Rec;
1212 if (SubOpIdx != -1)
1213 Rec = cast<DefInit>(Val: OI.MIOperandInfo->getArg(Num: SubOpIdx))->getDef();
1214 return getOperandClass(Rec, SubOpIdx);
1215}
1216
1217ClassInfo *AsmMatcherInfo::getOperandClass(const Record *Rec, int SubOpIdx) {
1218 if (Rec->isSubClassOf(Name: "RegisterOperand")) {
1219 // RegisterOperand may have an associated ParserMatchClass. If it does,
1220 // use it, else just fall back to the underlying register class.
1221 const RecordVal *R = Rec->getValue(Name: "ParserMatchClass");
1222 if (!R || !R->getValue())
1223 PrintFatalError(ErrorLoc: Rec->getLoc(),
1224 Msg: "Record `" + Rec->getName() +
1225 "' does not have a ParserMatchClass!\n");
1226
1227 if (const DefInit *DI = dyn_cast<DefInit>(Val: R->getValue())) {
1228 const Record *MatchClass = DI->getDef();
1229 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1230 return CI;
1231 }
1232
1233 // No custom match class. Just use the register class.
1234 const Record *ClassRec = Rec->getValueAsDef(FieldName: "RegClass");
1235 if (!ClassRec)
1236 PrintFatalError(ErrorLoc: Rec->getLoc(),
1237 Msg: "RegisterOperand `" + Rec->getName() +
1238 "' has no associated register class!\n");
1239
1240 if (ClassRec->isSubClassOf(Name: "RegisterClassLike")) {
1241 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1242 return CI;
1243
1244 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1245 }
1246 }
1247
1248 if (Rec->isSubClassOf(Name: "RegisterClass")) {
1249 if (ClassInfo *CI = RegisterClassClasses[Rec])
1250 return CI;
1251 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1252 }
1253
1254 if (Rec->isSubClassOf(Name: "Operand")) {
1255 const Record *MatchClass = Rec->getValueAsDef(FieldName: "ParserMatchClass");
1256 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1257 return CI;
1258 } else if (Rec->isSubClassOf(Name: "RegisterClassLike")) {
1259 if (ClassInfo *CI = RegisterClassClasses[Rec])
1260 return CI;
1261 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1262 } else {
1263 PrintFatalError(ErrorLoc: Rec->getLoc(),
1264 Msg: "Operand `" + Rec->getName() +
1265 "' does not derive from class Operand!\n");
1266 }
1267
1268 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "operand has no match class!");
1269}
1270
1271struct LessRegisterSet {
1272 bool operator()(const RegisterSet &LHS, const RegisterSet &RHS) const {
1273 // std::set<T> defines its own compariso "operator<", but it
1274 // performs a lexicographical comparison by T's innate comparison
1275 // for some reason. We don't want non-deterministic pointer
1276 // comparisons so use this instead.
1277 return std::lexicographical_compare(first1: LHS.begin(), last1: LHS.end(), first2: RHS.begin(),
1278 last2: RHS.end(), comp: LessRecordByID());
1279 }
1280};
1281
1282void AsmMatcherInfo::buildRegisterClasses(
1283 SmallPtrSetImpl<const Record *> &SingletonRegisters) {
1284 const auto &Registers = Target.getRegBank().getRegisters();
1285 auto &RegClassList = Target.getRegBank().getRegClasses();
1286
1287 using RegisterSetSet = std::set<RegisterSet, LessRegisterSet>;
1288
1289 // The register sets used for matching.
1290 RegisterSetSet RegisterSets;
1291
1292 // Gather the defined sets.
1293 for (const CodeGenRegisterClass &RC : RegClassList)
1294 RegisterSets.insert(
1295 x: RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1296
1297 // Add any required singleton sets.
1298 for (const Record *Rec : SingletonRegisters) {
1299 RegisterSets.insert(x: RegisterSet(&Rec, &Rec + 1));
1300 }
1301
1302 // Introduce derived sets where necessary (when a register does not determine
1303 // a unique register set class), and build the mapping of registers to the set
1304 // they should classify to.
1305 std::map<const Record *, RegisterSet> RegisterMap;
1306 for (const CodeGenRegister &CGR : Registers) {
1307 // Compute the intersection of all sets containing this register.
1308 RegisterSet ContainingSet;
1309
1310 for (const RegisterSet &RS : RegisterSets) {
1311 if (!RS.count(x: CGR.TheDef))
1312 continue;
1313
1314 if (ContainingSet.empty()) {
1315 ContainingSet = RS;
1316 continue;
1317 }
1318
1319 RegisterSet Tmp;
1320 std::set_intersection(first1: ContainingSet.begin(), last1: ContainingSet.end(),
1321 first2: RS.begin(), last2: RS.end(),
1322 result: std::inserter(x&: Tmp, i: Tmp.begin()), comp: LessRecordByID());
1323 ContainingSet = std::move(Tmp);
1324 }
1325
1326 if (!ContainingSet.empty()) {
1327 RegisterSets.insert(x: ContainingSet);
1328 RegisterMap.try_emplace(k: CGR.TheDef, args&: ContainingSet);
1329 }
1330 }
1331
1332 // Construct the register classes.
1333 std::map<RegisterSet, ClassInfo *, LessRegisterSet> RegisterSetClasses;
1334 unsigned Index = 0;
1335 for (const RegisterSet &RS : RegisterSets) {
1336 Classes.emplace_front();
1337 ClassInfo *CI = &Classes.front();
1338 CI->Kind = ClassInfo::RegisterClass0 + Index;
1339 CI->ClassName = "Reg" + utostr(X: Index);
1340 CI->Name = "MCK_Reg" + utostr(X: Index);
1341 CI->ValueName = "";
1342 CI->PredicateMethod = ""; // unused
1343 CI->RenderMethod = "addRegOperands";
1344 CI->Registers = RS;
1345 // FIXME: diagnostic type.
1346 CI->DiagnosticType = "";
1347 CI->IsOptional = false;
1348 CI->DefaultMethod = ""; // unused
1349 RegisterSetClasses.try_emplace(k: RS, args&: CI);
1350 ++Index;
1351 assert(CI->isRegisterClass());
1352 }
1353
1354 // Find the superclasses; we could compute only the subgroup lattice edges,
1355 // but there isn't really a point.
1356 for (const RegisterSet &RS : RegisterSets) {
1357 ClassInfo *CI = RegisterSetClasses[RS];
1358 for (const RegisterSet &RS2 : RegisterSets)
1359 if (RS != RS2 && llvm::includes(Range1: RS2, Range2: RS, C: LessRecordByID()))
1360 CI->SuperClasses.push_back(x: RegisterSetClasses[RS2]);
1361 }
1362
1363 // Name the register classes which correspond to a user defined RegisterClass.
1364 for (const CodeGenRegisterClass &RC : RegClassList) {
1365 // Def will be NULL for non-user defined register classes.
1366 const Record *Def = RC.getDef();
1367 if (!Def)
1368 continue;
1369 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1370 RC.getOrder().end())];
1371 if (CI->ValueName.empty()) {
1372 CI->ClassName = RC.getName();
1373 CI->Name = "MCK_" + RC.getName();
1374 CI->ValueName = RC.getName();
1375 } else {
1376 CI->ValueName = CI->ValueName + "," + RC.getName();
1377 }
1378
1379 const Init *DiagnosticType = Def->getValueInit(FieldName: "DiagnosticType");
1380 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticType))
1381 CI->DiagnosticType = SI->getValue().str();
1382
1383 const Init *DiagnosticString = Def->getValueInit(FieldName: "DiagnosticString");
1384 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticString))
1385 CI->DiagnosticString = SI->getValue().str();
1386
1387 // If we have a diagnostic string but the diagnostic type is not specified
1388 // explicitly, create an anonymous diagnostic type.
1389 if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1390 CI->DiagnosticType = RC.getName();
1391
1392 RegisterClassClasses.try_emplace(k: Def, args&: CI);
1393 assert(CI->isRegisterClass());
1394 }
1395
1396 unsigned RegClassByHwModeIndex = 0;
1397 for (const Record *ClassByHwMode : Target.getAllRegClassByHwMode()) {
1398 ClassInfo &CI = Classes.emplace_front();
1399 CI.Kind = ClassInfo::RegisterClassByHwMode0 + RegClassByHwModeIndex;
1400
1401 CI.ClassName = "RegByHwMode_" + ClassByHwMode->getName().str();
1402 CI.Name = "MCK_" + CI.ClassName;
1403 CI.ValueName = ClassByHwMode->getName();
1404 CI.RenderMethod = "addRegOperands";
1405 // FIXME: Set diagnostic type.
1406 ++RegClassByHwModeIndex;
1407
1408 assert(CI.isRegisterClassByHwMode());
1409
1410 RegisterClassClasses.try_emplace(k: ClassByHwMode, args: &CI);
1411 }
1412
1413 // Populate the map for individual registers.
1414 for (auto &It : RegisterMap)
1415 RegisterClasses[It.first] = RegisterSetClasses[It.second];
1416
1417 // Name the register classes which correspond to singleton registers.
1418 for (const Record *Rec : SingletonRegisters) {
1419 ClassInfo *CI = RegisterClasses[Rec];
1420 assert(CI && "Missing singleton register class info!");
1421
1422 if (CI->ValueName.empty()) {
1423 CI->ClassName = Rec->getName().str();
1424 CI->Name = "MCK_" + Rec->getName().str();
1425 CI->ValueName = Rec->getName().str();
1426 } else {
1427 CI->ValueName = CI->ValueName + "," + Rec->getName().str();
1428 }
1429 }
1430}
1431
1432void AsmMatcherInfo::buildOperandClasses() {
1433 ArrayRef<const Record *> AsmOperands =
1434 Records.getAllDerivedDefinitions(ClassName: "AsmOperandClass");
1435
1436 // Pre-populate AsmOperandClasses map.
1437 for (const Record *Rec : AsmOperands) {
1438 Classes.emplace_front();
1439 AsmOperandClasses[Rec] = &Classes.front();
1440 }
1441
1442 unsigned Index = 0;
1443 for (const Record *Rec : AsmOperands) {
1444 ClassInfo *CI = AsmOperandClasses[Rec];
1445 CI->Kind = ClassInfo::UserClass0 + Index;
1446
1447 const ListInit *Supers = Rec->getValueAsListInit(FieldName: "SuperClasses");
1448 for (const Init *I : Supers->getElements()) {
1449 const DefInit *DI = dyn_cast<DefInit>(Val: I);
1450 if (!DI) {
1451 PrintError(ErrorLoc: Rec->getLoc(), Msg: "Invalid super class reference!");
1452 continue;
1453 }
1454
1455 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1456 if (!SC)
1457 PrintError(ErrorLoc: Rec->getLoc(), Msg: "Invalid super class reference!");
1458 else
1459 CI->SuperClasses.push_back(x: SC);
1460 }
1461 CI->ClassName = Rec->getValueAsString(FieldName: "Name").str();
1462 CI->Name = "MCK_" + CI->ClassName;
1463 CI->ValueName = Rec->getName().str();
1464
1465 // Get or construct the predicate method name.
1466 const Init *PMName = Rec->getValueInit(FieldName: "PredicateMethod");
1467 if (const StringInit *SI = dyn_cast<StringInit>(Val: PMName)) {
1468 CI->PredicateMethod = SI->getValue().str();
1469 } else {
1470 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1471 CI->PredicateMethod = "is" + CI->ClassName;
1472 }
1473
1474 // Get or construct the render method name.
1475 const Init *RMName = Rec->getValueInit(FieldName: "RenderMethod");
1476 if (const StringInit *SI = dyn_cast<StringInit>(Val: RMName)) {
1477 CI->RenderMethod = SI->getValue().str();
1478 } else {
1479 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1480 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1481 }
1482
1483 // Get the parse method name or leave it as empty.
1484 const Init *PRMName = Rec->getValueInit(FieldName: "ParserMethod");
1485 if (const StringInit *SI = dyn_cast<StringInit>(Val: PRMName))
1486 CI->ParserMethod = SI->getValue().str();
1487
1488 // Get the diagnostic type and string or leave them as empty.
1489 const Init *DiagnosticType = Rec->getValueInit(FieldName: "DiagnosticType");
1490 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticType))
1491 CI->DiagnosticType = SI->getValue().str();
1492 const Init *DiagnosticString = Rec->getValueInit(FieldName: "DiagnosticString");
1493 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticString))
1494 CI->DiagnosticString = SI->getValue().str();
1495 // If we have a DiagnosticString, we need a DiagnosticType for use within
1496 // the matcher.
1497 if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1498 CI->DiagnosticType = CI->ClassName;
1499
1500 const Init *IsOptional = Rec->getValueInit(FieldName: "IsOptional");
1501 if (const BitInit *BI = dyn_cast<BitInit>(Val: IsOptional))
1502 CI->IsOptional = BI->getValue();
1503
1504 // Get or construct the default method name.
1505 const Init *DMName = Rec->getValueInit(FieldName: "DefaultMethod");
1506 if (const StringInit *SI = dyn_cast<StringInit>(Val: DMName)) {
1507 CI->DefaultMethod = SI->getValue().str();
1508 } else {
1509 assert(isa<UnsetInit>(DMName) && "Unexpected DefaultMethod field!");
1510 CI->DefaultMethod = "default" + CI->ClassName + "Operands";
1511 }
1512
1513 ++Index;
1514 }
1515}
1516
1517AsmMatcherInfo::AsmMatcherInfo(const Record *asmParser,
1518 const CodeGenTarget &target,
1519 const RecordKeeper &records)
1520 : Records(records), AsmParser(asmParser), Target(target) {}
1521
1522/// buildOperandMatchInfo - Build the necessary information to handle user
1523/// defined operand parsing methods.
1524void AsmMatcherInfo::buildOperandMatchInfo() {
1525 /// Map containing a mask with all operands indices that can be found for
1526 /// that class inside a instruction.
1527 using OpClassMaskTy = std::map<ClassInfo *, unsigned, deref<std::less<>>>;
1528 OpClassMaskTy OpClassMask;
1529
1530 bool CallCustomParserForAllOperands =
1531 AsmParser->getValueAsBit(FieldName: "CallCustomParserForAllOperands");
1532 for (const auto &MI : Matchables) {
1533 OpClassMask.clear();
1534
1535 // Keep track of all operands of this instructions which belong to the
1536 // same class.
1537 unsigned NumOptionalOps = 0;
1538 for (const auto &[Idx, Op] : enumerate(First&: MI->AsmOperands)) {
1539 if (CallCustomParserForAllOperands || !Op.Class->ParserMethod.empty()) {
1540 unsigned &OperandMask = OpClassMask[Op.Class];
1541 OperandMask |= maskTrailingOnes<unsigned>(N: NumOptionalOps + 1)
1542 << (Idx - NumOptionalOps);
1543 }
1544 if (Op.Class->IsOptional)
1545 ++NumOptionalOps;
1546 }
1547
1548 // Generate operand match info for each mnemonic/operand class pair.
1549 for (const auto [CI, OpMask] : OpClassMask) {
1550 OperandMatchInfo.push_back(
1551 x: OperandMatchEntry::create(mi: MI.get(), ci: CI, opMask: OpMask));
1552 }
1553 }
1554}
1555
1556void AsmMatcherInfo::buildInfo() {
1557 // Build information about all of the AssemblerPredicates.
1558 SubtargetFeaturesInfoVec SubtargetFeaturePairs =
1559 SubtargetFeatureInfo::getAll(Records);
1560 SubtargetFeatures.insert(first: SubtargetFeaturePairs.begin(),
1561 last: SubtargetFeaturePairs.end());
1562#ifndef NDEBUG
1563 for (const auto &Pair : SubtargetFeatures)
1564 LLVM_DEBUG(Pair.second.dump());
1565#endif // NDEBUG
1566
1567 bool HasMnemonicFirst = AsmParser->getValueAsBit(FieldName: "HasMnemonicFirst");
1568 bool ReportMultipleNearMisses =
1569 AsmParser->getValueAsBit(FieldName: "ReportMultipleNearMisses");
1570
1571 // Parse the instructions; we need to do this first so that we can gather the
1572 // singleton register classes.
1573 SmallPtrSet<const Record *, 16> SingletonRegisters;
1574 unsigned VariantCount = Target.getAsmParserVariantCount();
1575 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1576 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
1577 StringRef CommentDelimiter =
1578 AsmVariant->getValueAsString(FieldName: "CommentDelimiter");
1579 AsmVariantInfo Variant;
1580 Variant.RegisterPrefix = AsmVariant->getValueAsString(FieldName: "RegisterPrefix");
1581 Variant.TokenizingCharacters =
1582 AsmVariant->getValueAsString(FieldName: "TokenizingCharacters");
1583 Variant.SeparatorCharacters =
1584 AsmVariant->getValueAsString(FieldName: "SeparatorCharacters");
1585 Variant.BreakCharacters = AsmVariant->getValueAsString(FieldName: "BreakCharacters");
1586 Variant.Name = AsmVariant->getValueAsString(FieldName: "Name");
1587 Variant.AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
1588
1589 for (const CodeGenInstruction *CGI : Target.getInstructions()) {
1590 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1591 // filter the set of instructions we consider.
1592 if (!CGI->getName().starts_with(Prefix: MatchPrefix))
1593 continue;
1594
1595 // Ignore "codegen only" instructions.
1596 if (CGI->isCodeGenOnly)
1597 continue;
1598
1599 // Ignore instructions for different instructions
1600 StringRef V = CGI->TheDef->getValueAsString(FieldName: "AsmVariantName");
1601 if (!V.empty() && V != Variant.Name)
1602 continue;
1603
1604 auto II = std::make_unique<MatchableInfo>(args: *CGI);
1605
1606 II->initialize(Info: *this, SingletonRegisters, Variant, HasMnemonicFirst);
1607
1608 // Ignore instructions which shouldn't be matched and diagnose invalid
1609 // instruction definitions with an error.
1610 if (!II->validate(CommentDelimiter, IsAlias: false))
1611 continue;
1612
1613 Matchables.push_back(x: std::move(II));
1614 }
1615
1616 // Parse all of the InstAlias definitions and stick them in the list of
1617 // matchables.
1618 for (const Record *InstAlias :
1619 Records.getAllDerivedDefinitions(ClassName: "InstAlias")) {
1620 auto Alias = std::make_unique<CodeGenInstAlias>(args&: InstAlias, args: Target);
1621
1622 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1623 // filter the set of instruction aliases we consider, based on the target
1624 // instruction.
1625 if (!Alias->ResultInst->getName().starts_with(Prefix: MatchPrefix))
1626 continue;
1627
1628 StringRef V = Alias->TheDef->getValueAsString(FieldName: "AsmVariantName");
1629 if (!V.empty() && V != Variant.Name)
1630 continue;
1631
1632 auto II = std::make_unique<MatchableInfo>(args: std::move(Alias));
1633
1634 II->initialize(Info: *this, SingletonRegisters, Variant, HasMnemonicFirst);
1635
1636 // Validate the alias definitions.
1637 II->validate(CommentDelimiter, IsAlias: true);
1638
1639 Matchables.push_back(x: std::move(II));
1640 }
1641 }
1642
1643 // Build info for the register classes.
1644 buildRegisterClasses(SingletonRegisters);
1645
1646 // Build info for the user defined assembly operand classes.
1647 buildOperandClasses();
1648
1649 // Build the information about matchables, now that we have fully formed
1650 // classes.
1651 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1652 for (auto &II : Matchables) {
1653 // Parse the tokens after the mnemonic.
1654 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1655 // don't precompute the loop bound, i.e., cannot use range based for loop
1656 // here.
1657 for (size_t Idx = 0; Idx < II->AsmOperands.size(); ++Idx) {
1658 MatchableInfo::AsmOperand &Op = II->AsmOperands[Idx];
1659 StringRef Token = Op.Token;
1660 // Check for singleton registers.
1661 if (const Record *RegRecord = Op.SingletonReg) {
1662 Op.Class = RegisterClasses[RegRecord];
1663 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1664 "Unexpected class for singleton register");
1665 continue;
1666 }
1667
1668 // Check for simple tokens.
1669 if (Token[0] != '$') {
1670 Op.Class = getTokenClass(Token, /*WantDiagnostic=*/true);
1671 continue;
1672 }
1673
1674 if (Token.size() > 1 && isdigit(Token[1])) {
1675 Op.Class = getTokenClass(Token);
1676 continue;
1677 }
1678
1679 // Otherwise this is an operand reference.
1680 StringRef OperandName;
1681 if (Token[1] == '{')
1682 OperandName = Token.substr(Start: 2, N: Token.size() - 3);
1683 else
1684 OperandName = Token.substr(Start: 1);
1685
1686 if (isa<const CodeGenInstruction *>(Val: II->DefRec))
1687 buildInstructionOperandReference(II: II.get(), OpName: OperandName, AsmOpIdx: Idx);
1688 else
1689 buildAliasOperandReference(II: II.get(), OpName: OperandName, Op);
1690 }
1691
1692 if (isa<const CodeGenInstruction *>(Val: II->DefRec)) {
1693 II->buildInstructionResultOperands();
1694 // If the instruction has a two-operand alias, build up the
1695 // matchable here. We'll add them in bulk at the end to avoid
1696 // confusing this loop.
1697 StringRef Constraint =
1698 II->TheDef->getValueAsString(FieldName: "TwoOperandAliasConstraint");
1699 if (Constraint != "") {
1700 // Start by making a copy of the original matchable.
1701 auto AliasII = std::make_unique<MatchableInfo>(args&: *II);
1702
1703 // Adjust it to be a two-operand alias.
1704 AliasII->formTwoOperandAlias(Constraint);
1705
1706 // Add the alias to the matchables list.
1707 NewMatchables.push_back(x: std::move(AliasII));
1708 }
1709 } else {
1710 // FIXME: The tied operands checking is not yet integrated with the
1711 // framework for reporting multiple near misses. To prevent invalid
1712 // formats from being matched with an alias if a tied-operands check
1713 // would otherwise have disallowed it, we just disallow such constructs
1714 // in TableGen completely.
1715 II->buildAliasResultOperands(AliasConstraintsAreChecked: !ReportMultipleNearMisses);
1716 }
1717 }
1718 if (!NewMatchables.empty())
1719 Matchables.insert(position: Matchables.end(),
1720 first: std::make_move_iterator(i: NewMatchables.begin()),
1721 last: std::make_move_iterator(i: NewMatchables.end()));
1722
1723 // Process token alias definitions and set up the associated superclass
1724 // information.
1725 for (const Record *Rec : Records.getAllDerivedDefinitions(ClassName: "TokenAlias")) {
1726 ClassInfo *FromClass = getTokenClass(Token: Rec->getValueAsString(FieldName: "FromToken"));
1727 ClassInfo *ToClass = getTokenClass(Token: Rec->getValueAsString(FieldName: "ToToken"));
1728 if (FromClass == ToClass)
1729 PrintFatalError(ErrorLoc: Rec->getLoc(),
1730 Msg: "error: Destination value identical to source value.");
1731 FromClass->SuperClasses.push_back(x: ToClass);
1732 }
1733
1734 // Reorder classes so that classes precede super classes.
1735 Classes.sort();
1736
1737#ifdef EXPENSIVE_CHECKS
1738 // Verify that the table is sorted and operator < works transitively.
1739 for (auto I = Classes.begin(), E = Classes.end(); I != E; ++I) {
1740 for (auto J = I; J != E; ++J) {
1741 assert(!(*J < *I));
1742 assert(I == J || !J->isSubsetOf(*I));
1743 }
1744 }
1745#endif
1746}
1747
1748/// buildInstructionOperandReference - The specified operand is a reference to a
1749/// named operand such as $src. Resolve the Class and OperandInfo pointers.
1750void AsmMatcherInfo::buildInstructionOperandReference(MatchableInfo *II,
1751 StringRef OperandName,
1752 unsigned AsmOpIdx) {
1753 const CodeGenInstruction &CGI = *cast<const CodeGenInstruction *>(Val&: II->DefRec);
1754 const CGIOperandList &Operands = CGI.Operands;
1755 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1756
1757 // Map this token to an operand.
1758 std::optional<unsigned> Idx = Operands.findOperandNamed(Name: OperandName);
1759 if (!Idx)
1760 PrintFatalError(ErrorLoc: II->TheDef->getLoc(),
1761 Msg: "error: unable to find operand: '" + OperandName + "'");
1762 // If the instruction operand has multiple suboperands, but the parser
1763 // match class for the asm operand is still the default "ImmAsmOperand",
1764 // then handle each suboperand separately.
1765 if (Op->SubOpIdx == -1 && Operands[*Idx].MINumOperands > 1) {
1766 const Record *Rec = Operands[*Idx].Rec;
1767 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1768 const Record *MatchClass = Rec->getValueAsDef(FieldName: "ParserMatchClass");
1769 if (MatchClass && MatchClass->getValueAsString(FieldName: "Name") == "Imm") {
1770 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1771 StringRef Token = Op->Token; // save this in case Op gets moved
1772 for (unsigned SI = 1, SE = Operands[*Idx].MINumOperands; SI != SE; ++SI) {
1773 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1774 NewAsmOp.SubOpIdx = SI;
1775 II->AsmOperands.insert(I: II->AsmOperands.begin() + AsmOpIdx + SI,
1776 Elt: NewAsmOp);
1777 }
1778 // Replace Op with first suboperand.
1779 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1780 Op->SubOpIdx = 0;
1781 }
1782 }
1783
1784 // Set up the operand class.
1785 Op->Class = getOperandClass(OI: Operands[*Idx], SubOpIdx: Op->SubOpIdx);
1786 Op->OrigSrcOpName = OperandName;
1787
1788 // If the named operand is tied, canonicalize it to the untied operand.
1789 // For example, something like:
1790 // (outs GPR:$dst), (ins GPR:$src)
1791 // with an asmstring of
1792 // "inc $src"
1793 // we want to canonicalize to:
1794 // "inc $dst"
1795 // so that we know how to provide the $dst operand when filling in the result.
1796 int OITied = -1;
1797 if (Operands[*Idx].MINumOperands == 1)
1798 OITied = Operands[*Idx].getTiedRegister();
1799 if (OITied != -1) {
1800 // The tied operand index is an MIOperand index, find the operand that
1801 // contains it.
1802 auto [OpIdx, SubopIdx] = Operands.getSubOperandNumber(Op: OITied);
1803 OperandName = Operands[OpIdx].Name;
1804 Op->SubOpIdx = SubopIdx;
1805 }
1806
1807 Op->SrcOpName = OperandName;
1808}
1809
1810/// buildAliasOperandReference - When parsing an operand reference out of the
1811/// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1812/// operand reference is by looking it up in the result pattern definition.
1813void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1814 StringRef OperandName,
1815 MatchableInfo::AsmOperand &Op) {
1816 const CodeGenInstAlias &CGA = *cast<const CodeGenInstAlias *>(Val&: II->DefRec);
1817
1818 // Set up the operand class.
1819 for (const auto &[ResultOp, SubOpIdx] :
1820 zip_equal(t: CGA.ResultOperands, u: CGA.ResultInstOperandIndex)) {
1821 if (ResultOp.isRecord() && ResultOp.getName() == OperandName) {
1822 // It's safe to go with the first one we find, because CodeGenInstAlias
1823 // validates that all operands with the same name have the same record.
1824 Op.SubOpIdx = SubOpIdx.second;
1825 // Use the match class from the Alias definition, not the
1826 // destination instruction, as we may have an immediate that's
1827 // being munged by the match class.
1828 Op.Class = getOperandClass(Rec: ResultOp.getRecord(), SubOpIdx: Op.SubOpIdx);
1829 Op.SrcOpName = OperandName;
1830 Op.OrigSrcOpName = OperandName;
1831 return;
1832 }
1833 }
1834
1835 PrintFatalError(ErrorLoc: II->TheDef->getLoc(),
1836 Msg: "error: unable to find operand: '" + OperandName + "'");
1837}
1838
1839void MatchableInfo::buildInstructionResultOperands() {
1840 const CodeGenInstruction *ResultInst = getResultInst();
1841
1842 // Loop over all operands of the result instruction, determining how to
1843 // populate them.
1844 for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
1845 // If this is a tied operand, just copy from the previously handled operand.
1846 int TiedOp = -1;
1847 if (OpInfo.MINumOperands == 1)
1848 TiedOp = OpInfo.getTiedRegister();
1849 if (TiedOp != -1) {
1850 int TiedSrcOperand = findAsmOperandOriginallyNamed(N: OpInfo.Name);
1851 if (TiedSrcOperand != -1 &&
1852 ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand)
1853 ResOperands.push_back(Elt: ResOperand::getTiedOp(
1854 TiedOperandNum: TiedOp, SrcOperand1: ResOperands[TiedOp].AsmOperandNum, SrcOperand2: TiedSrcOperand));
1855 else
1856 ResOperands.push_back(Elt: ResOperand::getTiedOp(TiedOperandNum: TiedOp, SrcOperand1: 0, SrcOperand2: 0));
1857 continue;
1858 }
1859
1860 int SrcOperand = findAsmOperandNamed(N: OpInfo.Name);
1861 if (OpInfo.Name.empty() || SrcOperand == -1) {
1862 // This may happen for operands that are tied to a suboperand of a
1863 // complex operand. Simply use a dummy value here; nobody should
1864 // use this operand slot.
1865 // FIXME: The long term goal is for the MCOperand list to not contain
1866 // tied operands at all.
1867 ResOperands.push_back(Elt: ResOperand::getImmOp(Val: 0));
1868 continue;
1869 }
1870
1871 // Check if the one AsmOperand populates the entire operand.
1872 unsigned NumOperands = OpInfo.MINumOperands;
1873 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1874 ResOperands.push_back(Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand, NumOperands));
1875 continue;
1876 }
1877
1878 // Add a separate ResOperand for each suboperand.
1879 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1880 assert(AsmOperands[SrcOperand + AI].SubOpIdx == (int)AI &&
1881 AsmOperands[SrcOperand + AI].SrcOpName == OpInfo.Name &&
1882 "unexpected AsmOperands for suboperands");
1883 ResOperands.push_back(Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand + AI, NumOperands: 1));
1884 }
1885 }
1886}
1887
1888void MatchableInfo::buildAliasResultOperands(bool AliasConstraintsAreChecked) {
1889 const CodeGenInstAlias &CGA = *cast<const CodeGenInstAlias *>(Val&: DefRec);
1890 const CodeGenInstruction *ResultInst = getResultInst();
1891
1892 // Map of: $reg -> #lastref
1893 // where $reg is the name of the operand in the asm string
1894 // where #lastref is the last processed index where $reg was referenced in
1895 // the asm string.
1896 SmallDenseMap<StringRef, int> OperandRefs;
1897
1898 // Loop over all operands of the result instruction, determining how to
1899 // populate them.
1900 unsigned AliasOpNo = 0;
1901 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1902 for (const auto &[Idx, OpInfo] : enumerate(First: ResultInst->Operands)) {
1903 // If this is a tied operand, just copy from the previously handled operand.
1904 int TiedOp = -1;
1905 if (OpInfo.MINumOperands == 1)
1906 TiedOp = OpInfo.getTiedRegister();
1907 if (TiedOp != -1) {
1908 unsigned SrcOp1 = 0;
1909 unsigned SrcOp2 = 0;
1910
1911 // If an operand has been specified twice in the asm string,
1912 // add the two source operand's indices to the TiedOp so that
1913 // at runtime the 'tied' constraint is checked.
1914 if (ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand) {
1915 SrcOp1 = ResOperands[TiedOp].AsmOperandNum;
1916
1917 // Find the next operand (similarly named operand) in the string.
1918 StringRef Name = AsmOperands[SrcOp1].SrcOpName;
1919 auto Insert = OperandRefs.try_emplace(Key: Name, Args&: SrcOp1);
1920 SrcOp2 = findAsmOperandNamed(N: Name, LastIdx: Insert.first->second);
1921
1922 // Not updating the record in OperandRefs will cause TableGen
1923 // to fail with an error at the end of this function.
1924 if (AliasConstraintsAreChecked)
1925 Insert.first->second = SrcOp2;
1926
1927 // In case it only has one reference in the asm string,
1928 // it doesn't need to be checked for tied constraints.
1929 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2;
1930 }
1931
1932 // If the alias operand is of a different operand class, we only want
1933 // to benefit from the tied-operands check and just match the operand
1934 // as a normal, but not copy the original (TiedOp) to the result
1935 // instruction. We do this by passing -1 as the tied operand to copy.
1936 if (OpInfo.Rec->getName() !=
1937 ResultInst->Operands[TiedOp].Rec->getName()) {
1938 SrcOp1 = ResOperands[TiedOp].AsmOperandNum;
1939 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1940 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1941 SrcOp2 = findAsmOperand(N: Name, SubOpIdx: SubIdx);
1942 ResOperands.push_back(
1943 Elt: ResOperand::getTiedOp(TiedOperandNum: (unsigned)-1, SrcOperand1: SrcOp1, SrcOperand2: SrcOp2));
1944 } else {
1945 ResOperands.push_back(Elt: ResOperand::getTiedOp(TiedOperandNum: TiedOp, SrcOperand1: SrcOp1, SrcOperand2: SrcOp2));
1946 continue;
1947 }
1948 }
1949
1950 // Handle all the suboperands for this operand.
1951 StringRef OpName = OpInfo.Name;
1952 for (; AliasOpNo < LastOpNo &&
1953 CGA.ResultInstOperandIndex[AliasOpNo].first == Idx;
1954 ++AliasOpNo) {
1955 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1956
1957 // Find out what operand from the asmparser that this MCInst operand
1958 // comes from.
1959 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1960 case CodeGenInstAlias::ResultOperand::K_Record: {
1961 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1962 int SrcOperand = findAsmOperand(N: Name, SubOpIdx: SubIdx);
1963 if (SrcOperand == -1)
1964 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1965 Msg: "Instruction '" + TheDef->getName() +
1966 "' has operand '" + OpName +
1967 "' that doesn't appear in asm string!");
1968
1969 // Add it to the operand references. If it is added a second time, the
1970 // record won't be updated and it will fail later on.
1971 OperandRefs.try_emplace(Key: Name, Args&: SrcOperand);
1972
1973 unsigned NumOperands = (SubIdx == -1 ? OpInfo.MINumOperands : 1);
1974 ResOperands.push_back(
1975 Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand, NumOperands));
1976 break;
1977 }
1978 case CodeGenInstAlias::ResultOperand::K_Imm: {
1979 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1980 ResOperands.push_back(Elt: ResOperand::getImmOp(Val: ImmVal));
1981 break;
1982 }
1983 case CodeGenInstAlias::ResultOperand::K_Reg: {
1984 const Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1985 ResOperands.push_back(Elt: ResOperand::getRegOp(Reg));
1986 break;
1987 }
1988 }
1989 }
1990 }
1991
1992 // Check that operands are not repeated more times than is supported.
1993 for (auto &T : OperandRefs) {
1994 if (T.second != -1 && findAsmOperandNamed(N: T.first, LastIdx: T.second) != -1)
1995 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1996 Msg: "Operand '" + T.first + "' can never be matched");
1997 }
1998}
1999
2000static unsigned
2001getConverterOperandID(const std::string &Name,
2002 SmallSetVector<CachedHashString, 16> &Table,
2003 bool &IsNew) {
2004 IsNew = Table.insert(X: CachedHashString(Name));
2005
2006 unsigned ID = IsNew ? Table.size() - 1 : find(Range&: Table, Val: Name) - Table.begin();
2007
2008 assert(ID < Table.size());
2009
2010 return ID;
2011}
2012
2013static unsigned
2014emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
2015 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
2016 bool HasMnemonicFirst, bool HasOptionalOperands,
2017 raw_ostream &OS) {
2018 SmallSetVector<CachedHashString, 16> OperandConversionKinds;
2019 SmallSetVector<CachedHashString, 16> InstructionConversionKinds;
2020 std::vector<std::vector<uint8_t>> ConversionTable;
2021
2022 // minimum is custom converter plus a operand index in parsed OperandVector
2023 // (0 for custom converter) and terminator (CVT_Done).
2024 size_t MaxRowLength = 3;
2025
2026 // TargetOperandClass - This is the target's operand class, like X86Operand.
2027 std::string TargetOperandClass = Target.getName().str() + "Operand";
2028
2029 // Write the convert function to a separate stream, so we can drop it after
2030 // the enum. We'll build up the conversion handlers for the individual
2031 // operand types opportunistically as we encounter them.
2032 std::string ConvertFnBody;
2033 raw_string_ostream CvtOS(ConvertFnBody);
2034 // Start the unified conversion function.
2035 if (HasOptionalOperands) {
2036 CvtOS << "void " << Target.getName() << ClassName << "::\n"
2037 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
2038 << "unsigned Opcode,\n"
2039 << " const OperandVector &Operands,\n"
2040 << " const SmallBitVector &OptionalOperandsMask,\n"
2041 << " ArrayRef<unsigned> DefaultsOffset) {\n";
2042 } else {
2043 CvtOS << "void " << Target.getName() << ClassName << "::\n"
2044 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
2045 << "unsigned Opcode,\n"
2046 << " const OperandVector &Operands) {\n";
2047 }
2048 CvtOS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
2049 CvtOS << " const uint8_t *Converter = ConversionTable[Kind];\n";
2050 CvtOS << " Inst.setOpcode(Opcode);\n";
2051 CvtOS << " for (const uint8_t *p = Converter; *p; p += 2) {\n";
2052 if (HasOptionalOperands) {
2053 // When optional operands are involved, formal and actual operand indices
2054 // may differ. Map the former to the latter by subtracting the number of
2055 // absent optional operands.
2056 // FIXME: This is not an operand index in the CVT_Tied case
2057 CvtOS << " unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];\n";
2058 } else {
2059 CvtOS << " unsigned OpIdx = *(p + 1);\n";
2060 }
2061 CvtOS << " switch (*p) {\n";
2062 CvtOS << " default: llvm_unreachable(\"invalid conversion entry!\");\n";
2063 CvtOS << " case CVT_Reg:\n";
2064 CvtOS << " static_cast<" << TargetOperandClass
2065 << " &>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";
2066 CvtOS << " break;\n";
2067 CvtOS << " case CVT_Tied: {\n";
2068 CvtOS << " assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -\n";
2069 CvtOS
2070 << " std::begin(TiedAsmOperandTable)) &&\n";
2071 CvtOS << " \"Tied operand not found\");\n";
2072 CvtOS << " unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];\n";
2073 CvtOS << " if (TiedResOpnd != (uint8_t)-1)\n";
2074 CvtOS << " Inst.addOperand(Inst.getOperand(TiedResOpnd));\n";
2075 CvtOS << " break;\n";
2076 CvtOS << " }\n";
2077
2078 std::string OperandFnBody;
2079 raw_string_ostream OpOS(OperandFnBody);
2080 // Start the operand number lookup function.
2081 OpOS << "void " << Target.getName() << ClassName << "::\n"
2082 << "convertToMapAndConstraints(unsigned Kind,\n";
2083 OpOS.indent(NumSpaces: 27);
2084 OpOS << "const OperandVector &Operands) {\n"
2085 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
2086 << " unsigned NumMCOperands = 0;\n"
2087 << " const uint8_t *Converter = ConversionTable[Kind];\n"
2088 << " for (const uint8_t *p = Converter; *p; p += 2) {\n"
2089 << " switch (*p) {\n"
2090 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
2091 << " case CVT_Reg:\n"
2092 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2093 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
2094 << " ++NumMCOperands;\n"
2095 << " break;\n"
2096 << " case CVT_Tied:\n"
2097 << " ++NumMCOperands;\n"
2098 << " break;\n";
2099
2100 // Pre-populate the operand conversion kinds with the standard always
2101 // available entries.
2102 OperandConversionKinds.insert(X: CachedHashString("CVT_Done"));
2103 OperandConversionKinds.insert(X: CachedHashString("CVT_Reg"));
2104 OperandConversionKinds.insert(X: CachedHashString("CVT_Tied"));
2105 enum { CVT_Done, CVT_Reg, CVT_Tied };
2106
2107 // Map of e.g. <0, 2, 3> -> "Tie_0_2_3" enum label.
2108 std::map<std::tuple<uint8_t, uint8_t, uint8_t>, std::string>
2109 TiedOperandsEnumMap;
2110
2111 for (auto &II : Infos) {
2112 // Check if we have a custom match function.
2113 StringRef AsmMatchConverter =
2114 II->getResultInst()->TheDef->getValueAsString(FieldName: "AsmMatchConverter");
2115 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
2116 std::string Signature = ("ConvertCustom_" + AsmMatchConverter).str();
2117 II->ConversionFnKind = Signature;
2118
2119 // Check if we have already generated this signature.
2120 if (!InstructionConversionKinds.insert(X: CachedHashString(Signature)))
2121 continue;
2122
2123 // Remember this converter for the kind enum.
2124 unsigned KindID = OperandConversionKinds.size();
2125 OperandConversionKinds.insert(
2126 X: CachedHashString("CVT_" + getEnumNameForToken(Str: AsmMatchConverter)));
2127
2128 // Add the converter row for this instruction.
2129 ConversionTable.emplace_back();
2130 ConversionTable.back().push_back(x: KindID);
2131 ConversionTable.back().push_back(x: CVT_Done);
2132
2133 // Add the handler to the conversion driver function.
2134 CvtOS << " case CVT_" << getEnumNameForToken(Str: AsmMatchConverter)
2135 << ":\n"
2136 << " " << AsmMatchConverter << "(Inst, Operands);\n"
2137 << " break;\n";
2138
2139 // FIXME: Handle the operand number lookup for custom match functions.
2140 continue;
2141 }
2142
2143 // Build the conversion function signature.
2144 std::string Signature = "Convert";
2145
2146 std::vector<uint8_t> ConversionRow;
2147
2148 // Compute the convert enum and the case body.
2149 MaxRowLength = std::max(a: MaxRowLength, b: II->ResOperands.size() * 2 + 1);
2150
2151 for (const auto &[Idx, OpInfo] : enumerate(First&: II->ResOperands)) {
2152 // Generate code to populate each result operand.
2153 switch (OpInfo.Kind) {
2154 case MatchableInfo::ResOperand::RenderAsmOperand: {
2155 // This comes from something we parsed.
2156 const MatchableInfo::AsmOperand &Op =
2157 II->AsmOperands[OpInfo.AsmOperandNum];
2158
2159 // Registers are always converted the same, don't duplicate the
2160 // conversion function based on them.
2161 Signature += "__";
2162 std::string Class;
2163 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
2164 Signature += Class;
2165 Signature += utostr(X: OpInfo.MINumOperands);
2166 Signature += "_" + itostr(X: OpInfo.AsmOperandNum);
2167
2168 // Add the conversion kind, if necessary, and get the associated ID
2169 // the index of its entry in the vector).
2170 std::string Name =
2171 "CVT_" +
2172 (Op.Class->isRegisterClass() ? "Reg" : Op.Class->RenderMethod);
2173 if (Op.Class->IsOptional) {
2174 // For optional operands we must also care about DefaultMethod
2175 assert(HasOptionalOperands);
2176 Name += "_" + Op.Class->DefaultMethod;
2177 }
2178 Name = getEnumNameForToken(Str: Name);
2179
2180 bool IsNewConverter = false;
2181 unsigned ID =
2182 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2183
2184 // Add the operand entry to the instruction kind conversion row.
2185 ConversionRow.push_back(x: ID);
2186 ConversionRow.push_back(x: OpInfo.AsmOperandNum + HasMnemonicFirst);
2187
2188 if (!IsNewConverter)
2189 break;
2190
2191 // This is a new operand kind. Add a handler for it to the
2192 // converter driver.
2193 CvtOS << " case " << Name << ":\n";
2194 if (Op.Class->IsOptional) {
2195 // If optional operand is not present in actual instruction then we
2196 // should call its DefaultMethod before RenderMethod
2197 assert(HasOptionalOperands);
2198 CvtOS << " if (OptionalOperandsMask[*(p + 1)]) {\n"
2199 << " " << Op.Class->DefaultMethod << "()"
2200 << "->" << Op.Class->RenderMethod << "(Inst, "
2201 << OpInfo.MINumOperands << ");\n"
2202 << " } else {\n"
2203 << " static_cast<" << TargetOperandClass
2204 << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod
2205 << "(Inst, " << OpInfo.MINumOperands << ");\n"
2206 << " }\n";
2207 } else {
2208 CvtOS << " static_cast<" << TargetOperandClass
2209 << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod
2210 << "(Inst, " << OpInfo.MINumOperands << ");\n";
2211 }
2212 CvtOS << " break;\n";
2213
2214 // Add a handler for the operand number lookup.
2215 OpOS << " case " << Name << ":\n"
2216 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
2217
2218 if (Op.Class->isRegisterClass())
2219 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
2220 else
2221 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
2222 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
2223 << " break;\n";
2224 break;
2225 }
2226 case MatchableInfo::ResOperand::TiedOperand: {
2227 // If this operand is tied to a previous one, just copy the MCInst
2228 // operand from the earlier one.We can only tie single MCOperand values.
2229 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
2230 uint8_t TiedOp = OpInfo.TiedOperands.ResOpnd;
2231 uint8_t SrcOp1 = OpInfo.TiedOperands.SrcOpnd1Idx + HasMnemonicFirst;
2232 uint8_t SrcOp2 = OpInfo.TiedOperands.SrcOpnd2Idx + HasMnemonicFirst;
2233 assert((Idx > TiedOp || TiedOp == (uint8_t)-1) &&
2234 "Tied operand precedes its target!");
2235 auto TiedTupleName = std::string("Tie") + utostr(X: TiedOp) + '_' +
2236 utostr(X: SrcOp1) + '_' + utostr(X: SrcOp2);
2237 Signature += "__" + TiedTupleName;
2238 ConversionRow.push_back(x: CVT_Tied);
2239 ConversionRow.push_back(x: TiedOp);
2240 ConversionRow.push_back(x: SrcOp1);
2241 ConversionRow.push_back(x: SrcOp2);
2242
2243 // Also create an 'enum' for this combination of tied operands.
2244 auto Key = std::tuple(TiedOp, SrcOp1, SrcOp2);
2245 TiedOperandsEnumMap.emplace(args&: Key, args&: TiedTupleName);
2246 break;
2247 }
2248 case MatchableInfo::ResOperand::ImmOperand: {
2249 int64_t Val = OpInfo.ImmVal;
2250 std::string Ty = "imm_" + itostr(X: Val);
2251 Ty = getEnumNameForToken(Str: Ty);
2252 Signature += "__" + Ty;
2253
2254 std::string Name = "CVT_" + Ty;
2255 bool IsNewConverter = false;
2256 unsigned ID =
2257 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2258 // Add the operand entry to the instruction kind conversion row.
2259 ConversionRow.push_back(x: ID);
2260 ConversionRow.push_back(x: 0);
2261
2262 if (!IsNewConverter)
2263 break;
2264
2265 CvtOS << " case " << Name << ":\n"
2266 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
2267 << " break;\n";
2268
2269 OpOS << " case " << Name << ":\n"
2270 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2271 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
2272 << " ++NumMCOperands;\n"
2273 << " break;\n";
2274 break;
2275 }
2276 case MatchableInfo::ResOperand::RegOperand: {
2277 std::string Reg, Name;
2278 bool IsRegByHwMode = false;
2279 if (!OpInfo.Register) {
2280 Name = "reg0";
2281 Reg = "0";
2282 } else {
2283 Reg = getQualifiedName(R: OpInfo.Register);
2284 Name = "reg" + OpInfo.Register->getName().str();
2285 IsRegByHwMode = OpInfo.Register->isSubClassOf(Name: "RegisterByHwMode");
2286 }
2287 Signature += "__" + Name;
2288 Name = "CVT_" + Name;
2289 bool IsNewConverter = false;
2290 unsigned ID =
2291 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2292 // Add the operand entry to the instruction kind conversion row.
2293 ConversionRow.push_back(x: ID);
2294 ConversionRow.push_back(x: 0);
2295
2296 if (!IsNewConverter)
2297 break;
2298
2299 CvtOS << indent(4) << "case " << Name << ":\n"
2300 << indent(6) << "Inst.addOperand(MCOperand::createReg(";
2301 if (IsRegByHwMode) {
2302 RegisterByHwMode(OpInfo.Register, Target.getRegBank())
2303 .emitResolverCall(
2304 OS&: CvtOS, HwMode: "STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo)");
2305 } else {
2306 CvtOS << Reg;
2307 }
2308 CvtOS << "));\n" << indent(6) << "break;\n";
2309 OpOS << " case " << Name << ":\n"
2310 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2311 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
2312 << " ++NumMCOperands;\n"
2313 << " break;\n";
2314 }
2315 }
2316 }
2317
2318 // If there were no operands, add to the signature to that effect
2319 if (Signature == "Convert")
2320 Signature += "_NoOperands";
2321
2322 II->ConversionFnKind = Signature;
2323
2324 // Save the signature. If we already have it, don't add a new row
2325 // to the table.
2326 if (!InstructionConversionKinds.insert(X: CachedHashString(Signature)))
2327 continue;
2328
2329 // Add the row to the table.
2330 ConversionTable.push_back(x: std::move(ConversionRow));
2331 }
2332
2333 // Finish up the converter driver function.
2334 CvtOS << " }\n }\n}\n\n";
2335
2336 // Finish up the operand number lookup function.
2337 OpOS << " }\n }\n}\n\n";
2338
2339 // Output a static table for tied operands.
2340 if (TiedOperandsEnumMap.size()) {
2341 // The number of tied operand combinations will be small in practice,
2342 // but just add the assert to be sure.
2343 assert(TiedOperandsEnumMap.size() <= 254 &&
2344 "Too many tied-operand combinations to reference with "
2345 "an 8bit offset from the conversion table, where index "
2346 "'255' is reserved as operand not to be copied.");
2347
2348 OS << "enum {\n";
2349 for (auto &KV : TiedOperandsEnumMap) {
2350 OS << " " << KV.second << ",\n";
2351 }
2352 OS << "};\n\n";
2353
2354 OS << "static const uint8_t TiedAsmOperandTable[][3] = {\n";
2355 for (auto &KV : TiedOperandsEnumMap) {
2356 OS << " /* " << KV.second << " */ { " << utostr(X: std::get<0>(t: KV.first))
2357 << ", " << utostr(X: std::get<1>(t: KV.first)) << ", "
2358 << utostr(X: std::get<2>(t: KV.first)) << " },\n";
2359 }
2360 OS << "};\n\n";
2361 } else {
2362 OS << "static const uint8_t TiedAsmOperandTable[][3] = "
2363 "{ /* empty */ {0, 0, 0} };\n\n";
2364 }
2365
2366 OS << "namespace {\n";
2367
2368 // Output the operand conversion kind enum.
2369 OS << "enum OperatorConversionKind {\n";
2370 for (const auto &Converter : OperandConversionKinds)
2371 OS << " " << Converter << ",\n";
2372 OS << " CVT_NUM_CONVERTERS\n";
2373 OS << "};\n\n";
2374
2375 // Output the instruction conversion kind enum.
2376 OS << "enum InstructionConversionKind {\n";
2377 for (const auto &Signature : InstructionConversionKinds)
2378 OS << " " << Signature << ",\n";
2379 OS << " CVT_NUM_SIGNATURES\n";
2380 OS << "};\n\n";
2381
2382 OS << "} // end anonymous namespace\n\n";
2383
2384 // Output the conversion table.
2385 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2386 << MaxRowLength << "] = {\n";
2387
2388 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2389 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2390 OS << " // " << InstructionConversionKinds[Row] << "\n";
2391 OS << " { ";
2392 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2) {
2393 const auto &OCK = OperandConversionKinds[ConversionTable[Row][i]];
2394 OS << OCK << ", ";
2395 if (OCK != CachedHashString("CVT_Tied")) {
2396 OS << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2397 continue;
2398 }
2399
2400 // For a tied operand, emit a reference to the TiedAsmOperandTable
2401 // that contains the operand to copy, and the parsed operands to
2402 // check for their tied constraints.
2403 auto Key = std::tuple((uint8_t)ConversionTable[Row][i + 1],
2404 (uint8_t)ConversionTable[Row][i + 2],
2405 (uint8_t)ConversionTable[Row][i + 3]);
2406 auto TiedOpndEnum = TiedOperandsEnumMap.find(x: Key);
2407 assert(TiedOpndEnum != TiedOperandsEnumMap.end() &&
2408 "No record for tied operand pair");
2409 OS << TiedOpndEnum->second << ", ";
2410 i += 2;
2411 }
2412 OS << "CVT_Done },\n";
2413 }
2414
2415 OS << "};\n\n";
2416
2417 // Spit out the conversion driver function.
2418 OS << ConvertFnBody;
2419
2420 // Spit out the operand number lookup function.
2421 OS << OperandFnBody;
2422
2423 return ConversionTable.size();
2424}
2425
2426/// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2427static void emitMatchClassEnumeration(CodeGenTarget &Target,
2428 std::forward_list<ClassInfo> &Infos,
2429 raw_ostream &OS) {
2430 OS << "namespace {\n\n";
2431
2432 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2433 << "/// instruction matching.\n";
2434 OS << "enum MatchClassKind {\n";
2435 OS << " InvalidMatchClass = 0,\n";
2436 OS << " OptionalMatchClass = 1,\n";
2437 ClassInfo::ClassInfoKind LastKind = ClassInfo::Token;
2438 StringRef LastName = "OptionalMatchClass";
2439 for (const auto &CI : Infos) {
2440 if (LastKind == ClassInfo::Token && CI.Kind != ClassInfo::Token) {
2441 OS << " MCK_LAST_TOKEN = " << LastName << ",\n";
2442 } else if (LastKind < ClassInfo::RegisterClassByHwMode0 &&
2443 CI.Kind >= ClassInfo::RegisterClassByHwMode0) {
2444 OS << " MCK_LAST_REGISTER = " << LastName << ",\n";
2445 } else if (LastKind < ClassInfo::UserClass0 &&
2446 CI.Kind >= ClassInfo::UserClass0) {
2447 OS << " MCK_LAST_REGCLASS_BY_HWMODE = " << LastName << ",\n";
2448 }
2449
2450 LastKind = (ClassInfo::ClassInfoKind)CI.Kind;
2451 LastName = CI.Name;
2452
2453 OS << " " << CI.Name << ", // ";
2454 if (CI.Kind == ClassInfo::Token) {
2455 OS << "'" << CI.ValueName << "'\n";
2456 } else if (CI.isRegisterClass()) {
2457 if (!CI.ValueName.empty())
2458 OS << "register class '" << CI.ValueName << "'\n";
2459 else
2460 OS << "derived register class\n";
2461 } else if (CI.isRegisterClassByHwMode()) {
2462 OS << "register class by hwmode\n";
2463 } else {
2464 OS << "user defined class '" << CI.ValueName << "'\n";
2465 }
2466 }
2467 OS << " NumMatchClassKinds\n";
2468 OS << "};\n\n";
2469
2470 OS << "} // end anonymous namespace\n\n";
2471}
2472
2473/// emitMatchClassDiagStrings - Emit a function to get the diagnostic text to be
2474/// used when an assembly operand does not match the expected operand class.
2475static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info,
2476 raw_ostream &OS) {
2477 // If the target does not use DiagnosticString for any operands, don't emit
2478 // an unused function.
2479 if (llvm::all_of(Range&: Info.Classes, P: [](const ClassInfo &CI) {
2480 return CI.DiagnosticString.empty();
2481 }))
2482 return;
2483
2484 OS << "static const char *getMatchKindDiag(" << Info.Target.getName()
2485 << "AsmParser::" << Info.Target.getName()
2486 << "MatchResultTy MatchResult) {\n";
2487 OS << " switch (MatchResult) {\n";
2488
2489 for (const auto &CI : Info.Classes) {
2490 if (!CI.DiagnosticString.empty()) {
2491 assert(!CI.DiagnosticType.empty() &&
2492 "DiagnosticString set without DiagnosticType");
2493 OS << " case " << Info.Target.getName() << "AsmParser::Match_"
2494 << CI.DiagnosticType << ":\n";
2495 OS << " return \"" << CI.DiagnosticString << "\";\n";
2496 }
2497 }
2498
2499 OS << " default:\n";
2500 OS << " return nullptr;\n";
2501
2502 OS << " }\n";
2503 OS << "}\n\n";
2504}
2505
2506static void emitRegisterMatchErrorFunc(AsmMatcherInfo &Info, raw_ostream &OS) {
2507 OS << "static unsigned getDiagKindFromRegisterClass(MatchClassKind "
2508 "RegisterClass) {\n";
2509 if (none_of(Range&: Info.Classes, P: [](const ClassInfo &CI) {
2510 return CI.isRegisterClass() && !CI.DiagnosticType.empty();
2511 })) {
2512 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2513 } else {
2514 OS << " switch (RegisterClass) {\n";
2515 for (const auto &CI : Info.Classes) {
2516 if (CI.isRegisterClass() && !CI.DiagnosticType.empty()) {
2517 OS << " case " << CI.Name << ":\n";
2518 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2519 << CI.DiagnosticType << ";\n";
2520 }
2521 }
2522
2523 OS << " default:\n";
2524 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2525
2526 OS << " }\n";
2527 }
2528 OS << "}\n\n";
2529}
2530
2531/// emitTokenDiagFunction - Emit a function mapping token class kinds to
2532/// diagnostics.
2533static void emitTokenDiagFunction(AsmMatcherInfo &Info, raw_ostream &OS) {
2534 OS << "static unsigned getDiagKindFromTokenClass(MatchClassKind Kind) {\n";
2535 OS << " switch (Kind) {\n";
2536 OS << " default:\n";
2537 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2538 for (const auto &CI : Info.Classes) {
2539 if (CI.Kind == ClassInfo::Token && !CI.DiagnosticType.empty()) {
2540 OS << " case " << CI.Name << ":\n";
2541 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2542 << CI.DiagnosticType << ";\n";
2543 }
2544 }
2545 OS << " }\n";
2546 OS << "}\n\n";
2547}
2548
2549// Returns true if ClassName corresponds to a RegisterClass defined in the
2550// target description (and thus has a generated RegClassID), rather than a
2551// singleton register or an anonymous derived register class.
2552static bool isDefinedRegisterClass(const AsmMatcherInfo &Info,
2553 StringRef ClassName) {
2554 for (const auto &RC : Info.Target.getRegBank().getRegClasses()) {
2555 if (RC.getName() == ClassName)
2556 return true;
2557 }
2558 return false;
2559}
2560
2561static void emitGetRegClassFromMatchKindFunc(AsmMatcherInfo &Info,
2562 raw_ostream &OS) {
2563 OS << "[[maybe_unused]] static const MCRegisterClass "
2564 "*getRegClassFromMatchKind(MatchClassKind Kind) {\n";
2565 OS << " switch (Kind) {\n";
2566
2567 // Emit the straightforward RegisterClass mapping.
2568 for (const auto &CI : Info.Classes) {
2569 if (CI.isRegisterClass() && !CI.ValueName.empty() &&
2570 isDefinedRegisterClass(Info, ClassName: CI.ClassName)) {
2571 OS << " case " << CI.Name << ":\n";
2572 OS << " return &get" << Info.Target.getName() << "MCRegisterClass("
2573 << Info.Target.getName() << "::" << CI.ClassName << "RegClassID);\n";
2574 }
2575 }
2576
2577 // Next Collect RegisterOperand MCK_* -> RegisterClass mappings and emit
2578 // it for all non-ambiguous RegisterOperands.
2579 // Many targets reuse the same ParserMatchClass for different register
2580 // classes so we can't emit a these unconditionally.
2581 std::map<const ClassInfo *, const ClassInfo *, deref<std::less<>>>
2582 UserClassToRegClassMap;
2583 for (const Record *RO :
2584 Info.Records.getAllDerivedDefinitions(ClassName: "RegisterOperand")) {
2585 const RecordVal *R = RO->getValue(Name: "ParserMatchClass");
2586 if (!R)
2587 continue;
2588 const DefInit *DI = dyn_cast<DefInit>(Val: R->getValue());
2589 if (!DI)
2590 continue;
2591 const Record *PMC = DI->getDef();
2592 const Record *RC = RO->getValueAsDef(FieldName: "RegClass");
2593 if (!RC || !RC->isSubClassOf(Name: "RegisterClassLike"))
2594 continue;
2595 auto PMC_It = Info.AsmOperandClasses.find(x: PMC);
2596 auto RC_It = Info.RegisterClassClasses.find(x: RC);
2597 if (PMC_It == Info.AsmOperandClasses.end() ||
2598 RC_It == Info.RegisterClassClasses.end())
2599 continue;
2600 const ClassInfo *UserCI = PMC_It->second;
2601 const ClassInfo *RegCI = RC_It->second;
2602
2603 auto It = UserClassToRegClassMap.find(x: UserCI);
2604 if (It == UserClassToRegClassMap.end()) {
2605 UserClassToRegClassMap[UserCI] = RegCI;
2606 } else if (It->second && It->second != RegCI) {
2607 // TODO: Warn about ambiguous ParserMatchClass mapping when we can.
2608 // Many targets currently have ambiguous mappings.
2609 It->second = nullptr; // Mark as ambiguous
2610 }
2611 }
2612 for (const auto [UserCI, RegCI] : UserClassToRegClassMap) {
2613 if (RegCI && isDefinedRegisterClass(Info, ClassName: RegCI->ClassName)) {
2614 OS << " case " << UserCI->Name << ":\n";
2615 OS << " return &get" << Info.Target.getName() << "MCRegisterClass("
2616 << Info.Target.getName() << "::" << RegCI->ClassName
2617 << "RegClassID);\n";
2618 }
2619 }
2620
2621 OS << " default:\n";
2622 OS << " return nullptr;\n";
2623 OS << " }\n";
2624 OS << "}\n\n";
2625}
2626
2627/// emitValidateOperandClass - Emit the function to validate an operand class.
2628static void emitValidateOperandClass(const CodeGenTarget &Target,
2629 AsmMatcherInfo &Info, raw_ostream &OS) {
2630 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2631 << "MatchClassKind Kind, const MCSubtargetInfo &STI) {\n";
2632 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2633 << Info.Target.getName() << "Operand &)GOp;\n";
2634
2635 // The InvalidMatchClass is not to match any operand.
2636 OS << " if (Kind == InvalidMatchClass)\n";
2637 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2638
2639 // Check for Token operands first.
2640 OS << " if (Kind <= MCK_LAST_TOKEN) {\n";
2641 OS << " if (Operand.isToken() &&\n"
2642 << " isSubclass(matchTokenString(Operand.getToken()), Kind))\n";
2643 OS << " return MCTargetAsmParser::Match_Success;\n";
2644 if (Info.AsmParser->getValueAsBit(FieldName: "EmitTokenDiagnosticTypes"))
2645 OS << " return getDiagKindFromTokenClass(Kind);\n";
2646 else
2647 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2648 OS << " }\n\n";
2649
2650 // Check the user classes. We don't care what order since we're only
2651 // actually matching against one of them.
2652 OS << " switch (Kind) {\n"
2653 " default: break;\n";
2654 for (const auto &CI : Info.Classes) {
2655 if (!CI.isUserClass())
2656 continue;
2657
2658 OS << " case " << CI.Name << ": {\n";
2659 OS << " DiagnosticPredicate DP(Operand." << CI.PredicateMethod
2660 << "());\n";
2661 OS << " if (DP.isMatch())\n";
2662 OS << " return MCTargetAsmParser::Match_Success;\n";
2663 if (!CI.DiagnosticType.empty()) {
2664 OS << " if (DP.isNearMatch())\n";
2665 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2666 << CI.DiagnosticType << ";\n";
2667 OS << " break;\n";
2668 } else {
2669 OS << " break;\n";
2670 }
2671 OS << " }\n";
2672 }
2673 OS << " } // end switch (Kind)\n\n";
2674
2675 const CodeGenRegBank &RegBank = Target.getRegBank();
2676 ArrayRef<const Record *> RegClassesByHwMode = Target.getAllRegClassByHwMode();
2677 unsigned NumClassesByHwMode = RegClassesByHwMode.size();
2678
2679 if (!RegClassesByHwMode.empty()) {
2680 // Resolve RegClassByHwMode kinds to their concrete class regardless of
2681 // whether Operand is actually a register, so that the diagnostic
2682 // fallback paths below (for both register and non-register operands)
2683 // see a concrete class rather than an unresolved by-hwmode one.
2684 OS << " if (Kind > MCK_LAST_REGISTER &&"
2685 " Kind <= MCK_LAST_REGCLASS_BY_HWMODE) {\n";
2686
2687 const CodeGenHwModes &CGH = Target.getHwModes();
2688 unsigned NumModes = CGH.getNumModeIds();
2689
2690 OS << indent(4)
2691 << "static constexpr MatchClassKind RegClassByHwModeMatchTable["
2692 << NumModes << "][" << RegClassesByHwMode.size() << "] = {\n";
2693
2694 // TODO: If the instruction predicates can statically resolve which hwmode,
2695 // directly match the register class
2696 for (unsigned M = 0; M < NumModes; ++M) {
2697 OS << indent(6) << "{ // " << CGH.getModeName(Id: M, /*IncludeDefault=*/true)
2698 << '\n';
2699 for (unsigned I = 0; I != NumClassesByHwMode; ++I) {
2700 const Record *Class = RegClassesByHwMode[I];
2701 const HwModeSelect &ModeSelect = CGH.getHwModeSelect(R: Class);
2702
2703 auto FoundMode =
2704 find_if(Range: ModeSelect.Items, P: [=](const HwModeSelect::PairType P) {
2705 return P.first == M;
2706 });
2707
2708 if (FoundMode == ModeSelect.Items.end()) {
2709 OS << indent(8) << "InvalidMatchClass, // Missing mode entry for "
2710 << Class->getName() << "\n";
2711 } else {
2712 const CodeGenRegisterClass *RegClass =
2713 RegBank.getRegClass(FoundMode->second);
2714 const ClassInfo *CI =
2715 Info.RegisterClassClasses.at(k: RegClass->getDef());
2716 OS << indent(8) << CI->Name << ", // " << Class->getName() << "\n";
2717 }
2718 }
2719
2720 OS << indent(6) << "},\n";
2721 }
2722
2723 OS << indent(4) << "};\n\n";
2724
2725 OS << indent(4)
2726 << "static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == "
2727 << NumClassesByHwMode << ");\n";
2728
2729 OS << indent(4)
2730 << "const unsigned HwMode = "
2731 "STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);\n"
2732 << indent(4)
2733 << "Kind = RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER "
2734 "+ 1)];\n"
2735 " }\n\n";
2736 }
2737
2738 // Check for register operands, including sub-classes.
2739 const auto &Regs = RegBank.getRegisters();
2740 StringRef Namespace = Regs.front().TheDef->getValueAsString(FieldName: "Namespace");
2741 SmallVector<StringRef> Table(1 + Regs.size(), "InvalidMatchClass");
2742 for (const auto &RC : Info.RegisterClasses) {
2743 const auto &Reg = Target.getRegBank().getReg(RC.first);
2744 Table[Reg->EnumValue] = RC.second->Name;
2745 }
2746 OS << " if (Operand.isReg()) {\n";
2747 OS << " static constexpr uint16_t Table[" << Namespace
2748 << "::NUM_TARGET_REGS] = {\n";
2749 for (auto &MatchClassName : Table)
2750 OS << " " << MatchClassName << ",\n";
2751 OS << " };\n\n";
2752 OS << " MCRegister Reg = Operand.getReg();\n";
2753 OS << " MatchClassKind OpKind = Reg.isPhysical() ? "
2754 "(MatchClassKind)Table[Reg.id()] : InvalidMatchClass;\n";
2755 OS << " return isSubclass(OpKind, Kind) ? "
2756 << "(unsigned)MCTargetAsmParser::Match_Success :\n "
2757 << " getDiagKindFromRegisterClass(Kind);\n }\n\n";
2758
2759 // Expected operand is a register, but actual is not.
2760 OS << " if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)\n";
2761 OS << " return getDiagKindFromRegisterClass(Kind);\n\n";
2762
2763 // Generic fallthrough match failure case for operands that don't have
2764 // specialized diagnostic types.
2765 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2766 OS << "}\n\n";
2767}
2768
2769/// emitIsSubclass - Emit the subclass predicate function.
2770static void emitIsSubclass(CodeGenTarget &Target,
2771 std::forward_list<ClassInfo> &Infos,
2772 raw_ostream &OS) {
2773 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2774 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2775 OS << " if (A == B)\n";
2776 OS << " return true;\n\n";
2777
2778 // TODO: Use something like SequenceToOffsetTable to allow sequences to
2779 // overlap in this table.
2780 SmallVector<bool> SuperClassData;
2781
2782 OS << " [[maybe_unused]] static constexpr struct {\n";
2783 OS << " uint32_t Offset;\n";
2784 OS << " uint16_t Start;\n";
2785 OS << " uint16_t Length;\n";
2786 OS << " } Table[] = {\n";
2787 OS << " {0, 0, 0},\n"; // InvalidMatchClass
2788 OS << " {0, 0, 0},\n"; // OptionalMatchClass
2789 for (const auto &A : Infos) {
2790 SmallVector<bool> SuperClasses;
2791 SuperClasses.push_back(Elt: false); // InvalidMatchClass
2792 SuperClasses.push_back(Elt: A.IsOptional); // OptionalMatchClass
2793 for (const auto &B : Infos)
2794 SuperClasses.push_back(Elt: &A != &B && A.isSubsetOf(RHS: B));
2795
2796 // Trim leading and trailing zeros.
2797 auto End = find_if(Range: reverse(C&: SuperClasses), P: [](bool B) { return B; }).base();
2798 auto Start =
2799 std::find_if(first: SuperClasses.begin(), last: End, pred: [](bool B) { return B; });
2800
2801 unsigned Offset = SuperClassData.size();
2802 SuperClassData.append(in_start: Start, in_end: End);
2803
2804 OS << " {" << Offset << ", " << (Start - SuperClasses.begin()) << ", "
2805 << (End - Start) << "},\n";
2806 }
2807 OS << " };\n\n";
2808
2809 if (SuperClassData.empty()) {
2810 OS << " return false;\n";
2811 } else {
2812 // Dump the boolean data packed into bytes.
2813 SuperClassData.append(NumInputs: -SuperClassData.size() % 8, Elt: false);
2814 OS << " static constexpr uint8_t Data[] = {\n";
2815 for (unsigned I = 0, E = SuperClassData.size(); I < E; I += 8) {
2816 unsigned Byte = 0;
2817 for (unsigned J = 0; J < 8; ++J)
2818 Byte |= (unsigned)SuperClassData[I + J] << J;
2819 OS << formatv(Fmt: " {:X2},\n", Vals&: Byte);
2820 }
2821 OS << " };\n\n";
2822
2823 OS << " auto &Entry = Table[A];\n";
2824 OS << " unsigned Idx = B - Entry.Start;\n";
2825 OS << " if (Idx >= Entry.Length)\n";
2826 OS << " return false;\n";
2827 OS << " Idx += Entry.Offset;\n";
2828 OS << " return (Data[Idx / 8] >> (Idx % 8)) & 1;\n";
2829 }
2830 OS << "}\n\n";
2831}
2832
2833/// emitMatchTokenString - Emit the function to match a token string to the
2834/// appropriate match class value.
2835static void emitMatchTokenString(CodeGenTarget &Target,
2836 std::forward_list<ClassInfo> &Infos,
2837 raw_ostream &OS) {
2838 // Construct the match list.
2839 std::vector<StringMatcher::StringPair> Matches;
2840 for (const auto &CI : Infos) {
2841 if (CI.Kind == ClassInfo::Token)
2842 Matches.emplace_back(args: CI.ValueName, args: "return " + CI.Name + ";");
2843 }
2844
2845 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2846
2847 StringMatcher("Name", Matches, OS).Emit();
2848
2849 OS << " return InvalidMatchClass;\n";
2850 OS << "}\n\n";
2851}
2852
2853/// emitMatchRegisterName - Emit the function to match a string to the target
2854/// specific register enum.
2855static void emitMatchRegisterName(const CodeGenTarget &Target,
2856 const Record *AsmParser, raw_ostream &OS) {
2857 // Construct the match list.
2858 std::vector<StringMatcher::StringPair> Matches;
2859 const auto &Regs = Target.getRegBank().getRegisters();
2860 std::string Namespace =
2861 Regs.front().TheDef->getValueAsString(FieldName: "Namespace").str();
2862 for (const CodeGenRegister &Reg : Regs) {
2863 StringRef AsmName = Reg.TheDef->getValueAsString(FieldName: "AsmName");
2864 if (AsmName.empty())
2865 continue;
2866
2867 Matches.emplace_back(args: AsmName.str(), args: "return " + Namespace +
2868 "::" + Reg.getName().str() + ';');
2869 }
2870
2871 OS << "static MCRegister MatchRegisterName(StringRef Name) {\n";
2872
2873 bool IgnoreDuplicates =
2874 AsmParser->getValueAsBit(FieldName: "AllowDuplicateRegisterNames");
2875 StringMatcher("Name", Matches, OS).Emit(Indent: 0, IgnoreDuplicates);
2876
2877 OS << " return " << Namespace << "::NoRegister;\n";
2878 OS << "}\n\n";
2879}
2880
2881/// Emit the function to match a string to the target
2882/// specific register enum.
2883static void emitMatchRegisterAltName(const CodeGenTarget &Target,
2884 const Record *AsmParser, raw_ostream &OS) {
2885 // Construct the match list.
2886 std::vector<StringMatcher::StringPair> Matches;
2887 const auto &Regs = Target.getRegBank().getRegisters();
2888 std::string Namespace =
2889 Regs.front().TheDef->getValueAsString(FieldName: "Namespace").str();
2890 for (const CodeGenRegister &Reg : Regs) {
2891 for (StringRef AltName : Reg.TheDef->getValueAsListOfStrings(FieldName: "AltNames")) {
2892 AltName = AltName.trim();
2893
2894 // don't handle empty alternative names
2895 if (AltName.empty())
2896 continue;
2897
2898 Matches.emplace_back(args: AltName.str(), args: "return " + Namespace +
2899 "::" + Reg.getName().str() + ';');
2900 }
2901 }
2902
2903 OS << "static MCRegister MatchRegisterAltName(StringRef Name) {\n";
2904
2905 bool IgnoreDuplicates =
2906 AsmParser->getValueAsBit(FieldName: "AllowDuplicateRegisterNames");
2907 StringMatcher("Name", Matches, OS).Emit(Indent: 0, IgnoreDuplicates);
2908
2909 OS << " return " << Namespace << "::NoRegister;\n";
2910 OS << "}\n\n";
2911}
2912
2913/// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2914static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2915 // Get the set of diagnostic types from all of the operand classes.
2916 std::set<StringRef> Types;
2917 for (const auto &CI : Info.Classes) {
2918 if (!CI.DiagnosticType.empty())
2919 Types.insert(x: CI.DiagnosticType);
2920 }
2921
2922 if (Types.empty())
2923 return;
2924
2925 // Now emit the enum entries.
2926 for (StringRef Type : Types)
2927 OS << " Match_" << Type << ",\n";
2928 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2929}
2930
2931/// emitGetSubtargetFeatureName - Emit the helper function to get the
2932/// user-level name for a subtarget feature.
2933static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2934 OS << "// User-level names for subtarget features that participate in\n"
2935 << "// instruction matching.\n"
2936 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2937 if (!Info.SubtargetFeatures.empty()) {
2938 OS << " switch(Val) {\n";
2939 for (const SubtargetFeatureInfo &SFI :
2940 make_second_range(c&: Info.SubtargetFeatures)) {
2941 // FIXME: Totally just a placeholder name to get the algorithm working.
2942 OS << " case " << SFI.getEnumBitName() << ": return \""
2943 << SFI.TheDef->getValueAsString(FieldName: "PredicateName") << "\";\n";
2944 }
2945 OS << " default: return \"(unknown)\";\n";
2946 OS << " }\n";
2947 } else {
2948 // Nothing to emit, so skip the switch
2949 OS << " return \"(unknown)\";\n";
2950 }
2951 OS << "}\n\n";
2952}
2953
2954static std::string GetAliasRequiredFeatures(const Record *R,
2955 const AsmMatcherInfo &Info) {
2956 std::string Result;
2957
2958 ListSeparator LS(" && ");
2959 for (const Record *RF : R->getValueAsListOfDefs(FieldName: "Predicates")) {
2960 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(Def: RF);
2961 if (!F)
2962 PrintFatalError(ErrorLoc: R->getLoc(),
2963 Msg: "Predicate '" + RF->getName() +
2964 "' is not marked as an AssemblerPredicate!");
2965 Result += LS;
2966 Result += "Features.test(" + F->getEnumBitName() + ')';
2967 }
2968
2969 return Result;
2970}
2971
2972static void
2973emitMnemonicAliasVariant(raw_ostream &OS, const AsmMatcherInfo &Info,
2974 ArrayRef<const Record *> Aliases, unsigned Indent = 0,
2975 StringRef AsmParserVariantName = StringRef()) {
2976 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2977 // iteration order of the map is stable.
2978 std::map<std::string, std::vector<const Record *>> AliasesFromMnemonic;
2979
2980 for (const Record *R : Aliases) {
2981 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2982 StringRef AsmVariantName = R->getValueAsString(FieldName: "AsmVariantName");
2983 if (AsmVariantName != AsmParserVariantName)
2984 continue;
2985 AliasesFromMnemonic[R->getValueAsString(FieldName: "FromMnemonic").lower()].push_back(
2986 x: R);
2987 }
2988 if (AliasesFromMnemonic.empty())
2989 return;
2990
2991 // Process each alias a "from" mnemonic at a time, building the code executed
2992 // by the string remapper.
2993 std::vector<StringMatcher::StringPair> Cases;
2994 for (const auto &AliasEntry : AliasesFromMnemonic) {
2995 // Loop through each alias and emit code that handles each case. If there
2996 // are two instructions without predicates, emit an error. If there is one,
2997 // emit it last.
2998 std::string MatchCode;
2999 int AliasWithNoPredicate = -1;
3000
3001 ArrayRef<const Record *> ToVec = AliasEntry.second;
3002 for (const auto &[Idx, R] : enumerate(First&: ToVec)) {
3003 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
3004
3005 // If this unconditionally matches, remember it for later and diagnose
3006 // duplicates.
3007 if (FeatureMask.empty()) {
3008 if (AliasWithNoPredicate != -1 &&
3009 R->getValueAsString(FieldName: "ToMnemonic") !=
3010 ToVec[AliasWithNoPredicate]->getValueAsString(FieldName: "ToMnemonic")) {
3011 // We can't have two different aliases from the same mnemonic with no
3012 // predicate.
3013 PrintError(
3014 ErrorLoc: ToVec[AliasWithNoPredicate]->getLoc(),
3015 Msg: "two different MnemonicAliases with the same 'from' mnemonic!");
3016 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "this is the other MnemonicAlias.");
3017 }
3018
3019 AliasWithNoPredicate = Idx;
3020 continue;
3021 }
3022 if (R->getValueAsString(FieldName: "ToMnemonic") == AliasEntry.first)
3023 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "MnemonicAlias to the same string");
3024
3025 if (!MatchCode.empty())
3026 MatchCode += "else ";
3027 MatchCode += "if (" + FeatureMask + ")\n";
3028 MatchCode += " Mnemonic = \"";
3029 MatchCode += R->getValueAsString(FieldName: "ToMnemonic").lower();
3030 MatchCode += "\";\n";
3031 }
3032
3033 if (AliasWithNoPredicate != -1) {
3034 const Record *R = ToVec[AliasWithNoPredicate];
3035 if (!MatchCode.empty())
3036 MatchCode += "else\n ";
3037 MatchCode += "Mnemonic = \"";
3038 MatchCode += R->getValueAsString(FieldName: "ToMnemonic").lower();
3039 MatchCode += "\";\n";
3040 }
3041
3042 MatchCode += "return;";
3043
3044 Cases.emplace_back(args: AliasEntry.first, args&: MatchCode);
3045 }
3046 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
3047}
3048
3049/// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
3050/// emit a function for them and return true, otherwise return false.
3051static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
3052 CodeGenTarget &Target) {
3053 // Ignore aliases when match-prefix is set.
3054 if (!MatchPrefix.empty())
3055 return false;
3056
3057 ArrayRef<const Record *> Aliases =
3058 Info.getRecords().getAllDerivedDefinitions(ClassName: "MnemonicAlias");
3059 if (Aliases.empty())
3060 return false;
3061
3062 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
3063 "const FeatureBitset &Features, unsigned VariantID) {\n";
3064 unsigned VariantCount = Target.getAsmParserVariantCount();
3065 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3066 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3067 int AsmParserVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3068 StringRef AsmParserVariantName = AsmVariant->getValueAsString(FieldName: "Name");
3069
3070 // If the variant doesn't have a name, defer to the emitMnemonicAliasVariant
3071 // call after the loop.
3072 if (AsmParserVariantName.empty()) {
3073 assert(VariantCount == 1 && "Multiple variants should each be named");
3074 continue;
3075 }
3076
3077 if (VC == 0)
3078 OS << " switch (VariantID) {\n";
3079 OS << " case " << AsmParserVariantNo << ":\n";
3080 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
3081 AsmParserVariantName);
3082 OS << " break;\n";
3083
3084 if (VC == VariantCount - 1)
3085 OS << " }\n";
3086 }
3087
3088 // Emit aliases that apply to all variants.
3089 emitMnemonicAliasVariant(OS, Info, Aliases);
3090
3091 OS << "}\n\n";
3092
3093 return true;
3094}
3095
3096static void
3097emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
3098 const AsmMatcherInfo &Info, StringRef ClassName,
3099 const StringToOffsetTable &StringTable,
3100 unsigned MaxMnemonicIndex, unsigned MaxFeaturesIndex,
3101 bool HasMnemonicFirst, const Record &AsmParser) {
3102 unsigned MaxMask = 0;
3103 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
3104 MaxMask |= OMI.OperandMask;
3105 }
3106
3107 // Emit the static custom operand parsing table;
3108 OS << "namespace {\n";
3109 OS << " struct OperandMatchEntry {\n";
3110 OS << " " << getMinimalTypeForRange(Range: MaxMnemonicIndex) << " Mnemonic;\n";
3111 OS << " " << getMinimalTypeForRange(Range: MaxMask) << " OperandMask;\n";
3112 OS << " "
3113 << getMinimalTypeForRange(
3114 Range: std::distance(first: Info.Classes.begin(), last: Info.Classes.end()) +
3115 2 /* Include 'InvalidMatchClass' and 'OptionalMatchClass' */)
3116 << " Class;\n";
3117 OS << " " << getMinimalTypeForRange(Range: MaxFeaturesIndex)
3118 << " RequiredFeaturesIdx;\n\n";
3119 OS << " StringRef getMnemonic() const {\n";
3120 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
3121 OS << " MnemonicTable[Mnemonic]);\n";
3122 OS << " }\n";
3123 OS << " };\n\n";
3124
3125 OS << " // Predicate for searching for an opcode.\n";
3126 OS << " struct LessOpcodeOperand {\n";
3127 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
3128 OS << " return LHS.getMnemonic() < RHS;\n";
3129 OS << " }\n";
3130 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
3131 OS << " return LHS < RHS.getMnemonic();\n";
3132 OS << " }\n";
3133 OS << " bool operator()(const OperandMatchEntry &LHS,";
3134 OS << " const OperandMatchEntry &RHS) {\n";
3135 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
3136 OS << " }\n";
3137 OS << " };\n";
3138
3139 OS << "} // end anonymous namespace\n\n";
3140
3141 OS << "static const OperandMatchEntry OperandMatchTable["
3142 << Info.OperandMatchInfo.size() << "] = {\n";
3143
3144 OS << " /* Operand List Mnemonic, Mask, Operand Class, Features */\n";
3145 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
3146 const MatchableInfo &II = *OMI.MI;
3147
3148 OS << " { ";
3149
3150 // Store a pascal-style length byte in the mnemonic.
3151 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.lower();
3152 OS << *StringTable.GetStringOffset(Str: LenMnemonic) << " /* " << II.Mnemonic
3153 << " */, ";
3154
3155 OS << OMI.OperandMask;
3156 OS << " /* ";
3157 ListSeparator LS;
3158 for (int i = 0, e = 31; i != e; ++i)
3159 if (OMI.OperandMask & (1 << i))
3160 OS << LS << i;
3161 OS << " */, ";
3162
3163 OS << OMI.CI->Name;
3164
3165 // Write the required features mask.
3166 OS << ", AMFBS";
3167 if (II.RequiredFeatures.empty())
3168 OS << "_None";
3169 else
3170 for (const auto &F : II.RequiredFeatures)
3171 OS << '_' << F->TheDef->getName();
3172
3173 OS << " },\n";
3174 }
3175 OS << "};\n\n";
3176
3177 // Emit the operand class switch to call the correct custom parser for
3178 // the found operand class.
3179 OS << "ParseStatus " << Target.getName() << ClassName << "::\n"
3180 << "tryCustomParseOperand(OperandVector"
3181 << " &Operands,\n unsigned MCK) {\n\n"
3182 << " switch(MCK) {\n";
3183
3184 for (const auto &CI : Info.Classes) {
3185 if (CI.ParserMethod.empty())
3186 continue;
3187 OS << " case " << CI.Name << ":\n"
3188 << " return " << CI.ParserMethod << "(Operands);\n";
3189 }
3190
3191 OS << " default:\n";
3192 OS << " return ParseStatus::NoMatch;\n";
3193 OS << " }\n";
3194 OS << " return ParseStatus::NoMatch;\n";
3195 OS << "}\n\n";
3196
3197 // Emit the static custom operand parser. This code is very similar with
3198 // the other matcher. Also use MatchResultTy here just in case we go for
3199 // a better error handling.
3200 OS << "ParseStatus " << Target.getName() << ClassName << "::\n"
3201 << "MatchOperandParserImpl(OperandVector"
3202 << " &Operands,\n StringRef Mnemonic,\n"
3203 << " bool ParseForAllFeatures) {\n";
3204
3205 // Emit code to get the available features.
3206 OS << " // Get the current feature set.\n";
3207 OS << " const FeatureBitset &AvailableFeatures = "
3208 "getAvailableFeatures();\n\n";
3209
3210 OS << " // Get the next operand index.\n";
3211 OS << " unsigned NextOpNum = Operands.size()"
3212 << (HasMnemonicFirst ? " - 1" : "") << ";\n";
3213
3214 // Emit code to search the table.
3215 OS << " // Search the table.\n";
3216 if (HasMnemonicFirst) {
3217 OS << " auto MnemonicRange =\n";
3218 OS << " std::equal_range(std::begin(OperandMatchTable), "
3219 "std::end(OperandMatchTable),\n";
3220 OS << " Mnemonic, LessOpcodeOperand());\n\n";
3221 } else {
3222 OS << " auto MnemonicRange = std::pair(std::begin(OperandMatchTable),"
3223 " std::end(OperandMatchTable));\n";
3224 OS << " if (!Mnemonic.empty())\n";
3225 OS << " MnemonicRange =\n";
3226 OS << " std::equal_range(std::begin(OperandMatchTable), "
3227 "std::end(OperandMatchTable),\n";
3228 OS << " Mnemonic, LessOpcodeOperand());\n\n";
3229 }
3230
3231 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3232 OS << " return ParseStatus::NoMatch;\n\n";
3233
3234 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
3235 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
3236
3237 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3238 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
3239
3240 // Emit check that the required features are available.
3241 OS << " // check if the available features match\n";
3242 OS << " const FeatureBitset &RequiredFeatures = "
3243 "FeatureBitsets[it->RequiredFeaturesIdx];\n";
3244 OS << " if (!ParseForAllFeatures && (AvailableFeatures & "
3245 "RequiredFeatures) != RequiredFeatures)\n";
3246 OS << " continue;\n\n";
3247
3248 // Emit check to ensure the operand number matches.
3249 OS << " // check if the operand in question has a custom parser.\n";
3250 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
3251 OS << " continue;\n\n";
3252
3253 // Emit call to the custom parser method
3254 StringRef ParserName = AsmParser.getValueAsString(FieldName: "OperandParserMethod");
3255 if (ParserName.empty())
3256 ParserName = "tryCustomParseOperand";
3257 OS << " // call custom parse method to handle the operand\n";
3258 OS << " ParseStatus Result = " << ParserName << "(Operands, it->Class);\n";
3259 OS << " if (!Result.isNoMatch())\n";
3260 OS << " return Result;\n";
3261 OS << " }\n\n";
3262
3263 OS << " // Okay, we had no match.\n";
3264 OS << " return ParseStatus::NoMatch;\n";
3265 OS << "}\n\n";
3266}
3267
3268static void emitAsmTiedOperandConstraints(CodeGenTarget &Target,
3269 AsmMatcherInfo &Info, raw_ostream &OS,
3270 bool HasOptionalOperands) {
3271 std::string AsmParserName =
3272 Info.AsmParser->getValueAsString(FieldName: "AsmParserClassName").str();
3273 OS << "static bool ";
3274 OS << "checkAsmTiedOperandConstraints(const " << Target.getName()
3275 << AsmParserName << "&AsmParser,\n";
3276 OS << " unsigned Kind, const OperandVector "
3277 "&Operands,\n";
3278 if (HasOptionalOperands)
3279 OS << " ArrayRef<unsigned> DefaultsOffset,\n";
3280 OS << " uint64_t &ErrorInfo) {\n";
3281 OS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
3282 OS << " const uint8_t *Converter = ConversionTable[Kind];\n";
3283 OS << " for (const uint8_t *p = Converter; *p; p += 2) {\n";
3284 OS << " switch (*p) {\n";
3285 OS << " case CVT_Tied: {\n";
3286 OS << " unsigned OpIdx = *(p + 1);\n";
3287 OS << " assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";
3288 OS << " std::begin(TiedAsmOperandTable)) &&\n";
3289 OS << " \"Tied operand not found\");\n";
3290 OS << " unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];\n";
3291 OS << " unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];\n";
3292 if (HasOptionalOperands) {
3293 // When optional operands are involved, formal and actual operand indices
3294 // may differ. Map the former to the latter by subtracting the number of
3295 // absent optional operands.
3296 OS << " OpndNum1 = OpndNum1 - DefaultsOffset[OpndNum1];\n";
3297 OS << " OpndNum2 = OpndNum2 - DefaultsOffset[OpndNum2];\n";
3298 }
3299 OS << " if (OpndNum1 != OpndNum2) {\n";
3300 OS << " auto &SrcOp1 = Operands[OpndNum1];\n";
3301 OS << " auto &SrcOp2 = Operands[OpndNum2];\n";
3302 OS << " if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {\n";
3303 OS << " ErrorInfo = OpndNum2;\n";
3304 OS << " return false;\n";
3305 OS << " }\n";
3306 OS << " }\n";
3307 OS << " break;\n";
3308 OS << " }\n";
3309 OS << " default:\n";
3310 OS << " break;\n";
3311 OS << " }\n";
3312 OS << " }\n";
3313 OS << " return true;\n";
3314 OS << "}\n\n";
3315}
3316
3317static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target,
3318 unsigned VariantCount) {
3319 OS << "static std::string " << Target.getName()
3320 << "MnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,"
3321 << " unsigned VariantID) {\n";
3322 if (!VariantCount)
3323 OS << " return \"\";";
3324 else {
3325 OS << " const unsigned MaxEditDist = 2;\n";
3326 OS << " std::vector<StringRef> Candidates;\n";
3327 OS << " StringRef Prev = \"\";\n\n";
3328
3329 OS << " // Find the appropriate table for this asm variant.\n";
3330 OS << " const MatchEntry *Start, *End;\n";
3331 OS << " switch (VariantID) {\n";
3332 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3333 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3334 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3335 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3336 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3337 << "); End = std::end(MatchTable" << VC << "); break;\n";
3338 }
3339 OS << " }\n\n";
3340 OS << " for (auto I = Start; I < End; I++) {\n";
3341 OS << " // Ignore unsupported instructions.\n";
3342 OS << " const FeatureBitset &RequiredFeatures = "
3343 "FeatureBitsets[I->RequiredFeaturesIdx];\n";
3344 OS << " if ((FBS & RequiredFeatures) != RequiredFeatures)\n";
3345 OS << " continue;\n";
3346 OS << "\n";
3347 OS << " StringRef T = I->getMnemonic();\n";
3348 OS << " // Avoid recomputing the edit distance for the same string.\n";
3349 OS << " if (T == Prev)\n";
3350 OS << " continue;\n";
3351 OS << "\n";
3352 OS << " Prev = T;\n";
3353 OS << " unsigned Dist = S.edit_distance(T, false, MaxEditDist);\n";
3354 OS << " if (Dist <= MaxEditDist)\n";
3355 OS << " Candidates.push_back(T);\n";
3356 OS << " }\n";
3357 OS << "\n";
3358 OS << " if (Candidates.empty())\n";
3359 OS << " return \"\";\n";
3360 OS << "\n";
3361 OS << " std::string Res = \", did you mean: \";\n";
3362 OS << " unsigned i = 0;\n";
3363 OS << " for (; i < Candidates.size() - 1; i++)\n";
3364 OS << " Res += Candidates[i].str() + \", \";\n";
3365 OS << " return Res + Candidates[i].str() + \"?\";\n";
3366 }
3367 OS << "}\n";
3368 OS << "\n";
3369}
3370
3371static void emitMnemonicChecker(raw_ostream &OS, CodeGenTarget &Target,
3372 unsigned VariantCount, bool HasMnemonicFirst,
3373 bool HasMnemonicAliases) {
3374 OS << "static bool " << Target.getName()
3375 << "CheckMnemonic(StringRef Mnemonic,\n";
3376 OS << " "
3377 << "const FeatureBitset &AvailableFeatures,\n";
3378 OS << " "
3379 << "unsigned VariantID) {\n";
3380
3381 if (!VariantCount) {
3382 OS << " return false;\n";
3383 } else {
3384 if (HasMnemonicAliases) {
3385 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3386 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);";
3387 OS << "\n\n";
3388 }
3389 OS << " // Find the appropriate table for this asm variant.\n";
3390 OS << " const MatchEntry *Start, *End;\n";
3391 OS << " switch (VariantID) {\n";
3392 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3393 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3394 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3395 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3396 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3397 << "); End = std::end(MatchTable" << VC << "); break;\n";
3398 }
3399 OS << " }\n\n";
3400
3401 OS << " // Search the table.\n";
3402 if (HasMnemonicFirst) {
3403 OS << " auto MnemonicRange = "
3404 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3405 } else {
3406 OS << " auto MnemonicRange = std::pair(Start, End);\n";
3407 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3408 OS << " if (!Mnemonic.empty())\n";
3409 OS << " MnemonicRange = "
3410 << "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3411 }
3412
3413 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3414 OS << " return false;\n\n";
3415
3416 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3417 << "*ie = MnemonicRange.second;\n";
3418 OS << " it != ie; ++it) {\n";
3419 OS << " const FeatureBitset &RequiredFeatures =\n";
3420 OS << " FeatureBitsets[it->RequiredFeaturesIdx];\n";
3421 OS << " if ((AvailableFeatures & RequiredFeatures) == ";
3422 OS << "RequiredFeatures)\n";
3423 OS << " return true;\n";
3424 OS << " }\n";
3425 OS << " return false;\n";
3426 }
3427 OS << "}\n";
3428 OS << "\n";
3429}
3430
3431// Emit a function mapping match classes to strings, for debugging.
3432static void emitMatchClassKindNames(std::forward_list<ClassInfo> &Infos,
3433 raw_ostream &OS) {
3434 OS << "#ifndef NDEBUG\n";
3435 OS << "const char *getMatchClassName(MatchClassKind Kind) {\n";
3436 OS << " switch (Kind) {\n";
3437
3438 OS << " case InvalidMatchClass: return \"InvalidMatchClass\";\n";
3439 OS << " case OptionalMatchClass: return \"OptionalMatchClass\";\n";
3440 for (const auto &CI : Infos) {
3441 OS << " case " << CI.Name << ": return \"" << CI.Name << "\";\n";
3442 }
3443 OS << " case NumMatchClassKinds: return \"NumMatchClassKinds\";\n";
3444
3445 OS << " }\n";
3446 OS << " llvm_unreachable(\"unhandled MatchClassKind!\");\n";
3447 OS << "}\n\n";
3448 OS << "#endif // NDEBUG\n";
3449}
3450
3451static std::string
3452getNameForFeatureBitset(ArrayRef<const Record *> FeatureBitset) {
3453 std::string Name = "AMFBS";
3454 for (const Record *Feature : FeatureBitset)
3455 Name += ("_" + Feature->getName()).str();
3456 return Name;
3457}
3458
3459void AsmMatcherEmitter::run(raw_ostream &OS) {
3460 CodeGenTarget Target(Records);
3461 const Record *AsmParser = Target.getAsmParser();
3462 StringRef ClassName = AsmParser->getValueAsString(FieldName: "AsmParserClassName");
3463
3464 emitSourceFileHeader(Desc: "Assembly Matcher Source Fragment", OS, Record: Records);
3465
3466 // Compute the information on the instructions to match.
3467 AsmMatcherInfo Info(AsmParser, Target, Records);
3468 Info.buildInfo();
3469
3470 bool PreferSmallerInstructions = getPreferSmallerInstructions(Target);
3471 // Sort the instruction table using the partial order on classes. We use
3472 // stable_sort to ensure that ambiguous instructions are still
3473 // deterministically ordered.
3474 llvm::stable_sort(
3475 Range&: Info.Matchables,
3476 C: [PreferSmallerInstructions](const std::unique_ptr<MatchableInfo> &A,
3477 const std::unique_ptr<MatchableInfo> &B) {
3478 return A->shouldBeMatchedBefore(RHS: *B, PreferSmallerInstructions);
3479 });
3480
3481#ifdef EXPENSIVE_CHECKS
3482 // Verify that the table is sorted and operator < works transitively.
3483 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
3484 ++I) {
3485 for (auto J = I; J != E; ++J) {
3486 assert(!(*J)->shouldBeMatchedBefore(**I, PreferSmallerInstructions));
3487 }
3488 }
3489#endif
3490
3491 DEBUG_WITH_TYPE("instruction_info", {
3492 for (const auto &MI : Info.Matchables)
3493 MI->dump();
3494 });
3495
3496 // Check for ambiguous matchables.
3497 DEBUG_WITH_TYPE("ambiguous_instrs", {
3498 unsigned NumAmbiguous = 0;
3499 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
3500 ++I) {
3501 for (auto J = std::next(I); J != E; ++J) {
3502 const MatchableInfo &A = **I;
3503 const MatchableInfo &B = **J;
3504
3505 if (A.couldMatchAmbiguouslyWith(B, PreferSmallerInstructions)) {
3506 errs() << "warning: ambiguous matchables:\n";
3507 A.dump();
3508 errs() << "\nis incomparable with:\n";
3509 B.dump();
3510 errs() << "\n\n";
3511 ++NumAmbiguous;
3512 }
3513 }
3514 }
3515 if (NumAmbiguous)
3516 errs() << "warning: " << NumAmbiguous << " ambiguous matchables!\n";
3517 });
3518
3519 // Compute the information on the custom operand parsing.
3520 Info.buildOperandMatchInfo();
3521
3522 bool HasMnemonicFirst = AsmParser->getValueAsBit(FieldName: "HasMnemonicFirst");
3523 bool HasOptionalOperands = Info.hasOptionalOperands();
3524 bool ReportMultipleNearMisses =
3525 AsmParser->getValueAsBit(FieldName: "ReportMultipleNearMisses");
3526
3527 // Write the output.
3528
3529 // Information for the class declaration.
3530 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
3531 OS << "#undef GET_ASSEMBLER_HEADER\n";
3532 OS << " // This should be included into the middle of the declaration of\n";
3533 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
3534 OS << " FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) "
3535 "const;\n";
3536 if (HasOptionalOperands) {
3537 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
3538 << "unsigned Opcode,\n"
3539 << " const OperandVector &Operands,\n"
3540 << " const SmallBitVector "
3541 "&OptionalOperandsMask,\n"
3542 << " ArrayRef<unsigned> DefaultsOffset);\n";
3543 } else {
3544 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
3545 << "unsigned Opcode,\n"
3546 << " const OperandVector &Operands);\n";
3547 }
3548 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
3549 OS << " const OperandVector &Operands) override;\n";
3550 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
3551 << " MCInst &Inst,\n";
3552 if (ReportMultipleNearMisses)
3553 OS << " SmallVectorImpl<NearMissInfo> "
3554 "*NearMisses,\n";
3555 else
3556 OS << " uint64_t &ErrorInfo,\n"
3557 << " FeatureBitset &MissingFeatures,\n";
3558 OS << " bool matchingInlineAsm,\n"
3559 << " unsigned VariantID = 0);\n";
3560 if (!ReportMultipleNearMisses)
3561 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
3562 << " MCInst &Inst,\n"
3563 << " uint64_t &ErrorInfo,\n"
3564 << " bool matchingInlineAsm,\n"
3565 << " unsigned VariantID = 0) {\n"
3566 << " FeatureBitset MissingFeatures;\n"
3567 << " return MatchInstructionImpl(Operands, Inst, ErrorInfo, "
3568 "MissingFeatures,\n"
3569 << " matchingInlineAsm, VariantID);\n"
3570 << " }\n\n";
3571
3572 if (!Info.OperandMatchInfo.empty()) {
3573 OS << " ParseStatus MatchOperandParserImpl(\n";
3574 OS << " OperandVector &Operands,\n";
3575 OS << " StringRef Mnemonic,\n";
3576 OS << " bool ParseForAllFeatures = false);\n";
3577
3578 OS << " ParseStatus tryCustomParseOperand(\n";
3579 OS << " OperandVector &Operands,\n";
3580 OS << " unsigned MCK);\n\n";
3581 }
3582
3583 OS << "#endif // GET_ASSEMBLER_HEADER\n\n";
3584
3585 // Emit the operand match diagnostic enum names.
3586 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
3587 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3588 emitOperandDiagnosticTypes(Info, OS);
3589 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3590
3591 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
3592 OS << "#undef GET_REGISTER_MATCHER\n\n";
3593
3594 // Emit the subtarget feature enumeration.
3595 SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(
3596 SubtargetFeatures: Info.SubtargetFeatures, OS);
3597
3598 // Emit the function to match a register name to number.
3599 // This should be omitted for Mips target
3600 if (AsmParser->getValueAsBit(FieldName: "ShouldEmitMatchRegisterName"))
3601 emitMatchRegisterName(Target, AsmParser, OS);
3602
3603 if (AsmParser->getValueAsBit(FieldName: "ShouldEmitMatchRegisterAltName"))
3604 emitMatchRegisterAltName(Target, AsmParser, OS);
3605
3606 OS << "#endif // GET_REGISTER_MATCHER\n\n";
3607
3608 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
3609 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
3610
3611 // Generate the helper function to get the names for subtarget features.
3612 emitGetSubtargetFeatureName(Info, OS);
3613
3614 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
3615
3616 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
3617 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
3618
3619 // Generate the function that remaps for mnemonic aliases.
3620 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
3621
3622 // Generate the convertToMCInst function to convert operands into an MCInst.
3623 // Also, generate the convertToMapAndConstraints function for MS-style inline
3624 // assembly. The latter doesn't actually generate a MCInst.
3625 unsigned NumConverters =
3626 emitConvertFuncs(Target, ClassName, Infos&: Info.Matchables, HasMnemonicFirst,
3627 HasOptionalOperands, OS);
3628
3629 // Emit the enumeration for classes which participate in matching.
3630 emitMatchClassEnumeration(Target, Infos&: Info.Classes, OS);
3631
3632 // Emit a function to get the user-visible string to describe an operand
3633 // match failure in diagnostics.
3634 emitOperandMatchErrorDiagStrings(Info, OS);
3635
3636 // Emit a function to map register classes to operand match failure codes.
3637 emitRegisterMatchErrorFunc(Info, OS);
3638
3639 // Emit a function to map MatchClassKind to MCRegisterClass.
3640 emitGetRegClassFromMatchKindFunc(Info, OS);
3641
3642 // Emit the routine to match token strings to their match class.
3643 emitMatchTokenString(Target, Infos&: Info.Classes, OS);
3644
3645 // Emit the subclass predicate routine.
3646 emitIsSubclass(Target, Infos&: Info.Classes, OS);
3647
3648 // Emit the function mapping token class kinds to diagnostic codes.
3649 if (AsmParser->getValueAsBit(FieldName: "EmitTokenDiagnosticTypes"))
3650 emitTokenDiagFunction(Info, OS);
3651
3652 // Emit the routine to validate an operand against a match class.
3653 emitValidateOperandClass(Target, Info, OS);
3654
3655 emitMatchClassKindNames(Infos&: Info.Classes, OS);
3656
3657 // Emit the available features compute function.
3658 SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
3659 TargetName: Info.Target.getName(), ClassName, FuncName: "ComputeAvailableFeatures",
3660 SubtargetFeatures&: Info.SubtargetFeatures, OS);
3661
3662 if (!ReportMultipleNearMisses)
3663 emitAsmTiedOperandConstraints(Target, Info, OS, HasOptionalOperands);
3664
3665 StringToOffsetTable StringTable(/*AppendZero=*/false);
3666
3667 size_t MaxNumOperands = 0;
3668 unsigned MaxMnemonicIndex = 0;
3669 bool HasDeprecation = false;
3670 for (const auto &MI : Info.Matchables) {
3671 MaxNumOperands = std::max(a: MaxNumOperands, b: MI->AsmOperands.size());
3672 HasDeprecation |= MI->HasDeprecation;
3673
3674 // Store a pascal-style length byte in the mnemonic.
3675 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
3676 MaxMnemonicIndex = std::max(a: MaxMnemonicIndex,
3677 b: StringTable.GetOrAddStringOffset(Str: LenMnemonic));
3678 }
3679
3680 OS << "static const char MnemonicTable[] =\n";
3681 StringTable.EmitString(O&: OS);
3682 OS << ";\n\n";
3683
3684 std::vector<std::vector<const Record *>> FeatureBitsets;
3685 for (const auto &MI : Info.Matchables) {
3686 if (MI->RequiredFeatures.empty())
3687 continue;
3688 FeatureBitsets.emplace_back();
3689 for (const auto *F : MI->RequiredFeatures)
3690 FeatureBitsets.back().push_back(x: F->TheDef);
3691 }
3692
3693 llvm::sort(C&: FeatureBitsets,
3694 Comp: [&](ArrayRef<const Record *> A, ArrayRef<const Record *> B) {
3695 if (A.size() != B.size())
3696 return A.size() < B.size();
3697 for (const auto [ARec, BRec] : zip_equal(t&: A, u&: B)) {
3698 if (ARec->getName() != BRec->getName())
3699 return ARec->getName() < BRec->getName();
3700 }
3701 return false;
3702 });
3703 FeatureBitsets.erase(first: llvm::unique(R&: FeatureBitsets), last: FeatureBitsets.end());
3704 OS << "// Feature bitsets.\n"
3705 << "enum : " << getMinimalTypeForRange(Range: FeatureBitsets.size()) << " {\n"
3706 << " AMFBS_None,\n";
3707 for (const auto &FeatureBitset : FeatureBitsets) {
3708 if (FeatureBitset.empty())
3709 continue;
3710 OS << " " << getNameForFeatureBitset(FeatureBitset) << ",\n";
3711 }
3712 OS << "};\n\n"
3713 << "static constexpr FeatureBitset FeatureBitsets[] = {\n"
3714 << " {}, // AMFBS_None\n";
3715 for (const auto &FeatureBitset : FeatureBitsets) {
3716 if (FeatureBitset.empty())
3717 continue;
3718 OS << " {";
3719 for (const auto &Feature : FeatureBitset) {
3720 const auto &I = Info.SubtargetFeatures.find(x: Feature);
3721 assert(I != Info.SubtargetFeatures.end() && "Didn't import predicate?");
3722 OS << I->second.getEnumBitName() << ", ";
3723 }
3724 OS << "}, // " << getNameForFeatureBitset(FeatureBitset) << "\n";
3725 }
3726 OS << "};\n\n";
3727
3728 // Emit the static match table; unused classes get initialized to 0 which is
3729 // guaranteed to be InvalidMatchClass.
3730 //
3731 // FIXME: We can reduce the size of this table very easily. First, we change
3732 // it so that store the kinds in separate bit-fields for each index, which
3733 // only needs to be the max width used for classes at that index (we also need
3734 // to reject based on this during classification). If we then make sure to
3735 // order the match kinds appropriately (putting mnemonics last), then we
3736 // should only end up using a few bits for each class, especially the ones
3737 // following the mnemonic.
3738 OS << "namespace {\n";
3739 OS << " struct MatchEntry {\n";
3740 OS << " " << getMinimalTypeForRange(Range: MaxMnemonicIndex) << " Mnemonic;\n";
3741 OS << " uint32_t Opcode;\n";
3742 OS << " " << getMinimalTypeForRange(Range: NumConverters) << " ConvertFn;\n";
3743 OS << " " << getMinimalTypeForRange(Range: FeatureBitsets.size())
3744 << " RequiredFeaturesIdx;\n";
3745 OS << " "
3746 << getMinimalTypeForRange(
3747 Range: std::distance(first: Info.Classes.begin(), last: Info.Classes.end()) +
3748 2 /* Include 'InvalidMatchClass' and 'OptionalMatchClass' */)
3749 << " Classes[" << MaxNumOperands << "];\n";
3750 OS << " StringRef getMnemonic() const {\n";
3751 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
3752 OS << " MnemonicTable[Mnemonic]);\n";
3753 OS << " }\n";
3754 OS << " };\n\n";
3755
3756 OS << " // Predicate for searching for an opcode.\n";
3757 OS << " struct LessOpcode {\n";
3758 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
3759 OS << " return LHS.getMnemonic() < RHS;\n";
3760 OS << " }\n";
3761 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
3762 OS << " return LHS < RHS.getMnemonic();\n";
3763 OS << " }\n";
3764 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
3765 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
3766 OS << " }\n";
3767 OS << " };\n";
3768
3769 OS << "} // end anonymous namespace\n\n";
3770
3771 unsigned VariantCount = Target.getAsmParserVariantCount();
3772 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3773 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3774 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3775
3776 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
3777
3778 for (const auto &MI : Info.Matchables) {
3779 if (MI->AsmVariantID != AsmVariantNo)
3780 continue;
3781
3782 // Store a pascal-style length byte in the mnemonic.
3783 std::string LenMnemonic =
3784 char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
3785 OS << " { " << *StringTable.GetStringOffset(Str: LenMnemonic) << " /* "
3786 << MI->Mnemonic << " */, " << Target.getInstNamespace()
3787 << "::" << MI->getResultInst()->getName() << ", "
3788 << MI->ConversionFnKind << ", ";
3789
3790 // Write the required features mask.
3791 OS << "AMFBS";
3792 if (MI->RequiredFeatures.empty())
3793 OS << "_None";
3794 else
3795 for (const auto &F : MI->RequiredFeatures)
3796 OS << '_' << F->TheDef->getName();
3797
3798 OS << ", { ";
3799 ListSeparator LS;
3800 for (const MatchableInfo::AsmOperand &Op : MI->AsmOperands)
3801 OS << LS << Op.Class->Name;
3802 OS << " }, },\n";
3803 }
3804
3805 OS << "};\n\n";
3806 }
3807
3808 OS << "#include \"llvm/Support/Debug.h\"\n";
3809 OS << "#include \"llvm/Support/Format.h\"\n\n";
3810
3811 // Finally, build the match function.
3812 OS << "unsigned " << Target.getName() << ClassName << "::\n"
3813 << "MatchInstructionImpl(const OperandVector &Operands,\n";
3814 OS << " MCInst &Inst,\n";
3815 if (ReportMultipleNearMisses)
3816 OS << " SmallVectorImpl<NearMissInfo> *NearMisses,\n";
3817 else
3818 OS << " uint64_t &ErrorInfo,\n"
3819 << " FeatureBitset &MissingFeatures,\n";
3820 OS << " bool matchingInlineAsm, unsigned VariantID) {\n";
3821
3822 if (!ReportMultipleNearMisses) {
3823 OS << " // Eliminate obvious mismatches.\n";
3824 OS << " if (Operands.size() > " << (MaxNumOperands + HasMnemonicFirst)
3825 << ") {\n";
3826 OS << " ErrorInfo = " << (MaxNumOperands + HasMnemonicFirst) << ";\n";
3827 OS << " return Match_InvalidOperand;\n";
3828 OS << " }\n\n";
3829 }
3830
3831 // Emit code to get the available features.
3832 OS << " // Get the current feature set.\n";
3833 OS << " const FeatureBitset &AvailableFeatures = "
3834 "getAvailableFeatures();\n\n";
3835
3836 OS << " // Get the instruction mnemonic, which is the first token.\n";
3837 if (HasMnemonicFirst) {
3838 OS << " StringRef Mnemonic = ((" << Target.getName()
3839 << "Operand &)*Operands[0]).getToken();\n\n";
3840 } else {
3841 OS << " StringRef Mnemonic;\n";
3842 OS << " if (Operands[0]->isToken())\n";
3843 OS << " Mnemonic = ((" << Target.getName()
3844 << "Operand &)*Operands[0]).getToken();\n\n";
3845 }
3846
3847 if (HasMnemonicAliases) {
3848 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3849 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
3850 }
3851
3852 // Emit code to compute the class list for this operand vector.
3853 if (!ReportMultipleNearMisses) {
3854 OS << " // Some state to try to produce better error messages.\n";
3855 OS << " bool HadMatchOtherThanFeatures = false;\n";
3856 OS << " bool HadMatchOtherThanPredicate = false;\n";
3857 OS << " unsigned RetCode = Match_InvalidOperand;\n";
3858 OS << " MissingFeatures.set();\n";
3859 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
3860 OS << " // wrong for all instances of the instruction.\n";
3861 OS << " ErrorInfo = ~0ULL;\n";
3862 }
3863
3864 if (HasOptionalOperands)
3865 OS << " SmallBitVector OptionalOperandsMask("
3866 << MaxNumOperands + HasMnemonicFirst << ");\n";
3867
3868 // Emit code to search the table.
3869 OS << " // Find the appropriate table for this asm variant.\n";
3870 OS << " const MatchEntry *Start, *End;\n";
3871 OS << " switch (VariantID) {\n";
3872 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3873 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3874 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3875 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3876 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3877 << "); End = std::end(MatchTable" << VC << "); break;\n";
3878 }
3879 OS << " }\n";
3880
3881 OS << " // Search the table.\n";
3882 if (HasMnemonicFirst) {
3883 OS << " auto MnemonicRange = "
3884 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3885 } else {
3886 OS << " auto MnemonicRange = std::pair(Start, End);\n";
3887 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3888 OS << " if (!Mnemonic.empty())\n";
3889 OS << " MnemonicRange = "
3890 "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3891 }
3892
3893 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"AsmMatcher: found \" "
3894 "<<\n"
3895 << " std::distance(MnemonicRange.first, MnemonicRange.second) <<\n"
3896 << " \" encodings with mnemonic '\" << Mnemonic << \"'\\n\");\n\n";
3897
3898 OS << " // Return a more specific error code if no mnemonics match.\n";
3899 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3900 OS << " return Match_MnemonicFail;\n\n";
3901
3902 if (ReportMultipleNearMisses) {
3903 OS << " // First operand near-miss of each opcode that mismatched in\n";
3904 OS << " // more than one operand. Used only if no opcode yields a\n";
3905 OS << " // near-miss of its own (see below).\n";
3906 OS << " SmallVector<NearMissInfo, 4> MultiMismatchFallback;\n\n";
3907 }
3908
3909 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3910 << "*ie = MnemonicRange.second;\n";
3911 OS << " it != ie; ++it) {\n";
3912 OS << " const FeatureBitset &RequiredFeatures = "
3913 "FeatureBitsets[it->RequiredFeaturesIdx];\n";
3914 OS << " bool HasRequiredFeatures =\n";
3915 OS << " (AvailableFeatures & RequiredFeatures) == RequiredFeatures;\n";
3916 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Trying to match "
3917 "opcode \"\n";
3918 OS << " << MII.getName(it->Opcode) "
3919 "<< \"\\n\");\n";
3920
3921 if (ReportMultipleNearMisses) {
3922 OS << " // Some state to record ways in which this instruction did not "
3923 "match.\n";
3924 OS << " NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n";
3925 OS << " NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n";
3926 OS << " NearMissInfo EarlyPredicateNearMiss = "
3927 "NearMissInfo::getSuccess();\n";
3928 OS << " NearMissInfo LatePredicateNearMiss = "
3929 "NearMissInfo::getSuccess();\n";
3930 OS << " bool MultipleInvalidOperands = false;\n";
3931 }
3932
3933 if (HasMnemonicFirst) {
3934 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3935 OS << " assert(Mnemonic == it->getMnemonic());\n";
3936 }
3937
3938 // Emit check that the subclasses match.
3939 if (!ReportMultipleNearMisses)
3940 OS << " bool OperandsValid = true;\n";
3941 if (HasOptionalOperands)
3942 OS << " OptionalOperandsMask.reset(0, "
3943 << MaxNumOperands + HasMnemonicFirst << ");\n";
3944 OS << " unsigned ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")
3945 << ";\n";
3946 OS << " for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")
3947 << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";
3948 OS << " auto Formal = "
3949 << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";
3950 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3951 OS << " dbgs() << \" Matching formal operand class \" "
3952 "<< getMatchClassName(Formal)\n";
3953 OS << " << \" against actual operand at index \" "
3954 "<< ActualIdx);\n";
3955 OS << " if (ActualIdx < Operands.size())\n";
3956 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \" (\";\n";
3957 OS << " Operands[ActualIdx]->print(dbgs(), "
3958 "getContext().getAsmInfo()); dbgs() << "
3959 "\"): \");\n";
3960 OS << " else\n";
3961 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \": \");\n";
3962 OS << " if (ActualIdx >= Operands.size()) {\n";
3963 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"actual operand "
3964 "index out of range\\n\");\n";
3965 if (ReportMultipleNearMisses) {
3966 OS << " bool ThisOperandValid = (Formal == "
3967 << "InvalidMatchClass) || "
3968 "isSubclass(Formal, OptionalMatchClass);\n";
3969 OS << " if (!ThisOperandValid) {\n";
3970 OS << " if (!OperandNearMiss) {\n";
3971 OS << " // Record info about match failure for later use.\n";
3972 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording "
3973 "too-few-operands near miss\\n\");\n";
3974 OS << " OperandNearMiss =\n";
3975 OS << " NearMissInfo::getTooFewOperands(Formal, "
3976 "it->Opcode);\n";
3977 OS << " } else if (OperandNearMiss.getKind() != "
3978 "NearMissInfo::NearMissTooFewOperands) {\n";
3979 OS << " // If more than one operand is invalid, give up on this "
3980 "match entry.\n";
3981 OS << " DEBUG_WITH_TYPE(\n";
3982 OS << " \"asm-matcher\",\n";
3983 OS << " dbgs() << \"second invalid operand, giving up on "
3984 "this opcode\\n\");\n";
3985 OS << " MultipleInvalidOperands = true;\n";
3986 OS << " break;\n";
3987 OS << " }\n";
3988 OS << " } else {\n";
3989 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal "
3990 "operand not required\\n\");\n";
3991 OS << " if (isSubclass(Formal, OptionalMatchClass)) {\n";
3992 OS << " OptionalOperandsMask.set("
3993 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
3994 OS << " }\n";
3995 OS << " }\n";
3996 OS << " continue;\n";
3997 } else {
3998 OS << " if (Formal == InvalidMatchClass) {\n";
3999 if (HasOptionalOperands) {
4000 OS << " OptionalOperandsMask.set("
4001 << (HasMnemonicFirst ? "FormalIdx + 1, " : "FormalIdx, ")
4002 << MaxNumOperands + HasMnemonicFirst << ");\n";
4003 }
4004 OS << " break;\n";
4005 OS << " }\n";
4006 OS << " if (isSubclass(Formal, OptionalMatchClass)) {\n";
4007 if (HasOptionalOperands)
4008 OS << " OptionalOperandsMask.set("
4009 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
4010 OS << " continue;\n";
4011 OS << " }\n";
4012 OS << " OperandsValid = false;\n";
4013 OS << " ErrorInfo = ActualIdx;\n";
4014 OS << " break;\n";
4015 }
4016 OS << " }\n";
4017 OS << " MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";
4018 OS << " unsigned Diag = validateOperandClass(Actual, Formal, *STI);\n";
4019 OS << " if (Diag == Match_Success) {\n";
4020 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
4021 OS << " dbgs() << \"match success using generic "
4022 "matcher\\n\");\n";
4023 OS << " ++ActualIdx;\n";
4024 OS << " continue;\n";
4025 OS << " }\n";
4026 OS << " // If the generic handler indicates an invalid operand\n";
4027 OS << " // failure, check for a special case.\n";
4028 OS << " if (Diag != Match_Success) {\n";
4029 OS << " unsigned TargetDiag = validateTargetOperandClass(Actual, "
4030 "Formal);\n";
4031 OS << " if (TargetDiag == Match_Success) {\n";
4032 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
4033 OS << " dbgs() << \"match success using target "
4034 "matcher\\n\");\n";
4035 OS << " ++ActualIdx;\n";
4036 OS << " continue;\n";
4037 OS << " }\n";
4038 OS << " // If the target matcher returned a specific error code use\n";
4039 OS << " // that, else use the one from the generic matcher.\n";
4040 OS << " if (TargetDiag != Match_InvalidOperand && "
4041 "HasRequiredFeatures)\n";
4042 OS << " Diag = TargetDiag;\n";
4043 OS << " }\n";
4044 OS << " // If current formal operand wasn't matched and it is optional\n"
4045 << " // then try to match next formal operand\n";
4046 OS << " if (Diag == Match_InvalidOperand "
4047 << "&& isSubclass(Formal, OptionalMatchClass)) {\n";
4048 if (HasOptionalOperands)
4049 OS << " OptionalOperandsMask.set("
4050 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
4051 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"ignoring "
4052 "optional operand\\n\");\n";
4053 OS << " continue;\n";
4054 OS << " }\n";
4055
4056 if (ReportMultipleNearMisses) {
4057 OS << " if (!OperandNearMiss) {\n";
4058 OS << " // If this is the first invalid operand we have seen, "
4059 "record some\n";
4060 OS << " // information about it.\n";
4061 OS << " DEBUG_WITH_TYPE(\n";
4062 OS << " \"asm-matcher\",\n";
4063 OS << " dbgs()\n";
4064 OS << " << \"operand match failed, recording near-miss with "
4065 "diag code \"\n";
4066 OS << " << Diag << \"\\n\");\n";
4067 OS << " OperandNearMiss =\n";
4068 OS << " NearMissInfo::getMissedOperand(Diag, Formal, "
4069 "it->Opcode, ActualIdx);\n";
4070 OS << " ++ActualIdx;\n";
4071 OS << " } else {\n";
4072 OS << " // If more than one operand is invalid, give up on this "
4073 "match entry.\n";
4074 OS << " DEBUG_WITH_TYPE(\n";
4075 OS << " \"asm-matcher\",\n";
4076 OS << " dbgs() << \"second operand mismatch, skipping this "
4077 "opcode\\n\");\n";
4078 OS << " MultipleInvalidOperands = true;\n";
4079 OS << " break;\n";
4080 OS << " }\n";
4081 OS << " }\n\n";
4082 OS << " // Reject surplus operands as one more operand mismatch.\n";
4083 OS << " if (!MultipleInvalidOperands && ActualIdx < Operands.size()) "
4084 "{\n";
4085 OS << " if (!OperandNearMiss) {\n";
4086 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"too many "
4087 "operands, recording near-miss at index \"\n";
4088 OS << " << ActualIdx << \"\\n\");\n";
4089 OS << " OperandNearMiss = NearMissInfo::getMissedOperand(\n";
4090 OS << " Match_InvalidOperand, InvalidMatchClass, it->Opcode, "
4091 "ActualIdx);\n";
4092 OS << " } else {\n";
4093 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"too many "
4094 "operands after an earlier mismatch, skipping this opcode\\n\");\n";
4095 OS << " MultipleInvalidOperands = true;\n";
4096 OS << " }\n";
4097 OS << " }\n\n";
4098 } else {
4099 OS << " // If this operand is broken for all of the instances of "
4100 "this\n";
4101 OS << " // mnemonic, keep track of it so we can report loc info.\n";
4102 OS << " // If we already had a match that only failed due to a\n";
4103 OS << " // target predicate, that diagnostic is preferred.\n";
4104 OS << " if (!HadMatchOtherThanPredicate &&\n";
4105 OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) "
4106 "{\n";
4107 OS << " if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag "
4108 "!= Match_InvalidOperand))\n";
4109 OS << " RetCode = Diag;\n";
4110 OS << " ErrorInfo = ActualIdx;\n";
4111 OS << " }\n";
4112 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
4113 OS << " OperandsValid = false;\n";
4114 OS << " break;\n";
4115 OS << " }\n\n";
4116 }
4117
4118 if (ReportMultipleNearMisses)
4119 OS << " if (MultipleInvalidOperands) {\n";
4120 else
4121 OS << " if (!OperandsValid) {\n";
4122 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4123 "multiple \"\n";
4124 OS << " \"operand mismatches, "
4125 "ignoring \"\n";
4126 OS << " \"this opcode\\n\");\n";
4127 if (ReportMultipleNearMisses) {
4128 OS << " // Too many invalid operands to report a single near-miss;\n";
4129 OS << " // keep the first one as a fallback in case no opcode\n";
4130 OS << " // matches more closely.\n";
4131 OS << " if (OperandNearMiss)\n";
4132 OS << " MultiMismatchFallback.push_back(OperandNearMiss);\n";
4133 }
4134 OS << " continue;\n";
4135 OS << " }\n";
4136
4137 // Emit check that the required features are available.
4138 OS << " if (!HasRequiredFeatures) {\n";
4139 if (!ReportMultipleNearMisses)
4140 OS << " HadMatchOtherThanFeatures = true;\n";
4141 OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
4142 "~AvailableFeatures;\n";
4143 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
4144 "features:\";\n";
4145 OS << " for (unsigned I = 0, E = "
4146 "NewMissingFeatures.size(); I != E; ++I)\n";
4147 OS << " if (NewMissingFeatures[I])\n";
4148 OS << " dbgs() << ' ' << I;\n";
4149 OS << " dbgs() << \"\\n\");\n";
4150 if (ReportMultipleNearMisses) {
4151 OS << " FeaturesNearMiss = "
4152 "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
4153 } else {
4154 OS << " if (NewMissingFeatures.count() <=\n"
4155 " MissingFeatures.count())\n";
4156 OS << " MissingFeatures = NewMissingFeatures;\n";
4157 OS << " continue;\n";
4158 }
4159 OS << " }\n";
4160 OS << "\n";
4161 OS << " Inst.clear();\n\n";
4162 OS << " Inst.setOpcode(it->Opcode);\n";
4163 // Verify the instruction with the target-specific match predicate function.
4164 OS << " // We have a potential match but have not rendered the operands.\n"
4165 << " // Check the target predicate to handle any context sensitive\n"
4166 " // constraints.\n"
4167 << " // For example, Ties that are referenced multiple times must be\n"
4168 " // checked here to ensure the input is the same for each match\n"
4169 " // constraints. If we leave it any later the ties will have been\n"
4170 " // canonicalized\n"
4171 << " unsigned MatchResult;\n"
4172 << " if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "
4173 "Operands)) != Match_Success) {\n"
4174 << " Inst.clear();\n";
4175 OS << " DEBUG_WITH_TYPE(\n";
4176 OS << " \"asm-matcher\",\n";
4177 OS << " dbgs() << \"Early target match predicate failed with diag "
4178 "code \"\n";
4179 OS << " << MatchResult << \"\\n\");\n";
4180 if (ReportMultipleNearMisses) {
4181 OS << " EarlyPredicateNearMiss = "
4182 "NearMissInfo::getMissedPredicate(MatchResult);\n";
4183 } else {
4184 OS << " RetCode = MatchResult;\n"
4185 << " HadMatchOtherThanPredicate = true;\n"
4186 << " continue;\n";
4187 }
4188 OS << " }\n\n";
4189
4190 if (ReportMultipleNearMisses) {
4191 OS << " // If we did not successfully match the operands, then we can't "
4192 "convert to\n";
4193 OS << " // an MCInst, so bail out on this instruction variant now.\n";
4194 OS << " if (OperandNearMiss) {\n";
4195 OS << " // If the operand mismatch was the only problem, report it as "
4196 "a near-miss.\n";
4197 OS << " if (NearMisses && !FeaturesNearMiss && "
4198 "!EarlyPredicateNearMiss) {\n";
4199 OS << " DEBUG_WITH_TYPE(\n";
4200 OS << " \"asm-matcher\",\n";
4201 OS << " dbgs()\n";
4202 OS << " << \"Opcode result: one mismatched operand, adding "
4203 "near-miss\\n\");\n";
4204 OS << " NearMisses->push_back(OperandNearMiss);\n";
4205 OS << " } else {\n";
4206 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4207 "multiple \"\n";
4208 OS << " \"types of "
4209 "mismatch, so not \"\n";
4210 OS << " \"reporting "
4211 "near-miss\\n\");\n";
4212 OS << " }\n";
4213 OS << " continue;\n";
4214 OS << " }\n\n";
4215 }
4216
4217 // When converting parsed operands to MCInst we need to know whether optional
4218 // operands were parsed or not so that we can choose the correct converter
4219 // function. We also need to know this when checking tied operand constraints.
4220 // DefaultsOffset is an array of deltas between the formal (MCInst) and the
4221 // actual (parsed operand array) operand indices. When all optional operands
4222 // are present, all elements of the array are zeros. If some of the optional
4223 // operands are absent, the array might look like '0, 0, 1, 1, 1, 2, 2, 3',
4224 // where each increment in value reflects the absence of an optional operand.
4225 if (HasOptionalOperands) {
4226 OS << " unsigned DefaultsOffset[" << (MaxNumOperands + 1)
4227 << "] = { 0 };\n";
4228 OS << " assert(OptionalOperandsMask.size() == "
4229 << (MaxNumOperands + HasMnemonicFirst) << ");\n";
4230 OS << " for (unsigned i = 0, NumDefaults = 0; i < " << (MaxNumOperands)
4231 << "; ++i) {\n";
4232 OS << " NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);\n";
4233 OS << " DefaultsOffset[i + 1] = NumDefaults;\n";
4234 OS << " }\n\n";
4235 }
4236
4237 OS << " if (matchingInlineAsm) {\n";
4238 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
4239 if (!ReportMultipleNearMisses) {
4240 if (HasOptionalOperands) {
4241 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4242 "Operands,\n";
4243 OS << " DefaultsOffset, "
4244 "ErrorInfo))\n";
4245 } else {
4246 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4247 "Operands,\n";
4248 OS << " ErrorInfo))\n";
4249 }
4250 OS << " return Match_InvalidTiedOperand;\n";
4251 OS << "\n";
4252 }
4253 OS << " return Match_Success;\n";
4254 OS << " }\n\n";
4255 OS << " // We have selected a definite instruction, convert the parsed\n"
4256 << " // operands into the appropriate MCInst.\n";
4257 if (HasOptionalOperands) {
4258 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,\n"
4259 << " OptionalOperandsMask, DefaultsOffset);\n";
4260 } else {
4261 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
4262 }
4263 OS << "\n";
4264
4265 // Verify the instruction with the target-specific match predicate function.
4266 OS << " // We have a potential match. Check the target predicate to\n"
4267 << " // handle any context sensitive constraints.\n"
4268 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
4269 << " Match_Success) {\n"
4270 << " DEBUG_WITH_TYPE(\"asm-matcher\",\n"
4271 << " dbgs() << \"Target match predicate failed with "
4272 "diag code \"\n"
4273 << " << MatchResult << \"\\n\");\n"
4274 << " Inst.clear();\n";
4275 if (ReportMultipleNearMisses) {
4276 OS << " LatePredicateNearMiss = "
4277 "NearMissInfo::getMissedPredicate(MatchResult);\n";
4278 } else {
4279 OS << " RetCode = MatchResult;\n"
4280 << " HadMatchOtherThanPredicate = true;\n"
4281 << " continue;\n";
4282 }
4283 OS << " }\n\n";
4284
4285 if (ReportMultipleNearMisses) {
4286 OS << " int NumNearMisses = ((int)(bool)OperandNearMiss +\n";
4287 OS << " (int)(bool)FeaturesNearMiss +\n";
4288 OS << " (int)(bool)EarlyPredicateNearMiss +\n";
4289 OS << " (int)(bool)LatePredicateNearMiss);\n";
4290 OS << " if (NumNearMisses == 1) {\n";
4291 OS << " // We had exactly one type of near-miss, so add that to the "
4292 "list.\n";
4293 OS << " assert(!OperandNearMiss && \"OperandNearMiss was handled "
4294 "earlier\");\n";
4295 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4296 "found one type of \"\n";
4297 OS << " \"mismatch, so "
4298 "reporting a \"\n";
4299 OS << " \"near-miss\\n\");\n";
4300 OS << " if (NearMisses && FeaturesNearMiss)\n";
4301 OS << " NearMisses->push_back(FeaturesNearMiss);\n";
4302 OS << " else if (NearMisses && EarlyPredicateNearMiss)\n";
4303 OS << " NearMisses->push_back(EarlyPredicateNearMiss);\n";
4304 OS << " else if (NearMisses && LatePredicateNearMiss)\n";
4305 OS << " NearMisses->push_back(LatePredicateNearMiss);\n";
4306 OS << "\n";
4307 OS << " continue;\n";
4308 OS << " } else if (NumNearMisses > 1) {\n";
4309 OS << " // This instruction missed in more than one way, so ignore "
4310 "it.\n";
4311 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4312 "multiple \"\n";
4313 OS << " \"types of mismatch, "
4314 "so not \"\n";
4315 OS << " \"reporting "
4316 "near-miss\\n\");\n";
4317 OS << " continue;\n";
4318 OS << " }\n";
4319 }
4320
4321 // Call the post-processing function, if used.
4322 StringRef InsnCleanupFn = AsmParser->getValueAsString(FieldName: "AsmParserInstCleanup");
4323 if (!InsnCleanupFn.empty())
4324 OS << " " << InsnCleanupFn << "(Inst);\n";
4325
4326 if (HasDeprecation) {
4327 OS << " std::string Info;\n";
4328 OS << " if "
4329 "(!getParser().getTargetParser().getTargetOptions()."
4330 "MCNoDeprecatedWarn &&\n";
4331 OS << " MII.getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
4332 OS << " SMLoc Loc = ((" << Target.getName()
4333 << "Operand &)*Operands[0]).getStartLoc();\n";
4334 OS << " getParser().Warning(Loc, Info, {});\n";
4335 OS << " }\n";
4336 }
4337
4338 if (!ReportMultipleNearMisses) {
4339 if (HasOptionalOperands) {
4340 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4341 "Operands,\n";
4342 OS << " DefaultsOffset, "
4343 "ErrorInfo))\n";
4344 } else {
4345 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4346 "Operands,\n";
4347 OS << " ErrorInfo))\n";
4348 }
4349 OS << " return Match_InvalidTiedOperand;\n";
4350 OS << "\n";
4351 }
4352
4353 OS << " DEBUG_WITH_TYPE(\n";
4354 OS << " \"asm-matcher\",\n";
4355 OS << " dbgs() << \"Opcode result: complete match, selecting this "
4356 "opcode\\n\");\n";
4357 OS << " return Match_Success;\n";
4358 OS << " }\n\n";
4359
4360 if (ReportMultipleNearMisses) {
4361 OS << " // No instruction variants matched exactly. If nothing produced\n";
4362 OS << " // a near-miss, fall back to the multi-mismatch list so we can\n";
4363 OS << " // still give a specific diagnostic rather than a generic\n";
4364 OS << " // \"invalid instruction\".\n";
4365 OS << " if (NearMisses && NearMisses->empty())\n";
4366 OS << " NearMisses->append(MultiMismatchFallback.begin(),\n";
4367 OS << " MultiMismatchFallback.end());\n";
4368 OS << " return Match_NearMisses;\n";
4369 } else {
4370 OS << " // Okay, we had no match. Try to return a useful error code.\n";
4371 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
4372 OS << " return RetCode;\n\n";
4373 OS << " ErrorInfo = 0;\n";
4374 OS << " return Match_MissingFeature;\n";
4375 }
4376 OS << "}\n\n";
4377
4378 if (!Info.OperandMatchInfo.empty())
4379 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
4380 MaxMnemonicIndex, MaxFeaturesIndex: FeatureBitsets.size(),
4381 HasMnemonicFirst, AsmParser: *AsmParser);
4382
4383 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
4384
4385 OS << "\n#ifdef GET_MNEMONIC_SPELL_CHECKER\n";
4386 OS << "#undef GET_MNEMONIC_SPELL_CHECKER\n\n";
4387
4388 emitMnemonicSpellChecker(OS, Target, VariantCount);
4389
4390 OS << "#endif // GET_MNEMONIC_SPELL_CHECKER\n\n";
4391
4392 OS << "\n#ifdef GET_MNEMONIC_CHECKER\n";
4393 OS << "#undef GET_MNEMONIC_CHECKER\n\n";
4394
4395 emitMnemonicChecker(OS, Target, VariantCount, HasMnemonicFirst,
4396 HasMnemonicAliases);
4397
4398 OS << "#endif // GET_MNEMONIC_CHECKER\n\n";
4399}
4400
4401static TableGen::Emitter::OptClass<AsmMatcherEmitter>
4402 X("gen-asm-matcher", "Generate assembly instruction matcher");
4403