1//===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend emits a target specifier matcher for converting parsed
10// assembly operands in the MCInst structures. It also emits a matcher for
11// custom operand parsing.
12//
13// Converting assembly operands into MCInst structures
14// ---------------------------------------------------
15//
16// The input to the target specific matcher is a list of literal tokens and
17// operands. The target specific parser should generally eliminate any syntax
18// which is not relevant for matching; for example, comma tokens should have
19// already been consumed and eliminated by the parser. Most instructions will
20// end up with a single literal token (the instruction name) and some number of
21// operands.
22//
23// Some example inputs, for X86:
24// 'addl' (immediate ...) (register ...)
25// 'add' (immediate ...) (memory ...)
26// 'call' '*' %epc
27//
28// The assembly matcher is responsible for converting this input into a precise
29// machine instruction (i.e., an instruction with a well defined encoding). This
30// mapping has several properties which complicate matching:
31//
32// - It may be ambiguous; many architectures can legally encode particular
33// variants of an instruction in different ways (for example, using a smaller
34// encoding for small immediates). Such ambiguities should never be
35// arbitrarily resolved by the assembler, the assembler is always responsible
36// for choosing the "best" available instruction.
37//
38// - It may depend on the subtarget or the assembler context. Instructions
39// which are invalid for the current mode, but otherwise unambiguous (e.g.,
40// an SSE instruction in a file being assembled for i486) should be accepted
41// and rejected by the assembler front end. However, if the proper encoding
42// for an instruction is dependent on the assembler context then the matcher
43// is responsible for selecting the correct machine instruction for the
44// current mode.
45//
46// The core matching algorithm attempts to exploit the regularity in most
47// instruction sets to quickly determine the set of possibly matching
48// instructions, and the simplify the generated code. Additionally, this helps
49// to ensure that the ambiguities are intentionally resolved by the user.
50//
51// The matching is divided into two distinct phases:
52//
53// 1. Classification: Each operand is mapped to the unique set which (a)
54// contains it, and (b) is the largest such subset for which a single
55// instruction could match all members.
56//
57// For register classes, we can generate these subgroups automatically. For
58// arbitrary operands, we expect the user to define the classes and their
59// relations to one another (for example, 8-bit signed immediates as a
60// subset of 32-bit immediates).
61//
62// By partitioning the operands in this way, we guarantee that for any
63// tuple of classes, any single instruction must match either all or none
64// of the sets of operands which could classify to that tuple.
65//
66// In addition, the subset relation amongst classes induces a partial order
67// on such tuples, which we use to resolve ambiguities.
68//
69// 2. The input can now be treated as a tuple of classes (static tokens are
70// simple singleton sets). Each such tuple should generally map to a single
71// instruction (we currently ignore cases where this isn't true, whee!!!),
72// which we can emit a simple matcher for.
73//
74// Custom Operand Parsing
75// ----------------------
76//
77// Some targets need a custom way to parse operands, some specific instructions
78// can contain arguments that can represent processor flags and other kinds of
79// identifiers that need to be mapped to specific values in the final encoded
80// instructions. The target specific custom operand parsing works in the
81// following way:
82//
83// 1. A operand match table is built, each entry contains a mnemonic, an
84// operand class, a mask for all operand positions for that same
85// class/mnemonic and target features to be checked while trying to match.
86//
87// 2. The operand matcher will try every possible entry with the same
88// mnemonic and will check if the target feature for this mnemonic also
89// matches. After that, if the operand to be matched has its index
90// present in the mask, a successful match occurs. Otherwise, fallback
91// to the regular operand parsing.
92//
93// 3. For a match success, each operand class that has a 'ParserMethod'
94// becomes part of a switch from where the custom method is called.
95//
96//===----------------------------------------------------------------------===//
97
98#include "Common/CodeGenInstAlias.h"
99#include "Common/CodeGenInstruction.h"
100#include "Common/CodeGenRegisters.h"
101#include "Common/CodeGenTarget.h"
102#include "Common/SubtargetFeatureInfo.h"
103#include "Common/Types.h"
104#include "llvm/ADT/CachedHashString.h"
105#include "llvm/ADT/PointerUnion.h"
106#include "llvm/ADT/STLExtras.h"
107#include "llvm/ADT/SmallPtrSet.h"
108#include "llvm/ADT/SmallVector.h"
109#include "llvm/ADT/StringExtras.h"
110#include "llvm/Support/CommandLine.h"
111#include "llvm/Support/Debug.h"
112#include "llvm/Support/ErrorHandling.h"
113#include "llvm/Support/FormatVariadic.h"
114#include "llvm/TableGen/Error.h"
115#include "llvm/TableGen/Record.h"
116#include "llvm/TableGen/StringMatcher.h"
117#include "llvm/TableGen/StringToOffsetTable.h"
118#include "llvm/TableGen/TableGenBackend.h"
119#include <cassert>
120#include <cctype>
121#include <forward_list>
122#include <map>
123#include <set>
124
125using namespace llvm;
126
127#define DEBUG_TYPE "asm-matcher-emitter"
128
129static cl::OptionCategory AsmMatcherEmitterCat("Options for -gen-asm-matcher");
130
131static cl::opt<std::string>
132 MatchPrefix("match-prefix", cl::init(Val: ""),
133 cl::desc("Only match instructions with the given prefix"),
134 cl::cat(AsmMatcherEmitterCat));
135
136namespace {
137class AsmMatcherInfo;
138
139// Register sets are used as keys in some second-order sets TableGen creates
140// when generating its data structures. This means that the order of two
141// RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
142// can even affect compiler output (at least seen in diagnostics produced when
143// all matches fail). So we use a type that sorts them consistently.
144using RegisterSet = std::set<const Record *, LessRecordByID>;
145
146class AsmMatcherEmitter {
147 const RecordKeeper &Records;
148
149public:
150 AsmMatcherEmitter(const RecordKeeper &R) : Records(R) {}
151
152 void run(raw_ostream &o);
153};
154
155/// ClassInfo - Helper class for storing the information about a particular
156/// class of operands which can be matched.
157struct ClassInfo {
158 enum ClassInfoKind {
159 /// Invalid kind, for use as a sentinel value.
160 Invalid = 0,
161
162 /// The class for a particular token.
163 Token,
164
165 /// The (first) register class, subsequent register classes are
166 /// RegisterClass0+1, and so on.
167 RegisterClass0,
168
169 /// The (first) register class by hwmode, subsequent register classes by
170 /// hwmode are RegisterClassByHwMode0+1, and so on.
171 RegisterClassByHwMode0 = 1 << 12,
172
173 /// The (first) user defined class, subsequent user defined classes are
174 /// UserClass0+1, and so on.
175 UserClass0 = 1 << 24
176 };
177
178 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
179 /// N) for the Nth user defined class.
180 unsigned Kind = 0;
181
182 /// SuperClasses - The super classes of this class. Note that for simplicities
183 /// sake user operands only record their immediate super class, while register
184 /// operands include all superclasses.
185 std::vector<ClassInfo *> SuperClasses;
186
187 /// Name - The full class name, suitable for use in an enum.
188 std::string Name;
189
190 /// ClassName - The unadorned generic name for this class (e.g., Token).
191 std::string ClassName;
192
193 /// ValueName - The name of the value this class represents; for a token this
194 /// is the literal token string, for an operand it is the TableGen class (or
195 /// empty if this is a derived class).
196 std::string ValueName;
197
198 /// PredicateMethod - The name of the operand method to test whether the
199 /// operand matches this class; this is not valid for Token or register kinds.
200 std::string PredicateMethod;
201
202 /// RenderMethod - The name of the operand method to add this operand to an
203 /// MCInst; this is not valid for Token or register kinds.
204 std::string RenderMethod;
205
206 /// ParserMethod - The name of the operand method to do a target specific
207 /// parsing on the operand.
208 std::string ParserMethod;
209
210 /// For register classes: the records for all the registers in this class.
211 RegisterSet Registers;
212
213 /// For custom match classes: the diagnostic kind for when the predicate
214 /// fails.
215 std::string DiagnosticType;
216
217 /// For custom match classes: the diagnostic string for when the predicate
218 /// fails.
219 std::string DiagnosticString;
220
221 /// Is this operand optional and not always required.
222 bool IsOptional = false;
223
224 /// DefaultMethod - The name of the method that returns the default operand
225 /// for optional operand
226 std::string DefaultMethod;
227
228public:
229 /// isRegisterClass() - Check if this is a register class.
230 bool isRegisterClass() const {
231 return Kind >= RegisterClass0 && Kind < RegisterClassByHwMode0;
232 }
233
234 bool isRegisterClassByHwMode() const {
235 return Kind >= RegisterClassByHwMode0 && Kind < UserClass0;
236 }
237
238 /// isUserClass() - Check if this is a user defined class.
239 bool isUserClass() const { return Kind >= UserClass0; }
240
241 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
242 /// are related if they are in the same class hierarchy.
243 bool isRelatedTo(const ClassInfo &RHS) const {
244 // Tokens are only related to tokens.
245 if (Kind == Token || RHS.Kind == Token)
246 return Kind == Token && RHS.Kind == Token;
247
248 // Registers classes are only related to registers classes, and only if
249 // their intersection is non-empty.
250 if (isRegisterClass() || RHS.isRegisterClass()) {
251 if (!isRegisterClass() || !RHS.isRegisterClass())
252 return false;
253
254 std::vector<const Record *> Tmp;
255 std::set_intersection(first1: Registers.begin(), last1: Registers.end(),
256 first2: RHS.Registers.begin(), last2: RHS.Registers.end(),
257 result: std::back_inserter(x&: Tmp), comp: LessRecordByID());
258
259 return !Tmp.empty();
260 }
261
262 if (isRegisterClassByHwMode() || RHS.isRegisterClassByHwMode())
263 return isRegisterClassByHwMode() == RHS.isRegisterClassByHwMode();
264
265 // Otherwise we have two users operands; they are related if they are in the
266 // same class hierarchy.
267 //
268 // FIXME: This is an oversimplification, they should only be related if they
269 // intersect, however we don't have that information.
270 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
271 const ClassInfo *Root = this;
272 while (!Root->SuperClasses.empty())
273 Root = Root->SuperClasses.front();
274
275 const ClassInfo *RHSRoot = &RHS;
276 while (!RHSRoot->SuperClasses.empty())
277 RHSRoot = RHSRoot->SuperClasses.front();
278
279 return Root == RHSRoot;
280 }
281
282 /// isSubsetOf - Test whether this class is a subset of \p RHS.
283 bool isSubsetOf(const ClassInfo &RHS) const {
284 // This is a subset of RHS if it is the same class...
285 if (this == &RHS)
286 return true;
287
288 // ... or if any of its super classes are a subset of RHS.
289 SmallVector<const ClassInfo *, 16> Worklist(SuperClasses.begin(),
290 SuperClasses.end());
291 SmallPtrSet<const ClassInfo *, 16> Visited;
292 while (!Worklist.empty()) {
293 auto *CI = Worklist.pop_back_val();
294 if (CI == &RHS)
295 return true;
296 for (auto *Super : CI->SuperClasses)
297 if (Visited.insert(Ptr: Super).second)
298 Worklist.push_back(Elt: Super);
299 }
300
301 return false;
302 }
303
304 int getTreeDepth() const {
305 int Depth = 0;
306 const ClassInfo *Root = this;
307 while (!Root->SuperClasses.empty()) {
308 Depth++;
309 Root = Root->SuperClasses.front();
310 }
311 return Depth;
312 }
313
314 const ClassInfo *findRoot() const {
315 const ClassInfo *Root = this;
316 while (!Root->SuperClasses.empty())
317 Root = Root->SuperClasses.front();
318 return Root;
319 }
320
321 /// Compare two classes. This does not produce a total ordering, but does
322 /// guarantee that subclasses are sorted before their parents, and that the
323 /// ordering is transitive.
324 bool operator<(const ClassInfo &RHS) const {
325 if (this == &RHS)
326 return false;
327
328 // First, enforce the ordering between the three different types of class.
329 // Tokens sort before registers, which sort before regclass by hwmode, which
330 // sort before user classes.
331 if (Kind == Token) {
332 if (RHS.Kind != Token)
333 return true;
334 assert(RHS.Kind == Token);
335 } else if (isRegisterClass()) {
336 if (RHS.Kind == Token)
337 return false;
338 else if (RHS.isUserClass() || RHS.isRegisterClassByHwMode())
339 return true;
340 assert(RHS.isRegisterClass());
341 } else if (isRegisterClassByHwMode()) {
342 if (RHS.Kind == Token || RHS.isRegisterClass())
343 return false;
344 else if (RHS.isUserClass())
345 return true;
346 assert(RHS.isRegisterClassByHwMode());
347 } else if (isUserClass()) {
348 if (!RHS.isUserClass())
349 return false;
350 assert(RHS.isUserClass());
351 } else {
352 llvm_unreachable("Unknown ClassInfoKind");
353 }
354
355 if (Kind == Token || isUserClass()) {
356 // Related tokens and user classes get sorted by depth in the inheritence
357 // tree (so that subclasses are before their parents).
358 if (isRelatedTo(RHS)) {
359 if (getTreeDepth() > RHS.getTreeDepth())
360 return true;
361 if (getTreeDepth() < RHS.getTreeDepth())
362 return false;
363 } else {
364 // Unrelated tokens and user classes are ordered by the name of their
365 // root nodes, so that there is a consistent ordering between
366 // unconnected trees.
367 return findRoot()->ValueName < RHS.findRoot()->ValueName;
368 }
369 } else if (isRegisterClass()) {
370 // For register sets, sort by number of registers. This guarantees that
371 // a set will always sort before all of it's strict supersets.
372 if (Registers.size() != RHS.Registers.size())
373 return Registers.size() < RHS.Registers.size();
374 } else if (isRegisterClassByHwMode()) {
375 // Ensure the MCK enum entries are in the same order as RegClassIDs. The
376 // lookup table to from RegByHwMode to concrete class relies on it.
377 return Kind < RHS.Kind;
378 } else {
379 llvm_unreachable("Unknown ClassInfoKind");
380 }
381
382 // FIXME: We should be able to just return false here, as we only need a
383 // partial order (we use stable sorts, so this is deterministic) and the
384 // name of a class shouldn't be significant. However, some of the backends
385 // accidentally rely on this behaviour, so it will have to stay like this
386 // until they are fixed.
387 return ValueName < RHS.ValueName;
388 }
389};
390
391class AsmVariantInfo {
392public:
393 StringRef RegisterPrefix;
394 StringRef TokenizingCharacters;
395 StringRef SeparatorCharacters;
396 StringRef BreakCharacters;
397 StringRef Name;
398 int AsmVariantNo;
399};
400
401bool getPreferSmallerInstructions(CodeGenTarget const &Target) {
402 return Target.getAsmParser()->getValueAsBit(FieldName: "PreferSmallerInstructions");
403}
404
405/// MatchableInfo - Helper class for storing the necessary information for an
406/// instruction or alias which is capable of being matched.
407struct MatchableInfo {
408 struct AsmOperand {
409 /// Token - This is the token that the operand came from.
410 StringRef Token;
411
412 /// The unique class instance this operand should match.
413 ClassInfo *Class = nullptr;
414
415 /// The operand name this is, if anything.
416 StringRef SrcOpName;
417
418 /// The operand name this is, before renaming for tied operands.
419 StringRef OrigSrcOpName;
420
421 /// The suboperand index within SrcOpName, or -1 for the entire operand.
422 int SubOpIdx = -1;
423
424 /// Whether the token is "isolated", i.e., it is preceded and followed
425 /// by separators.
426 bool IsIsolatedToken;
427
428 /// Register record if this token is singleton register.
429 const Record *SingletonReg = nullptr;
430
431 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
432 : Token(T), IsIsolatedToken(IsIsolatedToken) {}
433 };
434
435 /// ResOperand - This represents a single operand in the result instruction
436 /// generated by the match. In cases (like addressing modes) where a single
437 /// assembler operand expands to multiple MCOperands, this represents the
438 /// single assembler operand, not the MCOperand.
439 struct ResOperand {
440 enum {
441 /// RenderAsmOperand - This represents an operand result that is
442 /// generated by calling the render method on the assembly operand. The
443 /// corresponding AsmOperand is specified by AsmOperandNum.
444 RenderAsmOperand,
445
446 /// TiedOperand - This represents a result operand that is a duplicate of
447 /// a previous result operand.
448 TiedOperand,
449
450 /// ImmOperand - This represents an immediate value that is dumped into
451 /// the operand.
452 ImmOperand,
453
454 /// RegOperand - This represents a fixed register that is dumped in.
455 RegOperand
456 } Kind;
457
458 /// Tuple containing the index of the (earlier) result operand that should
459 /// be copied from, as well as the indices of the corresponding (parsed)
460 /// operands in the asm string.
461 struct TiedOperandsTuple {
462 unsigned ResOpnd;
463 unsigned SrcOpnd1Idx;
464 unsigned SrcOpnd2Idx;
465 };
466
467 union {
468 /// This is the operand # in the AsmOperands list that this should be
469 /// copied from.
470 unsigned AsmOperandNum;
471
472 /// Description of tied operands.
473 TiedOperandsTuple TiedOperands;
474
475 /// ImmVal - This is the immediate value added to the instruction.
476 int64_t ImmVal;
477
478 /// Register - This is the register record.
479 const Record *Register;
480 };
481
482 /// MINumOperands - The number of MCInst operands populated by this
483 /// operand.
484 unsigned MINumOperands;
485
486 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
487 ResOperand X;
488 X.Kind = RenderAsmOperand;
489 X.AsmOperandNum = AsmOpNum;
490 X.MINumOperands = NumOperands;
491 return X;
492 }
493
494 static ResOperand getTiedOp(unsigned TiedOperandNum, unsigned SrcOperand1,
495 unsigned SrcOperand2) {
496 ResOperand X;
497 X.Kind = TiedOperand;
498 X.TiedOperands = {.ResOpnd: TiedOperandNum, .SrcOpnd1Idx: SrcOperand1, .SrcOpnd2Idx: SrcOperand2};
499 X.MINumOperands = 1;
500 return X;
501 }
502
503 static ResOperand getImmOp(int64_t Val) {
504 ResOperand X;
505 X.Kind = ImmOperand;
506 X.ImmVal = Val;
507 X.MINumOperands = 1;
508 return X;
509 }
510
511 static ResOperand getRegOp(const Record *Reg) {
512 ResOperand X;
513 X.Kind = RegOperand;
514 X.Register = Reg;
515 X.MINumOperands = 1;
516 return X;
517 }
518 };
519
520 /// AsmVariantID - Target's assembly syntax variant no.
521 int AsmVariantID;
522
523 /// AsmString - The assembly string for this instruction (with variants
524 /// removed), e.g. "movsx $src, $dst".
525 std::string AsmString;
526
527 /// TheDef - This is the definition of the instruction or InstAlias that this
528 /// matchable came from.
529 const Record *const TheDef;
530
531 // ResInstSize - The size of the resulting instruction for this matchable.
532 unsigned ResInstSize;
533
534 /// DefRec - This is the definition that it came from.
535 PointerUnion<const CodeGenInstruction *, const CodeGenInstAlias *> DefRec;
536
537 const CodeGenInstruction *getResultInst() const {
538 if (isa<const CodeGenInstruction *>(Val: DefRec))
539 return cast<const CodeGenInstruction *>(Val: DefRec);
540 return cast<const CodeGenInstAlias *>(Val: DefRec)->ResultInst;
541 }
542
543 /// ResOperands - This is the operand list that should be built for the result
544 /// MCInst.
545 SmallVector<ResOperand, 8> ResOperands;
546
547 /// Mnemonic - This is the first token of the matched instruction, its
548 /// mnemonic.
549 StringRef Mnemonic;
550
551 /// AsmOperands - The textual operands that this instruction matches,
552 /// annotated with a class and where in the OperandList they were defined.
553 /// This directly corresponds to the tokenized AsmString after the mnemonic is
554 /// removed.
555 SmallVector<AsmOperand, 8> AsmOperands;
556
557 /// Predicates - The required subtarget features to match this instruction.
558 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
559
560 /// ConversionFnKind - The enum value which is passed to the generated
561 /// convertToMCInst to convert parsed operands into an MCInst for this
562 /// function.
563 std::string ConversionFnKind;
564
565 /// If this instruction is deprecated in some form.
566 bool HasDeprecation = false;
567
568 /// If this is an alias, this is use to determine whether or not to using
569 /// the conversion function defined by the instruction's AsmMatchConverter
570 /// or to use the function generated by the alias.
571 bool UseInstAsmMatchConverter;
572
573 MatchableInfo(const CodeGenInstruction &CGI)
574 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef),
575 ResInstSize(TheDef->getValueAsInt(FieldName: "Size")), DefRec(&CGI),
576 UseInstAsmMatchConverter(true) {}
577
578 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
579 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
580 ResInstSize(Alias->ResultInst->TheDef->getValueAsInt(FieldName: "Size")),
581 DefRec(Alias.release()), UseInstAsmMatchConverter(TheDef->getValueAsBit(
582 FieldName: "UseInstAsmMatchConverter")) {}
583
584 // Could remove this and the dtor if PointerUnion supported unique_ptr
585 // elements with a dynamic failure/assertion (like the one below) in the case
586 // where it was copied while being in an owning state.
587 MatchableInfo(const MatchableInfo &RHS)
588 : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
589 TheDef(RHS.TheDef), ResInstSize(RHS.ResInstSize), DefRec(RHS.DefRec),
590 ResOperands(RHS.ResOperands), Mnemonic(RHS.Mnemonic),
591 AsmOperands(RHS.AsmOperands), RequiredFeatures(RHS.RequiredFeatures),
592 ConversionFnKind(RHS.ConversionFnKind),
593 HasDeprecation(RHS.HasDeprecation),
594 UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
595 assert(!isa<const CodeGenInstAlias *>(DefRec));
596 }
597
598 ~MatchableInfo() {
599 delete dyn_cast_if_present<const CodeGenInstAlias *>(Val&: DefRec);
600 }
601
602 // Two-operand aliases clone from the main matchable, but mark the second
603 // operand as a tied operand of the first for purposes of the assembler.
604 void formTwoOperandAlias(StringRef Constraint);
605
606 void initialize(const AsmMatcherInfo &Info,
607 SmallPtrSetImpl<const Record *> &SingletonRegisters,
608 AsmVariantInfo const &Variant, bool HasMnemonicFirst);
609
610 /// validate - Return true if this matchable is a valid thing to match against
611 /// and perform a bunch of validity checking.
612 bool validate(StringRef CommentDelimiter, bool IsAlias) const;
613
614 /// findAsmOperand - Find the AsmOperand with the specified name and
615 /// suboperand index.
616 int findAsmOperand(StringRef N, int SubOpIdx) const {
617 auto I = find_if(Range: AsmOperands, P: [&](const AsmOperand &Op) {
618 return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;
619 });
620 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
621 }
622
623 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
624 /// This does not check the suboperand index.
625 int findAsmOperandNamed(StringRef N, int LastIdx = -1) const {
626 auto I =
627 llvm::find_if(Range: llvm::drop_begin(RangeOrContainer: AsmOperands, N: LastIdx + 1),
628 P: [&](const AsmOperand &Op) { return Op.SrcOpName == N; });
629 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
630 }
631
632 int findAsmOperandOriginallyNamed(StringRef N) const {
633 auto I = find_if(Range: AsmOperands, P: [&](const AsmOperand &Op) {
634 return Op.OrigSrcOpName == N;
635 });
636 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
637 }
638
639 void buildInstructionResultOperands();
640 void buildAliasResultOperands(bool AliasConstraintsAreChecked);
641
642 /// shouldBeMatchedBefore - Compare two matchables for ordering.
643 bool shouldBeMatchedBefore(const MatchableInfo &RHS,
644 bool PreferSmallerInstructions) const {
645 // The primary comparator is the instruction mnemonic.
646 if (int Cmp = Mnemonic.compare_insensitive(RHS: RHS.Mnemonic))
647 return Cmp == -1;
648
649 // (Optionally) Order by the resultant instuctions size.
650 // eg. for ARM thumb instructions smaller encodings should be preferred.
651 if (PreferSmallerInstructions && ResInstSize != RHS.ResInstSize)
652 return ResInstSize < RHS.ResInstSize;
653
654 if (AsmOperands.size() != RHS.AsmOperands.size())
655 return AsmOperands.size() < RHS.AsmOperands.size();
656
657 // Compare lexicographically by operand. The matcher validates that other
658 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
659 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
660 if (*LHSOp.Class < *RHSOp.Class)
661 return true;
662 if (*RHSOp.Class < *LHSOp.Class)
663 return false;
664 }
665
666 // For X86 AVX/AVX512 instructions, we prefer vex encoding because the
667 // vex encoding size is smaller. Since X86InstrSSE.td is included ahead
668 // of X86InstrAVX512.td, the AVX instruction ID is less than AVX512 ID.
669 // We use the ID to sort AVX instruction before AVX512 instruction in
670 // matching table. As well as InstAlias.
671 if (getResultInst()->TheDef->isSubClassOf(Name: "Instruction") &&
672 getResultInst()->TheDef->getValueAsBit(FieldName: "HasPositionOrder") &&
673 RHS.getResultInst()->TheDef->isSubClassOf(Name: "Instruction") &&
674 RHS.getResultInst()->TheDef->getValueAsBit(FieldName: "HasPositionOrder"))
675 return getResultInst()->TheDef->getID() <
676 RHS.getResultInst()->TheDef->getID();
677
678 // Give matches that require more features higher precedence. This is useful
679 // because we cannot define AssemblerPredicates with the negation of
680 // processor features. For example, ARM v6 "nop" may be either a HINT or
681 // MOV. With v6, we want to match HINT. The assembler has no way to
682 // predicate MOV under "NoV6", but HINT will always match first because it
683 // requires V6 while MOV does not.
684 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
685 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
686
687 return false;
688 }
689
690 /// couldMatchAmbiguouslyWith - Check whether this matchable could
691 /// ambiguously match the same set of operands as \p RHS (without being a
692 /// strictly superior match).
693 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS,
694 bool PreferSmallerInstructions) const {
695 // The primary comparator is the instruction mnemonic.
696 if (Mnemonic != RHS.Mnemonic)
697 return false;
698
699 // Different variants can't conflict.
700 if (AsmVariantID != RHS.AsmVariantID)
701 return false;
702
703 // The size of instruction is unambiguous.
704 if (PreferSmallerInstructions && ResInstSize != RHS.ResInstSize)
705 return false;
706
707 // The number of operands is unambiguous.
708 if (AsmOperands.size() != RHS.AsmOperands.size())
709 return false;
710
711 // Otherwise, make sure the ordering of the two instructions is unambiguous
712 // by checking that either (a) a token or operand kind discriminates them,
713 // or (b) the ordering among equivalent kinds is consistent.
714
715 // Tokens and operand kinds are unambiguous (assuming a correct target
716 // specific parser).
717 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
718 if (LHSOp.Class->Kind != RHSOp.Class->Kind ||
719 LHSOp.Class->Kind == ClassInfo::Token)
720 if (*LHSOp.Class < *RHSOp.Class || *RHSOp.Class < *LHSOp.Class)
721 return false;
722 }
723
724 // Otherwise, this operand could commute if all operands are equivalent, or
725 // there is a pair of operands that compare less than and a pair that
726 // compare greater than.
727 bool HasLT = false, HasGT = false;
728 for (const auto &[LHSOp, RHSOp] : zip_equal(t: AsmOperands, u: RHS.AsmOperands)) {
729 if (*LHSOp.Class < *RHSOp.Class)
730 HasLT = true;
731 if (*RHSOp.Class < *LHSOp.Class)
732 HasGT = true;
733 }
734
735 return HasLT == HasGT;
736 }
737
738 void dump() const;
739
740private:
741 void tokenizeAsmString(AsmMatcherInfo const &Info,
742 AsmVariantInfo const &Variant);
743 void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);
744};
745
746struct OperandMatchEntry {
747 unsigned OperandMask;
748 const MatchableInfo *MI;
749 ClassInfo *CI;
750
751 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
752 unsigned opMask) {
753 OperandMatchEntry X;
754 X.OperandMask = opMask;
755 X.CI = ci;
756 X.MI = mi;
757 return X;
758 }
759};
760
761class AsmMatcherInfo {
762public:
763 /// Tracked Records
764 const RecordKeeper &Records;
765
766 /// The tablegen AsmParser record.
767 const Record *AsmParser;
768
769 /// Target - The target information.
770 const CodeGenTarget &Target;
771
772 /// The classes which are needed for matching.
773 std::forward_list<ClassInfo> Classes;
774
775 /// The information on the matchables to match.
776 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
777
778 /// Info for custom matching operands by user defined methods.
779 std::vector<OperandMatchEntry> OperandMatchInfo;
780
781 /// Map of Register records to their class information.
782 using RegisterClassesTy =
783 std::map<const Record *, ClassInfo *, LessRecordByID>;
784 RegisterClassesTy RegisterClasses;
785
786 /// Map of Predicate records to their subtarget information.
787 SubtargetFeatureInfoMap SubtargetFeatures;
788
789 /// Map of AsmOperandClass records to their class information.
790 std::map<const Record *, ClassInfo *> AsmOperandClasses;
791
792 /// Map of RegisterClass records to their class information.
793 std::map<const Record *, ClassInfo *> RegisterClassClasses;
794
795private:
796 /// Map of token to class information which has already been constructed.
797 std::map<std::string, ClassInfo *> TokenClasses;
798
799private:
800 /// getTokenClass - Lookup or create the class for the given token.
801 ClassInfo *getTokenClass(StringRef Token);
802
803 /// getOperandClass - Lookup or create the class for the given operand.
804 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
805 int SubOpIdx);
806 ClassInfo *getOperandClass(const Record *Rec, int SubOpIdx);
807
808 /// buildRegisterClasses - Build the ClassInfo* instances for register
809 /// classes.
810 void
811 buildRegisterClasses(SmallPtrSetImpl<const Record *> &SingletonRegisters);
812
813 /// buildOperandClasses - Build the ClassInfo* instances for user defined
814 /// operand classes.
815 void buildOperandClasses();
816
817 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
818 unsigned AsmOpIdx);
819 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
820 MatchableInfo::AsmOperand &Op);
821
822public:
823 AsmMatcherInfo(const Record *AsmParser, const CodeGenTarget &Target,
824 const RecordKeeper &Records);
825
826 /// Construct the various tables used during matching.
827 void buildInfo();
828
829 /// buildOperandMatchInfo - Build the necessary information to handle user
830 /// defined operand parsing methods.
831 void buildOperandMatchInfo();
832
833 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
834 /// given operand.
835 const SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const {
836 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
837 const auto &I = SubtargetFeatures.find(x: Def);
838 return I == SubtargetFeatures.end() ? nullptr : &I->second;
839 }
840
841 const RecordKeeper &getRecords() const { return Records; }
842
843 bool hasOptionalOperands() const {
844 return any_of(Range: Classes,
845 P: [](const ClassInfo &Class) { return Class.IsOptional; });
846 }
847};
848
849} // end anonymous namespace
850
851#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
852LLVM_DUMP_METHOD void MatchableInfo::dump() const {
853 errs() << TheDef->getName() << " -- "
854 << "flattened:\"" << AsmString << "\"\n";
855
856 errs() << " variant: " << AsmVariantID << "\n";
857
858 for (const auto &[Idx, Op] : enumerate(AsmOperands)) {
859 errs() << " op[" << Idx << "] = " << Op.Class->ClassName << " - ";
860 errs() << '\"' << Op.Token << "\"\n";
861 }
862}
863#endif
864
865static std::pair<StringRef, StringRef>
866parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
867 // Trim whitespace and the leading '$' on the operand names.
868 auto TrimWSDollar = [Loc](StringRef OpName) {
869 OpName = OpName.trim(Chars: " \t");
870 if (!OpName.consume_front(Prefix: "$"))
871 PrintFatalError(ErrorLoc: Loc, Msg: "expected '$' prefix on asm operand name");
872 return OpName;
873 };
874
875 // Split via the '='.
876 auto [Src, Dst] = S.split(Separator: '=');
877 if (Dst == "")
878 PrintFatalError(ErrorLoc: Loc, Msg: "missing '=' in two-operand alias constraint");
879 return {TrimWSDollar(Src), TrimWSDollar(Dst)};
880}
881
882void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
883 // Figure out which operands are aliased and mark them as tied.
884 auto [Src, Dst] = parseTwoOperandConstraint(S: Constraint, Loc: TheDef->getLoc());
885
886 // Find the AsmOperands that refer to the operands we're aliasing.
887 int SrcAsmOperand = findAsmOperandNamed(N: Src);
888 int DstAsmOperand = findAsmOperandNamed(N: Dst);
889 if (SrcAsmOperand == -1)
890 PrintFatalError(ErrorLoc: TheDef->getLoc(),
891 Msg: "unknown source two-operand alias operand '" + Src + "'.");
892 if (DstAsmOperand == -1)
893 PrintFatalError(ErrorLoc: TheDef->getLoc(),
894 Msg: "unknown destination two-operand alias operand '" + Dst +
895 "'.");
896
897 // Find the ResOperand that refers to the operand we're aliasing away
898 // and update it to refer to the combined operand instead.
899 for (ResOperand &Op : ResOperands) {
900 if (Op.Kind == ResOperand::RenderAsmOperand &&
901 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
902 Op.AsmOperandNum = DstAsmOperand;
903 break;
904 }
905 }
906 // Remove the AsmOperand for the alias operand.
907 AsmOperands.erase(CI: AsmOperands.begin() + SrcAsmOperand);
908 // Adjust the ResOperand references to any AsmOperands that followed
909 // the one we just deleted.
910 for (ResOperand &Op : ResOperands) {
911 if (Op.Kind == ResOperand::RenderAsmOperand &&
912 Op.AsmOperandNum > (unsigned)SrcAsmOperand)
913 --Op.AsmOperandNum;
914 }
915}
916
917/// extractSingletonRegisterForAsmOperand - Extract singleton register,
918/// if present, from specified token.
919static void extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
920 const AsmMatcherInfo &Info,
921 StringRef RegisterPrefix) {
922 StringRef Tok = Op.Token;
923
924 // If this token is not an isolated token, i.e., it isn't separated from
925 // other tokens (e.g. with whitespace), don't interpret it as a register name.
926 if (!Op.IsIsolatedToken)
927 return;
928
929 if (RegisterPrefix.empty()) {
930 std::string LoweredTok = Tok.lower();
931 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(Name: LoweredTok))
932 Op.SingletonReg = Reg->TheDef;
933 return;
934 }
935
936 if (!Tok.consume_front(Prefix: RegisterPrefix))
937 return;
938
939 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(Name: Tok))
940 Op.SingletonReg = Reg->TheDef;
941
942 // If there is no register prefix (i.e. "%" in "%eax"), then this may
943 // be some random non-register token, just ignore it.
944}
945
946void MatchableInfo::initialize(
947 const AsmMatcherInfo &Info,
948 SmallPtrSetImpl<const Record *> &SingletonRegisters,
949 AsmVariantInfo const &Variant, bool HasMnemonicFirst) {
950 AsmVariantID = Variant.AsmVariantNo;
951 AsmString = CodeGenInstruction::FlattenAsmStringVariants(
952 AsmString, Variant: Variant.AsmVariantNo);
953
954 tokenizeAsmString(Info, Variant);
955
956 // The first token of the instruction is the mnemonic, which must be a
957 // simple string, not a $foo variable or a singleton register.
958 if (AsmOperands.empty())
959 PrintFatalError(ErrorLoc: TheDef->getLoc(),
960 Msg: "Instruction '" + TheDef->getName() + "' has no tokens");
961
962 assert(!AsmOperands[0].Token.empty());
963 if (HasMnemonicFirst) {
964 Mnemonic = AsmOperands[0].Token;
965 if (Mnemonic[0] == '$')
966 PrintFatalError(ErrorLoc: TheDef->getLoc(),
967 Msg: "Invalid instruction mnemonic '" + Mnemonic + "'!");
968
969 // Remove the first operand, it is tracked in the mnemonic field.
970 AsmOperands.erase(CI: AsmOperands.begin());
971 } else if (AsmOperands[0].Token[0] != '$')
972 Mnemonic = AsmOperands[0].Token;
973
974 // Compute the require features.
975 for (const Record *Predicate : TheDef->getValueAsListOfDefs(FieldName: "Predicates"))
976 if (const SubtargetFeatureInfo *Feature =
977 Info.getSubtargetFeature(Def: Predicate))
978 RequiredFeatures.push_back(Elt: Feature);
979
980 // Collect singleton registers, if used.
981 for (MatchableInfo::AsmOperand &Op : AsmOperands) {
982 extractSingletonRegisterForAsmOperand(Op, Info, RegisterPrefix: Variant.RegisterPrefix);
983 if (Op.SingletonReg)
984 SingletonRegisters.insert(Ptr: Op.SingletonReg);
985 }
986
987 const RecordVal *DepMask = TheDef->getValue(Name: "DeprecatedFeatureMask");
988 if (!DepMask)
989 DepMask = TheDef->getValue(Name: "ComplexDeprecationPredicate");
990
991 HasDeprecation =
992 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
993}
994
995/// Append an AsmOperand for the given substring of AsmString.
996void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {
997 AsmOperands.push_back(Elt: AsmOperand(IsIsolatedToken, Token));
998}
999
1000/// tokenizeAsmString - Tokenize a simplified assembly string.
1001void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
1002 AsmVariantInfo const &Variant) {
1003 StringRef String = AsmString;
1004 size_t Prev = 0;
1005 bool InTok = false;
1006 bool IsIsolatedToken = true;
1007 for (size_t i = 0, e = String.size(); i != e; ++i) {
1008 char Char = String[i];
1009 if (Variant.BreakCharacters.contains(C: Char)) {
1010 if (InTok) {
1011 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken: false);
1012 Prev = i;
1013 IsIsolatedToken = false;
1014 }
1015 InTok = true;
1016 continue;
1017 }
1018 if (Variant.TokenizingCharacters.contains(C: Char)) {
1019 if (InTok) {
1020 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1021 InTok = false;
1022 IsIsolatedToken = false;
1023 }
1024 addAsmOperand(Token: String.substr(Start: i, N: 1), IsIsolatedToken);
1025 Prev = i + 1;
1026 IsIsolatedToken = true;
1027 continue;
1028 }
1029 if (Variant.SeparatorCharacters.contains(C: Char)) {
1030 if (InTok) {
1031 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1032 InTok = false;
1033 }
1034 Prev = i + 1;
1035 IsIsolatedToken = true;
1036 continue;
1037 }
1038
1039 switch (Char) {
1040 case '\\':
1041 if (InTok) {
1042 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken: false);
1043 InTok = false;
1044 IsIsolatedToken = false;
1045 }
1046 ++i;
1047 assert(i != String.size() && "Invalid quoted character");
1048 addAsmOperand(Token: String.substr(Start: i, N: 1), IsIsolatedToken);
1049 Prev = i + 1;
1050 IsIsolatedToken = false;
1051 break;
1052
1053 case '$': {
1054 if (InTok) {
1055 addAsmOperand(Token: String.substr(Start: Prev, N: i - Prev), IsIsolatedToken);
1056 InTok = false;
1057 IsIsolatedToken = false;
1058 }
1059
1060 // If this isn't "${", start new identifier looking like "$xxx"
1061 if (i + 1 == String.size() || String[i + 1] != '{') {
1062 Prev = i;
1063 break;
1064 }
1065
1066 size_t EndPos = String.find(C: '}', From: i);
1067 assert(EndPos != StringRef::npos &&
1068 "Missing brace in operand reference!");
1069 addAsmOperand(Token: String.substr(Start: i, N: EndPos + 1 - i), IsIsolatedToken);
1070 Prev = EndPos + 1;
1071 i = EndPos;
1072 IsIsolatedToken = false;
1073 break;
1074 }
1075
1076 default:
1077 InTok = true;
1078 break;
1079 }
1080 }
1081 if (InTok && Prev != String.size())
1082 addAsmOperand(Token: String.substr(Start: Prev), IsIsolatedToken);
1083}
1084
1085bool MatchableInfo::validate(StringRef CommentDelimiter, bool IsAlias) const {
1086 // Reject matchables with no .s string.
1087 if (AsmString.empty())
1088 PrintFatalError(ErrorLoc: TheDef->getLoc(), Msg: "instruction with empty asm string");
1089
1090 // Reject any matchables with a newline in them, they should be marked
1091 // isCodeGenOnly if they are pseudo instructions.
1092 if (AsmString.find(c: '\n') != std::string::npos)
1093 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1094 Msg: "multiline instruction is not valid for the asmparser, "
1095 "mark it isCodeGenOnly");
1096
1097 // Remove comments from the asm string. We know that the asmstring only
1098 // has one line.
1099 if (!CommentDelimiter.empty() &&
1100 StringRef(AsmString).contains(Other: CommentDelimiter))
1101 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1102 Msg: "asmstring for instruction has comment character in it, "
1103 "mark it isCodeGenOnly");
1104
1105 // Reject matchables with operand modifiers, these aren't something we can
1106 // handle, the target should be refactored to use operands instead of
1107 // modifiers.
1108 //
1109 // Also, check for instructions which reference the operand multiple times,
1110 // if they don't define a custom AsmMatcher: this implies a constraint that
1111 // the built-in matching code would not honor.
1112 std::set<std::string> OperandNames;
1113 for (const AsmOperand &Op : AsmOperands) {
1114 StringRef Tok = Op.Token;
1115 if (Tok[0] == '$' && Tok.contains(C: ':'))
1116 PrintFatalError(
1117 ErrorLoc: TheDef->getLoc(),
1118 Msg: "matchable with operand modifier '" + Tok +
1119 "' not supported by asm matcher. Mark isCodeGenOnly!");
1120 // Verify that any operand is only mentioned once.
1121 // We reject aliases and ignore instructions for now.
1122 if (!IsAlias && TheDef->getValueAsString(FieldName: "AsmMatchConverter").empty() &&
1123 Tok[0] == '$' && !OperandNames.insert(x: Tok.str()).second) {
1124 LLVM_DEBUG({
1125 errs() << "warning: '" << TheDef->getName() << "': "
1126 << "ignoring instruction with tied operand '" << Tok << "'\n";
1127 });
1128 return false;
1129 }
1130 }
1131
1132 return true;
1133}
1134
1135static std::string getEnumNameForToken(StringRef Str) {
1136 std::string Res;
1137
1138 for (char C : Str) {
1139 switch (C) {
1140 case '*':
1141 Res += "_STAR_";
1142 break;
1143 case '%':
1144 Res += "_PCT_";
1145 break;
1146 case ':':
1147 Res += "_COLON_";
1148 break;
1149 case '!':
1150 Res += "_EXCLAIM_";
1151 break;
1152 case '.':
1153 Res += "_DOT_";
1154 break;
1155 case '<':
1156 Res += "_LT_";
1157 break;
1158 case '>':
1159 Res += "_GT_";
1160 break;
1161 case '-':
1162 Res += "_MINUS_";
1163 break;
1164 case '#':
1165 Res += "_HASH_";
1166 break;
1167 default:
1168 if (isAlnum(C))
1169 Res += C;
1170 else
1171 Res += "_" + utostr(X: (unsigned)C) + "_";
1172 }
1173 }
1174
1175 return Res;
1176}
1177
1178ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1179 ClassInfo *&Entry = TokenClasses[Token.str()];
1180
1181 if (!Entry) {
1182 Classes.emplace_front();
1183 Entry = &Classes.front();
1184 Entry->Kind = ClassInfo::Token;
1185 Entry->ClassName = "Token";
1186 Entry->Name = "MCK_" + getEnumNameForToken(Str: Token);
1187 Entry->ValueName = Token.str();
1188 Entry->PredicateMethod = "<invalid>";
1189 Entry->RenderMethod = "<invalid>";
1190 Entry->ParserMethod = "";
1191 Entry->DiagnosticType = "";
1192 Entry->IsOptional = false;
1193 Entry->DefaultMethod = "<invalid>";
1194 }
1195
1196 return Entry;
1197}
1198
1199ClassInfo *
1200AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1201 int SubOpIdx) {
1202 const Record *Rec = OI.Rec;
1203 if (SubOpIdx != -1)
1204 Rec = cast<DefInit>(Val: OI.MIOperandInfo->getArg(Num: SubOpIdx))->getDef();
1205 return getOperandClass(Rec, SubOpIdx);
1206}
1207
1208ClassInfo *AsmMatcherInfo::getOperandClass(const Record *Rec, int SubOpIdx) {
1209 if (Rec->isSubClassOf(Name: "RegisterOperand")) {
1210 // RegisterOperand may have an associated ParserMatchClass. If it does,
1211 // use it, else just fall back to the underlying register class.
1212 const RecordVal *R = Rec->getValue(Name: "ParserMatchClass");
1213 if (!R || !R->getValue())
1214 PrintFatalError(ErrorLoc: Rec->getLoc(),
1215 Msg: "Record `" + Rec->getName() +
1216 "' does not have a ParserMatchClass!\n");
1217
1218 if (const DefInit *DI = dyn_cast<DefInit>(Val: R->getValue())) {
1219 const Record *MatchClass = DI->getDef();
1220 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1221 return CI;
1222 }
1223
1224 // No custom match class. Just use the register class.
1225 const Record *ClassRec = Rec->getValueAsDef(FieldName: "RegClass");
1226 if (!ClassRec)
1227 PrintFatalError(ErrorLoc: Rec->getLoc(),
1228 Msg: "RegisterOperand `" + Rec->getName() +
1229 "' has no associated register class!\n");
1230
1231 if (ClassRec->isSubClassOf(Name: "RegisterClassLike")) {
1232 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1233 return CI;
1234
1235 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1236 }
1237 }
1238
1239 if (Rec->isSubClassOf(Name: "RegisterClass")) {
1240 if (ClassInfo *CI = RegisterClassClasses[Rec])
1241 return CI;
1242 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1243 }
1244
1245 if (Rec->isSubClassOf(Name: "Operand")) {
1246 const Record *MatchClass = Rec->getValueAsDef(FieldName: "ParserMatchClass");
1247 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1248 return CI;
1249 } else if (Rec->isSubClassOf(Name: "RegisterClassLike")) {
1250 if (ClassInfo *CI = RegisterClassClasses[Rec])
1251 return CI;
1252 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "register class has no class info!");
1253 } else {
1254 PrintFatalError(ErrorLoc: Rec->getLoc(),
1255 Msg: "Operand `" + Rec->getName() +
1256 "' does not derive from class Operand!\n");
1257 }
1258
1259 PrintFatalError(ErrorLoc: Rec->getLoc(), Msg: "operand has no match class!");
1260}
1261
1262struct LessRegisterSet {
1263 bool operator()(const RegisterSet &LHS, const RegisterSet &RHS) const {
1264 // std::set<T> defines its own compariso "operator<", but it
1265 // performs a lexicographical comparison by T's innate comparison
1266 // for some reason. We don't want non-deterministic pointer
1267 // comparisons so use this instead.
1268 return std::lexicographical_compare(first1: LHS.begin(), last1: LHS.end(), first2: RHS.begin(),
1269 last2: RHS.end(), comp: LessRecordByID());
1270 }
1271};
1272
1273void AsmMatcherInfo::buildRegisterClasses(
1274 SmallPtrSetImpl<const Record *> &SingletonRegisters) {
1275 const auto &Registers = Target.getRegBank().getRegisters();
1276 auto &RegClassList = Target.getRegBank().getRegClasses();
1277
1278 using RegisterSetSet = std::set<RegisterSet, LessRegisterSet>;
1279
1280 // The register sets used for matching.
1281 RegisterSetSet RegisterSets;
1282
1283 // Gather the defined sets.
1284 for (const CodeGenRegisterClass &RC : RegClassList)
1285 RegisterSets.insert(
1286 x: RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1287
1288 // Add any required singleton sets.
1289 for (const Record *Rec : SingletonRegisters) {
1290 RegisterSets.insert(x: RegisterSet(&Rec, &Rec + 1));
1291 }
1292
1293 // Introduce derived sets where necessary (when a register does not determine
1294 // a unique register set class), and build the mapping of registers to the set
1295 // they should classify to.
1296 std::map<const Record *, RegisterSet> RegisterMap;
1297 for (const CodeGenRegister &CGR : Registers) {
1298 // Compute the intersection of all sets containing this register.
1299 RegisterSet ContainingSet;
1300
1301 for (const RegisterSet &RS : RegisterSets) {
1302 if (!RS.count(x: CGR.TheDef))
1303 continue;
1304
1305 if (ContainingSet.empty()) {
1306 ContainingSet = RS;
1307 continue;
1308 }
1309
1310 RegisterSet Tmp;
1311 std::set_intersection(first1: ContainingSet.begin(), last1: ContainingSet.end(),
1312 first2: RS.begin(), last2: RS.end(),
1313 result: std::inserter(x&: Tmp, i: Tmp.begin()), comp: LessRecordByID());
1314 ContainingSet = std::move(Tmp);
1315 }
1316
1317 if (!ContainingSet.empty()) {
1318 RegisterSets.insert(x: ContainingSet);
1319 RegisterMap.try_emplace(k: CGR.TheDef, args&: ContainingSet);
1320 }
1321 }
1322
1323 // Construct the register classes.
1324 std::map<RegisterSet, ClassInfo *, LessRegisterSet> RegisterSetClasses;
1325 unsigned Index = 0;
1326 for (const RegisterSet &RS : RegisterSets) {
1327 Classes.emplace_front();
1328 ClassInfo *CI = &Classes.front();
1329 CI->Kind = ClassInfo::RegisterClass0 + Index;
1330 CI->ClassName = "Reg" + utostr(X: Index);
1331 CI->Name = "MCK_Reg" + utostr(X: Index);
1332 CI->ValueName = "";
1333 CI->PredicateMethod = ""; // unused
1334 CI->RenderMethod = "addRegOperands";
1335 CI->Registers = RS;
1336 // FIXME: diagnostic type.
1337 CI->DiagnosticType = "";
1338 CI->IsOptional = false;
1339 CI->DefaultMethod = ""; // unused
1340 RegisterSetClasses.try_emplace(k: RS, args&: CI);
1341 ++Index;
1342 assert(CI->isRegisterClass());
1343 }
1344
1345 // Find the superclasses; we could compute only the subgroup lattice edges,
1346 // but there isn't really a point.
1347 for (const RegisterSet &RS : RegisterSets) {
1348 ClassInfo *CI = RegisterSetClasses[RS];
1349 for (const RegisterSet &RS2 : RegisterSets)
1350 if (RS != RS2 && llvm::includes(Range1: RS2, Range2: RS, C: LessRecordByID()))
1351 CI->SuperClasses.push_back(x: RegisterSetClasses[RS2]);
1352 }
1353
1354 // Name the register classes which correspond to a user defined RegisterClass.
1355 for (const CodeGenRegisterClass &RC : RegClassList) {
1356 // Def will be NULL for non-user defined register classes.
1357 const Record *Def = RC.getDef();
1358 if (!Def)
1359 continue;
1360 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1361 RC.getOrder().end())];
1362 if (CI->ValueName.empty()) {
1363 CI->ClassName = RC.getName();
1364 CI->Name = "MCK_" + RC.getName();
1365 CI->ValueName = RC.getName();
1366 } else {
1367 CI->ValueName = CI->ValueName + "," + RC.getName();
1368 }
1369
1370 const Init *DiagnosticType = Def->getValueInit(FieldName: "DiagnosticType");
1371 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticType))
1372 CI->DiagnosticType = SI->getValue().str();
1373
1374 const Init *DiagnosticString = Def->getValueInit(FieldName: "DiagnosticString");
1375 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticString))
1376 CI->DiagnosticString = SI->getValue().str();
1377
1378 // If we have a diagnostic string but the diagnostic type is not specified
1379 // explicitly, create an anonymous diagnostic type.
1380 if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1381 CI->DiagnosticType = RC.getName();
1382
1383 RegisterClassClasses.try_emplace(k: Def, args&: CI);
1384 assert(CI->isRegisterClass());
1385 }
1386
1387 unsigned RegClassByHwModeIndex = 0;
1388 for (const Record *ClassByHwMode : Target.getAllRegClassByHwMode()) {
1389 ClassInfo &CI = Classes.emplace_front();
1390 CI.Kind = ClassInfo::RegisterClassByHwMode0 + RegClassByHwModeIndex;
1391
1392 CI.ClassName = "RegByHwMode_" + ClassByHwMode->getName().str();
1393 CI.Name = "MCK_" + CI.ClassName;
1394 CI.ValueName = ClassByHwMode->getName();
1395 CI.RenderMethod = "addRegOperands";
1396 // FIXME: Set diagnostic type.
1397 ++RegClassByHwModeIndex;
1398
1399 assert(CI.isRegisterClassByHwMode());
1400
1401 RegisterClassClasses.try_emplace(k: ClassByHwMode, args: &CI);
1402 }
1403
1404 // Populate the map for individual registers.
1405 for (auto &It : RegisterMap)
1406 RegisterClasses[It.first] = RegisterSetClasses[It.second];
1407
1408 // Name the register classes which correspond to singleton registers.
1409 for (const Record *Rec : SingletonRegisters) {
1410 ClassInfo *CI = RegisterClasses[Rec];
1411 assert(CI && "Missing singleton register class info!");
1412
1413 if (CI->ValueName.empty()) {
1414 CI->ClassName = Rec->getName().str();
1415 CI->Name = "MCK_" + Rec->getName().str();
1416 CI->ValueName = Rec->getName().str();
1417 } else {
1418 CI->ValueName = CI->ValueName + "," + Rec->getName().str();
1419 }
1420 }
1421}
1422
1423void AsmMatcherInfo::buildOperandClasses() {
1424 ArrayRef<const Record *> AsmOperands =
1425 Records.getAllDerivedDefinitions(ClassName: "AsmOperandClass");
1426
1427 // Pre-populate AsmOperandClasses map.
1428 for (const Record *Rec : AsmOperands) {
1429 Classes.emplace_front();
1430 AsmOperandClasses[Rec] = &Classes.front();
1431 }
1432
1433 unsigned Index = 0;
1434 for (const Record *Rec : AsmOperands) {
1435 ClassInfo *CI = AsmOperandClasses[Rec];
1436 CI->Kind = ClassInfo::UserClass0 + Index;
1437
1438 const ListInit *Supers = Rec->getValueAsListInit(FieldName: "SuperClasses");
1439 for (const Init *I : Supers->getElements()) {
1440 const DefInit *DI = dyn_cast<DefInit>(Val: I);
1441 if (!DI) {
1442 PrintError(ErrorLoc: Rec->getLoc(), Msg: "Invalid super class reference!");
1443 continue;
1444 }
1445
1446 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1447 if (!SC)
1448 PrintError(ErrorLoc: Rec->getLoc(), Msg: "Invalid super class reference!");
1449 else
1450 CI->SuperClasses.push_back(x: SC);
1451 }
1452 CI->ClassName = Rec->getValueAsString(FieldName: "Name").str();
1453 CI->Name = "MCK_" + CI->ClassName;
1454 CI->ValueName = Rec->getName().str();
1455
1456 // Get or construct the predicate method name.
1457 const Init *PMName = Rec->getValueInit(FieldName: "PredicateMethod");
1458 if (const StringInit *SI = dyn_cast<StringInit>(Val: PMName)) {
1459 CI->PredicateMethod = SI->getValue().str();
1460 } else {
1461 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1462 CI->PredicateMethod = "is" + CI->ClassName;
1463 }
1464
1465 // Get or construct the render method name.
1466 const Init *RMName = Rec->getValueInit(FieldName: "RenderMethod");
1467 if (const StringInit *SI = dyn_cast<StringInit>(Val: RMName)) {
1468 CI->RenderMethod = SI->getValue().str();
1469 } else {
1470 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1471 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1472 }
1473
1474 // Get the parse method name or leave it as empty.
1475 const Init *PRMName = Rec->getValueInit(FieldName: "ParserMethod");
1476 if (const StringInit *SI = dyn_cast<StringInit>(Val: PRMName))
1477 CI->ParserMethod = SI->getValue().str();
1478
1479 // Get the diagnostic type and string or leave them as empty.
1480 const Init *DiagnosticType = Rec->getValueInit(FieldName: "DiagnosticType");
1481 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticType))
1482 CI->DiagnosticType = SI->getValue().str();
1483 const Init *DiagnosticString = Rec->getValueInit(FieldName: "DiagnosticString");
1484 if (const StringInit *SI = dyn_cast<StringInit>(Val: DiagnosticString))
1485 CI->DiagnosticString = SI->getValue().str();
1486 // If we have a DiagnosticString, we need a DiagnosticType for use within
1487 // the matcher.
1488 if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1489 CI->DiagnosticType = CI->ClassName;
1490
1491 const Init *IsOptional = Rec->getValueInit(FieldName: "IsOptional");
1492 if (const BitInit *BI = dyn_cast<BitInit>(Val: IsOptional))
1493 CI->IsOptional = BI->getValue();
1494
1495 // Get or construct the default method name.
1496 const Init *DMName = Rec->getValueInit(FieldName: "DefaultMethod");
1497 if (const StringInit *SI = dyn_cast<StringInit>(Val: DMName)) {
1498 CI->DefaultMethod = SI->getValue().str();
1499 } else {
1500 assert(isa<UnsetInit>(DMName) && "Unexpected DefaultMethod field!");
1501 CI->DefaultMethod = "default" + CI->ClassName + "Operands";
1502 }
1503
1504 ++Index;
1505 }
1506}
1507
1508AsmMatcherInfo::AsmMatcherInfo(const Record *asmParser,
1509 const CodeGenTarget &target,
1510 const RecordKeeper &records)
1511 : Records(records), AsmParser(asmParser), Target(target) {}
1512
1513/// buildOperandMatchInfo - Build the necessary information to handle user
1514/// defined operand parsing methods.
1515void AsmMatcherInfo::buildOperandMatchInfo() {
1516 /// Map containing a mask with all operands indices that can be found for
1517 /// that class inside a instruction.
1518 using OpClassMaskTy = std::map<ClassInfo *, unsigned, deref<std::less<>>>;
1519 OpClassMaskTy OpClassMask;
1520
1521 bool CallCustomParserForAllOperands =
1522 AsmParser->getValueAsBit(FieldName: "CallCustomParserForAllOperands");
1523 for (const auto &MI : Matchables) {
1524 OpClassMask.clear();
1525
1526 // Keep track of all operands of this instructions which belong to the
1527 // same class.
1528 unsigned NumOptionalOps = 0;
1529 for (const auto &[Idx, Op] : enumerate(First&: MI->AsmOperands)) {
1530 if (CallCustomParserForAllOperands || !Op.Class->ParserMethod.empty()) {
1531 unsigned &OperandMask = OpClassMask[Op.Class];
1532 OperandMask |= maskTrailingOnes<unsigned>(N: NumOptionalOps + 1)
1533 << (Idx - NumOptionalOps);
1534 }
1535 if (Op.Class->IsOptional)
1536 ++NumOptionalOps;
1537 }
1538
1539 // Generate operand match info for each mnemonic/operand class pair.
1540 for (const auto [CI, OpMask] : OpClassMask) {
1541 OperandMatchInfo.push_back(
1542 x: OperandMatchEntry::create(mi: MI.get(), ci: CI, opMask: OpMask));
1543 }
1544 }
1545}
1546
1547void AsmMatcherInfo::buildInfo() {
1548 // Build information about all of the AssemblerPredicates.
1549 SubtargetFeaturesInfoVec SubtargetFeaturePairs =
1550 SubtargetFeatureInfo::getAll(Records);
1551 SubtargetFeatures.insert(first: SubtargetFeaturePairs.begin(),
1552 last: SubtargetFeaturePairs.end());
1553#ifndef NDEBUG
1554 for (const auto &Pair : SubtargetFeatures)
1555 LLVM_DEBUG(Pair.second.dump());
1556#endif // NDEBUG
1557
1558 bool HasMnemonicFirst = AsmParser->getValueAsBit(FieldName: "HasMnemonicFirst");
1559 bool ReportMultipleNearMisses =
1560 AsmParser->getValueAsBit(FieldName: "ReportMultipleNearMisses");
1561
1562 // Parse the instructions; we need to do this first so that we can gather the
1563 // singleton register classes.
1564 SmallPtrSet<const Record *, 16> SingletonRegisters;
1565 unsigned VariantCount = Target.getAsmParserVariantCount();
1566 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1567 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
1568 StringRef CommentDelimiter =
1569 AsmVariant->getValueAsString(FieldName: "CommentDelimiter");
1570 AsmVariantInfo Variant;
1571 Variant.RegisterPrefix = AsmVariant->getValueAsString(FieldName: "RegisterPrefix");
1572 Variant.TokenizingCharacters =
1573 AsmVariant->getValueAsString(FieldName: "TokenizingCharacters");
1574 Variant.SeparatorCharacters =
1575 AsmVariant->getValueAsString(FieldName: "SeparatorCharacters");
1576 Variant.BreakCharacters = AsmVariant->getValueAsString(FieldName: "BreakCharacters");
1577 Variant.Name = AsmVariant->getValueAsString(FieldName: "Name");
1578 Variant.AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
1579
1580 for (const CodeGenInstruction *CGI : Target.getInstructions()) {
1581 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1582 // filter the set of instructions we consider.
1583 if (!CGI->getName().starts_with(Prefix: MatchPrefix))
1584 continue;
1585
1586 // Ignore "codegen only" instructions.
1587 if (CGI->TheDef->getValueAsBit(FieldName: "isCodeGenOnly"))
1588 continue;
1589
1590 // Ignore instructions for different instructions
1591 StringRef V = CGI->TheDef->getValueAsString(FieldName: "AsmVariantName");
1592 if (!V.empty() && V != Variant.Name)
1593 continue;
1594
1595 auto II = std::make_unique<MatchableInfo>(args: *CGI);
1596
1597 II->initialize(Info: *this, SingletonRegisters, Variant, HasMnemonicFirst);
1598
1599 // Ignore instructions which shouldn't be matched and diagnose invalid
1600 // instruction definitions with an error.
1601 if (!II->validate(CommentDelimiter, IsAlias: false))
1602 continue;
1603
1604 Matchables.push_back(x: std::move(II));
1605 }
1606
1607 // Parse all of the InstAlias definitions and stick them in the list of
1608 // matchables.
1609 for (const Record *InstAlias :
1610 Records.getAllDerivedDefinitions(ClassName: "InstAlias")) {
1611 auto Alias = std::make_unique<CodeGenInstAlias>(args&: InstAlias, args: Target);
1612
1613 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1614 // filter the set of instruction aliases we consider, based on the target
1615 // instruction.
1616 if (!Alias->ResultInst->getName().starts_with(Prefix: MatchPrefix))
1617 continue;
1618
1619 StringRef V = Alias->TheDef->getValueAsString(FieldName: "AsmVariantName");
1620 if (!V.empty() && V != Variant.Name)
1621 continue;
1622
1623 auto II = std::make_unique<MatchableInfo>(args: std::move(Alias));
1624
1625 II->initialize(Info: *this, SingletonRegisters, Variant, HasMnemonicFirst);
1626
1627 // Validate the alias definitions.
1628 II->validate(CommentDelimiter, IsAlias: true);
1629
1630 Matchables.push_back(x: std::move(II));
1631 }
1632 }
1633
1634 // Build info for the register classes.
1635 buildRegisterClasses(SingletonRegisters);
1636
1637 // Build info for the user defined assembly operand classes.
1638 buildOperandClasses();
1639
1640 // Build the information about matchables, now that we have fully formed
1641 // classes.
1642 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1643 for (auto &II : Matchables) {
1644 // Parse the tokens after the mnemonic.
1645 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1646 // don't precompute the loop bound, i.e., cannot use range based for loop
1647 // here.
1648 for (size_t Idx = 0; Idx < II->AsmOperands.size(); ++Idx) {
1649 MatchableInfo::AsmOperand &Op = II->AsmOperands[Idx];
1650 StringRef Token = Op.Token;
1651 // Check for singleton registers.
1652 if (const Record *RegRecord = Op.SingletonReg) {
1653 Op.Class = RegisterClasses[RegRecord];
1654 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1655 "Unexpected class for singleton register");
1656 continue;
1657 }
1658
1659 // Check for simple tokens.
1660 if (Token[0] != '$') {
1661 Op.Class = getTokenClass(Token);
1662 continue;
1663 }
1664
1665 if (Token.size() > 1 && isdigit(Token[1])) {
1666 Op.Class = getTokenClass(Token);
1667 continue;
1668 }
1669
1670 // Otherwise this is an operand reference.
1671 StringRef OperandName;
1672 if (Token[1] == '{')
1673 OperandName = Token.substr(Start: 2, N: Token.size() - 3);
1674 else
1675 OperandName = Token.substr(Start: 1);
1676
1677 if (isa<const CodeGenInstruction *>(Val: II->DefRec))
1678 buildInstructionOperandReference(II: II.get(), OpName: OperandName, AsmOpIdx: Idx);
1679 else
1680 buildAliasOperandReference(II: II.get(), OpName: OperandName, Op);
1681 }
1682
1683 if (isa<const CodeGenInstruction *>(Val: II->DefRec)) {
1684 II->buildInstructionResultOperands();
1685 // If the instruction has a two-operand alias, build up the
1686 // matchable here. We'll add them in bulk at the end to avoid
1687 // confusing this loop.
1688 StringRef Constraint =
1689 II->TheDef->getValueAsString(FieldName: "TwoOperandAliasConstraint");
1690 if (Constraint != "") {
1691 // Start by making a copy of the original matchable.
1692 auto AliasII = std::make_unique<MatchableInfo>(args&: *II);
1693
1694 // Adjust it to be a two-operand alias.
1695 AliasII->formTwoOperandAlias(Constraint);
1696
1697 // Add the alias to the matchables list.
1698 NewMatchables.push_back(x: std::move(AliasII));
1699 }
1700 } else {
1701 // FIXME: The tied operands checking is not yet integrated with the
1702 // framework for reporting multiple near misses. To prevent invalid
1703 // formats from being matched with an alias if a tied-operands check
1704 // would otherwise have disallowed it, we just disallow such constructs
1705 // in TableGen completely.
1706 II->buildAliasResultOperands(AliasConstraintsAreChecked: !ReportMultipleNearMisses);
1707 }
1708 }
1709 if (!NewMatchables.empty())
1710 Matchables.insert(position: Matchables.end(),
1711 first: std::make_move_iterator(i: NewMatchables.begin()),
1712 last: std::make_move_iterator(i: NewMatchables.end()));
1713
1714 // Process token alias definitions and set up the associated superclass
1715 // information.
1716 for (const Record *Rec : Records.getAllDerivedDefinitions(ClassName: "TokenAlias")) {
1717 ClassInfo *FromClass = getTokenClass(Token: Rec->getValueAsString(FieldName: "FromToken"));
1718 ClassInfo *ToClass = getTokenClass(Token: Rec->getValueAsString(FieldName: "ToToken"));
1719 if (FromClass == ToClass)
1720 PrintFatalError(ErrorLoc: Rec->getLoc(),
1721 Msg: "error: Destination value identical to source value.");
1722 FromClass->SuperClasses.push_back(x: ToClass);
1723 }
1724
1725 // Reorder classes so that classes precede super classes.
1726 Classes.sort();
1727
1728#ifdef EXPENSIVE_CHECKS
1729 // Verify that the table is sorted and operator < works transitively.
1730 for (auto I = Classes.begin(), E = Classes.end(); I != E; ++I) {
1731 for (auto J = I; J != E; ++J) {
1732 assert(!(*J < *I));
1733 assert(I == J || !J->isSubsetOf(*I));
1734 }
1735 }
1736#endif
1737}
1738
1739/// buildInstructionOperandReference - The specified operand is a reference to a
1740/// named operand such as $src. Resolve the Class and OperandInfo pointers.
1741void AsmMatcherInfo::buildInstructionOperandReference(MatchableInfo *II,
1742 StringRef OperandName,
1743 unsigned AsmOpIdx) {
1744 const CodeGenInstruction &CGI = *cast<const CodeGenInstruction *>(Val&: II->DefRec);
1745 const CGIOperandList &Operands = CGI.Operands;
1746 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1747
1748 // Map this token to an operand.
1749 std::optional<unsigned> Idx = Operands.findOperandNamed(Name: OperandName);
1750 if (!Idx)
1751 PrintFatalError(ErrorLoc: II->TheDef->getLoc(),
1752 Msg: "error: unable to find operand: '" + OperandName + "'");
1753 // If the instruction operand has multiple suboperands, but the parser
1754 // match class for the asm operand is still the default "ImmAsmOperand",
1755 // then handle each suboperand separately.
1756 if (Op->SubOpIdx == -1 && Operands[*Idx].MINumOperands > 1) {
1757 const Record *Rec = Operands[*Idx].Rec;
1758 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1759 const Record *MatchClass = Rec->getValueAsDef(FieldName: "ParserMatchClass");
1760 if (MatchClass && MatchClass->getValueAsString(FieldName: "Name") == "Imm") {
1761 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1762 StringRef Token = Op->Token; // save this in case Op gets moved
1763 for (unsigned SI = 1, SE = Operands[*Idx].MINumOperands; SI != SE; ++SI) {
1764 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1765 NewAsmOp.SubOpIdx = SI;
1766 II->AsmOperands.insert(I: II->AsmOperands.begin() + AsmOpIdx + SI,
1767 Elt: NewAsmOp);
1768 }
1769 // Replace Op with first suboperand.
1770 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1771 Op->SubOpIdx = 0;
1772 }
1773 }
1774
1775 // Set up the operand class.
1776 Op->Class = getOperandClass(OI: Operands[*Idx], SubOpIdx: Op->SubOpIdx);
1777 Op->OrigSrcOpName = OperandName;
1778
1779 // If the named operand is tied, canonicalize it to the untied operand.
1780 // For example, something like:
1781 // (outs GPR:$dst), (ins GPR:$src)
1782 // with an asmstring of
1783 // "inc $src"
1784 // we want to canonicalize to:
1785 // "inc $dst"
1786 // so that we know how to provide the $dst operand when filling in the result.
1787 int OITied = -1;
1788 if (Operands[*Idx].MINumOperands == 1)
1789 OITied = Operands[*Idx].getTiedRegister();
1790 if (OITied != -1) {
1791 // The tied operand index is an MIOperand index, find the operand that
1792 // contains it.
1793 auto [OpIdx, SubopIdx] = Operands.getSubOperandNumber(Op: OITied);
1794 OperandName = Operands[OpIdx].Name;
1795 Op->SubOpIdx = SubopIdx;
1796 }
1797
1798 Op->SrcOpName = OperandName;
1799}
1800
1801/// buildAliasOperandReference - When parsing an operand reference out of the
1802/// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1803/// operand reference is by looking it up in the result pattern definition.
1804void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1805 StringRef OperandName,
1806 MatchableInfo::AsmOperand &Op) {
1807 const CodeGenInstAlias &CGA = *cast<const CodeGenInstAlias *>(Val&: II->DefRec);
1808
1809 // Set up the operand class.
1810 for (const auto &[ResultOp, SubOpIdx] :
1811 zip_equal(t: CGA.ResultOperands, u: CGA.ResultInstOperandIndex)) {
1812 if (ResultOp.isRecord() && ResultOp.getName() == OperandName) {
1813 // It's safe to go with the first one we find, because CodeGenInstAlias
1814 // validates that all operands with the same name have the same record.
1815 Op.SubOpIdx = SubOpIdx.second;
1816 // Use the match class from the Alias definition, not the
1817 // destination instruction, as we may have an immediate that's
1818 // being munged by the match class.
1819 Op.Class = getOperandClass(Rec: ResultOp.getRecord(), SubOpIdx: Op.SubOpIdx);
1820 Op.SrcOpName = OperandName;
1821 Op.OrigSrcOpName = OperandName;
1822 return;
1823 }
1824 }
1825
1826 PrintFatalError(ErrorLoc: II->TheDef->getLoc(),
1827 Msg: "error: unable to find operand: '" + OperandName + "'");
1828}
1829
1830void MatchableInfo::buildInstructionResultOperands() {
1831 const CodeGenInstruction *ResultInst = getResultInst();
1832
1833 // Loop over all operands of the result instruction, determining how to
1834 // populate them.
1835 for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
1836 // If this is a tied operand, just copy from the previously handled operand.
1837 int TiedOp = -1;
1838 if (OpInfo.MINumOperands == 1)
1839 TiedOp = OpInfo.getTiedRegister();
1840 if (TiedOp != -1) {
1841 int TiedSrcOperand = findAsmOperandOriginallyNamed(N: OpInfo.Name);
1842 if (TiedSrcOperand != -1 &&
1843 ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand)
1844 ResOperands.push_back(Elt: ResOperand::getTiedOp(
1845 TiedOperandNum: TiedOp, SrcOperand1: ResOperands[TiedOp].AsmOperandNum, SrcOperand2: TiedSrcOperand));
1846 else
1847 ResOperands.push_back(Elt: ResOperand::getTiedOp(TiedOperandNum: TiedOp, SrcOperand1: 0, SrcOperand2: 0));
1848 continue;
1849 }
1850
1851 int SrcOperand = findAsmOperandNamed(N: OpInfo.Name);
1852 if (OpInfo.Name.empty() || SrcOperand == -1) {
1853 // This may happen for operands that are tied to a suboperand of a
1854 // complex operand. Simply use a dummy value here; nobody should
1855 // use this operand slot.
1856 // FIXME: The long term goal is for the MCOperand list to not contain
1857 // tied operands at all.
1858 ResOperands.push_back(Elt: ResOperand::getImmOp(Val: 0));
1859 continue;
1860 }
1861
1862 // Check if the one AsmOperand populates the entire operand.
1863 unsigned NumOperands = OpInfo.MINumOperands;
1864 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1865 ResOperands.push_back(Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand, NumOperands));
1866 continue;
1867 }
1868
1869 // Add a separate ResOperand for each suboperand.
1870 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1871 assert(AsmOperands[SrcOperand + AI].SubOpIdx == (int)AI &&
1872 AsmOperands[SrcOperand + AI].SrcOpName == OpInfo.Name &&
1873 "unexpected AsmOperands for suboperands");
1874 ResOperands.push_back(Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand + AI, NumOperands: 1));
1875 }
1876 }
1877}
1878
1879void MatchableInfo::buildAliasResultOperands(bool AliasConstraintsAreChecked) {
1880 const CodeGenInstAlias &CGA = *cast<const CodeGenInstAlias *>(Val&: DefRec);
1881 const CodeGenInstruction *ResultInst = getResultInst();
1882
1883 // Map of: $reg -> #lastref
1884 // where $reg is the name of the operand in the asm string
1885 // where #lastref is the last processed index where $reg was referenced in
1886 // the asm string.
1887 SmallDenseMap<StringRef, int> OperandRefs;
1888
1889 // Loop over all operands of the result instruction, determining how to
1890 // populate them.
1891 unsigned AliasOpNo = 0;
1892 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1893 for (const auto &[Idx, OpInfo] : enumerate(First: ResultInst->Operands)) {
1894 // If this is a tied operand, just copy from the previously handled operand.
1895 int TiedOp = -1;
1896 if (OpInfo.MINumOperands == 1)
1897 TiedOp = OpInfo.getTiedRegister();
1898 if (TiedOp != -1) {
1899 unsigned SrcOp1 = 0;
1900 unsigned SrcOp2 = 0;
1901
1902 // If an operand has been specified twice in the asm string,
1903 // add the two source operand's indices to the TiedOp so that
1904 // at runtime the 'tied' constraint is checked.
1905 if (ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand) {
1906 SrcOp1 = ResOperands[TiedOp].AsmOperandNum;
1907
1908 // Find the next operand (similarly named operand) in the string.
1909 StringRef Name = AsmOperands[SrcOp1].SrcOpName;
1910 auto Insert = OperandRefs.try_emplace(Key: Name, Args&: SrcOp1);
1911 SrcOp2 = findAsmOperandNamed(N: Name, LastIdx: Insert.first->second);
1912
1913 // Not updating the record in OperandRefs will cause TableGen
1914 // to fail with an error at the end of this function.
1915 if (AliasConstraintsAreChecked)
1916 Insert.first->second = SrcOp2;
1917
1918 // In case it only has one reference in the asm string,
1919 // it doesn't need to be checked for tied constraints.
1920 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2;
1921 }
1922
1923 // If the alias operand is of a different operand class, we only want
1924 // to benefit from the tied-operands check and just match the operand
1925 // as a normal, but not copy the original (TiedOp) to the result
1926 // instruction. We do this by passing -1 as the tied operand to copy.
1927 if (OpInfo.Rec->getName() !=
1928 ResultInst->Operands[TiedOp].Rec->getName()) {
1929 SrcOp1 = ResOperands[TiedOp].AsmOperandNum;
1930 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1931 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1932 SrcOp2 = findAsmOperand(N: Name, SubOpIdx: SubIdx);
1933 ResOperands.push_back(
1934 Elt: ResOperand::getTiedOp(TiedOperandNum: (unsigned)-1, SrcOperand1: SrcOp1, SrcOperand2: SrcOp2));
1935 } else {
1936 ResOperands.push_back(Elt: ResOperand::getTiedOp(TiedOperandNum: TiedOp, SrcOperand1: SrcOp1, SrcOperand2: SrcOp2));
1937 continue;
1938 }
1939 }
1940
1941 // Handle all the suboperands for this operand.
1942 StringRef OpName = OpInfo.Name;
1943 for (; AliasOpNo < LastOpNo &&
1944 CGA.ResultInstOperandIndex[AliasOpNo].first == Idx;
1945 ++AliasOpNo) {
1946 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1947
1948 // Find out what operand from the asmparser that this MCInst operand
1949 // comes from.
1950 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1951 case CodeGenInstAlias::ResultOperand::K_Record: {
1952 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1953 int SrcOperand = findAsmOperand(N: Name, SubOpIdx: SubIdx);
1954 if (SrcOperand == -1)
1955 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1956 Msg: "Instruction '" + TheDef->getName() +
1957 "' has operand '" + OpName +
1958 "' that doesn't appear in asm string!");
1959
1960 // Add it to the operand references. If it is added a second time, the
1961 // record won't be updated and it will fail later on.
1962 OperandRefs.try_emplace(Key: Name, Args&: SrcOperand);
1963
1964 unsigned NumOperands = (SubIdx == -1 ? OpInfo.MINumOperands : 1);
1965 ResOperands.push_back(
1966 Elt: ResOperand::getRenderedOp(AsmOpNum: SrcOperand, NumOperands));
1967 break;
1968 }
1969 case CodeGenInstAlias::ResultOperand::K_Imm: {
1970 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1971 ResOperands.push_back(Elt: ResOperand::getImmOp(Val: ImmVal));
1972 break;
1973 }
1974 case CodeGenInstAlias::ResultOperand::K_Reg: {
1975 const Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1976 ResOperands.push_back(Elt: ResOperand::getRegOp(Reg));
1977 break;
1978 }
1979 }
1980 }
1981 }
1982
1983 // Check that operands are not repeated more times than is supported.
1984 for (auto &T : OperandRefs) {
1985 if (T.second != -1 && findAsmOperandNamed(N: T.first, LastIdx: T.second) != -1)
1986 PrintFatalError(ErrorLoc: TheDef->getLoc(),
1987 Msg: "Operand '" + T.first + "' can never be matched");
1988 }
1989}
1990
1991static unsigned
1992getConverterOperandID(const std::string &Name,
1993 SmallSetVector<CachedHashString, 16> &Table,
1994 bool &IsNew) {
1995 IsNew = Table.insert(X: CachedHashString(Name));
1996
1997 unsigned ID = IsNew ? Table.size() - 1 : find(Range&: Table, Val: Name) - Table.begin();
1998
1999 assert(ID < Table.size());
2000
2001 return ID;
2002}
2003
2004static unsigned
2005emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
2006 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
2007 bool HasMnemonicFirst, bool HasOptionalOperands,
2008 raw_ostream &OS) {
2009 SmallSetVector<CachedHashString, 16> OperandConversionKinds;
2010 SmallSetVector<CachedHashString, 16> InstructionConversionKinds;
2011 std::vector<std::vector<uint8_t>> ConversionTable;
2012 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
2013
2014 // TargetOperandClass - This is the target's operand class, like X86Operand.
2015 std::string TargetOperandClass = Target.getName().str() + "Operand";
2016
2017 // Write the convert function to a separate stream, so we can drop it after
2018 // the enum. We'll build up the conversion handlers for the individual
2019 // operand types opportunistically as we encounter them.
2020 std::string ConvertFnBody;
2021 raw_string_ostream CvtOS(ConvertFnBody);
2022 // Start the unified conversion function.
2023 if (HasOptionalOperands) {
2024 CvtOS << "void " << Target.getName() << ClassName << "::\n"
2025 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
2026 << "unsigned Opcode,\n"
2027 << " const OperandVector &Operands,\n"
2028 << " const SmallBitVector &OptionalOperandsMask,\n"
2029 << " ArrayRef<unsigned> DefaultsOffset) {\n";
2030 } else {
2031 CvtOS << "void " << Target.getName() << ClassName << "::\n"
2032 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
2033 << "unsigned Opcode,\n"
2034 << " const OperandVector &Operands) {\n";
2035 }
2036 CvtOS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
2037 CvtOS << " const uint8_t *Converter = ConversionTable[Kind];\n";
2038 CvtOS << " Inst.setOpcode(Opcode);\n";
2039 CvtOS << " for (const uint8_t *p = Converter; *p; p += 2) {\n";
2040 if (HasOptionalOperands) {
2041 // When optional operands are involved, formal and actual operand indices
2042 // may differ. Map the former to the latter by subtracting the number of
2043 // absent optional operands.
2044 // FIXME: This is not an operand index in the CVT_Tied case
2045 CvtOS << " unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];\n";
2046 } else {
2047 CvtOS << " unsigned OpIdx = *(p + 1);\n";
2048 }
2049 CvtOS << " switch (*p) {\n";
2050 CvtOS << " default: llvm_unreachable(\"invalid conversion entry!\");\n";
2051 CvtOS << " case CVT_Reg:\n";
2052 CvtOS << " static_cast<" << TargetOperandClass
2053 << " &>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";
2054 CvtOS << " break;\n";
2055 CvtOS << " case CVT_Tied: {\n";
2056 CvtOS << " assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -\n";
2057 CvtOS
2058 << " std::begin(TiedAsmOperandTable)) &&\n";
2059 CvtOS << " \"Tied operand not found\");\n";
2060 CvtOS << " unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];\n";
2061 CvtOS << " if (TiedResOpnd != (uint8_t)-1)\n";
2062 CvtOS << " Inst.addOperand(Inst.getOperand(TiedResOpnd));\n";
2063 CvtOS << " break;\n";
2064 CvtOS << " }\n";
2065
2066 std::string OperandFnBody;
2067 raw_string_ostream OpOS(OperandFnBody);
2068 // Start the operand number lookup function.
2069 OpOS << "void " << Target.getName() << ClassName << "::\n"
2070 << "convertToMapAndConstraints(unsigned Kind,\n";
2071 OpOS.indent(NumSpaces: 27);
2072 OpOS << "const OperandVector &Operands) {\n"
2073 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
2074 << " unsigned NumMCOperands = 0;\n"
2075 << " const uint8_t *Converter = ConversionTable[Kind];\n"
2076 << " for (const uint8_t *p = Converter; *p; p += 2) {\n"
2077 << " switch (*p) {\n"
2078 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
2079 << " case CVT_Reg:\n"
2080 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2081 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
2082 << " ++NumMCOperands;\n"
2083 << " break;\n"
2084 << " case CVT_Tied:\n"
2085 << " ++NumMCOperands;\n"
2086 << " break;\n";
2087
2088 // Pre-populate the operand conversion kinds with the standard always
2089 // available entries.
2090 OperandConversionKinds.insert(X: CachedHashString("CVT_Done"));
2091 OperandConversionKinds.insert(X: CachedHashString("CVT_Reg"));
2092 OperandConversionKinds.insert(X: CachedHashString("CVT_Tied"));
2093 enum { CVT_Done, CVT_Reg, CVT_Tied };
2094
2095 // Map of e.g. <0, 2, 3> -> "Tie_0_2_3" enum label.
2096 std::map<std::tuple<uint8_t, uint8_t, uint8_t>, std::string>
2097 TiedOperandsEnumMap;
2098
2099 for (auto &II : Infos) {
2100 // Check if we have a custom match function.
2101 StringRef AsmMatchConverter =
2102 II->getResultInst()->TheDef->getValueAsString(FieldName: "AsmMatchConverter");
2103 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
2104 std::string Signature = ("ConvertCustom_" + AsmMatchConverter).str();
2105 II->ConversionFnKind = Signature;
2106
2107 // Check if we have already generated this signature.
2108 if (!InstructionConversionKinds.insert(X: CachedHashString(Signature)))
2109 continue;
2110
2111 // Remember this converter for the kind enum.
2112 unsigned KindID = OperandConversionKinds.size();
2113 OperandConversionKinds.insert(
2114 X: CachedHashString("CVT_" + getEnumNameForToken(Str: AsmMatchConverter)));
2115
2116 // Add the converter row for this instruction.
2117 ConversionTable.emplace_back();
2118 ConversionTable.back().push_back(x: KindID);
2119 ConversionTable.back().push_back(x: CVT_Done);
2120
2121 // Add the handler to the conversion driver function.
2122 CvtOS << " case CVT_" << getEnumNameForToken(Str: AsmMatchConverter)
2123 << ":\n"
2124 << " " << AsmMatchConverter << "(Inst, Operands);\n"
2125 << " break;\n";
2126
2127 // FIXME: Handle the operand number lookup for custom match functions.
2128 continue;
2129 }
2130
2131 // Build the conversion function signature.
2132 std::string Signature = "Convert";
2133
2134 std::vector<uint8_t> ConversionRow;
2135
2136 // Compute the convert enum and the case body.
2137 MaxRowLength = std::max(a: MaxRowLength, b: II->ResOperands.size() * 2 + 1);
2138
2139 for (const auto &[Idx, OpInfo] : enumerate(First&: II->ResOperands)) {
2140 // Generate code to populate each result operand.
2141 switch (OpInfo.Kind) {
2142 case MatchableInfo::ResOperand::RenderAsmOperand: {
2143 // This comes from something we parsed.
2144 const MatchableInfo::AsmOperand &Op =
2145 II->AsmOperands[OpInfo.AsmOperandNum];
2146
2147 // Registers are always converted the same, don't duplicate the
2148 // conversion function based on them.
2149 Signature += "__";
2150 std::string Class;
2151 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
2152 Signature += Class;
2153 Signature += utostr(X: OpInfo.MINumOperands);
2154 Signature += "_" + itostr(X: OpInfo.AsmOperandNum);
2155
2156 // Add the conversion kind, if necessary, and get the associated ID
2157 // the index of its entry in the vector).
2158 std::string Name =
2159 "CVT_" +
2160 (Op.Class->isRegisterClass() ? "Reg" : Op.Class->RenderMethod);
2161 if (Op.Class->IsOptional) {
2162 // For optional operands we must also care about DefaultMethod
2163 assert(HasOptionalOperands);
2164 Name += "_" + Op.Class->DefaultMethod;
2165 }
2166 Name = getEnumNameForToken(Str: Name);
2167
2168 bool IsNewConverter = false;
2169 unsigned ID =
2170 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2171
2172 // Add the operand entry to the instruction kind conversion row.
2173 ConversionRow.push_back(x: ID);
2174 ConversionRow.push_back(x: OpInfo.AsmOperandNum + HasMnemonicFirst);
2175
2176 if (!IsNewConverter)
2177 break;
2178
2179 // This is a new operand kind. Add a handler for it to the
2180 // converter driver.
2181 CvtOS << " case " << Name << ":\n";
2182 if (Op.Class->IsOptional) {
2183 // If optional operand is not present in actual instruction then we
2184 // should call its DefaultMethod before RenderMethod
2185 assert(HasOptionalOperands);
2186 CvtOS << " if (OptionalOperandsMask[*(p + 1)]) {\n"
2187 << " " << Op.Class->DefaultMethod << "()"
2188 << "->" << Op.Class->RenderMethod << "(Inst, "
2189 << OpInfo.MINumOperands << ");\n"
2190 << " } else {\n"
2191 << " static_cast<" << TargetOperandClass
2192 << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod
2193 << "(Inst, " << OpInfo.MINumOperands << ");\n"
2194 << " }\n";
2195 } else {
2196 CvtOS << " static_cast<" << TargetOperandClass
2197 << " &>(*Operands[OpIdx])." << Op.Class->RenderMethod
2198 << "(Inst, " << OpInfo.MINumOperands << ");\n";
2199 }
2200 CvtOS << " break;\n";
2201
2202 // Add a handler for the operand number lookup.
2203 OpOS << " case " << Name << ":\n"
2204 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
2205
2206 if (Op.Class->isRegisterClass())
2207 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
2208 else
2209 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
2210 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
2211 << " break;\n";
2212 break;
2213 }
2214 case MatchableInfo::ResOperand::TiedOperand: {
2215 // If this operand is tied to a previous one, just copy the MCInst
2216 // operand from the earlier one.We can only tie single MCOperand values.
2217 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
2218 uint8_t TiedOp = OpInfo.TiedOperands.ResOpnd;
2219 uint8_t SrcOp1 = OpInfo.TiedOperands.SrcOpnd1Idx + HasMnemonicFirst;
2220 uint8_t SrcOp2 = OpInfo.TiedOperands.SrcOpnd2Idx + HasMnemonicFirst;
2221 assert((Idx > TiedOp || TiedOp == (uint8_t)-1) &&
2222 "Tied operand precedes its target!");
2223 auto TiedTupleName = std::string("Tie") + utostr(X: TiedOp) + '_' +
2224 utostr(X: SrcOp1) + '_' + utostr(X: SrcOp2);
2225 Signature += "__" + TiedTupleName;
2226 ConversionRow.push_back(x: CVT_Tied);
2227 ConversionRow.push_back(x: TiedOp);
2228 ConversionRow.push_back(x: SrcOp1);
2229 ConversionRow.push_back(x: SrcOp2);
2230
2231 // Also create an 'enum' for this combination of tied operands.
2232 auto Key = std::tuple(TiedOp, SrcOp1, SrcOp2);
2233 TiedOperandsEnumMap.emplace(args&: Key, args&: TiedTupleName);
2234 break;
2235 }
2236 case MatchableInfo::ResOperand::ImmOperand: {
2237 int64_t Val = OpInfo.ImmVal;
2238 std::string Ty = "imm_" + itostr(X: Val);
2239 Ty = getEnumNameForToken(Str: Ty);
2240 Signature += "__" + Ty;
2241
2242 std::string Name = "CVT_" + Ty;
2243 bool IsNewConverter = false;
2244 unsigned ID =
2245 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2246 // Add the operand entry to the instruction kind conversion row.
2247 ConversionRow.push_back(x: ID);
2248 ConversionRow.push_back(x: 0);
2249
2250 if (!IsNewConverter)
2251 break;
2252
2253 CvtOS << " case " << Name << ":\n"
2254 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
2255 << " break;\n";
2256
2257 OpOS << " case " << Name << ":\n"
2258 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2259 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
2260 << " ++NumMCOperands;\n"
2261 << " break;\n";
2262 break;
2263 }
2264 case MatchableInfo::ResOperand::RegOperand: {
2265 std::string Reg, Name;
2266 if (!OpInfo.Register) {
2267 Name = "reg0";
2268 Reg = "0";
2269 } else {
2270 Reg = getQualifiedName(R: OpInfo.Register);
2271 Name = "reg" + OpInfo.Register->getName().str();
2272 }
2273 Signature += "__" + Name;
2274 Name = "CVT_" + Name;
2275 bool IsNewConverter = false;
2276 unsigned ID =
2277 getConverterOperandID(Name, Table&: OperandConversionKinds, IsNew&: IsNewConverter);
2278 // Add the operand entry to the instruction kind conversion row.
2279 ConversionRow.push_back(x: ID);
2280 ConversionRow.push_back(x: 0);
2281
2282 if (!IsNewConverter)
2283 break;
2284 CvtOS << " case " << Name << ":\n"
2285 << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
2286 << " break;\n";
2287
2288 OpOS << " case " << Name << ":\n"
2289 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2290 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
2291 << " ++NumMCOperands;\n"
2292 << " break;\n";
2293 }
2294 }
2295 }
2296
2297 // If there were no operands, add to the signature to that effect
2298 if (Signature == "Convert")
2299 Signature += "_NoOperands";
2300
2301 II->ConversionFnKind = Signature;
2302
2303 // Save the signature. If we already have it, don't add a new row
2304 // to the table.
2305 if (!InstructionConversionKinds.insert(X: CachedHashString(Signature)))
2306 continue;
2307
2308 // Add the row to the table.
2309 ConversionTable.push_back(x: std::move(ConversionRow));
2310 }
2311
2312 // Finish up the converter driver function.
2313 CvtOS << " }\n }\n}\n\n";
2314
2315 // Finish up the operand number lookup function.
2316 OpOS << " }\n }\n}\n\n";
2317
2318 // Output a static table for tied operands.
2319 if (TiedOperandsEnumMap.size()) {
2320 // The number of tied operand combinations will be small in practice,
2321 // but just add the assert to be sure.
2322 assert(TiedOperandsEnumMap.size() <= 254 &&
2323 "Too many tied-operand combinations to reference with "
2324 "an 8bit offset from the conversion table, where index "
2325 "'255' is reserved as operand not to be copied.");
2326
2327 OS << "enum {\n";
2328 for (auto &KV : TiedOperandsEnumMap) {
2329 OS << " " << KV.second << ",\n";
2330 }
2331 OS << "};\n\n";
2332
2333 OS << "static const uint8_t TiedAsmOperandTable[][3] = {\n";
2334 for (auto &KV : TiedOperandsEnumMap) {
2335 OS << " /* " << KV.second << " */ { " << utostr(X: std::get<0>(t: KV.first))
2336 << ", " << utostr(X: std::get<1>(t: KV.first)) << ", "
2337 << utostr(X: std::get<2>(t: KV.first)) << " },\n";
2338 }
2339 OS << "};\n\n";
2340 } else {
2341 OS << "static const uint8_t TiedAsmOperandTable[][3] = "
2342 "{ /* empty */ {0, 0, 0} };\n\n";
2343 }
2344
2345 OS << "namespace {\n";
2346
2347 // Output the operand conversion kind enum.
2348 OS << "enum OperatorConversionKind {\n";
2349 for (const auto &Converter : OperandConversionKinds)
2350 OS << " " << Converter << ",\n";
2351 OS << " CVT_NUM_CONVERTERS\n";
2352 OS << "};\n\n";
2353
2354 // Output the instruction conversion kind enum.
2355 OS << "enum InstructionConversionKind {\n";
2356 for (const auto &Signature : InstructionConversionKinds)
2357 OS << " " << Signature << ",\n";
2358 OS << " CVT_NUM_SIGNATURES\n";
2359 OS << "};\n\n";
2360
2361 OS << "} // end anonymous namespace\n\n";
2362
2363 // Output the conversion table.
2364 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2365 << MaxRowLength << "] = {\n";
2366
2367 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2368 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2369 OS << " // " << InstructionConversionKinds[Row] << "\n";
2370 OS << " { ";
2371 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2) {
2372 const auto &OCK = OperandConversionKinds[ConversionTable[Row][i]];
2373 OS << OCK << ", ";
2374 if (OCK != CachedHashString("CVT_Tied")) {
2375 OS << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2376 continue;
2377 }
2378
2379 // For a tied operand, emit a reference to the TiedAsmOperandTable
2380 // that contains the operand to copy, and the parsed operands to
2381 // check for their tied constraints.
2382 auto Key = std::tuple((uint8_t)ConversionTable[Row][i + 1],
2383 (uint8_t)ConversionTable[Row][i + 2],
2384 (uint8_t)ConversionTable[Row][i + 3]);
2385 auto TiedOpndEnum = TiedOperandsEnumMap.find(x: Key);
2386 assert(TiedOpndEnum != TiedOperandsEnumMap.end() &&
2387 "No record for tied operand pair");
2388 OS << TiedOpndEnum->second << ", ";
2389 i += 2;
2390 }
2391 OS << "CVT_Done },\n";
2392 }
2393
2394 OS << "};\n\n";
2395
2396 // Spit out the conversion driver function.
2397 OS << ConvertFnBody;
2398
2399 // Spit out the operand number lookup function.
2400 OS << OperandFnBody;
2401
2402 return ConversionTable.size();
2403}
2404
2405/// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2406static void emitMatchClassEnumeration(CodeGenTarget &Target,
2407 std::forward_list<ClassInfo> &Infos,
2408 raw_ostream &OS) {
2409 OS << "namespace {\n\n";
2410
2411 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2412 << "/// instruction matching.\n";
2413 OS << "enum MatchClassKind {\n";
2414 OS << " InvalidMatchClass = 0,\n";
2415 OS << " OptionalMatchClass = 1,\n";
2416 ClassInfo::ClassInfoKind LastKind = ClassInfo::Token;
2417 StringRef LastName = "OptionalMatchClass";
2418 for (const auto &CI : Infos) {
2419 if (LastKind == ClassInfo::Token && CI.Kind != ClassInfo::Token) {
2420 OS << " MCK_LAST_TOKEN = " << LastName << ",\n";
2421 } else if (LastKind < ClassInfo::RegisterClassByHwMode0 &&
2422 CI.Kind >= ClassInfo::RegisterClassByHwMode0) {
2423 OS << " MCK_LAST_REGISTER = " << LastName << ",\n";
2424 } else if (LastKind < ClassInfo::UserClass0 &&
2425 CI.Kind >= ClassInfo::UserClass0) {
2426 OS << " MCK_LAST_REGCLASS_BY_HWMODE = " << LastName << ",\n";
2427 }
2428
2429 LastKind = (ClassInfo::ClassInfoKind)CI.Kind;
2430 LastName = CI.Name;
2431
2432 OS << " " << CI.Name << ", // ";
2433 if (CI.Kind == ClassInfo::Token) {
2434 OS << "'" << CI.ValueName << "'\n";
2435 } else if (CI.isRegisterClass()) {
2436 if (!CI.ValueName.empty())
2437 OS << "register class '" << CI.ValueName << "'\n";
2438 else
2439 OS << "derived register class\n";
2440 } else if (CI.isRegisterClassByHwMode()) {
2441 OS << "register class by hwmode\n";
2442 } else {
2443 OS << "user defined class '" << CI.ValueName << "'\n";
2444 }
2445 }
2446 OS << " NumMatchClassKinds\n";
2447 OS << "};\n\n";
2448
2449 OS << "} // end anonymous namespace\n\n";
2450}
2451
2452/// emitMatchClassDiagStrings - Emit a function to get the diagnostic text to be
2453/// used when an assembly operand does not match the expected operand class.
2454static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info,
2455 raw_ostream &OS) {
2456 // If the target does not use DiagnosticString for any operands, don't emit
2457 // an unused function.
2458 if (llvm::all_of(Range&: Info.Classes, P: [](const ClassInfo &CI) {
2459 return CI.DiagnosticString.empty();
2460 }))
2461 return;
2462
2463 OS << "static const char *getMatchKindDiag(" << Info.Target.getName()
2464 << "AsmParser::" << Info.Target.getName()
2465 << "MatchResultTy MatchResult) {\n";
2466 OS << " switch (MatchResult) {\n";
2467
2468 for (const auto &CI : Info.Classes) {
2469 if (!CI.DiagnosticString.empty()) {
2470 assert(!CI.DiagnosticType.empty() &&
2471 "DiagnosticString set without DiagnosticType");
2472 OS << " case " << Info.Target.getName() << "AsmParser::Match_"
2473 << CI.DiagnosticType << ":\n";
2474 OS << " return \"" << CI.DiagnosticString << "\";\n";
2475 }
2476 }
2477
2478 OS << " default:\n";
2479 OS << " return nullptr;\n";
2480
2481 OS << " }\n";
2482 OS << "}\n\n";
2483}
2484
2485static void emitRegisterMatchErrorFunc(AsmMatcherInfo &Info, raw_ostream &OS) {
2486 OS << "static unsigned getDiagKindFromRegisterClass(MatchClassKind "
2487 "RegisterClass) {\n";
2488 if (none_of(Range&: Info.Classes, P: [](const ClassInfo &CI) {
2489 return CI.isRegisterClass() && !CI.DiagnosticType.empty();
2490 })) {
2491 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2492 } else {
2493 OS << " switch (RegisterClass) {\n";
2494 for (const auto &CI : Info.Classes) {
2495 if (CI.isRegisterClass() && !CI.DiagnosticType.empty()) {
2496 OS << " case " << CI.Name << ":\n";
2497 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2498 << CI.DiagnosticType << ";\n";
2499 }
2500 }
2501
2502 OS << " default:\n";
2503 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2504
2505 OS << " }\n";
2506 }
2507 OS << "}\n\n";
2508}
2509
2510/// emitValidateOperandClass - Emit the function to validate an operand class.
2511static void emitValidateOperandClass(const CodeGenTarget &Target,
2512 AsmMatcherInfo &Info, raw_ostream &OS) {
2513 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2514 << "MatchClassKind Kind, const MCSubtargetInfo &STI) {\n";
2515 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2516 << Info.Target.getName() << "Operand &)GOp;\n";
2517
2518 // The InvalidMatchClass is not to match any operand.
2519 OS << " if (Kind == InvalidMatchClass)\n";
2520 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2521
2522 // Check for Token operands first.
2523 // FIXME: Use a more specific diagnostic type.
2524 OS << " if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)\n";
2525 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2526 << " MCTargetAsmParser::Match_Success :\n"
2527 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2528
2529 // Check the user classes. We don't care what order since we're only
2530 // actually matching against one of them.
2531 OS << " switch (Kind) {\n"
2532 " default: break;\n";
2533 for (const auto &CI : Info.Classes) {
2534 if (!CI.isUserClass())
2535 continue;
2536
2537 OS << " case " << CI.Name << ": {\n";
2538 OS << " DiagnosticPredicate DP(Operand." << CI.PredicateMethod
2539 << "());\n";
2540 OS << " if (DP.isMatch())\n";
2541 OS << " return MCTargetAsmParser::Match_Success;\n";
2542 if (!CI.DiagnosticType.empty()) {
2543 OS << " if (DP.isNearMatch())\n";
2544 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2545 << CI.DiagnosticType << ";\n";
2546 OS << " break;\n";
2547 } else {
2548 OS << " break;\n";
2549 }
2550 OS << " }\n";
2551 }
2552 OS << " } // end switch (Kind)\n\n";
2553
2554 const CodeGenRegBank &RegBank = Target.getRegBank();
2555 ArrayRef<const Record *> RegClassesByHwMode = Target.getAllRegClassByHwMode();
2556 unsigned NumClassesByHwMode = RegClassesByHwMode.size();
2557
2558 if (!RegClassesByHwMode.empty()) {
2559 OS << " if (Operand.isReg() && Kind > MCK_LAST_REGISTER &&"
2560 " Kind <= MCK_LAST_REGCLASS_BY_HWMODE) {\n";
2561
2562 const CodeGenHwModes &CGH = Target.getHwModes();
2563 unsigned NumModes = CGH.getNumModeIds();
2564
2565 OS << indent(4)
2566 << "static constexpr MatchClassKind RegClassByHwModeMatchTable["
2567 << NumModes << "][" << RegClassesByHwMode.size() << "] = {\n";
2568
2569 // TODO: If the instruction predicates can statically resolve which hwmode,
2570 // directly match the register class
2571 for (unsigned M = 0; M < NumModes; ++M) {
2572 OS << indent(6) << "{ // " << CGH.getModeName(Id: M, /*IncludeDefault=*/true)
2573 << '\n';
2574 for (unsigned I = 0; I != NumClassesByHwMode; ++I) {
2575 const Record *Class = RegClassesByHwMode[I];
2576 const HwModeSelect &ModeSelect = CGH.getHwModeSelect(R: Class);
2577
2578 auto FoundMode =
2579 find_if(Range: ModeSelect.Items, P: [=](const HwModeSelect::PairType P) {
2580 return P.first == M;
2581 });
2582
2583 if (FoundMode == ModeSelect.Items.end()) {
2584 OS << indent(8) << "InvalidMatchClass, // Missing mode entry for "
2585 << Class->getName() << "\n";
2586 } else {
2587 const CodeGenRegisterClass *RegClass =
2588 RegBank.getRegClass(FoundMode->second);
2589 const ClassInfo *CI =
2590 Info.RegisterClassClasses.at(k: RegClass->getDef());
2591 OS << indent(8) << CI->Name << ", // " << Class->getName() << "\n";
2592 }
2593 }
2594
2595 OS << indent(6) << "},\n";
2596 }
2597
2598 OS << indent(4) << "};\n\n";
2599
2600 OS << indent(4)
2601 << "static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == "
2602 << NumClassesByHwMode << ");\n";
2603
2604 OS << indent(4)
2605 << "const unsigned HwMode = "
2606 "STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);\n"
2607 "Kind = RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER "
2608 "+ 1)];\n"
2609 " }\n\n";
2610 }
2611
2612 // Check for register operands, including sub-classes.
2613 const auto &Regs = RegBank.getRegisters();
2614 StringRef Namespace = Regs.front().TheDef->getValueAsString(FieldName: "Namespace");
2615 SmallVector<StringRef> Table(1 + Regs.size(), "InvalidMatchClass");
2616 for (const auto &RC : Info.RegisterClasses) {
2617 const auto &Reg = Target.getRegBank().getReg(RC.first);
2618 Table[Reg->EnumValue] = RC.second->Name;
2619 }
2620 OS << " if (Operand.isReg()) {\n";
2621 OS << " static constexpr uint16_t Table[" << Namespace
2622 << "::NUM_TARGET_REGS] = {\n";
2623 for (auto &MatchClassName : Table)
2624 OS << " " << MatchClassName << ",\n";
2625 OS << " };\n\n";
2626 OS << " MCRegister Reg = Operand.getReg();\n";
2627 OS << " MatchClassKind OpKind = Reg.isPhysical() ? "
2628 "(MatchClassKind)Table[Reg.id()] : InvalidMatchClass;\n";
2629 OS << " return isSubclass(OpKind, Kind) ? "
2630 << "(unsigned)MCTargetAsmParser::Match_Success :\n "
2631 << " getDiagKindFromRegisterClass(Kind);\n }\n\n";
2632
2633 // Expected operand is a register, but actual is not.
2634 OS << " if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)\n";
2635 OS << " return getDiagKindFromRegisterClass(Kind);\n\n";
2636
2637 // Generic fallthrough match failure case for operands that don't have
2638 // specialized diagnostic types.
2639 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2640 OS << "}\n\n";
2641}
2642
2643/// emitIsSubclass - Emit the subclass predicate function.
2644static void emitIsSubclass(CodeGenTarget &Target,
2645 std::forward_list<ClassInfo> &Infos,
2646 raw_ostream &OS) {
2647 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2648 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2649 OS << " if (A == B)\n";
2650 OS << " return true;\n\n";
2651
2652 // TODO: Use something like SequenceToOffsetTable to allow sequences to
2653 // overlap in this table.
2654 SmallVector<bool> SuperClassData;
2655
2656 OS << " [[maybe_unused]] static constexpr struct {\n";
2657 OS << " uint32_t Offset;\n";
2658 OS << " uint16_t Start;\n";
2659 OS << " uint16_t Length;\n";
2660 OS << " } Table[] = {\n";
2661 OS << " {0, 0, 0},\n"; // InvalidMatchClass
2662 OS << " {0, 0, 0},\n"; // OptionalMatchClass
2663 for (const auto &A : Infos) {
2664 SmallVector<bool> SuperClasses;
2665 SuperClasses.push_back(Elt: false); // InvalidMatchClass
2666 SuperClasses.push_back(Elt: A.IsOptional); // OptionalMatchClass
2667 for (const auto &B : Infos)
2668 SuperClasses.push_back(Elt: &A != &B && A.isSubsetOf(RHS: B));
2669
2670 // Trim leading and trailing zeros.
2671 auto End = find_if(Range: reverse(C&: SuperClasses), P: [](bool B) { return B; }).base();
2672 auto Start =
2673 std::find_if(first: SuperClasses.begin(), last: End, pred: [](bool B) { return B; });
2674
2675 unsigned Offset = SuperClassData.size();
2676 SuperClassData.append(in_start: Start, in_end: End);
2677
2678 OS << " {" << Offset << ", " << (Start - SuperClasses.begin()) << ", "
2679 << (End - Start) << "},\n";
2680 }
2681 OS << " };\n\n";
2682
2683 if (SuperClassData.empty()) {
2684 OS << " return false;\n";
2685 } else {
2686 // Dump the boolean data packed into bytes.
2687 SuperClassData.append(NumInputs: -SuperClassData.size() % 8, Elt: false);
2688 OS << " static constexpr uint8_t Data[] = {\n";
2689 for (unsigned I = 0, E = SuperClassData.size(); I < E; I += 8) {
2690 unsigned Byte = 0;
2691 for (unsigned J = 0; J < 8; ++J)
2692 Byte |= (unsigned)SuperClassData[I + J] << J;
2693 OS << formatv(Fmt: " {:X2},\n", Vals&: Byte);
2694 }
2695 OS << " };\n\n";
2696
2697 OS << " auto &Entry = Table[A];\n";
2698 OS << " unsigned Idx = B - Entry.Start;\n";
2699 OS << " if (Idx >= Entry.Length)\n";
2700 OS << " return false;\n";
2701 OS << " Idx += Entry.Offset;\n";
2702 OS << " return (Data[Idx / 8] >> (Idx % 8)) & 1;\n";
2703 }
2704 OS << "}\n\n";
2705}
2706
2707/// emitMatchTokenString - Emit the function to match a token string to the
2708/// appropriate match class value.
2709static void emitMatchTokenString(CodeGenTarget &Target,
2710 std::forward_list<ClassInfo> &Infos,
2711 raw_ostream &OS) {
2712 // Construct the match list.
2713 std::vector<StringMatcher::StringPair> Matches;
2714 for (const auto &CI : Infos) {
2715 if (CI.Kind == ClassInfo::Token)
2716 Matches.emplace_back(args: CI.ValueName, args: "return " + CI.Name + ";");
2717 }
2718
2719 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2720
2721 StringMatcher("Name", Matches, OS).Emit();
2722
2723 OS << " return InvalidMatchClass;\n";
2724 OS << "}\n\n";
2725}
2726
2727/// emitMatchRegisterName - Emit the function to match a string to the target
2728/// specific register enum.
2729static void emitMatchRegisterName(const CodeGenTarget &Target,
2730 const Record *AsmParser, raw_ostream &OS) {
2731 // Construct the match list.
2732 std::vector<StringMatcher::StringPair> Matches;
2733 const auto &Regs = Target.getRegBank().getRegisters();
2734 std::string Namespace =
2735 Regs.front().TheDef->getValueAsString(FieldName: "Namespace").str();
2736 for (const CodeGenRegister &Reg : Regs) {
2737 StringRef AsmName = Reg.TheDef->getValueAsString(FieldName: "AsmName");
2738 if (AsmName.empty())
2739 continue;
2740
2741 Matches.emplace_back(args: AsmName.str(), args: "return " + Namespace +
2742 "::" + Reg.getName().str() + ';');
2743 }
2744
2745 OS << "static MCRegister MatchRegisterName(StringRef Name) {\n";
2746
2747 bool IgnoreDuplicates =
2748 AsmParser->getValueAsBit(FieldName: "AllowDuplicateRegisterNames");
2749 StringMatcher("Name", Matches, OS).Emit(Indent: 0, IgnoreDuplicates);
2750
2751 OS << " return " << Namespace << "::NoRegister;\n";
2752 OS << "}\n\n";
2753}
2754
2755/// Emit the function to match a string to the target
2756/// specific register enum.
2757static void emitMatchRegisterAltName(const CodeGenTarget &Target,
2758 const Record *AsmParser, raw_ostream &OS) {
2759 // Construct the match list.
2760 std::vector<StringMatcher::StringPair> Matches;
2761 const auto &Regs = Target.getRegBank().getRegisters();
2762 std::string Namespace =
2763 Regs.front().TheDef->getValueAsString(FieldName: "Namespace").str();
2764 for (const CodeGenRegister &Reg : Regs) {
2765 for (StringRef AltName : Reg.TheDef->getValueAsListOfStrings(FieldName: "AltNames")) {
2766 AltName = AltName.trim();
2767
2768 // don't handle empty alternative names
2769 if (AltName.empty())
2770 continue;
2771
2772 Matches.emplace_back(args: AltName.str(), args: "return " + Namespace +
2773 "::" + Reg.getName().str() + ';');
2774 }
2775 }
2776
2777 OS << "static MCRegister MatchRegisterAltName(StringRef Name) {\n";
2778
2779 bool IgnoreDuplicates =
2780 AsmParser->getValueAsBit(FieldName: "AllowDuplicateRegisterNames");
2781 StringMatcher("Name", Matches, OS).Emit(Indent: 0, IgnoreDuplicates);
2782
2783 OS << " return " << Namespace << "::NoRegister;\n";
2784 OS << "}\n\n";
2785}
2786
2787/// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2788static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2789 // Get the set of diagnostic types from all of the operand classes.
2790 std::set<StringRef> Types;
2791 for (const auto &OpClassEntry : Info.AsmOperandClasses) {
2792 if (!OpClassEntry.second->DiagnosticType.empty())
2793 Types.insert(x: OpClassEntry.second->DiagnosticType);
2794 }
2795 for (const auto &OpClassEntry : Info.RegisterClassClasses) {
2796 if (!OpClassEntry.second->DiagnosticType.empty())
2797 Types.insert(x: OpClassEntry.second->DiagnosticType);
2798 }
2799
2800 if (Types.empty())
2801 return;
2802
2803 // Now emit the enum entries.
2804 for (StringRef Type : Types)
2805 OS << " Match_" << Type << ",\n";
2806 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2807}
2808
2809/// emitGetSubtargetFeatureName - Emit the helper function to get the
2810/// user-level name for a subtarget feature.
2811static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2812 OS << "// User-level names for subtarget features that participate in\n"
2813 << "// instruction matching.\n"
2814 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2815 if (!Info.SubtargetFeatures.empty()) {
2816 OS << " switch(Val) {\n";
2817 for (const SubtargetFeatureInfo &SFI :
2818 make_second_range(c&: Info.SubtargetFeatures)) {
2819 // FIXME: Totally just a placeholder name to get the algorithm working.
2820 OS << " case " << SFI.getEnumBitName() << ": return \""
2821 << SFI.TheDef->getValueAsString(FieldName: "PredicateName") << "\";\n";
2822 }
2823 OS << " default: return \"(unknown)\";\n";
2824 OS << " }\n";
2825 } else {
2826 // Nothing to emit, so skip the switch
2827 OS << " return \"(unknown)\";\n";
2828 }
2829 OS << "}\n\n";
2830}
2831
2832static std::string GetAliasRequiredFeatures(const Record *R,
2833 const AsmMatcherInfo &Info) {
2834 std::string Result;
2835
2836 ListSeparator LS(" && ");
2837 for (const Record *RF : R->getValueAsListOfDefs(FieldName: "Predicates")) {
2838 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(Def: RF);
2839 if (!F)
2840 PrintFatalError(ErrorLoc: R->getLoc(),
2841 Msg: "Predicate '" + RF->getName() +
2842 "' is not marked as an AssemblerPredicate!");
2843 Result += LS;
2844 Result += "Features.test(" + F->getEnumBitName() + ')';
2845 }
2846
2847 return Result;
2848}
2849
2850static void
2851emitMnemonicAliasVariant(raw_ostream &OS, const AsmMatcherInfo &Info,
2852 ArrayRef<const Record *> Aliases, unsigned Indent = 0,
2853 StringRef AsmParserVariantName = StringRef()) {
2854 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2855 // iteration order of the map is stable.
2856 std::map<std::string, std::vector<const Record *>> AliasesFromMnemonic;
2857
2858 for (const Record *R : Aliases) {
2859 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2860 StringRef AsmVariantName = R->getValueAsString(FieldName: "AsmVariantName");
2861 if (AsmVariantName != AsmParserVariantName)
2862 continue;
2863 AliasesFromMnemonic[R->getValueAsString(FieldName: "FromMnemonic").lower()].push_back(
2864 x: R);
2865 }
2866 if (AliasesFromMnemonic.empty())
2867 return;
2868
2869 // Process each alias a "from" mnemonic at a time, building the code executed
2870 // by the string remapper.
2871 std::vector<StringMatcher::StringPair> Cases;
2872 for (const auto &AliasEntry : AliasesFromMnemonic) {
2873 // Loop through each alias and emit code that handles each case. If there
2874 // are two instructions without predicates, emit an error. If there is one,
2875 // emit it last.
2876 std::string MatchCode;
2877 int AliasWithNoPredicate = -1;
2878
2879 ArrayRef<const Record *> ToVec = AliasEntry.second;
2880 for (const auto &[Idx, R] : enumerate(First&: ToVec)) {
2881 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2882
2883 // If this unconditionally matches, remember it for later and diagnose
2884 // duplicates.
2885 if (FeatureMask.empty()) {
2886 if (AliasWithNoPredicate != -1 &&
2887 R->getValueAsString(FieldName: "ToMnemonic") !=
2888 ToVec[AliasWithNoPredicate]->getValueAsString(FieldName: "ToMnemonic")) {
2889 // We can't have two different aliases from the same mnemonic with no
2890 // predicate.
2891 PrintError(
2892 ErrorLoc: ToVec[AliasWithNoPredicate]->getLoc(),
2893 Msg: "two different MnemonicAliases with the same 'from' mnemonic!");
2894 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "this is the other MnemonicAlias.");
2895 }
2896
2897 AliasWithNoPredicate = Idx;
2898 continue;
2899 }
2900 if (R->getValueAsString(FieldName: "ToMnemonic") == AliasEntry.first)
2901 PrintFatalError(ErrorLoc: R->getLoc(), Msg: "MnemonicAlias to the same string");
2902
2903 if (!MatchCode.empty())
2904 MatchCode += "else ";
2905 MatchCode += "if (" + FeatureMask + ")\n";
2906 MatchCode += " Mnemonic = \"";
2907 MatchCode += R->getValueAsString(FieldName: "ToMnemonic").lower();
2908 MatchCode += "\";\n";
2909 }
2910
2911 if (AliasWithNoPredicate != -1) {
2912 const Record *R = ToVec[AliasWithNoPredicate];
2913 if (!MatchCode.empty())
2914 MatchCode += "else\n ";
2915 MatchCode += "Mnemonic = \"";
2916 MatchCode += R->getValueAsString(FieldName: "ToMnemonic").lower();
2917 MatchCode += "\";\n";
2918 }
2919
2920 MatchCode += "return;";
2921
2922 Cases.emplace_back(args: AliasEntry.first, args&: MatchCode);
2923 }
2924 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2925}
2926
2927/// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2928/// emit a function for them and return true, otherwise return false.
2929static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2930 CodeGenTarget &Target) {
2931 // Ignore aliases when match-prefix is set.
2932 if (!MatchPrefix.empty())
2933 return false;
2934
2935 ArrayRef<const Record *> Aliases =
2936 Info.getRecords().getAllDerivedDefinitions(ClassName: "MnemonicAlias");
2937 if (Aliases.empty())
2938 return false;
2939
2940 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2941 "const FeatureBitset &Features, unsigned VariantID) {\n";
2942 unsigned VariantCount = Target.getAsmParserVariantCount();
2943 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2944 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
2945 int AsmParserVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
2946 StringRef AsmParserVariantName = AsmVariant->getValueAsString(FieldName: "Name");
2947
2948 // If the variant doesn't have a name, defer to the emitMnemonicAliasVariant
2949 // call after the loop.
2950 if (AsmParserVariantName.empty()) {
2951 assert(VariantCount == 1 && "Multiple variants should each be named");
2952 continue;
2953 }
2954
2955 if (VC == 0)
2956 OS << " switch (VariantID) {\n";
2957 OS << " case " << AsmParserVariantNo << ":\n";
2958 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2959 AsmParserVariantName);
2960 OS << " break;\n";
2961
2962 if (VC == VariantCount - 1)
2963 OS << " }\n";
2964 }
2965
2966 // Emit aliases that apply to all variants.
2967 emitMnemonicAliasVariant(OS, Info, Aliases);
2968
2969 OS << "}\n\n";
2970
2971 return true;
2972}
2973
2974static void
2975emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2976 const AsmMatcherInfo &Info, StringRef ClassName,
2977 const StringToOffsetTable &StringTable,
2978 unsigned MaxMnemonicIndex, unsigned MaxFeaturesIndex,
2979 bool HasMnemonicFirst, const Record &AsmParser) {
2980 unsigned MaxMask = 0;
2981 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2982 MaxMask |= OMI.OperandMask;
2983 }
2984
2985 // Emit the static custom operand parsing table;
2986 OS << "namespace {\n";
2987 OS << " struct OperandMatchEntry {\n";
2988 OS << " " << getMinimalTypeForRange(Range: MaxMnemonicIndex) << " Mnemonic;\n";
2989 OS << " " << getMinimalTypeForRange(Range: MaxMask) << " OperandMask;\n";
2990 OS << " "
2991 << getMinimalTypeForRange(
2992 Range: std::distance(first: Info.Classes.begin(), last: Info.Classes.end()) +
2993 2 /* Include 'InvalidMatchClass' and 'OptionalMatchClass' */)
2994 << " Class;\n";
2995 OS << " " << getMinimalTypeForRange(Range: MaxFeaturesIndex)
2996 << " RequiredFeaturesIdx;\n\n";
2997 OS << " StringRef getMnemonic() const {\n";
2998 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2999 OS << " MnemonicTable[Mnemonic]);\n";
3000 OS << " }\n";
3001 OS << " };\n\n";
3002
3003 OS << " // Predicate for searching for an opcode.\n";
3004 OS << " struct LessOpcodeOperand {\n";
3005 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
3006 OS << " return LHS.getMnemonic() < RHS;\n";
3007 OS << " }\n";
3008 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
3009 OS << " return LHS < RHS.getMnemonic();\n";
3010 OS << " }\n";
3011 OS << " bool operator()(const OperandMatchEntry &LHS,";
3012 OS << " const OperandMatchEntry &RHS) {\n";
3013 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
3014 OS << " }\n";
3015 OS << " };\n";
3016
3017 OS << "} // end anonymous namespace\n\n";
3018
3019 OS << "static const OperandMatchEntry OperandMatchTable["
3020 << Info.OperandMatchInfo.size() << "] = {\n";
3021
3022 OS << " /* Operand List Mnemonic, Mask, Operand Class, Features */\n";
3023 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
3024 const MatchableInfo &II = *OMI.MI;
3025
3026 OS << " { ";
3027
3028 // Store a pascal-style length byte in the mnemonic.
3029 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.lower();
3030 OS << *StringTable.GetStringOffset(Str: LenMnemonic) << " /* " << II.Mnemonic
3031 << " */, ";
3032
3033 OS << OMI.OperandMask;
3034 OS << " /* ";
3035 ListSeparator LS;
3036 for (int i = 0, e = 31; i != e; ++i)
3037 if (OMI.OperandMask & (1 << i))
3038 OS << LS << i;
3039 OS << " */, ";
3040
3041 OS << OMI.CI->Name;
3042
3043 // Write the required features mask.
3044 OS << ", AMFBS";
3045 if (II.RequiredFeatures.empty())
3046 OS << "_None";
3047 else
3048 for (const auto &F : II.RequiredFeatures)
3049 OS << '_' << F->TheDef->getName();
3050
3051 OS << " },\n";
3052 }
3053 OS << "};\n\n";
3054
3055 // Emit the operand class switch to call the correct custom parser for
3056 // the found operand class.
3057 OS << "ParseStatus " << Target.getName() << ClassName << "::\n"
3058 << "tryCustomParseOperand(OperandVector"
3059 << " &Operands,\n unsigned MCK) {\n\n"
3060 << " switch(MCK) {\n";
3061
3062 for (const auto &CI : Info.Classes) {
3063 if (CI.ParserMethod.empty())
3064 continue;
3065 OS << " case " << CI.Name << ":\n"
3066 << " return " << CI.ParserMethod << "(Operands);\n";
3067 }
3068
3069 OS << " default:\n";
3070 OS << " return ParseStatus::NoMatch;\n";
3071 OS << " }\n";
3072 OS << " return ParseStatus::NoMatch;\n";
3073 OS << "}\n\n";
3074
3075 // Emit the static custom operand parser. This code is very similar with
3076 // the other matcher. Also use MatchResultTy here just in case we go for
3077 // a better error handling.
3078 OS << "ParseStatus " << Target.getName() << ClassName << "::\n"
3079 << "MatchOperandParserImpl(OperandVector"
3080 << " &Operands,\n StringRef Mnemonic,\n"
3081 << " bool ParseForAllFeatures) {\n";
3082
3083 // Emit code to get the available features.
3084 OS << " // Get the current feature set.\n";
3085 OS << " const FeatureBitset &AvailableFeatures = "
3086 "getAvailableFeatures();\n\n";
3087
3088 OS << " // Get the next operand index.\n";
3089 OS << " unsigned NextOpNum = Operands.size()"
3090 << (HasMnemonicFirst ? " - 1" : "") << ";\n";
3091
3092 // Emit code to search the table.
3093 OS << " // Search the table.\n";
3094 if (HasMnemonicFirst) {
3095 OS << " auto MnemonicRange =\n";
3096 OS << " std::equal_range(std::begin(OperandMatchTable), "
3097 "std::end(OperandMatchTable),\n";
3098 OS << " Mnemonic, LessOpcodeOperand());\n\n";
3099 } else {
3100 OS << " auto MnemonicRange = std::pair(std::begin(OperandMatchTable),"
3101 " std::end(OperandMatchTable));\n";
3102 OS << " if (!Mnemonic.empty())\n";
3103 OS << " MnemonicRange =\n";
3104 OS << " std::equal_range(std::begin(OperandMatchTable), "
3105 "std::end(OperandMatchTable),\n";
3106 OS << " Mnemonic, LessOpcodeOperand());\n\n";
3107 }
3108
3109 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3110 OS << " return ParseStatus::NoMatch;\n\n";
3111
3112 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
3113 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
3114
3115 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3116 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
3117
3118 // Emit check that the required features are available.
3119 OS << " // check if the available features match\n";
3120 OS << " const FeatureBitset &RequiredFeatures = "
3121 "FeatureBitsets[it->RequiredFeaturesIdx];\n";
3122 OS << " if (!ParseForAllFeatures && (AvailableFeatures & "
3123 "RequiredFeatures) != RequiredFeatures)\n";
3124 OS << " continue;\n\n";
3125
3126 // Emit check to ensure the operand number matches.
3127 OS << " // check if the operand in question has a custom parser.\n";
3128 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
3129 OS << " continue;\n\n";
3130
3131 // Emit call to the custom parser method
3132 StringRef ParserName = AsmParser.getValueAsString(FieldName: "OperandParserMethod");
3133 if (ParserName.empty())
3134 ParserName = "tryCustomParseOperand";
3135 OS << " // call custom parse method to handle the operand\n";
3136 OS << " ParseStatus Result = " << ParserName << "(Operands, it->Class);\n";
3137 OS << " if (!Result.isNoMatch())\n";
3138 OS << " return Result;\n";
3139 OS << " }\n\n";
3140
3141 OS << " // Okay, we had no match.\n";
3142 OS << " return ParseStatus::NoMatch;\n";
3143 OS << "}\n\n";
3144}
3145
3146static void emitAsmTiedOperandConstraints(CodeGenTarget &Target,
3147 AsmMatcherInfo &Info, raw_ostream &OS,
3148 bool HasOptionalOperands) {
3149 std::string AsmParserName =
3150 Info.AsmParser->getValueAsString(FieldName: "AsmParserClassName").str();
3151 OS << "static bool ";
3152 OS << "checkAsmTiedOperandConstraints(const " << Target.getName()
3153 << AsmParserName << "&AsmParser,\n";
3154 OS << " unsigned Kind, const OperandVector "
3155 "&Operands,\n";
3156 if (HasOptionalOperands)
3157 OS << " ArrayRef<unsigned> DefaultsOffset,\n";
3158 OS << " uint64_t &ErrorInfo) {\n";
3159 OS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
3160 OS << " const uint8_t *Converter = ConversionTable[Kind];\n";
3161 OS << " for (const uint8_t *p = Converter; *p; p += 2) {\n";
3162 OS << " switch (*p) {\n";
3163 OS << " case CVT_Tied: {\n";
3164 OS << " unsigned OpIdx = *(p + 1);\n";
3165 OS << " assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";
3166 OS << " std::begin(TiedAsmOperandTable)) &&\n";
3167 OS << " \"Tied operand not found\");\n";
3168 OS << " unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];\n";
3169 OS << " unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];\n";
3170 if (HasOptionalOperands) {
3171 // When optional operands are involved, formal and actual operand indices
3172 // may differ. Map the former to the latter by subtracting the number of
3173 // absent optional operands.
3174 OS << " OpndNum1 = OpndNum1 - DefaultsOffset[OpndNum1];\n";
3175 OS << " OpndNum2 = OpndNum2 - DefaultsOffset[OpndNum2];\n";
3176 }
3177 OS << " if (OpndNum1 != OpndNum2) {\n";
3178 OS << " auto &SrcOp1 = Operands[OpndNum1];\n";
3179 OS << " auto &SrcOp2 = Operands[OpndNum2];\n";
3180 OS << " if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {\n";
3181 OS << " ErrorInfo = OpndNum2;\n";
3182 OS << " return false;\n";
3183 OS << " }\n";
3184 OS << " }\n";
3185 OS << " break;\n";
3186 OS << " }\n";
3187 OS << " default:\n";
3188 OS << " break;\n";
3189 OS << " }\n";
3190 OS << " }\n";
3191 OS << " return true;\n";
3192 OS << "}\n\n";
3193}
3194
3195static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target,
3196 unsigned VariantCount) {
3197 OS << "static std::string " << Target.getName()
3198 << "MnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,"
3199 << " unsigned VariantID) {\n";
3200 if (!VariantCount)
3201 OS << " return \"\";";
3202 else {
3203 OS << " const unsigned MaxEditDist = 2;\n";
3204 OS << " std::vector<StringRef> Candidates;\n";
3205 OS << " StringRef Prev = \"\";\n\n";
3206
3207 OS << " // Find the appropriate table for this asm variant.\n";
3208 OS << " const MatchEntry *Start, *End;\n";
3209 OS << " switch (VariantID) {\n";
3210 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3211 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3212 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3213 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3214 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3215 << "); End = std::end(MatchTable" << VC << "); break;\n";
3216 }
3217 OS << " }\n\n";
3218 OS << " for (auto I = Start; I < End; I++) {\n";
3219 OS << " // Ignore unsupported instructions.\n";
3220 OS << " const FeatureBitset &RequiredFeatures = "
3221 "FeatureBitsets[I->RequiredFeaturesIdx];\n";
3222 OS << " if ((FBS & RequiredFeatures) != RequiredFeatures)\n";
3223 OS << " continue;\n";
3224 OS << "\n";
3225 OS << " StringRef T = I->getMnemonic();\n";
3226 OS << " // Avoid recomputing the edit distance for the same string.\n";
3227 OS << " if (T == Prev)\n";
3228 OS << " continue;\n";
3229 OS << "\n";
3230 OS << " Prev = T;\n";
3231 OS << " unsigned Dist = S.edit_distance(T, false, MaxEditDist);\n";
3232 OS << " if (Dist <= MaxEditDist)\n";
3233 OS << " Candidates.push_back(T);\n";
3234 OS << " }\n";
3235 OS << "\n";
3236 OS << " if (Candidates.empty())\n";
3237 OS << " return \"\";\n";
3238 OS << "\n";
3239 OS << " std::string Res = \", did you mean: \";\n";
3240 OS << " unsigned i = 0;\n";
3241 OS << " for (; i < Candidates.size() - 1; i++)\n";
3242 OS << " Res += Candidates[i].str() + \", \";\n";
3243 OS << " return Res + Candidates[i].str() + \"?\";\n";
3244 }
3245 OS << "}\n";
3246 OS << "\n";
3247}
3248
3249static void emitMnemonicChecker(raw_ostream &OS, CodeGenTarget &Target,
3250 unsigned VariantCount, bool HasMnemonicFirst,
3251 bool HasMnemonicAliases) {
3252 OS << "static bool " << Target.getName()
3253 << "CheckMnemonic(StringRef Mnemonic,\n";
3254 OS << " "
3255 << "const FeatureBitset &AvailableFeatures,\n";
3256 OS << " "
3257 << "unsigned VariantID) {\n";
3258
3259 if (!VariantCount) {
3260 OS << " return false;\n";
3261 } else {
3262 if (HasMnemonicAliases) {
3263 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3264 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);";
3265 OS << "\n\n";
3266 }
3267 OS << " // Find the appropriate table for this asm variant.\n";
3268 OS << " const MatchEntry *Start, *End;\n";
3269 OS << " switch (VariantID) {\n";
3270 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3271 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3272 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3273 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3274 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3275 << "); End = std::end(MatchTable" << VC << "); break;\n";
3276 }
3277 OS << " }\n\n";
3278
3279 OS << " // Search the table.\n";
3280 if (HasMnemonicFirst) {
3281 OS << " auto MnemonicRange = "
3282 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3283 } else {
3284 OS << " auto MnemonicRange = std::pair(Start, End);\n";
3285 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3286 OS << " if (!Mnemonic.empty())\n";
3287 OS << " MnemonicRange = "
3288 << "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3289 }
3290
3291 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3292 OS << " return false;\n\n";
3293
3294 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3295 << "*ie = MnemonicRange.second;\n";
3296 OS << " it != ie; ++it) {\n";
3297 OS << " const FeatureBitset &RequiredFeatures =\n";
3298 OS << " FeatureBitsets[it->RequiredFeaturesIdx];\n";
3299 OS << " if ((AvailableFeatures & RequiredFeatures) == ";
3300 OS << "RequiredFeatures)\n";
3301 OS << " return true;\n";
3302 OS << " }\n";
3303 OS << " return false;\n";
3304 }
3305 OS << "}\n";
3306 OS << "\n";
3307}
3308
3309// Emit a function mapping match classes to strings, for debugging.
3310static void emitMatchClassKindNames(std::forward_list<ClassInfo> &Infos,
3311 raw_ostream &OS) {
3312 OS << "#ifndef NDEBUG\n";
3313 OS << "const char *getMatchClassName(MatchClassKind Kind) {\n";
3314 OS << " switch (Kind) {\n";
3315
3316 OS << " case InvalidMatchClass: return \"InvalidMatchClass\";\n";
3317 OS << " case OptionalMatchClass: return \"OptionalMatchClass\";\n";
3318 for (const auto &CI : Infos) {
3319 OS << " case " << CI.Name << ": return \"" << CI.Name << "\";\n";
3320 }
3321 OS << " case NumMatchClassKinds: return \"NumMatchClassKinds\";\n";
3322
3323 OS << " }\n";
3324 OS << " llvm_unreachable(\"unhandled MatchClassKind!\");\n";
3325 OS << "}\n\n";
3326 OS << "#endif // NDEBUG\n";
3327}
3328
3329static std::string
3330getNameForFeatureBitset(ArrayRef<const Record *> FeatureBitset) {
3331 std::string Name = "AMFBS";
3332 for (const Record *Feature : FeatureBitset)
3333 Name += ("_" + Feature->getName()).str();
3334 return Name;
3335}
3336
3337void AsmMatcherEmitter::run(raw_ostream &OS) {
3338 CodeGenTarget Target(Records);
3339 const Record *AsmParser = Target.getAsmParser();
3340 StringRef ClassName = AsmParser->getValueAsString(FieldName: "AsmParserClassName");
3341
3342 emitSourceFileHeader(Desc: "Assembly Matcher Source Fragment", OS, Record: Records);
3343
3344 // Compute the information on the instructions to match.
3345 AsmMatcherInfo Info(AsmParser, Target, Records);
3346 Info.buildInfo();
3347
3348 bool PreferSmallerInstructions = getPreferSmallerInstructions(Target);
3349 // Sort the instruction table using the partial order on classes. We use
3350 // stable_sort to ensure that ambiguous instructions are still
3351 // deterministically ordered.
3352 llvm::stable_sort(
3353 Range&: Info.Matchables,
3354 C: [PreferSmallerInstructions](const std::unique_ptr<MatchableInfo> &A,
3355 const std::unique_ptr<MatchableInfo> &B) {
3356 return A->shouldBeMatchedBefore(RHS: *B, PreferSmallerInstructions);
3357 });
3358
3359#ifdef EXPENSIVE_CHECKS
3360 // Verify that the table is sorted and operator < works transitively.
3361 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
3362 ++I) {
3363 for (auto J = I; J != E; ++J) {
3364 assert(!(*J)->shouldBeMatchedBefore(**I, PreferSmallerInstructions));
3365 }
3366 }
3367#endif
3368
3369 DEBUG_WITH_TYPE("instruction_info", {
3370 for (const auto &MI : Info.Matchables)
3371 MI->dump();
3372 });
3373
3374 // Check for ambiguous matchables.
3375 DEBUG_WITH_TYPE("ambiguous_instrs", {
3376 unsigned NumAmbiguous = 0;
3377 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
3378 ++I) {
3379 for (auto J = std::next(I); J != E; ++J) {
3380 const MatchableInfo &A = **I;
3381 const MatchableInfo &B = **J;
3382
3383 if (A.couldMatchAmbiguouslyWith(B, PreferSmallerInstructions)) {
3384 errs() << "warning: ambiguous matchables:\n";
3385 A.dump();
3386 errs() << "\nis incomparable with:\n";
3387 B.dump();
3388 errs() << "\n\n";
3389 ++NumAmbiguous;
3390 }
3391 }
3392 }
3393 if (NumAmbiguous)
3394 errs() << "warning: " << NumAmbiguous << " ambiguous matchables!\n";
3395 });
3396
3397 // Compute the information on the custom operand parsing.
3398 Info.buildOperandMatchInfo();
3399
3400 bool HasMnemonicFirst = AsmParser->getValueAsBit(FieldName: "HasMnemonicFirst");
3401 bool HasOptionalOperands = Info.hasOptionalOperands();
3402 bool ReportMultipleNearMisses =
3403 AsmParser->getValueAsBit(FieldName: "ReportMultipleNearMisses");
3404
3405 // Write the output.
3406
3407 // Information for the class declaration.
3408 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
3409 OS << "#undef GET_ASSEMBLER_HEADER\n";
3410 OS << " // This should be included into the middle of the declaration of\n";
3411 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
3412 OS << " FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) "
3413 "const;\n";
3414 if (HasOptionalOperands) {
3415 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
3416 << "unsigned Opcode,\n"
3417 << " const OperandVector &Operands,\n"
3418 << " const SmallBitVector "
3419 "&OptionalOperandsMask,\n"
3420 << " ArrayRef<unsigned> DefaultsOffset);\n";
3421 } else {
3422 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
3423 << "unsigned Opcode,\n"
3424 << " const OperandVector &Operands);\n";
3425 }
3426 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
3427 OS << " const OperandVector &Operands) override;\n";
3428 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
3429 << " MCInst &Inst,\n";
3430 if (ReportMultipleNearMisses)
3431 OS << " SmallVectorImpl<NearMissInfo> "
3432 "*NearMisses,\n";
3433 else
3434 OS << " uint64_t &ErrorInfo,\n"
3435 << " FeatureBitset &MissingFeatures,\n";
3436 OS << " bool matchingInlineAsm,\n"
3437 << " unsigned VariantID = 0);\n";
3438 if (!ReportMultipleNearMisses)
3439 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
3440 << " MCInst &Inst,\n"
3441 << " uint64_t &ErrorInfo,\n"
3442 << " bool matchingInlineAsm,\n"
3443 << " unsigned VariantID = 0) {\n"
3444 << " FeatureBitset MissingFeatures;\n"
3445 << " return MatchInstructionImpl(Operands, Inst, ErrorInfo, "
3446 "MissingFeatures,\n"
3447 << " matchingInlineAsm, VariantID);\n"
3448 << " }\n\n";
3449
3450 if (!Info.OperandMatchInfo.empty()) {
3451 OS << " ParseStatus MatchOperandParserImpl(\n";
3452 OS << " OperandVector &Operands,\n";
3453 OS << " StringRef Mnemonic,\n";
3454 OS << " bool ParseForAllFeatures = false);\n";
3455
3456 OS << " ParseStatus tryCustomParseOperand(\n";
3457 OS << " OperandVector &Operands,\n";
3458 OS << " unsigned MCK);\n\n";
3459 }
3460
3461 OS << "#endif // GET_ASSEMBLER_HEADER\n\n";
3462
3463 // Emit the operand match diagnostic enum names.
3464 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
3465 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3466 emitOperandDiagnosticTypes(Info, OS);
3467 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3468
3469 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
3470 OS << "#undef GET_REGISTER_MATCHER\n\n";
3471
3472 // Emit the subtarget feature enumeration.
3473 SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(
3474 SubtargetFeatures: Info.SubtargetFeatures, OS);
3475
3476 // Emit the function to match a register name to number.
3477 // This should be omitted for Mips target
3478 if (AsmParser->getValueAsBit(FieldName: "ShouldEmitMatchRegisterName"))
3479 emitMatchRegisterName(Target, AsmParser, OS);
3480
3481 if (AsmParser->getValueAsBit(FieldName: "ShouldEmitMatchRegisterAltName"))
3482 emitMatchRegisterAltName(Target, AsmParser, OS);
3483
3484 OS << "#endif // GET_REGISTER_MATCHER\n\n";
3485
3486 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
3487 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
3488
3489 // Generate the helper function to get the names for subtarget features.
3490 emitGetSubtargetFeatureName(Info, OS);
3491
3492 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
3493
3494 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
3495 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
3496
3497 // Generate the function that remaps for mnemonic aliases.
3498 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
3499
3500 // Generate the convertToMCInst function to convert operands into an MCInst.
3501 // Also, generate the convertToMapAndConstraints function for MS-style inline
3502 // assembly. The latter doesn't actually generate a MCInst.
3503 unsigned NumConverters =
3504 emitConvertFuncs(Target, ClassName, Infos&: Info.Matchables, HasMnemonicFirst,
3505 HasOptionalOperands, OS);
3506
3507 // Emit the enumeration for classes which participate in matching.
3508 emitMatchClassEnumeration(Target, Infos&: Info.Classes, OS);
3509
3510 // Emit a function to get the user-visible string to describe an operand
3511 // match failure in diagnostics.
3512 emitOperandMatchErrorDiagStrings(Info, OS);
3513
3514 // Emit a function to map register classes to operand match failure codes.
3515 emitRegisterMatchErrorFunc(Info, OS);
3516
3517 // Emit the routine to match token strings to their match class.
3518 emitMatchTokenString(Target, Infos&: Info.Classes, OS);
3519
3520 // Emit the subclass predicate routine.
3521 emitIsSubclass(Target, Infos&: Info.Classes, OS);
3522
3523 // Emit the routine to validate an operand against a match class.
3524 emitValidateOperandClass(Target, Info, OS);
3525
3526 emitMatchClassKindNames(Infos&: Info.Classes, OS);
3527
3528 // Emit the available features compute function.
3529 SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
3530 TargetName: Info.Target.getName(), ClassName, FuncName: "ComputeAvailableFeatures",
3531 SubtargetFeatures&: Info.SubtargetFeatures, OS);
3532
3533 if (!ReportMultipleNearMisses)
3534 emitAsmTiedOperandConstraints(Target, Info, OS, HasOptionalOperands);
3535
3536 StringToOffsetTable StringTable(/*AppendZero=*/false);
3537
3538 size_t MaxNumOperands = 0;
3539 unsigned MaxMnemonicIndex = 0;
3540 bool HasDeprecation = false;
3541 for (const auto &MI : Info.Matchables) {
3542 MaxNumOperands = std::max(a: MaxNumOperands, b: MI->AsmOperands.size());
3543 HasDeprecation |= MI->HasDeprecation;
3544
3545 // Store a pascal-style length byte in the mnemonic.
3546 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
3547 MaxMnemonicIndex = std::max(a: MaxMnemonicIndex,
3548 b: StringTable.GetOrAddStringOffset(Str: LenMnemonic));
3549 }
3550
3551 OS << "static const char MnemonicTable[] =\n";
3552 StringTable.EmitString(O&: OS);
3553 OS << ";\n\n";
3554
3555 std::vector<std::vector<const Record *>> FeatureBitsets;
3556 for (const auto &MI : Info.Matchables) {
3557 if (MI->RequiredFeatures.empty())
3558 continue;
3559 FeatureBitsets.emplace_back();
3560 for (const auto *F : MI->RequiredFeatures)
3561 FeatureBitsets.back().push_back(x: F->TheDef);
3562 }
3563
3564 llvm::sort(C&: FeatureBitsets,
3565 Comp: [&](ArrayRef<const Record *> A, ArrayRef<const Record *> B) {
3566 if (A.size() != B.size())
3567 return A.size() < B.size();
3568 for (const auto [ARec, BRec] : zip_equal(t&: A, u&: B)) {
3569 if (ARec->getName() != BRec->getName())
3570 return ARec->getName() < BRec->getName();
3571 }
3572 return false;
3573 });
3574 FeatureBitsets.erase(first: llvm::unique(R&: FeatureBitsets), last: FeatureBitsets.end());
3575 OS << "// Feature bitsets.\n"
3576 << "enum : " << getMinimalTypeForRange(Range: FeatureBitsets.size()) << " {\n"
3577 << " AMFBS_None,\n";
3578 for (const auto &FeatureBitset : FeatureBitsets) {
3579 if (FeatureBitset.empty())
3580 continue;
3581 OS << " " << getNameForFeatureBitset(FeatureBitset) << ",\n";
3582 }
3583 OS << "};\n\n"
3584 << "static constexpr FeatureBitset FeatureBitsets[] = {\n"
3585 << " {}, // AMFBS_None\n";
3586 for (const auto &FeatureBitset : FeatureBitsets) {
3587 if (FeatureBitset.empty())
3588 continue;
3589 OS << " {";
3590 for (const auto &Feature : FeatureBitset) {
3591 const auto &I = Info.SubtargetFeatures.find(x: Feature);
3592 assert(I != Info.SubtargetFeatures.end() && "Didn't import predicate?");
3593 OS << I->second.getEnumBitName() << ", ";
3594 }
3595 OS << "},\n";
3596 }
3597 OS << "};\n\n";
3598
3599 // Emit the static match table; unused classes get initialized to 0 which is
3600 // guaranteed to be InvalidMatchClass.
3601 //
3602 // FIXME: We can reduce the size of this table very easily. First, we change
3603 // it so that store the kinds in separate bit-fields for each index, which
3604 // only needs to be the max width used for classes at that index (we also need
3605 // to reject based on this during classification). If we then make sure to
3606 // order the match kinds appropriately (putting mnemonics last), then we
3607 // should only end up using a few bits for each class, especially the ones
3608 // following the mnemonic.
3609 OS << "namespace {\n";
3610 OS << " struct MatchEntry {\n";
3611 OS << " " << getMinimalTypeForRange(Range: MaxMnemonicIndex) << " Mnemonic;\n";
3612 OS << " uint16_t Opcode;\n";
3613 OS << " " << getMinimalTypeForRange(Range: NumConverters) << " ConvertFn;\n";
3614 OS << " " << getMinimalTypeForRange(Range: FeatureBitsets.size())
3615 << " RequiredFeaturesIdx;\n";
3616 OS << " "
3617 << getMinimalTypeForRange(
3618 Range: std::distance(first: Info.Classes.begin(), last: Info.Classes.end()) +
3619 2 /* Include 'InvalidMatchClass' and 'OptionalMatchClass' */)
3620 << " Classes[" << MaxNumOperands << "];\n";
3621 OS << " StringRef getMnemonic() const {\n";
3622 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
3623 OS << " MnemonicTable[Mnemonic]);\n";
3624 OS << " }\n";
3625 OS << " };\n\n";
3626
3627 OS << " // Predicate for searching for an opcode.\n";
3628 OS << " struct LessOpcode {\n";
3629 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
3630 OS << " return LHS.getMnemonic() < RHS;\n";
3631 OS << " }\n";
3632 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
3633 OS << " return LHS < RHS.getMnemonic();\n";
3634 OS << " }\n";
3635 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
3636 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
3637 OS << " }\n";
3638 OS << " };\n";
3639
3640 OS << "} // end anonymous namespace\n\n";
3641
3642 unsigned VariantCount = Target.getAsmParserVariantCount();
3643 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3644 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3645 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3646
3647 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
3648
3649 for (const auto &MI : Info.Matchables) {
3650 if (MI->AsmVariantID != AsmVariantNo)
3651 continue;
3652
3653 // Store a pascal-style length byte in the mnemonic.
3654 std::string LenMnemonic =
3655 char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
3656 OS << " { " << *StringTable.GetStringOffset(Str: LenMnemonic) << " /* "
3657 << MI->Mnemonic << " */, " << Target.getInstNamespace()
3658 << "::" << MI->getResultInst()->getName() << ", "
3659 << MI->ConversionFnKind << ", ";
3660
3661 // Write the required features mask.
3662 OS << "AMFBS";
3663 if (MI->RequiredFeatures.empty())
3664 OS << "_None";
3665 else
3666 for (const auto &F : MI->RequiredFeatures)
3667 OS << '_' << F->TheDef->getName();
3668
3669 OS << ", { ";
3670 ListSeparator LS;
3671 for (const MatchableInfo::AsmOperand &Op : MI->AsmOperands)
3672 OS << LS << Op.Class->Name;
3673 OS << " }, },\n";
3674 }
3675
3676 OS << "};\n\n";
3677 }
3678
3679 OS << "#include \"llvm/Support/Debug.h\"\n";
3680 OS << "#include \"llvm/Support/Format.h\"\n\n";
3681
3682 // Finally, build the match function.
3683 OS << "unsigned " << Target.getName() << ClassName << "::\n"
3684 << "MatchInstructionImpl(const OperandVector &Operands,\n";
3685 OS << " MCInst &Inst,\n";
3686 if (ReportMultipleNearMisses)
3687 OS << " SmallVectorImpl<NearMissInfo> *NearMisses,\n";
3688 else
3689 OS << " uint64_t &ErrorInfo,\n"
3690 << " FeatureBitset &MissingFeatures,\n";
3691 OS << " bool matchingInlineAsm, unsigned VariantID) {\n";
3692
3693 if (!ReportMultipleNearMisses) {
3694 OS << " // Eliminate obvious mismatches.\n";
3695 OS << " if (Operands.size() > " << (MaxNumOperands + HasMnemonicFirst)
3696 << ") {\n";
3697 OS << " ErrorInfo = " << (MaxNumOperands + HasMnemonicFirst) << ";\n";
3698 OS << " return Match_InvalidOperand;\n";
3699 OS << " }\n\n";
3700 }
3701
3702 // Emit code to get the available features.
3703 OS << " // Get the current feature set.\n";
3704 OS << " const FeatureBitset &AvailableFeatures = "
3705 "getAvailableFeatures();\n\n";
3706
3707 OS << " // Get the instruction mnemonic, which is the first token.\n";
3708 if (HasMnemonicFirst) {
3709 OS << " StringRef Mnemonic = ((" << Target.getName()
3710 << "Operand &)*Operands[0]).getToken();\n\n";
3711 } else {
3712 OS << " StringRef Mnemonic;\n";
3713 OS << " if (Operands[0]->isToken())\n";
3714 OS << " Mnemonic = ((" << Target.getName()
3715 << "Operand &)*Operands[0]).getToken();\n\n";
3716 }
3717
3718 if (HasMnemonicAliases) {
3719 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3720 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
3721 }
3722
3723 // Emit code to compute the class list for this operand vector.
3724 if (!ReportMultipleNearMisses) {
3725 OS << " // Some state to try to produce better error messages.\n";
3726 OS << " bool HadMatchOtherThanFeatures = false;\n";
3727 OS << " bool HadMatchOtherThanPredicate = false;\n";
3728 OS << " unsigned RetCode = Match_InvalidOperand;\n";
3729 OS << " MissingFeatures.set();\n";
3730 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
3731 OS << " // wrong for all instances of the instruction.\n";
3732 OS << " ErrorInfo = ~0ULL;\n";
3733 }
3734
3735 if (HasOptionalOperands)
3736 OS << " SmallBitVector OptionalOperandsMask("
3737 << MaxNumOperands + HasMnemonicFirst << ");\n";
3738
3739 // Emit code to search the table.
3740 OS << " // Find the appropriate table for this asm variant.\n";
3741 OS << " const MatchEntry *Start, *End;\n";
3742 OS << " switch (VariantID) {\n";
3743 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3744 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3745 const Record *AsmVariant = Target.getAsmParserVariant(i: VC);
3746 int AsmVariantNo = AsmVariant->getValueAsInt(FieldName: "Variant");
3747 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3748 << "); End = std::end(MatchTable" << VC << "); break;\n";
3749 }
3750 OS << " }\n";
3751
3752 OS << " // Search the table.\n";
3753 if (HasMnemonicFirst) {
3754 OS << " auto MnemonicRange = "
3755 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3756 } else {
3757 OS << " auto MnemonicRange = std::pair(Start, End);\n";
3758 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3759 OS << " if (!Mnemonic.empty())\n";
3760 OS << " MnemonicRange = "
3761 "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3762 }
3763
3764 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"AsmMatcher: found \" "
3765 "<<\n"
3766 << " std::distance(MnemonicRange.first, MnemonicRange.second) <<\n"
3767 << " \" encodings with mnemonic '\" << Mnemonic << \"'\\n\");\n\n";
3768
3769 OS << " // Return a more specific error code if no mnemonics match.\n";
3770 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3771 OS << " return Match_MnemonicFail;\n\n";
3772
3773 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3774 << "*ie = MnemonicRange.second;\n";
3775 OS << " it != ie; ++it) {\n";
3776 OS << " const FeatureBitset &RequiredFeatures = "
3777 "FeatureBitsets[it->RequiredFeaturesIdx];\n";
3778 OS << " bool HasRequiredFeatures =\n";
3779 OS << " (AvailableFeatures & RequiredFeatures) == RequiredFeatures;\n";
3780 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Trying to match "
3781 "opcode \"\n";
3782 OS << " << MII.getName(it->Opcode) "
3783 "<< \"\\n\");\n";
3784
3785 if (ReportMultipleNearMisses) {
3786 OS << " // Some state to record ways in which this instruction did not "
3787 "match.\n";
3788 OS << " NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n";
3789 OS << " NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n";
3790 OS << " NearMissInfo EarlyPredicateNearMiss = "
3791 "NearMissInfo::getSuccess();\n";
3792 OS << " NearMissInfo LatePredicateNearMiss = "
3793 "NearMissInfo::getSuccess();\n";
3794 OS << " bool MultipleInvalidOperands = false;\n";
3795 }
3796
3797 if (HasMnemonicFirst) {
3798 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3799 OS << " assert(Mnemonic == it->getMnemonic());\n";
3800 }
3801
3802 // Emit check that the subclasses match.
3803 if (!ReportMultipleNearMisses)
3804 OS << " bool OperandsValid = true;\n";
3805 if (HasOptionalOperands)
3806 OS << " OptionalOperandsMask.reset(0, "
3807 << MaxNumOperands + HasMnemonicFirst << ");\n";
3808 OS << " for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")
3809 << ", ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")
3810 << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";
3811 OS << " auto Formal = "
3812 << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";
3813 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3814 OS << " dbgs() << \" Matching formal operand class \" "
3815 "<< getMatchClassName(Formal)\n";
3816 OS << " << \" against actual operand at index \" "
3817 "<< ActualIdx);\n";
3818 OS << " if (ActualIdx < Operands.size())\n";
3819 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \" (\";\n";
3820 OS << " Operands[ActualIdx]->print(dbgs(), "
3821 "*getContext().getAsmInfo()); dbgs() << "
3822 "\"): \");\n";
3823 OS << " else\n";
3824 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \": \");\n";
3825 OS << " if (ActualIdx >= Operands.size()) {\n";
3826 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"actual operand "
3827 "index out of range\\n\");\n";
3828 if (ReportMultipleNearMisses) {
3829 OS << " bool ThisOperandValid = (Formal == "
3830 << "InvalidMatchClass) || "
3831 "isSubclass(Formal, OptionalMatchClass);\n";
3832 OS << " if (!ThisOperandValid) {\n";
3833 OS << " if (!OperandNearMiss) {\n";
3834 OS << " // Record info about match failure for later use.\n";
3835 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording "
3836 "too-few-operands near miss\\n\");\n";
3837 OS << " OperandNearMiss =\n";
3838 OS << " NearMissInfo::getTooFewOperands(Formal, "
3839 "it->Opcode);\n";
3840 OS << " } else if (OperandNearMiss.getKind() != "
3841 "NearMissInfo::NearMissTooFewOperands) {\n";
3842 OS << " // If more than one operand is invalid, give up on this "
3843 "match entry.\n";
3844 OS << " DEBUG_WITH_TYPE(\n";
3845 OS << " \"asm-matcher\",\n";
3846 OS << " dbgs() << \"second invalid operand, giving up on "
3847 "this opcode\\n\");\n";
3848 OS << " MultipleInvalidOperands = true;\n";
3849 OS << " break;\n";
3850 OS << " }\n";
3851 OS << " } else {\n";
3852 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal "
3853 "operand not required\\n\");\n";
3854 OS << " if (isSubclass(Formal, OptionalMatchClass)) {\n";
3855 OS << " OptionalOperandsMask.set("
3856 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
3857 OS << " }\n";
3858 OS << " }\n";
3859 OS << " continue;\n";
3860 } else {
3861 OS << " if (Formal == InvalidMatchClass) {\n";
3862 if (HasOptionalOperands) {
3863 OS << " OptionalOperandsMask.set("
3864 << (HasMnemonicFirst ? "FormalIdx + 1, " : "FormalIdx, ")
3865 << MaxNumOperands + HasMnemonicFirst << ");\n";
3866 }
3867 OS << " break;\n";
3868 OS << " }\n";
3869 OS << " if (isSubclass(Formal, OptionalMatchClass)) {\n";
3870 if (HasOptionalOperands)
3871 OS << " OptionalOperandsMask.set("
3872 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
3873 OS << " continue;\n";
3874 OS << " }\n";
3875 OS << " OperandsValid = false;\n";
3876 OS << " ErrorInfo = ActualIdx;\n";
3877 OS << " break;\n";
3878 }
3879 OS << " }\n";
3880 OS << " MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";
3881 OS << " unsigned Diag = validateOperandClass(Actual, Formal, *STI);\n";
3882 OS << " if (Diag == Match_Success) {\n";
3883 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3884 OS << " dbgs() << \"match success using generic "
3885 "matcher\\n\");\n";
3886 OS << " ++ActualIdx;\n";
3887 OS << " continue;\n";
3888 OS << " }\n";
3889 OS << " // If the generic handler indicates an invalid operand\n";
3890 OS << " // failure, check for a special case.\n";
3891 OS << " if (Diag != Match_Success) {\n";
3892 OS << " unsigned TargetDiag = validateTargetOperandClass(Actual, "
3893 "Formal);\n";
3894 OS << " if (TargetDiag == Match_Success) {\n";
3895 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3896 OS << " dbgs() << \"match success using target "
3897 "matcher\\n\");\n";
3898 OS << " ++ActualIdx;\n";
3899 OS << " continue;\n";
3900 OS << " }\n";
3901 OS << " // If the target matcher returned a specific error code use\n";
3902 OS << " // that, else use the one from the generic matcher.\n";
3903 OS << " if (TargetDiag != Match_InvalidOperand && "
3904 "HasRequiredFeatures)\n";
3905 OS << " Diag = TargetDiag;\n";
3906 OS << " }\n";
3907 OS << " // If current formal operand wasn't matched and it is optional\n"
3908 << " // then try to match next formal operand\n";
3909 OS << " if (Diag == Match_InvalidOperand "
3910 << "&& isSubclass(Formal, OptionalMatchClass)) {\n";
3911 if (HasOptionalOperands)
3912 OS << " OptionalOperandsMask.set("
3913 << (HasMnemonicFirst ? "FormalIdx + 1" : "FormalIdx") << ");\n";
3914 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"ignoring "
3915 "optional operand\\n\");\n";
3916 OS << " continue;\n";
3917 OS << " }\n";
3918
3919 if (ReportMultipleNearMisses) {
3920 OS << " if (!OperandNearMiss) {\n";
3921 OS << " // If this is the first invalid operand we have seen, "
3922 "record some\n";
3923 OS << " // information about it.\n";
3924 OS << " DEBUG_WITH_TYPE(\n";
3925 OS << " \"asm-matcher\",\n";
3926 OS << " dbgs()\n";
3927 OS << " << \"operand match failed, recording near-miss with "
3928 "diag code \"\n";
3929 OS << " << Diag << \"\\n\");\n";
3930 OS << " OperandNearMiss =\n";
3931 OS << " NearMissInfo::getMissedOperand(Diag, Formal, "
3932 "it->Opcode, ActualIdx);\n";
3933 OS << " ++ActualIdx;\n";
3934 OS << " } else {\n";
3935 OS << " // If more than one operand is invalid, give up on this "
3936 "match entry.\n";
3937 OS << " DEBUG_WITH_TYPE(\n";
3938 OS << " \"asm-matcher\",\n";
3939 OS << " dbgs() << \"second operand mismatch, skipping this "
3940 "opcode\\n\");\n";
3941 OS << " MultipleInvalidOperands = true;\n";
3942 OS << " break;\n";
3943 OS << " }\n";
3944 OS << " }\n\n";
3945 } else {
3946 OS << " // If this operand is broken for all of the instances of "
3947 "this\n";
3948 OS << " // mnemonic, keep track of it so we can report loc info.\n";
3949 OS << " // If we already had a match that only failed due to a\n";
3950 OS << " // target predicate, that diagnostic is preferred.\n";
3951 OS << " if (!HadMatchOtherThanPredicate &&\n";
3952 OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) "
3953 "{\n";
3954 OS << " if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag "
3955 "!= Match_InvalidOperand))\n";
3956 OS << " RetCode = Diag;\n";
3957 OS << " ErrorInfo = ActualIdx;\n";
3958 OS << " }\n";
3959 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
3960 OS << " OperandsValid = false;\n";
3961 OS << " break;\n";
3962 OS << " }\n\n";
3963 }
3964
3965 if (ReportMultipleNearMisses)
3966 OS << " if (MultipleInvalidOperands) {\n";
3967 else
3968 OS << " if (!OperandsValid) {\n";
3969 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
3970 "multiple \"\n";
3971 OS << " \"operand mismatches, "
3972 "ignoring \"\n";
3973 OS << " \"this opcode\\n\");\n";
3974 OS << " continue;\n";
3975 OS << " }\n";
3976
3977 // Emit check that the required features are available.
3978 OS << " if (!HasRequiredFeatures) {\n";
3979 if (!ReportMultipleNearMisses)
3980 OS << " HadMatchOtherThanFeatures = true;\n";
3981 OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
3982 "~AvailableFeatures;\n";
3983 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
3984 "features:\";\n";
3985 OS << " for (unsigned I = 0, E = "
3986 "NewMissingFeatures.size(); I != E; ++I)\n";
3987 OS << " if (NewMissingFeatures[I])\n";
3988 OS << " dbgs() << ' ' << I;\n";
3989 OS << " dbgs() << \"\\n\");\n";
3990 if (ReportMultipleNearMisses) {
3991 OS << " FeaturesNearMiss = "
3992 "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
3993 } else {
3994 OS << " if (NewMissingFeatures.count() <=\n"
3995 " MissingFeatures.count())\n";
3996 OS << " MissingFeatures = NewMissingFeatures;\n";
3997 OS << " continue;\n";
3998 }
3999 OS << " }\n";
4000 OS << "\n";
4001 OS << " Inst.clear();\n\n";
4002 OS << " Inst.setOpcode(it->Opcode);\n";
4003 // Verify the instruction with the target-specific match predicate function.
4004 OS << " // We have a potential match but have not rendered the operands.\n"
4005 << " // Check the target predicate to handle any context sensitive\n"
4006 " // constraints.\n"
4007 << " // For example, Ties that are referenced multiple times must be\n"
4008 " // checked here to ensure the input is the same for each match\n"
4009 " // constraints. If we leave it any later the ties will have been\n"
4010 " // canonicalized\n"
4011 << " unsigned MatchResult;\n"
4012 << " if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "
4013 "Operands)) != Match_Success) {\n"
4014 << " Inst.clear();\n";
4015 OS << " DEBUG_WITH_TYPE(\n";
4016 OS << " \"asm-matcher\",\n";
4017 OS << " dbgs() << \"Early target match predicate failed with diag "
4018 "code \"\n";
4019 OS << " << MatchResult << \"\\n\");\n";
4020 if (ReportMultipleNearMisses) {
4021 OS << " EarlyPredicateNearMiss = "
4022 "NearMissInfo::getMissedPredicate(MatchResult);\n";
4023 } else {
4024 OS << " RetCode = MatchResult;\n"
4025 << " HadMatchOtherThanPredicate = true;\n"
4026 << " continue;\n";
4027 }
4028 OS << " }\n\n";
4029
4030 if (ReportMultipleNearMisses) {
4031 OS << " // If we did not successfully match the operands, then we can't "
4032 "convert to\n";
4033 OS << " // an MCInst, so bail out on this instruction variant now.\n";
4034 OS << " if (OperandNearMiss) {\n";
4035 OS << " // If the operand mismatch was the only problem, report it as "
4036 "a near-miss.\n";
4037 OS << " if (NearMisses && !FeaturesNearMiss && "
4038 "!EarlyPredicateNearMiss) {\n";
4039 OS << " DEBUG_WITH_TYPE(\n";
4040 OS << " \"asm-matcher\",\n";
4041 OS << " dbgs()\n";
4042 OS << " << \"Opcode result: one mismatched operand, adding "
4043 "near-miss\\n\");\n";
4044 OS << " NearMisses->push_back(OperandNearMiss);\n";
4045 OS << " } else {\n";
4046 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4047 "multiple \"\n";
4048 OS << " \"types of "
4049 "mismatch, so not \"\n";
4050 OS << " \"reporting "
4051 "near-miss\\n\");\n";
4052 OS << " }\n";
4053 OS << " continue;\n";
4054 OS << " }\n\n";
4055 }
4056
4057 // When converting parsed operands to MCInst we need to know whether optional
4058 // operands were parsed or not so that we can choose the correct converter
4059 // function. We also need to know this when checking tied operand constraints.
4060 // DefaultsOffset is an array of deltas between the formal (MCInst) and the
4061 // actual (parsed operand array) operand indices. When all optional operands
4062 // are present, all elements of the array are zeros. If some of the optional
4063 // operands are absent, the array might look like '0, 0, 1, 1, 1, 2, 2, 3',
4064 // where each increment in value reflects the absence of an optional operand.
4065 if (HasOptionalOperands) {
4066 OS << " unsigned DefaultsOffset[" << (MaxNumOperands + 1)
4067 << "] = { 0 };\n";
4068 OS << " assert(OptionalOperandsMask.size() == "
4069 << (MaxNumOperands + HasMnemonicFirst) << ");\n";
4070 OS << " for (unsigned i = 0, NumDefaults = 0; i < " << (MaxNumOperands)
4071 << "; ++i) {\n";
4072 OS << " NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);\n";
4073 OS << " DefaultsOffset[i + 1] = NumDefaults;\n";
4074 OS << " }\n\n";
4075 }
4076
4077 OS << " if (matchingInlineAsm) {\n";
4078 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
4079 if (!ReportMultipleNearMisses) {
4080 if (HasOptionalOperands) {
4081 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4082 "Operands,\n";
4083 OS << " DefaultsOffset, "
4084 "ErrorInfo))\n";
4085 } else {
4086 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4087 "Operands,\n";
4088 OS << " ErrorInfo))\n";
4089 }
4090 OS << " return Match_InvalidTiedOperand;\n";
4091 OS << "\n";
4092 }
4093 OS << " return Match_Success;\n";
4094 OS << " }\n\n";
4095 OS << " // We have selected a definite instruction, convert the parsed\n"
4096 << " // operands into the appropriate MCInst.\n";
4097 if (HasOptionalOperands) {
4098 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,\n"
4099 << " OptionalOperandsMask, DefaultsOffset);\n";
4100 } else {
4101 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
4102 }
4103 OS << "\n";
4104
4105 // Verify the instruction with the target-specific match predicate function.
4106 OS << " // We have a potential match. Check the target predicate to\n"
4107 << " // handle any context sensitive constraints.\n"
4108 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
4109 << " Match_Success) {\n"
4110 << " DEBUG_WITH_TYPE(\"asm-matcher\",\n"
4111 << " dbgs() << \"Target match predicate failed with "
4112 "diag code \"\n"
4113 << " << MatchResult << \"\\n\");\n"
4114 << " Inst.clear();\n";
4115 if (ReportMultipleNearMisses) {
4116 OS << " LatePredicateNearMiss = "
4117 "NearMissInfo::getMissedPredicate(MatchResult);\n";
4118 } else {
4119 OS << " RetCode = MatchResult;\n"
4120 << " HadMatchOtherThanPredicate = true;\n"
4121 << " continue;\n";
4122 }
4123 OS << " }\n\n";
4124
4125 if (ReportMultipleNearMisses) {
4126 OS << " int NumNearMisses = ((int)(bool)OperandNearMiss +\n";
4127 OS << " (int)(bool)FeaturesNearMiss +\n";
4128 OS << " (int)(bool)EarlyPredicateNearMiss +\n";
4129 OS << " (int)(bool)LatePredicateNearMiss);\n";
4130 OS << " if (NumNearMisses == 1) {\n";
4131 OS << " // We had exactly one type of near-miss, so add that to the "
4132 "list.\n";
4133 OS << " assert(!OperandNearMiss && \"OperandNearMiss was handled "
4134 "earlier\");\n";
4135 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4136 "found one type of \"\n";
4137 OS << " \"mismatch, so "
4138 "reporting a \"\n";
4139 OS << " \"near-miss\\n\");\n";
4140 OS << " if (NearMisses && FeaturesNearMiss)\n";
4141 OS << " NearMisses->push_back(FeaturesNearMiss);\n";
4142 OS << " else if (NearMisses && EarlyPredicateNearMiss)\n";
4143 OS << " NearMisses->push_back(EarlyPredicateNearMiss);\n";
4144 OS << " else if (NearMisses && LatePredicateNearMiss)\n";
4145 OS << " NearMisses->push_back(LatePredicateNearMiss);\n";
4146 OS << "\n";
4147 OS << " continue;\n";
4148 OS << " } else if (NumNearMisses > 1) {\n";
4149 OS << " // This instruction missed in more than one way, so ignore "
4150 "it.\n";
4151 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
4152 "multiple \"\n";
4153 OS << " \"types of mismatch, "
4154 "so not \"\n";
4155 OS << " \"reporting "
4156 "near-miss\\n\");\n";
4157 OS << " continue;\n";
4158 OS << " }\n";
4159 }
4160
4161 // Call the post-processing function, if used.
4162 StringRef InsnCleanupFn = AsmParser->getValueAsString(FieldName: "AsmParserInstCleanup");
4163 if (!InsnCleanupFn.empty())
4164 OS << " " << InsnCleanupFn << "(Inst);\n";
4165
4166 if (HasDeprecation) {
4167 OS << " std::string Info;\n";
4168 OS << " if "
4169 "(!getParser().getTargetParser().getTargetOptions()."
4170 "MCNoDeprecatedWarn &&\n";
4171 OS << " MII.getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
4172 OS << " SMLoc Loc = ((" << Target.getName()
4173 << "Operand &)*Operands[0]).getStartLoc();\n";
4174 OS << " getParser().Warning(Loc, Info, {});\n";
4175 OS << " }\n";
4176 }
4177
4178 if (!ReportMultipleNearMisses) {
4179 if (HasOptionalOperands) {
4180 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4181 "Operands,\n";
4182 OS << " DefaultsOffset, "
4183 "ErrorInfo))\n";
4184 } else {
4185 OS << " if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
4186 "Operands,\n";
4187 OS << " ErrorInfo))\n";
4188 }
4189 OS << " return Match_InvalidTiedOperand;\n";
4190 OS << "\n";
4191 }
4192
4193 OS << " DEBUG_WITH_TYPE(\n";
4194 OS << " \"asm-matcher\",\n";
4195 OS << " dbgs() << \"Opcode result: complete match, selecting this "
4196 "opcode\\n\");\n";
4197 OS << " return Match_Success;\n";
4198 OS << " }\n\n";
4199
4200 if (ReportMultipleNearMisses) {
4201 OS << " // No instruction variants matched exactly.\n";
4202 OS << " return Match_NearMisses;\n";
4203 } else {
4204 OS << " // Okay, we had no match. Try to return a useful error code.\n";
4205 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
4206 OS << " return RetCode;\n\n";
4207 OS << " ErrorInfo = 0;\n";
4208 OS << " return Match_MissingFeature;\n";
4209 }
4210 OS << "}\n\n";
4211
4212 if (!Info.OperandMatchInfo.empty())
4213 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
4214 MaxMnemonicIndex, MaxFeaturesIndex: FeatureBitsets.size(),
4215 HasMnemonicFirst, AsmParser: *AsmParser);
4216
4217 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
4218
4219 OS << "\n#ifdef GET_MNEMONIC_SPELL_CHECKER\n";
4220 OS << "#undef GET_MNEMONIC_SPELL_CHECKER\n\n";
4221
4222 emitMnemonicSpellChecker(OS, Target, VariantCount);
4223
4224 OS << "#endif // GET_MNEMONIC_SPELL_CHECKER\n\n";
4225
4226 OS << "\n#ifdef GET_MNEMONIC_CHECKER\n";
4227 OS << "#undef GET_MNEMONIC_CHECKER\n\n";
4228
4229 emitMnemonicChecker(OS, Target, VariantCount, HasMnemonicFirst,
4230 HasMnemonicAliases);
4231
4232 OS << "#endif // GET_MNEMONIC_CHECKER\n\n";
4233}
4234
4235static TableGen::Emitter::OptClass<AsmMatcherEmitter>
4236 X("gen-asm-matcher", "Generate assembly instruction matcher");
4237