1//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines wrappers for the Target class and related global
10// functionality. This makes it easier to access the data and provides a single
11// place that needs to check it for validity. All of these classes abort
12// on error conditions.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
17#define LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
18
19#include "Basic/CodeGenIntrinsics.h"
20#include "Basic/SDNodeProperties.h"
21#include "CodeGenHwModes.h"
22#include "CodeGenInstruction.h"
23#include "InfoByHwMode.h"
24#include "llvm/ADT/ArrayRef.h"
25#include "llvm/ADT/DenseMap.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/StringRef.h"
28#include "llvm/CodeGenTypes/MachineValueType.h"
29#include <cassert>
30#include <memory>
31#include <string>
32#include <vector>
33
34namespace llvm {
35
36class RecordKeeper;
37class Record;
38class CodeGenRegBank;
39class CodeGenRegister;
40class CodeGenRegisterClass;
41class CodeGenSchedModels;
42class CodeGenSubRegIndex;
43
44/// Returns the MVT that the specified TableGen
45/// record corresponds to.
46MVT getValueType(const Record *Rec);
47
48StringRef getEnumName(MVT T);
49
50/// getQualifiedName - Return the name of the specified record, with a
51/// namespace qualifier if the record contains one.
52std::string getQualifiedName(const Record *R);
53
54/// CodeGenTarget - This class corresponds to the Target class in the .td files.
55///
56class CodeGenTarget {
57 const RecordKeeper &Records;
58 const Record *TargetRec;
59
60 mutable DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>>
61 InstructionMap;
62 mutable std::unique_ptr<CodeGenRegBank> RegBank;
63 mutable ArrayRef<const Record *> RegAltNameIndices;
64 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
65 CodeGenHwModes CGH;
66 ArrayRef<const Record *> MacroFusions;
67 mutable bool HasVariableLengthEncodings = false;
68
69 void ReadInstructions() const;
70 void ReadLegalValueTypes() const;
71
72 mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
73
74 mutable StringRef InstNamespace;
75 mutable std::vector<const CodeGenInstruction *> InstrsByEnum;
76 mutable CodeGenIntrinsicMap Intrinsics;
77
78 mutable unsigned NumPseudoInstructions = 0;
79
80public:
81 CodeGenTarget(const RecordKeeper &Records);
82 ~CodeGenTarget();
83
84 const Record *getTargetRecord() const { return TargetRec; }
85 StringRef getName() const;
86
87 /// getInstNamespace - Return the target-specific instruction namespace.
88 ///
89 StringRef getInstNamespace() const;
90
91 /// getRegNamespace - Return the target-specific register namespace.
92 StringRef getRegNamespace() const;
93
94 /// getInstructionSet - Return the InstructionSet object.
95 ///
96 const Record *getInstructionSet() const;
97
98 /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
99 /// this target.
100 ///
101 bool getAllowRegisterRenaming() const;
102
103 /// getRegistersAreIntervals - Return the RegistersAreIntervals flag value for
104 /// this target.
105 ///
106 bool getRegistersAreIntervals() const;
107
108 /// getAsmParser - Return the AssemblyParser definition for this target.
109 ///
110 const Record *getAsmParser() const;
111
112 /// getAsmParserVariant - Return the AssemblyParserVariant definition for
113 /// this target.
114 ///
115 const Record *getAsmParserVariant(unsigned i) const;
116
117 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
118 /// available for this target.
119 ///
120 unsigned getAsmParserVariantCount() const;
121
122 /// getAsmWriter - Return the AssemblyWriter definition for this target.
123 ///
124 const Record *getAsmWriter() const;
125
126 /// getRegBank - Return the register bank description.
127 CodeGenRegBank &getRegBank() const;
128
129 /// getRegisterByName - If there is a register with the specific AsmName,
130 /// return it.
131 const CodeGenRegister *getRegisterByName(StringRef Name) const;
132
133 ArrayRef<const Record *> getRegAltNameIndices() const {
134 if (RegAltNameIndices.empty())
135 RegAltNameIndices = Records.getAllDerivedDefinitions(ClassName: "RegAltNameIndex");
136 return RegAltNameIndices;
137 }
138
139 const CodeGenRegisterClass &getRegisterClass(const Record *R,
140 ArrayRef<SMLoc> Loc = {}) const;
141
142 /// Convenience wrapper to avoid hardcoding the name of RegClassByHwMode
143 /// everywhere. This is here instead of CodeGenRegBank to avoid the fatal
144 /// error that occurs when no RegisterClasses are defined when constructing
145 /// the bank.
146 ArrayRef<const Record *> getAllRegClassByHwMode() const {
147 return Records.getAllDerivedDefinitions(ClassName: "RegClassByHwMode");
148 }
149
150 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
151 /// specified physical register.
152 std::vector<ValueTypeByHwMode> getRegisterVTs(const Record *R) const;
153
154 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
155 if (LegalValueTypes.empty())
156 ReadLegalValueTypes();
157 return LegalValueTypes;
158 }
159
160 /// If \p V is a DefInit that can be interpreted as a RegisterClass (e.g.,
161 /// it's a RegisterOperand, or a direct RegisterClass reference), return the
162 /// Record for that RegisterClass.
163 ///
164 /// AssumeRegClassByHwModeIsDefault is a hack which should be removed. It only
165 /// happens to be adequate for the current GlobalISel usage.
166 const Record *
167 getInitValueAsRegClass(const Init *V,
168 bool AssumeRegClassByHwModeIsDefault = false) const;
169
170 /// If \p V is a DefInit that can be interpreted as a RegisterClassLike,
171 /// return the Record. This is used as a convenience function to handle direct
172 /// RegisterClass references, or those wrapped in a RegisterOperand.
173 const Record *getInitValueAsRegClassLike(const Init *V) const;
174 const Record *getAsRegClassLike(const Record *V) const;
175
176 CodeGenSchedModels &getSchedModels() const;
177
178 const CodeGenHwModes &getHwModes() const { return CGH; }
179
180 bool hasMacroFusion() const { return !MacroFusions.empty(); }
181
182 ArrayRef<const Record *> getMacroFusions() const { return MacroFusions; }
183
184private:
185 DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &
186 getInstructionMap() const {
187 if (InstructionMap.empty())
188 ReadInstructions();
189 return InstructionMap;
190 }
191
192public:
193 CodeGenInstruction &getInstruction(const Record *InstRec) const {
194 auto I = getInstructionMap().find(Val: InstRec);
195 assert(I != InstructionMap.end() && "Not an instruction");
196 return *I->second;
197 }
198
199 /// Returns the number of predefined instructions.
200 static unsigned getNumFixedInstructions();
201
202 /// Return all of the instructions defined by the target, ordered by their
203 /// enum value.
204 /// The following order of instructions is also guaranteed:
205 /// - fixed / generic instructions as declared in TargetOpcodes.def, in order;
206 /// - pseudo instructions in lexicographical order sorted by name;
207 /// - other instructions in lexicographical order sorted by name.
208 ArrayRef<const CodeGenInstruction *> getInstructions() const {
209 if (InstrsByEnum.empty())
210 ComputeInstrsByEnum();
211 return InstrsByEnum;
212 }
213
214 // Functions that return various slices of `getInstructions`, ordered by
215 // their enum values.
216 ArrayRef<const CodeGenInstruction *> getGenericInstructions() const {
217 return getInstructions().take_front(N: getNumFixedInstructions());
218 }
219
220 ArrayRef<const CodeGenInstruction *> getTargetInstructions() const {
221 return getInstructions().drop_front(N: getNumFixedInstructions());
222 }
223
224 ArrayRef<const CodeGenInstruction *> getTargetPseudoInstructions() const {
225 return getTargetInstructions().take_front(N: NumPseudoInstructions);
226 }
227
228 ArrayRef<const CodeGenInstruction *> getTargetNonPseudoInstructions() const {
229 return getTargetInstructions().drop_front(N: NumPseudoInstructions);
230 }
231
232 /// Return the integer enum value corresponding to this instruction record.
233 unsigned getInstrIntValue(const Record *R) const {
234 if (InstrsByEnum.empty())
235 ComputeInstrsByEnum();
236 return getInstruction(InstRec: R).EnumVal;
237 }
238
239 /// Return whether instructions have variable length encodings on this target.
240 bool hasVariableLengthEncodings() const { return HasVariableLengthEncodings; }
241
242 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
243 ///
244 bool isLittleEndianEncoding() const;
245
246 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
247 /// encodings, reverse the bit order of all instructions.
248 void reverseBitsForLittleEndianEncoding();
249
250 /// guessInstructionProperties - should we just guess unset instruction
251 /// properties?
252 bool guessInstructionProperties() const;
253
254 const CodeGenIntrinsic &getIntrinsic(const Record *Def) const {
255 return Intrinsics[Def];
256 }
257
258private:
259 void ComputeInstrsByEnum() const;
260};
261
262/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
263/// tablegen class in TargetSelectionDAG.td
264class ComplexPattern {
265 const Record *Ty;
266 unsigned NumOperands;
267 std::string SelectFunc;
268 std::vector<const Record *> RootNodes;
269 unsigned Properties; // Node properties
270 unsigned Complexity;
271 bool WantsRoot;
272 bool WantsParent;
273
274public:
275 ComplexPattern(const Record *R);
276
277 const Record *getValueType() const { return Ty; }
278 unsigned getNumOperands() const { return NumOperands; }
279 const std::string &getSelectFunc() const { return SelectFunc; }
280 ArrayRef<const Record *> getRootNodes() const { return RootNodes; }
281 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
282 unsigned getComplexity() const { return Complexity; }
283 bool wantsRoot() const { return WantsRoot; }
284 bool wantsParent() const { return WantsParent; }
285};
286
287} // namespace llvm
288
289#endif // LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
290