1//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines wrappers for the Target class and related global
10// functionality. This makes it easier to access the data and provides a single
11// place that needs to check it for validity. All of these classes abort
12// on error conditions.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
17#define LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
18
19#include "Basic/CodeGenIntrinsics.h"
20#include "Basic/SDNodeProperties.h"
21#include "CodeGenHwModes.h"
22#include "CodeGenInstruction.h"
23#include "InfoByHwMode.h"
24#include "llvm/ADT/ArrayRef.h"
25#include "llvm/ADT/DenseMap.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/StringRef.h"
28#include "llvm/CodeGenTypes/MachineValueType.h"
29#include <cassert>
30#include <memory>
31#include <optional>
32#include <string>
33#include <vector>
34
35namespace llvm {
36
37class RecordKeeper;
38class Record;
39class CodeGenRegBank;
40class CodeGenRegister;
41class CodeGenRegisterClass;
42class CodeGenSchedModels;
43class CodeGenSubRegIndex;
44
45/// Returns the MVT that the specified TableGen
46/// record corresponds to.
47MVT getValueType(const Record *Rec);
48
49StringRef getEnumName(MVT T);
50
51/// getQualifiedName - Return the name of the specified record, with a
52/// namespace qualifier if the record contains one.
53std::string getQualifiedName(const Record *R);
54
55/// CodeGenTarget - This class corresponds to the Target class in the .td files.
56///
57class CodeGenTarget {
58 const RecordKeeper &Records;
59 const Record *TargetRec;
60
61 mutable DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>>
62 InstructionMap;
63 mutable std::unique_ptr<CodeGenRegBank> RegBank;
64 mutable ArrayRef<const Record *> RegAltNameIndices;
65 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
66 mutable std::optional<std::vector<const Record *>> RegClassByHwModeList;
67 CodeGenHwModes CGH;
68 ArrayRef<const Record *> MacroFusions;
69 mutable bool HasVariableLengthEncodings = false;
70
71 void ReadInstructions() const;
72 void ReadLegalValueTypes() const;
73
74 mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
75
76 mutable StringRef InstNamespace;
77 mutable std::vector<const CodeGenInstruction *> InstrsByEnum;
78 mutable CodeGenIntrinsicMap Intrinsics;
79
80 mutable unsigned NumPseudoInstructions = 0;
81
82public:
83 CodeGenTarget(const RecordKeeper &Records);
84 ~CodeGenTarget();
85
86 const Record *getTargetRecord() const { return TargetRec; }
87 StringRef getName() const;
88
89 /// getInstNamespace - Return the target-specific instruction namespace.
90 ///
91 StringRef getInstNamespace() const;
92
93 /// getRegNamespace - Return the target-specific register namespace.
94 StringRef getRegNamespace() const;
95
96 /// getInstructionSet - Return the InstructionSet object.
97 ///
98 const Record *getInstructionSet() const;
99
100 /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
101 /// this target.
102 ///
103 bool getAllowRegisterRenaming() const;
104
105 /// getRegistersAreIntervals - Return the RegistersAreIntervals flag value for
106 /// this target.
107 ///
108 bool getRegistersAreIntervals() const;
109
110 /// getAsmParser - Return the AssemblyParser definition for this target.
111 ///
112 const Record *getAsmParser() const;
113
114 /// getAsmParserVariant - Return the AssemblyParserVariant definition for
115 /// this target.
116 ///
117 const Record *getAsmParserVariant(unsigned i) const;
118
119 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
120 /// available for this target.
121 ///
122 unsigned getAsmParserVariantCount() const;
123
124 /// getAsmWriter - Return the AssemblyWriter definition for this target.
125 ///
126 const Record *getAsmWriter() const;
127
128 /// getRegBank - Return the register bank description.
129 CodeGenRegBank &getRegBank() const;
130
131 /// getRegisterByName - If there is a register with the specific AsmName,
132 /// return it.
133 const CodeGenRegister *getRegisterByName(StringRef Name) const;
134
135 ArrayRef<const Record *> getRegAltNameIndices() const {
136 if (RegAltNameIndices.empty())
137 RegAltNameIndices = Records.getAllDerivedDefinitions(ClassName: "RegAltNameIndex");
138 return RegAltNameIndices;
139 }
140
141 const CodeGenRegisterClass &getRegisterClass(const Record *R,
142 ArrayRef<SMLoc> Loc = {}) const;
143
144 /// Convenience wrapper to avoid hardcoding the name of RegClassByHwMode
145 /// everywhere. This is here instead of CodeGenRegBank to avoid the fatal
146 /// error that occurs when no RegisterClasses are defined when constructing
147 /// the bank. The empty ptr_rc placeholder is excluded: it carries no register
148 /// classes and only exists to be substituted per target.
149 ArrayRef<const Record *> getAllRegClassByHwMode() const;
150
151 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
152 /// specified physical register.
153 std::vector<ValueTypeByHwMode> getRegisterVTs(const Record *R) const;
154
155 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
156 if (LegalValueTypes.empty())
157 ReadLegalValueTypes();
158 return LegalValueTypes;
159 }
160
161 /// If \p V is a DefInit that can be interpreted as a RegisterClass (e.g.,
162 /// it's a RegisterOperand, or a direct RegisterClass reference), return the
163 /// Record for that RegisterClass.
164 ///
165 /// AssumeRegClassByHwModeIsDefault is a hack which should be removed. It only
166 /// happens to be adequate for the current GlobalISel usage.
167 const Record *
168 getInitValueAsRegClass(const Init *V,
169 bool AssumeRegClassByHwModeIsDefault = false) const;
170
171 /// If \p V is a DefInit that can be interpreted as a RegisterClassLike,
172 /// return the Record. This is used as a convenience function to handle direct
173 /// RegisterClass references, or those wrapped in a RegisterOperand.
174 const Record *getInitValueAsRegClassLike(const Init *V) const;
175 const Record *getAsRegClassLike(const Record *V) const;
176
177 CodeGenSchedModels &getSchedModels() const;
178
179 const CodeGenHwModes &getHwModes() const { return CGH; }
180
181 bool hasMacroFusion() const { return !MacroFusions.empty(); }
182
183 ArrayRef<const Record *> getMacroFusions() const { return MacroFusions; }
184
185private:
186 DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &
187 getInstructionMap() const {
188 if (InstructionMap.empty())
189 ReadInstructions();
190 return InstructionMap;
191 }
192
193public:
194 CodeGenInstruction &getInstruction(const Record *InstRec) const {
195 auto I = getInstructionMap().find(Val: InstRec);
196 assert(I != InstructionMap.end() && "Not an instruction");
197 return *I->second;
198 }
199
200 /// Returns the number of predefined instructions.
201 static unsigned getNumFixedInstructions();
202
203 /// Return all of the instructions defined by the target, ordered by their
204 /// enum value.
205 /// The following order of instructions is also guaranteed:
206 /// - fixed / generic instructions as declared in TargetOpcodes.def, in order;
207 /// - pseudo instructions in lexicographical order sorted by name;
208 /// - other instructions in lexicographical order sorted by name.
209 ArrayRef<const CodeGenInstruction *> getInstructions() const {
210 if (InstrsByEnum.empty())
211 ComputeInstrsByEnum();
212 return InstrsByEnum;
213 }
214
215 // Functions that return various slices of `getInstructions`, ordered by
216 // their enum values.
217 ArrayRef<const CodeGenInstruction *> getGenericInstructions() const {
218 return getInstructions().take_front(N: getNumFixedInstructions());
219 }
220
221 ArrayRef<const CodeGenInstruction *> getTargetInstructions() const {
222 return getInstructions().drop_front(N: getNumFixedInstructions());
223 }
224
225 ArrayRef<const CodeGenInstruction *> getTargetPseudoInstructions() const {
226 return getTargetInstructions().take_front(N: NumPseudoInstructions);
227 }
228
229 ArrayRef<const CodeGenInstruction *> getTargetNonPseudoInstructions() const {
230 return getTargetInstructions().drop_front(N: NumPseudoInstructions);
231 }
232
233 /// Return the integer enum value corresponding to this instruction record.
234 unsigned getInstrIntValue(const Record *R) const {
235 if (InstrsByEnum.empty())
236 ComputeInstrsByEnum();
237 return getInstruction(InstRec: R).EnumVal;
238 }
239
240 /// Return whether instructions have variable length encodings on this target.
241 bool hasVariableLengthEncodings() const { return HasVariableLengthEncodings; }
242
243 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
244 ///
245 bool isLittleEndianEncoding() const;
246
247 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
248 /// encodings, reverse the bit order of all instructions.
249 void reverseBitsForLittleEndianEncoding();
250
251 /// guessInstructionProperties - should we just guess unset instruction
252 /// properties?
253 bool guessInstructionProperties() const;
254
255 const CodeGenIntrinsic &getIntrinsic(const Record *Def) const {
256 return Intrinsics[Def];
257 }
258
259private:
260 void ComputeInstrsByEnum() const;
261};
262
263/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
264/// tablegen class in TargetSelectionDAG.td
265class ComplexPattern {
266 const Record *Ty;
267 unsigned NumOperands;
268 std::string SelectFunc;
269 std::vector<const Record *> RootNodes;
270 unsigned Properties; // Node properties
271 unsigned Complexity;
272 bool WantsRoot;
273 bool WantsParent;
274
275public:
276 ComplexPattern(const Record *R);
277
278 const Record *getValueType() const { return Ty; }
279 unsigned getNumOperands() const { return NumOperands; }
280 const std::string &getSelectFunc() const { return SelectFunc; }
281 ArrayRef<const Record *> getRootNodes() const { return RootNodes; }
282 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
283 unsigned getComplexity() const { return Complexity; }
284 bool wantsRoot() const { return WantsRoot; }
285 bool wantsParent() const { return WantsParent; }
286};
287
288} // namespace llvm
289
290#endif // LLVM_UTILS_TABLEGEN_COMMON_CODEGENTARGET_H
291