1//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// CodeEmitterGen uses the descriptions of instructions and their fields to
10// construct an automated code emitter: a function called
11// getBinaryCodeForInstr() that, given a MCInst, returns the value of the
12// instruction - either as an uint64_t or as an APInt, depending on the
13// maximum bit width of all Inst definitions.
14//
15// In addition, it generates another function called getOperandBitOffset()
16// that, given a MCInst and an operand index, returns the minimum of indices of
17// all bits that carry some portion of the respective operand. When the target's
18// encodeInstruction() stores the instruction in a little-endian byte order, the
19// returned value is the offset of the start of the operand in the encoded
20// instruction. Other targets might need to adjust the returned value according
21// to their encodeInstruction() implementation.
22//
23//===----------------------------------------------------------------------===//
24
25#include "Common/CodeGenHwModes.h"
26#include "Common/CodeGenInstruction.h"
27#include "Common/CodeGenTarget.h"
28#include "Common/InfoByHwMode.h"
29#include "Common/VarLenCodeEmitterGen.h"
30#include "llvm/ADT/APInt.h"
31#include "llvm/ADT/ArrayRef.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/Support/Casting.h"
35#include "llvm/Support/Format.h"
36#include "llvm/Support/FormatVariadic.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/TableGen/CodeGenHelpers.h"
40#include "llvm/TableGen/Error.h"
41#include "llvm/TableGen/Record.h"
42#include "llvm/TableGen/TableGenBackend.h"
43#include <cstdint>
44#include <map>
45#include <set>
46#include <string>
47#include <utility>
48#include <vector>
49
50using namespace llvm;
51
52namespace {
53
54// A map of uniqued case statements. The key is the body of the case statement
55// and the value is a list of cases which share the same body.
56using CaseMapT = std::map<std::string, std::vector<unsigned>>;
57
58struct BaseEncodingPool {
59 std::vector<APInt> Values;
60 std::map<unsigned, std::vector<unsigned>> IndicesByHwMode;
61 unsigned IndexBitWidth = 0;
62
63 bool empty() const { return Values.empty(); }
64};
65
66class CodeEmitterGen {
67 const RecordKeeper &RK;
68 CodeGenTarget Target;
69 const CodeGenHwModes &CGH;
70
71public:
72 explicit CodeEmitterGen(const RecordKeeper &RK);
73
74 void run(raw_ostream &O);
75
76private:
77 int getVariableBit(const std::string &VarName, const BitsInit *BI, int Bit);
78 std::pair<std::string, std::string> getInstructionCases(const Record *R);
79 void addInstructionCasesForEncoding(const Record *R,
80 const Record *EncodingDef,
81 std::string &Case,
82 std::string &BitOffsetCase);
83 bool addCodeToMergeInOperand(const Record *R, const BitsInit *BI,
84 const std::string &VarName, std::string &Case,
85 std::string &BitOffsetCase);
86
87 APInt getInstructionBaseValue(const CodeGenInstruction *CGI, unsigned HwMode);
88 void buildBaseEncodingPool(
89 ArrayRef<const CodeGenInstruction *> NumberedInstructions,
90 const std::set<unsigned> &HwModes);
91 void emitBaseEncodingPool(raw_ostream &O);
92 void emitInstructionBaseValues(
93 raw_ostream &O, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
94 unsigned HwMode = DefaultMode);
95 BaseEncodingPool BaseEncodings;
96 unsigned BitWidth = 0u;
97 bool UseAPInt = false;
98};
99
100} // end anonymous namespace
101
102// If the VarBitInit at position 'bit' matches the specified variable then
103// return the variable bit position. Otherwise return -1.
104int CodeEmitterGen::getVariableBit(const std::string &VarName,
105 const BitsInit *BI, int Bit) {
106 if (const VarBitInit *VBI = dyn_cast<VarBitInit>(Val: BI->getBit(Bit))) {
107 if (const VarInit *VI = dyn_cast<VarInit>(Val: VBI->getBitVar()))
108 if (VI->getName() == VarName)
109 return VBI->getBitNum();
110 } else if (const VarInit *VI = dyn_cast<VarInit>(Val: BI->getBit(Bit))) {
111 if (VI->getName() == VarName)
112 return 0;
113 }
114
115 return -1;
116}
117
118// Returns true if it succeeds, false if an error.
119bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
120 const BitsInit *BI,
121 const std::string &VarName,
122 std::string &Case,
123 std::string &BitOffsetCase) {
124 const CodeGenInstruction &CGI = Target.getInstruction(InstRec: R);
125
126 // Determine if VarName actually contributes to the Inst encoding.
127 int Bit = BI->getNumBits() - 1;
128
129 // Scan for a bit that this contributed to.
130 for (; Bit >= 0;) {
131 if (getVariableBit(VarName, BI, Bit) != -1)
132 break;
133
134 --Bit;
135 }
136
137 // If we found no bits, ignore this value, otherwise emit the call to get the
138 // operand encoding.
139 if (Bit < 0)
140 return true;
141
142 // If the operand matches by name, reference according to that
143 // operand number. Non-matching operands are assumed to be in
144 // order.
145 unsigned OpIdx;
146 if (auto SubOp = CGI.Operands.findSubOperandAlias(Name: VarName)) {
147 OpIdx = CGI.Operands[SubOp->first].MIOperandNo + SubOp->second;
148 } else if (auto MayBeOpIdx = CGI.Operands.findOperandNamed(Name: VarName)) {
149 // Get the machine operand number for the indicated operand.
150 OpIdx = CGI.Operands[*MayBeOpIdx].MIOperandNo;
151 } else {
152 PrintError(Rec: R, Msg: Twine("No operand named ") + VarName + " in record " +
153 R->getName());
154 return false;
155 }
156
157 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(Op: OpIdx);
158 StringRef EncoderMethodName =
159 CGI.Operands[SO.first].EncoderMethodNames[SO.second];
160
161 raw_string_ostream OS(Case);
162 indent Indent(6);
163
164 OS << Indent << "// op: " << VarName << '\n';
165
166 if (UseAPInt)
167 OS << Indent << "op.clearAllBits();\n";
168
169 if (!EncoderMethodName.empty()) {
170 if (UseAPInt)
171 OS << Indent << EncoderMethodName << "(MI, " << OpIdx
172 << ", op, Fixups, STI);\n";
173 else
174 OS << Indent << "op = " << EncoderMethodName << "(MI, " << OpIdx
175 << ", Fixups, STI);\n";
176 } else {
177 if (UseAPInt)
178 OS << Indent << "getMachineOpValue(MI, MI.getOperand(" << OpIdx
179 << "), op, Fixups, STI);\n";
180 else
181 OS << Indent << "op = getMachineOpValue(MI, MI.getOperand(" << OpIdx
182 << "), Fixups, STI);\n";
183 }
184
185 unsigned BitOffset = -1;
186 for (; Bit >= 0;) {
187 int VarBit = getVariableBit(VarName, BI, Bit);
188
189 // If this bit isn't from a variable, skip it.
190 if (VarBit == -1) {
191 --Bit;
192 continue;
193 }
194
195 // Figure out the consecutive range of bits covered by this operand, in
196 // order to generate better encoding code.
197 int BeginInstBit = Bit;
198 int BeginVarBit = VarBit;
199 int N = 1;
200 for (--Bit; Bit >= 0;) {
201 VarBit = getVariableBit(VarName, BI, Bit);
202 if (VarBit == -1 || VarBit != (BeginVarBit - N))
203 break;
204 ++N;
205 --Bit;
206 }
207
208 unsigned LoBit = BeginVarBit - N + 1;
209 unsigned LoInstBit = BeginInstBit - N + 1;
210 BitOffset = LoInstBit;
211 if (UseAPInt) {
212 if (N > 64)
213 OS << Indent << "Value.insertBits(op.extractBits(" << N << ", " << LoBit
214 << "), " << LoInstBit << ");\n";
215 else
216 OS << Indent << "Value.insertBits(op.extractBitsAsZExtValue(" << N
217 << ", " << LoBit << "), " << LoInstBit << ", " << N << ");\n";
218 } else {
219 uint64_t OpMask = maskTrailingOnes<uint64_t>(N) << LoBit;
220 OS << Indent << "Value |= (op & " << format_hex(N: OpMask, Width: 0) << ')';
221 int OpShift = BeginInstBit - BeginVarBit;
222 if (OpShift > 0)
223 OS << " << " << OpShift;
224 else if (OpShift < 0)
225 OS << " >> " << -OpShift;
226 OS << ";\n";
227 }
228 }
229
230 if (BitOffset != (unsigned)-1) {
231 BitOffsetCase += " case " + utostr(X: OpIdx) + ":\n";
232 BitOffsetCase += " // op: " + VarName + "\n";
233 BitOffsetCase += " return " + utostr(X: BitOffset) + ";\n";
234 }
235
236 return true;
237}
238
239static void emitCaseMap(raw_ostream &O, const CaseMapT &CaseMap,
240 function_ref<void(raw_ostream &, unsigned)> PrintCase) {
241 for (const auto &[CaseBody, Cases] : CaseMap) {
242 ListSeparator LS("\n");
243 for (unsigned Case : Cases) {
244 O << LS << " case ";
245 PrintCase(O, Case);
246 O << ":";
247 }
248 O << " {\n";
249 O << CaseBody;
250 O << " break;\n"
251 << " }\n";
252 }
253}
254
255std::pair<std::string, std::string>
256CodeEmitterGen::getInstructionCases(const Record *R) {
257 std::string Case, BitOffsetCase;
258
259 auto Append = [&](const std::string &S) {
260 Case += S;
261 BitOffsetCase += S;
262 };
263
264 if (const Record *RV = R->getValueAsOptionalDef(FieldName: "EncodingInfos")) {
265 EncodingInfoByHwMode EBM(RV, CGH);
266
267 // Invoke the interface to obtain the HwMode ID controlling the
268 // EncodingInfo for the current subtarget. This interface will
269 // mask off irrelevant HwMode IDs.
270 Append(" unsigned HwMode = "
271 "STI.getHwMode(MCSubtargetInfo::HwMode_EncodingInfo);\n");
272 Case += " switch (HwMode) {\n";
273 Case += " default: llvm_unreachable(\"Unknown hardware mode!\"); "
274 "break;\n";
275 std::string InstBitsTableName =
276 BaseEncodings.empty() ? "InstBits" : "InstBitsIndices";
277 for (auto &[ModeId, Encoding] : EBM) {
278 if (ModeId == DefaultMode) {
279 Case += " case " + itostr(X: DefaultMode) + ": " + InstBitsTableName +
280 "ByHw = " + InstBitsTableName;
281 } else {
282 Case += " case " + itostr(X: ModeId) + ": " + InstBitsTableName +
283 "ByHw = " + InstBitsTableName + "_" +
284 CGH.getModeName(Id: ModeId).str();
285 }
286 Case += "; break;\n";
287 }
288 Case += " };\n";
289
290 // Reload Inst from the selected HwMode table.
291 if (UseAPInt) {
292 if (BaseEncodings.empty()) {
293 int NumWords = APInt::getNumWords(BitWidth);
294 Case += " Inst = APInt(" + itostr(X: BitWidth);
295 Case += ", ArrayRef(InstBitsByHw + TableIndex * " + itostr(X: NumWords) +
296 ", " + itostr(X: NumWords);
297 Case += "));\n";
298 } else {
299 Case += " InstBitsIndex = InstBitsIndicesByHw[TableIndex];\n";
300 Case += " Inst = APInt(" + itostr(X: BitWidth) +
301 ", ArrayRef(InstBits[InstBitsIndex]));\n";
302 }
303 Case += " Value = Inst;\n";
304 } else {
305 Case += " Value = InstBitsByHw[TableIndex];\n";
306 }
307
308 Append(" switch (HwMode) {\n");
309 Append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
310
311 // Attempt to unique the per-hw-mode encoding case statements. This helps
312 // reduce the code size if 2 or more hw-modes share the same encoding for
313 // the fields of the instruction.
314 CaseMapT CaseMap, BitOffsetCaseMap;
315 std::string ModeCase, ModeBitOffsetCase;
316
317 auto PrintHWMode = [](raw_ostream &O, unsigned Mode) { O << Mode; };
318
319 for (auto &[ModeId, Encoding] : EBM) {
320 ModeCase.clear();
321 ModeBitOffsetCase.clear();
322 addInstructionCasesForEncoding(R, EncodingDef: Encoding, Case&: ModeCase, BitOffsetCase&: ModeBitOffsetCase);
323 CaseMap[ModeCase].push_back(x: ModeId);
324 BitOffsetCaseMap[ModeBitOffsetCase].push_back(x: ModeId);
325 }
326
327 raw_string_ostream CaseOS(Case);
328 raw_string_ostream BitOffsetCaseOS(BitOffsetCase);
329 emitCaseMap(O&: CaseOS, CaseMap, PrintCase: PrintHWMode);
330 emitCaseMap(O&: BitOffsetCaseOS, CaseMap: BitOffsetCaseMap, PrintCase: PrintHWMode);
331
332 Append(" }\n");
333 return {std::move(Case), std::move(BitOffsetCase)};
334 }
335 addInstructionCasesForEncoding(R, EncodingDef: R, Case, BitOffsetCase);
336 return {std::move(Case), std::move(BitOffsetCase)};
337}
338
339void CodeEmitterGen::addInstructionCasesForEncoding(
340 const Record *R, const Record *EncodingDef, std::string &Case,
341 std::string &BitOffsetCase) {
342 const BitsInit *BI = EncodingDef->getValueAsBitsInit(FieldName: "Inst");
343
344 // Loop over all of the fields in the instruction, determining which are the
345 // operands to the instruction.
346 bool Success = true;
347 size_t OrigBitOffsetCaseSize = BitOffsetCase.size();
348 BitOffsetCase += " switch (OpNum) {\n";
349 size_t BitOffsetCaseSizeBeforeLoop = BitOffsetCase.size();
350 for (const RecordVal &RV : EncodingDef->getValues()) {
351 // Ignore fixed fields in the record, we're looking for values like:
352 // bits<5> RST = { ?, ?, ?, ?, ? };
353 if (RV.isNonconcreteOK() || RV.getValue()->isComplete())
354 continue;
355
356 Success &=
357 addCodeToMergeInOperand(R, BI, VarName: RV.getName().str(), Case, BitOffsetCase);
358 }
359 // Avoid empty switches.
360 if (BitOffsetCase.size() == BitOffsetCaseSizeBeforeLoop)
361 BitOffsetCase.resize(n: OrigBitOffsetCaseSize);
362 else
363 BitOffsetCase += " }\n";
364
365 if (!Success) {
366 // Dump the record, so we can see what's going on...
367 std::string E;
368 raw_string_ostream S(E);
369 S << "Dumping record for previous error:\n";
370 S << *R;
371 PrintNote(Msg: E);
372 }
373
374 StringRef PostEmitter = R->getValueAsString(FieldName: "PostEncoderMethod");
375 if (!PostEmitter.empty()) {
376 Case += " Value = ";
377 Case += PostEmitter;
378 Case += "(MI, Value";
379 Case += ", STI";
380 Case += ");\n";
381 }
382}
383
384static void emitInstBits(raw_ostream &OS, const APInt &Bits) {
385 for (unsigned I = 0; I < Bits.getNumWords(); ++I)
386 OS << ((I > 0) ? ", " : "") << "UINT64_C(" << Bits.getRawData()[I] << ")";
387}
388
389APInt CodeEmitterGen::getInstructionBaseValue(const CodeGenInstruction *CGI,
390 unsigned HwMode) {
391 const Record *R = CGI->TheDef;
392 const Record *EncodingDef = R;
393 if (const Record *RV = R->getValueAsOptionalDef(FieldName: "EncodingInfos")) {
394 EncodingInfoByHwMode EBM(RV, CGH);
395 if (!EBM.hasMode(M: HwMode))
396 return APInt(BitWidth, 0);
397 EncodingDef = EBM.get(Mode: HwMode);
398 }
399
400 const BitsInit *BI = EncodingDef->getValueAsBitsInit(FieldName: "Inst");
401 APInt Value(BitWidth, 0);
402 for (unsigned I = 0, E = BI->getNumBits(); I != E; ++I) {
403 if (const auto *B = dyn_cast<BitInit>(Val: BI->getBit(Bit: I)); B && B->getValue())
404 Value.setBit(I);
405 }
406 return Value;
407}
408
409void CodeEmitterGen::buildBaseEncodingPool(
410 ArrayRef<const CodeGenInstruction *> NumberedInstructions,
411 const std::set<unsigned> &HwModes) {
412 assert(UseAPInt && "pooling is only used for multiword encodings");
413
414 const unsigned NumWords = APInt::getNumWords(BitWidth);
415 DenseMap<APInt, unsigned> ValueToIndex;
416 BaseEncodings.IndicesByHwMode.try_emplace(k: DefaultMode);
417 for (unsigned HwMode : HwModes)
418 BaseEncodings.IndicesByHwMode.try_emplace(k: HwMode);
419
420 for (auto &[HwMode, Indices] : BaseEncodings.IndicesByHwMode) {
421 for (const CodeGenInstruction *CGI : NumberedInstructions) {
422 APInt Value = getInstructionBaseValue(CGI, HwMode);
423 auto [It, Inserted] =
424 ValueToIndex.try_emplace(Key: Value, Args: BaseEncodings.Values.size());
425 if (Inserted)
426 BaseEncodings.Values.push_back(x: std::move(Value));
427 Indices.push_back(x: It->second);
428 }
429 }
430
431 const uint64_t NumValues = BaseEncodings.Values.size();
432 BaseEncodings.IndexBitWidth =
433 std::max<uint64_t>(a: 8, b: PowerOf2Ceil(A: Log2_64_Ceil(Value: NumValues)));
434 if (BaseEncodings.IndexBitWidth > 32) {
435 BaseEncodings = {};
436 return;
437 }
438
439 const uint64_t NumTables = BaseEncodings.IndicesByHwMode.size();
440 const uint64_t RawSize =
441 NumTables * NumberedInstructions.size() * NumWords * sizeof(uint64_t);
442 const uint64_t PooledSize = NumValues * NumWords * sizeof(uint64_t) +
443 NumTables * NumberedInstructions.size() *
444 (BaseEncodings.IndexBitWidth / 8);
445 if (PooledSize >= RawSize)
446 BaseEncodings = {};
447}
448
449void CodeEmitterGen::emitBaseEncodingPool(raw_ostream &O) {
450 const unsigned NumWords = APInt::getNumWords(BitWidth);
451 O << " static const uint64_t InstBits[][" << NumWords << "] = {\n";
452 for (const APInt &Value : BaseEncodings.Values) {
453 O << " {";
454 emitInstBits(OS&: O, Bits: Value);
455 O << "},\n";
456 }
457 O << " };\n";
458
459 for (const auto &[HwMode, Indices] : BaseEncodings.IndicesByHwMode) {
460 O << formatv(Fmt: " static const uint{}_t InstBitsIndices",
461 Vals&: BaseEncodings.IndexBitWidth);
462 if (HwMode != DefaultMode)
463 O << "_" << CGH.getModeName(Id: HwMode);
464 O << "[] = {\n";
465 for (unsigned Index : Indices)
466 O << " " << Index << ",\n";
467 O << " };\n";
468 }
469 O << " static_assert(sizeof(InstBits) / sizeof(InstBits[0]) <=\n"
470 " (UINT64_C(1) << (sizeof(InstBitsIndices[0]) * 8)));\n";
471}
472
473void CodeEmitterGen::emitInstructionBaseValues(
474 raw_ostream &O, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
475 unsigned HwMode) {
476 if (HwMode == DefaultMode)
477 O << " static const uint64_t InstBits[] = {\n";
478 else
479 O << " static const uint64_t InstBits_" << CGH.getModeName(Id: HwMode)
480 << "[] = {\n";
481
482 for (const CodeGenInstruction *CGI : NumberedInstructions) {
483 const Record *R = CGI->TheDef;
484 APInt Value = getInstructionBaseValue(CGI, HwMode);
485 O << " ";
486 emitInstBits(OS&: O, Bits: Value);
487 O << "," << '\t' << "// " << R->getName() << "\n";
488 }
489 O << " };\n";
490}
491
492CodeEmitterGen::CodeEmitterGen(const RecordKeeper &RK)
493 : RK(RK), Target(RK), CGH(Target.getHwModes()) {
494 // For little-endian instruction bit encodings, reverse the bit order.
495 Target.reverseBitsForLittleEndianEncoding();
496}
497
498void CodeEmitterGen::run(raw_ostream &O) {
499 emitSourceFileHeader(Desc: "Machine Code Emitter", OS&: O);
500
501 ArrayRef<const CodeGenInstruction *> EncodedInstructions =
502 Target.getTargetNonPseudoInstructions();
503
504 if (Target.hasVariableLengthEncodings()) {
505 emitVarLenCodeEmitter(R: RK, OS&: O);
506 return;
507 }
508 // The set of HwModes used by instruction encodings.
509 std::set<unsigned> HwModes;
510 BitWidth = 0;
511 for (const CodeGenInstruction *CGI : EncodedInstructions) {
512 const Record *R = CGI->TheDef;
513 if (const Record *RV = R->getValueAsOptionalDef(FieldName: "EncodingInfos")) {
514 EncodingInfoByHwMode EBM(RV, CGH);
515 for (const auto &[Key, Value] : EBM) {
516 const BitsInit *BI = Value->getValueAsBitsInit(FieldName: "Inst");
517 BitWidth = std::max(a: BitWidth, b: BI->getNumBits());
518 HwModes.insert(x: Key);
519 }
520 continue;
521 }
522 const BitsInit *BI = R->getValueAsBitsInit(FieldName: "Inst");
523 BitWidth = std::max(a: BitWidth, b: BI->getNumBits());
524 }
525 UseAPInt = BitWidth > 64;
526 if (UseAPInt)
527 buildBaseEncodingPool(NumberedInstructions: EncodedInstructions, HwModes);
528
529 // Emit function declaration
530 if (UseAPInt) {
531 O << "void " << Target.getName()
532 << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
533 << " SmallVectorImpl<MCFixup> &Fixups,\n"
534 << " APInt &Inst,\n"
535 << " APInt &Scratch,\n"
536 << " const MCSubtargetInfo &STI) const {\n";
537 } else {
538 O << "uint64_t " << Target.getName();
539 O << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
540 << " SmallVectorImpl<MCFixup> &Fixups,\n"
541 << " const MCSubtargetInfo &STI) const {\n";
542 }
543
544 // Emit instruction base values
545 if (BaseEncodings.empty()) {
546 emitInstructionBaseValues(O, NumberedInstructions: EncodedInstructions, HwMode: DefaultMode);
547 for (unsigned HwMode : HwModes) {
548 if (HwMode == DefaultMode)
549 continue;
550 emitInstructionBaseValues(O, NumberedInstructions: EncodedInstructions, HwMode);
551 }
552 } else {
553 emitBaseEncodingPool(O);
554 }
555
556 if (!HwModes.empty()) {
557 // This pointer will be assigned to the HwMode table later.
558 if (BaseEncodings.empty())
559 O << " const uint64_t *InstBitsByHw;\n";
560 else
561 O << formatv(Fmt: " const uint{0}_t *InstBitsIndicesByHw;\n",
562 Vals&: BaseEncodings.IndexBitWidth);
563 }
564
565 // Map to accumulate all the cases.
566 CaseMapT CaseMap, BitOffsetCaseMap;
567
568 // Construct all cases statement for each opcode
569 for (auto [Index, CGI] : enumerate(First&: EncodedInstructions)) {
570 const Record *R = CGI->TheDef;
571 auto [Case, BitOffsetCase] = getInstructionCases(R);
572
573 CaseMap[Case].push_back(x: Index);
574 BitOffsetCaseMap[BitOffsetCase].push_back(x: Index);
575 }
576
577 auto PrintInstName = [&](raw_ostream &OS, unsigned Index) {
578 const CodeGenInstruction *CGI = EncodedInstructions[Index];
579 const Record *R = CGI->TheDef;
580 OS << R->getValueAsString(FieldName: "Namespace") << "::" << R->getName();
581 };
582
583 unsigned FirstSupportedOpcode = EncodedInstructions.front()->EnumVal;
584 O << " constexpr unsigned FirstSupportedOpcode = " << FirstSupportedOpcode
585 << ";\n";
586 O << R"(
587 const unsigned opcode = MI.getOpcode();
588 if (opcode < FirstSupportedOpcode)
589 reportUnsupportedInst(MI);
590 unsigned TableIndex = opcode - FirstSupportedOpcode;
591)";
592
593 // Emit initial function code
594 if (UseAPInt) {
595 int NumWords = APInt::getNumWords(BitWidth);
596 O << " if (Scratch.getBitWidth() != " << BitWidth << ")\n"
597 << " Scratch = Scratch.zext(" << BitWidth << ");\n";
598 if (BaseEncodings.empty()) {
599 O << " Inst = APInt(" << BitWidth
600 << ", ArrayRef(InstBits + TableIndex * " << NumWords << ", " << NumWords
601 << "));\n";
602 } else {
603 O << " unsigned InstBitsIndex = InstBitsIndices[TableIndex];\n"
604 << " Inst = APInt(" << BitWidth
605 << ", ArrayRef(InstBits[InstBitsIndex]));\n";
606 }
607 O << " APInt &Value = Inst;\n"
608 << " APInt &op = Scratch;\n"
609 << " switch (opcode) {\n";
610 } else {
611 O << " uint64_t Value = InstBits[TableIndex];\n"
612 << " uint64_t op = 0;\n"
613 << " (void)op; // suppress warning\n"
614 << " switch (opcode) {\n";
615 }
616
617 // Emit each case statement
618 emitCaseMap(O, CaseMap, PrintCase: PrintInstName);
619
620 // Default case: unhandled opcode.
621 O << " default:\n"
622 << " reportUnsupportedInst(MI);\n"
623 << " }\n";
624 if (UseAPInt)
625 O << " Inst = Value;\n";
626 else
627 O << " return Value;\n";
628 O << "}\n\n";
629
630 IfDefEmitter IfDef(O, "GET_OPERAND_BIT_OFFSET");
631 O << "uint32_t " << Target.getName()
632 << "MCCodeEmitter::getOperandBitOffset(const MCInst &MI,\n"
633 << " unsigned OpNum,\n"
634 << " const MCSubtargetInfo &STI) const {\n"
635 << " switch (MI.getOpcode()) {\n";
636 emitCaseMap(O, CaseMap: BitOffsetCaseMap, PrintCase: PrintInstName);
637 O << " default:\n"
638 << " reportUnsupportedInst(MI);\n"
639 << " }\n"
640 << " reportUnsupportedOperand(MI, OpNum);\n"
641 << "}\n";
642}
643
644static TableGen::Emitter::OptClass<CodeEmitterGen>
645 X("gen-emitter", "Generate machine code emitter");
646