1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend is responsible for emitting a description of the target
10// instruction set for the code generator.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Basic/SequenceToOffsetTable.h"
15#include "Common/CodeGenDAGPatterns.h"
16#include "Common/CodeGenInstruction.h"
17#include "Common/CodeGenRegisters.h"
18#include "Common/CodeGenSchedule.h"
19#include "Common/CodeGenTarget.h"
20#include "Common/PredicateExpander.h"
21#include "Common/SubtargetFeatureInfo.h"
22#include "Common/Types.h"
23#include "TableGenBackends.h"
24#include "llvm/ADT/ArrayRef.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/StringExtras.h"
28#include "llvm/Support/Casting.h"
29#include "llvm/Support/Format.h"
30#include "llvm/Support/SourceMgr.h"
31#include "llvm/Support/raw_ostream.h"
32#include "llvm/TableGen/CodeGenHelpers.h"
33#include "llvm/TableGen/Error.h"
34#include "llvm/TableGen/Record.h"
35#include "llvm/TableGen/TGTimer.h"
36#include "llvm/TableGen/TableGenBackend.h"
37#include <cassert>
38#include <cstdint>
39#include <iterator>
40#include <map>
41#include <string>
42#include <utility>
43#include <vector>
44
45using namespace llvm;
46
47static cl::OptionCategory InstrInfoEmitterCat("Options for -gen-instr-info");
48static cl::opt<bool> ExpandMIOperandInfo(
49 "instr-info-expand-mi-operand-info",
50 cl::desc("Expand operand's MIOperandInfo DAG into suboperands"),
51 cl::cat(InstrInfoEmitterCat), cl::init(Val: true));
52
53namespace {
54
55class InstrInfoEmitter {
56 const RecordKeeper &Records;
57 const CodeGenDAGPatterns CDP;
58 const CodeGenSchedModels &SchedModels;
59
60public:
61 InstrInfoEmitter(const RecordKeeper &R)
62 : Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
63
64 // run - Output the instruction set description.
65 void run(raw_ostream &OS);
66
67private:
68 void emitEnums(raw_ostream &OS,
69 ArrayRef<const CodeGenInstruction *> NumberedInstructions);
70
71 using OperandInfoTy = std::vector<std::string>;
72 using OperandInfoListTy = std::vector<OperandInfoTy>;
73 using OperandInfoMapTy = std::map<OperandInfoTy, unsigned>;
74
75 DenseMap<const CodeGenInstruction *, const CodeGenInstruction *>
76 TargetSpecializedPseudoInsts;
77
78 /// Compute mapping of opcodes which should have their definitions overridden
79 /// by a target version.
80 void buildTargetSpecializedPseudoInstsMap();
81
82 /// Generate member functions in the target-specific GenInstrInfo class.
83 ///
84 /// This method is used to custom expand TIIPredicate definitions.
85 /// See file llvm/Target/TargetInstPredicates.td for a description of what is
86 /// a TIIPredicate and how to use it.
87 void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName,
88 bool ExpandDefinition = true);
89
90 /// Expand TIIPredicate definitions to functions that accept a const MCInst
91 /// reference.
92 void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
93
94 /// Write verifyInstructionPredicates methods.
95 void emitFeatureVerifier(raw_ostream &OS, const CodeGenTarget &Target);
96 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
97 const Record *InstrInfo,
98 std::map<std::vector<const Record *>, unsigned> &EL,
99 const OperandInfoMapTy &OperandInfo, raw_ostream &OS);
100 void emitOperandTypeMappings(
101 raw_ostream &OS, const CodeGenTarget &Target,
102 ArrayRef<const CodeGenInstruction *> NumberedInstructions);
103 void emitOperandNameMappings(
104 raw_ostream &OS, const CodeGenTarget &Target,
105 ArrayRef<const CodeGenInstruction *> TargetInstructions);
106 void emitLogicalOperandSizeMappings(
107 raw_ostream &OS, StringRef Namespace,
108 ArrayRef<const CodeGenInstruction *> TargetInstructions);
109
110 // Operand information.
111 unsigned CollectOperandInfo(OperandInfoListTy &OperandInfoList,
112 OperandInfoMapTy &OperandInfoMap);
113 void EmitOperandInfo(raw_ostream &OS, OperandInfoListTy &OperandInfoList);
114 OperandInfoTy GetOperandInfo(const CodeGenInstruction &Inst);
115};
116
117} // end anonymous namespace
118
119//===----------------------------------------------------------------------===//
120// Operand Info Emission.
121//===----------------------------------------------------------------------===//
122
123InstrInfoEmitter::OperandInfoTy
124InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
125 OperandInfoTy Result;
126 StringRef Namespace = CDP.getTargetInfo().getInstNamespace();
127
128 for (auto &Op : Inst.Operands) {
129 // Handle aggregate operands and normal operands the same way by expanding
130 // either case into a list of operands for this op.
131 std::vector<CGIOperandList::OperandInfo> OperandList;
132
133 // This might be a multiple operand thing. Targets like X86 have registers
134 // in their multi-operand operands. It may also be an anonymous operand,
135 // which has a single operand, but no declared class for the operand.
136 const DagInit *MIOI = Op.MIOperandInfo;
137
138 if (!MIOI || MIOI->getNumArgs() == 0) {
139 // Single, anonymous, operand.
140 OperandList.push_back(x: Op);
141 } else {
142 for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
143 OperandList.push_back(x: Op);
144
145 auto *OpR = cast<DefInit>(Val: MIOI->getArg(Num: j))->getDef();
146 OperandList.back().Rec = OpR;
147 }
148 }
149
150 for (const auto &[OpInfo, Constraint] :
151 zip_equal(t&: OperandList, u: Op.Constraints)) {
152 const Record *OpR = OpInfo.Rec;
153 std::string Res;
154
155 if (OpR->isSubClassOf(Name: "RegisterOperand"))
156 OpR = OpR->getValueAsDef(FieldName: "RegClass");
157
158 if (OpR->isSubClassOf(Name: "RegClassByHwMode")) {
159 Res += Namespace;
160 Res += "::";
161 Res += OpR->getName();
162 Res += ", ";
163 } else if (OpR->isSubClassOf(Name: "RegisterClass"))
164 Res += getQualifiedName(R: OpR) + "RegClassID, ";
165 else if (OpR->isSubClassOf(Name: "PointerLikeRegClass")) {
166 if (Inst.isPseudo) {
167 // TODO: Verify this is a fixed pseudo
168 PrintError(Rec: Inst.TheDef,
169 Msg: "missing target override for pseudoinstruction "
170 "using PointerLikeRegClass");
171 PrintNote(NoteLoc: OpR->getLoc(),
172 Msg: "target should define equivalent instruction "
173 "with RegisterClassLike replacement; (use "
174 "RemapAllTargetPseudoPointerOperands?)");
175 } else {
176 PrintError(Rec: Inst.TheDef,
177 Msg: "non-pseudoinstruction user of PointerLikeRegClass");
178 }
179 } else
180 // -1 means the operand does not have a fixed register class.
181 Res += "-1, ";
182
183 // Fill in applicable flags.
184 Res += "0";
185
186 if (OpR->isSubClassOf(Name: "RegClassByHwMode"))
187 Res += "|(1<<MCOI::LookupRegClassByHwMode)";
188
189 // Predicate operands. Check to see if the original unexpanded operand
190 // was of type PredicateOp.
191 if (Op.Rec->isSubClassOf(Name: "PredicateOp"))
192 Res += "|(1<<MCOI::Predicate)";
193
194 // Optional def operands. Check to see if the original unexpanded operand
195 // was of type OptionalDefOperand.
196 if (Op.Rec->isSubClassOf(Name: "OptionalDefOperand"))
197 Res += "|(1<<MCOI::OptionalDef)";
198
199 // Branch target operands. Check to see if the original unexpanded
200 // operand was of type BranchTargetOperand.
201 if (Op.Rec->isSubClassOf(Name: "BranchTargetOperand"))
202 Res += "|(1<<MCOI::BranchTarget)";
203
204 // Fill in operand type.
205 Res += ", ";
206 assert(!Op.OperandType.empty() && "Invalid operand type.");
207 Res += Op.OperandType;
208
209 // Fill in constraint info.
210 Res += ", ";
211
212 if (Constraint.isNone()) {
213 Res += "0";
214 } else if (Constraint.isEarlyClobber()) {
215 Res += "MCOI_EARLY_CLOBBER";
216 } else {
217 assert(Constraint.isTied());
218 Res += "MCOI_TIED_TO(" + utostr(X: Constraint.getTiedOperand()) + ")";
219 }
220
221 Result.push_back(x: Res);
222 }
223 }
224
225 return Result;
226}
227
228unsigned
229InstrInfoEmitter::CollectOperandInfo(OperandInfoListTy &OperandInfoList,
230 OperandInfoMapTy &OperandInfoMap) {
231 const CodeGenTarget &Target = CDP.getTargetInfo();
232 unsigned Offset = 0;
233 for (const CodeGenInstruction *Inst : Target.getInstructions()) {
234 auto OverrideEntry = TargetSpecializedPseudoInsts.find(Val: Inst);
235 if (OverrideEntry != TargetSpecializedPseudoInsts.end())
236 Inst = OverrideEntry->second;
237
238 OperandInfoTy OperandInfo = GetOperandInfo(Inst: *Inst);
239 if (OperandInfoMap.try_emplace(k: OperandInfo, args&: Offset).second) {
240 OperandInfoList.push_back(x: OperandInfo);
241 Offset += OperandInfo.size();
242 }
243 }
244 return Offset;
245}
246
247void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
248 OperandInfoListTy &OperandInfoList) {
249 unsigned Offset = 0;
250 for (auto &OperandInfo : OperandInfoList) {
251 OS << " /* " << Offset << " */";
252 for (auto &Info : OperandInfo)
253 OS << " { " << Info << " },";
254 OS << '\n';
255 Offset += OperandInfo.size();
256 }
257}
258
259static void emitGetInstructionIndexForOpLookup(
260 raw_ostream &OS, const MapVector<SmallVector<int>, unsigned> &OperandMap,
261 ArrayRef<unsigned> InstructionIndex) {
262 StringRef Type = OperandMap.size() <= UINT8_MAX + 1 ? "uint8_t" : "uint16_t";
263 OS << "LLVM_READONLY static " << Type
264 << " getInstructionIndexForOpLookup(uint16_t Opcode) {\n"
265 " static constexpr "
266 << Type << " InstructionIndex[] = {";
267 for (auto [TableIndex, Entry] : enumerate(First&: InstructionIndex))
268 OS << (TableIndex % 16 == 0 ? "\n " : " ") << Entry << ',';
269 OS << "\n };\n"
270 " return InstructionIndex[Opcode];\n"
271 "}\n";
272}
273
274static void
275emitGetNamedOperandIdx(raw_ostream &OS,
276 const MapVector<SmallVector<int>, unsigned> &OperandMap,
277 unsigned MaxOperandNo, unsigned NumOperandNames) {
278 OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName "
279 "Name) {\n";
280 OS << " assert(Name != OpName::NUM_OPERAND_NAMES);\n";
281 if (!NumOperandNames) {
282 // There are no operands, so no need to emit anything
283 OS << " return -1;\n}\n";
284 return;
285 }
286 assert(MaxOperandNo <= INT16_MAX &&
287 "Too many operands for the operand name -> index table");
288 StringRef Type = MaxOperandNo <= INT8_MAX ? "int8_t" : "int16_t";
289 OS << " static constexpr " << Type << " OperandMap[][" << NumOperandNames
290 << "] = {\n";
291 for (const auto &[OpList, _] : OperandMap) {
292 // Emit a row of the OperandMap table.
293 OS << " {";
294 for (unsigned ID = 0; ID < NumOperandNames; ++ID)
295 OS << (ID < OpList.size() ? OpList[ID] : -1) << ", ";
296 OS << "},\n";
297 }
298 OS << " };\n";
299
300 OS << " unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);\n"
301 " return OperandMap[InstrIdx][(unsigned)Name];\n"
302 "}\n";
303}
304
305static void
306emitGetOperandIdxName(raw_ostream &OS,
307 const MapVector<StringRef, unsigned> &OperandNameToID,
308 const MapVector<SmallVector<int>, unsigned> &OperandMap,
309 unsigned MaxNumOperands, unsigned NumOperandNames) {
310 OS << "LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) "
311 "{\n";
312 OS << " assert(Idx >= 0 && Idx < " << MaxNumOperands << ");\n";
313 if (!MaxNumOperands) {
314 // There are no operands, so no need to emit anything
315 OS << " return -1;\n}\n";
316 return;
317 }
318 OS << " static constexpr OpName OperandMap[][" << MaxNumOperands
319 << "] = {\n";
320 for (const auto &[OpList, _] : OperandMap) {
321 SmallVector<unsigned> IDs(MaxNumOperands, NumOperandNames);
322 for (const auto &[ID, Idx] : enumerate(First: OpList)) {
323 if (Idx >= 0)
324 IDs[Idx] = ID;
325 }
326 // Emit a row of the OperandMap table. Map operand indices to enum values.
327 OS << " {";
328 for (unsigned ID : IDs) {
329 if (ID == NumOperandNames)
330 OS << "OpName::NUM_OPERAND_NAMES, ";
331 else
332 OS << "OpName::" << OperandNameToID.getArrayRef()[ID].first << ", ";
333 }
334 OS << "},\n";
335 }
336 OS << " };\n";
337
338 OS << " unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);\n"
339 " return OperandMap[InstrIdx][(unsigned)Idx];\n"
340 "}\n";
341}
342
343/// Generate a table and function for looking up the indices of operands by
344/// name.
345///
346/// This code generates:
347/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
348/// for each operand name.
349/// - A 2-dimensional table for mapping OpName enum values to operand indices.
350/// - A function called getNamedOperandIdx(uint16_t Opcode, OpName Name)
351/// for looking up the operand index for an instruction, given a value from
352/// OpName enum
353/// - A 2-dimensional table for mapping operand indices to OpName enum values.
354/// - A function called getOperandIdxName(uint16_t Opcode, int16_t Idx)
355/// for looking up the OpName enum for an instruction, given the operand
356/// index. This is the inverse of getNamedOperandIdx().
357///
358/// Fixed/Predefined instructions do not have UseNamedOperandTable enabled, so
359/// we can just skip them. Hence accept just the TargetInstructions.
360void InstrInfoEmitter::emitOperandNameMappings(
361 raw_ostream &OS, const CodeGenTarget &Target,
362 ArrayRef<const CodeGenInstruction *> TargetInstructions) {
363 // Map of operand names to their ID.
364 MapVector<StringRef, unsigned> OperandNameToID;
365
366 /// A key in this map is a vector mapping OpName ID values to instruction
367 /// operand indices or -1 (but without any trailing -1 values which will be
368 /// added later). The corresponding value in this map is the index of that row
369 /// in the emitted OperandMap table. This map helps to unique entries among
370 /// instructions that have identical OpName -> Operand index mapping.
371 MapVector<SmallVector<int>, unsigned> OperandMap;
372
373 // Max operand index seen.
374 unsigned MaxOperandNo = 0;
375
376 // Fixed/Predefined instructions do not have UseNamedOperandTable enabled, so
377 // add a dummy map entry for them.
378 OperandMap.try_emplace(Key: {}, Args: 0);
379 unsigned FirstTargetVal = TargetInstructions.front()->EnumVal;
380 SmallVector<unsigned> InstructionIndex(FirstTargetVal, 0);
381 for (const CodeGenInstruction *Inst : TargetInstructions) {
382 if (!Inst->TheDef->getValueAsBit(FieldName: "UseNamedOperandTable")) {
383 InstructionIndex.push_back(Elt: 0);
384 continue;
385 }
386 SmallVector<int> OpList;
387 for (const auto &Info : Inst->Operands) {
388 unsigned ID =
389 OperandNameToID.try_emplace(Key: Info.Name, Args: OperandNameToID.size())
390 .first->second;
391 OpList.resize(N: std::max(a: (unsigned)OpList.size(), b: ID + 1), NV: -1);
392 OpList[ID] = Info.MIOperandNo;
393 MaxOperandNo = std::max(a: MaxOperandNo, b: Info.MIOperandNo);
394 }
395 auto [It, Inserted] =
396 OperandMap.try_emplace(Key: std::move(OpList), Args: OperandMap.size());
397 InstructionIndex.push_back(Elt: It->second);
398 }
399
400 const size_t NumOperandNames = OperandNameToID.size();
401 const unsigned MaxNumOperands = MaxOperandNo + 1;
402
403 const SmallString<32> Namespace({"llvm::", Target.getInstNamespace()});
404 {
405 IfDefEmitter IfDef(OS, "GET_INSTRINFO_OPERAND_ENUM");
406 NamespaceEmitter NS(OS, Namespace);
407
408 assert(NumOperandNames <= UINT16_MAX &&
409 "Too many operands for the operand index -> name table");
410 StringRef EnumType = getMinimalTypeForRange(Range: NumOperandNames);
411 OS << "enum class OpName : " << EnumType << " {\n";
412 for (const auto &[Op, I] : OperandNameToID)
413 OS << " " << Op << " = " << I << ",\n";
414 OS << " NUM_OPERAND_NAMES = " << NumOperandNames << ",\n";
415 OS << "}; // enum class OpName\n\n";
416
417 OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName "
418 "Name);\n";
419 OS << "LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t "
420 "Idx);\n";
421 }
422
423 {
424 IfDefEmitter IfDef(OS, "GET_INSTRINFO_NAMED_OPS");
425 NamespaceEmitter NS(OS, Namespace);
426 emitGetInstructionIndexForOpLookup(OS, OperandMap, InstructionIndex);
427
428 emitGetNamedOperandIdx(OS, OperandMap, MaxOperandNo, NumOperandNames);
429 emitGetOperandIdxName(OS, OperandNameToID, OperandMap, MaxNumOperands,
430 NumOperandNames);
431 }
432}
433
434/// Generate an enum for all the operand types for this target, under the
435/// llvm::TargetNamespace::OpTypes namespace.
436/// Operand types are all definitions derived of the Operand Target.td class.
437///
438void InstrInfoEmitter::emitOperandTypeMappings(
439 raw_ostream &OS, const CodeGenTarget &Target,
440 ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
441 StringRef Namespace = Target.getInstNamespace();
442
443 // These generated functions are used only by the X86 target
444 // (in bolt/lib/Target/X86/X86MCPlusBuilder.cpp). So emit them only
445 // for X86.
446 if (Namespace != "X86")
447 return;
448
449 ArrayRef<const Record *> Operands =
450 Records.getAllDerivedDefinitions(ClassName: "Operand");
451 ArrayRef<const Record *> RegisterOperands =
452 Records.getAllDerivedDefinitions(ClassName: "RegisterOperand");
453 ArrayRef<const Record *> RegisterClasses =
454 Records.getAllDerivedDefinitions(ClassName: "RegisterClass");
455
456 unsigned EnumVal = 0;
457
458 {
459 IfDefEmitter IfDef(OS, "GET_INSTRINFO_OPERAND_TYPES_ENUM");
460 NamespaceEmitter NS(OS, ("llvm::" + Namespace + "::OpTypes").str());
461 OS << "enum OperandType {\n";
462
463 for (ArrayRef<const Record *> RecordsToAdd :
464 {Operands, RegisterOperands, RegisterClasses}) {
465 for (const Record *Op : RecordsToAdd) {
466 if (!Op->isAnonymous())
467 OS << " " << Op->getName() << " = " << EnumVal << ",\n";
468 ++EnumVal;
469 }
470 }
471
472 OS << " OPERAND_TYPE_LIST_END" << "\n};\n";
473 }
474
475 {
476 IfDefEmitter IfDef(OS, "GET_INSTRINFO_OPERAND_TYPE");
477 NamespaceEmitter NS(OS, ("llvm::" + Namespace).str());
478 OS << "LLVM_READONLY\n";
479 OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
480 auto getInstrName = [&](int I) -> StringRef {
481 return NumberedInstructions[I]->getName();
482 };
483 // TODO: Factor out duplicate operand lists to compress the tables.
484 std::vector<size_t> OperandOffsets;
485 std::vector<const Record *> OperandRecords;
486 size_t CurrentOffset = 0;
487 for (const CodeGenInstruction *Inst : NumberedInstructions) {
488 OperandOffsets.push_back(x: CurrentOffset);
489 for (const auto &Op : Inst->Operands) {
490 const DagInit *MIOI = Op.MIOperandInfo;
491 if (!ExpandMIOperandInfo || !MIOI || MIOI->getNumArgs() == 0) {
492 // Single, anonymous, operand.
493 OperandRecords.push_back(x: Op.Rec);
494 ++CurrentOffset;
495 } else {
496 for (const Init *Arg : MIOI->getArgs()) {
497 OperandRecords.push_back(x: cast<DefInit>(Val: Arg)->getDef());
498 ++CurrentOffset;
499 }
500 }
501 }
502 }
503
504 // Emit the table of offsets (indexes) into the operand type table.
505 // Size the unsigned integer offset to save space.
506 assert(OperandRecords.size() <= UINT32_MAX &&
507 "Too many operands for offset table");
508 OS << " static constexpr "
509 << getMinimalTypeForRange(Range: OperandRecords.size());
510 OS << " Offsets[] = {\n";
511 for (const auto &[Idx, Offset] : enumerate(First&: OperandOffsets))
512 OS << " " << Offset << ", // " << getInstrName(Idx) << '\n';
513 OS << " };\n";
514
515 // Add an entry for the end so that we don't need to special case it below.
516 OperandOffsets.push_back(x: OperandRecords.size());
517
518 // Emit the actual operand types in a flat table.
519 // Size the signed integer operand type to save space.
520 assert(EnumVal <= INT16_MAX &&
521 "Too many operand types for operand types table");
522 OS << "\n using namespace OpTypes;\n";
523 OS << " static";
524 OS << (EnumVal <= INT8_MAX ? " constexpr int8_t" : " constexpr int16_t");
525 OS << " OpcodeOperandTypes[] = {";
526 size_t CurOffset = 0;
527 for (auto [Idx, OpR] : enumerate(First&: OperandRecords)) {
528 // We print each Opcode's operands in its own row.
529 if (Idx == OperandOffsets[CurOffset]) {
530 OS << "\n /* " << getInstrName(CurOffset) << " */\n ";
531 while (OperandOffsets[++CurOffset] == Idx)
532 OS << "/* " << getInstrName(CurOffset) << " */\n ";
533 }
534 if ((OpR->isSubClassOf(Name: "Operand") ||
535 OpR->isSubClassOf(Name: "RegisterOperand") ||
536 OpR->isSubClassOf(Name: "RegisterClass")) &&
537 !OpR->isAnonymous())
538 OS << OpR->getName();
539 else
540 OS << -1;
541 OS << ", ";
542 }
543 OS << "\n };\n";
544
545 OS << " return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];\n";
546 OS << "}\n";
547 }
548
549 {
550 IfDefEmitter IfDef(OS, "GET_INSTRINFO_MEM_OPERAND_SIZE");
551 NamespaceEmitter NS(OS, ("llvm::" + Namespace).str());
552
553 OS << "LLVM_READONLY\n";
554 OS << "static int getMemOperandSize(int OpType) {\n";
555 OS << " switch (OpType) {\n";
556 std::map<int, SmallVector<StringRef, 0>> SizeToOperandName;
557 for (const Record *Op : Operands) {
558 if (!Op->isSubClassOf(Name: "X86MemOperand"))
559 continue;
560 if (int Size = Op->getValueAsInt(FieldName: "Size"))
561 SizeToOperandName[Size].push_back(Elt: Op->getName());
562 }
563 OS << " default: return 0;\n";
564 for (const auto &[Size, OperandNames] : SizeToOperandName) {
565 for (const StringRef &OperandName : OperandNames)
566 OS << " case OpTypes::" << OperandName << ":\n";
567 OS << " return " << Size << ";\n\n";
568 }
569 OS << " }\n}\n";
570 }
571}
572
573// Fixed/Predefined instructions do not have UseLogicalOperandMappings
574// enabled, so we can just skip them. Hence accept TargetInstructions.
575void InstrInfoEmitter::emitLogicalOperandSizeMappings(
576 raw_ostream &OS, StringRef Namespace,
577 ArrayRef<const CodeGenInstruction *> TargetInstructions) {
578 std::map<std::vector<unsigned>, unsigned> LogicalOpSizeMap;
579 std::map<unsigned, std::vector<std::string>> InstMap;
580
581 size_t LogicalOpListSize = 0U;
582 std::vector<unsigned> LogicalOpList;
583
584 for (const auto *Inst : TargetInstructions) {
585 if (!Inst->TheDef->getValueAsBit(FieldName: "UseLogicalOperandMappings"))
586 continue;
587
588 LogicalOpList.clear();
589 llvm::transform(Range: Inst->Operands, d_first: std::back_inserter(x&: LogicalOpList),
590 F: [](const CGIOperandList::OperandInfo &Op) -> unsigned {
591 auto *MIOI = Op.MIOperandInfo;
592 if (!MIOI || MIOI->getNumArgs() == 0)
593 return 1;
594 return MIOI->getNumArgs();
595 });
596 LogicalOpListSize = std::max(a: LogicalOpList.size(), b: LogicalOpListSize);
597
598 auto I =
599 LogicalOpSizeMap.try_emplace(k: LogicalOpList, args: LogicalOpSizeMap.size())
600 .first;
601 InstMap[I->second].push_back(x: (Namespace + "::" + Inst->getName()).str());
602 }
603
604 IfDefEmitter IfDef(OS, "GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP");
605 NamespaceEmitter NS(OS, ("llvm::" + Namespace).str());
606 OS << "LLVM_READONLY static unsigned\n";
607 OS << "getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
608 if (!InstMap.empty()) {
609 std::vector<const std::vector<unsigned> *> LogicalOpSizeList(
610 LogicalOpSizeMap.size());
611 for (auto &P : LogicalOpSizeMap) {
612 LogicalOpSizeList[P.second] = &P.first;
613 }
614 OS << " static const unsigned SizeMap[][" << LogicalOpListSize
615 << "] = {\n";
616 for (auto &R : LogicalOpSizeList) {
617 const auto &Row = *R;
618 OS << " {";
619 int i;
620 for (i = 0; i < static_cast<int>(Row.size()); ++i) {
621 OS << Row[i] << ", ";
622 }
623 for (; i < static_cast<int>(LogicalOpListSize); ++i) {
624 OS << "0, ";
625 }
626 OS << "}, \n";
627 }
628 OS << " };\n";
629
630 OS << " switch (Opcode) {\n";
631 OS << " default: return LogicalOpIdx;\n";
632 for (auto &P : InstMap) {
633 auto OpMapIdx = P.first;
634 const auto &Insts = P.second;
635 for (const auto &Inst : Insts) {
636 OS << " case " << Inst << ":\n";
637 }
638 OS << " return SizeMap[" << OpMapIdx << "][LogicalOpIdx];\n";
639 }
640 OS << " }\n";
641 } else {
642 OS << " return LogicalOpIdx;\n";
643 }
644 OS << "}\n";
645
646 OS << "LLVM_READONLY static inline unsigned\n";
647 OS << "getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
648 OS << " auto S = 0U;\n";
649 OS << " for (auto i = 0U; i < LogicalOpIdx; ++i)\n";
650 OS << " S += getLogicalOperandSize(Opcode, i);\n";
651 OS << " return S;\n";
652 OS << "}\n";
653}
654
655void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
656 StringRef TargetName) {
657 ArrayRef<const Record *> TIIPredicates =
658 Records.getAllDerivedDefinitions(ClassName: "TIIPredicate");
659
660 {
661 IfDefEmitter IfDef(OS, "GET_INSTRINFO_MC_HELPER_DECLS");
662 NamespaceEmitter LlvmNS(OS, "llvm");
663 OS << "class MCInst;\n";
664 OS << "class FeatureBitset;\n\n";
665
666 NamespaceEmitter TargetNS(OS, (TargetName + "_MC").str());
667 for (const Record *Rec : TIIPredicates)
668 OS << "bool " << Rec->getValueAsString(FieldName: "FunctionName")
669 << "(const MCInst &MI);\n";
670
671 OS << "void verifyInstructionPredicates(unsigned Opcode, const "
672 "FeatureBitset "
673 "&Features);\n";
674 }
675
676 {
677 IfDefEmitter IfDef(OS, "GET_INSTRINFO_MC_HELPERS");
678 NamespaceEmitter NS(OS, ("llvm::" + TargetName + "_MC").str());
679
680 PredicateExpander PE(TargetName);
681 PE.setExpandForMC(true);
682
683 for (const Record *Rec : TIIPredicates) {
684 OS << "bool " << Rec->getValueAsString(FieldName: "FunctionName");
685 OS << "(const MCInst &MI) {\n";
686
687 OS << PE.getIndent();
688 PE.expandStatement(OS, Rec: Rec->getValueAsDef(FieldName: "Body"));
689 OS << "\n}\n\n";
690 }
691 }
692}
693
694static std::string
695getNameForFeatureBitset(ArrayRef<const Record *> FeatureBitset) {
696 std::string Name = "CEFBS";
697 for (const Record *Feature : FeatureBitset)
698 Name += ("_" + Feature->getName()).str();
699 return Name;
700}
701
702void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
703 const CodeGenTarget &Target) {
704 const auto &All = SubtargetFeatureInfo::getAll(Records);
705 SubtargetFeatureInfoMap SubtargetFeatures;
706 SubtargetFeatures.insert(first: All.begin(), last: All.end());
707
708 OS << "#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) "
709 << "||\\\n"
710 << " defined(GET_AVAILABLE_OPCODE_CHECKER)\n"
711 << "#define GET_COMPUTE_FEATURES\n"
712 << "#endif\n";
713 std::string Namespace = ("llvm::" + Target.getName() + "_MC").str();
714 {
715 IfDefEmitter IfDef(OS, "GET_COMPUTE_FEATURES");
716 NamespaceEmitter NS(OS, Namespace);
717
718 // Emit the subtarget feature enumeration.
719 SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(SubtargetFeatures,
720 OS);
721 // Emit the available features compute function.
722 OS << "inline ";
723 SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
724 TargetName: Target.getName(), ClassName: "", FuncName: "computeAvailableFeatures", SubtargetFeatures,
725 OS);
726
727 std::vector<std::vector<const Record *>> FeatureBitsets;
728 for (const CodeGenInstruction *Inst : Target.getInstructions()) {
729 FeatureBitsets.emplace_back();
730 for (const Record *Predicate :
731 Inst->TheDef->getValueAsListOfDefs(FieldName: "Predicates")) {
732 const auto &I = SubtargetFeatures.find(x: Predicate);
733 if (I != SubtargetFeatures.end())
734 FeatureBitsets.back().push_back(x: I->second.TheDef);
735 }
736 }
737
738 llvm::sort(C&: FeatureBitsets, Comp: [&](ArrayRef<const Record *> A,
739 ArrayRef<const Record *> B) {
740 if (A.size() < B.size())
741 return true;
742 if (A.size() > B.size())
743 return false;
744 for (auto Pair : zip(t&: A, u&: B)) {
745 if (std::get<0>(t&: Pair)->getName() < std::get<1>(t&: Pair)->getName())
746 return true;
747 if (std::get<0>(t&: Pair)->getName() > std::get<1>(t&: Pair)->getName())
748 return false;
749 }
750 return false;
751 });
752 FeatureBitsets.erase(first: llvm::unique(R&: FeatureBitsets), last: FeatureBitsets.end());
753 OS << "inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {\n"
754 << " enum : " << getMinimalTypeForRange(Range: FeatureBitsets.size()) << " {\n"
755 << " CEFBS_None,\n";
756 for (const auto &FeatureBitset : FeatureBitsets) {
757 if (FeatureBitset.empty())
758 continue;
759 OS << " " << getNameForFeatureBitset(FeatureBitset) << ",\n";
760 }
761 OS << " };\n\n"
762 << " static constexpr FeatureBitset FeatureBitsets[] = {\n"
763 << " {}, // CEFBS_None\n";
764 for (const auto &FeatureBitset : FeatureBitsets) {
765 if (FeatureBitset.empty())
766 continue;
767 OS << " {";
768 for (const auto &Feature : FeatureBitset) {
769 const auto &I = SubtargetFeatures.find(x: Feature);
770 assert(I != SubtargetFeatures.end() && "Didn't import predicate?");
771 OS << I->second.getEnumBitName() << ", ";
772 }
773 OS << "},\n";
774 }
775 OS << " };\n"
776 << " static constexpr " << getMinimalTypeForRange(Range: FeatureBitsets.size())
777 << " RequiredFeaturesRefs[] = {\n";
778 ArrayRef<const CodeGenInstruction *> NumberedInstructions =
779 Target.getInstructions();
780 for (const CodeGenInstruction *Inst : NumberedInstructions) {
781 OS << " CEFBS";
782 unsigned NumPredicates = 0;
783 for (const Record *Predicate :
784 Inst->TheDef->getValueAsListOfDefs(FieldName: "Predicates")) {
785 const auto &I = SubtargetFeatures.find(x: Predicate);
786 if (I != SubtargetFeatures.end()) {
787 OS << '_' << I->second.TheDef->getName();
788 NumPredicates++;
789 }
790 }
791 if (!NumPredicates)
792 OS << "_None";
793 OS << ", // " << Inst->getName() << '\n';
794 }
795 OS << " };\n\n"
796 << " assert(Opcode < " << NumberedInstructions.size() << ");\n"
797 << " return FeatureBitsets[RequiredFeaturesRefs[Opcode]];\n"
798 << "}\n\n";
799 } // end scope for GET_COMPUTE_FEATURES
800
801 {
802 IfDefEmitter IfDef(OS, "GET_AVAILABLE_OPCODE_CHECKER");
803 NamespaceEmitter NS(OS, Namespace);
804 OS << "bool isOpcodeAvailable("
805 << "unsigned Opcode, const FeatureBitset &Features) {\n"
806 << " FeatureBitset AvailableFeatures = "
807 << "computeAvailableFeatures(Features);\n"
808 << " FeatureBitset RequiredFeatures = "
809 << "computeRequiredFeatures(Opcode);\n"
810 << " FeatureBitset MissingFeatures =\n"
811 << " (AvailableFeatures & RequiredFeatures) ^\n"
812 << " RequiredFeatures;\n"
813 << " return !MissingFeatures.any();\n"
814 << "}\n";
815 }
816
817 {
818 IfDefEmitter IfDef(OS, "ENABLE_INSTR_PREDICATE_VERIFIER");
819 OS << "#include <sstream>\n\n";
820 NamespaceEmitter NS(OS, Namespace);
821 // Emit the name table for error messages.
822 OS << "#ifndef NDEBUG\n";
823 SubtargetFeatureInfo::emitNameTable(SubtargetFeatures, OS);
824 OS << "#endif // NDEBUG\n\n";
825 // Emit the predicate verifier.
826 OS << "void verifyInstructionPredicates(\n"
827 << " unsigned Opcode, const FeatureBitset &Features) {\n"
828 << "#ifndef NDEBUG\n";
829 OS << " FeatureBitset AvailableFeatures = "
830 "computeAvailableFeatures(Features);\n";
831 OS << " FeatureBitset RequiredFeatures = "
832 << "computeRequiredFeatures(Opcode);\n";
833 OS << " FeatureBitset MissingFeatures =\n"
834 << " (AvailableFeatures & RequiredFeatures) ^\n"
835 << " RequiredFeatures;\n"
836 << " if (MissingFeatures.any()) {\n"
837 << " std::ostringstream Msg;\n"
838 << " Msg << \"Attempting to emit \" << &" << Target.getName()
839 << "InstrNameData[" << Target.getName() << "InstrNameIndices[Opcode]]\n"
840 << " << \" instruction but the \";\n"
841 << " for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)\n"
842 << " if (MissingFeatures.test(i))\n"
843 << " Msg << SubtargetFeatureNames[i] << \" \";\n"
844 << " Msg << \"predicate(s) are not met\";\n"
845 << " report_fatal_error(Msg.str().c_str());\n"
846 << " }\n"
847 << "#endif // NDEBUG\n";
848 OS << "}\n";
849 }
850}
851
852void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS,
853 StringRef TargetName,
854 bool ExpandDefinition) {
855 ArrayRef<const Record *> TIIPredicates =
856 Records.getAllDerivedDefinitions(ClassName: "TIIPredicate");
857 if (TIIPredicates.empty())
858 return;
859
860 PredicateExpander PE(TargetName);
861 PE.setExpandForMC(false);
862
863 for (const Record *Rec : TIIPredicates) {
864 OS << (ExpandDefinition ? "" : "static ") << "bool ";
865 if (ExpandDefinition)
866 OS << TargetName << "InstrInfo::";
867 OS << Rec->getValueAsString(FieldName: "FunctionName");
868 OS << "(const MachineInstr &MI)";
869 if (!ExpandDefinition) {
870 OS << ";\n";
871 continue;
872 }
873
874 OS << " {\n";
875 OS << PE.getIndent();
876 PE.expandStatement(OS, Rec: Rec->getValueAsDef(FieldName: "Body"));
877 OS << "\n}\n\n";
878 }
879}
880
881void InstrInfoEmitter::buildTargetSpecializedPseudoInstsMap() {
882 ArrayRef<const Record *> SpecializedInsts = Records.getAllDerivedDefinitions(
883 ClassName: "TargetSpecializedStandardPseudoInstruction");
884 const CodeGenTarget &Target = CDP.getTargetInfo();
885
886 for (const Record *SpecializedRec : SpecializedInsts) {
887 const CodeGenInstruction &SpecializedInst =
888 Target.getInstruction(InstRec: SpecializedRec);
889 const Record *BaseInstRec = SpecializedRec->getValueAsDef(FieldName: "Instruction");
890
891 const CodeGenInstruction &BaseInst = Target.getInstruction(InstRec: BaseInstRec);
892
893 if (!TargetSpecializedPseudoInsts.insert(KV: {&BaseInst, &SpecializedInst})
894 .second)
895 PrintFatalError(Rec: SpecializedRec, Msg: "multiple overrides of '" +
896 BaseInst.getName() + "' defined");
897 }
898}
899
900//===----------------------------------------------------------------------===//
901// Main Output.
902//===----------------------------------------------------------------------===//
903
904// run - Emit the main instruction description records for the target...
905void InstrInfoEmitter::run(raw_ostream &OS) {
906 TGTimer &Timer = Records.getTimer();
907 Timer.startTimer(Name: "Analyze DAG patterns");
908
909 emitSourceFileHeader(Desc: "Target Instruction Enum Values and Descriptors", OS);
910
911 const CodeGenTarget &Target = CDP.getTargetInfo();
912 ArrayRef<const CodeGenInstruction *> NumberedInstructions =
913 Target.getInstructions();
914
915 emitEnums(OS, NumberedInstructions);
916
917 StringRef TargetName = Target.getName();
918 const Record *InstrInfo = Target.getInstructionSet();
919
920 // Collect all of the operand info records.
921 Timer.startTimer(Name: "Collect operand info");
922 buildTargetSpecializedPseudoInstsMap();
923
924 OperandInfoListTy OperandInfoList;
925 OperandInfoMapTy OperandInfoMap;
926 unsigned OperandInfoSize =
927 CollectOperandInfo(OperandInfoList, OperandInfoMap);
928
929 // Collect all of the instruction's implicit uses and defs.
930 // Also collect which features are enabled by instructions to control
931 // emission of various mappings.
932
933 bool HasUseLogicalOperandMappings = false;
934 bool HasUseNamedOperandTable = false;
935
936 Timer.startTimer(Name: "Collect uses/defs");
937 std::map<std::vector<const Record *>, unsigned> EmittedLists;
938 std::vector<std::vector<const Record *>> ImplicitLists;
939 unsigned ImplicitListSize = 0;
940 for (const CodeGenInstruction *Inst : NumberedInstructions) {
941 HasUseLogicalOperandMappings |=
942 Inst->TheDef->getValueAsBit(FieldName: "UseLogicalOperandMappings");
943 HasUseNamedOperandTable |=
944 Inst->TheDef->getValueAsBit(FieldName: "UseNamedOperandTable");
945
946 std::vector<const Record *> ImplicitOps = Inst->ImplicitUses;
947 llvm::append_range(C&: ImplicitOps, R: Inst->ImplicitDefs);
948 if (EmittedLists.try_emplace(k: ImplicitOps, args&: ImplicitListSize).second) {
949 ImplicitLists.push_back(x: ImplicitOps);
950 ImplicitListSize += ImplicitOps.size();
951 }
952 }
953
954 {
955 IfGuardEmitter IfGuard(
956 OS,
957 "defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)");
958 NamespaceEmitter NS(OS, "llvm");
959
960 OS << "struct " << TargetName << "InstrTable {\n";
961 OS << " MCInstrDesc Insts[" << NumberedInstructions.size() << "];\n";
962 OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "
963 "\"Unwanted padding between Insts and ImplicitOps\");\n";
964 OS << " MCPhysReg ImplicitOps[" << std::max(a: ImplicitListSize, b: 1U)
965 << "];\n";
966 // Emit enough padding to make ImplicitOps plus Padding add up to the size
967 // of a whole number of MCOperandInfo structs. This allows us to index into
968 // the OperandInfo array starting from the end of the Insts array, by
969 // biasing the indices by the OpInfoBase value calculated below.
970 OS << " char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % "
971 "sizeof(MCOperandInfo)];\n";
972 OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "
973 "\"Unwanted padding between Insts and OperandInfo\");\n";
974 OS << " MCOperandInfo OperandInfo[" << OperandInfoSize << "];\n";
975 OS << "};";
976 }
977
978 const CodeGenRegBank &RegBank = Target.getRegBank();
979 const CodeGenHwModes &CGH = Target.getHwModes();
980 unsigned NumModes = CGH.getNumModeIds();
981 ArrayRef<const Record *> RegClassByHwMode = Target.getAllRegClassByHwMode();
982 unsigned NumClassesByHwMode = RegClassByHwMode.size();
983
984 bool HasDeprecationFeatures =
985 llvm::any_of(Range&: NumberedInstructions, P: [](const CodeGenInstruction *Inst) {
986 return !Inst->HasComplexDeprecationPredicate &&
987 !Inst->DeprecatedReason.empty();
988 });
989 bool HasComplexDeprecationInfos =
990 llvm::any_of(Range&: NumberedInstructions, P: [](const CodeGenInstruction *Inst) {
991 return Inst->HasComplexDeprecationPredicate;
992 });
993
994 {
995 IfDefEmitter IfDef(OS, "GET_INSTRINFO_MC_DESC");
996 NamespaceEmitter LlvmNS(OS, "llvm");
997
998 // Emit all of the MCInstrDesc records in reverse ENUM ordering.
999 Timer.startTimer(Name: "Emit InstrDesc records");
1000 OS << "static_assert((sizeof " << TargetName
1001 << "InstrTable::ImplicitOps + sizeof " << TargetName
1002 << "InstrTable::Padding) % sizeof(MCOperandInfo) == 0);\n";
1003 OS << "static constexpr unsigned " << TargetName << "OpInfoBase = (sizeof "
1004 << TargetName << "InstrTable::ImplicitOps + sizeof " << TargetName
1005 << "InstrTable::Padding) / sizeof(MCOperandInfo);\n\n";
1006
1007 OS << "extern const " << TargetName << "InstrTable " << TargetName
1008 << "Descs = {\n {\n";
1009 SequenceToOffsetTable<StringRef> InstrNames;
1010 unsigned Num = NumberedInstructions.size();
1011 for (const CodeGenInstruction *Inst : reverse(C&: NumberedInstructions)) {
1012 // Keep a list of the instruction names.
1013 InstrNames.add(Seq: Inst->getName());
1014
1015 auto OverrideEntry = TargetSpecializedPseudoInsts.find(Val: Inst);
1016 if (OverrideEntry != TargetSpecializedPseudoInsts.end())
1017 Inst = OverrideEntry->second;
1018
1019 // Emit the record into the table.
1020 emitRecord(Inst: *Inst, Num: --Num, InstrInfo, EL&: EmittedLists, OperandInfo: OperandInfoMap, OS);
1021 }
1022
1023 OS << " }, {\n";
1024
1025 // Emit all of the instruction's implicit uses and defs.
1026 Timer.startTimer(Name: "Emit uses/defs");
1027 for (auto &List : ImplicitLists) {
1028 OS << " /* " << EmittedLists[List] << " */";
1029 for (auto &Reg : List)
1030 OS << ' ' << getQualifiedName(R: Reg) << ',';
1031 OS << '\n';
1032 }
1033
1034 OS << " }, {\n";
1035
1036 // Emit the padding.
1037 OS << " 0\n";
1038
1039 OS << " }, {\n";
1040
1041 // Emit all of the operand info records.
1042 Timer.startTimer(Name: "Emit operand info");
1043 EmitOperandInfo(OS, OperandInfoList);
1044
1045 OS << " }\n};\n\n";
1046
1047 // Emit the array of instruction names.
1048 Timer.startTimer(Name: "Emit instruction names");
1049 InstrNames.layout();
1050 InstrNames.emitStringLiteralDef(OS, Decl: Twine("extern const char ") +
1051 TargetName + "InstrNameData[]");
1052 OS << "extern const unsigned " << TargetName << "InstrNameIndices[] = {";
1053 Num = 0;
1054 for (const CodeGenInstruction *Inst : NumberedInstructions) {
1055 // Newline every eight entries.
1056 if (Num % 8 == 0)
1057 OS << "\n ";
1058 OS << InstrNames.get(Seq: Inst->getName()) << "U, ";
1059 ++Num;
1060 }
1061 OS << "\n};\n\n";
1062
1063 if (HasDeprecationFeatures) {
1064 OS << "extern const uint8_t " << TargetName
1065 << "InstrDeprecationFeatures[] = {";
1066 Num = 0;
1067 for (const CodeGenInstruction *Inst : NumberedInstructions) {
1068 if (Num % 8 == 0)
1069 OS << "\n ";
1070 if (!Inst->HasComplexDeprecationPredicate &&
1071 !Inst->DeprecatedReason.empty())
1072 OS << Target.getInstNamespace() << "::" << Inst->DeprecatedReason
1073 << ", ";
1074 else
1075 OS << "uint8_t(-1), ";
1076 ++Num;
1077 }
1078 OS << "\n};\n\n";
1079 }
1080
1081 if (HasComplexDeprecationInfos) {
1082 OS << "extern const MCInstrInfo::ComplexDeprecationPredicate "
1083 << TargetName << "InstrComplexDeprecationInfos[] = {";
1084 Num = 0;
1085 for (const CodeGenInstruction *Inst : NumberedInstructions) {
1086 if (Num % 8 == 0)
1087 OS << "\n ";
1088 if (Inst->HasComplexDeprecationPredicate)
1089 // Emit a function pointer to the complex predicate method.
1090 OS << "&get" << Inst->DeprecatedReason << "DeprecationInfo, ";
1091 else
1092 OS << "nullptr, ";
1093 ++Num;
1094 }
1095 OS << "\n};\n\n";
1096 }
1097
1098 // MCInstrInfo initialization routine.
1099 Timer.startTimer(Name: "Emit initialization routine");
1100
1101 if (NumClassesByHwMode != 0) {
1102 OS << "extern const int16_t " << TargetName << "RegClassByHwModeTables["
1103 << NumModes << "][" << NumClassesByHwMode << "] = {\n";
1104
1105 for (unsigned M = 0; M < NumModes; ++M) {
1106 OS << " { // " << CGH.getModeName(Id: M, /*IncludeDefault=*/true) << '\n';
1107 for (unsigned I = 0; I != NumClassesByHwMode; ++I) {
1108 const Record *Class = RegClassByHwMode[I];
1109 const HwModeSelect &ModeSelect = CGH.getHwModeSelect(R: Class);
1110
1111 auto FoundMode =
1112 find_if(Range: ModeSelect.Items, P: [=](const HwModeSelect::PairType P) {
1113 return P.first == M;
1114 });
1115
1116 if (FoundMode == ModeSelect.Items.end()) {
1117 // If a RegClassByHwMode doesn't have an entry corresponding to a
1118 // mode, pad with default register class.
1119 OS << indent(4) << "-1, // Missing mode entry for "
1120 << Class->getName() << "\n";
1121 } else {
1122 const CodeGenRegisterClass *RegClass =
1123 RegBank.getRegClass(FoundMode->second);
1124 OS << indent(4) << RegClass->getQualifiedIdName() << ", // "
1125 << Class->getName() << "\n";
1126 }
1127 }
1128
1129 OS << " },\n";
1130 }
1131
1132 OS << "};\n\n";
1133 }
1134
1135 OS << "static inline void Init" << TargetName
1136 << "MCInstrInfo(MCInstrInfo *II) {\n";
1137 OS << " II->InitMCInstrInfo(" << TargetName << "Descs.Insts, "
1138 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, ";
1139 if (HasDeprecationFeatures)
1140 OS << TargetName << "InstrDeprecationFeatures, ";
1141 else
1142 OS << "nullptr, ";
1143 if (HasComplexDeprecationInfos)
1144 OS << TargetName << "InstrComplexDeprecationInfos, ";
1145 else
1146 OS << "nullptr, ";
1147 OS << NumberedInstructions.size() << ", ";
1148
1149 if (NumClassesByHwMode != 0) {
1150 OS << '&' << TargetName << "RegClassByHwModeTables[0][0], "
1151 << NumClassesByHwMode;
1152 } else
1153 OS << "nullptr, 0";
1154
1155 OS << ");\n}\n\n";
1156 } // end GET_INSTRINFO_MC_DESC scope.
1157
1158 {
1159 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
1160 IfDefEmitter IfDef(OS, "GET_INSTRINFO_HEADER");
1161 {
1162 NamespaceEmitter LlvmNS(OS, "llvm");
1163 Twine ClassName = TargetName + "GenInstrInfo";
1164 OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
1165 << " explicit " << ClassName
1166 << "(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, "
1167 "unsigned CFSetupOpcode = ~0u, "
1168 "unsigned CFDestroyOpcode = ~0u, "
1169 "unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);\n"
1170 << " ~" << ClassName << "() override = default;\n"
1171 << "};\n";
1172
1173 // Declare RegClassByHwModeTables, so that other files can use this
1174 // without having to indirect via MCInstInfo.
1175 if (NumClassesByHwMode != 0) {
1176 OS << "extern const int16_t " << TargetName << "RegClassByHwModeTables["
1177 << NumModes << "][" << NumClassesByHwMode << "];\n";
1178 }
1179 } // end llvm namespace.
1180
1181 OS << "\n";
1182 NamespaceEmitter InstNS(OS, ("llvm::" + Target.getInstNamespace()).str());
1183 for (const Record *R : Records.getAllDerivedDefinitions(ClassName: "Operand")) {
1184 if (R->isAnonymous())
1185 continue;
1186 const DagInit *D = R->getValueAsDag(FieldName: "MIOperandInfo");
1187 if (!D)
1188 continue;
1189 for (const auto &[Idx, Name] : enumerate(First: D->getArgNames())) {
1190 if (Name)
1191 OS << "constexpr unsigned SUBOP_" << R->getName() << "_"
1192 << Name->getValue() << " = " << Idx << ";\n";
1193 }
1194 }
1195 } // end GET_INSTRINFO_HEADER scope.
1196
1197 {
1198 IfDefEmitter IfDef(OS, "GET_INSTRINFO_HELPER_DECLS");
1199 emitTIIHelperMethods(OS, TargetName, /* ExpandDefinition = */ false);
1200 }
1201
1202 {
1203 IfDefEmitter IfDef(OS, "GET_INSTRINFO_HELPERS");
1204 emitTIIHelperMethods(OS, TargetName, /* ExpandDefinition = */ true);
1205 }
1206
1207 {
1208 IfDefEmitter IfDef(OS, "GET_INSTRINFO_CTOR_DTOR");
1209 NamespaceEmitter LlvmNS(OS, "llvm");
1210 OS << "extern const " << TargetName << "InstrTable " << TargetName
1211 << "Descs;\n";
1212 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
1213 OS << "extern const char " << TargetName << "InstrNameData[];\n";
1214
1215 if (HasDeprecationFeatures)
1216 OS << "extern const uint8_t " << TargetName
1217 << "InstrDeprecationFeatures[];\n";
1218 if (HasComplexDeprecationInfos)
1219 OS << "extern const MCInstrInfo::ComplexDeprecationPredicate "
1220 << TargetName << "InstrComplexDeprecationInfos[];\n";
1221 Twine ClassName = TargetName + "GenInstrInfo";
1222 OS << ClassName << "::" << ClassName
1223 << "(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, "
1224 "unsigned CFSetupOpcode, unsigned "
1225 "CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)\n"
1226 << " : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, "
1227 "CatchRetOpcode, "
1228 "ReturnOpcode";
1229 if (NumClassesByHwMode != 0)
1230 OS << ", " << TargetName
1231 << "RegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_"
1232 "RegInfo)]";
1233
1234 OS << ") {\n"
1235 << " InitMCInstrInfo(" << TargetName << "Descs.Insts, " << TargetName
1236 << "InstrNameIndices, " << TargetName << "InstrNameData, ";
1237 if (HasDeprecationFeatures)
1238 OS << TargetName << "InstrDeprecationFeatures, ";
1239 else
1240 OS << "nullptr, ";
1241 if (HasComplexDeprecationInfos)
1242 OS << TargetName << "InstrComplexDeprecationInfos, ";
1243 else
1244 OS << "nullptr, ";
1245 OS << NumberedInstructions.size();
1246
1247 if (NumClassesByHwMode != 0) {
1248 OS << ", &" << TargetName << "RegClassByHwModeTables[0][0], "
1249 << NumClassesByHwMode;
1250 }
1251
1252 OS << ");\n"
1253 "}\n";
1254 } // end GET_INSTRINFO_CTOR_DTOR scope.
1255
1256 ArrayRef<const CodeGenInstruction *> TargetInstructions =
1257 Target.getTargetInstructions();
1258
1259 if (HasUseNamedOperandTable) {
1260 Timer.startTimer(Name: "Emit operand name mappings");
1261 emitOperandNameMappings(OS, Target, TargetInstructions);
1262 }
1263
1264 Timer.startTimer(Name: "Emit operand type mappings");
1265 emitOperandTypeMappings(OS, Target, NumberedInstructions);
1266
1267 if (HasUseLogicalOperandMappings) {
1268 Timer.startTimer(Name: "Emit logical operand size mappings");
1269 emitLogicalOperandSizeMappings(OS, Namespace: TargetName, TargetInstructions);
1270 }
1271
1272 Timer.startTimer(Name: "Emit helper methods");
1273 emitMCIIHelperMethods(OS, TargetName);
1274
1275 Timer.startTimer(Name: "Emit verifier methods");
1276 emitFeatureVerifier(OS, Target);
1277
1278 Timer.startTimer(Name: "Emit map table");
1279 EmitMapTable(RK: Records, OS);
1280}
1281
1282void InstrInfoEmitter::emitRecord(
1283 const CodeGenInstruction &Inst, unsigned Num, const Record *InstrInfo,
1284 std::map<std::vector<const Record *>, unsigned> &EmittedLists,
1285 const OperandInfoMapTy &OperandInfoMap, raw_ostream &OS) {
1286 int MinOperands = 0;
1287 if (!Inst.Operands.empty())
1288 // Each logical operand can be multiple MI operands.
1289 MinOperands =
1290 Inst.Operands.back().MIOperandNo + Inst.Operands.back().MINumOperands;
1291 // Even the logical output operand may be multiple MI operands.
1292 int DefOperands = 0;
1293 if (Inst.Operands.NumDefs) {
1294 auto &Opnd = Inst.Operands[Inst.Operands.NumDefs - 1];
1295 DefOperands = Opnd.MIOperandNo + Opnd.MINumOperands;
1296 }
1297
1298 OS << " { ";
1299 OS << Num << ",\t" << MinOperands << ",\t" << DefOperands << ",\t"
1300 << Inst.TheDef->getValueAsInt(FieldName: "Size") << ",\t"
1301 << SchedModels.getSchedClassIdx(Inst) << ",\t";
1302
1303 const CodeGenTarget &Target = CDP.getTargetInfo();
1304
1305 // Emit the implicit use/def list...
1306 OS << Inst.ImplicitUses.size() << ",\t" << Inst.ImplicitDefs.size() << ",\t";
1307 std::vector<const Record *> ImplicitOps = Inst.ImplicitUses;
1308 llvm::append_range(C&: ImplicitOps, R: Inst.ImplicitDefs);
1309
1310 // Emit the operand info offset.
1311 OperandInfoTy OperandInfo = GetOperandInfo(Inst);
1312 OS << Target.getName() << "OpInfoBase + "
1313 << OperandInfoMap.find(x: OperandInfo)->second << ",\t";
1314
1315 // Emit implicit operand base.
1316 OS << EmittedLists[ImplicitOps] << ",\t0";
1317
1318 // Emit all of the target independent flags...
1319 if (Inst.isPreISelOpcode)
1320 OS << "|(1ULL<<MCID::PreISelOpcode)";
1321 if (Inst.isPseudo)
1322 OS << "|(1ULL<<MCID::Pseudo)";
1323 if (Inst.isMeta)
1324 OS << "|(1ULL<<MCID::Meta)";
1325 if (Inst.isReturn)
1326 OS << "|(1ULL<<MCID::Return)";
1327 if (Inst.isEHScopeReturn)
1328 OS << "|(1ULL<<MCID::EHScopeReturn)";
1329 if (Inst.isBranch)
1330 OS << "|(1ULL<<MCID::Branch)";
1331 if (Inst.isIndirectBranch)
1332 OS << "|(1ULL<<MCID::IndirectBranch)";
1333 if (Inst.isCompare)
1334 OS << "|(1ULL<<MCID::Compare)";
1335 if (Inst.isMoveImm)
1336 OS << "|(1ULL<<MCID::MoveImm)";
1337 if (Inst.isMoveReg)
1338 OS << "|(1ULL<<MCID::MoveReg)";
1339 if (Inst.isBitcast)
1340 OS << "|(1ULL<<MCID::Bitcast)";
1341 if (Inst.isAdd)
1342 OS << "|(1ULL<<MCID::Add)";
1343 if (Inst.isTrap)
1344 OS << "|(1ULL<<MCID::Trap)";
1345 if (Inst.isSelect)
1346 OS << "|(1ULL<<MCID::Select)";
1347 if (Inst.isBarrier)
1348 OS << "|(1ULL<<MCID::Barrier)";
1349 if (Inst.hasDelaySlot)
1350 OS << "|(1ULL<<MCID::DelaySlot)";
1351 if (Inst.isCall)
1352 OS << "|(1ULL<<MCID::Call)";
1353 if (Inst.canFoldAsLoad)
1354 OS << "|(1ULL<<MCID::FoldableAsLoad)";
1355 if (Inst.mayLoad)
1356 OS << "|(1ULL<<MCID::MayLoad)";
1357 if (Inst.mayStore)
1358 OS << "|(1ULL<<MCID::MayStore)";
1359 if (Inst.mayRaiseFPException)
1360 OS << "|(1ULL<<MCID::MayRaiseFPException)";
1361 if (Inst.isPredicable)
1362 OS << "|(1ULL<<MCID::Predicable)";
1363 if (Inst.isConvertibleToThreeAddress)
1364 OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
1365 if (Inst.isCommutable)
1366 OS << "|(1ULL<<MCID::Commutable)";
1367 if (Inst.isTerminator)
1368 OS << "|(1ULL<<MCID::Terminator)";
1369 if (Inst.isReMaterializable)
1370 OS << "|(1ULL<<MCID::Rematerializable)";
1371 if (Inst.isNotDuplicable)
1372 OS << "|(1ULL<<MCID::NotDuplicable)";
1373 if (Inst.Operands.hasOptionalDef)
1374 OS << "|(1ULL<<MCID::HasOptionalDef)";
1375 if (Inst.usesCustomInserter)
1376 OS << "|(1ULL<<MCID::UsesCustomInserter)";
1377 if (Inst.hasPostISelHook)
1378 OS << "|(1ULL<<MCID::HasPostISelHook)";
1379 if (Inst.Operands.isVariadic)
1380 OS << "|(1ULL<<MCID::Variadic)";
1381 if (Inst.hasSideEffects)
1382 OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
1383 if (Inst.isAsCheapAsAMove)
1384 OS << "|(1ULL<<MCID::CheapAsAMove)";
1385 if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
1386 OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
1387 if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
1388 OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
1389 if (Inst.isRegSequence)
1390 OS << "|(1ULL<<MCID::RegSequence)";
1391 if (Inst.isExtractSubreg)
1392 OS << "|(1ULL<<MCID::ExtractSubreg)";
1393 if (Inst.isInsertSubreg)
1394 OS << "|(1ULL<<MCID::InsertSubreg)";
1395 if (Inst.isConvergent)
1396 OS << "|(1ULL<<MCID::Convergent)";
1397 if (Inst.variadicOpsAreDefs)
1398 OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
1399 if (Inst.isAuthenticated)
1400 OS << "|(1ULL<<MCID::Authenticated)";
1401
1402 // Emit all of the target-specific flags...
1403 const BitsInit *TSF = Inst.TheDef->getValueAsBitsInit(FieldName: "TSFlags");
1404 if (!TSF)
1405 PrintFatalError(ErrorLoc: Inst.TheDef->getLoc(), Msg: "no TSFlags?");
1406 std::optional<uint64_t> Value = TSF->convertInitializerToInt();
1407 if (!Value)
1408 PrintFatalError(Rec: Inst.TheDef, Msg: "Invalid TSFlags bit in " + Inst.getName());
1409
1410 OS << ", 0x";
1411 OS.write_hex(N: *Value);
1412 OS << "ULL";
1413
1414 OS << " }, // " << Inst.getName() << '\n';
1415}
1416
1417// emitEnums - Print out enum values for all of the instructions.
1418void InstrInfoEmitter::emitEnums(
1419 raw_ostream &OS,
1420 ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
1421
1422 const CodeGenTarget &Target = CDP.getTargetInfo();
1423 StringRef Namespace = Target.getInstNamespace();
1424
1425 if (Namespace.empty())
1426 PrintFatalError(Msg: "No instructions defined!");
1427
1428 {
1429 IfDefEmitter IfDef(OS, "GET_INSTRINFO_ENUM");
1430 NamespaceEmitter NS(OS, ("llvm::" + Namespace).str());
1431
1432 auto II = llvm::max_element(
1433 Range&: NumberedInstructions,
1434 C: [](const CodeGenInstruction *InstA, const CodeGenInstruction *InstB) {
1435 return InstA->getName().size() < InstB->getName().size();
1436 });
1437 size_t MaxNameSize = (*II)->getName().size();
1438
1439 OS << " enum {\n";
1440 for (const CodeGenInstruction *Inst : NumberedInstructions) {
1441 OS << " " << left_justify(Str: Inst->getName(), Width: MaxNameSize) << " = "
1442 << Target.getInstrIntValue(R: Inst->TheDef) << ", // "
1443 << SrcMgr.getFormattedLocationNoOffset(Loc: Inst->TheDef->getLoc().front())
1444 << '\n';
1445 }
1446 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << '\n';
1447 OS << " };\n";
1448
1449 ArrayRef<const Record *> RegClassesByHwMode =
1450 Target.getAllRegClassByHwMode();
1451 if (!RegClassesByHwMode.empty()) {
1452 OS << " enum RegClassByHwModeUses : uint16_t {\n";
1453 for (const Record *ClassByHwMode : RegClassesByHwMode)
1454 OS << indent(4) << ClassByHwMode->getName() << ",\n";
1455 OS << " };\n";
1456 }
1457 }
1458
1459 {
1460 IfDefEmitter IfDef(OS, "GET_INSTRINFO_SCHED_ENUM");
1461 NamespaceEmitter NS(OS, ("llvm::" + Namespace + "::Sched").str());
1462
1463 OS << " enum {\n";
1464 auto ExplictClasses = SchedModels.explicitSchedClasses();
1465 for (const auto &[Idx, Class] : enumerate(First&: ExplictClasses))
1466 OS << " " << Class.Name << "\t= " << Idx << ",\n";
1467 OS << " SCHED_LIST_END = " << ExplictClasses.size() << '\n';
1468 OS << " };\n";
1469 }
1470}
1471
1472static TableGen::Emitter::OptClass<InstrInfoEmitter>
1473 X("gen-instr-info", "Generate instruction descriptions");
1474