1//===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend is responsible for emitting a description of a target
10// register bank for a code generator.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Common/CodeGenRegisters.h"
15#include "Common/CodeGenTarget.h"
16#include "Common/InfoByHwMode.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/Support/Debug.h"
19#include "llvm/Support/MathExtras.h"
20#include "llvm/TableGen/CodeGenHelpers.h"
21#include "llvm/TableGen/Error.h"
22#include "llvm/TableGen/Record.h"
23#include "llvm/TableGen/TGTimer.h"
24#include "llvm/TableGen/TableGenBackend.h"
25
26#define DEBUG_TYPE "register-bank-emitter"
27
28using namespace llvm;
29
30namespace {
31class RegisterBank {
32
33 /// A vector of register classes that are included in the register bank.
34 using RegisterClassesTy = std::vector<const CodeGenRegisterClass *>;
35
36private:
37 const Record &TheDef;
38
39 /// The register classes that are covered by the register bank.
40 RegisterClassesTy RCs;
41
42 /// The register class with the largest register size.
43 std::vector<const CodeGenRegisterClass *> RCsWithLargestRegSize;
44
45public:
46 RegisterBank(const Record &TheDef, unsigned NumModeIds)
47 : TheDef(TheDef), RCsWithLargestRegSize(NumModeIds) {}
48
49 /// Get the human-readable name for the bank.
50 StringRef getName() const { return TheDef.getValueAsString(FieldName: "Name"); }
51
52 /// Get the name of the enumerator in the ID enumeration.
53 std::string getEnumeratorName() const {
54 return (TheDef.getName() + "ID").str();
55 }
56
57 /// Get the name of the array holding the register class coverage data;
58 std::string getCoverageArrayName() const {
59 return (TheDef.getName() + "CoverageData").str();
60 }
61
62 /// Get the name of the global instance variable.
63 StringRef getInstanceVarName() const { return TheDef.getName(); }
64
65 const Record &getDef() const { return TheDef; }
66
67 /// Get the register classes listed in the RegisterBank.RegisterClasses field.
68 std::vector<const CodeGenRegisterClass *>
69 getExplicitlySpecifiedRegisterClasses(
70 const CodeGenRegBank &RegisterClassHierarchy) const {
71 std::vector<const CodeGenRegisterClass *> RCs;
72 for (const auto *RCDef : getDef().getValueAsListOfDefs(FieldName: "RegisterClasses"))
73 RCs.push_back(x: RegisterClassHierarchy.getRegClass(RCDef));
74 return RCs;
75 }
76
77 /// Add a register class to the bank without duplicates.
78 void addRegisterClass(const CodeGenRegisterClass *RC) {
79 if (llvm::is_contained(Range&: RCs, Element: RC))
80 return;
81
82 // FIXME? We really want the register size rather than the spill size
83 // since the spill size may be bigger on some targets with
84 // limited load/store instructions. However, we don't store the
85 // register size anywhere (we could sum the sizes of the subregisters
86 // but there may be additional bits too) and we can't derive it from
87 // the VT's reliably due to Untyped.
88 unsigned NumModeIds = RCsWithLargestRegSize.size();
89 for (unsigned M = 0; M < NumModeIds; ++M) {
90 if (RCsWithLargestRegSize[M] == nullptr)
91 RCsWithLargestRegSize[M] = RC;
92 else if (RCsWithLargestRegSize[M]->RSI.get(Mode: M).SpillSize <
93 RC->RSI.get(Mode: M).SpillSize)
94 RCsWithLargestRegSize[M] = RC;
95 assert(RCsWithLargestRegSize[M] && "RC was nullptr?");
96 }
97
98 RCs.emplace_back(args&: RC);
99 }
100
101 const CodeGenRegisterClass *getRCWithLargestRegSize(unsigned HwMode) const {
102 return RCsWithLargestRegSize[HwMode];
103 }
104
105 iterator_range<RegisterClassesTy::const_iterator> register_classes() const {
106 return RCs;
107 }
108};
109
110class RegisterBankEmitter {
111private:
112 const CodeGenTarget Target;
113 const RecordKeeper &Records;
114
115 void emitHeader(raw_ostream &OS, StringRef TargetName,
116 ArrayRef<RegisterBank> Banks);
117 void emitBaseClassDefinition(raw_ostream &OS, StringRef TargetName,
118 ArrayRef<RegisterBank> Banks);
119 void emitBaseClassImplementation(raw_ostream &OS, StringRef TargetName,
120 ArrayRef<RegisterBank> Banks);
121
122public:
123 RegisterBankEmitter(const RecordKeeper &R) : Target(R), Records(R) {}
124
125 void run(raw_ostream &OS);
126};
127
128} // end anonymous namespace
129
130/// Emit code to declare the ID enumeration and external global instance
131/// variables.
132void RegisterBankEmitter::emitHeader(raw_ostream &OS, StringRef TargetName,
133 ArrayRef<RegisterBank> Banks) {
134 IfDefEmitter IfDef(OS, "GET_REGBANK_DECLARATIONS");
135 NamespaceEmitter NS(OS, ("llvm::" + TargetName).str());
136
137 // <Target>RegisterBankInfo.h
138 OS << "enum : unsigned {\n";
139
140 OS << " InvalidRegBankID = ~0u,\n";
141 unsigned ID = 0;
142 for (const auto &Bank : Banks)
143 OS << " " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";
144 OS << " NumRegisterBanks,\n"
145 << "};\n";
146}
147
148/// Emit declarations of the <Target>GenRegisterBankInfo class.
149void RegisterBankEmitter::emitBaseClassDefinition(
150 raw_ostream &OS, StringRef TargetName, ArrayRef<RegisterBank> Banks) {
151 IfDefEmitter IfDef(OS, "GET_TARGET_REGBANK_CLASS");
152
153 OS << "private:\n"
154 << " static const RegisterBank *RegBanks[];\n"
155 << " static const unsigned Sizes[];\n\n"
156 << "public:\n"
157 << " const RegisterBank &getRegBankFromRegClass(const "
158 "TargetRegisterClass &RC, LLT Ty) const override;\n"
159 << "protected:\n"
160 << " " << TargetName << "GenRegisterBankInfo(unsigned HwMode = 0);\n"
161 << "\n";
162}
163
164/// Visit each register class belonging to the given register bank.
165///
166/// A class belongs to the bank iff any of these apply:
167/// * It is explicitly specified
168/// * It is a subclass of a class that is a member.
169/// * It is a class containing subregisters of the registers of a class that
170/// is a member. This is known as a subreg-class.
171///
172/// This function must be called for each explicitly specified register class.
173///
174/// \param RC The register class to search.
175/// \param Kind A debug string containing the path the visitor took to reach RC.
176/// \param VisitFn The action to take for each class visited. It may be called
177/// multiple times for a given class if there are multiple paths
178/// to the class.
179static void visitRegisterBankClasses(
180 const CodeGenRegBank &RegisterClassHierarchy,
181 const CodeGenRegisterClass *RC, const Twine &Kind,
182 std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
183 DenseSet<const CodeGenRegisterClass *> &VisitedRCs) {
184
185 // Make sure we only visit each class once to avoid infinite loops.
186 if (!VisitedRCs.insert(V: RC).second)
187 return;
188
189 // Visit each explicitly named class.
190 VisitFn(RC, Kind.str());
191
192 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
193 std::string TmpKind =
194 (Kind + " (" + PossibleSubclass.getName() + ")").str();
195
196 // Visit each subclass of an explicitly named class.
197 if (RC != &PossibleSubclass && RC->hasSubClass(RC: &PossibleSubclass))
198 visitRegisterBankClasses(RegisterClassHierarchy, RC: &PossibleSubclass,
199 Kind: TmpKind + " " + RC->getName() + " subclass",
200 VisitFn, VisitedRCs);
201
202 // Visit each class that contains only subregisters of RC with a common
203 // subregister-index.
204 //
205 // More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in
206 // PossibleSubclass for all registers Reg from RC using any
207 // subregister-index SubReg
208 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
209 if (PossibleSubclass.hasSuperRegClass(SubIdx: &SubIdx, RC)) {
210 std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +
211 " class-with-subregs: " + RC->getName())
212 .str();
213 VisitFn(&PossibleSubclass, TmpKind2);
214 }
215 }
216 }
217}
218
219void RegisterBankEmitter::emitBaseClassImplementation(
220 raw_ostream &OS, StringRef TargetName, ArrayRef<RegisterBank> Banks) {
221 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
222 const CodeGenHwModes &CGH = Target.getHwModes();
223
224 IfDefEmitter IfDef(OS, "GET_TARGET_REGBANK_IMPL");
225 NamespaceEmitter LlvmNS(OS, "llvm");
226
227 {
228 NamespaceEmitter TargetNS(OS, TargetName);
229 for (const auto &Bank : Banks) {
230 std::vector<std::vector<const CodeGenRegisterClass *>> RCsGroupedByWord(
231 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
232
233 for (const auto &RC : Bank.register_classes())
234 RCsGroupedByWord[RC->EnumValue / 32].push_back(x: RC);
235
236 OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
237 unsigned LowestIdxInWord = 0;
238 for (const auto &RCs : RCsGroupedByWord) {
239 OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31)
240 << "\n";
241 for (const auto &RC : RCs) {
242 OS << " (1u << (" << RC->getQualifiedIdName() << " - "
243 << LowestIdxInWord << ")) |\n";
244 }
245 OS << " 0,\n";
246 LowestIdxInWord += 32;
247 }
248 OS << "};\n";
249 }
250 OS << "\n";
251
252 for (const auto &Bank : Banks) {
253 std::string QualifiedBankID =
254 (TargetName + "::" + Bank.getEnumeratorName()).str();
255 OS << "constexpr RegisterBank " << Bank.getInstanceVarName()
256 << "(/* ID */ " << QualifiedBankID << ", /* Name */ \""
257 << Bank.getName() << "\", " << "/* CoveredRegClasses */ "
258 << Bank.getCoverageArrayName() << ", /* NumRegClasses */ "
259 << RegisterClassHierarchy.getRegClasses().size() << ");\n";
260 }
261 } // End target namespace.
262
263 OS << "\nconst RegisterBank *" << TargetName
264 << "GenRegisterBankInfo::RegBanks[] = {\n";
265 for (const auto &Bank : Banks)
266 OS << " &" << TargetName << "::" << Bank.getInstanceVarName() << ",\n";
267 OS << "};\n\n";
268
269 unsigned NumModeIds = CGH.getNumModeIds();
270 OS << "const unsigned " << TargetName << "GenRegisterBankInfo::Sizes[] = {\n";
271 for (unsigned M = 0; M < NumModeIds; ++M) {
272 OS << " // Mode = " << M << " ("
273 << CGH.getModeName(Id: M, /*IncludeDefault=*/true) << ")\n";
274 for (const auto &Bank : Banks) {
275 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegSize(HwMode: M);
276 unsigned Size = RC.RSI.get(Mode: M).SpillSize;
277 OS << " " << Size << ",\n";
278 }
279 }
280 OS << "};\n\n";
281
282 OS << TargetName << "GenRegisterBankInfo::" << TargetName
283 << "GenRegisterBankInfo(unsigned HwMode)\n"
284 << " : RegisterBankInfo(RegBanks, " << TargetName
285 << "::NumRegisterBanks, Sizes, HwMode) {\n"
286 << " // Assert that RegBank indices match their ID's\n"
287 << "#ifndef NDEBUG\n"
288 << " for (auto RB : enumerate(RegBanks))\n"
289 << " assert(RB.index() == RB.value()->getID() && \"Index != ID\");\n"
290 << "#endif // NDEBUG\n"
291 << "}\n";
292
293 uint32_t NumRegBanks = Banks.size();
294 uint32_t BitSize = NextPowerOf2(A: Log2_32(Value: NumRegBanks));
295 uint32_t ElemsPerWord = 32 / BitSize;
296 uint32_t BitMask = (1 << BitSize) - 1;
297 bool HasAmbigousOrMissingEntry = false;
298 struct Entry {
299 std::string RCIdName;
300 std::string RBIdName;
301 };
302 SmallVector<Entry, 0> Entries;
303 for (const auto &Bank : Banks) {
304 for (const auto *RC : Bank.register_classes()) {
305 if (RC->EnumValue >= Entries.size())
306 Entries.resize(N: RC->EnumValue + 1);
307 Entry &E = Entries[RC->EnumValue];
308 E.RCIdName = RC->getIdName();
309 if (!E.RBIdName.empty()) {
310 HasAmbigousOrMissingEntry = true;
311 E.RBIdName = "InvalidRegBankID";
312 } else {
313 E.RBIdName = (TargetName + "::" + Bank.getEnumeratorName()).str();
314 }
315 }
316 }
317 for (auto &E : Entries) {
318 if (E.RBIdName.empty()) {
319 HasAmbigousOrMissingEntry = true;
320 E.RBIdName = "InvalidRegBankID";
321 }
322 }
323 OS << "\nconst RegisterBank &\n"
324 << TargetName
325 << "GenRegisterBankInfo::getRegBankFromRegClass"
326 "(const TargetRegisterClass &RC, LLT) const {\n";
327 if (HasAmbigousOrMissingEntry) {
328 OS << " constexpr uint32_t InvalidRegBankID = uint32_t("
329 << TargetName + "::InvalidRegBankID) & " << BitMask << ";\n";
330 }
331 unsigned TableSize =
332 Entries.size() / ElemsPerWord + ((Entries.size() % ElemsPerWord) > 0);
333 OS << " static const uint32_t RegClass2RegBank[" << TableSize << "] = {\n";
334 uint32_t Shift = 32 - BitSize;
335 bool First = true;
336 std::string TrailingComment;
337 for (auto &E : Entries) {
338 Shift += BitSize;
339 if (Shift == 32) {
340 Shift = 0;
341 if (First)
342 First = false;
343 else
344 OS << ',' << TrailingComment << '\n';
345 } else {
346 OS << " |" << TrailingComment << '\n';
347 }
348 OS << " ("
349 << (E.RBIdName.empty()
350 ? "InvalidRegBankID"
351 : Twine("uint32_t(").concat(Suffix: E.RBIdName).concat(Suffix: ")").str())
352 << " << " << Shift << ')';
353 if (!E.RCIdName.empty())
354 TrailingComment = " // " + E.RCIdName;
355 else
356 TrailingComment = "";
357 }
358 OS << TrailingComment
359 << "\n };\n"
360 " const unsigned RegClassID = RC.getID();\n"
361 " if (LLVM_LIKELY(RegClassID < "
362 << Entries.size()
363 << ")) {\n"
364 " unsigned RegBankID = (RegClass2RegBank[RegClassID / "
365 << ElemsPerWord << "] >> ((RegClassID % " << ElemsPerWord << ") * "
366 << BitSize << ")) & " << BitMask << ";\n";
367 if (HasAmbigousOrMissingEntry) {
368 OS << " if (RegBankID != InvalidRegBankID)\n"
369 " return getRegBank(RegBankID);\n";
370 } else {
371 OS << " return getRegBank(RegBankID);\n";
372 }
373 OS << " }\n"
374 " llvm_unreachable(llvm::Twine(\"Target needs to handle register "
375 "class ID "
376 "0x\").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());\n"
377 "}\n";
378}
379
380void RegisterBankEmitter::run(raw_ostream &OS) {
381 StringRef TargetName = Target.getName();
382 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
383 const CodeGenHwModes &CGH = Target.getHwModes();
384
385 TGTimer &Timer = Records.getTimer();
386 Timer.startTimer(Name: "Analyze records");
387 std::vector<RegisterBank> Banks;
388 for (const auto &V : Records.getAllDerivedDefinitions(ClassName: "RegisterBank")) {
389 DenseSet<const CodeGenRegisterClass *> VisitedRCs;
390 RegisterBank Bank(*V, CGH.getNumModeIds());
391
392 for (const CodeGenRegisterClass *RC :
393 Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
394 visitRegisterBankClasses(
395 RegisterClassHierarchy, RC, Kind: "explicit",
396 VisitFn: [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
397 LLVM_DEBUG(dbgs()
398 << "Added " << RC->getName() << "(" << Kind << ")\n");
399 Bank.addRegisterClass(RC);
400 },
401 VisitedRCs);
402 }
403
404 Banks.push_back(x: Bank);
405 }
406
407 if (Banks.empty())
408 PrintFatalError(Msg: "No register banks defined");
409
410 // Warn about ambiguous MIR caused by register bank/class name clashes.
411 Timer.startTimer(Name: "Warn ambiguous");
412 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {
413 for (const auto &Bank : Banks) {
414 if (Bank.getName().lower() == StringRef(Class.getName()).lower()) {
415 PrintWarning(WarningLoc: Bank.getDef().getLoc(), Msg: "Register bank names should be "
416 "distinct from register classes "
417 "to avoid ambiguous MIR");
418 PrintNote(NoteLoc: Bank.getDef().getLoc(), Msg: "RegisterBank was declared here");
419 PrintNote(NoteLoc: Class.getDef()->getLoc(), Msg: "RegisterClass was declared here");
420 }
421 }
422 }
423
424 Timer.startTimer(Name: "Emit output");
425 emitSourceFileHeader(Desc: "Register Bank Source Fragments", OS);
426 emitHeader(OS, TargetName, Banks);
427 emitBaseClassDefinition(OS, TargetName, Banks);
428 emitBaseClassImplementation(OS, TargetName, Banks);
429}
430
431static TableGen::Emitter::OptClass<RegisterBankEmitter>
432 X("gen-register-bank", "Generate registers bank descriptions");
433