1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend is responsible for emitting a description of a target
10// register file for a code generator. It uses instances of the Register,
11// RegisterAliases, and RegisterClass classes to gather this information.
12//
13//===----------------------------------------------------------------------===//
14
15#include "Basic/SequenceToOffsetTable.h"
16#include "Common/CodeGenHwModes.h"
17#include "Common/CodeGenRegisters.h"
18#include "Common/CodeGenTarget.h"
19#include "Common/InfoByHwMode.h"
20#include "Common/Types.h"
21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/SetVector.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/ADT/SparseBitVector.h"
27#include "llvm/ADT/Twine.h"
28#include "llvm/CodeGenTypes/MachineValueType.h"
29#include "llvm/Support/Casting.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Format.h"
32#include "llvm/Support/raw_ostream.h"
33#include "llvm/TableGen/Error.h"
34#include "llvm/TableGen/Record.h"
35#include "llvm/TableGen/SetTheory.h"
36#include "llvm/TableGen/TGTimer.h"
37#include "llvm/TableGen/TableGenBackend.h"
38#include <algorithm>
39#include <cassert>
40#include <cstddef>
41#include <cstdint>
42#include <deque>
43#include <iterator>
44#include <set>
45#include <string>
46#include <vector>
47
48using namespace llvm;
49
50static cl::OptionCategory RegisterInfoCat("Options for -gen-register-info");
51
52static cl::opt<bool>
53 RegisterInfoDebug("register-info-debug", cl::init(Val: false),
54 cl::desc("Dump register information to help debugging"),
55 cl::cat(RegisterInfoCat));
56
57namespace {
58
59class RegisterInfoEmitter {
60 const RecordKeeper &Records;
61 const CodeGenTarget Target;
62 CodeGenRegBank &RegBank;
63
64public:
65 RegisterInfoEmitter(const RecordKeeper &R)
66 : Records(R), Target(R), RegBank(Target.getRegBank()) {
67 RegBank.computeDerivedInfo();
68 }
69
70 // runEnums - Print out enum values for all of the registers.
71 void runEnums(raw_ostream &OS, raw_ostream &MainOS, StringRef FilenamePrefix);
72
73 // runMCDesc - Print out MC register descriptions.
74 void runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
75 StringRef FilenamePrefix);
76
77 // runTargetHeader - Emit a header fragment for the register info emitter.
78 void runTargetHeader(raw_ostream &OS, raw_ostream &MainOS,
79 StringRef FilenamePrefix);
80
81 // runTargetDesc - Output the target register and register file descriptions.
82 void runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
83 StringRef FilenamePrefix);
84
85 // run - Output the register file description.
86 TableGenOutputFiles run(StringRef FilenamePrefix);
87
88 void debugDump(raw_ostream &OS);
89
90private:
91 void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs,
92 bool isCtor);
93 void EmitRegMappingTables(raw_ostream &OS,
94 const std::deque<CodeGenRegister> &Regs,
95 bool isCtor);
96 void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName);
97 void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName);
98 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName);
99};
100
101} // end anonymous namespace
102
103static void emitInclude(StringRef FilenamePrefix, StringRef IncludeFile,
104 StringRef GuardMacro, raw_ostream &OS) {
105 OS << "#ifdef " << GuardMacro << '\n';
106 OS << "#undef " << GuardMacro << '\n';
107 OS << "#include \"" << FilenamePrefix << IncludeFile << "\"\n";
108 OS << "#endif\n\n";
109}
110
111// runEnums - Print out enum values for all of the registers.
112void RegisterInfoEmitter::runEnums(raw_ostream &OS, raw_ostream &MainOS,
113 StringRef FilenamePrefix) {
114 emitInclude(FilenamePrefix, IncludeFile: "Enums.inc", GuardMacro: "GET_REGINFO_ENUM", OS&: MainOS);
115
116 const auto &Registers = RegBank.getRegisters();
117
118 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
119 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
120
121 StringRef Namespace = Registers.front().TheDef->getValueAsString(FieldName: "Namespace");
122
123 emitSourceFileHeader(Desc: "Target Register Enum Values", OS);
124
125 OS << "namespace llvm {\n\n";
126
127 OS << "class MCRegisterClass;\n"
128 << "extern const MCRegisterClass " << Target.getName()
129 << "MCRegisterClasses[];\n\n";
130
131 if (!Namespace.empty())
132 OS << "namespace " << Namespace << " {\n";
133 OS << "enum : unsigned {\n NoRegister,\n";
134
135 for (const auto &Reg : Registers)
136 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
137 assert(Registers.size() == Registers.back().EnumValue &&
138 "Register enum value mismatch!");
139 OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n";
140 OS << "};\n";
141 if (!Namespace.empty())
142 OS << "} // end namespace " << Namespace << "\n";
143
144 const auto &RegisterClasses = RegBank.getRegClasses();
145 if (!RegisterClasses.empty()) {
146
147 // RegisterClass enums are stored as uint16_t in the tables.
148 assert(RegisterClasses.size() <= 0xffff &&
149 "Too many register classes to fit in tables");
150
151 OS << "\n// Register classes\n\n";
152 if (!Namespace.empty())
153 OS << "namespace " << Namespace << " {\n";
154 OS << "enum {\n";
155 for (const auto &RC : RegisterClasses)
156 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
157 OS << "\n};\n";
158 if (!Namespace.empty())
159 OS << "} // end namespace " << Namespace << "\n\n";
160 }
161
162 ArrayRef<const Record *> RegAltNameIndices = Target.getRegAltNameIndices();
163 // If the only definition is the default NoRegAltName, we don't need to
164 // emit anything.
165 if (RegAltNameIndices.size() > 1) {
166 OS << "\n// Register alternate name indices\n\n";
167 if (!Namespace.empty())
168 OS << "namespace " << Namespace << " {\n";
169 OS << "enum {\n";
170 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
171 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
172 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
173 OS << "};\n";
174 if (!Namespace.empty())
175 OS << "} // end namespace " << Namespace << "\n\n";
176 }
177
178 auto &SubRegIndices = RegBank.getSubRegIndices();
179 if (!SubRegIndices.empty()) {
180 OS << "\n// Subregister indices\n\n";
181 std::string Namespace = SubRegIndices.front().getNamespace();
182 if (!Namespace.empty())
183 OS << "namespace " << Namespace << " {\n";
184 OS << "enum : uint16_t {\n NoSubRegister,\n";
185 unsigned i = 0;
186 for (const auto &Idx : SubRegIndices)
187 OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
188 OS << " NUM_TARGET_SUBREGS\n};\n";
189 if (!Namespace.empty())
190 OS << "} // end namespace " << Namespace << "\n\n";
191 }
192
193 OS << "// Register pressure sets enum.\n";
194 if (!Namespace.empty())
195 OS << "namespace " << Namespace << " {\n";
196 OS << "enum RegisterPressureSets {\n";
197 unsigned NumSets = RegBank.getNumRegPressureSets();
198 for (unsigned i = 0; i < NumSets; ++i) {
199 const RegUnitSet &RegUnits = RegBank.getRegSetAt(Order: i);
200 OS << " " << RegUnits.Name << " = " << i << ",\n";
201 }
202 OS << "};\n";
203 if (!Namespace.empty())
204 OS << "} // end namespace " << Namespace << '\n';
205 OS << '\n';
206
207 OS << "} // end namespace llvm\n\n";
208}
209
210static void printInt(raw_ostream &OS, int Val) { OS << Val; }
211
212void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
213 StringRef ClassName) {
214 unsigned NumRCs = RegBank.getRegClasses().size();
215 unsigned NumSets = RegBank.getNumRegPressureSets();
216
217 OS << "/// Get the weight in units of pressure for this register class.\n"
218 << "const RegClassWeight &" << ClassName << "::\n"
219 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
220 << " static const RegClassWeight RCWeightTable[] = {\n";
221 for (const auto &RC : RegBank.getRegClasses()) {
222 const CodeGenRegister::Vec &Regs = RC.getMembers();
223 OS << " {" << RC.getWeight(RegBank) << ", ";
224 if (Regs.empty() || RC.Artificial)
225 OS << '0';
226 else {
227 std::vector<unsigned> RegUnits;
228 RC.buildRegUnitSet(RegBank, RegUnits);
229 OS << RegBank.getRegUnitSetWeight(Units: RegUnits);
230 }
231 OS << "}, \t// " << RC.getName() << "\n";
232 }
233 OS << " };\n"
234 << " return RCWeightTable[RC->getID()];\n"
235 << "}\n\n";
236
237 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
238 // bother generating a table.
239 bool RegUnitsHaveUnitWeight = true;
240 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
241 UnitIdx < UnitEnd; ++UnitIdx) {
242 if (RegBank.getRegUnit(RUID: UnitIdx).Weight > 1)
243 RegUnitsHaveUnitWeight = false;
244 }
245 OS << "/// Get the weight in units of pressure for this register unit.\n"
246 << "unsigned " << ClassName << "::\n"
247 << "getRegUnitWeight(MCRegUnit RegUnit) const {\n"
248 << " assert(static_cast<unsigned>(RegUnit) < "
249 << RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n";
250 if (!RegUnitsHaveUnitWeight) {
251 OS << " static const uint8_t RUWeightTable[] = {\n ";
252 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
253 UnitIdx < UnitEnd; ++UnitIdx) {
254 const RegUnit &RU = RegBank.getRegUnit(RUID: UnitIdx);
255 assert(RU.Weight < 256 && "RegUnit too heavy");
256 OS << RU.Weight << ", ";
257 }
258 OS << "};\n"
259 << " return RUWeightTable[static_cast<unsigned>(RegUnit)];\n";
260 } else {
261 OS << " // All register units have unit weight.\n"
262 << " return 1;\n";
263 }
264 OS << "}\n\n";
265
266 OS << "\n"
267 << "// Get the number of dimensions of register pressure.\n"
268 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
269 << " return " << NumSets << ";\n}\n\n";
270
271 OS << "// Get the name of this register unit pressure set.\n"
272 << "const char *" << ClassName << "::\n"
273 << "getRegPressureSetName(unsigned Idx) const {\n"
274 << " static const char *PressureNameTable[] = {\n";
275 unsigned MaxRegUnitWeight = 0;
276 for (unsigned i = 0; i < NumSets; ++i) {
277 const RegUnitSet &RegUnits = RegBank.getRegSetAt(Order: i);
278 MaxRegUnitWeight = std::max(a: MaxRegUnitWeight, b: RegUnits.Weight);
279 OS << " \"" << RegUnits.Name << "\",\n";
280 }
281 OS << " };\n"
282 << " return PressureNameTable[Idx];\n"
283 << "}\n\n";
284
285 OS << "// Get the register unit pressure limit for this dimension.\n"
286 << "// This limit must be adjusted dynamically for reserved registers.\n"
287 << "unsigned " << ClassName << "::\n"
288 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const "
289 "{\n"
290 << " static const " << getMinimalTypeForRange(Range: MaxRegUnitWeight, MaxSize: 32)
291 << " PressureLimitTable[] = {\n";
292 for (unsigned i = 0; i < NumSets; ++i) {
293 const RegUnitSet &RegUnits = RegBank.getRegSetAt(Order: i);
294 OS << " " << RegUnits.Weight << ", \t// " << i << ": " << RegUnits.Name
295 << "\n";
296 }
297 OS << " };\n"
298 << " return PressureLimitTable[Idx];\n"
299 << "}\n\n";
300
301 SequenceToOffsetTable<std::vector<int>> PSetsSeqs(/*Terminator=*/-1);
302
303 // This table may be larger than NumRCs if some register units needed a list
304 // of unit sets that did not correspond to a register class.
305 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
306 std::vector<std::vector<int>> PSets(NumRCUnitSets);
307
308 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
309 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(RCIdx: i);
310 PSets[i].reserve(n: PSetIDs.size());
311 for (unsigned PSetID : PSetIDs) {
312 PSets[i].push_back(x: RegBank.getRegPressureSet(Idx: PSetID).Order);
313 }
314 llvm::sort(C&: PSets[i]);
315 PSetsSeqs.add(Seq: PSets[i]);
316 }
317
318 PSetsSeqs.layout();
319
320 OS << "/// Table of pressure sets per register class or unit.\n"
321 << "static const int RCSetsTable[] = {\n";
322 PSetsSeqs.emit(OS, Print: printInt);
323 OS << "};\n\n";
324
325 OS << "/// Get the dimensions of register pressure impacted by this "
326 << "register class.\n"
327 << "/// Returns a -1 terminated array of pressure set IDs\n"
328 << "const int *" << ClassName << "::\n"
329 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
330 OS << " static const " << getMinimalTypeForRange(Range: PSetsSeqs.size() - 1, MaxSize: 32)
331 << " RCSetStartTable[] = {\n ";
332 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
333 OS << PSetsSeqs.get(Seq: PSets[i]) << ",";
334 }
335 OS << "};\n"
336 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
337 << "}\n\n";
338
339 OS << "/// Get the dimensions of register pressure impacted by this "
340 << "register unit.\n"
341 << "/// Returns a -1 terminated array of pressure set IDs\n"
342 << "const int *" << ClassName << "::\n"
343 << "getRegUnitPressureSets(MCRegUnit RegUnit) const {\n"
344 << " assert(static_cast<unsigned>(RegUnit) < "
345 << RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n";
346 OS << " static const " << getMinimalTypeForRange(Range: PSetsSeqs.size() - 1, MaxSize: 32)
347 << " RUSetStartTable[] = {\n ";
348 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
349 UnitIdx < UnitEnd; ++UnitIdx) {
350 OS << PSetsSeqs.get(Seq: PSets[RegBank.getRegUnit(RUID: UnitIdx).RegClassUnitSetsIdx])
351 << ",";
352 }
353 OS << "};\n"
354 << " return "
355 "&RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];\n"
356 << "}\n\n";
357}
358
359using DwarfRegNumsMapPair = std::pair<const Record *, std::vector<int64_t>>;
360using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>;
361
362static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) {
363 // Sort and unique to get a map-like vector. We want the last assignment to
364 // match previous behaviour.
365 llvm::stable_sort(Range&: DwarfRegNums, C: on_first<LessRecordRegister>());
366 // Warn about duplicate assignments.
367 const Record *LastSeenReg = nullptr;
368 for (const auto &X : DwarfRegNums) {
369 const auto &Reg = X.first;
370 // The only way LessRecordRegister can return equal is if they're the same
371 // string. Use simple equality instead.
372 if (LastSeenReg && Reg->getName() == LastSeenReg->getName())
373 PrintWarning(WarningLoc: Reg->getLoc(), Msg: Twine("DWARF numbers for register ") +
374 getQualifiedName(R: Reg) +
375 "specified multiple times");
376 LastSeenReg = Reg;
377 }
378 auto Last = llvm::unique(R&: DwarfRegNums, P: [](const DwarfRegNumsMapPair &A,
379 const DwarfRegNumsMapPair &B) {
380 return A.first->getName() == B.first->getName();
381 });
382 DwarfRegNums.erase(first: Last, last: DwarfRegNums.end());
383}
384
385void RegisterInfoEmitter::EmitRegMappingTables(
386 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
387 // Collect all information about dwarf register numbers
388 DwarfRegNumsVecTy DwarfRegNums;
389
390 // First, just pull all provided information to the map
391 unsigned maxLength = 0;
392 for (auto &RE : Regs) {
393 const Record *Reg = RE.TheDef;
394 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts(FieldName: "DwarfNumbers");
395 maxLength = std::max(a: (size_t)maxLength, b: RegNums.size());
396 DwarfRegNums.emplace_back(args&: Reg, args: std::move(RegNums));
397 }
398 finalizeDwarfRegNumsKeys(DwarfRegNums);
399
400 if (!maxLength)
401 return;
402
403 // Now we know maximal length of number list. Append -1's, where needed
404 for (auto &DwarfRegNum : DwarfRegNums)
405 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I)
406 DwarfRegNum.second.push_back(x: -1);
407
408 StringRef Namespace = Regs.front().TheDef->getValueAsString(FieldName: "Namespace");
409
410 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
411
412 // Emit reverse information about the dwarf register numbers.
413 for (unsigned j = 0; j < 2; ++j) {
414 for (unsigned I = 0, E = maxLength; I != E; ++I) {
415 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
416 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
417 OS << I << "Dwarf2L[]";
418
419 if (!isCtor) {
420 OS << " = {\n";
421
422 // Store the mapping sorted by the LLVM reg num so lookup can be done
423 // with a binary search.
424 std::map<uint64_t, const Record *> Dwarf2LMap;
425 for (auto &DwarfRegNum : DwarfRegNums) {
426 int DwarfRegNo = DwarfRegNum.second[I];
427 if (DwarfRegNo < 0)
428 continue;
429 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first;
430 }
431
432 for (auto &I : Dwarf2LMap)
433 OS << " { " << I.first << "U, " << getQualifiedName(R: I.second)
434 << " },\n";
435
436 OS << "};\n";
437 } else {
438 OS << ";\n";
439 }
440
441 // We have to store the size in a const global, it's used in multiple
442 // places.
443 OS << "extern const unsigned " << Namespace
444 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize";
445 if (!isCtor)
446 OS << " = std::size(" << Namespace
447 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n";
448 else
449 OS << ";\n\n";
450 }
451 }
452
453 for (auto &RE : Regs) {
454 const Record *Reg = RE.TheDef;
455 const RecordVal *V = Reg->getValue(Name: "DwarfAlias");
456 if (!V || !V->getValue())
457 continue;
458
459 const DefInit *DI = cast<DefInit>(Val: V->getValue());
460 const Record *Alias = DI->getDef();
461 const auto &AliasIter = llvm::lower_bound(
462 Range&: DwarfRegNums, Value&: Alias, C: [](const DwarfRegNumsMapPair &A, const Record *B) {
463 return LessRecordRegister()(A.first, B);
464 });
465 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias &&
466 "Expected Alias to be present in map");
467 const auto &RegIter = llvm::lower_bound(
468 Range&: DwarfRegNums, Value&: Reg, C: [](const DwarfRegNumsMapPair &A, const Record *B) {
469 return LessRecordRegister()(A.first, B);
470 });
471 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg &&
472 "Expected Reg to be present in map");
473 RegIter->second = AliasIter->second;
474 }
475
476 // Emit information about the dwarf register numbers.
477 for (unsigned j = 0; j < 2; ++j) {
478 for (unsigned i = 0, e = maxLength; i != e; ++i) {
479 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
480 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
481 OS << i << "L2Dwarf[]";
482 if (!isCtor) {
483 OS << " = {\n";
484 // Store the mapping sorted by the Dwarf reg num so lookup can be done
485 // with a binary search.
486 for (auto &DwarfRegNum : DwarfRegNums) {
487 int RegNo = DwarfRegNum.second[i];
488 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
489 continue;
490
491 OS << " { " << getQualifiedName(R: DwarfRegNum.first) << ", " << RegNo
492 << "U },\n";
493 }
494 OS << "};\n";
495 } else {
496 OS << ";\n";
497 }
498
499 // We have to store the size in a const global, it's used in multiple
500 // places.
501 OS << "extern const unsigned " << Namespace
502 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
503 if (!isCtor)
504 OS << " = std::size(" << Namespace
505 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
506 else
507 OS << ";\n\n";
508 }
509 }
510}
511
512void RegisterInfoEmitter::EmitRegMapping(
513 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
514 // Emit the initializer so the tables from EmitRegMappingTables get wired up
515 // to the MCRegisterInfo object.
516 unsigned maxLength = 0;
517 for (auto &RE : Regs) {
518 const Record *Reg = RE.TheDef;
519 maxLength = std::max(a: (size_t)maxLength,
520 b: Reg->getValueAsListOfInts(FieldName: "DwarfNumbers").size());
521 }
522
523 if (!maxLength)
524 return;
525
526 StringRef Namespace = Regs.front().TheDef->getValueAsString(FieldName: "Namespace");
527
528 // Emit reverse information about the dwarf register numbers.
529 for (unsigned j = 0; j < 2; ++j) {
530 OS << " switch (";
531 if (j == 0)
532 OS << "DwarfFlavour";
533 else
534 OS << "EHFlavour";
535 OS << ") {\n"
536 << " default:\n"
537 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
538
539 for (unsigned i = 0, e = maxLength; i != e; ++i) {
540 OS << " case " << i << ":\n";
541 OS << " ";
542 if (!isCtor)
543 OS << "RI->";
544 std::string Tmp;
545 raw_string_ostream(Tmp)
546 << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
547 << "Dwarf2L";
548 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
549 if (j == 0)
550 OS << "false";
551 else
552 OS << "true";
553 OS << ");\n";
554 OS << " break;\n";
555 }
556 OS << " }\n";
557 }
558
559 // Emit information about the dwarf register numbers.
560 for (unsigned j = 0; j < 2; ++j) {
561 OS << " switch (";
562 if (j == 0)
563 OS << "DwarfFlavour";
564 else
565 OS << "EHFlavour";
566 OS << ") {\n"
567 << " default:\n"
568 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
569
570 for (unsigned i = 0, e = maxLength; i != e; ++i) {
571 OS << " case " << i << ":\n";
572 OS << " ";
573 if (!isCtor)
574 OS << "RI->";
575 std::string Tmp;
576 raw_string_ostream(Tmp)
577 << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
578 << "L2Dwarf";
579 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
580 if (j == 0)
581 OS << "false";
582 else
583 OS << "true";
584 OS << ");\n";
585 OS << " break;\n";
586 }
587 OS << " }\n";
588 }
589}
590
591// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
592// Width is the number of bits per hex number.
593static void printBitVectorAsHex(raw_ostream &OS, const BitVector &Bits,
594 unsigned Width) {
595 assert(Width <= 32 && "Width too large");
596 unsigned Digits = (Width + 3) / 4;
597 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
598 unsigned Value = 0;
599 for (unsigned j = 0; j != Width && i + j != e; ++j)
600 Value |= Bits.test(Idx: i + j) << j;
601 OS << format(Fmt: "0x%0*x, ", Vals: Digits, Vals: Value);
602 }
603}
604
605// Helper to emit a set of bits into a constant byte array.
606class BitVectorEmitter {
607 BitVector Values;
608
609public:
610 void add(unsigned v) {
611 if (v >= Values.size())
612 Values.resize(N: ((v / 8) + 1) * 8); // Round up to the next byte.
613 Values[v] = true;
614 }
615
616 void print(raw_ostream &OS) { printBitVectorAsHex(OS, Bits: Values, Width: 8); }
617};
618
619static void printSimpleValueType(raw_ostream &OS, MVT VT) {
620 OS << getEnumName(T: VT);
621}
622
623static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
624 OS << (Idx ? Idx->EnumValue : 0);
625}
626
627// Differentially encoded register and regunit lists allow for better
628// compression on regular register banks. The sequence is computed from the
629// differential list as:
630//
631// out[0] = InitVal;
632// out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
633//
634// The initial value depends on the specific list. The list is terminated by a
635// 0 differential which means we can't encode repeated elements.
636
637using DiffVec = SmallVector<int16_t, 4>;
638using MaskVec = SmallVector<LaneBitmask, 4>;
639
640// Fills V with differentials between every two consecutive elements of List.
641static DiffVec &diffEncode(DiffVec &V, SparseBitVector<> List) {
642 assert(V.empty() && "Clear DiffVec before diffEncode.");
643 SparseBitVector<>::iterator I = List.begin(), E = List.end();
644 unsigned Val = *I;
645 while (++I != E) {
646 unsigned Cur = *I;
647 V.push_back(Elt: Cur - Val);
648 Val = Cur;
649 }
650 return V;
651}
652
653template <typename Iter>
654static DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
655 assert(V.empty() && "Clear DiffVec before diffEncode.");
656 unsigned Val = InitVal;
657 for (Iter I = Begin; I != End; ++I) {
658 unsigned Cur = (*I)->EnumValue;
659 V.push_back(Elt: Cur - Val);
660 Val = Cur;
661 }
662 return V;
663}
664
665static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; }
666
667static void printMask(raw_ostream &OS, LaneBitmask Val) {
668 OS << "LaneBitmask(0x" << PrintLaneMask(LaneMask: Val) << ')';
669}
670
671// Try to combine Idx's compose map into Vec if it is compatible.
672// Return false if it's not possible.
673static bool combine(const CodeGenSubRegIndex *Idx,
674 SmallVectorImpl<const CodeGenSubRegIndex *> &Vec) {
675 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
676 for (const auto &I : Map) {
677 const CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];
678 if (Entry && Entry != I.second)
679 return false;
680 }
681
682 // All entries are compatible. Make it so.
683 for (const auto &I : Map) {
684 const CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];
685 assert((!Entry || Entry == I.second) && "Expected EnumValue to be unique");
686 Entry = I.second;
687 }
688 return true;
689}
690
691void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
692 StringRef ClassName) {
693 const auto &SubRegIndices = RegBank.getSubRegIndices();
694
695 // Many sub-register indexes are composition-compatible, meaning that
696 //
697 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
698 //
699 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
700 // The illegal entries can be use as wildcards to compress the table further.
701
702 // Map each Sub-register index to a compatible table row.
703 SmallVector<unsigned, 4> RowMap;
704 SmallVector<SmallVector<const CodeGenSubRegIndex *, 4>, 4> Rows;
705
706 size_t SubRegIndicesSize = llvm::size(Range: SubRegIndices);
707 for (const auto &Idx : SubRegIndices) {
708 unsigned Found = ~0u;
709 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
710 if (combine(Idx: &Idx, Vec&: Rows[r])) {
711 Found = r;
712 break;
713 }
714 }
715 if (Found == ~0u) {
716 Found = Rows.size();
717 Rows.resize(N: Found + 1);
718 Rows.back().resize(N: SubRegIndicesSize);
719 combine(Idx: &Idx, Vec&: Rows.back());
720 }
721 RowMap.push_back(Elt: Found);
722 }
723
724 OS << "unsigned " << ClassName
725 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
726
727 // Output the row map if there are multiple rows.
728 if (Rows.size() > 1) {
729 OS << " static const " << getMinimalTypeForRange(Range: Rows.size(), MaxSize: 32)
730 << " RowMap[" << SubRegIndicesSize << "] = {\n ";
731 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
732 OS << RowMap[i] << ", ";
733 OS << "\n };\n";
734 }
735
736 // Output the rows.
737 OS << " static const " << getMinimalTypeForRange(Range: SubRegIndicesSize + 1, MaxSize: 32)
738 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
739 for (const auto &Row : Rows) {
740 OS << " { ";
741 for (const llvm::CodeGenSubRegIndex *Elem :
742 ArrayRef(&Row[0], SubRegIndicesSize))
743 if (Elem)
744 OS << Elem->getQualifiedName() << ", ";
745 else
746 OS << "0, ";
747 OS << "},\n";
748 }
749 OS << " };\n\n";
750
751 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n"
752 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
753 if (Rows.size() > 1)
754 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
755 else
756 OS << " return Rows[0][IdxB];\n";
757 OS << "}\n\n";
758
759 // Generate the reverse case.
760 //
761 // FIXME: This is the brute force approach. Compress the table similar to the
762 // forward case.
763 OS << "unsigned " << ClassName
764 << "::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const "
765 "{\n";
766 OS << " static const " << getMinimalTypeForRange(Range: SubRegIndicesSize + 1, MaxSize: 32)
767 << " Table[" << SubRegIndicesSize << "][" << SubRegIndicesSize
768 << "] = {\n";
769
770 // Find values where composeSubReg(A, X) == B;
771 for (const auto &IdxA : SubRegIndices) {
772 OS << " { ";
773
774 SmallVectorImpl<const CodeGenSubRegIndex *> &Row =
775 Rows[RowMap[IdxA.EnumValue - 1]];
776 for (const auto &IdxB : SubRegIndices) {
777 const CodeGenSubRegIndex *FoundReverse = nullptr;
778
779 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) {
780 const CodeGenSubRegIndex *This = &SubRegIndices[i];
781 const CodeGenSubRegIndex *Composed = Row[i];
782 if (Composed == &IdxB) {
783 if (FoundReverse && FoundReverse != This) // Not unique
784 break;
785 FoundReverse = This;
786 }
787 }
788
789 if (FoundReverse) {
790 OS << FoundReverse->getQualifiedName() << ", ";
791 } else {
792 OS << "0, ";
793 }
794 }
795 OS << "},\n";
796 }
797
798 OS << " };\n\n";
799 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
800 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
801 OS << " return Table[IdxA][IdxB];\n";
802 OS << " }\n\n";
803}
804
805void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
806 StringRef ClassName) {
807 // See the comments in computeSubRegLaneMasks() for our goal here.
808 const auto &SubRegIndices = RegBank.getSubRegIndices();
809
810 // Create a list of Mask+Rotate operations, with equivalent entries merged.
811 SmallVector<unsigned, 4> SubReg2SequenceIndexMap;
812 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences;
813 for (const auto &Idx : SubRegIndices) {
814 const SmallVector<MaskRolPair, 1> &IdxSequence =
815 Idx.CompositionLaneMaskTransform;
816
817 unsigned Found = ~0u;
818 unsigned SIdx = 0;
819 unsigned NextSIdx;
820 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) {
821 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
822 NextSIdx = SIdx + Sequence.size() + 1;
823 if (Sequence == IdxSequence) {
824 Found = SIdx;
825 break;
826 }
827 }
828 if (Found == ~0u) {
829 Sequences.push_back(Elt: IdxSequence);
830 Found = SIdx;
831 }
832 SubReg2SequenceIndexMap.push_back(Elt: Found);
833 }
834
835 OS << " struct MaskRolOp {\n"
836 " LaneBitmask Mask;\n"
837 " uint8_t RotateLeft;\n"
838 " };\n"
839 " static const MaskRolOp LaneMaskComposeSequences[] = {\n";
840 unsigned Idx = 0;
841 for (size_t s = 0, se = Sequences.size(); s != se; ++s) {
842 OS << " ";
843 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
844 for (const MaskRolPair &P : Sequence) {
845 printMask(OS&: OS << "{ ", Val: P.Mask);
846 OS << format(Fmt: ", %2u }, ", Vals: P.RotateLeft);
847 }
848 OS << "{ LaneBitmask::getNone(), 0 }";
849 if (s + 1 != se)
850 OS << ", ";
851 OS << " // Sequence " << Idx << "\n";
852 Idx += Sequence.size() + 1;
853 }
854 auto *IntType =
855 getMinimalTypeForRange(Range: *llvm::max_element(Range&: SubReg2SequenceIndexMap));
856 OS << " };\n"
857 " static const "
858 << IntType << " CompositeSequences[] = {\n";
859 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) {
860 OS << " ";
861 OS << SubReg2SequenceIndexMap[i];
862 if (i + 1 != e)
863 OS << ",";
864 OS << " // to " << SubRegIndices[i].getName() << "\n";
865 }
866 OS << " };\n\n";
867
868 OS << "LaneBitmask " << ClassName
869 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)"
870 " const {\n"
871 " --IdxA; assert(IdxA < "
872 << SubRegIndices.size()
873 << " && \"Subregister index out of bounds\");\n"
874 " LaneBitmask Result;\n"
875 " for (const MaskRolOp *Ops =\n"
876 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n"
877 " Ops->Mask.any(); ++Ops) {\n"
878 " LaneBitmask::Type M = LaneMask.getAsInteger() & "
879 "Ops->Mask.getAsInteger();\n"
880 " if (unsigned S = Ops->RotateLeft)\n"
881 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - "
882 "S)));\n"
883 " else\n"
884 " Result |= LaneBitmask(M);\n"
885 " }\n"
886 " return Result;\n"
887 "}\n\n";
888
889 OS << "LaneBitmask " << ClassName
890 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, "
891 " LaneBitmask LaneMask) const {\n"
892 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n"
893 " --IdxA; assert(IdxA < "
894 << SubRegIndices.size()
895 << " && \"Subregister index out of bounds\");\n"
896 " LaneBitmask Result;\n"
897 " for (const MaskRolOp *Ops =\n"
898 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n"
899 " Ops->Mask.any(); ++Ops) {\n"
900 " LaneBitmask::Type M = LaneMask.getAsInteger();\n"
901 " if (unsigned S = Ops->RotateLeft)\n"
902 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - "
903 "S)));\n"
904 " else\n"
905 " Result |= LaneBitmask(M);\n"
906 " }\n"
907 " return Result;\n"
908 "}\n\n";
909}
910
911//
912// runMCDesc - Print out MC register descriptions.
913//
914void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
915 StringRef FilenamePrefix) {
916 emitInclude(FilenamePrefix, IncludeFile: "MCDesc.inc", GuardMacro: "GET_REGINFO_MC_DESC", OS&: MainOS);
917
918 emitSourceFileHeader(Desc: "MC Register Information", OS);
919
920 const auto &Regs = RegBank.getRegisters();
921
922 auto &SubRegIndices = RegBank.getSubRegIndices();
923 // The lists of sub-registers and super-registers go in the same array. That
924 // allows us to share suffixes.
925 using RegVec = std::vector<const CodeGenRegister *>;
926
927 // Differentially encoded lists.
928 SequenceToOffsetTable<DiffVec> DiffSeqs;
929 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
930 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
931 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
932
933 // List of lane masks accompanying register unit sequences.
934 SequenceToOffsetTable<MaskVec> LaneMaskSeqs(/*Terminator=*/std::nullopt);
935 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());
936
937 // Keep track of sub-register names as well. These are not differentially
938 // encoded.
939 using SubRegIdxVec = SmallVector<const CodeGenSubRegIndex *, 4>;
940 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs(
941 /*Terminator=*/std::nullopt);
942 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
943
944 SequenceToOffsetTable<std::string> RegStrings;
945
946 // Precompute register lists for the SequenceToOffsetTable.
947 unsigned i = 0;
948 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
949 const auto &Reg = *I;
950 RegStrings.add(Seq: Reg.getName().str());
951
952 // Compute the ordered sub-register list.
953 SetVector<const CodeGenRegister *> SR;
954 Reg.addSubRegsPreOrder(OSet&: SR, RegBank);
955 diffEncode(V&: SubRegLists[i], InitVal: Reg.EnumValue, Begin: SR.begin(), End: SR.end());
956 DiffSeqs.add(Seq: SubRegLists[i]);
957
958 // Compute the corresponding sub-register indexes.
959 SubRegIdxVec &SRIs = SubRegIdxLists[i];
960 for (const CodeGenRegister *S : SR)
961 SRIs.push_back(Elt: Reg.getSubRegIndex(Reg: S));
962 SubRegIdxSeqs.add(Seq: SRIs);
963
964 // Super-registers are already computed.
965 const RegVec &SuperRegList = Reg.getSuperRegs();
966 diffEncode(V&: SuperRegLists[i], InitVal: Reg.EnumValue, Begin: SuperRegList.begin(),
967 End: SuperRegList.end());
968 DiffSeqs.add(Seq: SuperRegLists[i]);
969
970 const SparseBitVector<> &RUs = Reg.getNativeRegUnits();
971 DiffSeqs.add(Seq: diffEncode(V&: RegUnitLists[i], List: RUs));
972
973 const auto &RUMasks = Reg.getRegUnitLaneMasks();
974 MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
975 assert(LaneMaskVec.empty());
976 llvm::append_range(C&: LaneMaskVec, R: RUMasks);
977 LaneMaskSeqs.add(Seq: LaneMaskVec);
978 }
979
980 // Compute the final layout of the sequence table.
981 DiffSeqs.layout();
982 LaneMaskSeqs.layout();
983 SubRegIdxSeqs.layout();
984
985 OS << "namespace llvm {\n\n";
986
987 const std::string &TargetName = Target.getName().str();
988
989 // Emit the shared table of differential lists.
990 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n";
991 DiffSeqs.emit(OS, Print: printDiff16);
992 OS << "};\n\n";
993
994 // Emit the shared table of regunit lane mask sequences.
995 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n";
996 LaneMaskSeqs.emit(OS, Print: printMask);
997 OS << "};\n\n";
998
999 // Emit the table of sub-register indexes.
1000 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
1001 SubRegIdxSeqs.emit(OS, Print: printSubRegIndex);
1002 OS << "};\n\n";
1003
1004 // Emit the string table.
1005 RegStrings.layout();
1006 RegStrings.emitStringLiteralDef(OS, Decl: Twine("extern const char ") + TargetName +
1007 "RegStrings[]");
1008
1009 OS << "extern const MCRegisterDesc " << TargetName
1010 << "RegDesc[] = { // Descriptors\n";
1011 OS << " { " << RegStrings.get(Seq: "") << ", 0, 0, 0, 0, 0, 0, 0 },\n";
1012
1013 // Emit the register descriptors now.
1014 i = 0;
1015 for (const auto &Reg : Regs) {
1016 unsigned FirstRU = Reg.getNativeRegUnits().find_first();
1017 unsigned Offset = DiffSeqs.get(Seq: RegUnitLists[i]);
1018 // The value must be kept in sync with MCRegisterInfo.h.
1019 constexpr unsigned RegUnitBits = 12;
1020 assert(isUInt<RegUnitBits>(FirstRU) && "Too many regunits");
1021 assert(isUInt<32 - RegUnitBits>(Offset) && "Offset is too big");
1022 OS << " { " << RegStrings.get(Seq: Reg.getName().str()) << ", "
1023 << DiffSeqs.get(Seq: SubRegLists[i]) << ", " << DiffSeqs.get(Seq: SuperRegLists[i])
1024 << ", " << SubRegIdxSeqs.get(Seq: SubRegIdxLists[i]) << ", "
1025 << (Offset << RegUnitBits | FirstRU) << ", "
1026 << LaneMaskSeqs.get(Seq: RegUnitLaneMasks[i]) << ", " << Reg.Constant << ", "
1027 << Reg.Artificial << " },\n";
1028 ++i;
1029 }
1030 OS << "};\n\n"; // End of register descriptors...
1031
1032 // Emit the table of register unit roots. Each regunit has one or two root
1033 // registers.
1034 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
1035 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
1036 ArrayRef<const CodeGenRegister *> Roots = RegBank.getRegUnit(RUID: i).getRoots();
1037 assert(!Roots.empty() && "All regunits must have a root register.");
1038 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
1039 OS << " { ";
1040 ListSeparator LS;
1041 for (const CodeGenRegister *R : Roots)
1042 OS << LS << getQualifiedName(R: R->TheDef);
1043 OS << " },\n";
1044 }
1045 OS << "};\n\n";
1046
1047 // Emit the table of register unit intervals.
1048 if (Target.getRegistersAreIntervals()) {
1049 OS << "extern const unsigned " << TargetName
1050 << "RegUnitIntervals[][2] = {\n";
1051 for (const CodeGenRegister &Reg : Regs) {
1052 const auto &Units = Reg.getNativeRegUnits();
1053 if (Units.empty()) {
1054 OS << " { 0, 0 },\n";
1055 } else {
1056 unsigned First = Units.find_first();
1057 unsigned Last = Units.find_last();
1058 OS << " { " << First << ", " << Last + 1 << " },\n";
1059 }
1060 }
1061 OS << "};\n\n";
1062 }
1063
1064 const auto &RegisterClasses = RegBank.getRegClasses();
1065
1066 // Loop over all of the register classes... emitting each one.
1067 OS << "namespace { // Register classes...\n";
1068
1069 SequenceToOffsetTable<std::string> RegClassStrings;
1070
1071 // Emit the register enum value arrays for each RegisterClass
1072 for (const auto &RC : RegisterClasses) {
1073 ArrayRef<const Record *> Order = RC.getOrder();
1074
1075 // Give the register class a legal C name if it's anonymous.
1076 const std::string &Name = RC.getName();
1077
1078 RegClassStrings.add(Seq: Name);
1079
1080 // Emit the register list now (unless it would be a zero-length array).
1081 if (!Order.empty()) {
1082 OS << " // " << Name << " Register Class...\n"
1083 << " const MCPhysReg " << Name << "[] = {\n ";
1084 for (const Record *Reg : Order) {
1085 OS << getQualifiedName(R: Reg) << ", ";
1086 }
1087 OS << "\n };\n\n";
1088
1089 OS << " // " << Name << " Bit set.\n"
1090 << " const uint8_t " << Name << "Bits[] = {\n ";
1091 BitVectorEmitter BVE;
1092 for (const Record *Reg : Order) {
1093 BVE.add(v: RegBank.getReg(Reg)->EnumValue);
1094 }
1095 BVE.print(OS);
1096 OS << "\n };\n\n";
1097 }
1098 }
1099 OS << "} // end anonymous namespace\n\n";
1100
1101 RegClassStrings.layout();
1102 RegClassStrings.emitStringLiteralDef(
1103 OS, Decl: Twine("extern const char ") + TargetName + "RegClassStrings[]");
1104
1105 OS << "extern const MCRegisterClass " << TargetName
1106 << "MCRegisterClasses[] = {\n";
1107
1108 for (const auto &RC : RegisterClasses) {
1109 ArrayRef<const Record *> Order = RC.getOrder();
1110 std::string RCName = Order.empty() ? "nullptr" : RC.getName();
1111 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits";
1112 std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName + ")";
1113 uint32_t RegSize = 0;
1114 if (RC.RSI.isSimple())
1115 RegSize = RC.RSI.getSimple().RegSize;
1116 OS << " { " << RCName << ", " << RCBitsName << ", "
1117 << RegClassStrings.get(Seq: RC.getName()) << ", " << RC.getOrder().size()
1118 << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", "
1119 << RegSize << ", " << static_cast<unsigned>(RC.CopyCost) << ", "
1120 << (RC.Allocatable ? "true" : "false") << ", "
1121 << (RC.getBaseClassOrder() ? "true" : "false") << " },\n";
1122 }
1123
1124 OS << "};\n\n";
1125
1126 EmitRegMappingTables(OS, Regs, isCtor: false);
1127
1128 // Emit Reg encoding table
1129 OS << "extern const uint16_t " << TargetName;
1130 OS << "RegEncodingTable[] = {\n";
1131 // Add entry for NoRegister
1132 OS << " 0,\n";
1133 for (const auto &RE : Regs) {
1134 const Record *Reg = RE.TheDef;
1135 const BitsInit *BI = Reg->getValueAsBitsInit(FieldName: "HWEncoding");
1136 uint64_t Value = BI->convertKnownBitsToInt();
1137 OS << " " << Value << ",\n";
1138 }
1139 OS << "};\n"; // End of HW encoding table
1140
1141 // MCRegisterInfo initialization routine.
1142 OS << "static inline void Init" << TargetName
1143 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
1144 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
1145 "{\n"
1146 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
1147 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
1148 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
1149 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
1150 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
1151 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
1152 << (llvm::size(Range: SubRegIndices) + 1) << ",\n"
1153 << TargetName << "RegEncodingTable);\n\n";
1154
1155 EmitRegMapping(OS, Regs, isCtor: false);
1156
1157 OS << "}\n\n";
1158
1159 OS << "} // end namespace llvm\n\n";
1160}
1161
1162void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS,
1163 StringRef FilenamePrefix) {
1164 emitInclude(FilenamePrefix, IncludeFile: "Header.inc", GuardMacro: "GET_REGINFO_HEADER", OS&: MainOS);
1165
1166 emitSourceFileHeader(Desc: "Register Information Header Fragment", OS);
1167
1168 const std::string &TargetName = Target.getName().str();
1169 std::string ClassName = TargetName + "GenRegisterInfo";
1170
1171 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n";
1172
1173 OS << "namespace llvm {\n\n";
1174
1175 OS << "class " << TargetName << "FrameLowering;\n\n";
1176
1177 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
1178 << " explicit " << ClassName
1179 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n"
1180 << " unsigned PC = 0, unsigned HwMode = 0);\n";
1181 if (!RegBank.getSubRegIndices().empty()) {
1182 OS << " unsigned composeSubRegIndicesImpl"
1183 << "(unsigned, unsigned) const override;\n"
1184 << " unsigned reverseComposeSubRegIndicesImpl"
1185 << "(unsigned, unsigned) const override;\n"
1186 << " LaneBitmask composeSubRegIndexLaneMaskImpl"
1187 << "(unsigned, LaneBitmask) const override;\n"
1188 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl"
1189 << "(unsigned, LaneBitmask) const override;\n"
1190 << " const TargetRegisterClass *getSubClassWithSubReg"
1191 << "(const TargetRegisterClass *, unsigned) const override;\n"
1192 << " const TargetRegisterClass *getSubRegisterClass"
1193 << "(const TargetRegisterClass *, unsigned) const override;\n";
1194 }
1195 OS << " const RegClassWeight &getRegClassWeight("
1196 << "const TargetRegisterClass *RC) const override;\n"
1197 << " unsigned getRegUnitWeight(MCRegUnit RegUnit) const override;\n"
1198 << " unsigned getNumRegPressureSets() const override;\n"
1199 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
1200 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned "
1201 "Idx) const override;\n"
1202 << " const int *getRegClassPressureSets("
1203 << "const TargetRegisterClass *RC) const override;\n"
1204 << " const int *getRegUnitPressureSets("
1205 << "MCRegUnit RegUnit) const override;\n"
1206 << " ArrayRef<const char *> getRegMaskNames() const override;\n"
1207 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n"
1208 << " bool isGeneralPurposeRegister(const MachineFunction &, "
1209 << "MCRegister) const override;\n"
1210 << " bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)"
1211 << " const override;\n"
1212 << " bool isFixedRegister(const MachineFunction &, "
1213 << "MCRegister) const override;\n"
1214 << " bool isArgumentRegister(const MachineFunction &, "
1215 << "MCRegister) const override;\n"
1216 << " bool isConstantPhysReg(MCRegister PhysReg) const override final;\n"
1217 << " /// Devirtualized TargetFrameLowering.\n"
1218 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n"
1219 << " const MachineFunction &MF);\n";
1220
1221 const auto &RegisterClasses = RegBank.getRegClasses();
1222 if (llvm::any_of(Range: RegisterClasses,
1223 P: [](const auto &RC) { return RC.getBaseClassOrder(); })) {
1224 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) "
1225 "const override;\n";
1226 }
1227
1228 OS << "};\n\n";
1229
1230 if (!RegisterClasses.empty()) {
1231 OS << "namespace " << RegisterClasses.front().Namespace
1232 << " { // Register classes\n";
1233
1234 for (const auto &RC : RegisterClasses) {
1235 const std::string &Name = RC.getName();
1236
1237 // Output the extern for the instance.
1238 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1239 }
1240 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n";
1241 }
1242 OS << "} // end namespace llvm\n\n";
1243}
1244
1245//
1246// runTargetDesc - Output the target register and register file descriptions.
1247//
1248void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
1249 StringRef FilenamePrefix) {
1250 emitInclude(FilenamePrefix, IncludeFile: "TargetDesc.inc", GuardMacro: "GET_REGINFO_TARGET_DESC",
1251 OS&: MainOS);
1252
1253 emitSourceFileHeader(Desc: "Target Register and Register Classes Information", OS);
1254
1255 OS << "namespace llvm {\n\n";
1256
1257 // Get access to MCRegisterClass data.
1258 OS << "extern const MCRegisterClass " << Target.getName()
1259 << "MCRegisterClasses[];\n";
1260
1261 // Start out by emitting each of the register classes.
1262 const auto &RegisterClasses = RegBank.getRegClasses();
1263 const auto &SubRegIndices = RegBank.getSubRegIndices();
1264
1265 // Collect all registers belonging to any allocatable class.
1266 std::set<const Record *> AllocatableRegs;
1267
1268 // Collect allocatable registers.
1269 for (const auto &RC : RegisterClasses) {
1270 ArrayRef<const Record *> Order = RC.getOrder();
1271
1272 if (RC.Allocatable)
1273 AllocatableRegs.insert(first: Order.begin(), last: Order.end());
1274 }
1275
1276 const CodeGenHwModes &CGH = Target.getHwModes();
1277 unsigned NumModes = CGH.getNumModeIds();
1278
1279 // Build a shared array of value types.
1280 SequenceToOffsetTable<std::vector<MVT>> VTSeqs(
1281 /*Terminator=*/MVT::Other);
1282 for (unsigned M = 0; M < NumModes; ++M) {
1283 for (const auto &RC : RegisterClasses) {
1284 std::vector<MVT> S;
1285 for (const ValueTypeByHwMode &VVT : RC.VTs)
1286 if (VVT.hasDefault() || VVT.hasMode(M))
1287 S.push_back(x: VVT.get(Mode: M));
1288 VTSeqs.add(Seq: S);
1289 }
1290 }
1291 VTSeqs.layout();
1292 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1293 VTSeqs.emit(OS, Print: printSimpleValueType);
1294 OS << "};\n";
1295
1296 // Emit SubRegIndex names, skipping 0.
1297 OS << "\nstatic const char *SubRegIndexNameTable[] = { \"";
1298
1299 for (const auto &Idx : SubRegIndices) {
1300 OS << Idx.getName();
1301 OS << "\", \"";
1302 }
1303 OS << "\" };\n\n";
1304
1305 // Emit the table of sub-register index sizes.
1306 OS << "static const TargetRegisterInfo::SubRegCoveredBits "
1307 "SubRegIdxRangeTable[] = {\n";
1308 for (unsigned M = 0; M < NumModes; ++M) {
1309 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
1310 for (const auto &Idx : SubRegIndices) {
1311 const SubRegRange &Range = Idx.Range.get(Mode: M);
1312 OS << " { " << Range.Offset << ", " << Range.Size << " },\t// "
1313 << Idx.getName() << "\n";
1314 }
1315 }
1316 OS << "};\n\n";
1317
1318 // Emit SubRegIndex lane masks, including 0.
1319 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n "
1320 "LaneBitmask::getAll(),\n";
1321 for (const auto &Idx : SubRegIndices) {
1322 printMask(OS&: OS << " ", Val: Idx.LaneMask);
1323 OS << ", // " << Idx.getName() << '\n';
1324 }
1325 OS << " };\n\n";
1326
1327 OS << "\n";
1328
1329 // Now that all of the structs have been emitted, emit the instances.
1330 if (!RegisterClasses.empty()) {
1331 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]"
1332 << " = {\n";
1333 for (unsigned M = 0; M < NumModes; ++M) {
1334 unsigned EV = 0;
1335 OS << " // Mode = " << M << " (";
1336 if (M == 0)
1337 OS << "Default";
1338 else
1339 OS << CGH.getMode(Id: M).Name;
1340 OS << ")\n";
1341 for (const auto &RC : RegisterClasses) {
1342 assert(RC.EnumValue == EV && "Unexpected order of register classes");
1343 ++EV;
1344 (void)EV;
1345 const RegSizeInfo &RI = RC.RSI.get(Mode: M);
1346 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", "
1347 << RI.SpillAlignment;
1348 std::vector<MVT> VTs;
1349 for (const ValueTypeByHwMode &VVT : RC.VTs)
1350 if (VVT.hasDefault() || VVT.hasMode(M))
1351 VTs.push_back(x: VVT.get(Mode: M));
1352 OS << ", /*VTLists+*/" << VTSeqs.get(Seq: VTs) << " }, // "
1353 << RC.getName() << '\n';
1354 }
1355 }
1356 OS << "};\n";
1357
1358 // Emit register class bit mask tables. The first bit mask emitted for a
1359 // register class, RC, is the set of sub-classes, including RC itself.
1360 //
1361 // If RC has super-registers, also create a list of subreg indices and bit
1362 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1363 // SuperRC, that satisfies:
1364 //
1365 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1366 //
1367 // The 0-terminated list of subreg indices starts at:
1368 //
1369 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1370 //
1371 // The corresponding bitmasks follow the sub-class mask in memory. Each
1372 // mask has RCMaskWords uint32_t entries.
1373 //
1374 // Every bit mask present in the list has at least one bit set.
1375
1376 // Compress the sub-reg index lists.
1377 using IdxList = std::vector<const CodeGenSubRegIndex *>;
1378 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1379 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs;
1380 BitVector MaskBV(RegisterClasses.size());
1381
1382 for (const auto &RC : RegisterClasses) {
1383 OS << "static const uint32_t " << RC.getName()
1384 << "SubClassMask[] = {\n ";
1385 printBitVectorAsHex(OS, Bits: RC.getSubClasses(), Width: 32);
1386
1387 // Emit super-reg class masks for any relevant SubRegIndices that can
1388 // project into RC.
1389 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1390 for (auto &Idx : SubRegIndices) {
1391 MaskBV.reset();
1392 RC.getSuperRegClasses(SubIdx: &Idx, Out&: MaskBV);
1393 if (MaskBV.none())
1394 continue;
1395 SRIList.push_back(x: &Idx);
1396 OS << "\n ";
1397 printBitVectorAsHex(OS, Bits: MaskBV, Width: 32);
1398 OS << "// " << Idx.getName();
1399 }
1400 SuperRegIdxSeqs.add(Seq: SRIList);
1401 OS << "\n};\n\n";
1402 }
1403
1404 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1405 SuperRegIdxSeqs.layout();
1406 SuperRegIdxSeqs.emit(OS, Print: printSubRegIndex);
1407 OS << "};\n\n";
1408
1409 // Emit super-class lists.
1410 for (const auto &RC : RegisterClasses) {
1411 ArrayRef<CodeGenRegisterClass *> Supers = RC.getSuperClasses();
1412
1413 // Skip classes without supers.
1414 if (Supers.empty())
1415 continue;
1416
1417 OS << "static unsigned const " << RC.getName() << "Superclasses[] = {\n";
1418 for (const auto *Super : Supers)
1419 OS << " " << Super->getQualifiedIdName() << ",\n";
1420 OS << "};\n\n";
1421 }
1422
1423 // Emit methods.
1424 for (const auto &RC : RegisterClasses) {
1425 if (!RC.AltOrderSelect.empty()) {
1426 OS << "\nstatic inline unsigned " << RC.getName()
1427 << "AltOrderSelect(const MachineFunction &MF, bool Rev) {"
1428 << RC.AltOrderSelect << "}\n\n"
1429 << "static ArrayRef<MCPhysReg> " << RC.getName()
1430 << "GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {\n";
1431 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) {
1432 ArrayRef<const Record *> Elems = RC.getOrder(No: oi);
1433 if (!Elems.empty()) {
1434 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1435 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1436 OS << (elem ? ", " : " ") << getQualifiedName(R: Elems[elem]);
1437 OS << " };\n";
1438 }
1439 }
1440 OS << " const MCRegisterClass &MCR = " << Target.getName()
1441 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1442 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1443 << " ArrayRef(MCR.begin(), MCR.getNumRegs()";
1444 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1445 if (RC.getOrder(No: oi).empty())
1446 OS << "),\n ArrayRef<MCPhysReg>(";
1447 else
1448 OS << "),\n ArrayRef(AltOrder" << oi;
1449 OS << ")\n };\n const unsigned Select = " << RC.getName()
1450 << "AltOrderSelect(MF, Rev);\n assert(Select < "
1451 << RC.getNumOrders() << ");\n return Order[Select];\n}\n";
1452 }
1453 }
1454
1455 // Now emit the actual value-initialized register class instances.
1456 OS << "\nnamespace " << RegisterClasses.front().Namespace
1457 << " { // Register class instances\n";
1458
1459 for (const auto &RC : RegisterClasses) {
1460 OS << " extern const TargetRegisterClass " << RC.getName()
1461 << "RegClass = {\n " << '&' << Target.getName()
1462 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
1463 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1464 << SuperRegIdxSeqs.get(Seq: SuperRegIdxLists[RC.EnumValue]) << ",\n ";
1465 printMask(OS, Val: RC.LaneMask);
1466 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n "
1467 << (RC.GlobalPriority ? "true" : "false") << ",\n "
1468 << format(Fmt: "0x%02x", Vals: RC.TSFlags) << ", /* TSFlags */\n "
1469 << (RC.HasDisjunctSubRegs ? "true" : "false")
1470 << ", /* HasDisjunctSubRegs */\n "
1471 << (RC.CoveredBySubRegs ? "true" : "false")
1472 << ", /* CoveredBySubRegs */\n ";
1473 if (RC.getSuperClasses().empty())
1474 OS << "nullptr, ";
1475 else
1476 OS << RC.getName() << "Superclasses, ";
1477 OS << RC.getSuperClasses().size() << ",\n ";
1478 if (RC.AltOrderSelect.empty())
1479 OS << "nullptr\n";
1480 else
1481 OS << RC.getName() << "GetRawAllocationOrder\n";
1482 OS << " };\n\n";
1483 }
1484
1485 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";
1486 }
1487
1488 OS << "\nnamespace {\n";
1489 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n";
1490 for (const auto &RC : RegisterClasses)
1491 OS << " &" << RC.getQualifiedName() << "RegClass,\n";
1492 OS << " };\n";
1493 OS << "} // end anonymous namespace\n";
1494
1495 // Emit extra information about registers.
1496 const std::string &TargetName = Target.getName().str();
1497 const auto &Regs = RegBank.getRegisters();
1498 unsigned NumRegCosts = 1;
1499 for (const auto &Reg : Regs)
1500 NumRegCosts = std::max(a: (size_t)NumRegCosts, b: Reg.CostPerUse.size());
1501
1502 std::vector<unsigned> AllRegCostPerUse;
1503 llvm::BitVector InAllocClass(Regs.size() + 1, false);
1504 AllRegCostPerUse.insert(position: AllRegCostPerUse.end(), n: NumRegCosts, x: 0);
1505
1506 // Populate the vector RegCosts with the CostPerUse list of the registers
1507 // in the order they are read. Have at most NumRegCosts entries for
1508 // each register. Fill with zero for values which are not explicitly given.
1509 for (const auto &Reg : Regs) {
1510 auto Costs = Reg.CostPerUse;
1511 llvm::append_range(C&: AllRegCostPerUse, R&: Costs);
1512 if (NumRegCosts > Costs.size())
1513 AllRegCostPerUse.insert(position: AllRegCostPerUse.end(),
1514 n: NumRegCosts - Costs.size(), x: 0);
1515
1516 if (AllocatableRegs.count(x: Reg.TheDef))
1517 InAllocClass.set(Reg.EnumValue);
1518 }
1519
1520 // Emit the cost values as a 1D-array after grouping them by their indices,
1521 // i.e. the costs for all registers corresponds to index 0, 1, 2, etc.
1522 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1).
1523 OS << "\nstatic const uint8_t "
1524 << "CostPerUseTable[] = { \n";
1525 for (unsigned int I = 0; I < NumRegCosts; ++I) {
1526 for (unsigned J = I, E = AllRegCostPerUse.size(); J < E; J += NumRegCosts)
1527 OS << AllRegCostPerUse[J] << ", ";
1528 }
1529 OS << "};\n\n";
1530
1531 OS << "\nstatic const bool "
1532 << "InAllocatableClassTable[] = { \n";
1533 for (unsigned I = 0, E = InAllocClass.size(); I < E; ++I) {
1534 OS << (InAllocClass[I] ? "true" : "false") << ", ";
1535 }
1536 OS << "};\n\n";
1537
1538 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName
1539 << "RegInfoDesc = { // Extra Descriptors\n";
1540 OS << "CostPerUseTable, " << NumRegCosts << ", "
1541 << "InAllocatableClassTable";
1542 OS << "};\n\n"; // End of register descriptors...
1543
1544 std::string ClassName = Target.getName().str() + "GenRegisterInfo";
1545
1546 size_t SubRegIndicesSize = llvm::size(Range: SubRegIndices);
1547
1548 if (!SubRegIndices.empty()) {
1549 emitComposeSubRegIndices(OS, ClassName);
1550 emitComposeSubRegIndexLaneMask(OS, ClassName);
1551 }
1552
1553 if (!SubRegIndices.empty()) {
1554 // Emit getSubClassWithSubReg.
1555 OS << "const TargetRegisterClass *" << ClassName
1556 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1557 << " const {\n";
1558 // Use the smallest type that can hold a regclass ID with room for a
1559 // sentinel.
1560 if (RegisterClasses.size() <= UINT8_MAX)
1561 OS << " static const uint8_t Table[";
1562 else if (RegisterClasses.size() <= UINT16_MAX)
1563 OS << " static const uint16_t Table[";
1564 else
1565 PrintFatalError(Msg: "Too many register classes.");
1566 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1567 for (const auto &RC : RegisterClasses) {
1568 OS << " {\t// " << RC.getName() << "\n";
1569 for (auto &Idx : SubRegIndices) {
1570 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(SubIdx: &Idx))
1571 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1572 << " -> " << SRC->getName() << "\n";
1573 else
1574 OS << " 0,\t// " << Idx.getName() << "\n";
1575 }
1576 OS << " },\n";
1577 }
1578 OS << " };\n assert(RC && \"Missing regclass\");\n"
1579 << " if (!Idx) return RC;\n --Idx;\n"
1580 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
1581 << " unsigned TV = Table[RC->getID()][Idx];\n"
1582 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1583
1584 // Emit getSubRegisterClass
1585 OS << "const TargetRegisterClass *" << ClassName
1586 << "::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx)"
1587 << " const {\n";
1588
1589 // Use the smallest type that can hold a regclass ID with room for a
1590 // sentinel.
1591 if (RegisterClasses.size() <= UINT8_MAX)
1592 OS << " static const uint8_t Table[";
1593 else if (RegisterClasses.size() <= UINT16_MAX)
1594 OS << " static const uint16_t Table[";
1595 else
1596 PrintFatalError(Msg: "Too many register classes.");
1597
1598 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1599
1600 for (const auto &RC : RegisterClasses) {
1601 OS << " {\t// " << RC.getName() << '\n';
1602 for (auto &Idx : SubRegIndices) {
1603 std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
1604 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, SubIdx: &Idx);
1605
1606 unsigned EnumValue = 0;
1607 if (MatchingSubClass) {
1608 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second;
1609 EnumValue = SubRegClass->EnumValue + 1;
1610 }
1611
1612 OS << " " << EnumValue << ",\t// " << RC.getName() << ':'
1613 << Idx.getName();
1614
1615 if (MatchingSubClass) {
1616 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second;
1617 OS << " -> " << SubRegClass->getName();
1618 }
1619
1620 OS << '\n';
1621 }
1622
1623 OS << " },\n";
1624 }
1625 OS << " };\n assert(RC && \"Missing regclass\");\n"
1626 << " if (!Idx) return RC;\n --Idx;\n"
1627 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
1628 << " unsigned TV = Table[RC->getID()][Idx];\n"
1629 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1630 }
1631
1632 EmitRegUnitPressure(OS, ClassName);
1633
1634 // Emit register base class mapper
1635 if (!RegisterClasses.empty()) {
1636 // Collect base classes
1637 SmallVector<const CodeGenRegisterClass *> BaseClasses;
1638 for (const auto &RC : RegisterClasses) {
1639 if (RC.getBaseClassOrder())
1640 BaseClasses.push_back(Elt: &RC);
1641 }
1642 if (!BaseClasses.empty()) {
1643 assert(BaseClasses.size() < UINT16_MAX &&
1644 "Too many base register classes");
1645
1646 // Apply order
1647 struct BaseClassOrdering {
1648 bool operator()(const CodeGenRegisterClass *LHS,
1649 const CodeGenRegisterClass *RHS) const {
1650 return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) <
1651 std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue);
1652 }
1653 };
1654 llvm::stable_sort(Range&: BaseClasses, C: BaseClassOrdering());
1655
1656 OS << "\n// Register to base register class mapping\n\n";
1657 OS << "\n";
1658 OS << "const TargetRegisterClass *" << ClassName
1659 << "::getPhysRegBaseClass(MCRegister Reg)"
1660 << " const {\n";
1661 OS << " static const uint16_t InvalidRegClassID = UINT16_MAX;\n\n";
1662 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n";
1663 OS << " InvalidRegClassID, // NoRegister\n";
1664 for (const CodeGenRegister &Reg : Regs) {
1665 const CodeGenRegisterClass *BaseRC = nullptr;
1666 for (const CodeGenRegisterClass *RC : BaseClasses) {
1667 if (RC->contains(&Reg)) {
1668 BaseRC = RC;
1669 break;
1670 }
1671 }
1672
1673 OS << " "
1674 << (BaseRC ? BaseRC->getQualifiedIdName() : "InvalidRegClassID")
1675 << ", // " << Reg.getName() << "\n";
1676 }
1677 OS << " };\n\n"
1678 " assert(Reg < ArrayRef(Mapping).size());\n"
1679 " unsigned RCID = Mapping[Reg.id()];\n"
1680 " if (RCID == InvalidRegClassID)\n"
1681 " return nullptr;\n"
1682 " return RegisterClasses[RCID];\n"
1683 "}\n";
1684 }
1685 }
1686
1687 // Emit the constructor of the class...
1688 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1689 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n";
1690 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n";
1691 OS << "extern const char " << TargetName << "RegStrings[];\n";
1692 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1693 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1694 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1695 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1696
1697 EmitRegMappingTables(OS, Regs, isCtor: true);
1698
1699 OS << ClassName << "::\n"
1700 << ClassName
1701 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n"
1702 " unsigned PC, unsigned HwMode)\n"
1703 << " : TargetRegisterInfo(&" << TargetName << "RegInfoDesc"
1704 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n"
1705 << " SubRegIndexNameTable, SubRegIdxRangeTable, "
1706 "SubRegIndexLaneMaskTable,\n"
1707 << " ";
1708 printMask(OS, Val: RegBank.CoveringLanes);
1709 OS << ", RegClassInfos, VTLists, HwMode) {\n"
1710 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1711 << ", RA, PC,\n " << TargetName
1712 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1713 << " " << TargetName << "RegUnitRoots,\n"
1714 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1715 << " " << TargetName << "RegDiffLists,\n"
1716 << " " << TargetName << "LaneMaskLists,\n"
1717 << " " << TargetName << "RegStrings,\n"
1718 << " " << TargetName << "RegClassStrings,\n"
1719 << " " << TargetName << "SubRegIdxLists,\n"
1720 << " " << SubRegIndicesSize + 1 << ",\n"
1721 << " " << TargetName << "RegEncodingTable);\n\n";
1722
1723 EmitRegMapping(OS, Regs, isCtor: true);
1724
1725 OS << "}\n\n";
1726
1727 // Emit CalleeSavedRegs information.
1728 ArrayRef<const Record *> CSRSets =
1729 Records.getAllDerivedDefinitions(ClassName: "CalleeSavedRegs");
1730 for (const Record *CSRSet : CSRSets) {
1731 const SetTheory::RecVec *Regs = RegBank.getSets().expand(Set: CSRSet);
1732 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1733
1734 // Emit the *_SaveList list of callee-saved registers.
1735 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { ";
1736 for (const Record *Reg : *Regs)
1737 OS << getQualifiedName(R: Reg) << ", ";
1738 OS << "0 };\n";
1739
1740 // Emit the *_RegMask bit mask of call-preserved registers.
1741 BitVector Covered = RegBank.computeCoveredRegisters(Regs: *Regs);
1742
1743 // Check for an optional OtherPreserved set.
1744 // Add those registers to RegMask, but not to SaveList.
1745 if (const DagInit *OPDag =
1746 dyn_cast<DagInit>(Val: CSRSet->getValueInit(FieldName: "OtherPreserved"))) {
1747 SetTheory::RecSet OPSet;
1748 RegBank.getSets().evaluate(Expr: OPDag, Elts&: OPSet, Loc: CSRSet->getLoc());
1749 Covered |= RegBank.computeCoveredRegisters(Regs: OPSet.getArrayRef());
1750 }
1751
1752 // Add all constant physical registers to the preserved mask:
1753 SetTheory::RecSet ConstantSet;
1754 for (const auto &Reg : RegBank.getRegisters()) {
1755 if (Reg.Constant)
1756 ConstantSet.insert(X: Reg.TheDef);
1757 }
1758 Covered |= RegBank.computeCoveredRegisters(Regs: ConstantSet.getArrayRef());
1759
1760 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { ";
1761 printBitVectorAsHex(OS, Bits: Covered, Width: 32);
1762 OS << "};\n";
1763 }
1764 OS << "\n\n";
1765
1766 OS << "ArrayRef<const uint32_t *> " << ClassName
1767 << "::getRegMasks() const {\n";
1768 if (!CSRSets.empty()) {
1769 OS << " static const uint32_t *const Masks[] = {\n";
1770 for (const Record *CSRSet : CSRSets)
1771 OS << " " << CSRSet->getName() << "_RegMask,\n";
1772 OS << " };\n";
1773 OS << " return ArrayRef(Masks);\n";
1774 } else {
1775 OS << " return {};\n";
1776 }
1777 OS << "}\n\n";
1778
1779 const std::list<CodeGenRegisterCategory> &RegCategories =
1780 RegBank.getRegCategories();
1781 OS << "bool " << ClassName << "::\n"
1782 << "isGeneralPurposeRegister(const MachineFunction &MF, "
1783 << "MCRegister PhysReg) const {\n"
1784 << " return\n";
1785 for (const CodeGenRegisterCategory &Category : RegCategories)
1786 if (Category.getName() == "GeneralPurposeRegisters") {
1787 for (const CodeGenRegisterClass *RC : Category.getClasses())
1788 OS << " " << RC->getQualifiedName()
1789 << "RegClass.contains(PhysReg) ||\n";
1790 break;
1791 }
1792 OS << " false;\n";
1793 OS << "}\n\n";
1794
1795 OS << "bool " << ClassName << "::\n"
1796 << "isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)"
1797 << " const {\n"
1798 << " return\n";
1799 for (const CodeGenRegisterCategory &Category : RegCategories)
1800 if (Category.getName() == "GeneralPurposeRegisters") {
1801 for (const CodeGenRegisterClass *RC : Category.getClasses())
1802 OS << " " << RC->getQualifiedName()
1803 << "RegClass.hasSubClassEq(RC) ||\n";
1804 break;
1805 }
1806 OS << " false;\n";
1807 OS << "}\n\n";
1808
1809 OS << "bool " << ClassName << "::\n"
1810 << "isFixedRegister(const MachineFunction &MF, "
1811 << "MCRegister PhysReg) const {\n"
1812 << " return\n";
1813 for (const CodeGenRegisterCategory &Category : RegCategories)
1814 if (Category.getName() == "FixedRegisters") {
1815 for (const CodeGenRegisterClass *RC : Category.getClasses())
1816 OS << " " << RC->getQualifiedName()
1817 << "RegClass.contains(PhysReg) ||\n";
1818 break;
1819 }
1820 OS << " false;\n";
1821 OS << "}\n\n";
1822
1823 OS << "bool " << ClassName << "::\n"
1824 << "isArgumentRegister(const MachineFunction &MF, "
1825 << "MCRegister PhysReg) const {\n"
1826 << " return\n";
1827 for (const CodeGenRegisterCategory &Category : RegCategories)
1828 if (Category.getName() == "ArgumentRegisters") {
1829 for (const CodeGenRegisterClass *RC : Category.getClasses())
1830 OS << " " << RC->getQualifiedName()
1831 << "RegClass.contains(PhysReg) ||\n";
1832 break;
1833 }
1834 OS << " false;\n";
1835 OS << "}\n\n";
1836
1837 OS << "bool " << ClassName << "::\n"
1838 << "isConstantPhysReg(MCRegister PhysReg) const {\n"
1839 << " return\n";
1840 for (const auto &Reg : Regs)
1841 if (Reg.Constant)
1842 OS << " PhysReg == " << getQualifiedName(R: Reg.TheDef) << " ||\n";
1843 OS << " false;\n";
1844 OS << "}\n\n";
1845
1846 OS << "ArrayRef<const char *> " << ClassName
1847 << "::getRegMaskNames() const {\n";
1848 if (!CSRSets.empty()) {
1849 OS << " static const char *Names[] = {\n";
1850 for (const Record *CSRSet : CSRSets)
1851 OS << " " << '"' << CSRSet->getName() << '"' << ",\n";
1852 OS << " };\n";
1853 OS << " return ArrayRef(Names);\n";
1854 } else {
1855 OS << " return {};\n";
1856 }
1857 OS << "}\n\n";
1858
1859 OS << "const " << TargetName << "FrameLowering *\n"
1860 << TargetName
1861 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n"
1862 << " return static_cast<const " << TargetName << "FrameLowering *>(\n"
1863 << " MF.getSubtarget().getFrameLowering());\n"
1864 << "}\n\n";
1865
1866 OS << "} // end namespace llvm\n\n";
1867}
1868
1869TableGenOutputFiles RegisterInfoEmitter::run(StringRef FilenamePrefix) {
1870 TGTimer &Timer = Records.getTimer();
1871 Timer.startTimer(Name: "Print enums");
1872 std::string Main;
1873 raw_string_ostream MainOS(Main);
1874 std::string Enums;
1875 raw_string_ostream EnumsOS(Enums);
1876 runEnums(OS&: EnumsOS, MainOS, FilenamePrefix);
1877
1878 Timer.startTimer(Name: "Print MC registers");
1879 std::string MCDesc;
1880 raw_string_ostream MCDescOS(MCDesc);
1881 runMCDesc(OS&: MCDescOS, MainOS, FilenamePrefix);
1882
1883 Timer.startTimer(Name: "Print header fragment");
1884 std::string Header;
1885 raw_string_ostream HeaderOS(Header);
1886 runTargetHeader(OS&: HeaderOS, MainOS, FilenamePrefix);
1887
1888 Timer.startTimer(Name: "Print target registers");
1889 std::string TargetDesc;
1890 raw_string_ostream TargetDescOS(TargetDesc);
1891 runTargetDesc(OS&: TargetDescOS, MainOS, FilenamePrefix);
1892
1893 if (RegisterInfoDebug)
1894 debugDump(OS&: errs());
1895
1896 // The suffixes should be in sync with the tablegen function in
1897 // llvm/cmake/modules/TableGen.cmake.
1898 return {.MainFile: Main,
1899 .AdditionalFiles: {{"Enums.inc", Enums},
1900 {"MCDesc.inc", MCDesc},
1901 {"Header.inc", Header},
1902 {"TargetDesc.inc", TargetDesc}}};
1903}
1904
1905void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
1906 const CodeGenHwModes &CGH = Target.getHwModes();
1907 unsigned NumModes = CGH.getNumModeIds();
1908 auto getModeName = [CGH](unsigned M) -> StringRef {
1909 if (M == 0)
1910 return "Default";
1911 return CGH.getMode(Id: M).Name;
1912 };
1913
1914 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
1915 OS << "RegisterClass " << RC.getName() << ":\n";
1916 OS << "\tSpillSize: {";
1917 for (unsigned M = 0; M != NumModes; ++M)
1918 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(Mode: M).SpillSize;
1919 OS << " }\n\tSpillAlignment: {";
1920 for (unsigned M = 0; M != NumModes; ++M)
1921 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(Mode: M).SpillAlignment;
1922 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n';
1923 OS << "\tLaneMask: " << PrintLaneMask(LaneMask: RC.LaneMask) << '\n';
1924 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
1925 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
1926 OS << "\tAllocatable: " << RC.Allocatable << '\n';
1927 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n';
1928 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n';
1929 OS << "\tRegs:";
1930 for (const CodeGenRegister *R : RC.getMembers()) {
1931 OS << " " << R->getName();
1932 }
1933 OS << '\n';
1934 OS << "\tSubClasses:";
1935 const BitVector &SubClasses = RC.getSubClasses();
1936 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {
1937 if (!SubClasses.test(Idx: SRC.EnumValue))
1938 continue;
1939 OS << " " << SRC.getName();
1940 }
1941 OS << '\n';
1942 OS << "\tSuperClasses:";
1943 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) {
1944 OS << " " << SRC->getName();
1945 }
1946 OS << '\n';
1947 }
1948
1949 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {
1950 OS << "SubRegIndex " << SRI.getName() << ":\n";
1951 OS << "\tLaneMask: " << PrintLaneMask(LaneMask: SRI.LaneMask) << '\n';
1952 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n';
1953 OS << "\tOffset: {";
1954 for (unsigned M = 0; M != NumModes; ++M)
1955 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(Mode: M).Offset;
1956 OS << " }\n\tSize: {";
1957 for (unsigned M = 0; M != NumModes; ++M)
1958 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(Mode: M).Size;
1959 OS << " }\n";
1960 }
1961
1962 for (const CodeGenRegister &R : RegBank.getRegisters()) {
1963 OS << "Register " << R.getName() << ":\n";
1964 OS << "\tCostPerUse: ";
1965 for (const auto &Cost : R.CostPerUse)
1966 OS << Cost << " ";
1967 OS << '\n';
1968 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n';
1969 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n';
1970 for (auto &[SubIdx, SubReg] : R.getSubRegs()) {
1971 OS << "\tSubReg " << SubIdx->getName() << " = " << SubReg->getName()
1972 << '\n';
1973 }
1974 for (unsigned U : R.getNativeRegUnits())
1975 OS << "\tRegUnit " << U << '\n';
1976 }
1977}
1978
1979static TableGen::Emitter::MultiFileOptClass<RegisterInfoEmitter>
1980 X("gen-register-info", "Generate registers and register classes info");
1981