1//===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend emits subtarget enumerations.
10//
11//===----------------------------------------------------------------------===//
12
13#include "Basic/TargetFeaturesEmitter.h"
14#include "Common/CodeGenHwModes.h"
15#include "Common/CodeGenSchedule.h"
16#include "Common/CodeGenTarget.h"
17#include "Common/PredicateExpander.h"
18#include "Common/SubtargetFeatureInfo.h"
19#include "Common/Utils.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallPtrSet.h"
22#include "llvm/ADT/StringExtras.h"
23#include "llvm/ADT/StringMap.h"
24#include "llvm/ADT/StringRef.h"
25#include "llvm/MC/MCInstrItineraries.h"
26#include "llvm/MC/MCSchedule.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/Format.h"
29#include "llvm/Support/raw_ostream.h"
30#include "llvm/TableGen/CodeGenHelpers.h"
31#include "llvm/TableGen/Error.h"
32#include "llvm/TableGen/Record.h"
33#include "llvm/TableGen/StringToOffsetTable.h"
34#include "llvm/TableGen/TableGenBackend.h"
35#include <algorithm>
36#include <cassert>
37#include <cstdint>
38#include <iterator>
39#include <string>
40#include <vector>
41
42using namespace llvm;
43
44#define DEBUG_TYPE "subtarget-emitter"
45
46namespace {
47
48class SubtargetEmitter : TargetFeaturesEmitter {
49 // Each processor has a SchedClassDesc table with an entry for each
50 // SchedClass. The SchedClassDesc table indexes into a global write resource
51 // table, write latency table, and read advance table.
52 struct SchedClassTables {
53 std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
54 std::vector<MCWriteProcResEntry> WriteProcResources;
55 std::vector<MCWriteLatencyEntry> WriteLatencies;
56 std::vector<std::string> WriterNames;
57 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
58
59 // Reserve an invalid entry at index 0
60 SchedClassTables() {
61 ProcSchedClasses.resize(new_size: 1);
62 WriteProcResources.resize(new_size: 1);
63 WriteLatencies.resize(new_size: 1);
64 WriterNames.push_back(x: "InvalidWrite");
65 ReadAdvanceEntries.resize(new_size: 1);
66 }
67 };
68
69 struct LessWriteProcResources {
70 bool operator()(const MCWriteProcResEntry &LHS,
71 const MCWriteProcResEntry &RHS) {
72 return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
73 }
74 };
75
76 CodeGenTarget TGT;
77 CodeGenSchedModels &SchedModels;
78
79 FeatureMapTy emitEnums(raw_ostream &OS);
80 void emitSubtargetInfoMacroCalls(raw_ostream &OS);
81 std::tuple<unsigned, unsigned, unsigned>
82 emitMCDesc(raw_ostream &OS, const FeatureMapTy &FeatureMap);
83 void emitTargetDesc(raw_ostream &OS);
84 void emitHeader(raw_ostream &OS);
85 void emitCtor(raw_ostream &OS, unsigned NumNames, unsigned NumFeatures,
86 unsigned NumProcs);
87
88 unsigned featureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);
89 unsigned cpuKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);
90 unsigned cpuNames(raw_ostream &OS);
91 void formItineraryStageString(const std::string &Names,
92 const Record *ItinData, std::string &ItinString,
93 unsigned &NStages);
94 void formItineraryOperandCycleString(const Record *ItinData,
95 std::string &ItinString,
96 unsigned &NOperandCycles);
97 void formItineraryBypassString(const std::string &Names,
98 const Record *ItinData,
99 std::string &ItinString,
100 unsigned NOperandCycles);
101 void emitStageAndOperandCycleData(
102 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists);
103 void emitItineraries(raw_ostream &OS,
104 ArrayRef<std::vector<InstrItinerary>> ProcItinLists);
105 unsigned emitRegisterFileTables(const CodeGenProcModel &ProcModel,
106 raw_ostream &OS);
107 void emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
108 raw_ostream &OS);
109 void emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
110 raw_ostream &OS);
111 void emitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
112 char Separator);
113 void emitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
114 raw_ostream &OS);
115 void emitProcessorResources(const CodeGenProcModel &ProcModel,
116 raw_ostream &OS);
117 const Record *findWriteResources(const CodeGenSchedRW &SchedWrite,
118 const CodeGenProcModel &ProcModel);
119 const Record *findReadAdvance(const CodeGenSchedRW &SchedRead,
120 const CodeGenProcModel &ProcModel);
121 void expandProcResources(ConstRecVec &PRVec,
122 std::vector<int64_t> &ReleaseAtCycles,
123 std::vector<int64_t> &AcquireAtCycles,
124 const CodeGenProcModel &ProcModel);
125 void genSchedClassTables(const CodeGenProcModel &ProcModel,
126 SchedClassTables &SchedTables);
127 void emitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
128 void emitProcessorModels(raw_ostream &OS);
129 void emitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
130 void emitSchedModelHelpersImpl(raw_ostream &OS,
131 bool OnlyExpandMCInstPredicates = false);
132 void emitGenMCSubtargetInfo(raw_ostream &OS);
133 void emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS);
134
135 void emitSchedModel(raw_ostream &OS);
136 void emitGetMacroFusions(const std::string &ClassName, raw_ostream &OS);
137 void emitHwModeCheck(const std::string &ClassName, raw_ostream &OS,
138 bool IsMC);
139 void parseFeaturesFunction(raw_ostream &OS);
140
141public:
142 SubtargetEmitter(const RecordKeeper &R)
143 : TargetFeaturesEmitter(R), TGT(R), SchedModels(TGT.getSchedModels()) {}
144
145 void run(raw_ostream &O) override;
146};
147
148} // end anonymous namespace
149
150/// Emit some information about the SubtargetFeature as calls to a macro so
151/// that they can be used from C++.
152void SubtargetEmitter::emitSubtargetInfoMacroCalls(raw_ostream &OS) {
153 // Undef the GET_SUBTARGETINFO_MACRO macro at the end of the scope since it's
154 // used within the scope.
155 IfDefEmitter IfDefMacro(OS, "GET_SUBTARGETINFO_MACRO", /*LateUndef=*/true);
156
157 std::vector<const Record *> FeatureList =
158 Records.getAllDerivedDefinitions(ClassName: "SubtargetFeature");
159 llvm::sort(C&: FeatureList, Comp: LessRecordFieldFieldName());
160
161 for (const Record *Feature : FeatureList) {
162 const StringRef FieldName = Feature->getValueAsString(FieldName: "FieldName");
163 const StringRef Value = Feature->getValueAsString(FieldName: "Value");
164
165 // Only handle boolean features for now, excluding BitVectors and enums.
166 const bool IsBool = (Value == "false" || Value == "true") &&
167 !StringRef(FieldName).contains(C: '[');
168 if (!IsBool)
169 continue;
170
171 // Some features default to true, with values set to false if enabled.
172 const char *Default = Value == "false" ? "true" : "false";
173
174 // Define the getter with lowercased first char: xxxYyy() { return XxxYyy; }
175 const std::string Getter =
176 FieldName.substr(Start: 0, N: 1).lower() + FieldName.substr(Start: 1).str();
177
178 OS << "GET_SUBTARGETINFO_MACRO(" << FieldName << ", " << Default << ", "
179 << Getter << ")\n";
180 }
181}
182
183//
184// FeatureKeyValues - Emit data of all the subtarget features. Used by the
185// command line.
186//
187unsigned SubtargetEmitter::featureKeyValues(raw_ostream &OS,
188 const FeatureMapTy &FeatureMap) {
189 std::vector<const Record *> FeatureList =
190 Records.getAllDerivedDefinitions(ClassName: "SubtargetFeature");
191
192 // Remove features with empty name.
193 llvm::erase_if(C&: FeatureList, P: [](const Record *Rec) {
194 return Rec->getValueAsString(FieldName: "Name").empty();
195 });
196 if (FeatureList.empty())
197 return 0;
198
199 // Sort and check duplicate Feature name.
200 sortAndReportDuplicates(Records: FeatureList, ObjectName: "Feature");
201
202 // Begin feature table.
203 OS << "// Sorted (by key) array of values for CPU features.\n"
204 << "extern const llvm::SubtargetFeatureKV " << Target
205 << "FeatureKV[] = {\n";
206
207 for (const Record *Feature : FeatureList) {
208 // Next feature
209 StringRef Name = Feature->getName();
210 StringRef CommandLineName = Feature->getValueAsString(FieldName: "Name");
211 StringRef Desc = Feature->getValueAsString(FieldName: "Desc");
212
213 // Emit as { "feature", "description", { featureEnum }, { i1 , i2 , ... , in
214 // } }
215 OS << " { "
216 << "\"" << CommandLineName << "\", "
217 << "\"" << Desc << "\", " << Target << "::" << Name << ", ";
218
219 ConstRecVec ImpliesList = Feature->getValueAsListOfDefs(FieldName: "Implies");
220
221 printFeatureMask(OS, FeatureList: ImpliesList, FeatureMap);
222
223 OS << " },\n";
224 }
225
226 // End feature table.
227 OS << "};\n";
228
229 return FeatureList.size();
230}
231
232unsigned SubtargetEmitter::cpuNames(raw_ostream &OS) {
233 // Begin processor name table.
234 OS << "// Sorted array of names of CPU subtypes, including aliases.\n"
235 << "extern const llvm::StringRef " << Target << "Names[] = {\n";
236
237 std::vector<const Record *> ProcessorList =
238 Records.getAllDerivedDefinitions(ClassName: "Processor");
239
240 std::vector<const Record *> ProcessorAliasList =
241 Records.getAllDerivedDefinitionsIfDefined(ClassName: "ProcessorAlias");
242
243 SmallVector<StringRef> Names;
244 Names.reserve(N: ProcessorList.size() + ProcessorAliasList.size());
245
246 for (const Record *Processor : ProcessorList) {
247 StringRef Name = Processor->getValueAsString(FieldName: "Name");
248 Names.push_back(Elt: Name);
249 }
250
251 for (const Record *Rec : ProcessorAliasList) {
252 auto Name = Rec->getValueAsString(FieldName: "Name");
253 Names.push_back(Elt: Name);
254 }
255
256 llvm::sort(C&: Names);
257 llvm::interleave(
258 c: Names, os&: OS, each_fn: [&](StringRef Name) { OS << '"' << Name << '"'; }, separator: ",\n");
259
260 // End processor name table.
261 OS << "};\n";
262
263 return Names.size();
264}
265
266static void checkDuplicateCPUFeatures(StringRef CPUName,
267 ArrayRef<const Record *> Features,
268 ArrayRef<const Record *> TuneFeatures) {
269 // We have made sure each SubtargetFeature Record has a unique name, so we can
270 // simply use pointer sets here.
271 SmallPtrSet<const Record *, 8> FeatureSet, TuneFeatureSet;
272 for (const auto *FeatureRec : Features) {
273 if (!FeatureSet.insert(Ptr: FeatureRec).second)
274 PrintWarning(Msg: "Processor " + CPUName + " contains duplicate feature '" +
275 FeatureRec->getValueAsString(FieldName: "Name") + "'");
276 }
277
278 for (const auto *TuneFeatureRec : TuneFeatures) {
279 if (!TuneFeatureSet.insert(Ptr: TuneFeatureRec).second)
280 PrintWarning(Msg: "Processor " + CPUName +
281 " contains duplicate tune feature '" +
282 TuneFeatureRec->getValueAsString(FieldName: "Name") + "'");
283 if (FeatureSet.contains(Ptr: TuneFeatureRec))
284 PrintWarning(Msg: "Processor " + CPUName + " has '" +
285 TuneFeatureRec->getValueAsString(FieldName: "Name") +
286 "' in both feature and tune feature sets");
287 }
288}
289
290//
291// CPUKeyValues - Emit data of all the subtarget processors. Used by command
292// line.
293//
294unsigned SubtargetEmitter::cpuKeyValues(raw_ostream &OS,
295 const FeatureMapTy &FeatureMap) {
296 // Gather and sort processor information
297 std::vector<const Record *> ProcessorList =
298 Records.getAllDerivedDefinitions(ClassName: "Processor");
299 llvm::sort(C&: ProcessorList, Comp: LessRecordFieldName());
300
301 // Note that unlike `FeatureKeyValues`, here we do not need to check for
302 // duplicate processors, since that is already done when the SubtargetEmitter
303 // constructor calls `getSchedModels` to build a `CodeGenSchedModels` object,
304 // which does the duplicate processor check.
305
306 // Begin processor table.
307 OS << "// Sorted (by key) array of values for CPU subtype.\n"
308 << "extern const llvm::SubtargetSubTypeKV " << Target
309 << "SubTypeKV[] = {\n";
310
311 for (const Record *Processor : ProcessorList) {
312 StringRef Name = Processor->getValueAsString(FieldName: "Name");
313 ConstRecVec FeatureList = Processor->getValueAsListOfDefs(FieldName: "Features");
314 ConstRecVec TuneFeatureList =
315 Processor->getValueAsListOfDefs(FieldName: "TuneFeatures");
316
317 // Warn the user if there are duplicate processor features or tune
318 // features.
319 checkDuplicateCPUFeatures(CPUName: Name, Features: FeatureList, TuneFeatures: TuneFeatureList);
320
321 // Emit as "{ "cpu", "description", 0, { f1 , f2 , ... fn } },".
322 OS << " { "
323 << "\"" << Name << "\", ";
324
325 printFeatureMask(OS, FeatureList, FeatureMap);
326 OS << ", ";
327 printFeatureMask(OS, FeatureList: TuneFeatureList, FeatureMap);
328
329 // Emit the scheduler model pointer.
330 const std::string &ProcModelName =
331 SchedModels.getModelForProc(ProcDef: Processor).ModelName;
332 OS << ", &" << ProcModelName << " },\n";
333 }
334
335 // End processor table.
336 OS << "};\n";
337
338 return ProcessorList.size();
339}
340
341//
342// FormItineraryStageString - Compose a string containing the stage
343// data initialization for the specified itinerary. N is the number
344// of stages.
345//
346void SubtargetEmitter::formItineraryStageString(const std::string &Name,
347 const Record *ItinData,
348 std::string &ItinString,
349 unsigned &NStages) {
350 // Get states list
351 ConstRecVec StageList = ItinData->getValueAsListOfDefs(FieldName: "Stages");
352
353 // For each stage
354 unsigned N = NStages = StageList.size();
355 for (unsigned I = 0; I < N;) {
356 // Next stage
357 const Record *Stage = StageList[I];
358
359 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
360 int Cycles = Stage->getValueAsInt(FieldName: "Cycles");
361 ItinString += " { " + itostr(X: Cycles) + ", ";
362
363 // Get unit list
364 ConstRecVec UnitList = Stage->getValueAsListOfDefs(FieldName: "Units");
365
366 // For each unit
367 for (unsigned J = 0, M = UnitList.size(); J < M;) {
368 // Add name and bitwise or
369 ItinString += Name + "FU::" + UnitList[J]->getName().str();
370 if (++J < M)
371 ItinString += " | ";
372 }
373
374 int TimeInc = Stage->getValueAsInt(FieldName: "TimeInc");
375 ItinString += ", " + itostr(X: TimeInc);
376
377 int Kind = Stage->getValueAsInt(FieldName: "Kind");
378 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(X: Kind);
379
380 // Close off stage
381 ItinString += " }";
382 if (++I < N)
383 ItinString += ", ";
384 }
385}
386
387//
388// FormItineraryOperandCycleString - Compose a string containing the
389// operand cycle initialization for the specified itinerary. N is the
390// number of operands that has cycles specified.
391//
392void SubtargetEmitter::formItineraryOperandCycleString(
393 const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) {
394 // Get operand cycle list
395 std::vector<int64_t> OperandCycleList =
396 ItinData->getValueAsListOfInts(FieldName: "OperandCycles");
397
398 // For each operand cycle
399 NOperandCycles = OperandCycleList.size();
400 ListSeparator LS;
401 for (int OCycle : OperandCycleList) {
402 // Next operand cycle
403 ItinString += LS;
404 ItinString += " " + itostr(X: OCycle);
405 }
406}
407
408void SubtargetEmitter::formItineraryBypassString(const std::string &Name,
409 const Record *ItinData,
410 std::string &ItinString,
411 unsigned NOperandCycles) {
412 ConstRecVec BypassList = ItinData->getValueAsListOfDefs(FieldName: "Bypasses");
413 unsigned N = BypassList.size();
414 unsigned I = 0;
415 ListSeparator LS;
416 for (; I < N; ++I) {
417 ItinString += LS;
418 ItinString += Name + "Bypass::" + BypassList[I]->getName().str();
419 }
420 for (; I < NOperandCycles; ++I) {
421 ItinString += LS;
422 ItinString += " 0";
423 }
424}
425
426//
427// EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
428// cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
429// by CodeGenSchedClass::Index.
430//
431void SubtargetEmitter::emitStageAndOperandCycleData(
432 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
433 // Multiple processor models may share an itinerary record. Emit it once.
434 SmallPtrSet<const Record *, 8> ItinsDefSet;
435
436 // Emit functional units for all the itineraries.
437 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
438 if (!ItinsDefSet.insert(Ptr: ProcModel.ItinsDef).second)
439 continue;
440
441 ConstRecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs(FieldName: "FU");
442 if (FUs.empty())
443 continue;
444
445 StringRef Name = ProcModel.ItinsDef->getName();
446 {
447 OS << "\n// Functional units for \"" << Name << "\"\n";
448 NamespaceEmitter FUNamespace(OS, (Name + Twine("FU")).str());
449
450 for (const auto &[Idx, FU] : enumerate(First&: FUs))
451 OS << " const InstrStage::FuncUnits " << FU->getName() << " = 1ULL << "
452 << Idx << ";\n";
453 }
454
455 ConstRecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs(FieldName: "BP");
456 if (BPs.empty())
457 continue;
458 OS << "\n// Pipeline forwarding paths for itineraries \"" << Name << "\"\n";
459 NamespaceEmitter BypassNamespace(OS, (Name + Twine("Bypass")).str());
460
461 OS << " const unsigned NoBypass = 0;\n";
462 for (const auto &[Idx, BP] : enumerate(First&: BPs))
463 OS << " const unsigned " << BP->getName() << " = 1 << " << Idx << ";\n";
464 }
465
466 // Begin stages table
467 std::string StageTable =
468 "\nextern const llvm::InstrStage " + Target + "Stages[] = {\n";
469 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
470
471 // Begin operand cycle table
472 std::string OperandCycleTable =
473 "extern const unsigned " + Target + "OperandCycles[] = {\n";
474 OperandCycleTable += " 0, // No itinerary\n";
475
476 // Begin pipeline bypass table
477 std::string BypassTable =
478 "extern const unsigned " + Target + "ForwardingPaths[] = {\n";
479 BypassTable += " 0, // No itinerary\n";
480
481 // For each Itinerary across all processors, add a unique entry to the stages,
482 // operand cycles, and pipeline bypass tables. Then add the new Itinerary
483 // object with computed offsets to the ProcItinLists result.
484 unsigned StageCount = 1, OperandCycleCount = 1;
485 StringMap<unsigned> ItinStageMap, ItinOperandMap;
486 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
487 // Add process itinerary to the list.
488 std::vector<InstrItinerary> &ItinList = ProcItinLists.emplace_back();
489
490 // If this processor defines no itineraries, then leave the itinerary list
491 // empty.
492 if (!ProcModel.hasItineraries())
493 continue;
494
495 StringRef Name = ProcModel.ItinsDef->getName();
496
497 ItinList.resize(new_size: SchedModels.numInstrSchedClasses());
498 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
499
500 for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size();
501 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
502
503 // Next itinerary data
504 const Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
505
506 // Get string and stage count
507 std::string ItinStageString;
508 unsigned NStages = 0;
509 if (ItinData)
510 formItineraryStageString(Name: Name.str(), ItinData, ItinString&: ItinStageString,
511 NStages);
512
513 // Get string and operand cycle count
514 std::string ItinOperandCycleString;
515 unsigned NOperandCycles = 0;
516 std::string ItinBypassString;
517 if (ItinData) {
518 formItineraryOperandCycleString(ItinData, ItinString&: ItinOperandCycleString,
519 NOperandCycles);
520
521 formItineraryBypassString(Name: Name.str(), ItinData, ItinString&: ItinBypassString,
522 NOperandCycles);
523 }
524
525 // Check to see if stage already exists and create if it doesn't
526 uint16_t FindStage = 0;
527 if (NStages > 0) {
528 FindStage = ItinStageMap[ItinStageString];
529 if (FindStage == 0) {
530 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
531 StageTable += ItinStageString + ", // " + itostr(X: StageCount);
532 if (NStages > 1)
533 StageTable += "-" + itostr(X: StageCount + NStages - 1);
534 StageTable += "\n";
535 // Record Itin class number.
536 ItinStageMap[ItinStageString] = FindStage = StageCount;
537 StageCount += NStages;
538 }
539 }
540
541 // Check to see if operand cycle already exists and create if it doesn't
542 uint16_t FindOperandCycle = 0;
543 if (NOperandCycles > 0) {
544 std::string ItinOperandString =
545 ItinOperandCycleString + ItinBypassString;
546 FindOperandCycle = ItinOperandMap[ItinOperandString];
547 if (FindOperandCycle == 0) {
548 // Emit as cycle, // index
549 OperandCycleTable += ItinOperandCycleString + ", // ";
550 std::string OperandIdxComment = itostr(X: OperandCycleCount);
551 if (NOperandCycles > 1)
552 OperandIdxComment +=
553 "-" + itostr(X: OperandCycleCount + NOperandCycles - 1);
554 OperandCycleTable += OperandIdxComment + "\n";
555 // Record Itin class number.
556 ItinOperandMap[ItinOperandCycleString] = FindOperandCycle =
557 OperandCycleCount;
558 // Emit as bypass, // index
559 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
560 OperandCycleCount += NOperandCycles;
561 }
562 }
563
564 // Set up itinerary as location and location + stage count
565 int16_t NumUOps = ItinData ? ItinData->getValueAsInt(FieldName: "NumMicroOps") : 0;
566 InstrItinerary Intinerary = {
567 .NumMicroOps: NumUOps,
568 .FirstStage: FindStage,
569 .LastStage: uint16_t(FindStage + NStages),
570 .FirstOperandCycle: FindOperandCycle,
571 .LastOperandCycle: uint16_t(FindOperandCycle + NOperandCycles),
572 };
573
574 // Inject - empty slots will be 0, 0
575 ItinList[SchedClassIdx] = Intinerary;
576 }
577 }
578
579 // Closing stage
580 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
581 StageTable += "};\n";
582
583 // Closing operand cycles
584 OperandCycleTable += " 0 // End operand cycles\n";
585 OperandCycleTable += "};\n";
586
587 BypassTable += " 0 // End bypass tables\n";
588 BypassTable += "};\n";
589
590 // Emit tables.
591 OS << StageTable;
592 OS << OperandCycleTable;
593 OS << BypassTable;
594}
595
596//
597// EmitProcessorData - Generate data for processor itineraries that were
598// computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
599// Itineraries for each processor. The Itinerary lists are indexed on
600// CodeGenSchedClass::Index.
601//
602void SubtargetEmitter::emitItineraries(
603 raw_ostream &OS, ArrayRef<std::vector<InstrItinerary>> ProcItinLists) {
604 // Multiple processor models may share an itinerary record. Emit it once.
605 SmallPtrSet<const Record *, 8> ItinsDefSet;
606
607 for (const auto &[Proc, ItinList] :
608 zip_equal(t: SchedModels.procModels(), u&: ProcItinLists)) {
609 const Record *ItinsDef = Proc.ItinsDef;
610 if (!ItinsDefSet.insert(Ptr: ItinsDef).second)
611 continue;
612
613 // Empty itineraries aren't referenced anywhere in the tablegen output
614 // so don't emit them.
615 if (ItinList.empty())
616 continue;
617
618 // Begin processor itinerary table
619 OS << "\n";
620 OS << "static constexpr llvm::InstrItinerary " << ItinsDef->getName()
621 << "[] = {\n";
622
623 ArrayRef<CodeGenSchedClass> ItinSchedClasses =
624 SchedModels.schedClasses().take_front(N: ItinList.size());
625
626 // For each itinerary class in CodeGenSchedClass::Index order.
627 for (const auto &[Idx, Intinerary, SchedClass] :
628 enumerate(First: ItinList, Rest&: ItinSchedClasses)) {
629 // Emit Itinerary in the form of
630 // { NumMicroOps, FirstStage, LastStage, FirstOperandCycle,
631 // LastOperandCycle } // index class name
632 OS << " { " << Intinerary.NumMicroOps << ", " << Intinerary.FirstStage
633 << ", " << Intinerary.LastStage << ", " << Intinerary.FirstOperandCycle
634 << ", " << Intinerary.LastOperandCycle << " }" << ", // " << Idx << " "
635 << SchedClass.Name << "\n";
636 }
637 // End processor itinerary table
638 OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
639 "// end marker\n";
640 OS << "};\n";
641 }
642}
643
644// Emit either the value defined in the TableGen Record, or the default
645// value defined in the C++ header. The Record is null if the processor does not
646// define a model.
647void SubtargetEmitter::emitProcessorProp(raw_ostream &OS, const Record *R,
648 StringRef Name, char Separator) {
649 OS << " ";
650 int V = R ? R->getValueAsInt(FieldName: Name) : -1;
651 if (V >= 0)
652 OS << V << Separator << " // " << Name;
653 else
654 OS << "MCSchedModel::Default" << Name << Separator;
655 OS << '\n';
656}
657
658void SubtargetEmitter::emitProcessorResourceSubUnits(
659 const CodeGenProcModel &ProcModel, raw_ostream &OS) {
660 OS << "\nstatic const unsigned " << ProcModel.ModelName
661 << "ProcResourceSubUnits[] = {\n"
662 << " 0, // Invalid\n";
663
664 for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {
665 const Record *PRDef = ProcModel.ProcResourceDefs[I];
666 if (!PRDef->isSubClassOf(Name: "ProcResGroup"))
667 continue;
668 for (const Record *RUDef : PRDef->getValueAsListOfDefs(FieldName: "Resources")) {
669 const Record *RU =
670 SchedModels.findProcResUnits(ProcResKind: RUDef, PM: ProcModel, Loc: PRDef->getLoc());
671 for (unsigned J = 0; J < RU->getValueAsInt(FieldName: "NumUnits"); ++J) {
672 OS << " " << ProcModel.getProcResourceIdx(PRDef: RU) << ", ";
673 }
674 }
675 OS << " // " << PRDef->getName() << "\n";
676 }
677 OS << "};\n";
678}
679
680static void emitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
681 raw_ostream &OS) {
682 int64_t ReorderBufferSize = 0, MaxRetirePerCycle = 0;
683 if (const Record *RCU = ProcModel.RetireControlUnit) {
684 ReorderBufferSize =
685 std::max(a: ReorderBufferSize, b: RCU->getValueAsInt(FieldName: "ReorderBufferSize"));
686 MaxRetirePerCycle =
687 std::max(a: MaxRetirePerCycle, b: RCU->getValueAsInt(FieldName: "MaxRetirePerCycle"));
688 }
689
690 OS << ReorderBufferSize << ", // ReorderBufferSize\n ";
691 OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n ";
692}
693
694static void emitRegisterFileInfo(const CodeGenProcModel &ProcModel,
695 unsigned NumRegisterFiles,
696 unsigned NumCostEntries, raw_ostream &OS) {
697 if (NumRegisterFiles)
698 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles);
699 else
700 OS << "nullptr,\n 0";
701
702 OS << ", // Number of register files.\n ";
703 if (NumCostEntries)
704 OS << ProcModel.ModelName << "RegisterCosts,\n ";
705 else
706 OS << "nullptr,\n ";
707 OS << NumCostEntries << ", // Number of register cost entries.\n";
708}
709
710unsigned
711SubtargetEmitter::emitRegisterFileTables(const CodeGenProcModel &ProcModel,
712 raw_ostream &OS) {
713 if (llvm::all_of(Range: ProcModel.RegisterFiles, P: [](const CodeGenRegisterFile &RF) {
714 return RF.hasDefaultCosts();
715 }))
716 return 0;
717
718 // Print the RegisterCost table first.
719 OS << "\n// {RegisterClassID, Register Cost, AllowMoveElimination }\n";
720 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
721 << "RegisterCosts"
722 << "[] = {\n";
723
724 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {
725 // Skip register files with a default cost table.
726 if (RF.hasDefaultCosts())
727 continue;
728 // Add entries to the cost table.
729 for (const CodeGenRegisterCost &RC : RF.Costs) {
730 OS << " { ";
731 const Record *Rec = RC.RCDef;
732 if (Rec->getValue(Name: "Namespace"))
733 OS << Rec->getValueAsString(FieldName: "Namespace") << "::";
734 OS << Rec->getName() << "RegClassID, " << RC.Cost << ", "
735 << RC.AllowMoveElimination << "},\n";
736 }
737 }
738 OS << "};\n";
739
740 // Now generate a table with register file info.
741 OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl, "
742 << "MaxMovesEliminatedPerCycle, AllowZeroMoveEliminationOnly }\n";
743 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
744 << "RegisterFiles"
745 << "[] = {\n"
746 << " { \"InvalidRegisterFile\", 0, 0, 0, 0, 0 },\n";
747 unsigned CostTblIndex = 0;
748
749 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
750 OS << " { ";
751 OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", ";
752 unsigned NumCostEntries = RD.Costs.size();
753 OS << NumCostEntries << ", " << CostTblIndex << ", "
754 << RD.MaxMovesEliminatedPerCycle << ", "
755 << RD.AllowZeroMoveEliminationOnly << "},\n";
756 CostTblIndex += NumCostEntries;
757 }
758 OS << "};\n";
759
760 return CostTblIndex;
761}
762
763void SubtargetEmitter::emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
764 raw_ostream &OS) {
765 unsigned QueueID = 0;
766 if (ProcModel.LoadQueue) {
767 const Record *Queue = ProcModel.LoadQueue->getValueAsDef(FieldName: "QueueDescriptor");
768 QueueID = 1 + std::distance(first: ProcModel.ProcResourceDefs.begin(),
769 last: find(Range: ProcModel.ProcResourceDefs, Val: Queue));
770 }
771 OS << " " << QueueID << ", // Resource Descriptor for the Load Queue\n";
772
773 QueueID = 0;
774 if (ProcModel.StoreQueue) {
775 const Record *Queue =
776 ProcModel.StoreQueue->getValueAsDef(FieldName: "QueueDescriptor");
777 QueueID = 1 + std::distance(first: ProcModel.ProcResourceDefs.begin(),
778 last: find(Range: ProcModel.ProcResourceDefs, Val: Queue));
779 }
780 OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n";
781}
782
783void SubtargetEmitter::emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
784 raw_ostream &OS) {
785 // Generate a table of register file descriptors (one entry per each user
786 // defined register file), and a table of register costs.
787 unsigned NumCostEntries = emitRegisterFileTables(ProcModel, OS);
788
789 // Now generate a table for the extra processor info.
790 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
791 << "ExtraInfo = {\n ";
792
793 // Add information related to the retire control unit.
794 emitRetireControlUnitInfo(ProcModel, OS);
795
796 // Add information related to the register files (i.e. where to find register
797 // file descriptors and register costs).
798 emitRegisterFileInfo(ProcModel, NumRegisterFiles: ProcModel.RegisterFiles.size(),
799 NumCostEntries, OS);
800
801 // Add information about load/store queues.
802 emitLoadStoreQueueInfo(ProcModel, OS);
803
804 OS << "};\n";
805}
806
807void SubtargetEmitter::emitProcessorResources(const CodeGenProcModel &ProcModel,
808 raw_ostream &OS) {
809 emitProcessorResourceSubUnits(ProcModel, OS);
810
811 OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n";
812 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
813 << "ProcResources"
814 << "[] = {\n"
815 << " {\"InvalidUnit\", 0, 0, 0, 0},\n";
816
817 unsigned SubUnitsOffset = 1;
818 for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {
819 const Record *PRDef = ProcModel.ProcResourceDefs[I];
820
821 const Record *SuperDef = nullptr;
822 unsigned SuperIdx = 0;
823 unsigned NumUnits = 0;
824 const unsigned SubUnitsBeginOffset = SubUnitsOffset;
825 int BufferSize = PRDef->getValueAsInt(FieldName: "BufferSize");
826 if (PRDef->isSubClassOf(Name: "ProcResGroup")) {
827 for (const Record *RU : PRDef->getValueAsListOfDefs(FieldName: "Resources")) {
828 NumUnits += RU->getValueAsInt(FieldName: "NumUnits");
829 SubUnitsOffset += RU->getValueAsInt(FieldName: "NumUnits");
830 }
831 } else {
832 // Find the SuperIdx
833 if (PRDef->getValueInit(FieldName: "Super")->isComplete()) {
834 SuperDef = SchedModels.findProcResUnits(ProcResKind: PRDef->getValueAsDef(FieldName: "Super"),
835 PM: ProcModel, Loc: PRDef->getLoc());
836 SuperIdx = ProcModel.getProcResourceIdx(PRDef: SuperDef);
837 }
838 NumUnits = PRDef->getValueAsInt(FieldName: "NumUnits");
839 }
840 // Emit the ProcResourceDesc
841 OS << " {\"" << PRDef->getName() << "\", ";
842 if (PRDef->getName().size() < 15)
843 OS.indent(NumSpaces: 15 - PRDef->getName().size());
844 OS << NumUnits << ", " << SuperIdx << ", " << BufferSize << ", ";
845 if (SubUnitsBeginOffset != SubUnitsOffset) {
846 OS << ProcModel.ModelName << "ProcResourceSubUnits + "
847 << SubUnitsBeginOffset;
848 } else {
849 OS << "nullptr";
850 }
851 OS << "}, // #" << I + 1;
852 if (SuperDef)
853 OS << ", Super=" << SuperDef->getName();
854 OS << "\n";
855 }
856 OS << "};\n";
857}
858
859// Find the WriteRes Record that defines processor resources for this
860// SchedWrite.
861const Record *
862SubtargetEmitter::findWriteResources(const CodeGenSchedRW &SchedWrite,
863 const CodeGenProcModel &ProcModel) {
864
865 // Check if the SchedWrite is already subtarget-specific and directly
866 // specifies a set of processor resources.
867 if (SchedWrite.TheDef->isSubClassOf(Name: "SchedWriteRes"))
868 return SchedWrite.TheDef;
869
870 const Record *AliasDef = nullptr;
871 for (const Record *A : SchedWrite.Aliases) {
872 const CodeGenSchedRW &AliasRW =
873 SchedModels.getSchedRW(Def: A->getValueAsDef(FieldName: "AliasRW"));
874 if (AliasRW.TheDef->getValueInit(FieldName: "SchedModel")->isComplete()) {
875 const Record *ModelDef = AliasRW.TheDef->getValueAsDef(FieldName: "SchedModel");
876 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
877 continue;
878 }
879 if (AliasDef)
880 PrintFatalError(ErrorLoc: AliasRW.TheDef->getLoc(),
881 Msg: "Multiple aliases "
882 "defined for processor " +
883 ProcModel.ModelName +
884 " Ensure only one SchedAlias exists per RW.");
885 AliasDef = AliasRW.TheDef;
886 }
887 if (AliasDef && AliasDef->isSubClassOf(Name: "SchedWriteRes"))
888 return AliasDef;
889
890 // Check this processor's list of write resources.
891 const Record *ResDef = nullptr;
892
893 auto I = ProcModel.WriteResMap.find(Val: SchedWrite.TheDef);
894 if (I != ProcModel.WriteResMap.end())
895 ResDef = I->second;
896
897 if (AliasDef) {
898 I = ProcModel.WriteResMap.find(Val: AliasDef);
899 if (I != ProcModel.WriteResMap.end()) {
900 if (ResDef)
901 PrintFatalError(ErrorLoc: I->second->getLoc(),
902 Msg: "Resources are defined for both SchedWrite and its "
903 "alias on processor " +
904 ProcModel.ModelName);
905 ResDef = I->second;
906 }
907 }
908
909 // TODO: If ProcModel has a base model (previous generation processor),
910 // then call FindWriteResources recursively with that model here.
911 if (!ResDef) {
912 PrintFatalError(ErrorLoc: ProcModel.ModelDef->getLoc(),
913 Msg: Twine("Processor does not define resources for ") +
914 SchedWrite.TheDef->getName());
915 }
916 return ResDef;
917}
918
919/// Find the ReadAdvance record for the given SchedRead on this processor or
920/// return NULL.
921const Record *
922SubtargetEmitter::findReadAdvance(const CodeGenSchedRW &SchedRead,
923 const CodeGenProcModel &ProcModel) {
924 // Check for SchedReads that directly specify a ReadAdvance.
925 if (SchedRead.TheDef->isSubClassOf(Name: "SchedReadAdvance"))
926 return SchedRead.TheDef;
927
928 // Check this processor's list of aliases for SchedRead.
929 const Record *AliasDef = nullptr;
930 for (const Record *A : SchedRead.Aliases) {
931 const CodeGenSchedRW &AliasRW =
932 SchedModels.getSchedRW(Def: A->getValueAsDef(FieldName: "AliasRW"));
933 if (AliasRW.TheDef->getValueInit(FieldName: "SchedModel")->isComplete()) {
934 const Record *ModelDef = AliasRW.TheDef->getValueAsDef(FieldName: "SchedModel");
935 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
936 continue;
937 }
938 if (AliasDef)
939 PrintFatalError(ErrorLoc: AliasRW.TheDef->getLoc(),
940 Msg: "Multiple aliases "
941 "defined for processor " +
942 ProcModel.ModelName +
943 " Ensure only one SchedAlias exists per RW.");
944 AliasDef = AliasRW.TheDef;
945 }
946 if (AliasDef && AliasDef->isSubClassOf(Name: "SchedReadAdvance"))
947 return AliasDef;
948
949 // Check this processor's ReadAdvanceList.
950 const Record *ResDef = nullptr;
951
952 auto I = ProcModel.ReadAdvanceMap.find(Val: SchedRead.TheDef);
953 if (I != ProcModel.ReadAdvanceMap.end())
954 ResDef = I->second;
955
956 if (AliasDef) {
957 I = ProcModel.ReadAdvanceMap.find(Val: AliasDef);
958 if (I != ProcModel.ReadAdvanceMap.end()) {
959 if (ResDef)
960 PrintFatalError(
961 ErrorLoc: I->second->getLoc(),
962 Msg: "Resources are defined for both SchedRead and its alias on "
963 "processor " +
964 ProcModel.ModelName);
965 ResDef = I->second;
966 }
967 }
968
969 // TODO: If ProcModel has a base model (previous generation processor),
970 // then call FindReadAdvance recursively with that model here.
971 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
972 PrintFatalError(ErrorLoc: ProcModel.ModelDef->getLoc(),
973 Msg: Twine("Processor does not define resources for ") +
974 SchedRead.TheDef->getName());
975 }
976 return ResDef;
977}
978
979// Expand an explicit list of processor resources into a full list of implied
980// resource groups and super resources that cover them.
981void SubtargetEmitter::expandProcResources(
982 ConstRecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
983 std::vector<int64_t> &AcquireAtCycles, const CodeGenProcModel &PM) {
984 assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition");
985 for (unsigned I = 0, E = PRVec.size(); I != E; ++I) {
986 const Record *PRDef = PRVec[I];
987 ConstRecVec SubResources;
988 if (PRDef->isSubClassOf(Name: "ProcResGroup")) {
989 SubResources = PRDef->getValueAsListOfDefs(FieldName: "Resources");
990 } else {
991 SubResources.push_back(x: PRDef);
992 PRDef = SchedModels.findProcResUnits(ProcResKind: PRDef, PM, Loc: PRDef->getLoc());
993 for (const Record *SubDef = PRDef;
994 SubDef->getValueInit(FieldName: "Super")->isComplete();) {
995 if (SubDef->isSubClassOf(Name: "ProcResGroup")) {
996 // Disallow this for simplicitly.
997 PrintFatalError(ErrorLoc: SubDef->getLoc(), Msg: "Processor resource group "
998 " cannot be a super resources.");
999 }
1000 const Record *SuperDef = SchedModels.findProcResUnits(
1001 ProcResKind: SubDef->getValueAsDef(FieldName: "Super"), PM, Loc: SubDef->getLoc());
1002 PRVec.push_back(x: SuperDef);
1003 ReleaseAtCycles.push_back(x: ReleaseAtCycles[I]);
1004 AcquireAtCycles.push_back(x: AcquireAtCycles[I]);
1005 SubDef = SuperDef;
1006 }
1007 }
1008 for (const Record *PR : PM.ProcResourceDefs) {
1009 if (PR == PRDef || !PR->isSubClassOf(Name: "ProcResGroup"))
1010 continue;
1011 ConstRecVec SuperResources = PR->getValueAsListOfDefs(FieldName: "Resources");
1012 bool AllContained =
1013 all_of(Range&: SubResources, P: [SuperResources](const Record *SubResource) {
1014 return is_contained(Range: SuperResources, Element: SubResource);
1015 });
1016 if (AllContained) {
1017 PRVec.push_back(x: PR);
1018 ReleaseAtCycles.push_back(x: ReleaseAtCycles[I]);
1019 AcquireAtCycles.push_back(x: AcquireAtCycles[I]);
1020 }
1021 }
1022 }
1023}
1024
1025// Generate the SchedClass table for this processor and update global
1026// tables. Must be called for each processor in order.
1027void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel,
1028 SchedClassTables &SchedTables) {
1029 std::vector<MCSchedClassDesc> &SCTab =
1030 SchedTables.ProcSchedClasses.emplace_back();
1031 if (!ProcModel.hasInstrSchedModel())
1032 return;
1033
1034 LLVM_DEBUG(dbgs() << "\n+++ SCHED CLASSES (GenSchedClassTables) +++\n");
1035 for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
1036 LLVM_DEBUG(SC.dump(&SchedModels));
1037
1038 MCSchedClassDesc &SCDesc = SCTab.emplace_back();
1039 // SCDesc.Name is guarded by NDEBUG
1040 SCDesc.NumMicroOps = 0;
1041 SCDesc.BeginGroup = false;
1042 SCDesc.EndGroup = false;
1043 SCDesc.RetireOOO = false;
1044 SCDesc.WriteProcResIdx = 0;
1045 SCDesc.WriteLatencyIdx = 0;
1046 SCDesc.ReadAdvanceIdx = 0;
1047
1048 // A Variant SchedClass has no resources of its own.
1049 bool HasVariants = false;
1050 for (const CodeGenSchedTransition &CGT : SC.Transitions) {
1051 if (CGT.ProcIndex == ProcModel.Index) {
1052 HasVariants = true;
1053 break;
1054 }
1055 }
1056 if (HasVariants) {
1057 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
1058 continue;
1059 }
1060
1061 // Determine if the SchedClass is actually reachable on this processor. If
1062 // not don't try to locate the processor resources, it will fail.
1063 // If ProcIndices contains 0, this class applies to all processors.
1064 assert(!SC.ProcIndices.empty() && "expect at least one procidx");
1065 if (SC.ProcIndices[0] != 0) {
1066 if (!is_contained(Range: SC.ProcIndices, Element: ProcModel.Index))
1067 continue;
1068 }
1069 IdxVec Writes = SC.Writes;
1070 IdxVec Reads = SC.Reads;
1071 if (!SC.InstRWs.empty()) {
1072 // This class has a default ReadWrite list which can be overridden by
1073 // InstRW definitions.
1074 const Record *RWDef = nullptr;
1075 for (const Record *RW : SC.InstRWs) {
1076 const Record *RWModelDef = RW->getValueAsDef(FieldName: "SchedModel");
1077 if (&ProcModel == &SchedModels.getProcModel(ModelDef: RWModelDef)) {
1078 RWDef = RW;
1079 break;
1080 }
1081 }
1082 if (RWDef) {
1083 Writes.clear();
1084 Reads.clear();
1085 SchedModels.findRWs(RWDefs: RWDef->getValueAsListOfDefs(FieldName: "OperandReadWrites"),
1086 Writes, Reads);
1087 }
1088 }
1089 if (Writes.empty()) {
1090 // Check this processor's itinerary class resources.
1091 for (const Record *I : ProcModel.ItinRWDefs) {
1092 ConstRecVec Matched = I->getValueAsListOfDefs(FieldName: "MatchedItinClasses");
1093 if (is_contained(Range&: Matched, Element: SC.ItinClassDef)) {
1094 SchedModels.findRWs(RWDefs: I->getValueAsListOfDefs(FieldName: "OperandReadWrites"),
1095 Writes, Reads);
1096 break;
1097 }
1098 }
1099 if (Writes.empty()) {
1100 LLVM_DEBUG(dbgs() << ProcModel.ModelName
1101 << " does not have resources for class " << SC.Name
1102 << '\n');
1103 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1104 }
1105 }
1106 // Sum resources across all operand writes.
1107 std::vector<MCWriteProcResEntry> WriteProcResources;
1108 std::vector<MCWriteLatencyEntry> WriteLatencies;
1109 std::vector<std::string> WriterNames;
1110 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
1111 for (unsigned W : Writes) {
1112 IdxVec WriteSeq;
1113 SchedModels.expandRWSeqForProc(RWIdx: W, RWSeq&: WriteSeq, /*IsRead=*/false, ProcModel);
1114
1115 // For each operand, create a latency entry.
1116 MCWriteLatencyEntry WLEntry;
1117 WLEntry.Cycles = 0;
1118 unsigned WriteID = WriteSeq.back();
1119 WriterNames.push_back(x: SchedModels.getSchedWrite(Idx: WriteID).Name);
1120 // If this Write is not referenced by a ReadAdvance, don't distinguish it
1121 // from other WriteLatency entries.
1122 if (!ProcModel.hasReadOfWrite(WriteDef: SchedModels.getSchedWrite(Idx: WriteID).TheDef))
1123 WriteID = 0;
1124 WLEntry.WriteResourceID = WriteID;
1125
1126 for (unsigned WS : WriteSeq) {
1127 const Record *WriteRes =
1128 findWriteResources(SchedWrite: SchedModels.getSchedWrite(Idx: WS), ProcModel);
1129
1130 // Mark the parent class as invalid for unsupported write types.
1131 if (WriteRes->getValueAsBit(FieldName: "Unsupported")) {
1132 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1133 break;
1134 }
1135 WLEntry.Cycles += WriteRes->getValueAsInt(FieldName: "Latency");
1136 SCDesc.NumMicroOps += WriteRes->getValueAsInt(FieldName: "NumMicroOps");
1137 SCDesc.BeginGroup |= WriteRes->getValueAsBit(FieldName: "BeginGroup");
1138 SCDesc.EndGroup |= WriteRes->getValueAsBit(FieldName: "EndGroup");
1139 SCDesc.BeginGroup |= WriteRes->getValueAsBit(FieldName: "SingleIssue");
1140 SCDesc.EndGroup |= WriteRes->getValueAsBit(FieldName: "SingleIssue");
1141 SCDesc.RetireOOO |= WriteRes->getValueAsBit(FieldName: "RetireOOO");
1142
1143 // Create an entry for each ProcResource listed in WriteRes.
1144 ConstRecVec PRVec = WriteRes->getValueAsListOfDefs(FieldName: "ProcResources");
1145 std::vector<int64_t> ReleaseAtCycles =
1146 WriteRes->getValueAsListOfInts(FieldName: "ReleaseAtCycles");
1147
1148 std::vector<int64_t> AcquireAtCycles =
1149 WriteRes->getValueAsListOfInts(FieldName: "AcquireAtCycles");
1150
1151 // Check consistency of the two vectors carrying the start and
1152 // stop cycles of the resources.
1153 if (!ReleaseAtCycles.empty() &&
1154 ReleaseAtCycles.size() != PRVec.size()) {
1155 // If ReleaseAtCycles is provided, check consistency.
1156 PrintFatalError(
1157 ErrorLoc: WriteRes->getLoc(),
1158 Msg: Twine("Inconsistent release at cycles: size(ReleaseAtCycles) != "
1159 "size(ProcResources): ")
1160 .concat(Suffix: Twine(PRVec.size()))
1161 .concat(Suffix: " vs ")
1162 .concat(Suffix: Twine(ReleaseAtCycles.size())));
1163 }
1164
1165 if (!AcquireAtCycles.empty() &&
1166 AcquireAtCycles.size() != PRVec.size()) {
1167 PrintFatalError(
1168 ErrorLoc: WriteRes->getLoc(),
1169 Msg: Twine("Inconsistent resource cycles: size(AcquireAtCycles) != "
1170 "size(ProcResources): ")
1171 .concat(Suffix: Twine(AcquireAtCycles.size()))
1172 .concat(Suffix: " vs ")
1173 .concat(Suffix: Twine(PRVec.size())));
1174 }
1175
1176 if (ReleaseAtCycles.empty()) {
1177 // If ReleaseAtCycles is not provided, default to one cycle
1178 // per resource.
1179 ReleaseAtCycles.resize(new_size: PRVec.size(), x: 1);
1180 }
1181
1182 if (AcquireAtCycles.empty()) {
1183 // If AcquireAtCycles is not provided, reserve the resource
1184 // starting from cycle 0.
1185 AcquireAtCycles.resize(new_size: PRVec.size(), x: 0);
1186 }
1187
1188 assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
1189
1190 expandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, PM: ProcModel);
1191 assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
1192
1193 for (unsigned PRIdx = 0, PREnd = PRVec.size(); PRIdx != PREnd;
1194 ++PRIdx) {
1195 MCWriteProcResEntry WPREntry;
1196 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRDef: PRVec[PRIdx]);
1197 assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
1198 WPREntry.ReleaseAtCycle = ReleaseAtCycles[PRIdx];
1199 WPREntry.AcquireAtCycle = AcquireAtCycles[PRIdx];
1200 if (AcquireAtCycles[PRIdx] > ReleaseAtCycles[PRIdx]) {
1201 PrintFatalError(
1202 ErrorLoc: WriteRes->getLoc(),
1203 Msg: Twine("Inconsistent resource cycles: AcquireAtCycles "
1204 "<= ReleaseAtCycles must hold."));
1205 }
1206 if (AcquireAtCycles[PRIdx] < 0) {
1207 PrintFatalError(ErrorLoc: WriteRes->getLoc(),
1208 Msg: Twine("Invalid value: AcquireAtCycle "
1209 "must be a non-negative value."));
1210 }
1211 // If this resource is already used in this sequence, add the current
1212 // entry's cycles so that the same resource appears to be used
1213 // serially, rather than multiple parallel uses. This is important for
1214 // in-order machine where the resource consumption is a hazard.
1215 unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();
1216 for (; WPRIdx != WPREnd; ++WPRIdx) {
1217 if (WriteProcResources[WPRIdx].ProcResourceIdx ==
1218 WPREntry.ProcResourceIdx) {
1219 // TODO: multiple use of the same resources would
1220 // require either 1. thinking of how to handle multiple
1221 // intervals for the same resource in
1222 // `<Target>WriteProcResTable` (see
1223 // `SubtargetEmitter::EmitSchedClassTables`), or
1224 // 2. thinking how to merge multiple intervals into a
1225 // single interval.
1226 assert(WPREntry.AcquireAtCycle == 0 &&
1227 "multiple use ofthe same resource is not yet handled");
1228 WriteProcResources[WPRIdx].ReleaseAtCycle +=
1229 WPREntry.ReleaseAtCycle;
1230 break;
1231 }
1232 }
1233 if (WPRIdx == WPREnd)
1234 WriteProcResources.push_back(x: WPREntry);
1235 }
1236 }
1237 WriteLatencies.push_back(x: WLEntry);
1238 }
1239 // Create an entry for each operand Read in this SchedClass.
1240 // Entries must be sorted first by UseIdx then by WriteResourceID.
1241 for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx;
1242 ++UseIdx) {
1243 const Record *ReadAdvance =
1244 findReadAdvance(SchedRead: SchedModels.getSchedRead(Idx: Reads[UseIdx]), ProcModel);
1245 if (!ReadAdvance)
1246 continue;
1247
1248 // Mark the parent class as invalid for unsupported write types.
1249 if (ReadAdvance->getValueAsBit(FieldName: "Unsupported")) {
1250 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1251 break;
1252 }
1253 ConstRecVec ValidWrites =
1254 ReadAdvance->getValueAsListOfDefs(FieldName: "ValidWrites");
1255 std::vector<int64_t> CycleTunables =
1256 ReadAdvance->getValueAsListOfInts(FieldName: "CycleTunables");
1257 std::vector<std::pair<unsigned, int>> WriteIDs;
1258 assert(CycleTunables.size() <= ValidWrites.size() && "Bad ReadAdvance");
1259 CycleTunables.resize(new_size: ValidWrites.size(), x: 0);
1260 if (ValidWrites.empty())
1261 WriteIDs.emplace_back(args: 0, args: 0);
1262 else {
1263 for (const auto [VW, CT] : zip_equal(t&: ValidWrites, u&: CycleTunables)) {
1264 unsigned WriteID = SchedModels.getSchedRWIdx(Def: VW, /*IsRead=*/false);
1265 assert(WriteID != 0 &&
1266 "Expected a valid SchedRW in the list of ValidWrites");
1267 WriteIDs.emplace_back(args&: WriteID, args&: CT);
1268 }
1269 }
1270 llvm::sort(C&: WriteIDs);
1271 for (const auto &[W, T] : WriteIDs) {
1272 MCReadAdvanceEntry RAEntry;
1273 RAEntry.UseIdx = UseIdx;
1274 RAEntry.WriteResourceID = W;
1275 RAEntry.Cycles = ReadAdvance->getValueAsInt(FieldName: "Cycles") + T;
1276 ReadAdvanceEntries.push_back(x: RAEntry);
1277 }
1278 }
1279 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
1280 WriteProcResources.clear();
1281 WriteLatencies.clear();
1282 ReadAdvanceEntries.clear();
1283 }
1284 // Add the information for this SchedClass to the global tables using basic
1285 // compression.
1286 //
1287 // WritePrecRes entries are sorted by ProcResIdx.
1288 llvm::sort(C&: WriteProcResources, Comp: LessWriteProcResources());
1289
1290 SCDesc.NumWriteProcResEntries = WriteProcResources.size();
1291 std::vector<MCWriteProcResEntry>::iterator WPRPos =
1292 std::search(first1: SchedTables.WriteProcResources.begin(),
1293 last1: SchedTables.WriteProcResources.end(),
1294 first2: WriteProcResources.begin(), last2: WriteProcResources.end());
1295 if (WPRPos != SchedTables.WriteProcResources.end())
1296 SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();
1297 else {
1298 SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();
1299 SchedTables.WriteProcResources.insert(position: WPRPos, first: WriteProcResources.begin(),
1300 last: WriteProcResources.end());
1301 }
1302 // Latency entries must remain in operand order.
1303 SCDesc.NumWriteLatencyEntries = WriteLatencies.size();
1304 std::vector<MCWriteLatencyEntry>::iterator WLPos = std::search(
1305 first1: SchedTables.WriteLatencies.begin(), last1: SchedTables.WriteLatencies.end(),
1306 first2: WriteLatencies.begin(), last2: WriteLatencies.end());
1307 if (WLPos != SchedTables.WriteLatencies.end()) {
1308 unsigned Idx = WLPos - SchedTables.WriteLatencies.begin();
1309 SCDesc.WriteLatencyIdx = Idx;
1310 for (unsigned I = 0, E = WriteLatencies.size(); I < E; ++I)
1311 if (SchedTables.WriterNames[Idx + I].find(str: WriterNames[I]) ==
1312 std::string::npos) {
1313 SchedTables.WriterNames[Idx + I] += "_" + WriterNames[I];
1314 }
1315 } else {
1316 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
1317 llvm::append_range(C&: SchedTables.WriteLatencies, R&: WriteLatencies);
1318 llvm::append_range(C&: SchedTables.WriterNames, R&: WriterNames);
1319 }
1320 // ReadAdvanceEntries must remain in operand order.
1321 SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
1322 std::vector<MCReadAdvanceEntry>::iterator RAPos =
1323 std::search(first1: SchedTables.ReadAdvanceEntries.begin(),
1324 last1: SchedTables.ReadAdvanceEntries.end(),
1325 first2: ReadAdvanceEntries.begin(), last2: ReadAdvanceEntries.end());
1326 if (RAPos != SchedTables.ReadAdvanceEntries.end())
1327 SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
1328 else {
1329 SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
1330 llvm::append_range(C&: SchedTables.ReadAdvanceEntries, R&: ReadAdvanceEntries);
1331 }
1332 }
1333}
1334
1335// Emit SchedClass tables for all processors and associated global tables.
1336void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
1337 raw_ostream &OS) {
1338 // Emit global WriteProcResTable.
1339 OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n"
1340 << "extern const llvm::MCWriteProcResEntry " << Target
1341 << "WriteProcResTable[] = {\n"
1342 << " { 0, 0, 0 }, // Invalid\n";
1343 for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
1344 WPRIdx != WPREnd; ++WPRIdx) {
1345 MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
1346 OS << " {" << format(Fmt: "%2d", Vals: WPREntry.ProcResourceIdx) << ", "
1347 << format(Fmt: "%2d", Vals: WPREntry.ReleaseAtCycle) << ", "
1348 << format(Fmt: "%2d", Vals: WPREntry.AcquireAtCycle) << "}";
1349 if (WPRIdx + 1 < WPREnd)
1350 OS << ',';
1351 OS << " // #" << WPRIdx << '\n';
1352 }
1353 OS << "}; // " << Target << "WriteProcResTable\n";
1354
1355 // Emit global WriteLatencyTable.
1356 OS << "\n// {Cycles, WriteResourceID}\n"
1357 << "extern const llvm::MCWriteLatencyEntry " << Target
1358 << "WriteLatencyTable[] = {\n"
1359 << " { 0, 0}, // Invalid\n";
1360 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
1361 WLIdx != WLEnd; ++WLIdx) {
1362 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
1363 OS << " {" << format(Fmt: "%2d", Vals: WLEntry.Cycles) << ", "
1364 << format(Fmt: "%2d", Vals: WLEntry.WriteResourceID) << "}";
1365 if (WLIdx + 1 < WLEnd)
1366 OS << ',';
1367 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
1368 }
1369 OS << "}; // " << Target << "WriteLatencyTable\n";
1370
1371 // Emit global ReadAdvanceTable.
1372 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1373 << "extern const llvm::MCReadAdvanceEntry " << Target
1374 << "ReadAdvanceTable[] = {\n"
1375 << " {0, 0, 0}, // Invalid\n";
1376 for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
1377 RAIdx != RAEnd; ++RAIdx) {
1378 MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
1379 OS << " {" << RAEntry.UseIdx << ", "
1380 << format(Fmt: "%2d", Vals: RAEntry.WriteResourceID) << ", "
1381 << format(Fmt: "%2d", Vals: RAEntry.Cycles) << "}";
1382 if (RAIdx + 1 < RAEnd)
1383 OS << ',';
1384 OS << " // #" << RAIdx << '\n';
1385 }
1386 OS << "}; // " << Target << "ReadAdvanceTable\n";
1387
1388 // Pool all SchedClass names in a string table.
1389 StringToOffsetTable StrTab;
1390 unsigned InvalidNameOff = StrTab.GetOrAddStringOffset(Str: "InvalidSchedClass");
1391
1392 // Emit a SchedClass table for each processor.
1393 for (const auto &[Idx, Proc] : enumerate(First: SchedModels.procModels())) {
1394 if (!Proc.hasInstrSchedModel())
1395 continue;
1396
1397 std::vector<MCSchedClassDesc> &SCTab =
1398 SchedTables.ProcSchedClasses[1 + Idx];
1399
1400 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO,"
1401 << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
1402 OS << "static const llvm::MCSchedClassDesc " << Proc.ModelName
1403 << "SchedClasses[] = {\n";
1404
1405 // The first class is always invalid. We no way to distinguish it except by
1406 // name and position.
1407 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" &&
1408 "invalid class not first");
1409 OS << " {DBGFIELD(" << InvalidNameOff << ") "
1410 << MCSchedClassDesc::InvalidNumMicroOps
1411 << ", false, false, false, 0, 0, 0, 0, 0, 0},\n";
1412
1413 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
1414 MCSchedClassDesc &MCDesc = SCTab[SCIdx];
1415 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(Idx: SCIdx);
1416 unsigned NameOff = StrTab.GetOrAddStringOffset(Str: SchedClass.Name);
1417 OS << " {DBGFIELD(/*" << SchedClass.Name << "*/ " << NameOff << ") ";
1418 if (SchedClass.Name.size() < 18)
1419 OS.indent(NumSpaces: 18 - SchedClass.Name.size());
1420 OS << MCDesc.NumMicroOps << ", " << (MCDesc.BeginGroup ? "true" : "false")
1421 << ", " << (MCDesc.EndGroup ? "true" : "false") << ", "
1422 << (MCDesc.RetireOOO ? "true" : "false") << ", "
1423 << format(Fmt: "%2d", Vals: MCDesc.WriteProcResIdx) << ", "
1424 << MCDesc.NumWriteProcResEntries << ", "
1425 << format(Fmt: "%2d", Vals: MCDesc.WriteLatencyIdx) << ", "
1426 << MCDesc.NumWriteLatencyEntries << ", "
1427 << format(Fmt: "%2d", Vals: MCDesc.ReadAdvanceIdx) << ", "
1428 << MCDesc.NumReadAdvanceEntries << "}, // #" << SCIdx << '\n';
1429 }
1430 OS << "}; // " << Proc.ModelName << "SchedClasses\n";
1431 }
1432
1433 StrTab.EmitStringTableDef(OS, Name: Target + "SchedClassNames");
1434}
1435
1436void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {
1437 // For each processor model.
1438 for (const CodeGenProcModel &PM : SchedModels.procModels()) {
1439 // Emit extra processor info if available.
1440 if (PM.hasExtraProcessorInfo())
1441 emitExtraProcessorInfo(ProcModel: PM, OS);
1442 // Emit processor resource table.
1443 if (PM.hasInstrSchedModel())
1444 emitProcessorResources(ProcModel: PM, OS);
1445 else if (!PM.ProcResourceDefs.empty())
1446 PrintFatalError(ErrorLoc: PM.ModelDef->getLoc(),
1447 Msg: "SchedMachineModel defines "
1448 "ProcResources without defining WriteRes SchedWriteRes");
1449
1450 // Begin processor itinerary properties
1451 OS << "\n";
1452 OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n";
1453 emitProcessorProp(OS, R: PM.ModelDef, Name: "IssueWidth", Separator: ',');
1454 emitProcessorProp(OS, R: PM.ModelDef, Name: "MicroOpBufferSize", Separator: ',');
1455 emitProcessorProp(OS, R: PM.ModelDef, Name: "LoopMicroOpBufferSize", Separator: ',');
1456 emitProcessorProp(OS, R: PM.ModelDef, Name: "LoadLatency", Separator: ',');
1457 emitProcessorProp(OS, R: PM.ModelDef, Name: "HighLatency", Separator: ',');
1458 emitProcessorProp(OS, R: PM.ModelDef, Name: "MispredictPenalty", Separator: ',');
1459
1460 bool PostRAScheduler =
1461 (PM.ModelDef ? PM.ModelDef->getValueAsBit(FieldName: "PostRAScheduler") : false);
1462
1463 OS << " " << (PostRAScheduler ? "true" : "false") << ", // "
1464 << "PostRAScheduler\n";
1465
1466 bool CompleteModel =
1467 (PM.ModelDef ? PM.ModelDef->getValueAsBit(FieldName: "CompleteModel") : false);
1468
1469 OS << " " << (CompleteModel ? "true" : "false") << ", // "
1470 << "CompleteModel\n";
1471
1472 bool EnableIntervals =
1473 (PM.ModelDef ? PM.ModelDef->getValueAsBit(FieldName: "EnableIntervals") : false);
1474
1475 OS << " " << (EnableIntervals ? "true" : "false") << ", // "
1476 << "EnableIntervals\n";
1477
1478 OS << " " << PM.Index << ", // Processor ID\n";
1479 if (PM.hasInstrSchedModel())
1480 OS << " " << PM.ModelName << "ProcResources" << ",\n"
1481 << " " << PM.ModelName << "SchedClasses" << ",\n"
1482 << " " << PM.ProcResourceDefs.size() + 1 << ",\n"
1483 << " " << SchedModels.schedClasses().size() << ",\n";
1484 else
1485 OS << " nullptr, nullptr, 0, 0,"
1486 << " // No instruction-level machine model.\n";
1487 OS << " DBGVAL_OR_NULLPTR(&" << Target
1488 << "SchedClassNames), // SchedClassNames\n";
1489 if (PM.hasItineraries())
1490 OS << " " << PM.ItinsDef->getName() << ",\n";
1491 else
1492 OS << " nullptr, // No Itinerary\n";
1493 if (PM.hasExtraProcessorInfo())
1494 OS << " &" << PM.ModelName << "ExtraInfo,\n";
1495 else
1496 OS << " nullptr // No extra processor descriptor\n";
1497 OS << "};\n";
1498 }
1499}
1500
1501//
1502// EmitSchedModel - Emits all scheduling model tables, folding common patterns.
1503//
1504void SubtargetEmitter::emitSchedModel(raw_ostream &OS) {
1505 OS << "#ifdef DBGFIELD\n"
1506 << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
1507 << "#endif\n"
1508 << "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)\n"
1509 << "#define DBGFIELD(x) x,\n"
1510 << "#define DBGVAL_OR_NULLPTR(x) x\n"
1511 << "#else\n"
1512 << "#define DBGFIELD(x)\n"
1513 << "#define DBGVAL_OR_NULLPTR(x) nullptr\n"
1514 << "#endif\n";
1515
1516 if (SchedModels.hasItineraries()) {
1517 std::vector<std::vector<InstrItinerary>> ProcItinLists;
1518 // Emit the stage data
1519 emitStageAndOperandCycleData(OS, ProcItinLists);
1520 emitItineraries(OS, ProcItinLists);
1521 }
1522 OS << "\n// ===============================================================\n"
1523 << "// Data tables for the new per-operand machine model.\n";
1524
1525 SchedClassTables SchedTables;
1526 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
1527 genSchedClassTables(ProcModel, SchedTables);
1528 }
1529 emitSchedClassTables(SchedTables, OS);
1530
1531 // Emit the processor machine model
1532 emitProcessorModels(OS);
1533
1534 OS << "\n#undef DBGFIELD\n";
1535 OS << "\n#undef DBGVAL_OR_NULLPTR\n";
1536}
1537
1538static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
1539 std::string Buffer;
1540 raw_string_ostream Stream(Buffer);
1541
1542 // Print all PredicateProlog records to the output stream.
1543 for (const Record *P : Records.getAllDerivedDefinitions(ClassName: "PredicateProlog"))
1544 Stream << P->getValueAsString(FieldName: "Code") << '\n';
1545
1546 OS << Buffer;
1547}
1548
1549static bool isTruePredicate(const Record *Rec) {
1550 return Rec->isSubClassOf(Name: "MCSchedPredicate") &&
1551 Rec->getValueAsDef(FieldName: "Pred")->isSubClassOf(Name: "MCTrue");
1552}
1553
1554static void expandSchedPredicates(const Record *Rec, PredicateExpander &PE,
1555 bool WrapPredicate, raw_ostream &OS) {
1556 if (Rec->isSubClassOf(Name: "MCSchedPredicate")) {
1557 PE.expandPredicate(OS, Rec: Rec->getValueAsDef(FieldName: "Pred"));
1558 } else if (Rec->isSubClassOf(Name: "FeatureSchedPredicate")) {
1559 const Record *FR = Rec->getValueAsDef(FieldName: "Feature");
1560 if (PE.shouldExpandForMC()) {
1561 // MC version of this predicate will be emitted into
1562 // resolveVariantSchedClassImpl, which accesses MCSubtargetInfo
1563 // through argument STI.
1564 OS << "STI.";
1565 } else {
1566 // Otherwise, this predicate will be emitted directly into
1567 // TargetGenSubtargetInfo::resolveSchedClass, which can just access
1568 // TargetSubtargetInfo / MCSubtargetInfo through `this`.
1569 OS << "this->";
1570 }
1571 OS << "hasFeature(" << PE.getTargetName() << "::" << FR->getName() << ")";
1572 } else if (Rec->isSubClassOf(Name: "SchedPredicateCombiner")) {
1573 std::vector<const Record *> SubPreds =
1574 Rec->getValueAsListOfDefs(FieldName: "Predicates");
1575 if (SubPreds.empty())
1576 PrintFatalError(Rec, Msg: "Empty SchedPredicateCombiner is not allowed");
1577
1578 StringRef Sep;
1579 if (Rec->isSubClassOf(Name: "AllOfSchedPreds")) {
1580 Sep = " && ";
1581 } else if (Rec->isSubClassOf(Name: "AnyOfSchedPreds")) {
1582 Sep = " || ";
1583 } else if (Rec->isSubClassOf(Name: "NotSchedPred")) {
1584 if (SubPreds.size() != 1)
1585 PrintFatalError(Rec,
1586 Msg: "NotSchedPred can only have a single sub-predicate.");
1587 OS << "!";
1588 // We don't have to eagerly wrap this term right now: telling its (only)
1589 // sub-predicate to wrap itself should be sufficient.
1590 WrapPredicate = false;
1591 } else {
1592 PrintFatalError(Rec, Msg: "Unrecognized SchedPredicateCombiner");
1593 }
1594
1595 if (WrapPredicate)
1596 OS << "(";
1597
1598 ListSeparator LS(Sep);
1599 bool WrapSubPreds =
1600 SubPreds.size() > 1 || Rec->isSubClassOf(Name: "NotSchedPred");
1601 for (const Record *SubP : SubPreds)
1602 expandSchedPredicates(Rec: SubP, PE, WrapPredicate: WrapSubPreds, OS&: OS << LS);
1603
1604 if (WrapPredicate)
1605 OS << ")";
1606 } else {
1607 // Expand this legacy predicate and wrap it around braces if there is more
1608 // than one predicate to expand.
1609 OS << (WrapPredicate ? "(" : "") << Rec->getValueAsString(FieldName: "Predicate")
1610 << (WrapPredicate ? ")" : "");
1611 }
1612}
1613
1614static void emitPredicates(const CodeGenSchedTransition &T,
1615 const CodeGenSchedClass &SC, PredicateExpander &PE,
1616 raw_ostream &OS) {
1617 std::string Buffer;
1618 raw_string_ostream SS(Buffer);
1619
1620 // If not all predicates are MCTrue, then we need an if-stmt.
1621 unsigned NumNonTruePreds =
1622 T.PredTerm.size() - count_if(Range: T.PredTerm, P: isTruePredicate);
1623
1624 SS << PE.getIndent();
1625
1626 if (NumNonTruePreds) {
1627 bool FirstNonTruePredicate = true;
1628 SS << "if (";
1629
1630 PE.getIndent() += 2;
1631
1632 for (const Record *Rec : T.PredTerm) {
1633 // Skip predicates that evaluate to "true".
1634 if (isTruePredicate(Rec))
1635 continue;
1636
1637 if (FirstNonTruePredicate) {
1638 FirstNonTruePredicate = false;
1639 } else {
1640 SS << "\n";
1641 SS << PE.getIndent();
1642 SS << "&& ";
1643 }
1644
1645 expandSchedPredicates(Rec, PE, /*WrapPredicate=*/NumNonTruePreds > 1, OS&: SS);
1646 }
1647
1648 SS << ")\n"; // end of if-stmt
1649 --PE.getIndent();
1650 SS << PE.getIndent();
1651 --PE.getIndent();
1652 }
1653
1654 SS << "return " << T.ToClassIdx << "; // " << SC.Name << '\n';
1655 OS << Buffer;
1656}
1657
1658// Used by method `SubtargetEmitter::emitSchedModelHelpersImpl()` to generate
1659// epilogue code for the auto-generated helper.
1660static void emitSchedModelHelperEpilogue(raw_ostream &OS,
1661 bool ShouldReturnZero) {
1662 if (ShouldReturnZero) {
1663 OS << " // Don't know how to resolve this scheduling class.\n"
1664 << " return 0;\n";
1665 return;
1666 }
1667
1668 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n";
1669}
1670
1671static bool hasMCSchedPredicate(const Record *Rec) {
1672 if (Rec->isSubClassOf(Name: "MCSchedPredicate") ||
1673 Rec->isSubClassOf(Name: "FeatureSchedPredicate"))
1674 return true;
1675
1676 if (Rec->isSubClassOf(Name: "SchedPredicateCombiner")) {
1677 // Check its sub-predicates recursively.
1678 std::vector<const Record *> SubPreds =
1679 Rec->getValueAsListOfDefs(FieldName: "Predicates");
1680 return all_of(Range&: SubPreds, P: hasMCSchedPredicate);
1681 }
1682
1683 return false;
1684}
1685static bool hasMCSchedPredicates(const CodeGenSchedTransition &T) {
1686 return all_of(Range: T.PredTerm, P: hasMCSchedPredicate);
1687}
1688
1689static void collectVariantClasses(const CodeGenSchedModels &SchedModels,
1690 IdxVec &VariantClasses,
1691 bool OnlyExpandMCInstPredicates) {
1692 for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
1693 // Ignore non-variant scheduling classes.
1694 if (SC.Transitions.empty())
1695 continue;
1696
1697 if (OnlyExpandMCInstPredicates) {
1698 // Ignore this variant scheduling class no transitions use any meaningful
1699 // MCSchedPredicate definitions.
1700 if (llvm::none_of(Range: SC.Transitions, P: hasMCSchedPredicates))
1701 continue;
1702 }
1703
1704 VariantClasses.push_back(x: SC.Index);
1705 }
1706}
1707
1708static void collectProcessorIndices(const CodeGenSchedClass &SC,
1709 IdxVec &ProcIndices) {
1710 // A variant scheduling class may define transitions for multiple
1711 // processors. This function identifies wich processors are associated with
1712 // transition rules specified by variant class `SC`.
1713 for (const CodeGenSchedTransition &T : SC.Transitions) {
1714 IdxVec PI;
1715 std::set_union(first1: &T.ProcIndex, last1: &T.ProcIndex + 1, first2: ProcIndices.begin(),
1716 last2: ProcIndices.end(), result: std::back_inserter(x&: PI));
1717 ProcIndices = std::move(PI);
1718 }
1719}
1720
1721static bool isAlwaysTrue(const CodeGenSchedTransition &T) {
1722 return llvm::all_of(Range: T.PredTerm, P: isTruePredicate);
1723}
1724
1725void SubtargetEmitter::emitSchedModelHelpersImpl(
1726 raw_ostream &OS, bool OnlyExpandMCInstPredicates) {
1727 IdxVec VariantClasses;
1728 collectVariantClasses(SchedModels, VariantClasses,
1729 OnlyExpandMCInstPredicates);
1730
1731 if (VariantClasses.empty()) {
1732 emitSchedModelHelperEpilogue(OS, ShouldReturnZero: OnlyExpandMCInstPredicates);
1733 return;
1734 }
1735
1736 // Construct a switch statement where the condition is a check on the
1737 // scheduling class identifier. There is a `case` for every variant class
1738 // defined by the processor models of this target.
1739 // Each `case` implements a number of rules to resolve (i.e. to transition
1740 // from) a variant scheduling class to another scheduling class. Rules are
1741 // described by instances of CodeGenSchedTransition. Note that transitions may
1742 // not be valid for all processors.
1743 OS << " switch (SchedClass) {\n";
1744 for (unsigned VC : VariantClasses) {
1745 IdxVec ProcIndices;
1746 const CodeGenSchedClass &SC = SchedModels.getSchedClass(Idx: VC);
1747 collectProcessorIndices(SC, ProcIndices);
1748
1749 OS << " case " << VC << ": // " << SC.Name << '\n';
1750
1751 PredicateExpander PE(Target);
1752 PE.setByRef(false);
1753 PE.setExpandForMC(OnlyExpandMCInstPredicates);
1754 for (unsigned PI : ProcIndices) {
1755 OS << " ";
1756
1757 // Emit a guard on the processor ID.
1758 if (PI != 0) {
1759 OS << (OnlyExpandMCInstPredicates
1760 ? "if (CPUID == "
1761 : "if (SchedModel->getProcessorID() == ");
1762 OS << PI << ") ";
1763 OS << "{ // " << SchedModels.procModels()[PI].ModelName << '\n';
1764 }
1765
1766 // Now emit transitions associated with processor PI.
1767 const CodeGenSchedTransition *FinalT = nullptr;
1768 for (const CodeGenSchedTransition &T : SC.Transitions) {
1769 if (PI != 0 && T.ProcIndex != PI)
1770 continue;
1771
1772 // Emit only transitions based on MCSchedPredicate, if it's the case.
1773 // At least the transition specified by NoSchedPred is emitted,
1774 // which becomes the default transition for those variants otherwise
1775 // not based on MCSchedPredicate.
1776 // FIXME: preferably, llvm-mca should instead assume a reasonable
1777 // default when a variant transition is not based on MCSchedPredicate
1778 // for a given processor.
1779 if (OnlyExpandMCInstPredicates && !hasMCSchedPredicates(T))
1780 continue;
1781
1782 // If transition is folded to 'return X' it should be the last one.
1783 if (isAlwaysTrue(T)) {
1784 FinalT = &T;
1785 continue;
1786 }
1787 PE.getIndent() = 3;
1788 emitPredicates(T, SC: SchedModels.getSchedClass(Idx: T.ToClassIdx), PE, OS);
1789 }
1790 if (FinalT)
1791 emitPredicates(T: *FinalT, SC: SchedModels.getSchedClass(Idx: FinalT->ToClassIdx),
1792 PE, OS);
1793
1794 OS << " }\n";
1795
1796 if (PI == 0)
1797 break;
1798 }
1799
1800 if (SC.isInferred())
1801 OS << " return " << SC.Index << ";\n";
1802 OS << " break;\n";
1803 }
1804
1805 OS << " };\n";
1806
1807 emitSchedModelHelperEpilogue(OS, ShouldReturnZero: OnlyExpandMCInstPredicates);
1808}
1809
1810void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName,
1811 raw_ostream &OS) {
1812 OS << "unsigned " << ClassName
1813 << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
1814 << " const TargetSchedModel *SchedModel) const {\n";
1815
1816 // Emit the predicate prolog code.
1817 emitPredicateProlog(Records, OS);
1818
1819 // Emit target predicates.
1820 emitSchedModelHelpersImpl(OS);
1821
1822 OS << "} // " << ClassName << "::resolveSchedClass\n\n";
1823
1824 OS << "unsigned " << ClassName
1825 << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
1826 << " const MCInstrInfo *MCII, unsigned CPUID) const {\n"
1827 << " return " << Target << "_MC"
1828 << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n"
1829 << "} // " << ClassName << "::resolveVariantSchedClass\n\n";
1830
1831 STIPredicateExpander PE(Target, /*Indent=*/0);
1832 PE.setClassPrefix(ClassName);
1833 PE.setExpandDefinition(true);
1834 PE.setByRef(false);
1835
1836 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
1837 PE.expandSTIPredicate(OS, Fn);
1838}
1839
1840void SubtargetEmitter::emitHwModeCheck(const std::string &ClassName,
1841 raw_ostream &OS, bool IsMC) {
1842 const CodeGenHwModes &CGH = TGT.getHwModes();
1843 assert(CGH.getNumModeIds() > 0);
1844 if (CGH.getNumModeIds() == 1)
1845 return;
1846
1847 // Collect all HwModes and related features defined in the TD files,
1848 // and store them as a bit set.
1849 unsigned ValueTypeModes = 0;
1850 unsigned RegInfoModes = 0;
1851 unsigned EncodingInfoModes = 0;
1852 for (const auto &MS : CGH.getHwModeSelects()) {
1853 for (const HwModeSelect::PairType &P : MS.second.Items) {
1854 if (P.first == DefaultMode)
1855 continue;
1856 if (P.second->isSubClassOf(Name: "ValueType")) {
1857 ValueTypeModes |= (1 << (P.first - 1));
1858 } else if (P.second->isSubClassOf(Name: "RegInfo") ||
1859 P.second->isSubClassOf(Name: "SubRegRange") ||
1860 P.second->isSubClassOf(Name: "RegisterClassLike")) {
1861 RegInfoModes |= (1 << (P.first - 1));
1862 } else if (P.second->isSubClassOf(Name: "InstructionEncoding")) {
1863 EncodingInfoModes |= (1 << (P.first - 1));
1864 }
1865 }
1866 }
1867
1868 // Start emitting for getHwModeSet().
1869 OS << "unsigned " << ClassName << "::getHwModeSet() const {\n";
1870 if (IsMC) {
1871 OS << " [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();\n";
1872 } else {
1873 const ArrayRef<const Record *> &Prologs =
1874 Records.getAllDerivedDefinitions(ClassName: "HwModePredicateProlog");
1875 if (!Prologs.empty()) {
1876 for (const Record *P : Prologs)
1877 OS << P->getValueAsString(FieldName: "Code") << '\n';
1878 } else {
1879 // Works for most targets.
1880 OS << " [[maybe_unused]] const auto *Subtarget =\n"
1881 << " static_cast<const " << Target << "Subtarget *>(this);\n";
1882 }
1883 }
1884 OS << " // Collect HwModes and store them as a bit set.\n";
1885 OS << " unsigned Modes = 0;\n";
1886 for (unsigned M = 1, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
1887 const HwMode &HM = CGH.getMode(Id: M);
1888 OS << " if (";
1889 if (IsMC)
1890 SubtargetFeatureInfo::emitMCPredicateCheck(OS, TargetName: Target, Predicates: HM.Predicates);
1891 else
1892 SubtargetFeatureInfo::emitPredicateCheck(OS, Predicates: HM.Predicates);
1893 OS << ") Modes |= (1 << " << (M - 1) << ");\n";
1894 }
1895 OS << " return Modes;\n}\n";
1896 // End emitting for getHwModeSet().
1897
1898 auto HandlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) {
1899 OS << " case HwMode_" << ModeType << ":\n"
1900 << " Modes &= " << ModeInBitSet << ";\n"
1901 << " if (!Modes)\n return Modes;\n"
1902 << " if (!llvm::has_single_bit<unsigned>(Modes))\n"
1903 << " llvm_unreachable(\"Two or more HwModes for " << ModeType
1904 << " were found!\");\n"
1905 << " return llvm::countr_zero(Modes) + 1;\n";
1906 };
1907
1908 // Start emitting for getHwMode().
1909 OS << "unsigned " << ClassName
1910 << "::getHwMode(enum HwModeType type) const {\n";
1911 OS << " unsigned Modes = getHwModeSet();\n\n";
1912 OS << " if (!Modes)\n return Modes;\n\n";
1913 OS << " switch (type) {\n";
1914 OS << " case HwMode_Default:\n return llvm::countr_zero(Modes) + 1;\n";
1915 HandlePerMode("ValueType", ValueTypeModes);
1916 HandlePerMode("RegInfo", RegInfoModes);
1917 HandlePerMode("EncodingInfo", EncodingInfoModes);
1918 OS << " }\n";
1919 OS << " llvm_unreachable(\"unexpected HwModeType\");\n"
1920 << " return 0; // should not get here\n}\n";
1921 // End emitting for getHwMode().
1922}
1923
1924void SubtargetEmitter::emitGetMacroFusions(const std::string &ClassName,
1925 raw_ostream &OS) {
1926 if (!TGT.hasMacroFusion())
1927 return;
1928
1929 OS << "std::vector<MacroFusionPredTy> " << ClassName
1930 << "::getMacroFusions() const {\n";
1931 OS.indent(NumSpaces: 2) << "std::vector<MacroFusionPredTy> Fusions;\n";
1932 for (auto *Fusion : TGT.getMacroFusions()) {
1933 std::string Name = Fusion->getNameInitAsString();
1934 OS.indent(NumSpaces: 2) << "if (hasFeature(" << Target << "::" << Name
1935 << ")) Fusions.push_back(llvm::is" << Name << ");\n";
1936 }
1937
1938 OS.indent(NumSpaces: 2) << "return Fusions;\n";
1939 OS << "}\n";
1940}
1941
1942// Produces a subtarget specific function for parsing
1943// the subtarget features string.
1944void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) {
1945 ArrayRef<const Record *> Features =
1946 Records.getAllDerivedDefinitions(ClassName: "SubtargetFeature");
1947
1948 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1949 << "// subtarget options.\n"
1950 << "void llvm::";
1951 OS << Target;
1952 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, "
1953 << "StringRef FS) {\n"
1954 << " LLVM_DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
1955 << " LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n"
1956 << " LLVM_DEBUG(dbgs() << \"\\nTuneCPU:\" << TuneCPU << \"\\n\\n\");\n";
1957
1958 if (Features.empty()) {
1959 OS << "}\n";
1960 return;
1961 }
1962
1963 if (Target == "AArch64")
1964 OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
1965 << " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
1966
1967 OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
1968 << " const FeatureBitset &Bits = getFeatureBits();\n";
1969
1970 for (const Record *R : Features) {
1971 // Next record
1972 StringRef Instance = R->getName();
1973 StringRef Value = R->getValueAsString(FieldName: "Value");
1974 StringRef FieldName = R->getValueAsString(FieldName: "FieldName");
1975
1976 if (Value == "true" || Value == "false")
1977 OS << " if (Bits[" << Target << "::" << Instance << "]) " << FieldName
1978 << " = " << Value << ";\n";
1979 else
1980 OS << " if (Bits[" << Target << "::" << Instance << "] && " << FieldName
1981 << " < " << Value << ") " << FieldName << " = " << Value << ";\n";
1982 }
1983
1984 OS << "}\n";
1985}
1986
1987void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
1988 {
1989 NamespaceEmitter NS(OS, (Target + Twine("_MC")).str());
1990 OS << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
1991 << " const MCInst *MI, const MCInstrInfo *MCII, "
1992 << "const MCSubtargetInfo &STI, unsigned CPUID) {\n";
1993 emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ OnlyExpandMCInstPredicates: true);
1994 OS << "}\n";
1995 }
1996
1997 OS << "struct " << Target
1998 << "GenMCSubtargetInfo : public MCSubtargetInfo {\n";
1999 OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT,\n"
2000 << " StringRef CPU, StringRef TuneCPU, StringRef FS,\n"
2001 << " ArrayRef<StringRef> PN,\n"
2002 << " ArrayRef<SubtargetFeatureKV> PF,\n"
2003 << " ArrayRef<SubtargetSubTypeKV> PD,\n"
2004 << " const MCWriteProcResEntry *WPR,\n"
2005 << " const MCWriteLatencyEntry *WL,\n"
2006 << " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
2007 << " const unsigned *OC, const unsigned *FP) :\n"
2008 << " MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,\n"
2009 << " WPR, WL, RA, IS, OC, FP) { }\n\n"
2010 << " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
2011 << " const MCInst *MI, const MCInstrInfo *MCII,\n"
2012 << " unsigned CPUID) const final {\n"
2013 << " return " << Target << "_MC"
2014 << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n";
2015 OS << " }\n";
2016 if (TGT.getHwModes().getNumModeIds() > 1) {
2017 OS << " unsigned getHwModeSet() const final;\n";
2018 OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
2019 "final;\n";
2020 }
2021 if (Target == "AArch64")
2022 OS << " bool isCPUStringValid(StringRef CPU) const final {\n"
2023 << " CPU = AArch64::resolveCPUAlias(CPU);\n"
2024 << " return MCSubtargetInfo::isCPUStringValid(CPU);\n"
2025 << " }\n";
2026 OS << "};\n";
2027 emitHwModeCheck(ClassName: Target + "GenMCSubtargetInfo", OS, /*IsMC=*/true);
2028}
2029
2030void SubtargetEmitter::emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS) {
2031 STIPredicateExpander PE(Target, /*Indent=*/0);
2032
2033 {
2034 IfDefEmitter IfDefDecls(OS, "GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS");
2035 PE.setExpandForMC(true);
2036 PE.setByRef(true);
2037 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
2038 PE.expandSTIPredicate(OS, Fn);
2039 }
2040
2041 IfDefEmitter IfDefDefs(OS, "GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS");
2042 std::string ClassPrefix = Target + "MCInstrAnalysis";
2043 PE.setExpandDefinition(true);
2044 PE.setClassPrefix(ClassPrefix);
2045 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
2046 PE.expandSTIPredicate(OS, Fn);
2047}
2048
2049FeatureMapTy SubtargetEmitter::emitEnums(raw_ostream &OS) {
2050 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_ENUM");
2051 NamespaceEmitter NS(OS, "llvm");
2052 return enumeration(OS);
2053}
2054
2055std::tuple<unsigned, unsigned, unsigned>
2056SubtargetEmitter::emitMCDesc(raw_ostream &OS, const FeatureMapTy &FeatureMap) {
2057 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_MC_DESC");
2058 if (Target == "AArch64")
2059 OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
2060 NamespaceEmitter LlvmNS(OS, "llvm");
2061
2062 unsigned NumFeatures = featureKeyValues(OS, FeatureMap);
2063 OS << "\n";
2064 emitSchedModel(OS);
2065 OS << "\n";
2066 unsigned NumProcs = cpuKeyValues(OS, FeatureMap);
2067 OS << "\n";
2068 unsigned NumNames = cpuNames(OS);
2069 OS << "\n";
2070
2071 // MCInstrInfo initialization routine.
2072 emitGenMCSubtargetInfo(OS);
2073
2074 OS << "\nstatic inline MCSubtargetInfo *create" << Target
2075 << "MCSubtargetInfoImpl("
2076 << "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n";
2077 if (Target == "AArch64")
2078 OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
2079 << " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
2080 OS << " return new " << Target
2081 << "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";
2082 if (NumNames)
2083 OS << Target << "Names, ";
2084 else
2085 OS << "{}, ";
2086 if (NumFeatures)
2087 OS << Target << "FeatureKV, ";
2088 else
2089 OS << "{}, ";
2090 if (NumProcs)
2091 OS << Target << "SubTypeKV, ";
2092 else
2093 OS << "{}, ";
2094 OS << '\n';
2095 OS.indent(NumSpaces: 22);
2096 OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "
2097 << Target << "ReadAdvanceTable, ";
2098 OS << '\n';
2099 OS.indent(NumSpaces: 22);
2100 if (SchedModels.hasItineraries()) {
2101 OS << Target << "Stages, " << Target << "OperandCycles, " << Target
2102 << "ForwardingPaths";
2103 } else {
2104 OS << "nullptr, nullptr, nullptr";
2105 }
2106 OS << ");\n}\n\n";
2107 return {NumNames, NumFeatures, NumProcs};
2108}
2109
2110void SubtargetEmitter::emitTargetDesc(raw_ostream &OS) {
2111 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_TARGET_DESC");
2112
2113 OS << "#include \"llvm/ADT/BitmaskEnum.h\"\n";
2114 OS << "#include \"llvm/Support/Debug.h\"\n";
2115 OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
2116 if (Target == "AArch64")
2117 OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
2118 parseFeaturesFunction(OS);
2119}
2120
2121void SubtargetEmitter::emitHeader(raw_ostream &OS) {
2122 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
2123 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_HEADER");
2124 NamespaceEmitter LLVMNS(OS, "llvm");
2125
2126 std::string ClassName = Target + "GenSubtargetInfo";
2127 OS << "class DFAPacketizer;\n";
2128 {
2129 NamespaceEmitter MCNS(OS, (Target + Twine("_MC")).str());
2130 OS << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
2131 << " const MCInst *MI, const MCInstrInfo *MCII, "
2132 << "const MCSubtargetInfo &STI, unsigned CPUID);\n";
2133 }
2134 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
2135 << " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
2136 << "StringRef TuneCPU, StringRef FS);\n"
2137 << "public:\n"
2138 << " unsigned resolveSchedClass(unsigned SchedClass, "
2139 << " const MachineInstr *DefMI,"
2140 << " const TargetSchedModel *SchedModel) const final;\n"
2141 << " unsigned resolveVariantSchedClass(unsigned SchedClass,"
2142 << " const MCInst *MI, const MCInstrInfo *MCII,"
2143 << " unsigned CPUID) const final;\n"
2144 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
2145 << " const;\n";
2146
2147 const CodeGenHwModes &CGH = TGT.getHwModes();
2148 if (CGH.getNumModeIds() > 1) {
2149 OS << " enum class " << Target << "HwModeBits : unsigned {\n";
2150 for (unsigned M = 0, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
2151 StringRef ModeName = CGH.getModeName(Id: M, /*IncludeDefault=*/true);
2152 OS << " " << ModeName << " = ";
2153 if (M == 0)
2154 OS << "0";
2155 else
2156 OS << "(1 << " << (M - 1) << ")";
2157 OS << ",\n";
2158 if (M == NumModes - 1) {
2159 OS << "\n";
2160 OS << " LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/" << ModeName
2161 << "),\n";
2162 }
2163 }
2164 OS << " };\n";
2165
2166 OS << " unsigned getHwModeSet() const final;\n";
2167 OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
2168 "final;\n";
2169 }
2170 if (TGT.hasMacroFusion())
2171 OS << " std::vector<MacroFusionPredTy> getMacroFusions() const "
2172 "final;\n";
2173
2174 STIPredicateExpander PE(Target);
2175 PE.setByRef(false);
2176 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
2177 PE.expandSTIPredicate(OS, Fn);
2178 OS << "};\n";
2179}
2180
2181void SubtargetEmitter::emitCtor(raw_ostream &OS, unsigned NumNames,
2182 unsigned NumFeatures, unsigned NumProcs) {
2183 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_CTOR");
2184 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n";
2185
2186 NamespaceEmitter LLVMNS(OS, "llvm");
2187 OS << "extern const llvm::StringRef " << Target << "Names[];\n";
2188 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
2189 OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n";
2190 OS << "extern const llvm::MCWriteProcResEntry " << Target
2191 << "WriteProcResTable[];\n";
2192 OS << "extern const llvm::MCWriteLatencyEntry " << Target
2193 << "WriteLatencyTable[];\n";
2194 OS << "extern const llvm::MCReadAdvanceEntry " << Target
2195 << "ReadAdvanceTable[];\n";
2196
2197 if (SchedModels.hasItineraries()) {
2198 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
2199 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
2200 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
2201 }
2202
2203 std::string ClassName = Target + "GenSubtargetInfo";
2204 OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
2205 << "StringRef TuneCPU, StringRef FS)\n";
2206
2207 if (Target == "AArch64")
2208 OS << " : TargetSubtargetInfo(TT, AArch64::resolveCPUAlias(CPU),\n"
2209 << " AArch64::resolveCPUAlias(TuneCPU), FS, ";
2210 else
2211 OS << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
2212 if (NumNames)
2213 OS << "ArrayRef(" << Target << "Names, " << NumNames << "), ";
2214 else
2215 OS << "{}, ";
2216 if (NumFeatures)
2217 OS << "ArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
2218 else
2219 OS << "{}, ";
2220 if (NumProcs)
2221 OS << "ArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
2222 else
2223 OS << "{}, ";
2224 OS << '\n';
2225 OS.indent(NumSpaces: 24);
2226 OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "
2227 << Target << "ReadAdvanceTable, ";
2228 OS << '\n';
2229 OS.indent(NumSpaces: 24);
2230 if (SchedModels.hasItineraries()) {
2231 OS << Target << "Stages, " << Target << "OperandCycles, " << Target
2232 << "ForwardingPaths";
2233 } else {
2234 OS << "nullptr, nullptr, nullptr";
2235 }
2236 OS << ") {}\n\n";
2237
2238 emitSchedModelHelpers(ClassName, OS);
2239 emitHwModeCheck(ClassName, OS, /*IsMC=*/false);
2240 emitGetMacroFusions(ClassName, OS);
2241}
2242
2243//
2244// SubtargetEmitter::run - Main subtarget enumeration emitter.
2245//
2246void SubtargetEmitter::run(raw_ostream &OS) {
2247 emitSourceFileHeader(Desc: "Subtarget Enumeration Source Fragment", OS);
2248
2249 auto FeatureMap = emitEnums(OS);
2250 emitSubtargetInfoMacroCalls(OS);
2251 auto [NumNames, NumFeatures, NumProcs] = emitMCDesc(OS, FeatureMap);
2252 emitTargetDesc(OS);
2253 emitHeader(OS);
2254 emitCtor(OS, NumNames, NumFeatures, NumProcs);
2255 emitMcInstrAnalysisPredicateFunctions(OS);
2256}
2257
2258static TableGen::Emitter::OptClass<SubtargetEmitter>
2259 X("gen-subtarget", "Generate subtarget enumerations");
2260