1//===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend emits subtarget enumerations.
10//
11//===----------------------------------------------------------------------===//
12
13#include "Basic/TargetFeaturesEmitter.h"
14#include "Common/CodeGenHwModes.h"
15#include "Common/CodeGenSchedule.h"
16#include "Common/CodeGenTarget.h"
17#include "Common/PredicateExpander.h"
18#include "Common/SubtargetFeatureInfo.h"
19#include "Common/Utils.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallPtrSet.h"
22#include "llvm/ADT/StringExtras.h"
23#include "llvm/ADT/StringMap.h"
24#include "llvm/ADT/StringRef.h"
25#include "llvm/MC/MCInstrItineraries.h"
26#include "llvm/MC/MCSchedule.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/Format.h"
29#include "llvm/Support/raw_ostream.h"
30#include "llvm/TableGen/CodeGenHelpers.h"
31#include "llvm/TableGen/Error.h"
32#include "llvm/TableGen/Record.h"
33#include "llvm/TableGen/StringToOffsetTable.h"
34#include "llvm/TableGen/TableGenBackend.h"
35#include <algorithm>
36#include <cassert>
37#include <cstdint>
38#include <iterator>
39#include <string>
40#include <vector>
41
42using namespace llvm;
43
44#define DEBUG_TYPE "subtarget-emitter"
45
46namespace {
47
48class SubtargetEmitter : TargetFeaturesEmitter {
49 // Each processor has a SchedClassDesc table with an entry for each
50 // SchedClass. The SchedClassDesc table indexes into a global write resource
51 // table, write latency table, and read advance table.
52 struct SchedClassTables {
53 std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
54 std::vector<MCWriteProcResEntry> WriteProcResources;
55 std::vector<MCWriteLatencyEntry> WriteLatencies;
56 std::vector<std::string> WriterNames;
57 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
58
59 // Reserve an invalid entry at index 0
60 SchedClassTables() {
61 ProcSchedClasses.resize(new_size: 1);
62 WriteProcResources.resize(new_size: 1);
63 WriteLatencies.resize(new_size: 1);
64 WriterNames.push_back(x: "InvalidWrite");
65 ReadAdvanceEntries.resize(new_size: 1);
66 }
67 };
68
69 struct LessWriteProcResources {
70 bool operator()(const MCWriteProcResEntry &LHS,
71 const MCWriteProcResEntry &RHS) {
72 return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
73 }
74 };
75
76 CodeGenTarget TGT;
77 CodeGenSchedModels &SchedModels;
78
79 FeatureMapTy emitEnums(raw_ostream &OS);
80 void emitSubtargetInfoMacroCalls(raw_ostream &OS);
81 std::tuple<unsigned, unsigned, unsigned>
82 emitMCDesc(raw_ostream &OS, const FeatureMapTy &FeatureMap);
83 void emitTargetDesc(raw_ostream &OS);
84 void emitHeader(raw_ostream &OS);
85 void emitCtor(raw_ostream &OS, unsigned NumNames, unsigned NumFeatures,
86 unsigned NumProcs);
87
88 unsigned featureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);
89 unsigned cpuKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);
90 unsigned cpuNames(raw_ostream &OS);
91 void formItineraryStageString(const std::string &Names,
92 const Record *ItinData, std::string &ItinString,
93 unsigned &NStages);
94 void formItineraryOperandCycleString(const Record *ItinData,
95 std::string &ItinString,
96 unsigned &NOperandCycles);
97 void formItineraryBypassString(const std::string &Names,
98 const Record *ItinData,
99 std::string &ItinString,
100 unsigned NOperandCycles);
101 void emitStageAndOperandCycleData(
102 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists);
103 void emitItineraries(raw_ostream &OS,
104 ArrayRef<std::vector<InstrItinerary>> ProcItinLists);
105 unsigned emitRegisterFileTables(const CodeGenProcModel &ProcModel,
106 raw_ostream &OS);
107 void emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
108 raw_ostream &OS);
109 void emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
110 raw_ostream &OS);
111 void emitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
112 char Separator);
113 void emitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
114 raw_ostream &OS);
115 void emitProcessorResources(const CodeGenProcModel &ProcModel,
116 raw_ostream &OS);
117 const Record *findWriteResources(const CodeGenSchedRW &SchedWrite,
118 const CodeGenProcModel &ProcModel);
119 const Record *findReadAdvance(const CodeGenSchedRW &SchedRead,
120 const CodeGenProcModel &ProcModel);
121 void expandProcResources(ConstRecVec &PRVec,
122 std::vector<int64_t> &ReleaseAtCycles,
123 std::vector<int64_t> &AcquireAtCycles,
124 const CodeGenProcModel &ProcModel);
125 void genSchedClassTables(const CodeGenProcModel &ProcModel,
126 SchedClassTables &SchedTables);
127 void emitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
128 void emitProcessorModels(raw_ostream &OS);
129 void emitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
130 void emitSchedModelHelpersImpl(raw_ostream &OS,
131 bool OnlyExpandMCInstPredicates = false);
132 void emitGenMCSubtargetInfo(raw_ostream &OS);
133 void emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS);
134
135 void emitSchedModel(raw_ostream &OS);
136 void emitGetMacroFusions(const std::string &ClassName, raw_ostream &OS);
137 void emitHwModeCheck(const std::string &ClassName, raw_ostream &OS,
138 bool IsMC);
139 void emitInlineFeatures(const std::string &ClassName, raw_ostream &OS,
140 StringRef Behavior);
141 void parseFeaturesFunction(raw_ostream &OS);
142
143public:
144 SubtargetEmitter(const RecordKeeper &R)
145 : TargetFeaturesEmitter(R), TGT(R), SchedModels(TGT.getSchedModels()) {}
146
147 void run(raw_ostream &O) override;
148};
149
150} // end anonymous namespace
151
152/// Emit some information about the SubtargetFeature as calls to a macro so
153/// that they can be used from C++.
154void SubtargetEmitter::emitSubtargetInfoMacroCalls(raw_ostream &OS) {
155 // Undef the GET_SUBTARGETINFO_MACRO macro at the end of the scope since it's
156 // used within the scope.
157 IfDefEmitter IfDefMacro(OS, "GET_SUBTARGETINFO_MACRO", /*LateUndef=*/true);
158
159 std::vector<const Record *> FeatureList =
160 Records.getAllDerivedDefinitions(ClassName: "SubtargetFeature");
161 llvm::sort(C&: FeatureList, Comp: LessRecordFieldFieldName());
162
163 for (const Record *Feature : FeatureList) {
164 const StringRef FieldName = Feature->getValueAsString(FieldName: "FieldName");
165 const StringRef Value = Feature->getValueAsString(FieldName: "Value");
166
167 // Only handle boolean features for now, excluding BitVectors and enums.
168 const bool IsBool = (Value == "false" || Value == "true") &&
169 !StringRef(FieldName).contains(C: '[');
170 if (!IsBool)
171 continue;
172
173 // Some features default to true, with values set to false if enabled.
174 const char *Default = Value == "false" ? "true" : "false";
175
176 // Define the getter with lowercased first char: xxxYyy() { return XxxYyy; }
177 const std::string Getter =
178 FieldName.substr(Start: 0, N: 1).lower() + FieldName.substr(Start: 1).str();
179
180 OS << "GET_SUBTARGETINFO_MACRO(" << FieldName << ", " << Default << ", "
181 << Getter << ")\n";
182 }
183}
184
185//
186// FeatureKeyValues - Emit data of all the subtarget features. Used by the
187// command line.
188//
189unsigned SubtargetEmitter::featureKeyValues(raw_ostream &OS,
190 const FeatureMapTy &FeatureMap) {
191 std::vector<const Record *> FeatureList =
192 Records.getAllDerivedDefinitions(ClassName: "SubtargetFeature");
193
194 // Remove features with empty name.
195 llvm::erase_if(C&: FeatureList, P: [](const Record *Rec) {
196 return Rec->getValueAsString(FieldName: "Name").empty();
197 });
198 if (FeatureList.empty())
199 return 0;
200
201 // Sort and check duplicate Feature name.
202 sortAndReportDuplicates(Records: FeatureList, ObjectName: "Feature");
203
204 // Begin feature table.
205 OS << "// Sorted (by key) array of values for CPU features.\n"
206 << "extern const llvm::SubtargetFeatureKV " << Target
207 << "FeatureKV[] = {\n";
208
209 for (const Record *Feature : FeatureList) {
210 // Next feature
211 StringRef Name = Feature->getName();
212 StringRef CommandLineName = Feature->getValueAsString(FieldName: "Name");
213 StringRef Desc = Feature->getValueAsString(FieldName: "Desc");
214
215 // Emit as { "feature", "description", { featureEnum }, { i1 , i2 , ... , in
216 // } }
217 OS << " { "
218 << "\"" << CommandLineName << "\", "
219 << "\"" << Desc << "\", " << Target << "::" << Name << ", ";
220
221 ConstRecVec ImpliesList = Feature->getValueAsListOfDefs(FieldName: "Implies");
222
223 printFeatureMask(OS, FeatureList: ImpliesList, FeatureMap);
224
225 OS << " },\n";
226 }
227
228 // End feature table.
229 OS << "};\n";
230
231 return FeatureList.size();
232}
233
234unsigned SubtargetEmitter::cpuNames(raw_ostream &OS) {
235 // Begin processor name table.
236 OS << "// Sorted array of names of CPU subtypes, including aliases.\n"
237 << "extern const llvm::StringRef " << Target << "Names[] = {\n";
238
239 std::vector<const Record *> ProcessorList =
240 Records.getAllDerivedDefinitions(ClassName: "Processor");
241
242 std::vector<const Record *> ProcessorAliasList =
243 Records.getAllDerivedDefinitionsIfDefined(ClassName: "ProcessorAlias");
244
245 SmallVector<StringRef> Names;
246 Names.reserve(N: ProcessorList.size() + ProcessorAliasList.size());
247
248 for (const Record *Processor : ProcessorList) {
249 StringRef Name = Processor->getValueAsString(FieldName: "Name");
250 Names.push_back(Elt: Name);
251 }
252
253 for (const Record *Rec : ProcessorAliasList) {
254 auto Name = Rec->getValueAsString(FieldName: "Name");
255 Names.push_back(Elt: Name);
256 }
257
258 llvm::sort(C&: Names);
259 llvm::interleave(
260 c: Names, os&: OS, each_fn: [&](StringRef Name) { OS << '"' << Name << '"'; }, separator: ",\n");
261
262 // End processor name table.
263 OS << "};\n";
264
265 return Names.size();
266}
267
268static void checkDuplicateCPUFeatures(StringRef CPUName,
269 ArrayRef<const Record *> Features,
270 ArrayRef<const Record *> TuneFeatures) {
271 // We have made sure each SubtargetFeature Record has a unique name, so we can
272 // simply use pointer sets here.
273 SmallPtrSet<const Record *, 8> FeatureSet, TuneFeatureSet;
274 for (const auto *FeatureRec : Features) {
275 if (!FeatureSet.insert(Ptr: FeatureRec).second)
276 PrintWarning(Msg: "Processor " + CPUName + " contains duplicate feature '" +
277 FeatureRec->getValueAsString(FieldName: "Name") + "'");
278 }
279
280 for (const auto *TuneFeatureRec : TuneFeatures) {
281 if (!TuneFeatureSet.insert(Ptr: TuneFeatureRec).second)
282 PrintWarning(Msg: "Processor " + CPUName +
283 " contains duplicate tune feature '" +
284 TuneFeatureRec->getValueAsString(FieldName: "Name") + "'");
285 if (FeatureSet.contains(Ptr: TuneFeatureRec))
286 PrintWarning(Msg: "Processor " + CPUName + " has '" +
287 TuneFeatureRec->getValueAsString(FieldName: "Name") +
288 "' in both feature and tune feature sets");
289 }
290}
291
292//
293// CPUKeyValues - Emit data of all the subtarget processors. Used by command
294// line.
295//
296unsigned SubtargetEmitter::cpuKeyValues(raw_ostream &OS,
297 const FeatureMapTy &FeatureMap) {
298 // Gather and sort processor information
299 std::vector<const Record *> ProcessorList =
300 Records.getAllDerivedDefinitions(ClassName: "Processor");
301 llvm::sort(C&: ProcessorList, Comp: LessRecordFieldName());
302
303 // Note that unlike `FeatureKeyValues`, here we do not need to check for
304 // duplicate processors, since that is already done when the SubtargetEmitter
305 // constructor calls `getSchedModels` to build a `CodeGenSchedModels` object,
306 // which does the duplicate processor check.
307
308 // Begin processor table.
309 OS << "// Sorted (by key) array of values for CPU subtype.\n"
310 << "extern const llvm::SubtargetSubTypeKV " << Target
311 << "SubTypeKV[] = {\n";
312
313 for (const Record *Processor : ProcessorList) {
314 StringRef Name = Processor->getValueAsString(FieldName: "Name");
315 ConstRecVec FeatureList = Processor->getValueAsListOfDefs(FieldName: "Features");
316 ConstRecVec TuneFeatureList =
317 Processor->getValueAsListOfDefs(FieldName: "TuneFeatures");
318
319 // Warn the user if there are duplicate processor features or tune
320 // features.
321 checkDuplicateCPUFeatures(CPUName: Name, Features: FeatureList, TuneFeatures: TuneFeatureList);
322
323 // Emit as "{ "cpu", "description", 0, { f1 , f2 , ... fn } },".
324 OS << " { "
325 << "\"" << Name << "\", ";
326
327 printFeatureMask(OS, FeatureList, FeatureMap);
328 OS << ", ";
329 printFeatureMask(OS, FeatureList: TuneFeatureList, FeatureMap);
330
331 // Emit the scheduler model pointer.
332 const std::string &ProcModelName =
333 SchedModels.getModelForProc(ProcDef: Processor).ModelName;
334 OS << ", &" << ProcModelName << " },\n";
335 }
336
337 // End processor table.
338 OS << "};\n";
339
340 return ProcessorList.size();
341}
342
343//
344// FormItineraryStageString - Compose a string containing the stage
345// data initialization for the specified itinerary. N is the number
346// of stages.
347//
348void SubtargetEmitter::formItineraryStageString(const std::string &Name,
349 const Record *ItinData,
350 std::string &ItinString,
351 unsigned &NStages) {
352 // Get states list
353 ConstRecVec StageList = ItinData->getValueAsListOfDefs(FieldName: "Stages");
354
355 // For each stage
356 unsigned N = NStages = StageList.size();
357 for (unsigned I = 0; I < N;) {
358 // Next stage
359 const Record *Stage = StageList[I];
360
361 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
362 int Cycles = Stage->getValueAsInt(FieldName: "Cycles");
363 ItinString += " { " + itostr(X: Cycles) + ", ";
364
365 // Get unit list
366 ConstRecVec UnitList = Stage->getValueAsListOfDefs(FieldName: "Units");
367
368 // For each unit
369 for (unsigned J = 0, M = UnitList.size(); J < M;) {
370 // Add name and bitwise or
371 ItinString += Name + "FU::" + UnitList[J]->getName().str();
372 if (++J < M)
373 ItinString += " | ";
374 }
375
376 int TimeInc = Stage->getValueAsInt(FieldName: "TimeInc");
377 ItinString += ", " + itostr(X: TimeInc);
378
379 int Kind = Stage->getValueAsInt(FieldName: "Kind");
380 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(X: Kind);
381
382 // Close off stage
383 ItinString += " }";
384 if (++I < N)
385 ItinString += ", ";
386 }
387}
388
389//
390// FormItineraryOperandCycleString - Compose a string containing the
391// operand cycle initialization for the specified itinerary. N is the
392// number of operands that has cycles specified.
393//
394void SubtargetEmitter::formItineraryOperandCycleString(
395 const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) {
396 // Get operand cycle list
397 std::vector<int64_t> OperandCycleList =
398 ItinData->getValueAsListOfInts(FieldName: "OperandCycles");
399
400 // For each operand cycle
401 NOperandCycles = OperandCycleList.size();
402 ListSeparator LS;
403 for (int OCycle : OperandCycleList) {
404 // Next operand cycle
405 ItinString += LS;
406 ItinString += " " + itostr(X: OCycle);
407 }
408}
409
410void SubtargetEmitter::formItineraryBypassString(const std::string &Name,
411 const Record *ItinData,
412 std::string &ItinString,
413 unsigned NOperandCycles) {
414 ConstRecVec BypassList = ItinData->getValueAsListOfDefs(FieldName: "Bypasses");
415 unsigned N = BypassList.size();
416 unsigned I = 0;
417 ListSeparator LS;
418 for (; I < N; ++I) {
419 ItinString += LS;
420 ItinString += Name + "Bypass::" + BypassList[I]->getName().str();
421 }
422 for (; I < NOperandCycles; ++I) {
423 ItinString += LS;
424 ItinString += " 0";
425 }
426}
427
428//
429// EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
430// cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
431// by CodeGenSchedClass::Index.
432//
433void SubtargetEmitter::emitStageAndOperandCycleData(
434 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
435 // Multiple processor models may share an itinerary record. Emit it once.
436 SmallPtrSet<const Record *, 8> ItinsDefSet;
437
438 // Emit functional units for all the itineraries.
439 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
440 if (!ItinsDefSet.insert(Ptr: ProcModel.ItinsDef).second)
441 continue;
442
443 ConstRecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs(FieldName: "FU");
444 if (FUs.empty())
445 continue;
446
447 StringRef Name = ProcModel.ItinsDef->getName();
448 {
449 OS << "\n// Functional units for \"" << Name << "\"\n";
450 NamespaceEmitter FUNamespace(OS, (Name + Twine("FU")).str());
451
452 for (const auto &[Idx, FU] : enumerate(First&: FUs))
453 OS << " const InstrStage::FuncUnits " << FU->getName() << " = 1ULL << "
454 << Idx << ";\n";
455 }
456
457 ConstRecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs(FieldName: "BP");
458 if (BPs.empty())
459 continue;
460 OS << "\n// Pipeline forwarding paths for itineraries \"" << Name << "\"\n";
461 NamespaceEmitter BypassNamespace(OS, (Name + Twine("Bypass")).str());
462
463 OS << " const unsigned NoBypass = 0;\n";
464 for (const auto &[Idx, BP] : enumerate(First&: BPs))
465 OS << " const unsigned " << BP->getName() << " = 1 << " << Idx << ";\n";
466 }
467
468 // Begin stages table
469 std::string StageTable =
470 "\nextern const llvm::InstrStage " + Target + "Stages[] = {\n";
471 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
472
473 // Begin operand cycle table
474 std::string OperandCycleTable =
475 "extern const unsigned " + Target + "OperandCycles[] = {\n";
476 OperandCycleTable += " 0, // No itinerary\n";
477
478 // Begin pipeline bypass table
479 std::string BypassTable =
480 "extern const unsigned " + Target + "ForwardingPaths[] = {\n";
481 BypassTable += " 0, // No itinerary\n";
482
483 // For each Itinerary across all processors, add a unique entry to the stages,
484 // operand cycles, and pipeline bypass tables. Then add the new Itinerary
485 // object with computed offsets to the ProcItinLists result.
486 unsigned StageCount = 1, OperandCycleCount = 1;
487 StringMap<unsigned> ItinStageMap, ItinOperandMap;
488 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
489 // Add process itinerary to the list.
490 std::vector<InstrItinerary> &ItinList = ProcItinLists.emplace_back();
491
492 // If this processor defines no itineraries, then leave the itinerary list
493 // empty.
494 if (!ProcModel.hasItineraries())
495 continue;
496
497 StringRef Name = ProcModel.ItinsDef->getName();
498
499 ItinList.resize(new_size: SchedModels.numInstrSchedClasses());
500 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
501
502 for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size();
503 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
504
505 // Next itinerary data
506 const Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
507
508 // Get string and stage count
509 std::string ItinStageString;
510 unsigned NStages = 0;
511 if (ItinData)
512 formItineraryStageString(Name: Name.str(), ItinData, ItinString&: ItinStageString,
513 NStages);
514
515 // Get string and operand cycle count
516 std::string ItinOperandCycleString;
517 unsigned NOperandCycles = 0;
518 std::string ItinBypassString;
519 if (ItinData) {
520 formItineraryOperandCycleString(ItinData, ItinString&: ItinOperandCycleString,
521 NOperandCycles);
522
523 formItineraryBypassString(Name: Name.str(), ItinData, ItinString&: ItinBypassString,
524 NOperandCycles);
525 }
526
527 // Check to see if stage already exists and create if it doesn't
528 uint16_t FindStage = 0;
529 if (NStages > 0) {
530 FindStage = ItinStageMap[ItinStageString];
531 if (FindStage == 0) {
532 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
533 StageTable += ItinStageString + ", // " + itostr(X: StageCount);
534 if (NStages > 1)
535 StageTable += "-" + itostr(X: StageCount + NStages - 1);
536 StageTable += "\n";
537 // Record Itin class number.
538 ItinStageMap[ItinStageString] = FindStage = StageCount;
539 StageCount += NStages;
540 }
541 }
542
543 // Check to see if operand cycle already exists and create if it doesn't
544 uint16_t FindOperandCycle = 0;
545 if (NOperandCycles > 0) {
546 std::string ItinOperandString =
547 ItinOperandCycleString + ItinBypassString;
548 FindOperandCycle = ItinOperandMap[ItinOperandString];
549 if (FindOperandCycle == 0) {
550 // Emit as cycle, // index
551 OperandCycleTable += ItinOperandCycleString + ", // ";
552 std::string OperandIdxComment = itostr(X: OperandCycleCount);
553 if (NOperandCycles > 1)
554 OperandIdxComment +=
555 "-" + itostr(X: OperandCycleCount + NOperandCycles - 1);
556 OperandCycleTable += OperandIdxComment + "\n";
557 // Record Itin class number.
558 ItinOperandMap[ItinOperandCycleString] = FindOperandCycle =
559 OperandCycleCount;
560 // Emit as bypass, // index
561 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
562 OperandCycleCount += NOperandCycles;
563 }
564 }
565
566 // Set up itinerary as location and location + stage count
567 int16_t NumUOps = ItinData ? ItinData->getValueAsInt(FieldName: "NumMicroOps") : 0;
568 InstrItinerary Intinerary = {
569 .NumMicroOps: NumUOps,
570 .FirstStage: FindStage,
571 .LastStage: uint16_t(FindStage + NStages),
572 .FirstOperandCycle: FindOperandCycle,
573 .LastOperandCycle: uint16_t(FindOperandCycle + NOperandCycles),
574 };
575
576 // Inject - empty slots will be 0, 0
577 ItinList[SchedClassIdx] = Intinerary;
578 }
579 }
580
581 // Closing stage
582 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
583 StageTable += "};\n";
584
585 // Closing operand cycles
586 OperandCycleTable += " 0 // End operand cycles\n";
587 OperandCycleTable += "};\n";
588
589 BypassTable += " 0 // End bypass tables\n";
590 BypassTable += "};\n";
591
592 // Emit tables.
593 OS << StageTable;
594 OS << OperandCycleTable;
595 OS << BypassTable;
596}
597
598//
599// EmitProcessorData - Generate data for processor itineraries that were
600// computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
601// Itineraries for each processor. The Itinerary lists are indexed on
602// CodeGenSchedClass::Index.
603//
604void SubtargetEmitter::emitItineraries(
605 raw_ostream &OS, ArrayRef<std::vector<InstrItinerary>> ProcItinLists) {
606 // Multiple processor models may share an itinerary record. Emit it once.
607 SmallPtrSet<const Record *, 8> ItinsDefSet;
608
609 for (const auto &[Proc, ItinList] :
610 zip_equal(t: SchedModels.procModels(), u&: ProcItinLists)) {
611 const Record *ItinsDef = Proc.ItinsDef;
612 if (!ItinsDefSet.insert(Ptr: ItinsDef).second)
613 continue;
614
615 // Empty itineraries aren't referenced anywhere in the tablegen output
616 // so don't emit them.
617 if (ItinList.empty())
618 continue;
619
620 // Begin processor itinerary table
621 OS << "\n";
622 OS << "static constexpr llvm::InstrItinerary " << ItinsDef->getName()
623 << "[] = {\n";
624
625 ArrayRef<CodeGenSchedClass> ItinSchedClasses =
626 SchedModels.schedClasses().take_front(N: ItinList.size());
627
628 // For each itinerary class in CodeGenSchedClass::Index order.
629 for (const auto &[Idx, Intinerary, SchedClass] :
630 enumerate(First: ItinList, Rest&: ItinSchedClasses)) {
631 // Emit Itinerary in the form of
632 // { NumMicroOps, FirstStage, LastStage, FirstOperandCycle,
633 // LastOperandCycle } // index class name
634 OS << " { " << Intinerary.NumMicroOps << ", " << Intinerary.FirstStage
635 << ", " << Intinerary.LastStage << ", " << Intinerary.FirstOperandCycle
636 << ", " << Intinerary.LastOperandCycle << " }" << ", // " << Idx << " "
637 << SchedClass.Name << "\n";
638 }
639 // End processor itinerary table
640 OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
641 "// end marker\n";
642 OS << "};\n";
643 }
644}
645
646// Emit either the value defined in the TableGen Record, or the default
647// value defined in the C++ header. The Record is null if the processor does not
648// define a model.
649void SubtargetEmitter::emitProcessorProp(raw_ostream &OS, const Record *R,
650 StringRef Name, char Separator) {
651 OS << " ";
652 int V = R ? R->getValueAsInt(FieldName: Name) : -1;
653 if (V >= 0)
654 OS << V << Separator << " // " << Name;
655 else
656 OS << "MCSchedModel::Default" << Name << Separator;
657 OS << '\n';
658}
659
660void SubtargetEmitter::emitProcessorResourceSubUnits(
661 const CodeGenProcModel &ProcModel, raw_ostream &OS) {
662 OS << "\nstatic const unsigned " << ProcModel.ModelName
663 << "ProcResourceSubUnits[] = {\n"
664 << " 0, // Invalid\n";
665
666 for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {
667 const Record *PRDef = ProcModel.ProcResourceDefs[I];
668 if (!PRDef->isSubClassOf(Name: "ProcResGroup"))
669 continue;
670 for (const Record *RUDef : PRDef->getValueAsListOfDefs(FieldName: "Resources")) {
671 const Record *RU =
672 SchedModels.findProcResUnits(ProcResKind: RUDef, PM: ProcModel, Loc: PRDef->getLoc());
673 for (unsigned J = 0; J < RU->getValueAsInt(FieldName: "NumUnits"); ++J) {
674 OS << " " << ProcModel.getProcResourceIdx(PRDef: RU) << ", ";
675 }
676 }
677 OS << " // " << PRDef->getName() << "\n";
678 }
679 OS << "};\n";
680}
681
682static void emitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
683 raw_ostream &OS) {
684 int64_t ReorderBufferSize = 0, MaxRetirePerCycle = 0;
685 if (const Record *RCU = ProcModel.RetireControlUnit) {
686 ReorderBufferSize =
687 std::max(a: ReorderBufferSize, b: RCU->getValueAsInt(FieldName: "ReorderBufferSize"));
688 MaxRetirePerCycle =
689 std::max(a: MaxRetirePerCycle, b: RCU->getValueAsInt(FieldName: "MaxRetirePerCycle"));
690 }
691
692 OS << ReorderBufferSize << ", // ReorderBufferSize\n ";
693 OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n ";
694}
695
696static void emitRegisterFileInfo(const CodeGenProcModel &ProcModel,
697 unsigned NumRegisterFiles,
698 unsigned NumCostEntries, raw_ostream &OS) {
699 if (NumRegisterFiles)
700 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles);
701 else
702 OS << "nullptr,\n 0";
703
704 OS << ", // Number of register files.\n ";
705 if (NumCostEntries)
706 OS << ProcModel.ModelName << "RegisterCosts,\n ";
707 else
708 OS << "nullptr,\n ";
709 OS << NumCostEntries << ", // Number of register cost entries.\n";
710}
711
712unsigned
713SubtargetEmitter::emitRegisterFileTables(const CodeGenProcModel &ProcModel,
714 raw_ostream &OS) {
715 if (llvm::all_of(Range: ProcModel.RegisterFiles, P: [](const CodeGenRegisterFile &RF) {
716 return RF.hasDefaultCosts();
717 }))
718 return 0;
719
720 // Print the RegisterCost table first.
721 OS << "\n// {RegisterClassID, Register Cost, AllowMoveElimination }\n";
722 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
723 << "RegisterCosts"
724 << "[] = {\n";
725
726 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {
727 // Skip register files with a default cost table.
728 if (RF.hasDefaultCosts())
729 continue;
730 // Add entries to the cost table.
731 for (const CodeGenRegisterCost &RC : RF.Costs) {
732 OS << " { ";
733 const Record *Rec = RC.RCDef;
734 if (Rec->getValue(Name: "Namespace"))
735 OS << Rec->getValueAsString(FieldName: "Namespace") << "::";
736 OS << Rec->getName() << "RegClassID, " << RC.Cost << ", "
737 << RC.AllowMoveElimination << "},\n";
738 }
739 }
740 OS << "};\n";
741
742 // Now generate a table with register file info.
743 OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl, "
744 << "MaxMovesEliminatedPerCycle, AllowZeroMoveEliminationOnly }\n";
745 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
746 << "RegisterFiles"
747 << "[] = {\n"
748 << " { \"InvalidRegisterFile\", 0, 0, 0, 0, 0 },\n";
749 unsigned CostTblIndex = 0;
750
751 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
752 OS << " { ";
753 OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", ";
754 unsigned NumCostEntries = RD.Costs.size();
755 OS << NumCostEntries << ", " << CostTblIndex << ", "
756 << RD.MaxMovesEliminatedPerCycle << ", "
757 << RD.AllowZeroMoveEliminationOnly << "},\n";
758 CostTblIndex += NumCostEntries;
759 }
760 OS << "};\n";
761
762 return CostTblIndex;
763}
764
765void SubtargetEmitter::emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
766 raw_ostream &OS) {
767 unsigned QueueID = 0;
768 if (ProcModel.LoadQueue) {
769 const Record *Queue = ProcModel.LoadQueue->getValueAsDef(FieldName: "QueueDescriptor");
770 QueueID = 1 + std::distance(first: ProcModel.ProcResourceDefs.begin(),
771 last: find(Range: ProcModel.ProcResourceDefs, Val: Queue));
772 }
773 OS << " " << QueueID << ", // Resource Descriptor for the Load Queue\n";
774
775 QueueID = 0;
776 if (ProcModel.StoreQueue) {
777 const Record *Queue =
778 ProcModel.StoreQueue->getValueAsDef(FieldName: "QueueDescriptor");
779 QueueID = 1 + std::distance(first: ProcModel.ProcResourceDefs.begin(),
780 last: find(Range: ProcModel.ProcResourceDefs, Val: Queue));
781 }
782 OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n";
783}
784
785void SubtargetEmitter::emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
786 raw_ostream &OS) {
787 // Generate a table of register file descriptors (one entry per each user
788 // defined register file), and a table of register costs.
789 unsigned NumCostEntries = emitRegisterFileTables(ProcModel, OS);
790
791 // Now generate a table for the extra processor info.
792 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
793 << "ExtraInfo = {\n ";
794
795 // Add information related to the retire control unit.
796 emitRetireControlUnitInfo(ProcModel, OS);
797
798 // Add information related to the register files (i.e. where to find register
799 // file descriptors and register costs).
800 emitRegisterFileInfo(ProcModel, NumRegisterFiles: ProcModel.RegisterFiles.size(),
801 NumCostEntries, OS);
802
803 // Add information about load/store queues.
804 emitLoadStoreQueueInfo(ProcModel, OS);
805
806 OS << "};\n";
807}
808
809void SubtargetEmitter::emitProcessorResources(const CodeGenProcModel &ProcModel,
810 raw_ostream &OS) {
811 emitProcessorResourceSubUnits(ProcModel, OS);
812
813 OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n";
814 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
815 << "ProcResources"
816 << "[] = {\n"
817 << " {\"InvalidUnit\", 0, 0, 0, 0},\n";
818
819 unsigned SubUnitsOffset = 1;
820 for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {
821 const Record *PRDef = ProcModel.ProcResourceDefs[I];
822
823 const Record *SuperDef = nullptr;
824 unsigned SuperIdx = 0;
825 unsigned NumUnits = 0;
826 const unsigned SubUnitsBeginOffset = SubUnitsOffset;
827 int BufferSize = PRDef->getValueAsInt(FieldName: "BufferSize");
828 if (PRDef->isSubClassOf(Name: "ProcResGroup")) {
829 for (const Record *RU : PRDef->getValueAsListOfDefs(FieldName: "Resources")) {
830 NumUnits += RU->getValueAsInt(FieldName: "NumUnits");
831 SubUnitsOffset += RU->getValueAsInt(FieldName: "NumUnits");
832 }
833 } else {
834 // Find the SuperIdx
835 if (PRDef->getValueInit(FieldName: "Super")->isComplete()) {
836 SuperDef = SchedModels.findProcResUnits(ProcResKind: PRDef->getValueAsDef(FieldName: "Super"),
837 PM: ProcModel, Loc: PRDef->getLoc());
838 SuperIdx = ProcModel.getProcResourceIdx(PRDef: SuperDef);
839 }
840 NumUnits = PRDef->getValueAsInt(FieldName: "NumUnits");
841 }
842 // Emit the ProcResourceDesc
843 OS << " {\"" << PRDef->getName() << "\", ";
844 if (PRDef->getName().size() < 15)
845 OS.indent(NumSpaces: 15 - PRDef->getName().size());
846 OS << NumUnits << ", " << SuperIdx << ", " << BufferSize << ", ";
847 if (SubUnitsBeginOffset != SubUnitsOffset) {
848 OS << ProcModel.ModelName << "ProcResourceSubUnits + "
849 << SubUnitsBeginOffset;
850 } else {
851 OS << "nullptr";
852 }
853 OS << "}, // #" << I + 1;
854 if (SuperDef)
855 OS << ", Super=" << SuperDef->getName();
856 OS << "\n";
857 }
858 OS << "};\n";
859}
860
861// Find the WriteRes Record that defines processor resources for this
862// SchedWrite.
863const Record *
864SubtargetEmitter::findWriteResources(const CodeGenSchedRW &SchedWrite,
865 const CodeGenProcModel &ProcModel) {
866
867 // Check if the SchedWrite is already subtarget-specific and directly
868 // specifies a set of processor resources.
869 if (SchedWrite.TheDef->isSubClassOf(Name: "SchedWriteRes"))
870 return SchedWrite.TheDef;
871
872 const Record *AliasDef = nullptr;
873 for (const Record *A : SchedWrite.Aliases) {
874 const CodeGenSchedRW &AliasRW =
875 SchedModels.getSchedRW(Def: A->getValueAsDef(FieldName: "AliasRW"));
876 if (AliasRW.TheDef->getValueInit(FieldName: "SchedModel")->isComplete()) {
877 const Record *ModelDef = AliasRW.TheDef->getValueAsDef(FieldName: "SchedModel");
878 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
879 continue;
880 }
881 if (AliasDef)
882 PrintFatalError(ErrorLoc: AliasRW.TheDef->getLoc(),
883 Msg: "Multiple aliases "
884 "defined for processor " +
885 ProcModel.ModelName +
886 " Ensure only one SchedAlias exists per RW.");
887 AliasDef = AliasRW.TheDef;
888 }
889 if (AliasDef && AliasDef->isSubClassOf(Name: "SchedWriteRes"))
890 return AliasDef;
891
892 // Check this processor's list of write resources.
893 const Record *ResDef = nullptr;
894
895 auto I = ProcModel.WriteResMap.find(Val: SchedWrite.TheDef);
896 if (I != ProcModel.WriteResMap.end())
897 ResDef = I->second;
898
899 if (AliasDef) {
900 I = ProcModel.WriteResMap.find(Val: AliasDef);
901 if (I != ProcModel.WriteResMap.end()) {
902 if (ResDef)
903 PrintFatalError(ErrorLoc: I->second->getLoc(),
904 Msg: "Resources are defined for both SchedWrite and its "
905 "alias on processor " +
906 ProcModel.ModelName);
907 ResDef = I->second;
908 }
909 }
910
911 // TODO: If ProcModel has a base model (previous generation processor),
912 // then call FindWriteResources recursively with that model here.
913 if (!ResDef) {
914 PrintFatalError(ErrorLoc: ProcModel.ModelDef->getLoc(),
915 Msg: Twine("Processor does not define resources for ") +
916 SchedWrite.TheDef->getName());
917 }
918 return ResDef;
919}
920
921/// Find the ReadAdvance record for the given SchedRead on this processor or
922/// return NULL.
923const Record *
924SubtargetEmitter::findReadAdvance(const CodeGenSchedRW &SchedRead,
925 const CodeGenProcModel &ProcModel) {
926 // Check for SchedReads that directly specify a ReadAdvance.
927 if (SchedRead.TheDef->isSubClassOf(Name: "SchedReadAdvance"))
928 return SchedRead.TheDef;
929
930 // Check this processor's list of aliases for SchedRead.
931 const Record *AliasDef = nullptr;
932 for (const Record *A : SchedRead.Aliases) {
933 const CodeGenSchedRW &AliasRW =
934 SchedModels.getSchedRW(Def: A->getValueAsDef(FieldName: "AliasRW"));
935 if (AliasRW.TheDef->getValueInit(FieldName: "SchedModel")->isComplete()) {
936 const Record *ModelDef = AliasRW.TheDef->getValueAsDef(FieldName: "SchedModel");
937 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
938 continue;
939 }
940 if (AliasDef)
941 PrintFatalError(ErrorLoc: AliasRW.TheDef->getLoc(),
942 Msg: "Multiple aliases "
943 "defined for processor " +
944 ProcModel.ModelName +
945 " Ensure only one SchedAlias exists per RW.");
946 AliasDef = AliasRW.TheDef;
947 }
948 if (AliasDef && AliasDef->isSubClassOf(Name: "SchedReadAdvance"))
949 return AliasDef;
950
951 // Check this processor's ReadAdvanceList.
952 const Record *ResDef = nullptr;
953
954 auto I = ProcModel.ReadAdvanceMap.find(Val: SchedRead.TheDef);
955 if (I != ProcModel.ReadAdvanceMap.end())
956 ResDef = I->second;
957
958 if (AliasDef) {
959 I = ProcModel.ReadAdvanceMap.find(Val: AliasDef);
960 if (I != ProcModel.ReadAdvanceMap.end()) {
961 if (ResDef)
962 PrintFatalError(
963 ErrorLoc: I->second->getLoc(),
964 Msg: "Resources are defined for both SchedRead and its alias on "
965 "processor " +
966 ProcModel.ModelName);
967 ResDef = I->second;
968 }
969 }
970
971 // TODO: If ProcModel has a base model (previous generation processor),
972 // then call FindReadAdvance recursively with that model here.
973 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
974 PrintFatalError(ErrorLoc: ProcModel.ModelDef->getLoc(),
975 Msg: Twine("Processor does not define resources for ") +
976 SchedRead.TheDef->getName());
977 }
978 return ResDef;
979}
980
981// Expand an explicit list of processor resources into a full list of implied
982// resource groups and super resources that cover them.
983void SubtargetEmitter::expandProcResources(
984 ConstRecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
985 std::vector<int64_t> &AcquireAtCycles, const CodeGenProcModel &PM) {
986 assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition");
987 for (unsigned I = 0, E = PRVec.size(); I != E; ++I) {
988 const Record *PRDef = PRVec[I];
989 ConstRecVec SubResources;
990 if (PRDef->isSubClassOf(Name: "ProcResGroup")) {
991 SubResources = PRDef->getValueAsListOfDefs(FieldName: "Resources");
992 } else {
993 SubResources.push_back(x: PRDef);
994 PRDef = SchedModels.findProcResUnits(ProcResKind: PRDef, PM, Loc: PRDef->getLoc());
995 for (const Record *SubDef = PRDef;
996 SubDef->getValueInit(FieldName: "Super")->isComplete();) {
997 if (SubDef->isSubClassOf(Name: "ProcResGroup")) {
998 // Disallow this for simplicitly.
999 PrintFatalError(ErrorLoc: SubDef->getLoc(), Msg: "Processor resource group "
1000 " cannot be a super resources.");
1001 }
1002 const Record *SuperDef = SchedModels.findProcResUnits(
1003 ProcResKind: SubDef->getValueAsDef(FieldName: "Super"), PM, Loc: SubDef->getLoc());
1004 PRVec.push_back(x: SuperDef);
1005 ReleaseAtCycles.push_back(x: ReleaseAtCycles[I]);
1006 AcquireAtCycles.push_back(x: AcquireAtCycles[I]);
1007 SubDef = SuperDef;
1008 }
1009 }
1010 for (const Record *PR : PM.ProcResourceDefs) {
1011 if (PR == PRDef || !PR->isSubClassOf(Name: "ProcResGroup"))
1012 continue;
1013 ConstRecVec SuperResources = PR->getValueAsListOfDefs(FieldName: "Resources");
1014 bool AllContained =
1015 all_of(Range&: SubResources, P: [SuperResources](const Record *SubResource) {
1016 return is_contained(Range: SuperResources, Element: SubResource);
1017 });
1018 if (AllContained) {
1019 PRVec.push_back(x: PR);
1020 ReleaseAtCycles.push_back(x: ReleaseAtCycles[I]);
1021 AcquireAtCycles.push_back(x: AcquireAtCycles[I]);
1022 }
1023 }
1024 }
1025}
1026
1027// Generate the SchedClass table for this processor and update global
1028// tables. Must be called for each processor in order.
1029void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel,
1030 SchedClassTables &SchedTables) {
1031 std::vector<MCSchedClassDesc> &SCTab =
1032 SchedTables.ProcSchedClasses.emplace_back();
1033 if (!ProcModel.hasInstrSchedModel())
1034 return;
1035
1036 LLVM_DEBUG(dbgs() << "\n+++ SCHED CLASSES (GenSchedClassTables) +++\n");
1037 for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
1038 LLVM_DEBUG(SC.dump(&SchedModels));
1039
1040 MCSchedClassDesc &SCDesc = SCTab.emplace_back();
1041 // SCDesc.Name is guarded by NDEBUG
1042 SCDesc.NumMicroOps = 0;
1043 SCDesc.BeginGroup = false;
1044 SCDesc.EndGroup = false;
1045 SCDesc.RetireOOO = false;
1046 SCDesc.WriteProcResIdx = 0;
1047 SCDesc.WriteLatencyIdx = 0;
1048 SCDesc.ReadAdvanceIdx = 0;
1049
1050 // A Variant SchedClass has no resources of its own.
1051 bool HasVariants = false;
1052 for (const CodeGenSchedTransition &CGT : SC.Transitions) {
1053 if (CGT.ProcIndex == ProcModel.Index) {
1054 HasVariants = true;
1055 break;
1056 }
1057 }
1058 if (HasVariants) {
1059 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
1060 continue;
1061 }
1062
1063 // Determine if the SchedClass is actually reachable on this processor. If
1064 // not don't try to locate the processor resources, it will fail.
1065 // If ProcIndices contains 0, this class applies to all processors.
1066 assert(!SC.ProcIndices.empty() && "expect at least one procidx");
1067 if (SC.ProcIndices[0] != 0) {
1068 if (!is_contained(Range: SC.ProcIndices, Element: ProcModel.Index))
1069 continue;
1070 }
1071 IdxVec Writes = SC.Writes;
1072 IdxVec Reads = SC.Reads;
1073 if (!SC.InstRWs.empty()) {
1074 // This class has a default ReadWrite list which can be overridden by
1075 // InstRW definitions.
1076 const Record *RWDef = nullptr;
1077 for (const Record *RW : SC.InstRWs) {
1078 const Record *RWModelDef = RW->getValueAsDef(FieldName: "SchedModel");
1079 if (&ProcModel == &SchedModels.getProcModel(ModelDef: RWModelDef)) {
1080 RWDef = RW;
1081 break;
1082 }
1083 }
1084 if (RWDef) {
1085 Writes.clear();
1086 Reads.clear();
1087 SchedModels.findRWs(RWDefs: RWDef->getValueAsListOfDefs(FieldName: "OperandReadWrites"),
1088 Writes, Reads);
1089 }
1090 }
1091 if (Writes.empty()) {
1092 // Check this processor's itinerary class resources.
1093 for (const Record *I : ProcModel.ItinRWDefs) {
1094 ConstRecVec Matched = I->getValueAsListOfDefs(FieldName: "MatchedItinClasses");
1095 if (is_contained(Range&: Matched, Element: SC.ItinClassDef)) {
1096 SchedModels.findRWs(RWDefs: I->getValueAsListOfDefs(FieldName: "OperandReadWrites"),
1097 Writes, Reads);
1098 break;
1099 }
1100 }
1101 if (Writes.empty()) {
1102 LLVM_DEBUG(dbgs() << ProcModel.ModelName
1103 << " does not have resources for class " << SC.Name
1104 << '\n');
1105 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1106 }
1107 }
1108 // Sum resources across all operand writes.
1109 std::vector<MCWriteProcResEntry> WriteProcResources;
1110 std::vector<MCWriteLatencyEntry> WriteLatencies;
1111 std::vector<std::string> WriterNames;
1112 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
1113 for (unsigned W : Writes) {
1114 IdxVec WriteSeq;
1115 SchedModels.expandRWSeqForProc(RWIdx: W, RWSeq&: WriteSeq, /*IsRead=*/false, ProcModel);
1116
1117 // For each operand, create a latency entry.
1118 MCWriteLatencyEntry WLEntry;
1119 WLEntry.Cycles = 0;
1120 unsigned WriteID = WriteSeq.back();
1121 WriterNames.push_back(x: SchedModels.getSchedWrite(Idx: WriteID).Name);
1122 // If this Write is not referenced by a ReadAdvance, don't distinguish it
1123 // from other WriteLatency entries.
1124 if (!ProcModel.hasReadOfWrite(WriteDef: SchedModels.getSchedWrite(Idx: WriteID).TheDef))
1125 WriteID = 0;
1126 WLEntry.WriteResourceID = WriteID;
1127
1128 for (unsigned WS : WriteSeq) {
1129 const Record *WriteRes =
1130 findWriteResources(SchedWrite: SchedModels.getSchedWrite(Idx: WS), ProcModel);
1131
1132 // Mark the parent class as invalid for unsupported write types.
1133 if (WriteRes->getValueAsBit(FieldName: "Unsupported")) {
1134 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1135 break;
1136 }
1137 WLEntry.Cycles += WriteRes->getValueAsInt(FieldName: "Latency");
1138 SCDesc.NumMicroOps += WriteRes->getValueAsInt(FieldName: "NumMicroOps");
1139 SCDesc.BeginGroup |= WriteRes->getValueAsBit(FieldName: "BeginGroup");
1140 SCDesc.EndGroup |= WriteRes->getValueAsBit(FieldName: "EndGroup");
1141 SCDesc.BeginGroup |= WriteRes->getValueAsBit(FieldName: "SingleIssue");
1142 SCDesc.EndGroup |= WriteRes->getValueAsBit(FieldName: "SingleIssue");
1143 SCDesc.RetireOOO |= WriteRes->getValueAsBit(FieldName: "RetireOOO");
1144
1145 // Create an entry for each ProcResource listed in WriteRes.
1146 ConstRecVec PRVec = WriteRes->getValueAsListOfDefs(FieldName: "ProcResources");
1147 std::vector<int64_t> ReleaseAtCycles =
1148 WriteRes->getValueAsListOfInts(FieldName: "ReleaseAtCycles");
1149
1150 std::vector<int64_t> AcquireAtCycles =
1151 WriteRes->getValueAsListOfInts(FieldName: "AcquireAtCycles");
1152
1153 // Check consistency of the two vectors carrying the start and
1154 // stop cycles of the resources.
1155 if (!ReleaseAtCycles.empty() &&
1156 ReleaseAtCycles.size() != PRVec.size()) {
1157 // If ReleaseAtCycles is provided, check consistency.
1158 PrintFatalError(
1159 ErrorLoc: WriteRes->getLoc(),
1160 Msg: Twine("Inconsistent release at cycles: size(ReleaseAtCycles) != "
1161 "size(ProcResources): ")
1162 .concat(Suffix: Twine(PRVec.size()))
1163 .concat(Suffix: " vs ")
1164 .concat(Suffix: Twine(ReleaseAtCycles.size())));
1165 }
1166
1167 if (!AcquireAtCycles.empty() &&
1168 AcquireAtCycles.size() != PRVec.size()) {
1169 PrintFatalError(
1170 ErrorLoc: WriteRes->getLoc(),
1171 Msg: Twine("Inconsistent resource cycles: size(AcquireAtCycles) != "
1172 "size(ProcResources): ")
1173 .concat(Suffix: Twine(AcquireAtCycles.size()))
1174 .concat(Suffix: " vs ")
1175 .concat(Suffix: Twine(PRVec.size())));
1176 }
1177
1178 if (ReleaseAtCycles.empty()) {
1179 // If ReleaseAtCycles is not provided, default to one cycle
1180 // per resource.
1181 ReleaseAtCycles.resize(new_size: PRVec.size(), x: 1);
1182 }
1183
1184 if (AcquireAtCycles.empty()) {
1185 // If AcquireAtCycles is not provided, reserve the resource
1186 // starting from cycle 0.
1187 AcquireAtCycles.resize(new_size: PRVec.size(), x: 0);
1188 }
1189
1190 assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
1191
1192 expandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, PM: ProcModel);
1193 assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
1194
1195 for (unsigned PRIdx = 0, PREnd = PRVec.size(); PRIdx != PREnd;
1196 ++PRIdx) {
1197 MCWriteProcResEntry WPREntry;
1198 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRDef: PRVec[PRIdx]);
1199 assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
1200 WPREntry.ReleaseAtCycle = ReleaseAtCycles[PRIdx];
1201 WPREntry.AcquireAtCycle = AcquireAtCycles[PRIdx];
1202 if (AcquireAtCycles[PRIdx] > ReleaseAtCycles[PRIdx]) {
1203 PrintFatalError(
1204 ErrorLoc: WriteRes->getLoc(),
1205 Msg: Twine("Inconsistent resource cycles: AcquireAtCycles "
1206 "<= ReleaseAtCycles must hold."));
1207 }
1208 if (AcquireAtCycles[PRIdx] < 0) {
1209 PrintFatalError(ErrorLoc: WriteRes->getLoc(),
1210 Msg: Twine("Invalid value: AcquireAtCycle "
1211 "must be a non-negative value."));
1212 }
1213 // If this resource is already used in this sequence, add the current
1214 // entry's cycles so that the same resource appears to be used
1215 // serially, rather than multiple parallel uses. This is important for
1216 // in-order machine where the resource consumption is a hazard.
1217 unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();
1218 for (; WPRIdx != WPREnd; ++WPRIdx) {
1219 if (WriteProcResources[WPRIdx].ProcResourceIdx ==
1220 WPREntry.ProcResourceIdx) {
1221 // TODO: multiple use of the same resources would
1222 // require either 1. thinking of how to handle multiple
1223 // intervals for the same resource in
1224 // `<Target>WriteProcResTable` (see
1225 // `SubtargetEmitter::EmitSchedClassTables`), or
1226 // 2. thinking how to merge multiple intervals into a
1227 // single interval.
1228 assert(WPREntry.AcquireAtCycle == 0 &&
1229 "multiple use ofthe same resource is not yet handled");
1230 WriteProcResources[WPRIdx].ReleaseAtCycle +=
1231 WPREntry.ReleaseAtCycle;
1232 break;
1233 }
1234 }
1235 if (WPRIdx == WPREnd)
1236 WriteProcResources.push_back(x: WPREntry);
1237 }
1238 }
1239 WriteLatencies.push_back(x: WLEntry);
1240 }
1241 // Create an entry for each operand Read in this SchedClass.
1242 // Entries must be sorted first by UseIdx then by WriteResourceID.
1243 for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx;
1244 ++UseIdx) {
1245 const Record *ReadAdvance =
1246 findReadAdvance(SchedRead: SchedModels.getSchedRead(Idx: Reads[UseIdx]), ProcModel);
1247 if (!ReadAdvance)
1248 continue;
1249
1250 // Mark the parent class as invalid for unsupported write types.
1251 if (ReadAdvance->getValueAsBit(FieldName: "Unsupported")) {
1252 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1253 break;
1254 }
1255 ConstRecVec ValidWrites =
1256 ReadAdvance->getValueAsListOfDefs(FieldName: "ValidWrites");
1257 std::vector<int64_t> CycleTunables =
1258 ReadAdvance->getValueAsListOfInts(FieldName: "CycleTunables");
1259 std::vector<std::pair<unsigned, int>> WriteIDs;
1260 assert(CycleTunables.size() <= ValidWrites.size() && "Bad ReadAdvance");
1261 CycleTunables.resize(new_size: ValidWrites.size(), x: 0);
1262 if (ValidWrites.empty())
1263 WriteIDs.emplace_back(args: 0, args: 0);
1264 else {
1265 for (const auto [VW, CT] : zip_equal(t&: ValidWrites, u&: CycleTunables)) {
1266 unsigned WriteID = SchedModels.getSchedRWIdx(Def: VW, /*IsRead=*/false);
1267 assert(WriteID != 0 &&
1268 "Expected a valid SchedRW in the list of ValidWrites");
1269 WriteIDs.emplace_back(args&: WriteID, args&: CT);
1270 }
1271 }
1272 llvm::sort(C&: WriteIDs);
1273 for (const auto &[W, T] : WriteIDs) {
1274 MCReadAdvanceEntry RAEntry;
1275 RAEntry.UseIdx = UseIdx;
1276 RAEntry.WriteResourceID = W;
1277 RAEntry.Cycles = ReadAdvance->getValueAsInt(FieldName: "Cycles") + T;
1278 ReadAdvanceEntries.push_back(x: RAEntry);
1279 }
1280 }
1281 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
1282 WriteProcResources.clear();
1283 WriteLatencies.clear();
1284 ReadAdvanceEntries.clear();
1285 }
1286 // Add the information for this SchedClass to the global tables using basic
1287 // compression.
1288 //
1289 // WritePrecRes entries are sorted by ProcResIdx.
1290 llvm::sort(C&: WriteProcResources, Comp: LessWriteProcResources());
1291
1292 SCDesc.NumWriteProcResEntries = WriteProcResources.size();
1293 std::vector<MCWriteProcResEntry>::iterator WPRPos =
1294 std::search(first1: SchedTables.WriteProcResources.begin(),
1295 last1: SchedTables.WriteProcResources.end(),
1296 first2: WriteProcResources.begin(), last2: WriteProcResources.end());
1297 if (WPRPos != SchedTables.WriteProcResources.end())
1298 SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();
1299 else {
1300 SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();
1301 SchedTables.WriteProcResources.insert(position: WPRPos, first: WriteProcResources.begin(),
1302 last: WriteProcResources.end());
1303 }
1304 // Latency entries must remain in operand order.
1305 SCDesc.NumWriteLatencyEntries = WriteLatencies.size();
1306 std::vector<MCWriteLatencyEntry>::iterator WLPos = std::search(
1307 first1: SchedTables.WriteLatencies.begin(), last1: SchedTables.WriteLatencies.end(),
1308 first2: WriteLatencies.begin(), last2: WriteLatencies.end());
1309 if (WLPos != SchedTables.WriteLatencies.end()) {
1310 unsigned Idx = WLPos - SchedTables.WriteLatencies.begin();
1311 SCDesc.WriteLatencyIdx = Idx;
1312 for (unsigned I = 0, E = WriteLatencies.size(); I < E; ++I)
1313 if (SchedTables.WriterNames[Idx + I].find(str: WriterNames[I]) ==
1314 std::string::npos) {
1315 SchedTables.WriterNames[Idx + I] += "_" + WriterNames[I];
1316 }
1317 } else {
1318 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
1319 llvm::append_range(C&: SchedTables.WriteLatencies, R&: WriteLatencies);
1320 llvm::append_range(C&: SchedTables.WriterNames, R&: WriterNames);
1321 }
1322 // ReadAdvanceEntries must remain in operand order.
1323 SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
1324 std::vector<MCReadAdvanceEntry>::iterator RAPos =
1325 std::search(first1: SchedTables.ReadAdvanceEntries.begin(),
1326 last1: SchedTables.ReadAdvanceEntries.end(),
1327 first2: ReadAdvanceEntries.begin(), last2: ReadAdvanceEntries.end());
1328 if (RAPos != SchedTables.ReadAdvanceEntries.end())
1329 SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
1330 else {
1331 SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
1332 llvm::append_range(C&: SchedTables.ReadAdvanceEntries, R&: ReadAdvanceEntries);
1333 }
1334 }
1335}
1336
1337// Emit SchedClass tables for all processors and associated global tables.
1338void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
1339 raw_ostream &OS) {
1340 // Emit global WriteProcResTable.
1341 OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n"
1342 << "extern const llvm::MCWriteProcResEntry " << Target
1343 << "WriteProcResTable[] = {\n"
1344 << " { 0, 0, 0 }, // Invalid\n";
1345 for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
1346 WPRIdx != WPREnd; ++WPRIdx) {
1347 MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
1348 OS << " {" << format(Fmt: "%2d", Vals: WPREntry.ProcResourceIdx) << ", "
1349 << format(Fmt: "%2d", Vals: WPREntry.ReleaseAtCycle) << ", "
1350 << format(Fmt: "%2d", Vals: WPREntry.AcquireAtCycle) << "}";
1351 if (WPRIdx + 1 < WPREnd)
1352 OS << ',';
1353 OS << " // #" << WPRIdx << '\n';
1354 }
1355 OS << "}; // " << Target << "WriteProcResTable\n";
1356
1357 // Emit global WriteLatencyTable.
1358 OS << "\n// {Cycles, WriteResourceID}\n"
1359 << "extern const llvm::MCWriteLatencyEntry " << Target
1360 << "WriteLatencyTable[] = {\n"
1361 << " { 0, 0}, // Invalid\n";
1362 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
1363 WLIdx != WLEnd; ++WLIdx) {
1364 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
1365 OS << " {" << format(Fmt: "%2d", Vals: WLEntry.Cycles) << ", "
1366 << format(Fmt: "%2d", Vals: WLEntry.WriteResourceID) << "}";
1367 if (WLIdx + 1 < WLEnd)
1368 OS << ',';
1369 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
1370 }
1371 OS << "}; // " << Target << "WriteLatencyTable\n";
1372
1373 // Emit global ReadAdvanceTable.
1374 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1375 << "extern const llvm::MCReadAdvanceEntry " << Target
1376 << "ReadAdvanceTable[] = {\n"
1377 << " {0, 0, 0}, // Invalid\n";
1378 for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
1379 RAIdx != RAEnd; ++RAIdx) {
1380 MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
1381 OS << " {" << RAEntry.UseIdx << ", "
1382 << format(Fmt: "%2d", Vals: RAEntry.WriteResourceID) << ", "
1383 << format(Fmt: "%2d", Vals: RAEntry.Cycles) << "}";
1384 if (RAIdx + 1 < RAEnd)
1385 OS << ',';
1386 OS << " // #" << RAIdx << '\n';
1387 }
1388 OS << "}; // " << Target << "ReadAdvanceTable\n";
1389
1390 // Pool all SchedClass names in a string table.
1391 StringToOffsetTable StrTab;
1392 unsigned InvalidNameOff = StrTab.GetOrAddStringOffset(Str: "InvalidSchedClass");
1393
1394 // Emit a SchedClass table for each processor.
1395 for (const auto &[Idx, Proc] : enumerate(First: SchedModels.procModels())) {
1396 if (!Proc.hasInstrSchedModel())
1397 continue;
1398
1399 std::vector<MCSchedClassDesc> &SCTab =
1400 SchedTables.ProcSchedClasses[1 + Idx];
1401
1402 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO,"
1403 << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
1404 OS << "static const llvm::MCSchedClassDesc " << Proc.ModelName
1405 << "SchedClasses[] = {\n";
1406
1407 // The first class is always invalid. We no way to distinguish it except by
1408 // name and position.
1409 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" &&
1410 "invalid class not first");
1411 OS << " {DBGFIELD(" << InvalidNameOff << ") "
1412 << MCSchedClassDesc::InvalidNumMicroOps
1413 << ", false, false, false, 0, 0, 0, 0, 0, 0},\n";
1414
1415 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
1416 MCSchedClassDesc &MCDesc = SCTab[SCIdx];
1417 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(Idx: SCIdx);
1418 unsigned NameOff = StrTab.GetOrAddStringOffset(Str: SchedClass.Name);
1419 OS << " {DBGFIELD(/*" << SchedClass.Name << "*/ " << NameOff << ") ";
1420 if (SchedClass.Name.size() < 18)
1421 OS.indent(NumSpaces: 18 - SchedClass.Name.size());
1422 OS << MCDesc.NumMicroOps << ", " << (MCDesc.BeginGroup ? "true" : "false")
1423 << ", " << (MCDesc.EndGroup ? "true" : "false") << ", "
1424 << (MCDesc.RetireOOO ? "true" : "false") << ", "
1425 << format(Fmt: "%2d", Vals: MCDesc.WriteProcResIdx) << ", "
1426 << MCDesc.NumWriteProcResEntries << ", "
1427 << format(Fmt: "%2d", Vals: MCDesc.WriteLatencyIdx) << ", "
1428 << MCDesc.NumWriteLatencyEntries << ", "
1429 << format(Fmt: "%2d", Vals: MCDesc.ReadAdvanceIdx) << ", "
1430 << MCDesc.NumReadAdvanceEntries << "}, // #" << SCIdx << '\n';
1431 }
1432 OS << "}; // " << Proc.ModelName << "SchedClasses\n";
1433 }
1434
1435 StrTab.EmitStringTableDef(OS, Name: Target + "SchedClassNames");
1436}
1437
1438void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {
1439 // For each processor model.
1440 for (const CodeGenProcModel &PM : SchedModels.procModels()) {
1441 // Emit extra processor info if available.
1442 if (PM.hasExtraProcessorInfo())
1443 emitExtraProcessorInfo(ProcModel: PM, OS);
1444 // Emit processor resource table.
1445 if (PM.hasInstrSchedModel())
1446 emitProcessorResources(ProcModel: PM, OS);
1447 else if (!PM.ProcResourceDefs.empty())
1448 PrintFatalError(ErrorLoc: PM.ModelDef->getLoc(),
1449 Msg: "SchedMachineModel defines "
1450 "ProcResources without defining WriteRes SchedWriteRes");
1451
1452 // Begin processor itinerary properties
1453 OS << "\n";
1454 OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n";
1455 emitProcessorProp(OS, R: PM.ModelDef, Name: "IssueWidth", Separator: ',');
1456 emitProcessorProp(OS, R: PM.ModelDef, Name: "MicroOpBufferSize", Separator: ',');
1457 emitProcessorProp(OS, R: PM.ModelDef, Name: "LoopMicroOpBufferSize", Separator: ',');
1458 emitProcessorProp(OS, R: PM.ModelDef, Name: "LoadLatency", Separator: ',');
1459 emitProcessorProp(OS, R: PM.ModelDef, Name: "HighLatency", Separator: ',');
1460 emitProcessorProp(OS, R: PM.ModelDef, Name: "MispredictPenalty", Separator: ',');
1461
1462 bool PostRAScheduler =
1463 (PM.ModelDef ? PM.ModelDef->getValueAsBit(FieldName: "PostRAScheduler") : false);
1464
1465 OS << " " << (PostRAScheduler ? "true" : "false") << ", // "
1466 << "PostRAScheduler\n";
1467
1468 bool CompleteModel =
1469 (PM.ModelDef ? PM.ModelDef->getValueAsBit(FieldName: "CompleteModel") : false);
1470
1471 OS << " " << (CompleteModel ? "true" : "false") << ", // "
1472 << "CompleteModel\n";
1473
1474 bool EnableIntervals =
1475 (PM.ModelDef ? PM.ModelDef->getValueAsBit(FieldName: "EnableIntervals") : false);
1476
1477 OS << " " << (EnableIntervals ? "true" : "false") << ", // "
1478 << "EnableIntervals\n";
1479
1480 OS << " " << PM.Index << ", // Processor ID\n";
1481 if (PM.hasInstrSchedModel())
1482 OS << " " << PM.ModelName << "ProcResources" << ",\n"
1483 << " " << PM.ModelName << "SchedClasses" << ",\n"
1484 << " " << PM.ProcResourceDefs.size() + 1 << ",\n"
1485 << " " << SchedModels.schedClasses().size() << ",\n";
1486 else
1487 OS << " nullptr, nullptr, 0, 0,"
1488 << " // No instruction-level machine model.\n";
1489 OS << " DBGVAL_OR_NULLPTR(&" << Target
1490 << "SchedClassNames), // SchedClassNames\n";
1491 if (PM.hasItineraries())
1492 OS << " " << PM.ItinsDef->getName() << ",\n";
1493 else
1494 OS << " nullptr, // No Itinerary\n";
1495 if (PM.hasExtraProcessorInfo())
1496 OS << " &" << PM.ModelName << "ExtraInfo,\n";
1497 else
1498 OS << " nullptr // No extra processor descriptor\n";
1499 OS << "};\n";
1500 }
1501}
1502
1503//
1504// EmitSchedModel - Emits all scheduling model tables, folding common patterns.
1505//
1506void SubtargetEmitter::emitSchedModel(raw_ostream &OS) {
1507 OS << "#ifdef DBGFIELD\n"
1508 << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
1509 << "#endif\n"
1510 << "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)\n"
1511 << "#define DBGFIELD(x) x,\n"
1512 << "#define DBGVAL_OR_NULLPTR(x) x\n"
1513 << "#else\n"
1514 << "#define DBGFIELD(x)\n"
1515 << "#define DBGVAL_OR_NULLPTR(x) nullptr\n"
1516 << "#endif\n";
1517
1518 if (SchedModels.hasItineraries()) {
1519 std::vector<std::vector<InstrItinerary>> ProcItinLists;
1520 // Emit the stage data
1521 emitStageAndOperandCycleData(OS, ProcItinLists);
1522 emitItineraries(OS, ProcItinLists);
1523 }
1524 OS << "\n// ===============================================================\n"
1525 << "// Data tables for the new per-operand machine model.\n";
1526
1527 SchedClassTables SchedTables;
1528 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
1529 genSchedClassTables(ProcModel, SchedTables);
1530 }
1531 emitSchedClassTables(SchedTables, OS);
1532
1533 // Emit the processor machine model
1534 emitProcessorModels(OS);
1535
1536 OS << "\n#undef DBGFIELD\n";
1537 OS << "\n#undef DBGVAL_OR_NULLPTR\n";
1538}
1539
1540static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
1541 std::string Buffer;
1542 raw_string_ostream Stream(Buffer);
1543
1544 // Print all PredicateProlog records to the output stream.
1545 for (const Record *P : Records.getAllDerivedDefinitions(ClassName: "PredicateProlog"))
1546 Stream << P->getValueAsString(FieldName: "Code") << '\n';
1547
1548 OS << Buffer;
1549}
1550
1551static bool isTruePredicate(const Record *Rec) {
1552 return Rec->isSubClassOf(Name: "MCSchedPredicate") &&
1553 Rec->getValueAsDef(FieldName: "Pred")->isSubClassOf(Name: "MCTrue");
1554}
1555
1556static void expandSchedPredicates(const Record *Rec, PredicateExpander &PE,
1557 bool WrapPredicate, raw_ostream &OS) {
1558 if (Rec->isSubClassOf(Name: "MCSchedPredicate")) {
1559 PE.expandPredicate(OS, Rec: Rec->getValueAsDef(FieldName: "Pred"));
1560 } else if (Rec->isSubClassOf(Name: "FeatureSchedPredicate")) {
1561 const Record *FR = Rec->getValueAsDef(FieldName: "Feature");
1562 if (PE.shouldExpandForMC()) {
1563 // MC version of this predicate will be emitted into
1564 // resolveVariantSchedClassImpl, which accesses MCSubtargetInfo
1565 // through argument STI.
1566 OS << "STI.";
1567 } else {
1568 // Otherwise, this predicate will be emitted directly into
1569 // TargetGenSubtargetInfo::resolveSchedClass, which can just access
1570 // TargetSubtargetInfo / MCSubtargetInfo through `this`.
1571 OS << "this->";
1572 }
1573 OS << "hasFeature(" << PE.getTargetName() << "::" << FR->getName() << ")";
1574 } else if (Rec->isSubClassOf(Name: "SchedPredicateCombiner")) {
1575 std::vector<const Record *> SubPreds =
1576 Rec->getValueAsListOfDefs(FieldName: "Predicates");
1577 if (SubPreds.empty())
1578 PrintFatalError(Rec, Msg: "Empty SchedPredicateCombiner is not allowed");
1579
1580 StringRef Sep;
1581 if (Rec->isSubClassOf(Name: "AllOfSchedPreds")) {
1582 Sep = " && ";
1583 } else if (Rec->isSubClassOf(Name: "AnyOfSchedPreds")) {
1584 Sep = " || ";
1585 } else if (Rec->isSubClassOf(Name: "NotSchedPred")) {
1586 if (SubPreds.size() != 1)
1587 PrintFatalError(Rec,
1588 Msg: "NotSchedPred can only have a single sub-predicate.");
1589 OS << "!";
1590 // We don't have to eagerly wrap this term right now: telling its (only)
1591 // sub-predicate to wrap itself should be sufficient.
1592 WrapPredicate = false;
1593 } else {
1594 PrintFatalError(Rec, Msg: "Unrecognized SchedPredicateCombiner");
1595 }
1596
1597 if (WrapPredicate)
1598 OS << "(";
1599
1600 ListSeparator LS(Sep);
1601 bool WrapSubPreds =
1602 SubPreds.size() > 1 || Rec->isSubClassOf(Name: "NotSchedPred");
1603 for (const Record *SubP : SubPreds)
1604 expandSchedPredicates(Rec: SubP, PE, WrapPredicate: WrapSubPreds, OS&: OS << LS);
1605
1606 if (WrapPredicate)
1607 OS << ")";
1608 } else {
1609 // Expand this legacy predicate and wrap it around braces if there is more
1610 // than one predicate to expand.
1611 OS << (WrapPredicate ? "(" : "") << Rec->getValueAsString(FieldName: "Predicate")
1612 << (WrapPredicate ? ")" : "");
1613 }
1614}
1615
1616static void emitPredicates(const CodeGenSchedTransition &T,
1617 const CodeGenSchedClass &SC, PredicateExpander &PE,
1618 raw_ostream &OS) {
1619 std::string Buffer;
1620 raw_string_ostream SS(Buffer);
1621
1622 // If not all predicates are MCTrue, then we need an if-stmt.
1623 unsigned NumNonTruePreds =
1624 T.PredTerm.size() - count_if(Range: T.PredTerm, P: isTruePredicate);
1625
1626 SS << PE.getIndent();
1627
1628 if (NumNonTruePreds) {
1629 bool FirstNonTruePredicate = true;
1630 SS << "if (";
1631
1632 PE.getIndent() += 2;
1633
1634 for (const Record *Rec : T.PredTerm) {
1635 // Skip predicates that evaluate to "true".
1636 if (isTruePredicate(Rec))
1637 continue;
1638
1639 if (FirstNonTruePredicate) {
1640 FirstNonTruePredicate = false;
1641 } else {
1642 SS << "\n";
1643 SS << PE.getIndent();
1644 SS << "&& ";
1645 }
1646
1647 expandSchedPredicates(Rec, PE, /*WrapPredicate=*/NumNonTruePreds > 1, OS&: SS);
1648 }
1649
1650 SS << ")\n"; // end of if-stmt
1651 --PE.getIndent();
1652 SS << PE.getIndent();
1653 --PE.getIndent();
1654 }
1655
1656 SS << "return " << T.ToClassIdx << "; // " << SC.Name << '\n';
1657 OS << Buffer;
1658}
1659
1660// Used by method `SubtargetEmitter::emitSchedModelHelpersImpl()` to generate
1661// epilogue code for the auto-generated helper.
1662static void emitSchedModelHelperEpilogue(raw_ostream &OS,
1663 bool ShouldReturnZero) {
1664 if (ShouldReturnZero) {
1665 OS << " // Don't know how to resolve this scheduling class.\n"
1666 << " return 0;\n";
1667 return;
1668 }
1669
1670 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n";
1671}
1672
1673static bool hasMCSchedPredicate(const Record *Rec) {
1674 if (Rec->isSubClassOf(Name: "MCSchedPredicate") ||
1675 Rec->isSubClassOf(Name: "FeatureSchedPredicate"))
1676 return true;
1677
1678 if (Rec->isSubClassOf(Name: "SchedPredicateCombiner")) {
1679 // Check its sub-predicates recursively.
1680 std::vector<const Record *> SubPreds =
1681 Rec->getValueAsListOfDefs(FieldName: "Predicates");
1682 return all_of(Range&: SubPreds, P: hasMCSchedPredicate);
1683 }
1684
1685 return false;
1686}
1687static bool hasMCSchedPredicates(const CodeGenSchedTransition &T) {
1688 return all_of(Range: T.PredTerm, P: hasMCSchedPredicate);
1689}
1690
1691static void collectVariantClasses(const CodeGenSchedModels &SchedModels,
1692 IdxVec &VariantClasses,
1693 bool OnlyExpandMCInstPredicates) {
1694 for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
1695 // Ignore non-variant scheduling classes.
1696 if (SC.Transitions.empty())
1697 continue;
1698
1699 if (OnlyExpandMCInstPredicates) {
1700 // Ignore this variant scheduling class no transitions use any meaningful
1701 // MCSchedPredicate definitions.
1702 if (llvm::none_of(Range: SC.Transitions, P: hasMCSchedPredicates))
1703 continue;
1704 }
1705
1706 VariantClasses.push_back(x: SC.Index);
1707 }
1708}
1709
1710static void collectProcessorIndices(const CodeGenSchedClass &SC,
1711 IdxVec &ProcIndices) {
1712 // A variant scheduling class may define transitions for multiple
1713 // processors. This function identifies wich processors are associated with
1714 // transition rules specified by variant class `SC`.
1715 for (const CodeGenSchedTransition &T : SC.Transitions) {
1716 IdxVec PI;
1717 std::set_union(first1: &T.ProcIndex, last1: &T.ProcIndex + 1, first2: ProcIndices.begin(),
1718 last2: ProcIndices.end(), result: std::back_inserter(x&: PI));
1719 ProcIndices = std::move(PI);
1720 }
1721}
1722
1723static bool isAlwaysTrue(const CodeGenSchedTransition &T) {
1724 return llvm::all_of(Range: T.PredTerm, P: isTruePredicate);
1725}
1726
1727void SubtargetEmitter::emitSchedModelHelpersImpl(
1728 raw_ostream &OS, bool OnlyExpandMCInstPredicates) {
1729 IdxVec VariantClasses;
1730 collectVariantClasses(SchedModels, VariantClasses,
1731 OnlyExpandMCInstPredicates);
1732
1733 if (VariantClasses.empty()) {
1734 emitSchedModelHelperEpilogue(OS, ShouldReturnZero: OnlyExpandMCInstPredicates);
1735 return;
1736 }
1737
1738 // Construct a switch statement where the condition is a check on the
1739 // scheduling class identifier. There is a `case` for every variant class
1740 // defined by the processor models of this target.
1741 // Each `case` implements a number of rules to resolve (i.e. to transition
1742 // from) a variant scheduling class to another scheduling class. Rules are
1743 // described by instances of CodeGenSchedTransition. Note that transitions may
1744 // not be valid for all processors.
1745 OS << " switch (SchedClass) {\n";
1746 for (unsigned VC : VariantClasses) {
1747 IdxVec ProcIndices;
1748 const CodeGenSchedClass &SC = SchedModels.getSchedClass(Idx: VC);
1749 collectProcessorIndices(SC, ProcIndices);
1750
1751 OS << " case " << VC << ": // " << SC.Name << '\n';
1752
1753 PredicateExpander PE(Target);
1754 PE.setByRef(false);
1755 PE.setExpandForMC(OnlyExpandMCInstPredicates);
1756 for (unsigned PI : ProcIndices) {
1757 OS << " ";
1758
1759 // Emit a guard on the processor ID.
1760 if (PI != 0) {
1761 OS << (OnlyExpandMCInstPredicates
1762 ? "if (CPUID == "
1763 : "if (SchedModel->getProcessorID() == ");
1764 OS << PI << ") ";
1765 OS << "{ // " << SchedModels.procModels()[PI].ModelName << '\n';
1766 }
1767
1768 // Now emit transitions associated with processor PI.
1769 const CodeGenSchedTransition *FinalT = nullptr;
1770 for (const CodeGenSchedTransition &T : SC.Transitions) {
1771 if (PI != 0 && T.ProcIndex != PI)
1772 continue;
1773
1774 // Emit only transitions based on MCSchedPredicate, if it's the case.
1775 // At least the transition specified by NoSchedPred is emitted,
1776 // which becomes the default transition for those variants otherwise
1777 // not based on MCSchedPredicate.
1778 // FIXME: preferably, llvm-mca should instead assume a reasonable
1779 // default when a variant transition is not based on MCSchedPredicate
1780 // for a given processor.
1781 if (OnlyExpandMCInstPredicates && !hasMCSchedPredicates(T))
1782 continue;
1783
1784 // If transition is folded to 'return X' it should be the last one.
1785 if (isAlwaysTrue(T)) {
1786 FinalT = &T;
1787 continue;
1788 }
1789 PE.getIndent() = 3;
1790 emitPredicates(T, SC: SchedModels.getSchedClass(Idx: T.ToClassIdx), PE, OS);
1791 }
1792 if (FinalT)
1793 emitPredicates(T: *FinalT, SC: SchedModels.getSchedClass(Idx: FinalT->ToClassIdx),
1794 PE, OS);
1795
1796 OS << " }\n";
1797
1798 if (PI == 0)
1799 break;
1800 }
1801
1802 if (SC.isInferred())
1803 OS << " return " << SC.Index << ";\n";
1804 OS << " break;\n";
1805 }
1806
1807 OS << " };\n";
1808
1809 emitSchedModelHelperEpilogue(OS, ShouldReturnZero: OnlyExpandMCInstPredicates);
1810}
1811
1812void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName,
1813 raw_ostream &OS) {
1814 OS << "unsigned " << ClassName
1815 << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
1816 << " const TargetSchedModel *SchedModel) const {\n";
1817
1818 // Emit the predicate prolog code.
1819 emitPredicateProlog(Records, OS);
1820
1821 // Emit target predicates.
1822 emitSchedModelHelpersImpl(OS);
1823
1824 OS << "} // " << ClassName << "::resolveSchedClass\n\n";
1825
1826 OS << "unsigned " << ClassName
1827 << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
1828 << " const MCInstrInfo *MCII, unsigned CPUID) const {\n"
1829 << " return " << Target << "_MC"
1830 << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n"
1831 << "} // " << ClassName << "::resolveVariantSchedClass\n\n";
1832
1833 STIPredicateExpander PE(Target, /*Indent=*/0);
1834 PE.setClassPrefix(ClassName);
1835 PE.setExpandDefinition(true);
1836 PE.setByRef(false);
1837
1838 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
1839 PE.expandSTIPredicate(OS, Fn);
1840}
1841
1842void SubtargetEmitter::emitHwModeCheck(const std::string &ClassName,
1843 raw_ostream &OS, bool IsMC) {
1844 const CodeGenHwModes &CGH = TGT.getHwModes();
1845 assert(CGH.getNumModeIds() > 0);
1846 if (CGH.getNumModeIds() == 1)
1847 return;
1848
1849 // Collect all HwModes and related features defined in the TD files,
1850 // and store them as a bit set.
1851 unsigned ValueTypeModes = 0;
1852 unsigned RegInfoModes = 0;
1853 unsigned EncodingInfoModes = 0;
1854 for (const auto &MS : CGH.getHwModeSelects()) {
1855 for (const HwModeSelect::PairType &P : MS.second.Items) {
1856 if (P.first == DefaultMode)
1857 continue;
1858 if (P.second->isSubClassOf(Name: "ValueType")) {
1859 ValueTypeModes |= (1 << (P.first - 1));
1860 } else if (P.second->isSubClassOf(Name: "RegInfo") ||
1861 P.second->isSubClassOf(Name: "Register") ||
1862 P.second->isSubClassOf(Name: "SubRegRange") ||
1863 P.second->isSubClassOf(Name: "RegisterClassLike")) {
1864 RegInfoModes |= (1 << (P.first - 1));
1865 } else if (P.second->isSubClassOf(Name: "InstructionEncoding")) {
1866 EncodingInfoModes |= (1 << (P.first - 1));
1867 }
1868 }
1869 }
1870
1871 // Start emitting for getHwModeSet().
1872 OS << "unsigned " << ClassName << "::getHwModeSet() const {\n";
1873 if (IsMC) {
1874 OS << " [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();\n";
1875 } else {
1876 const ArrayRef<const Record *> &Prologs =
1877 Records.getAllDerivedDefinitions(ClassName: "HwModePredicateProlog");
1878 if (!Prologs.empty()) {
1879 for (const Record *P : Prologs)
1880 OS << P->getValueAsString(FieldName: "Code") << '\n';
1881 } else {
1882 // Works for most targets.
1883 OS << " [[maybe_unused]] const auto *Subtarget =\n"
1884 << " static_cast<const " << Target << "Subtarget *>(this);\n";
1885 }
1886 }
1887 OS << " // Collect HwModes and store them as a bit set.\n";
1888 OS << " unsigned Modes = 0;\n";
1889 for (unsigned M = 1, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
1890 const HwMode &HM = CGH.getMode(Id: M);
1891 OS << " if (";
1892 if (IsMC)
1893 SubtargetFeatureInfo::emitMCPredicateCheck(OS, TargetName: Target, Predicates: HM.Predicates);
1894 else
1895 SubtargetFeatureInfo::emitPredicateCheck(OS, Predicates: HM.Predicates);
1896 OS << ") Modes |= (1 << " << (M - 1) << ");\n";
1897 }
1898 OS << " return Modes;\n}\n";
1899 // End emitting for getHwModeSet().
1900
1901 auto HandlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) {
1902 OS << " case HwMode_" << ModeType << ":\n";
1903 if (ModeInBitSet == 0) {
1904 OS << " // No HwMode for " << ModeType << ".\n"
1905 << " return 0;\n";
1906 } else {
1907 OS << " Modes &= " << ModeInBitSet << ";\n"
1908 << " if (!Modes)\n return Modes;\n"
1909 << " if (!llvm::has_single_bit<unsigned>(Modes))\n"
1910 << " llvm_unreachable(\"Two or more HwModes for " << ModeType
1911 << " were found!\");\n"
1912 << " return llvm::countr_zero(Modes) + 1;\n";
1913 }
1914 };
1915
1916 // Start emitting for getHwMode().
1917 OS << "unsigned " << ClassName
1918 << "::getHwMode(enum HwModeType type) const {\n";
1919 OS << " unsigned Modes = getHwModeSet();\n\n";
1920 OS << " if (!Modes)\n return Modes;\n\n";
1921 OS << " switch (type) {\n";
1922 OS << " case HwMode_Default:\n return llvm::countr_zero(Modes) + 1;\n";
1923 HandlePerMode("ValueType", ValueTypeModes);
1924 HandlePerMode("RegInfo", RegInfoModes);
1925 HandlePerMode("EncodingInfo", EncodingInfoModes);
1926 OS << " }\n";
1927 OS << " llvm_unreachable(\"unexpected HwModeType\");\n"
1928 << " return 0; // should not get here\n}\n";
1929 // End emitting for getHwMode().
1930}
1931
1932void SubtargetEmitter::emitGetMacroFusions(const std::string &ClassName,
1933 raw_ostream &OS) {
1934 if (!TGT.hasMacroFusion())
1935 return;
1936
1937 OS << "std::vector<MacroFusionPredTy> " << ClassName
1938 << "::getMacroFusions() const {\n";
1939 OS.indent(NumSpaces: 2) << "std::vector<MacroFusionPredTy> Fusions;\n";
1940 for (auto *Fusion : TGT.getMacroFusions()) {
1941 std::string Name = Fusion->getNameInitAsString();
1942 OS.indent(NumSpaces: 2) << "if (hasFeature(" << Target << "::" << Name
1943 << ")) Fusions.push_back(llvm::is" << Name << ");\n";
1944 }
1945
1946 OS.indent(NumSpaces: 2) << "return Fusions;\n";
1947 OS << "}\n";
1948}
1949
1950// Produces a subtarget specific function for parsing
1951// the subtarget features string.
1952void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) {
1953 ArrayRef<const Record *> Features =
1954 Records.getAllDerivedDefinitions(ClassName: "SubtargetFeature");
1955
1956 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1957 << "// subtarget options.\n"
1958 << "void llvm::";
1959 OS << Target;
1960 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, "
1961 << "StringRef FS) {\n"
1962 << " LLVM_DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
1963 << " LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n"
1964 << " LLVM_DEBUG(dbgs() << \"\\nTuneCPU:\" << TuneCPU << \"\\n\\n\");\n";
1965
1966 if (Features.empty()) {
1967 OS << "}\n";
1968 return;
1969 }
1970
1971 if (Target == "AArch64")
1972 OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
1973 << " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
1974
1975 OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
1976 << " const FeatureBitset &Bits = getFeatureBits();\n";
1977
1978 for (const Record *R : Features) {
1979 // Next record
1980 StringRef Instance = R->getName();
1981 StringRef Value = R->getValueAsString(FieldName: "Value");
1982 StringRef FieldName = R->getValueAsString(FieldName: "FieldName");
1983
1984 if (Value == "true" || Value == "false")
1985 OS << " if (Bits[" << Target << "::" << Instance << "]) " << FieldName
1986 << " = " << Value << ";\n";
1987 else
1988 OS << " if (Bits[" << Target << "::" << Instance << "] && " << FieldName
1989 << " < " << Value << ") " << FieldName << " = " << Value << ";\n";
1990 }
1991
1992 OS << "}\n";
1993}
1994
1995void SubtargetEmitter::emitInlineFeatures(const std::string &ClassName,
1996 raw_ostream &OS, StringRef Behavior) {
1997 std::vector<const Record *> FeatureList =
1998 Records.getAllDerivedDefinitions(ClassName: "SubtargetFeature");
1999 llvm::sort(C&: FeatureList, Comp: LessRecordFieldFieldName());
2000
2001 OS << "const FeatureBitset &" << ClassName << "::get" << Behavior
2002 << "Features() const {\n"
2003 << " static constexpr FeatureBitset Features = {\n";
2004
2005 for (const Record *Feature : FeatureList)
2006 if (Behavior == Feature->getValueAsDef(FieldName: "InlineBehavior")->getName())
2007 OS << Target << "::" << Feature->getName() << ",\n";
2008
2009 OS << " };\n"
2010 << " return Features;\n"
2011 << "}\n\n";
2012}
2013
2014void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
2015 {
2016 NamespaceEmitter NS(OS, (Target + Twine("_MC")).str());
2017 OS << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
2018 << " const MCInst *MI, const MCInstrInfo *MCII, "
2019 << "const MCSubtargetInfo &STI, unsigned CPUID) {\n";
2020 emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ OnlyExpandMCInstPredicates: true);
2021 OS << "}\n";
2022 }
2023
2024 OS << "struct " << Target
2025 << "GenMCSubtargetInfo : public MCSubtargetInfo {\n";
2026 OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT,\n"
2027 << " StringRef CPU, StringRef TuneCPU, StringRef FS,\n"
2028 << " ArrayRef<StringRef> PN,\n"
2029 << " ArrayRef<SubtargetFeatureKV> PF,\n"
2030 << " ArrayRef<SubtargetSubTypeKV> PD,\n"
2031 << " const MCWriteProcResEntry *WPR,\n"
2032 << " const MCWriteLatencyEntry *WL,\n"
2033 << " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
2034 << " const unsigned *OC, const unsigned *FP) :\n"
2035 << " MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,\n"
2036 << " WPR, WL, RA, IS, OC, FP) { }\n\n"
2037 << " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
2038 << " const MCInst *MI, const MCInstrInfo *MCII,\n"
2039 << " unsigned CPUID) const final {\n"
2040 << " return " << Target << "_MC"
2041 << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n";
2042 OS << " }\n";
2043 if (TGT.getHwModes().getNumModeIds() > 1) {
2044 OS << " unsigned getHwModeSet() const final;\n";
2045 OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
2046 "final;\n";
2047 }
2048 if (Target == "AArch64")
2049 OS << " bool isCPUStringValid(StringRef CPU) const final {\n"
2050 << " CPU = AArch64::resolveCPUAlias(CPU);\n"
2051 << " return MCSubtargetInfo::isCPUStringValid(CPU);\n"
2052 << " }\n";
2053 OS << "};\n";
2054 emitHwModeCheck(ClassName: Target + "GenMCSubtargetInfo", OS, /*IsMC=*/true);
2055}
2056
2057void SubtargetEmitter::emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS) {
2058 STIPredicateExpander PE(Target, /*Indent=*/0);
2059
2060 {
2061 IfDefEmitter IfDefDecls(OS, "GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS");
2062 PE.setExpandForMC(true);
2063 PE.setByRef(true);
2064 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
2065 PE.expandSTIPredicate(OS, Fn);
2066 }
2067
2068 IfDefEmitter IfDefDefs(OS, "GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS");
2069 std::string ClassPrefix = Target + "MCInstrAnalysis";
2070 PE.setExpandDefinition(true);
2071 PE.setClassPrefix(ClassPrefix);
2072 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
2073 PE.expandSTIPredicate(OS, Fn);
2074}
2075
2076FeatureMapTy SubtargetEmitter::emitEnums(raw_ostream &OS) {
2077 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_ENUM");
2078 NamespaceEmitter NS(OS, "llvm");
2079 return enumeration(OS);
2080}
2081
2082std::tuple<unsigned, unsigned, unsigned>
2083SubtargetEmitter::emitMCDesc(raw_ostream &OS, const FeatureMapTy &FeatureMap) {
2084 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_MC_DESC");
2085 if (Target == "AArch64")
2086 OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
2087 NamespaceEmitter LlvmNS(OS, "llvm");
2088
2089 unsigned NumFeatures = featureKeyValues(OS, FeatureMap);
2090 OS << "\n";
2091 emitSchedModel(OS);
2092 OS << "\n";
2093 unsigned NumProcs = cpuKeyValues(OS, FeatureMap);
2094 OS << "\n";
2095 unsigned NumNames = cpuNames(OS);
2096 OS << "\n";
2097
2098 // MCInstrInfo initialization routine.
2099 emitGenMCSubtargetInfo(OS);
2100
2101 OS << "\nstatic inline MCSubtargetInfo *create" << Target
2102 << "MCSubtargetInfoImpl("
2103 << "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n";
2104 if (Target == "AArch64")
2105 OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
2106 << " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
2107 OS << " return new " << Target
2108 << "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";
2109 if (NumNames)
2110 OS << Target << "Names, ";
2111 else
2112 OS << "{}, ";
2113 if (NumFeatures)
2114 OS << Target << "FeatureKV, ";
2115 else
2116 OS << "{}, ";
2117 if (NumProcs)
2118 OS << Target << "SubTypeKV, ";
2119 else
2120 OS << "{}, ";
2121 OS << '\n';
2122 OS.indent(NumSpaces: 22);
2123 OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "
2124 << Target << "ReadAdvanceTable, ";
2125 OS << '\n';
2126 OS.indent(NumSpaces: 22);
2127 if (SchedModels.hasItineraries()) {
2128 OS << Target << "Stages, " << Target << "OperandCycles, " << Target
2129 << "ForwardingPaths";
2130 } else {
2131 OS << "nullptr, nullptr, nullptr";
2132 }
2133 OS << ");\n}\n\n";
2134 return {NumNames, NumFeatures, NumProcs};
2135}
2136
2137void SubtargetEmitter::emitTargetDesc(raw_ostream &OS) {
2138 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_TARGET_DESC");
2139
2140 OS << "#include \"llvm/ADT/BitmaskEnum.h\"\n";
2141 OS << "#include \"llvm/Support/Debug.h\"\n";
2142 OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
2143 if (Target == "AArch64")
2144 OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
2145 parseFeaturesFunction(OS);
2146}
2147
2148void SubtargetEmitter::emitHeader(raw_ostream &OS) {
2149 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
2150 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_HEADER");
2151 NamespaceEmitter LLVMNS(OS, "llvm");
2152
2153 std::string ClassName = Target + "GenSubtargetInfo";
2154 OS << "class DFAPacketizer;\n";
2155 {
2156 NamespaceEmitter MCNS(OS, (Target + Twine("_MC")).str());
2157 OS << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
2158 << " const MCInst *MI, const MCInstrInfo *MCII, "
2159 << "const MCSubtargetInfo &STI, unsigned CPUID);\n";
2160 }
2161 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
2162 << " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
2163 << "StringRef TuneCPU, StringRef FS);\n"
2164 << "public:\n"
2165 << " unsigned resolveSchedClass(unsigned SchedClass, "
2166 << " const MachineInstr *DefMI,"
2167 << " const TargetSchedModel *SchedModel) const final;\n"
2168 << " unsigned resolveVariantSchedClass(unsigned SchedClass,"
2169 << " const MCInst *MI, const MCInstrInfo *MCII,"
2170 << " unsigned CPUID) const final;\n"
2171 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
2172 << " const;\n";
2173
2174 const CodeGenHwModes &CGH = TGT.getHwModes();
2175 if (CGH.getNumModeIds() > 1) {
2176 OS << " enum class " << Target << "HwModeBits : unsigned {\n";
2177 for (unsigned M = 0, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
2178 StringRef ModeName = CGH.getModeName(Id: M, /*IncludeDefault=*/true);
2179 OS << " " << ModeName << " = ";
2180 if (M == 0)
2181 OS << "0";
2182 else
2183 OS << "(1 << " << (M - 1) << ")";
2184 OS << ",\n";
2185 if (M == NumModes - 1) {
2186 OS << "\n";
2187 OS << " LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/" << ModeName
2188 << "),\n";
2189 }
2190 }
2191 OS << " };\n";
2192
2193 OS << " unsigned getHwModeSet() const final;\n";
2194 OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
2195 "final;\n";
2196 }
2197 if (TGT.hasMacroFusion())
2198 OS << " std::vector<MacroFusionPredTy> getMacroFusions() const "
2199 "final;\n";
2200
2201 OS << " const FeatureBitset &getInlineIgnoreFeatures() const override;\n";
2202 OS << " const FeatureBitset &getInlineInverseFeatures() const override;\n";
2203
2204 STIPredicateExpander PE(Target);
2205 PE.setByRef(false);
2206 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
2207 PE.expandSTIPredicate(OS, Fn);
2208 OS << "};\n";
2209}
2210
2211void SubtargetEmitter::emitCtor(raw_ostream &OS, unsigned NumNames,
2212 unsigned NumFeatures, unsigned NumProcs) {
2213 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_CTOR");
2214 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n";
2215
2216 NamespaceEmitter LLVMNS(OS, "llvm");
2217 OS << "extern const llvm::StringRef " << Target << "Names[];\n";
2218 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
2219 OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n";
2220 OS << "extern const llvm::MCWriteProcResEntry " << Target
2221 << "WriteProcResTable[];\n";
2222 OS << "extern const llvm::MCWriteLatencyEntry " << Target
2223 << "WriteLatencyTable[];\n";
2224 OS << "extern const llvm::MCReadAdvanceEntry " << Target
2225 << "ReadAdvanceTable[];\n";
2226
2227 if (SchedModels.hasItineraries()) {
2228 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
2229 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
2230 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
2231 }
2232
2233 std::string ClassName = Target + "GenSubtargetInfo";
2234 OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
2235 << "StringRef TuneCPU, StringRef FS)\n";
2236
2237 if (Target == "AArch64")
2238 OS << " : TargetSubtargetInfo(TT, AArch64::resolveCPUAlias(CPU),\n"
2239 << " AArch64::resolveCPUAlias(TuneCPU), FS, ";
2240 else
2241 OS << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
2242 if (NumNames)
2243 OS << "ArrayRef(" << Target << "Names, " << NumNames << "), ";
2244 else
2245 OS << "{}, ";
2246 if (NumFeatures)
2247 OS << "ArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
2248 else
2249 OS << "{}, ";
2250 if (NumProcs)
2251 OS << "ArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
2252 else
2253 OS << "{}, ";
2254 OS << '\n';
2255 OS.indent(NumSpaces: 24);
2256 OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "
2257 << Target << "ReadAdvanceTable, ";
2258 OS << '\n';
2259 OS.indent(NumSpaces: 24);
2260 if (SchedModels.hasItineraries()) {
2261 OS << Target << "Stages, " << Target << "OperandCycles, " << Target
2262 << "ForwardingPaths";
2263 } else {
2264 OS << "nullptr, nullptr, nullptr";
2265 }
2266 OS << ") {}\n\n";
2267
2268 emitSchedModelHelpers(ClassName, OS);
2269 emitHwModeCheck(ClassName, OS, /*IsMC=*/false);
2270 emitGetMacroFusions(ClassName, OS);
2271 emitInlineFeatures(ClassName, OS, Behavior: "InlineIgnore");
2272 emitInlineFeatures(ClassName, OS, Behavior: "InlineInverse");
2273}
2274
2275//
2276// SubtargetEmitter::run - Main subtarget enumeration emitter.
2277//
2278void SubtargetEmitter::run(raw_ostream &OS) {
2279 emitSourceFileHeader(Desc: "Subtarget Enumeration Source Fragment", OS);
2280
2281 auto FeatureMap = emitEnums(OS);
2282 emitSubtargetInfoMacroCalls(OS);
2283 auto [NumNames, NumFeatures, NumProcs] = emitMCDesc(OS, FeatureMap);
2284 emitTargetDesc(OS);
2285 emitHeader(OS);
2286 emitCtor(OS, NumNames, NumFeatures, NumProcs);
2287 emitMcInstrAnalysisPredicateFunctions(OS);
2288}
2289
2290static TableGen::Emitter::OptClass<SubtargetEmitter>
2291 X("gen-subtarget", "Generate subtarget enumerations");
2292