1//========- utils/TableGen/X86InstrMappingEmitter.cpp - X86 backend-*- C++ -*-//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This tablegen backend is responsible for emitting the X86 backend
10/// instruction mapping.
11///
12//===----------------------------------------------------------------------===//
13
14#include "Common/CodeGenInstruction.h"
15#include "Common/CodeGenTarget.h"
16#include "X86RecognizableInstr.h"
17#include "llvm/TableGen/Error.h"
18#include "llvm/TableGen/Record.h"
19#include "llvm/TableGen/TableGenBackend.h"
20#include <map>
21#include <set>
22
23using namespace llvm;
24using namespace X86Disassembler;
25
26namespace {
27
28class X86InstrMappingEmitter {
29 const RecordKeeper &Records;
30 const CodeGenTarget Target;
31
32 // Hold all pontentially compressible EVEX instructions
33 std::vector<const CodeGenInstruction *> PreCompressionInsts;
34 // Hold all compressed instructions. Divided into groups with same opcodes
35 // to make the search more efficient
36 std::map<uint64_t, std::vector<const CodeGenInstruction *>> CompressedInsts;
37
38 using Entry =
39 std::pair<const CodeGenInstruction *, const CodeGenInstruction *>;
40 using PredicateInstMap =
41 std::map<StringRef, std::vector<const CodeGenInstruction *>>;
42
43 // Hold all compressed instructions that need to check predicate
44 PredicateInstMap PredicateInsts;
45
46public:
47 X86InstrMappingEmitter(const RecordKeeper &R) : Records(R), Target(R) {}
48
49 // run - Output X86 EVEX compression tables.
50 void run(raw_ostream &OS);
51
52private:
53 void emitCompressEVEXTable(ArrayRef<const CodeGenInstruction *> Insts,
54 raw_ostream &OS);
55 void emitNFTransformTable(ArrayRef<const CodeGenInstruction *> Insts,
56 raw_ostream &OS);
57 void emitND2NonNDTable(ArrayRef<const CodeGenInstruction *> Insts,
58 raw_ostream &OS);
59 void emitSSE2AVXTable(ArrayRef<const CodeGenInstruction *> Insts,
60 raw_ostream &OS);
61
62 // Prints the definition of class X86TableEntry.
63 void printClassDef(raw_ostream &OS);
64 // Prints the given table as a C++ array of type X86TableEntry under the guard
65 // \p Macro.
66 void printTable(ArrayRef<Entry> Table, StringRef Name, StringRef Macro,
67 raw_ostream &OS);
68};
69} // namespace
70
71void X86InstrMappingEmitter::printClassDef(raw_ostream &OS) {
72 OS << "struct X86TableEntry {\n"
73 " uint16_t OldOpc;\n"
74 " uint16_t NewOpc;\n"
75 " bool operator<(const X86TableEntry &RHS) const {\n"
76 " return OldOpc < RHS.OldOpc;\n"
77 " }"
78 " friend bool operator<(const X86TableEntry &TE, unsigned Opc) {\n"
79 " return TE.OldOpc < Opc;\n"
80 " }\n"
81 "};";
82
83 OS << "\n\n";
84}
85
86static void printMacroBegin(StringRef Macro, raw_ostream &OS) {
87 OS << "\n#ifdef " << Macro << "\n";
88}
89
90static void printMacroEnd(StringRef Macro, raw_ostream &OS) {
91 OS << "#endif // " << Macro << "\n\n";
92}
93
94void X86InstrMappingEmitter::printTable(ArrayRef<Entry> Table, StringRef Name,
95 StringRef Macro, raw_ostream &OS) {
96 printMacroBegin(Macro, OS);
97
98 OS << "static const X86TableEntry " << Name << "[] = {\n";
99
100 // Print all entries added to the table
101 for (const auto &Pair : Table)
102 OS << " { X86::" << Pair.first->getName()
103 << ", X86::" << Pair.second->getName() << " },\n";
104
105 OS << "};\n\n";
106
107 printMacroEnd(Macro, OS);
108}
109
110namespace {
111class IsMatch {
112 const CodeGenInstruction *OldInst;
113
114public:
115 IsMatch(const CodeGenInstruction *OldInst) : OldInst(OldInst) {}
116
117 bool operator()(const CodeGenInstruction *NewInst) {
118 RecognizableInstrBase NewRI(*NewInst);
119 RecognizableInstrBase OldRI(*OldInst);
120
121 // Return false if any of the following fields of does not match.
122 if (std::tuple(OldRI.IsCodeGenOnly, OldRI.OpMap, NewRI.OpPrefix,
123 OldRI.HasVEX_4V, OldRI.HasVEX_L, OldRI.HasREX_W,
124 OldRI.Form) !=
125 std::tuple(NewRI.IsCodeGenOnly, NewRI.OpMap, OldRI.OpPrefix,
126 NewRI.HasVEX_4V, NewRI.HasVEX_L, NewRI.HasREX_W, NewRI.Form))
127 return false;
128
129 for (unsigned I = 0, E = OldInst->Operands.size(); I < E; ++I) {
130 const Record *OldOpRec = OldInst->Operands[I].Rec;
131 const Record *NewOpRec = NewInst->Operands[I].Rec;
132
133 if (OldOpRec == NewOpRec)
134 continue;
135
136 if (isRegisterOperand(Rec: OldOpRec) && isRegisterOperand(Rec: NewOpRec)) {
137 if (getRegOperandSize(RegRec: OldOpRec) != getRegOperandSize(RegRec: NewOpRec))
138 return false;
139 } else if (isMemoryOperand(Rec: OldOpRec) && isMemoryOperand(Rec: NewOpRec)) {
140 if (getMemOperandSize(MemRec: OldOpRec) != getMemOperandSize(MemRec: NewOpRec))
141 return false;
142 } else if (isImmediateOperand(Rec: OldOpRec) && isImmediateOperand(Rec: NewOpRec)) {
143 if (OldOpRec->getValueAsDef(FieldName: "Type") != NewOpRec->getValueAsDef(FieldName: "Type"))
144 return false;
145 }
146 }
147
148 return true;
149 }
150};
151} // namespace
152
153static bool isInteresting(const Record *Rec) {
154 // _REV instruction should not appear before encoding optimization
155 return Rec->isSubClassOf(Name: "X86Inst") &&
156 !Rec->getValueAsBit(FieldName: "isAsmParserOnly") &&
157 !Rec->getName().ends_with(Suffix: "_REV");
158}
159
160void X86InstrMappingEmitter::emitCompressEVEXTable(
161 ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
162
163 const std::map<StringRef, StringRef> ManualMap = {
164#define ENTRY(OLD, NEW) {#OLD, #NEW},
165#include "X86ManualInstrMapping.def"
166 };
167 const std::set<StringRef> NoCompressSet = {
168#define NOCOMP(INSN) #INSN,
169#include "X86ManualInstrMapping.def"
170 };
171
172 for (const CodeGenInstruction *Inst : Insts) {
173 const Record *Rec = Inst->TheDef;
174 StringRef Name = Rec->getName();
175 if (!isInteresting(Rec))
176 continue;
177
178 // Promoted legacy instruction is in EVEX space, and has REX2-encoding
179 // alternative. It's added due to HW design and never emitted by compiler.
180 if (byteFromBitsInit(B: Rec->getValueAsBitsInit(FieldName: "OpMapBits")) ==
181 X86Local::T_MAP4 &&
182 byteFromBitsInit(B: Rec->getValueAsBitsInit(FieldName: "explicitOpPrefixBits")) ==
183 X86Local::ExplicitEVEX)
184 continue;
185
186 if (NoCompressSet.find(x: Name) != NoCompressSet.end())
187 continue;
188
189 RecognizableInstrBase RI(*Inst);
190
191 bool IsND = RI.OpMap == X86Local::T_MAP4 && RI.HasEVEX_B && RI.HasVEX_4V;
192 bool IsSETZUCCm = Name == "SETZUCCm";
193 // Add VEX encoded instructions to one of CompressedInsts vectors according
194 // to it's opcode.
195 if (RI.Encoding == X86Local::VEX)
196 CompressedInsts[RI.Opcode].push_back(x: Inst);
197 // Add relevant EVEX encoded instructions to PreCompressionInsts.
198 // Exclude instructions with:
199 // - EVEX_K (mask register)
200 // - EVEX_L2 (512-bit vectors)
201 // - EVEX_NF (No Flags) - VEX/legacy encodings don't support NF
202 // - EVEX_B (broadcast/rounding) unless it's NDD or SETZUCCm
203 else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 &&
204 !RI.HasEVEX_NF && (!RI.HasEVEX_B || IsND || IsSETZUCCm))
205 PreCompressionInsts.push_back(x: Inst);
206 }
207
208 std::vector<Entry> Table;
209 for (const CodeGenInstruction *Inst : PreCompressionInsts) {
210 const Record *Rec = Inst->TheDef;
211 uint8_t Opcode = byteFromBitsInit(B: Rec->getValueAsBitsInit(FieldName: "Opcode"));
212 StringRef Name = Rec->getName();
213 const CodeGenInstruction *NewInst = nullptr;
214 if (ManualMap.find(x: Name) != ManualMap.end()) {
215 const Record *NewRec = Records.getDef(Name: ManualMap.at(k: Rec->getName()));
216 assert(NewRec && "Instruction not found!");
217 NewInst = &Target.getInstruction(InstRec: NewRec);
218 } else if (Name.ends_with(Suffix: "_EVEX")) {
219 if (const auto *NewRec = Records.getDef(Name: Name.drop_back(N: 5)))
220 NewInst = &Target.getInstruction(InstRec: NewRec);
221 } else if (Name.ends_with(Suffix: "_ND"))
222 // Leave it to ND2NONND table.
223 continue;
224 else {
225 // For each pre-compression instruction look for a match in the
226 // appropriate vector (instructions with the same opcode) using function
227 // object IsMatch.
228 const auto &Insts = CompressedInsts[Opcode];
229 auto Match = llvm::find_if(Range: Insts, P: IsMatch(Inst));
230 if (Match != Insts.end())
231 NewInst = *Match;
232 }
233
234 if (!NewInst)
235 continue;
236
237 Table.emplace_back(args&: Inst, args&: NewInst);
238 auto Predicates = NewInst->TheDef->getValueAsListOfDefs(FieldName: "Predicates");
239 auto It = llvm::find_if(Range&: Predicates, P: [](const Record *R) {
240 StringRef Name = R->getName();
241 return Name == "HasAVXNECONVERT" || Name == "HasAVXVNNI" ||
242 Name == "HasAVXIFMA" || Name == "HasAVXVNNIINT8" ||
243 Name == "HasAVXVNNIINT16";
244 });
245 if (It != Predicates.end())
246 PredicateInsts[(*It)->getValueAsString(FieldName: "CondString")].push_back(x: NewInst);
247 }
248
249 StringRef Macro = "GET_X86_COMPRESS_EVEX_TABLE";
250 printTable(Table, Name: "X86CompressEVEXTable", Macro, OS);
251
252 // Prints function which checks target feature for compressed instructions.
253 printMacroBegin(Macro, OS);
254 OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget "
255 "*Subtarget) {\n"
256 << " switch (Opc) {\n"
257 << " default: return true;\n";
258 for (const auto &[Key, Val] : PredicateInsts) {
259 for (const auto &Inst : Val)
260 OS << " case X86::" << Inst->getName() << ":\n";
261 OS << " return " << Key << ";\n";
262 }
263 OS << " }\n";
264 OS << "}\n\n";
265 printMacroEnd(Macro, OS);
266}
267
268void X86InstrMappingEmitter::emitNFTransformTable(
269 ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
270 std::vector<Entry> Table;
271 for (const CodeGenInstruction *Inst : Insts) {
272 const Record *Rec = Inst->TheDef;
273 if (!isInteresting(Rec))
274 continue;
275 StringRef Name = Rec->getName();
276 if (Name.contains(Other: "_NF"))
277 continue;
278
279 if (auto *NewRec = Name.consume_back(Suffix: "_ND")
280 ? Records.getDef(Name: Name.str() + "_NF_ND")
281 : Records.getDef(Name: Name.str() + "_NF")) {
282#ifndef NDEBUG
283 auto ClobberEFLAGS = [](const Record *R) {
284 return llvm::any_of(
285 R->getValueAsListOfDefs("Defs"),
286 [](const Record *Def) { return Def->getName() == "EFLAGS"; });
287 };
288 if (ClobberEFLAGS(NewRec))
289 report_fatal_error("EFLAGS should not be clobbered by " +
290 NewRec->getName());
291 if (!ClobberEFLAGS(Rec))
292 report_fatal_error("EFLAGS should be clobbered by " + Rec->getName());
293#endif
294 Table.emplace_back(args&: Inst, args: &Target.getInstruction(InstRec: NewRec));
295 }
296 }
297 printTable(Table, Name: "X86NFTransformTable", Macro: "GET_X86_NF_TRANSFORM_TABLE", OS);
298}
299
300void X86InstrMappingEmitter::emitND2NonNDTable(
301 ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
302
303 const std::map<StringRef, StringRef> ManualMap = {
304#define ENTRY_ND(OLD, NEW) {#OLD, #NEW},
305#include "X86ManualInstrMapping.def"
306 };
307 const std::set<StringRef> NoCompressSet = {
308#define NOCOMP_ND(INSN) #INSN,
309#include "X86ManualInstrMapping.def"
310 };
311
312 std::vector<Entry> Table;
313 for (const CodeGenInstruction *Inst : Insts) {
314 const Record *Rec = Inst->TheDef;
315 StringRef Name = Rec->getName();
316 if (!isInteresting(Rec) || NoCompressSet.find(x: Name) != NoCompressSet.end())
317 continue;
318 if (ManualMap.find(x: Name) != ManualMap.end()) {
319 const auto *NewRec = Records.getDef(Name: ManualMap.at(k: Rec->getName()));
320 assert(NewRec && "Instruction not found!");
321 auto &NewInst = Target.getInstruction(InstRec: NewRec);
322 Table.emplace_back(args&: Inst, args: &NewInst);
323 continue;
324 }
325
326 if (!Name.ends_with(Suffix: "_ND"))
327 continue;
328 const auto *NewRec = Records.getDef(Name: Name.drop_back(N: 3));
329 if (!NewRec)
330 continue;
331 const auto &NewInst = Target.getInstruction(InstRec: NewRec);
332 if (isRegisterOperand(Rec: NewInst.Operands[0].Rec))
333 Table.emplace_back(args&: Inst, args: &NewInst);
334 }
335 printTable(Table, Name: "X86ND2NonNDTable", Macro: "GET_X86_ND2NONND_TABLE", OS);
336}
337
338void X86InstrMappingEmitter::emitSSE2AVXTable(
339 ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
340
341 const std::map<StringRef, StringRef> ManualMap = {
342#define ENTRY_SSE2AVX(OLD, NEW) {#OLD, #NEW},
343#include "X86ManualInstrMapping.def"
344 };
345
346 std::vector<Entry> Table;
347 for (const CodeGenInstruction *Inst : Insts) {
348 const Record *Rec = Inst->TheDef;
349 StringRef Name = Rec->getName();
350 if (!isInteresting(Rec))
351 continue;
352 if (ManualMap.find(x: Name) != ManualMap.end()) {
353 const auto *NewRec = Records.getDef(Name: ManualMap.at(k: Rec->getName()));
354 assert(NewRec && "Instruction not found!");
355 const auto &NewInst = Target.getInstruction(InstRec: NewRec);
356 Table.emplace_back(args&: Inst, args: &NewInst);
357 continue;
358 }
359
360 std::string NewName = ("V" + Name).str();
361 const auto *AVXRec = Records.getDef(Name: NewName);
362 if (!AVXRec)
363 continue;
364 auto &AVXInst = Target.getInstruction(InstRec: AVXRec);
365 Table.emplace_back(args&: Inst, args: &AVXInst);
366 }
367 printTable(Table, Name: "X86SSE2AVXTable", Macro: "GET_X86_SSE2AVX_TABLE", OS);
368}
369
370void X86InstrMappingEmitter::run(raw_ostream &OS) {
371 emitSourceFileHeader(Desc: "X86 instruction mapping", OS);
372
373 ArrayRef<const CodeGenInstruction *> Insts = Target.getInstructions();
374 printClassDef(OS);
375 emitCompressEVEXTable(Insts, OS);
376 emitNFTransformTable(Insts, OS);
377 emitND2NonNDTable(Insts, OS);
378 emitSSE2AVXTable(Insts, OS);
379}
380
381static TableGen::Emitter::OptClass<X86InstrMappingEmitter>
382 X("gen-x86-instr-mapping", "Generate X86 instruction mapping");
383