1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(0),
443 UINT64_C(0),
444 UINT64_C(0),
445 UINT64_C(0),
446 UINT64_C(0),
447 UINT64_C(0),
448 UINT64_C(0),
449 UINT64_C(0),
450 UINT64_C(0),
451 UINT64_C(0),
452 UINT64_C(0),
453 UINT64_C(0),
454 UINT64_C(0),
455 UINT64_C(0),
456 UINT64_C(0),
457 UINT64_C(0),
458 UINT64_C(0),
459 UINT64_C(0),
460 UINT64_C(0),
461 UINT64_C(0),
462 UINT64_C(0),
463 UINT64_C(0),
464 UINT64_C(0),
465 UINT64_C(0),
466 UINT64_C(0),
467 UINT64_C(0),
468 UINT64_C(0),
469 UINT64_C(0),
470 UINT64_C(0),
471 UINT64_C(0),
472 UINT64_C(0),
473 UINT64_C(0),
474 UINT64_C(0),
475 UINT64_C(0),
476 UINT64_C(0),
477 UINT64_C(0),
478 UINT64_C(0),
479 UINT64_C(0),
480 UINT64_C(0),
481 UINT64_C(0),
482 UINT64_C(0),
483 UINT64_C(0),
484 UINT64_C(0),
485 UINT64_C(0),
486 UINT64_C(0),
487 UINT64_C(0),
488 UINT64_C(0),
489 UINT64_C(0),
490 UINT64_C(0),
491 UINT64_C(0),
492 UINT64_C(0),
493 UINT64_C(0),
494 UINT64_C(0),
495 UINT64_C(0),
496 UINT64_C(0),
497 UINT64_C(0),
498 UINT64_C(0),
499 UINT64_C(0),
500 UINT64_C(0),
501 UINT64_C(0),
502 UINT64_C(0),
503 UINT64_C(0),
504 UINT64_C(0),
505 UINT64_C(0),
506 UINT64_C(0),
507 UINT64_C(0),
508 UINT64_C(0),
509 UINT64_C(0),
510 UINT64_C(0),
511 UINT64_C(0),
512 UINT64_C(0),
513 UINT64_C(0),
514 UINT64_C(0),
515 UINT64_C(0),
516 UINT64_C(0),
517 UINT64_C(0),
518 UINT64_C(0),
519 UINT64_C(0),
520 UINT64_C(0),
521 UINT64_C(0),
522 UINT64_C(0),
523 UINT64_C(0),
524 UINT64_C(0),
525 UINT64_C(0),
526 UINT64_C(0),
527 UINT64_C(0),
528 UINT64_C(0),
529 UINT64_C(0),
530 UINT64_C(0),
531 UINT64_C(0),
532 UINT64_C(0),
533 UINT64_C(0),
534 UINT64_C(0),
535 UINT64_C(0),
536 UINT64_C(0),
537 UINT64_C(0),
538 UINT64_C(0),
539 UINT64_C(0),
540 UINT64_C(0),
541 UINT64_C(0),
542 UINT64_C(0),
543 UINT64_C(0),
544 UINT64_C(0),
545 UINT64_C(0),
546 UINT64_C(0),
547 UINT64_C(0),
548 UINT64_C(0),
549 UINT64_C(0),
550 UINT64_C(0),
551 UINT64_C(0),
552 UINT64_C(0),
553 UINT64_C(0),
554 UINT64_C(0),
555 UINT64_C(0),
556 UINT64_C(0),
557 UINT64_C(0),
558 UINT64_C(0),
559 UINT64_C(0),
560 UINT64_C(0),
561 UINT64_C(0),
562 UINT64_C(0),
563 UINT64_C(0),
564 UINT64_C(0),
565 UINT64_C(0),
566 UINT64_C(0),
567 UINT64_C(0),
568 UINT64_C(0),
569 UINT64_C(0),
570 UINT64_C(0),
571 UINT64_C(0),
572 UINT64_C(0),
573 UINT64_C(0),
574 UINT64_C(0),
575 UINT64_C(0),
576 UINT64_C(0),
577 UINT64_C(0),
578 UINT64_C(0),
579 UINT64_C(0),
580 UINT64_C(0),
581 UINT64_C(0),
582 UINT64_C(0),
583 UINT64_C(0),
584 UINT64_C(0),
585 UINT64_C(0),
586 UINT64_C(0),
587 UINT64_C(0),
588 UINT64_C(0),
589 UINT64_C(0),
590 UINT64_C(0),
591 UINT64_C(0),
592 UINT64_C(0),
593 UINT64_C(0),
594 UINT64_C(0),
595 UINT64_C(0),
596 UINT64_C(0),
597 UINT64_C(0),
598 UINT64_C(0),
599 UINT64_C(0),
600 UINT64_C(0),
601 UINT64_C(0),
602 UINT64_C(0),
603 UINT64_C(0),
604 UINT64_C(0),
605 UINT64_C(0),
606 UINT64_C(0),
607 UINT64_C(0),
608 UINT64_C(0),
609 UINT64_C(0),
610 UINT64_C(0),
611 UINT64_C(0),
612 UINT64_C(0),
613 UINT64_C(0),
614 UINT64_C(0),
615 UINT64_C(0),
616 UINT64_C(0),
617 UINT64_C(0),
618 UINT64_C(0),
619 UINT64_C(0),
620 UINT64_C(0),
621 UINT64_C(0),
622 UINT64_C(0),
623 UINT64_C(0),
624 UINT64_C(0),
625 UINT64_C(0),
626 UINT64_C(0),
627 UINT64_C(0),
628 UINT64_C(0),
629 UINT64_C(0),
630 UINT64_C(0),
631 UINT64_C(0),
632 UINT64_C(0),
633 UINT64_C(0),
634 UINT64_C(0),
635 UINT64_C(0),
636 UINT64_C(0),
637 UINT64_C(0),
638 UINT64_C(0),
639 UINT64_C(0),
640 UINT64_C(0),
641 UINT64_C(0),
642 UINT64_C(0),
643 UINT64_C(0),
644 UINT64_C(0),
645 UINT64_C(0),
646 UINT64_C(0),
647 UINT64_C(0),
648 UINT64_C(0),
649 UINT64_C(0),
650 UINT64_C(0),
651 UINT64_C(0),
652 UINT64_C(0),
653 UINT64_C(0),
654 UINT64_C(0),
655 UINT64_C(0),
656 UINT64_C(0),
657 UINT64_C(0),
658 UINT64_C(0),
659 UINT64_C(0),
660 UINT64_C(0),
661 UINT64_C(0),
662 UINT64_C(0),
663 UINT64_C(0),
664 UINT64_C(0),
665 UINT64_C(0),
666 UINT64_C(0),
667 UINT64_C(0),
668 UINT64_C(0),
669 UINT64_C(0),
670 UINT64_C(0),
671 UINT64_C(0),
672 UINT64_C(0),
673 UINT64_C(0),
674 UINT64_C(0),
675 UINT64_C(0),
676 UINT64_C(0),
677 UINT64_C(0),
678 UINT64_C(0),
679 UINT64_C(0),
680 UINT64_C(0),
681 UINT64_C(0),
682 UINT64_C(0),
683 UINT64_C(0),
684 UINT64_C(0),
685 UINT64_C(0),
686 UINT64_C(0),
687 UINT64_C(0),
688 UINT64_C(0),
689 UINT64_C(0),
690 UINT64_C(0),
691 UINT64_C(0),
692 UINT64_C(0),
693 UINT64_C(0),
694 UINT64_C(0),
695 UINT64_C(0),
696 UINT64_C(0),
697 UINT64_C(0),
698 UINT64_C(0),
699 UINT64_C(0),
700 UINT64_C(0),
701 UINT64_C(0),
702 UINT64_C(0),
703 UINT64_C(0),
704 UINT64_C(0),
705 UINT64_C(0),
706 UINT64_C(0),
707 UINT64_C(0),
708 UINT64_C(0),
709 UINT64_C(0),
710 UINT64_C(0),
711 UINT64_C(0),
712 UINT64_C(0),
713 UINT64_C(0),
714 UINT64_C(0),
715 UINT64_C(0),
716 UINT64_C(0),
717 UINT64_C(0),
718 UINT64_C(0),
719 UINT64_C(0),
720 UINT64_C(0),
721 UINT64_C(0),
722 UINT64_C(0),
723 UINT64_C(0),
724 UINT64_C(0),
725 UINT64_C(0),
726 UINT64_C(0),
727 UINT64_C(0),
728 UINT64_C(0),
729 UINT64_C(0),
730 UINT64_C(0),
731 UINT64_C(0),
732 UINT64_C(0),
733 UINT64_C(0),
734 UINT64_C(0),
735 UINT64_C(0),
736 UINT64_C(0),
737 UINT64_C(0),
738 UINT64_C(0),
739 UINT64_C(0),
740 UINT64_C(0),
741 UINT64_C(0),
742 UINT64_C(0),
743 UINT64_C(0),
744 UINT64_C(0),
745 UINT64_C(0),
746 UINT64_C(0),
747 UINT64_C(0),
748 UINT64_C(0),
749 UINT64_C(0),
750 UINT64_C(0),
751 UINT64_C(0),
752 UINT64_C(0),
753 UINT64_C(0),
754 UINT64_C(0),
755 UINT64_C(0),
756 UINT64_C(0),
757 UINT64_C(0),
758 UINT64_C(0),
759 UINT64_C(0),
760 UINT64_C(0),
761 UINT64_C(0),
762 UINT64_C(0),
763 UINT64_C(0),
764 UINT64_C(0),
765 UINT64_C(0),
766 UINT64_C(0),
767 UINT64_C(0),
768 UINT64_C(0),
769 UINT64_C(0),
770 UINT64_C(0),
771 UINT64_C(0),
772 UINT64_C(0),
773 UINT64_C(0),
774 UINT64_C(0),
775 UINT64_C(0),
776 UINT64_C(0),
777 UINT64_C(0),
778 UINT64_C(0),
779 UINT64_C(0),
780 UINT64_C(0),
781 UINT64_C(0),
782 UINT64_C(0),
783 UINT64_C(0),
784 UINT64_C(0),
785 UINT64_C(0),
786 UINT64_C(0),
787 UINT64_C(0),
788 UINT64_C(0),
789 UINT64_C(0),
790 UINT64_C(0),
791 UINT64_C(0),
792 UINT64_C(0),
793 UINT64_C(0),
794 UINT64_C(0),
795 UINT64_C(0),
796 UINT64_C(0),
797 UINT64_C(0),
798 UINT64_C(0),
799 UINT64_C(0),
800 UINT64_C(0),
801 UINT64_C(0),
802 UINT64_C(0),
803 UINT64_C(0),
804 UINT64_C(0),
805 UINT64_C(0),
806 UINT64_C(0),
807 UINT64_C(0),
808 UINT64_C(0),
809 UINT64_C(0),
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1564 UINT64_C(0),
1565 UINT64_C(0),
1566 UINT64_C(0),
1567 UINT64_C(0),
1568 UINT64_C(0),
1569 UINT64_C(0),
1570 UINT64_C(0),
1571 UINT64_C(0),
1572 UINT64_C(0),
1573 UINT64_C(0),
1574 UINT64_C(0),
1575 UINT64_C(0),
1576 UINT64_C(0),
1577 UINT64_C(0),
1578 UINT64_C(0),
1579 UINT64_C(0),
1580 UINT64_C(0),
1581 UINT64_C(0),
1582 UINT64_C(0),
1583 UINT64_C(0),
1584 UINT64_C(0),
1585 UINT64_C(0),
1586 UINT64_C(0),
1587 UINT64_C(0),
1588 UINT64_C(0),
1589 UINT64_C(0),
1590 UINT64_C(0),
1591 UINT64_C(0),
1592 UINT64_C(0),
1593 UINT64_C(0),
1594 UINT64_C(0),
1595 UINT64_C(0),
1596 UINT64_C(0),
1597 UINT64_C(1522540544), // ABSWr
1598 UINT64_C(3670024192), // ABSXr
1599 UINT64_C(68591616), // ABS_ZPmZ_B
1600 UINT64_C(81174528), // ABS_ZPmZ_D
1601 UINT64_C(72785920), // ABS_ZPmZ_H
1602 UINT64_C(76980224), // ABS_ZPmZ_S
1603 UINT64_C(67543040), // ABS_ZPzZ_B
1604 UINT64_C(80125952), // ABS_ZPzZ_D
1605 UINT64_C(71737344), // ABS_ZPzZ_H
1606 UINT64_C(75931648), // ABS_ZPzZ_S
1607 UINT64_C(1310767104), // ABSv16i8
1608 UINT64_C(1591785472), // ABSv1i64
1609 UINT64_C(245413888), // ABSv2i32
1610 UINT64_C(1323350016), // ABSv2i64
1611 UINT64_C(241219584), // ABSv4i16
1612 UINT64_C(1319155712), // ABSv4i32
1613 UINT64_C(1314961408), // ABSv8i16
1614 UINT64_C(237025280), // ABSv8i8
1615 UINT64_C(1161875456), // ADCLB_ZZZ_D
1616 UINT64_C(1157681152), // ADCLB_ZZZ_S
1617 UINT64_C(1161876480), // ADCLT_ZZZ_D
1618 UINT64_C(1157682176), // ADCLT_ZZZ_S
1619 UINT64_C(973078528), // ADCSWr
1620 UINT64_C(3120562176), // ADCSXr
1621 UINT64_C(436207616), // ADCWr
1622 UINT64_C(2583691264), // ADCXr
1623 UINT64_C(2441084928), // ADDG
1624 UINT64_C(3234856960), // ADDHA_MPPZ_D
1625 UINT64_C(3230662656), // ADDHA_MPPZ_S
1626 UINT64_C(1163943936), // ADDHNB_ZZZ_B
1627 UINT64_C(1168138240), // ADDHNB_ZZZ_H
1628 UINT64_C(1172332544), // ADDHNB_ZZZ_S
1629 UINT64_C(1163944960), // ADDHNT_ZZZ_B
1630 UINT64_C(1168139264), // ADDHNT_ZZZ_H
1631 UINT64_C(1172333568), // ADDHNT_ZZZ_S
1632 UINT64_C(245383168), // ADDHNv2i64_v2i32
1633 UINT64_C(1319124992), // ADDHNv2i64_v4i32
1634 UINT64_C(241188864), // ADDHNv4i32_v4i16
1635 UINT64_C(1314930688), // ADDHNv4i32_v8i16
1636 UINT64_C(1310736384), // ADDHNv8i16_v16i8
1637 UINT64_C(236994560), // ADDHNv8i16_v8i8
1638 UINT64_C(73420800), // ADDPL_XXI
1639 UINT64_C(2583699456), // ADDPT_shift
1640 UINT64_C(1142005760), // ADDP_ZPmZ_B
1641 UINT64_C(1154588672), // ADDP_ZPmZ_D
1642 UINT64_C(1146200064), // ADDP_ZPmZ_H
1643 UINT64_C(1150394368), // ADDP_ZPmZ_S
1644 UINT64_C(1310768128), // ADDPv16i8
1645 UINT64_C(245414912), // ADDPv2i32
1646 UINT64_C(1323351040), // ADDPv2i64
1647 UINT64_C(1592899584), // ADDPv2i64p
1648 UINT64_C(241220608), // ADDPv4i16
1649 UINT64_C(1319156736), // ADDPv4i32
1650 UINT64_C(1314962432), // ADDPv8i16
1651 UINT64_C(237026304), // ADDPv8i8
1652 UINT64_C(67444736), // ADDQV_VPZ_B
1653 UINT64_C(80027648), // ADDQV_VPZ_D
1654 UINT64_C(71639040), // ADDQV_VPZ_H
1655 UINT64_C(75833344), // ADDQV_VPZ_S
1656 UINT64_C(73422848), // ADDSPL_XXI
1657 UINT64_C(69228544), // ADDSVL_XXI
1658 UINT64_C(822083584), // ADDSWri
1659 UINT64_C(721420288), // ADDSWrs
1660 UINT64_C(723517440), // ADDSWrx
1661 UINT64_C(2969567232), // ADDSXri
1662 UINT64_C(2868903936), // ADDSXrs
1663 UINT64_C(2871001088), // ADDSXrx
1664 UINT64_C(2871025664), // ADDSXrx64
1665 UINT64_C(3234922496), // ADDVA_MPPZ_D
1666 UINT64_C(3230728192), // ADDVA_MPPZ_S
1667 UINT64_C(69226496), // ADDVL_XXI
1668 UINT64_C(1311881216), // ADDVv16i8v
1669 UINT64_C(242333696), // ADDVv4i16v
1670 UINT64_C(1320269824), // ADDVv4i32v
1671 UINT64_C(1316075520), // ADDVv8i16v
1672 UINT64_C(238139392), // ADDVv8i8v
1673 UINT64_C(285212672), // ADDWri
1674 UINT64_C(184549376), // ADDWrs
1675 UINT64_C(186646528), // ADDWrx
1676 UINT64_C(2432696320), // ADDXri
1677 UINT64_C(2332033024), // ADDXrs
1678 UINT64_C(2334130176), // ADDXrx
1679 UINT64_C(2334154752), // ADDXrx64
1680 UINT64_C(3240141568), // ADD_VG2_2ZZ_B
1681 UINT64_C(3252724480), // ADD_VG2_2ZZ_D
1682 UINT64_C(3244335872), // ADD_VG2_2ZZ_H
1683 UINT64_C(3248530176), // ADD_VG2_2ZZ_S
1684 UINT64_C(3252688912), // ADD_VG2_M2Z2Z_D
1685 UINT64_C(3248494608), // ADD_VG2_M2Z2Z_S
1686 UINT64_C(3244300304), // ADD_VG2_M2ZZ_D
1687 UINT64_C(3240106000), // ADD_VG2_M2ZZ_S
1688 UINT64_C(3252689936), // ADD_VG2_M2Z_D
1689 UINT64_C(3248495632), // ADD_VG2_M2Z_S
1690 UINT64_C(3240143616), // ADD_VG4_4ZZ_B
1691 UINT64_C(3252726528), // ADD_VG4_4ZZ_D
1692 UINT64_C(3244337920), // ADD_VG4_4ZZ_H
1693 UINT64_C(3248532224), // ADD_VG4_4ZZ_S
1694 UINT64_C(3252754448), // ADD_VG4_M4Z4Z_D
1695 UINT64_C(3248560144), // ADD_VG4_M4Z4Z_S
1696 UINT64_C(3245348880), // ADD_VG4_M4ZZ_D
1697 UINT64_C(3241154576), // ADD_VG4_M4ZZ_S
1698 UINT64_C(3252755472), // ADD_VG4_M4Z_D
1699 UINT64_C(3248561168), // ADD_VG4_M4Z_S
1700 UINT64_C(622903296), // ADD_ZI_B
1701 UINT64_C(635486208), // ADD_ZI_D
1702 UINT64_C(627097600), // ADD_ZI_H
1703 UINT64_C(631291904), // ADD_ZI_S
1704 UINT64_C(67108864), // ADD_ZPmZ_B
1705 UINT64_C(79953920), // ADD_ZPmZ_CPA
1706 UINT64_C(79691776), // ADD_ZPmZ_D
1707 UINT64_C(71303168), // ADD_ZPmZ_H
1708 UINT64_C(75497472), // ADD_ZPmZ_S
1709 UINT64_C(69206016), // ADD_ZZZ_B
1710 UINT64_C(81790976), // ADD_ZZZ_CPA
1711 UINT64_C(81788928), // ADD_ZZZ_D
1712 UINT64_C(73400320), // ADD_ZZZ_H
1713 UINT64_C(77594624), // ADD_ZZZ_S
1714 UINT64_C(1310753792), // ADDv16i8
1715 UINT64_C(1591772160), // ADDv1i64
1716 UINT64_C(245400576), // ADDv2i32
1717 UINT64_C(1323336704), // ADDv2i64
1718 UINT64_C(241206272), // ADDv4i16
1719 UINT64_C(1319142400), // ADDv4i32
1720 UINT64_C(1314948096), // ADDv8i16
1721 UINT64_C(237011968), // ADDv8i8
1722 UINT64_C(268435456), // ADR
1723 UINT64_C(2415919104), // ADRP
1724 UINT64_C(81829888), // ADR_LSL_ZZZ_D_0
1725 UINT64_C(81830912), // ADR_LSL_ZZZ_D_1
1726 UINT64_C(81831936), // ADR_LSL_ZZZ_D_2
1727 UINT64_C(81832960), // ADR_LSL_ZZZ_D_3
1728 UINT64_C(77635584), // ADR_LSL_ZZZ_S_0
1729 UINT64_C(77636608), // ADR_LSL_ZZZ_S_1
1730 UINT64_C(77637632), // ADR_LSL_ZZZ_S_2
1731 UINT64_C(77638656), // ADR_LSL_ZZZ_S_3
1732 UINT64_C(69246976), // ADR_SXTW_ZZZ_D_0
1733 UINT64_C(69248000), // ADR_SXTW_ZZZ_D_1
1734 UINT64_C(69249024), // ADR_SXTW_ZZZ_D_2
1735 UINT64_C(69250048), // ADR_SXTW_ZZZ_D_3
1736 UINT64_C(73441280), // ADR_UXTW_ZZZ_D_0
1737 UINT64_C(73442304), // ADR_UXTW_ZZZ_D_1
1738 UINT64_C(73443328), // ADR_UXTW_ZZZ_D_2
1739 UINT64_C(73444352), // ADR_UXTW_ZZZ_D_3
1740 UINT64_C(1159982080), // AESDMIC_2ZZI_B
1741 UINT64_C(1160244224), // AESDMIC_4ZZI_B
1742 UINT64_C(1159916544), // AESD_2ZZI_B
1743 UINT64_C(1160178688), // AESD_4ZZI_B
1744 UINT64_C(1159914496), // AESD_ZZZ_B
1745 UINT64_C(1311266816), // AESDrr
1746 UINT64_C(1159981056), // AESEMC_2ZZI_B
1747 UINT64_C(1160243200), // AESEMC_4ZZI_B
1748 UINT64_C(1159915520), // AESE_2ZZI_B
1749 UINT64_C(1160177664), // AESE_4ZZI_B
1750 UINT64_C(1159913472), // AESE_ZZZ_B
1751 UINT64_C(1311262720), // AESErr
1752 UINT64_C(1159783424), // AESIMC_ZZ_B
1753 UINT64_C(1311275008), // AESIMCrr
1754 UINT64_C(1159782400), // AESMC_ZZ_B
1755 UINT64_C(1311270912), // AESMCrr
1756 UINT64_C(69083136), // ANDQV_VPZ_B
1757 UINT64_C(81666048), // ANDQV_VPZ_D
1758 UINT64_C(73277440), // ANDQV_VPZ_H
1759 UINT64_C(77471744), // ANDQV_VPZ_S
1760 UINT64_C(1912602624), // ANDSWri
1761 UINT64_C(1778384896), // ANDSWrs
1762 UINT64_C(4060086272), // ANDSXri
1763 UINT64_C(3925868544), // ANDSXrs
1764 UINT64_C(624967680), // ANDS_PPzPP
1765 UINT64_C(68820992), // ANDV_VPZ_B
1766 UINT64_C(81403904), // ANDV_VPZ_D
1767 UINT64_C(73015296), // ANDV_VPZ_H
1768 UINT64_C(77209600), // ANDV_VPZ_S
1769 UINT64_C(301989888), // ANDWri
1770 UINT64_C(167772160), // ANDWrs
1771 UINT64_C(2449473536), // ANDXri
1772 UINT64_C(2315255808), // ANDXrs
1773 UINT64_C(620773376), // AND_PPzPP
1774 UINT64_C(92274688), // AND_ZI
1775 UINT64_C(68812800), // AND_ZPmZ_B
1776 UINT64_C(81395712), // AND_ZPmZ_D
1777 UINT64_C(73007104), // AND_ZPmZ_H
1778 UINT64_C(77201408), // AND_ZPmZ_S
1779 UINT64_C(69218304), // AND_ZZZ
1780 UINT64_C(1310727168), // ANDv16i8
1781 UINT64_C(236985344), // ANDv8i8
1782 UINT64_C(3574493184), // APAS
1783 UINT64_C(67404032), // ASRD_ZPmI_B
1784 UINT64_C(75792384), // ASRD_ZPmI_D
1785 UINT64_C(67404288), // ASRD_ZPmI_H
1786 UINT64_C(71598080), // ASRD_ZPmI_S
1787 UINT64_C(68452352), // ASRR_ZPmZ_B
1788 UINT64_C(81035264), // ASRR_ZPmZ_D
1789 UINT64_C(72646656), // ASRR_ZPmZ_H
1790 UINT64_C(76840960), // ASRR_ZPmZ_S
1791 UINT64_C(448800768), // ASRVWr
1792 UINT64_C(2596284416), // ASRVXr
1793 UINT64_C(68714496), // ASR_WIDE_ZPmZ_B
1794 UINT64_C(72908800), // ASR_WIDE_ZPmZ_H
1795 UINT64_C(77103104), // ASR_WIDE_ZPmZ_S
1796 UINT64_C(69238784), // ASR_WIDE_ZZZ_B
1797 UINT64_C(73433088), // ASR_WIDE_ZZZ_H
1798 UINT64_C(77627392), // ASR_WIDE_ZZZ_S
1799 UINT64_C(67141888), // ASR_ZPmI_B
1800 UINT64_C(75530240), // ASR_ZPmI_D
1801 UINT64_C(67142144), // ASR_ZPmI_H
1802 UINT64_C(71335936), // ASR_ZPmI_S
1803 UINT64_C(68190208), // ASR_ZPmZ_B
1804 UINT64_C(80773120), // ASR_ZPmZ_D
1805 UINT64_C(72384512), // ASR_ZPmZ_H
1806 UINT64_C(76578816), // ASR_ZPmZ_S
1807 UINT64_C(69767168), // ASR_ZZI_B
1808 UINT64_C(77631488), // ASR_ZZI_D
1809 UINT64_C(70291456), // ASR_ZZI_H
1810 UINT64_C(73437184), // ASR_ZZI_S
1811 UINT64_C(3670087680), // AUTDA
1812 UINT64_C(3670088704), // AUTDB
1813 UINT64_C(3670096864), // AUTDZA
1814 UINT64_C(3670097888), // AUTDZB
1815 UINT64_C(3670085632), // AUTIA
1816 UINT64_C(3573752223), // AUTIA1716
1817 UINT64_C(3670129662), // AUTIA171615
1818 UINT64_C(3573752767), // AUTIASP
1819 UINT64_C(4085252127), // AUTIASPPCi
1820 UINT64_C(3670118430), // AUTIASPPCr
1821 UINT64_C(3573752735), // AUTIAZ
1822 UINT64_C(3670086656), // AUTIB
1823 UINT64_C(3573752287), // AUTIB1716
1824 UINT64_C(3670130686), // AUTIB171615
1825 UINT64_C(3573752831), // AUTIBSP
1826 UINT64_C(4087349279), // AUTIBSPPCi
1827 UINT64_C(3670119454), // AUTIBSPPCr
1828 UINT64_C(3573752799), // AUTIBZ
1829 UINT64_C(3670094816), // AUTIZA
1830 UINT64_C(3670095840), // AUTIZB
1831 UINT64_C(3573563487), // AXFLAG
1832 UINT64_C(335544320), // B
1833 UINT64_C(3458203648), // BCAX
1834 UINT64_C(73414656), // BCAX_ZZZZ
1835 UINT64_C(1409286160), // BCcc
1836 UINT64_C(1157673984), // BDEP_ZZZ_B
1837 UINT64_C(1170256896), // BDEP_ZZZ_D
1838 UINT64_C(1161868288), // BDEP_ZZZ_H
1839 UINT64_C(1166062592), // BDEP_ZZZ_S
1840 UINT64_C(1157672960), // BEXT_ZZZ_B
1841 UINT64_C(1170255872), // BEXT_ZZZ_D
1842 UINT64_C(1161867264), // BEXT_ZZZ_H
1843 UINT64_C(1166061568), // BEXT_ZZZ_S
1844 UINT64_C(255913984), // BF16DOTlanev4bf16
1845 UINT64_C(1329655808), // BF16DOTlanev8bf16
1846 UINT64_C(782333952), // BF1CVTL
1847 UINT64_C(1856075776), // BF1CVTL2
1848 UINT64_C(1695102976), // BF1CVTLT_ZZ_BtoH
1849 UINT64_C(3244744705), // BF1CVTL_2ZZ_BtoH
1850 UINT64_C(3244744704), // BF1CVT_2ZZ_BtoH
1851 UINT64_C(1695037440), // BF1CVT_ZZ_BtoH
1852 UINT64_C(786528256), // BF2CVTL
1853 UINT64_C(1860270080), // BF2CVTL2
1854 UINT64_C(1695104000), // BF2CVTLT_ZZ_BtoH
1855 UINT64_C(3253133313), // BF2CVTL_2ZZ_BtoH
1856 UINT64_C(3253133312), // BF2CVT_2ZZ_BtoH
1857 UINT64_C(1695038464), // BF2CVT_ZZ_BtoH
1858 UINT64_C(3252952064), // BFADD_VG2_M2Z_H
1859 UINT64_C(3253017600), // BFADD_VG4_M4Z_H
1860 UINT64_C(1694531584), // BFADD_ZPmZZ
1861 UINT64_C(1694498816), // BFADD_ZZZ
1862 UINT64_C(3240148992), // BFCLAMP_VG2_2ZZZ_H
1863 UINT64_C(3240151040), // BFCLAMP_VG4_4ZZZ_H
1864 UINT64_C(1679827968), // BFCLAMP_ZZZ
1865 UINT64_C(509820928), // BFCVT
1866 UINT64_C(245458944), // BFCVTN
1867 UINT64_C(1319200768), // BFCVTN2
1868 UINT64_C(1686806528), // BFCVTNT_ZPmZ
1869 UINT64_C(1686282240), // BFCVTNT_ZPzZ
1870 UINT64_C(1695168512), // BFCVTN_Z2Z_HtoB
1871 UINT64_C(3244351520), // BFCVTN_Z2Z_StoH
1872 UINT64_C(3244613632), // BFCVT_Z2Z_HtoB
1873 UINT64_C(3244351488), // BFCVT_Z2Z_StoH
1874 UINT64_C(1703583744), // BFCVT_ZPmZ
1875 UINT64_C(1687863296), // BFCVT_ZPzZ_StoH
1876 UINT64_C(3248492560), // BFDOT_VG2_M2Z2Z_HtoS
1877 UINT64_C(3243249688), // BFDOT_VG2_M2ZZI_HtoS
1878 UINT64_C(3240103952), // BFDOT_VG2_M2ZZ_HtoS
1879 UINT64_C(3248558096), // BFDOT_VG4_M4Z4Z_HtoS
1880 UINT64_C(3243282456), // BFDOT_VG4_M4ZZI_HtoS
1881 UINT64_C(3241152528), // BFDOT_VG4_M4ZZ_HtoS
1882 UINT64_C(1684029440), // BFDOT_ZZI
1883 UINT64_C(1684045824), // BFDOT_ZZZ
1884 UINT64_C(776010752), // BFDOTv4bf16
1885 UINT64_C(1849752576), // BFDOTv8bf16
1886 UINT64_C(3240145184), // BFMAXNM_VG2_2Z2Z_H
1887 UINT64_C(3240141088), // BFMAXNM_VG2_2ZZ_H
1888 UINT64_C(3240147232), // BFMAXNM_VG4_4Z2Z_H
1889 UINT64_C(3240143136), // BFMAXNM_VG4_4ZZ_H
1890 UINT64_C(1694793728), // BFMAXNM_ZPmZZ
1891 UINT64_C(3240145152), // BFMAX_VG2_2Z2Z_H
1892 UINT64_C(3240141056), // BFMAX_VG2_2ZZ_H
1893 UINT64_C(3240147200), // BFMAX_VG4_4Z2Z_H
1894 UINT64_C(3240143104), // BFMAX_VG4_4ZZ_H
1895 UINT64_C(1694924800), // BFMAX_ZPmZZ
1896 UINT64_C(3240145185), // BFMINNM_VG2_2Z2Z_H
1897 UINT64_C(3240141089), // BFMINNM_VG2_2ZZ_H
1898 UINT64_C(3240147233), // BFMINNM_VG4_4Z2Z_H
1899 UINT64_C(3240143137), // BFMINNM_VG4_4ZZ_H
1900 UINT64_C(1694859264), // BFMINNM_ZPmZZ
1901 UINT64_C(3240145153), // BFMIN_VG2_2Z2Z_H
1902 UINT64_C(3240141057), // BFMIN_VG2_2ZZ_H
1903 UINT64_C(3240147201), // BFMIN_VG4_4Z2Z_H
1904 UINT64_C(3240143105), // BFMIN_VG4_4ZZ_H
1905 UINT64_C(1694990336), // BFMIN_ZPmZZ
1906 UINT64_C(784399360), // BFMLALB
1907 UINT64_C(264302592), // BFMLALBIdx
1908 UINT64_C(1692434432), // BFMLALB_ZZZ
1909 UINT64_C(1692418048), // BFMLALB_ZZZI
1910 UINT64_C(1858141184), // BFMLALT
1911 UINT64_C(1338044416), // BFMLALTIdx
1912 UINT64_C(1692435456), // BFMLALT_ZZZ
1913 UINT64_C(1692419072), // BFMLALT_ZZZI
1914 UINT64_C(3246395408), // BFMLAL_MZZI_HtoS
1915 UINT64_C(3240102928), // BFMLAL_MZZ_HtoS
1916 UINT64_C(3248490512), // BFMLAL_VG2_M2Z2Z_HtoS
1917 UINT64_C(3247443984), // BFMLAL_VG2_M2ZZI_HtoS
1918 UINT64_C(3240101904), // BFMLAL_VG2_M2ZZ_HtoS
1919 UINT64_C(3248556048), // BFMLAL_VG4_M4Z4Z_HtoS
1920 UINT64_C(3247476752), // BFMLAL_VG4_M4ZZI_HtoS
1921 UINT64_C(3241150480), // BFMLAL_VG4_M4ZZ_HtoS
1922 UINT64_C(3252686856), // BFMLA_VG2_M2Z2Z
1923 UINT64_C(3244301312), // BFMLA_VG2_M2ZZ
1924 UINT64_C(3239055392), // BFMLA_VG2_M2ZZI
1925 UINT64_C(3252752392), // BFMLA_VG4_M4Z4Z
1926 UINT64_C(3245349888), // BFMLA_VG4_M4ZZ
1927 UINT64_C(3239088160), // BFMLA_VG4_M4ZZI
1928 UINT64_C(1696595968), // BFMLA_ZPmZZ
1929 UINT64_C(1679820800), // BFMLA_ZZZI
1930 UINT64_C(1692426240), // BFMLSLB_ZZZI_S
1931 UINT64_C(1692442624), // BFMLSLB_ZZZ_S
1932 UINT64_C(1692427264), // BFMLSLT_ZZZI_S
1933 UINT64_C(1692443648), // BFMLSLT_ZZZ_S
1934 UINT64_C(3246395416), // BFMLSL_MZZI_HtoS
1935 UINT64_C(3240102936), // BFMLSL_MZZ_HtoS
1936 UINT64_C(3248490520), // BFMLSL_VG2_M2Z2Z_HtoS
1937 UINT64_C(3247443992), // BFMLSL_VG2_M2ZZI_HtoS
1938 UINT64_C(3240101912), // BFMLSL_VG2_M2ZZ_HtoS
1939 UINT64_C(3248556056), // BFMLSL_VG4_M4Z4Z_HtoS
1940 UINT64_C(3247476760), // BFMLSL_VG4_M4ZZI_HtoS
1941 UINT64_C(3241150488), // BFMLSL_VG4_M4ZZ_HtoS
1942 UINT64_C(3252686872), // BFMLS_VG2_M2Z2Z
1943 UINT64_C(3244301320), // BFMLS_VG2_M2ZZ
1944 UINT64_C(3239055408), // BFMLS_VG2_M2ZZI
1945 UINT64_C(3252752408), // BFMLS_VG4_M4Z4Z
1946 UINT64_C(3245349896), // BFMLS_VG4_M4ZZ
1947 UINT64_C(3239088176), // BFMLS_VG4_M4ZZI
1948 UINT64_C(1696604160), // BFMLS_ZPmZZ
1949 UINT64_C(1679821824), // BFMLS_ZZZI
1950 UINT64_C(1849748480), // BFMMLA
1951 UINT64_C(1684071424), // BFMMLA_ZZZ
1952 UINT64_C(2167407112), // BFMOP4A_M2Z2Z_H
1953 UINT64_C(2165309952), // BFMOP4A_M2Z2Z_S
1954 UINT64_C(2166358536), // BFMOP4A_M2ZZ_H
1955 UINT64_C(2164261376), // BFMOP4A_M2ZZ_S
1956 UINT64_C(2167406600), // BFMOP4A_MZ2Z_H
1957 UINT64_C(2165309440), // BFMOP4A_MZ2Z_S
1958 UINT64_C(2166358024), // BFMOP4A_MZZ_H
1959 UINT64_C(2164260864), // BFMOP4A_MZZ_S
1960 UINT64_C(2167407128), // BFMOP4S_M2Z2Z_H
1961 UINT64_C(2165309968), // BFMOP4S_M2Z2Z_S
1962 UINT64_C(2166358552), // BFMOP4S_M2ZZ_H
1963 UINT64_C(2164261392), // BFMOP4S_M2ZZ_S
1964 UINT64_C(2167406616), // BFMOP4S_MZ2Z_H
1965 UINT64_C(2165309456), // BFMOP4S_MZ2Z_S
1966 UINT64_C(2166358040), // BFMOP4S_MZZ_H
1967 UINT64_C(2164260880), // BFMOP4S_MZZ_S
1968 UINT64_C(2172649472), // BFMOPA_MPPZZ
1969 UINT64_C(2174746632), // BFMOPA_MPPZZ_H
1970 UINT64_C(2172649488), // BFMOPS_MPPZZ
1971 UINT64_C(2174746648), // BFMOPS_MPPZZ_H
1972 UINT64_C(3240158208), // BFMUL_2Z2Z
1973 UINT64_C(3240159232), // BFMUL_2ZZ
1974 UINT64_C(3240223744), // BFMUL_4Z4Z
1975 UINT64_C(3240224768), // BFMUL_4ZZ
1976 UINT64_C(1694662656), // BFMUL_ZPmZZ
1977 UINT64_C(1694500864), // BFMUL_ZZZ
1978 UINT64_C(1679828992), // BFMUL_ZZZI
1979 UINT64_C(855638016), // BFMWri
1980 UINT64_C(3007315968), // BFMXri
1981 UINT64_C(3240145280), // BFSCALE_2Z2Z
1982 UINT64_C(3240141184), // BFSCALE_2ZZ
1983 UINT64_C(3240147328), // BFSCALE_4Z4Z
1984 UINT64_C(3240143232), // BFSCALE_4ZZ
1985 UINT64_C(1695121408), // BFSCALE_ZPZZ
1986 UINT64_C(3252952072), // BFSUB_VG2_M2Z_H
1987 UINT64_C(3253017608), // BFSUB_VG4_M4Z_H
1988 UINT64_C(1694597120), // BFSUB_ZPmZZ
1989 UINT64_C(1694499840), // BFSUB_ZZZ
1990 UINT64_C(2170552328), // BFTMOPA_M2ZZZI_HtoH
1991 UINT64_C(2168455168), // BFTMOPA_M2ZZZI_HtoS
1992 UINT64_C(3243245592), // BFVDOT_VG2_M2ZZI_HtoS
1993 UINT64_C(1157675008), // BGRP_ZZZ_B
1994 UINT64_C(1170257920), // BGRP_ZZZ_D
1995 UINT64_C(1161869312), // BGRP_ZZZ_H
1996 UINT64_C(1166063616), // BGRP_ZZZ_S
1997 UINT64_C(1780482048), // BICSWrs
1998 UINT64_C(3927965696), // BICSXrs
1999 UINT64_C(624967696), // BICS_PPzPP
2000 UINT64_C(169869312), // BICWrs
2001 UINT64_C(2317352960), // BICXrs
2002 UINT64_C(620773392), // BIC_PPzPP
2003 UINT64_C(68878336), // BIC_ZPmZ_B
2004 UINT64_C(81461248), // BIC_ZPmZ_D
2005 UINT64_C(73072640), // BIC_ZPmZ_H
2006 UINT64_C(77266944), // BIC_ZPmZ_S
2007 UINT64_C(81801216), // BIC_ZZZ
2008 UINT64_C(1314921472), // BICv16i8
2009 UINT64_C(788534272), // BICv2i32
2010 UINT64_C(788567040), // BICv4i16
2011 UINT64_C(1862276096), // BICv4i32
2012 UINT64_C(1862308864), // BICv8i16
2013 UINT64_C(241179648), // BICv8i8
2014 UINT64_C(1860180992), // BIFv16i8
2015 UINT64_C(786439168), // BIFv8i8
2016 UINT64_C(1855986688), // BITv16i8
2017 UINT64_C(782244864), // BITv8i8
2018 UINT64_C(2483027968), // BL
2019 UINT64_C(3594452992), // BLR
2020 UINT64_C(3611232256), // BLRAA
2021 UINT64_C(3594455071), // BLRAAZ
2022 UINT64_C(3611233280), // BLRAB
2023 UINT64_C(3594456095), // BLRABZ
2024 UINT64_C(2155872264), // BMOPA_MPPZZ_S
2025 UINT64_C(2155872280), // BMOPS_MPPZZ_S
2026 UINT64_C(3592355840), // BR
2027 UINT64_C(3609135104), // BRAA
2028 UINT64_C(3592357919), // BRAAZ
2029 UINT64_C(3609136128), // BRAB
2030 UINT64_C(3592358943), // BRABZ
2031 UINT64_C(3574166175), // BRB_IALL
2032 UINT64_C(3574166207), // BRB_INJ
2033 UINT64_C(3558866944), // BRK
2034 UINT64_C(626016256), // BRKAS_PPzP
2035 UINT64_C(621821968), // BRKA_PPmP
2036 UINT64_C(621821952), // BRKA_PPzP
2037 UINT64_C(634404864), // BRKBS_PPzP
2038 UINT64_C(630210576), // BRKB_PPmP
2039 UINT64_C(630210560), // BRKB_PPzP
2040 UINT64_C(626540544), // BRKNS_PPzP
2041 UINT64_C(622346240), // BRKN_PPzP
2042 UINT64_C(625000448), // BRKPAS_PPzPP
2043 UINT64_C(620806144), // BRKPA_PPzPP
2044 UINT64_C(625000464), // BRKPBS_PPzPP
2045 UINT64_C(620806160), // BRKPB_PPzPP
2046 UINT64_C(73415680), // BSL1N_ZZZZ
2047 UINT64_C(77609984), // BSL2N_ZZZZ
2048 UINT64_C(69221376), // BSL_ZZZZ
2049 UINT64_C(1851792384), // BSLv16i8
2050 UINT64_C(778050560), // BSLv8i8
2051 UINT64_C(1409286144), // Bcc
2052 UINT64_C(1157683200), // CADD_ZZI_B
2053 UINT64_C(1170266112), // CADD_ZZI_D
2054 UINT64_C(1161877504), // CADD_ZZI_H
2055 UINT64_C(1166071808), // CADD_ZZI_S
2056 UINT64_C(148929536), // CASAB
2057 UINT64_C(1222671360), // CASAH
2058 UINT64_C(148962304), // CASALB
2059 UINT64_C(1222704128), // CASALH
2060 UINT64_C(3384867840), // CASALTX
2061 UINT64_C(2296445952), // CASALW
2062 UINT64_C(3370187776), // CASALX
2063 UINT64_C(3384835072), // CASATX
2064 UINT64_C(2296413184), // CASAW
2065 UINT64_C(3370155008), // CASAX
2066 UINT64_C(144735232), // CASB
2067 UINT64_C(1218477056), // CASH
2068 UINT64_C(144768000), // CASLB
2069 UINT64_C(1218509824), // CASLH
2070 UINT64_C(3380673536), // CASLTX
2071 UINT64_C(2292251648), // CASLW
2072 UINT64_C(3365993472), // CASLX
2073 UINT64_C(1237384192), // CASPALTX
2074 UINT64_C(140573696), // CASPALW
2075 UINT64_C(1214315520), // CASPALX
2076 UINT64_C(1237351424), // CASPATX
2077 UINT64_C(140540928), // CASPAW
2078 UINT64_C(1214282752), // CASPAX
2079 UINT64_C(1233189888), // CASPLTX
2080 UINT64_C(136379392), // CASPLW
2081 UINT64_C(1210121216), // CASPLX
2082 UINT64_C(1233157120), // CASPTX
2083 UINT64_C(136346624), // CASPW
2084 UINT64_C(1210088448), // CASPX
2085 UINT64_C(3380640768), // CASTX
2086 UINT64_C(2292218880), // CASW
2087 UINT64_C(3365960704), // CASX
2088 UINT64_C(1958772736), // CBBEQWrr
2089 UINT64_C(1948286976), // CBBGEWrr
2090 UINT64_C(1946189824), // CBBGTWrr
2091 UINT64_C(1950384128), // CBBHIWrr
2092 UINT64_C(1952481280), // CBBHSWrr
2093 UINT64_C(1960869888), // CBBNEWrr
2094 UINT64_C(1975517184), // CBEQWri
2095 UINT64_C(1958739968), // CBEQWrr
2096 UINT64_C(4123000832), // CBEQXri
2097 UINT64_C(4106223616), // CBEQXrr
2098 UINT64_C(1948254208), // CBGEWrr
2099 UINT64_C(4095737856), // CBGEXrr
2100 UINT64_C(1962934272), // CBGTWri
2101 UINT64_C(1946157056), // CBGTWrr
2102 UINT64_C(4110417920), // CBGTXri
2103 UINT64_C(4093640704), // CBGTXrr
2104 UINT64_C(1958789120), // CBHEQWrr
2105 UINT64_C(1948303360), // CBHGEWrr
2106 UINT64_C(1946206208), // CBHGTWrr
2107 UINT64_C(1950400512), // CBHHIWrr
2108 UINT64_C(1952497664), // CBHHSWrr
2109 UINT64_C(1967128576), // CBHIWri
2110 UINT64_C(1950351360), // CBHIWrr
2111 UINT64_C(4114612224), // CBHIXri
2112 UINT64_C(4097835008), // CBHIXrr
2113 UINT64_C(1960886272), // CBHNEWrr
2114 UINT64_C(1952448512), // CBHSWrr
2115 UINT64_C(4099932160), // CBHSXrr
2116 UINT64_C(1969225728), // CBLOWri
2117 UINT64_C(4116709376), // CBLOXri
2118 UINT64_C(1965031424), // CBLTWri
2119 UINT64_C(4112515072), // CBLTXri
2120 UINT64_C(1977614336), // CBNEWri
2121 UINT64_C(1960837120), // CBNEWrr
2122 UINT64_C(4125097984), // CBNEXri
2123 UINT64_C(4108320768), // CBNEXrr
2124 UINT64_C(889192448), // CBNZW
2125 UINT64_C(3036676096), // CBNZX
2126 UINT64_C(872415232), // CBZW
2127 UINT64_C(3019898880), // CBZX
2128 UINT64_C(977274880), // CCMNWi
2129 UINT64_C(977272832), // CCMNWr
2130 UINT64_C(3124758528), // CCMNXi
2131 UINT64_C(3124756480), // CCMNXr
2132 UINT64_C(2051016704), // CCMPWi
2133 UINT64_C(2051014656), // CCMPWr
2134 UINT64_C(4198500352), // CCMPXi
2135 UINT64_C(4198498304), // CCMPXr
2136 UINT64_C(1155547136), // CDOT_ZZZI_D
2137 UINT64_C(1151352832), // CDOT_ZZZI_S
2138 UINT64_C(1153437696), // CDOT_ZZZ_D
2139 UINT64_C(1149243392), // CDOT_ZZZ_S
2140 UINT64_C(3573563423), // CFINV
2141 UINT64_C(3573753119), // CHKFEAT
2142 UINT64_C(87072768), // CLASTA_RPZ_B
2143 UINT64_C(99655680), // CLASTA_RPZ_D
2144 UINT64_C(91267072), // CLASTA_RPZ_H
2145 UINT64_C(95461376), // CLASTA_RPZ_S
2146 UINT64_C(86671360), // CLASTA_VPZ_B
2147 UINT64_C(99254272), // CLASTA_VPZ_D
2148 UINT64_C(90865664), // CLASTA_VPZ_H
2149 UINT64_C(95059968), // CLASTA_VPZ_S
2150 UINT64_C(86540288), // CLASTA_ZPZ_B
2151 UINT64_C(99123200), // CLASTA_ZPZ_D
2152 UINT64_C(90734592), // CLASTA_ZPZ_H
2153 UINT64_C(94928896), // CLASTA_ZPZ_S
2154 UINT64_C(87138304), // CLASTB_RPZ_B
2155 UINT64_C(99721216), // CLASTB_RPZ_D
2156 UINT64_C(91332608), // CLASTB_RPZ_H
2157 UINT64_C(95526912), // CLASTB_RPZ_S
2158 UINT64_C(86736896), // CLASTB_VPZ_B
2159 UINT64_C(99319808), // CLASTB_VPZ_D
2160 UINT64_C(90931200), // CLASTB_VPZ_H
2161 UINT64_C(95125504), // CLASTB_VPZ_S
2162 UINT64_C(86605824), // CLASTB_ZPZ_B
2163 UINT64_C(99188736), // CLASTB_ZPZ_D
2164 UINT64_C(90800128), // CLASTB_ZPZ_H
2165 UINT64_C(94994432), // CLASTB_ZPZ_S
2166 UINT64_C(3573755999), // CLREX
2167 UINT64_C(1522537472), // CLSWr
2168 UINT64_C(3670021120), // CLSXr
2169 UINT64_C(68722688), // CLS_ZPmZ_B
2170 UINT64_C(81305600), // CLS_ZPmZ_D
2171 UINT64_C(72916992), // CLS_ZPmZ_H
2172 UINT64_C(77111296), // CLS_ZPmZ_S
2173 UINT64_C(67674112), // CLS_ZPzZ_B
2174 UINT64_C(80257024), // CLS_ZPzZ_D
2175 UINT64_C(71868416), // CLS_ZPzZ_H
2176 UINT64_C(76062720), // CLS_ZPzZ_S
2177 UINT64_C(1310738432), // CLSv16i8
2178 UINT64_C(245385216), // CLSv2i32
2179 UINT64_C(241190912), // CLSv4i16
2180 UINT64_C(1319127040), // CLSv4i32
2181 UINT64_C(1314932736), // CLSv8i16
2182 UINT64_C(236996608), // CLSv8i8
2183 UINT64_C(1522536448), // CLZWr
2184 UINT64_C(3670020096), // CLZXr
2185 UINT64_C(68788224), // CLZ_ZPmZ_B
2186 UINT64_C(81371136), // CLZ_ZPmZ_D
2187 UINT64_C(72982528), // CLZ_ZPmZ_H
2188 UINT64_C(77176832), // CLZ_ZPmZ_S
2189 UINT64_C(67739648), // CLZ_ZPzZ_B
2190 UINT64_C(80322560), // CLZ_ZPzZ_D
2191 UINT64_C(71933952), // CLZ_ZPzZ_H
2192 UINT64_C(76128256), // CLZ_ZPzZ_S
2193 UINT64_C(1847609344), // CLZv16i8
2194 UINT64_C(782256128), // CLZv2i32
2195 UINT64_C(778061824), // CLZv4i16
2196 UINT64_C(1855997952), // CLZv4i32
2197 UINT64_C(1851803648), // CLZv8i16
2198 UINT64_C(773867520), // CLZv8i8
2199 UINT64_C(1847626752), // CMEQv16i8
2200 UINT64_C(1310758912), // CMEQv16i8rz
2201 UINT64_C(2128645120), // CMEQv1i64
2202 UINT64_C(1591777280), // CMEQv1i64rz
2203 UINT64_C(782273536), // CMEQv2i32
2204 UINT64_C(245405696), // CMEQv2i32rz
2205 UINT64_C(1860209664), // CMEQv2i64
2206 UINT64_C(1323341824), // CMEQv2i64rz
2207 UINT64_C(778079232), // CMEQv4i16
2208 UINT64_C(241211392), // CMEQv4i16rz
2209 UINT64_C(1856015360), // CMEQv4i32
2210 UINT64_C(1319147520), // CMEQv4i32rz
2211 UINT64_C(1851821056), // CMEQv8i16
2212 UINT64_C(1314953216), // CMEQv8i16rz
2213 UINT64_C(773884928), // CMEQv8i8
2214 UINT64_C(237017088), // CMEQv8i8rz
2215 UINT64_C(1310735360), // CMGEv16i8
2216 UINT64_C(1847625728), // CMGEv16i8rz
2217 UINT64_C(1591753728), // CMGEv1i64
2218 UINT64_C(2128644096), // CMGEv1i64rz
2219 UINT64_C(245382144), // CMGEv2i32
2220 UINT64_C(782272512), // CMGEv2i32rz
2221 UINT64_C(1323318272), // CMGEv2i64
2222 UINT64_C(1860208640), // CMGEv2i64rz
2223 UINT64_C(241187840), // CMGEv4i16
2224 UINT64_C(778078208), // CMGEv4i16rz
2225 UINT64_C(1319123968), // CMGEv4i32
2226 UINT64_C(1856014336), // CMGEv4i32rz
2227 UINT64_C(1314929664), // CMGEv8i16
2228 UINT64_C(1851820032), // CMGEv8i16rz
2229 UINT64_C(236993536), // CMGEv8i8
2230 UINT64_C(773883904), // CMGEv8i8rz
2231 UINT64_C(1310733312), // CMGTv16i8
2232 UINT64_C(1310754816), // CMGTv16i8rz
2233 UINT64_C(1591751680), // CMGTv1i64
2234 UINT64_C(1591773184), // CMGTv1i64rz
2235 UINT64_C(245380096), // CMGTv2i32
2236 UINT64_C(245401600), // CMGTv2i32rz
2237 UINT64_C(1323316224), // CMGTv2i64
2238 UINT64_C(1323337728), // CMGTv2i64rz
2239 UINT64_C(241185792), // CMGTv4i16
2240 UINT64_C(241207296), // CMGTv4i16rz
2241 UINT64_C(1319121920), // CMGTv4i32
2242 UINT64_C(1319143424), // CMGTv4i32rz
2243 UINT64_C(1314927616), // CMGTv8i16
2244 UINT64_C(1314949120), // CMGTv8i16rz
2245 UINT64_C(236991488), // CMGTv8i8
2246 UINT64_C(237012992), // CMGTv8i8rz
2247 UINT64_C(1847604224), // CMHIv16i8
2248 UINT64_C(2128622592), // CMHIv1i64
2249 UINT64_C(782251008), // CMHIv2i32
2250 UINT64_C(1860187136), // CMHIv2i64
2251 UINT64_C(778056704), // CMHIv4i16
2252 UINT64_C(1855992832), // CMHIv4i32
2253 UINT64_C(1851798528), // CMHIv8i16
2254 UINT64_C(773862400), // CMHIv8i8
2255 UINT64_C(1847606272), // CMHSv16i8
2256 UINT64_C(2128624640), // CMHSv1i64
2257 UINT64_C(782253056), // CMHSv2i32
2258 UINT64_C(1860189184), // CMHSv2i64
2259 UINT64_C(778058752), // CMHSv4i16
2260 UINT64_C(1855994880), // CMHSv4i32
2261 UINT64_C(1851800576), // CMHSv8i16
2262 UINT64_C(773864448), // CMHSv8i8
2263 UINT64_C(1151361024), // CMLA_ZZZI_H
2264 UINT64_C(1155555328), // CMLA_ZZZI_S
2265 UINT64_C(1140858880), // CMLA_ZZZ_B
2266 UINT64_C(1153441792), // CMLA_ZZZ_D
2267 UINT64_C(1145053184), // CMLA_ZZZ_H
2268 UINT64_C(1149247488), // CMLA_ZZZ_S
2269 UINT64_C(1847629824), // CMLEv16i8rz
2270 UINT64_C(2128648192), // CMLEv1i64rz
2271 UINT64_C(782276608), // CMLEv2i32rz
2272 UINT64_C(1860212736), // CMLEv2i64rz
2273 UINT64_C(778082304), // CMLEv4i16rz
2274 UINT64_C(1856018432), // CMLEv4i32rz
2275 UINT64_C(1851824128), // CMLEv8i16rz
2276 UINT64_C(773888000), // CMLEv8i8rz
2277 UINT64_C(1310763008), // CMLTv16i8rz
2278 UINT64_C(1591781376), // CMLTv1i64rz
2279 UINT64_C(245409792), // CMLTv2i32rz
2280 UINT64_C(1323345920), // CMLTv2i64rz
2281 UINT64_C(241215488), // CMLTv4i16rz
2282 UINT64_C(1319151616), // CMLTv4i32rz
2283 UINT64_C(1314957312), // CMLTv8i16rz
2284 UINT64_C(237021184), // CMLTv8i8rz
2285 UINT64_C(620789760), // CMPEQ_PPzZI_B
2286 UINT64_C(633372672), // CMPEQ_PPzZI_D
2287 UINT64_C(624984064), // CMPEQ_PPzZI_H
2288 UINT64_C(629178368), // CMPEQ_PPzZI_S
2289 UINT64_C(604020736), // CMPEQ_PPzZZ_B
2290 UINT64_C(616603648), // CMPEQ_PPzZZ_D
2291 UINT64_C(608215040), // CMPEQ_PPzZZ_H
2292 UINT64_C(612409344), // CMPEQ_PPzZZ_S
2293 UINT64_C(603987968), // CMPEQ_WIDE_PPzZZ_B
2294 UINT64_C(608182272), // CMPEQ_WIDE_PPzZZ_H
2295 UINT64_C(612376576), // CMPEQ_WIDE_PPzZZ_S
2296 UINT64_C(620756992), // CMPGE_PPzZI_B
2297 UINT64_C(633339904), // CMPGE_PPzZI_D
2298 UINT64_C(624951296), // CMPGE_PPzZI_H
2299 UINT64_C(629145600), // CMPGE_PPzZI_S
2300 UINT64_C(604012544), // CMPGE_PPzZZ_B
2301 UINT64_C(616595456), // CMPGE_PPzZZ_D
2302 UINT64_C(608206848), // CMPGE_PPzZZ_H
2303 UINT64_C(612401152), // CMPGE_PPzZZ_S
2304 UINT64_C(603996160), // CMPGE_WIDE_PPzZZ_B
2305 UINT64_C(608190464), // CMPGE_WIDE_PPzZZ_H
2306 UINT64_C(612384768), // CMPGE_WIDE_PPzZZ_S
2307 UINT64_C(620757008), // CMPGT_PPzZI_B
2308 UINT64_C(633339920), // CMPGT_PPzZI_D
2309 UINT64_C(624951312), // CMPGT_PPzZI_H
2310 UINT64_C(629145616), // CMPGT_PPzZI_S
2311 UINT64_C(604012560), // CMPGT_PPzZZ_B
2312 UINT64_C(616595472), // CMPGT_PPzZZ_D
2313 UINT64_C(608206864), // CMPGT_PPzZZ_H
2314 UINT64_C(612401168), // CMPGT_PPzZZ_S
2315 UINT64_C(603996176), // CMPGT_WIDE_PPzZZ_B
2316 UINT64_C(608190480), // CMPGT_WIDE_PPzZZ_H
2317 UINT64_C(612384784), // CMPGT_WIDE_PPzZZ_S
2318 UINT64_C(606076944), // CMPHI_PPzZI_B
2319 UINT64_C(618659856), // CMPHI_PPzZI_D
2320 UINT64_C(610271248), // CMPHI_PPzZI_H
2321 UINT64_C(614465552), // CMPHI_PPzZI_S
2322 UINT64_C(603979792), // CMPHI_PPzZZ_B
2323 UINT64_C(616562704), // CMPHI_PPzZZ_D
2324 UINT64_C(608174096), // CMPHI_PPzZZ_H
2325 UINT64_C(612368400), // CMPHI_PPzZZ_S
2326 UINT64_C(604028944), // CMPHI_WIDE_PPzZZ_B
2327 UINT64_C(608223248), // CMPHI_WIDE_PPzZZ_H
2328 UINT64_C(612417552), // CMPHI_WIDE_PPzZZ_S
2329 UINT64_C(606076928), // CMPHS_PPzZI_B
2330 UINT64_C(618659840), // CMPHS_PPzZI_D
2331 UINT64_C(610271232), // CMPHS_PPzZI_H
2332 UINT64_C(614465536), // CMPHS_PPzZI_S
2333 UINT64_C(603979776), // CMPHS_PPzZZ_B
2334 UINT64_C(616562688), // CMPHS_PPzZZ_D
2335 UINT64_C(608174080), // CMPHS_PPzZZ_H
2336 UINT64_C(612368384), // CMPHS_PPzZZ_S
2337 UINT64_C(604028928), // CMPHS_WIDE_PPzZZ_B
2338 UINT64_C(608223232), // CMPHS_WIDE_PPzZZ_H
2339 UINT64_C(612417536), // CMPHS_WIDE_PPzZZ_S
2340 UINT64_C(620765200), // CMPLE_PPzZI_B
2341 UINT64_C(633348112), // CMPLE_PPzZI_D
2342 UINT64_C(624959504), // CMPLE_PPzZI_H
2343 UINT64_C(629153808), // CMPLE_PPzZI_S
2344 UINT64_C(604004368), // CMPLE_WIDE_PPzZZ_B
2345 UINT64_C(608198672), // CMPLE_WIDE_PPzZZ_H
2346 UINT64_C(612392976), // CMPLE_WIDE_PPzZZ_S
2347 UINT64_C(606085120), // CMPLO_PPzZI_B
2348 UINT64_C(618668032), // CMPLO_PPzZI_D
2349 UINT64_C(610279424), // CMPLO_PPzZI_H
2350 UINT64_C(614473728), // CMPLO_PPzZI_S
2351 UINT64_C(604037120), // CMPLO_WIDE_PPzZZ_B
2352 UINT64_C(608231424), // CMPLO_WIDE_PPzZZ_H
2353 UINT64_C(612425728), // CMPLO_WIDE_PPzZZ_S
2354 UINT64_C(606085136), // CMPLS_PPzZI_B
2355 UINT64_C(618668048), // CMPLS_PPzZI_D
2356 UINT64_C(610279440), // CMPLS_PPzZI_H
2357 UINT64_C(614473744), // CMPLS_PPzZI_S
2358 UINT64_C(604037136), // CMPLS_WIDE_PPzZZ_B
2359 UINT64_C(608231440), // CMPLS_WIDE_PPzZZ_H
2360 UINT64_C(612425744), // CMPLS_WIDE_PPzZZ_S
2361 UINT64_C(620765184), // CMPLT_PPzZI_B
2362 UINT64_C(633348096), // CMPLT_PPzZI_D
2363 UINT64_C(624959488), // CMPLT_PPzZI_H
2364 UINT64_C(629153792), // CMPLT_PPzZI_S
2365 UINT64_C(604004352), // CMPLT_WIDE_PPzZZ_B
2366 UINT64_C(608198656), // CMPLT_WIDE_PPzZZ_H
2367 UINT64_C(612392960), // CMPLT_WIDE_PPzZZ_S
2368 UINT64_C(620789776), // CMPNE_PPzZI_B
2369 UINT64_C(633372688), // CMPNE_PPzZI_D
2370 UINT64_C(624984080), // CMPNE_PPzZI_H
2371 UINT64_C(629178384), // CMPNE_PPzZI_S
2372 UINT64_C(604020752), // CMPNE_PPzZZ_B
2373 UINT64_C(616603664), // CMPNE_PPzZZ_D
2374 UINT64_C(608215056), // CMPNE_PPzZZ_H
2375 UINT64_C(612409360), // CMPNE_PPzZZ_S
2376 UINT64_C(603987984), // CMPNE_WIDE_PPzZZ_B
2377 UINT64_C(608182288), // CMPNE_WIDE_PPzZZ_H
2378 UINT64_C(612376592), // CMPNE_WIDE_PPzZZ_S
2379 UINT64_C(1310755840), // CMTSTv16i8
2380 UINT64_C(1591774208), // CMTSTv1i64
2381 UINT64_C(245402624), // CMTSTv2i32
2382 UINT64_C(1323338752), // CMTSTv2i64
2383 UINT64_C(241208320), // CMTSTv4i16
2384 UINT64_C(1319144448), // CMTSTv4i32
2385 UINT64_C(1314950144), // CMTSTv8i16
2386 UINT64_C(237014016), // CMTSTv8i8
2387 UINT64_C(68919296), // CNOT_ZPmZ_B
2388 UINT64_C(81502208), // CNOT_ZPmZ_D
2389 UINT64_C(73113600), // CNOT_ZPmZ_H
2390 UINT64_C(77307904), // CNOT_ZPmZ_S
2391 UINT64_C(67870720), // CNOT_ZPzZ_B
2392 UINT64_C(80453632), // CNOT_ZPzZ_D
2393 UINT64_C(72065024), // CNOT_ZPzZ_H
2394 UINT64_C(76259328), // CNOT_ZPzZ_S
2395 UINT64_C(69263360), // CNTB_XPiI
2396 UINT64_C(81846272), // CNTD_XPiI
2397 UINT64_C(73457664), // CNTH_XPiI
2398 UINT64_C(622887424), // CNTP_XCI_B
2399 UINT64_C(635470336), // CNTP_XCI_D
2400 UINT64_C(627081728), // CNTP_XCI_H
2401 UINT64_C(631276032), // CNTP_XCI_S
2402 UINT64_C(622886912), // CNTP_XPP_B
2403 UINT64_C(635469824), // CNTP_XPP_D
2404 UINT64_C(627081216), // CNTP_XPP_H
2405 UINT64_C(631275520), // CNTP_XPP_S
2406 UINT64_C(77651968), // CNTW_XPiI
2407 UINT64_C(1522539520), // CNTWr
2408 UINT64_C(3670023168), // CNTXr
2409 UINT64_C(68853760), // CNT_ZPmZ_B
2410 UINT64_C(81436672), // CNT_ZPmZ_D
2411 UINT64_C(73048064), // CNT_ZPmZ_H
2412 UINT64_C(77242368), // CNT_ZPmZ_S
2413 UINT64_C(67805184), // CNT_ZPzZ_B
2414 UINT64_C(80388096), // CNT_ZPzZ_D
2415 UINT64_C(71999488), // CNT_ZPzZ_H
2416 UINT64_C(76193792), // CNT_ZPzZ_S
2417 UINT64_C(1310742528), // CNTv16i8
2418 UINT64_C(237000704), // CNTv8i8
2419 UINT64_C(86081536), // COMPACT_ZPZ_B
2420 UINT64_C(98664448), // COMPACT_ZPZ_D
2421 UINT64_C(90275840), // COMPACT_ZPZ_H
2422 UINT64_C(94470144), // COMPACT_ZPZ_S
2423 UINT64_C(494928896), // CPYE
2424 UINT64_C(494978048), // CPYEN
2425 UINT64_C(494961664), // CPYERN
2426 UINT64_C(494937088), // CPYERT
2427 UINT64_C(494986240), // CPYERTN
2428 UINT64_C(494969856), // CPYERTRN
2429 UINT64_C(494953472), // CPYERTWN
2430 UINT64_C(494941184), // CPYET
2431 UINT64_C(494990336), // CPYETN
2432 UINT64_C(494973952), // CPYETRN
2433 UINT64_C(494957568), // CPYETWN
2434 UINT64_C(494945280), // CPYEWN
2435 UINT64_C(494932992), // CPYEWT
2436 UINT64_C(494982144), // CPYEWTN
2437 UINT64_C(494965760), // CPYEWTRN
2438 UINT64_C(494949376), // CPYEWTWN
2439 UINT64_C(427820032), // CPYFE
2440 UINT64_C(427869184), // CPYFEN
2441 UINT64_C(427852800), // CPYFERN
2442 UINT64_C(427828224), // CPYFERT
2443 UINT64_C(427877376), // CPYFERTN
2444 UINT64_C(427860992), // CPYFERTRN
2445 UINT64_C(427844608), // CPYFERTWN
2446 UINT64_C(427832320), // CPYFET
2447 UINT64_C(427881472), // CPYFETN
2448 UINT64_C(427865088), // CPYFETRN
2449 UINT64_C(427848704), // CPYFETWN
2450 UINT64_C(427836416), // CPYFEWN
2451 UINT64_C(427824128), // CPYFEWT
2452 UINT64_C(427873280), // CPYFEWTN
2453 UINT64_C(427856896), // CPYFEWTRN
2454 UINT64_C(427840512), // CPYFEWTWN
2455 UINT64_C(423625728), // CPYFM
2456 UINT64_C(423674880), // CPYFMN
2457 UINT64_C(423658496), // CPYFMRN
2458 UINT64_C(423633920), // CPYFMRT
2459 UINT64_C(423683072), // CPYFMRTN
2460 UINT64_C(423666688), // CPYFMRTRN
2461 UINT64_C(423650304), // CPYFMRTWN
2462 UINT64_C(423638016), // CPYFMT
2463 UINT64_C(423687168), // CPYFMTN
2464 UINT64_C(423670784), // CPYFMTRN
2465 UINT64_C(423654400), // CPYFMTWN
2466 UINT64_C(423642112), // CPYFMWN
2467 UINT64_C(423629824), // CPYFMWT
2468 UINT64_C(423678976), // CPYFMWTN
2469 UINT64_C(423662592), // CPYFMWTRN
2470 UINT64_C(423646208), // CPYFMWTWN
2471 UINT64_C(419431424), // CPYFP
2472 UINT64_C(419480576), // CPYFPN
2473 UINT64_C(419464192), // CPYFPRN
2474 UINT64_C(419439616), // CPYFPRT
2475 UINT64_C(419488768), // CPYFPRTN
2476 UINT64_C(419472384), // CPYFPRTRN
2477 UINT64_C(419456000), // CPYFPRTWN
2478 UINT64_C(419443712), // CPYFPT
2479 UINT64_C(419492864), // CPYFPTN
2480 UINT64_C(419476480), // CPYFPTRN
2481 UINT64_C(419460096), // CPYFPTWN
2482 UINT64_C(419447808), // CPYFPWN
2483 UINT64_C(419435520), // CPYFPWT
2484 UINT64_C(419484672), // CPYFPWTN
2485 UINT64_C(419468288), // CPYFPWTRN
2486 UINT64_C(419451904), // CPYFPWTWN
2487 UINT64_C(490734592), // CPYM
2488 UINT64_C(490783744), // CPYMN
2489 UINT64_C(490767360), // CPYMRN
2490 UINT64_C(490742784), // CPYMRT
2491 UINT64_C(490791936), // CPYMRTN
2492 UINT64_C(490775552), // CPYMRTRN
2493 UINT64_C(490759168), // CPYMRTWN
2494 UINT64_C(490746880), // CPYMT
2495 UINT64_C(490796032), // CPYMTN
2496 UINT64_C(490779648), // CPYMTRN
2497 UINT64_C(490763264), // CPYMTWN
2498 UINT64_C(490750976), // CPYMWN
2499 UINT64_C(490738688), // CPYMWT
2500 UINT64_C(490787840), // CPYMWTN
2501 UINT64_C(490771456), // CPYMWTRN
2502 UINT64_C(490755072), // CPYMWTWN
2503 UINT64_C(486540288), // CPYP
2504 UINT64_C(486589440), // CPYPN
2505 UINT64_C(486573056), // CPYPRN
2506 UINT64_C(486548480), // CPYPRT
2507 UINT64_C(486597632), // CPYPRTN
2508 UINT64_C(486581248), // CPYPRTRN
2509 UINT64_C(486564864), // CPYPRTWN
2510 UINT64_C(486552576), // CPYPT
2511 UINT64_C(486601728), // CPYPTN
2512 UINT64_C(486585344), // CPYPTRN
2513 UINT64_C(486568960), // CPYPTWN
2514 UINT64_C(486556672), // CPYPWN
2515 UINT64_C(486544384), // CPYPWT
2516 UINT64_C(486593536), // CPYPWTN
2517 UINT64_C(486577152), // CPYPWTRN
2518 UINT64_C(486560768), // CPYPWTWN
2519 UINT64_C(84951040), // CPY_ZPmI_B
2520 UINT64_C(97533952), // CPY_ZPmI_D
2521 UINT64_C(89145344), // CPY_ZPmI_H
2522 UINT64_C(93339648), // CPY_ZPmI_S
2523 UINT64_C(86548480), // CPY_ZPmR_B
2524 UINT64_C(99131392), // CPY_ZPmR_D
2525 UINT64_C(90742784), // CPY_ZPmR_H
2526 UINT64_C(94937088), // CPY_ZPmR_S
2527 UINT64_C(86016000), // CPY_ZPmV_B
2528 UINT64_C(98598912), // CPY_ZPmV_D
2529 UINT64_C(90210304), // CPY_ZPmV_H
2530 UINT64_C(94404608), // CPY_ZPmV_S
2531 UINT64_C(84934656), // CPY_ZPzI_B
2532 UINT64_C(97517568), // CPY_ZPzI_D
2533 UINT64_C(89128960), // CPY_ZPzI_H
2534 UINT64_C(93323264), // CPY_ZPzI_S
2535 UINT64_C(448806912), // CRC32Brr
2536 UINT64_C(448811008), // CRC32CBrr
2537 UINT64_C(448812032), // CRC32CHrr
2538 UINT64_C(448813056), // CRC32CWrr
2539 UINT64_C(2596297728), // CRC32CXrr
2540 UINT64_C(448807936), // CRC32Hrr
2541 UINT64_C(448808960), // CRC32Wrr
2542 UINT64_C(2596293632), // CRC32Xrr
2543 UINT64_C(444596224), // CSELWr
2544 UINT64_C(2592079872), // CSELXr
2545 UINT64_C(444597248), // CSINCWr
2546 UINT64_C(2592080896), // CSINCXr
2547 UINT64_C(1518338048), // CSINVWr
2548 UINT64_C(3665821696), // CSINVXr
2549 UINT64_C(1518339072), // CSNEGWr
2550 UINT64_C(3665822720), // CSNEGXr
2551 UINT64_C(631250944), // CTERMEQ_WW
2552 UINT64_C(635445248), // CTERMEQ_XX
2553 UINT64_C(631250960), // CTERMNE_WW
2554 UINT64_C(635445264), // CTERMNE_XX
2555 UINT64_C(1522538496), // CTZWr
2556 UINT64_C(3670022144), // CTZXr
2557 UINT64_C(3567255553), // DCPS1
2558 UINT64_C(3567255554), // DCPS2
2559 UINT64_C(3567255555), // DCPS3
2560 UINT64_C(70312960), // DECB_XPiI
2561 UINT64_C(82895872), // DECD_XPiI
2562 UINT64_C(82887680), // DECD_ZPiI
2563 UINT64_C(74507264), // DECH_XPiI
2564 UINT64_C(74499072), // DECH_ZPiI
2565 UINT64_C(623740928), // DECP_XP_B
2566 UINT64_C(636323840), // DECP_XP_D
2567 UINT64_C(627935232), // DECP_XP_H
2568 UINT64_C(632129536), // DECP_XP_S
2569 UINT64_C(636321792), // DECP_ZP_D
2570 UINT64_C(627933184), // DECP_ZP_H
2571 UINT64_C(632127488), // DECP_ZP_S
2572 UINT64_C(78701568), // DECW_XPiI
2573 UINT64_C(78693376), // DECW_ZPiI
2574 UINT64_C(3573756095), // DMB
2575 UINT64_C(3602842592), // DRPS
2576 UINT64_C(3573756063), // DSB
2577 UINT64_C(3573756479), // DSBnXS
2578 UINT64_C(96468992), // DUPM_ZI
2579 UINT64_C(86057984), // DUPQ_ZZI_B
2580 UINT64_C(86516736), // DUPQ_ZZI_D
2581 UINT64_C(86123520), // DUPQ_ZZI_H
2582 UINT64_C(86254592), // DUPQ_ZZI_S
2583 UINT64_C(624476160), // DUP_ZI_B
2584 UINT64_C(637059072), // DUP_ZI_D
2585 UINT64_C(628670464), // DUP_ZI_H
2586 UINT64_C(632864768), // DUP_ZI_S
2587 UINT64_C(85997568), // DUP_ZR_B
2588 UINT64_C(98580480), // DUP_ZR_D
2589 UINT64_C(90191872), // DUP_ZR_H
2590 UINT64_C(94386176), // DUP_ZR_S
2591 UINT64_C(86056960), // DUP_ZZI_B
2592 UINT64_C(86515712), // DUP_ZZI_D
2593 UINT64_C(86122496), // DUP_ZZI_H
2594 UINT64_C(87040000), // DUP_ZZI_Q
2595 UINT64_C(86253568), // DUP_ZZI_S
2596 UINT64_C(1577190400), // DUPi16
2597 UINT64_C(1577321472), // DUPi32
2598 UINT64_C(1577583616), // DUPi64
2599 UINT64_C(1577124864), // DUPi8
2600 UINT64_C(1308691456), // DUPv16i8gpr
2601 UINT64_C(1308689408), // DUPv16i8lane
2602 UINT64_C(235146240), // DUPv2i32gpr
2603 UINT64_C(235144192), // DUPv2i32lane
2604 UINT64_C(1309150208), // DUPv2i64gpr
2605 UINT64_C(1309148160), // DUPv2i64lane
2606 UINT64_C(235015168), // DUPv4i16gpr
2607 UINT64_C(235013120), // DUPv4i16lane
2608 UINT64_C(1308888064), // DUPv4i32gpr
2609 UINT64_C(1308886016), // DUPv4i32lane
2610 UINT64_C(1308756992), // DUPv8i16gpr
2611 UINT64_C(1308754944), // DUPv8i16lane
2612 UINT64_C(234949632), // DUPv8i8gpr
2613 UINT64_C(234947584), // DUPv8i8lane
2614 UINT64_C(1243611136), // EONWrs
2615 UINT64_C(3391094784), // EONXrs
2616 UINT64_C(3456106496), // EOR3
2617 UINT64_C(69220352), // EOR3_ZZZZ
2618 UINT64_C(1157664768), // EORBT_ZZZ_B
2619 UINT64_C(1170247680), // EORBT_ZZZ_D
2620 UINT64_C(1161859072), // EORBT_ZZZ_H
2621 UINT64_C(1166053376), // EORBT_ZZZ_S
2622 UINT64_C(69017600), // EORQV_VPZ_B
2623 UINT64_C(81600512), // EORQV_VPZ_D
2624 UINT64_C(73211904), // EORQV_VPZ_H
2625 UINT64_C(77406208), // EORQV_VPZ_S
2626 UINT64_C(624968192), // EORS_PPzPP
2627 UINT64_C(1157665792), // EORTB_ZZZ_B
2628 UINT64_C(1170248704), // EORTB_ZZZ_D
2629 UINT64_C(1161860096), // EORTB_ZZZ_H
2630 UINT64_C(1166054400), // EORTB_ZZZ_S
2631 UINT64_C(68755456), // EORV_VPZ_B
2632 UINT64_C(81338368), // EORV_VPZ_D
2633 UINT64_C(72949760), // EORV_VPZ_H
2634 UINT64_C(77144064), // EORV_VPZ_S
2635 UINT64_C(1375731712), // EORWri
2636 UINT64_C(1241513984), // EORWrs
2637 UINT64_C(3523215360), // EORXri
2638 UINT64_C(3388997632), // EORXrs
2639 UINT64_C(620773888), // EOR_PPzPP
2640 UINT64_C(88080384), // EOR_ZI
2641 UINT64_C(68747264), // EOR_ZPmZ_B
2642 UINT64_C(81330176), // EOR_ZPmZ_D
2643 UINT64_C(72941568), // EOR_ZPmZ_H
2644 UINT64_C(77135872), // EOR_ZPmZ_S
2645 UINT64_C(77606912), // EOR_ZZZ
2646 UINT64_C(1847598080), // EORv16i8
2647 UINT64_C(773856256), // EORv8i8
2648 UINT64_C(3600745440), // ERET
2649 UINT64_C(3600747519), // ERETAA
2650 UINT64_C(3600748543), // ERETAB
2651 UINT64_C(87130112), // EXPAND_ZPZ_B
2652 UINT64_C(99713024), // EXPAND_ZPZ_D
2653 UINT64_C(91324416), // EXPAND_ZPZ_H
2654 UINT64_C(95518720), // EXPAND_ZPZ_S
2655 UINT64_C(90186752), // EXTQ_ZZI
2656 UINT64_C(3221356544), // EXTRACT_ZPMXI_H_B
2657 UINT64_C(3233939456), // EXTRACT_ZPMXI_H_D
2658 UINT64_C(3225550848), // EXTRACT_ZPMXI_H_H
2659 UINT64_C(3234004992), // EXTRACT_ZPMXI_H_Q
2660 UINT64_C(3229745152), // EXTRACT_ZPMXI_H_S
2661 UINT64_C(3221389312), // EXTRACT_ZPMXI_V_B
2662 UINT64_C(3233972224), // EXTRACT_ZPMXI_V_D
2663 UINT64_C(3225583616), // EXTRACT_ZPMXI_V_H
2664 UINT64_C(3234037760), // EXTRACT_ZPMXI_V_Q
2665 UINT64_C(3229777920), // EXTRACT_ZPMXI_V_S
2666 UINT64_C(327155712), // EXTRWrri
2667 UINT64_C(2478833664), // EXTRXrri
2668 UINT64_C(85983232), // EXT_ZZI
2669 UINT64_C(90177536), // EXT_ZZI_B
2670 UINT64_C(1845493760), // EXTv16i8
2671 UINT64_C(771751936), // EXTv8i8
2672 UINT64_C(773945344), // F1CVTL
2673 UINT64_C(1847687168), // F1CVTL2
2674 UINT64_C(1695100928), // F1CVTLT_ZZ_BtoH
2675 UINT64_C(3240550401), // F1CVTL_2ZZ_BtoH
2676 UINT64_C(3240550400), // F1CVT_2ZZ_BtoH
2677 UINT64_C(1695035392), // F1CVT_ZZ_BtoH
2678 UINT64_C(778139648), // F2CVTL
2679 UINT64_C(1851881472), // F2CVTL2
2680 UINT64_C(1695101952), // F2CVTLT_ZZ_BtoH
2681 UINT64_C(3248939009), // F2CVTL_2ZZ_BtoH
2682 UINT64_C(3248939008), // F2CVT_2ZZ_BtoH
2683 UINT64_C(1695036416), // F2CVT_ZZ_BtoH
2684 UINT64_C(2126517248), // FABD16
2685 UINT64_C(2124469248), // FABD32
2686 UINT64_C(2128663552), // FABD64
2687 UINT64_C(1707638784), // FABD_ZPmZ_D
2688 UINT64_C(1699250176), // FABD_ZPmZ_H
2689 UINT64_C(1703444480), // FABD_ZPmZ_S
2690 UINT64_C(782291968), // FABDv2f32
2691 UINT64_C(1860228096), // FABDv2f64
2692 UINT64_C(784339968), // FABDv4f16
2693 UINT64_C(1856033792), // FABDv4f32
2694 UINT64_C(1858081792), // FABDv8f16
2695 UINT64_C(509657088), // FABSDr
2696 UINT64_C(518045696), // FABSHr
2697 UINT64_C(505462784), // FABSSr
2698 UINT64_C(81567744), // FABS_ZPmZ_D
2699 UINT64_C(73179136), // FABS_ZPmZ_H
2700 UINT64_C(77373440), // FABS_ZPmZ_S
2701 UINT64_C(80519168), // FABS_ZPzZ_D
2702 UINT64_C(72130560), // FABS_ZPzZ_H
2703 UINT64_C(76324864), // FABS_ZPzZ_S
2704 UINT64_C(245430272), // FABSv2f32
2705 UINT64_C(1323366400), // FABSv2f64
2706 UINT64_C(251197440), // FABSv4f16
2707 UINT64_C(1319172096), // FABSv4f32
2708 UINT64_C(1324939264), // FABSv8f16
2709 UINT64_C(2118134784), // FACGE16
2710 UINT64_C(2116086784), // FACGE32
2711 UINT64_C(2120281088), // FACGE64
2712 UINT64_C(1707130896), // FACGE_PPzZZ_D
2713 UINT64_C(1698742288), // FACGE_PPzZZ_H
2714 UINT64_C(1702936592), // FACGE_PPzZZ_S
2715 UINT64_C(773909504), // FACGEv2f32
2716 UINT64_C(1851845632), // FACGEv2f64
2717 UINT64_C(775957504), // FACGEv4f16
2718 UINT64_C(1847651328), // FACGEv4f32
2719 UINT64_C(1849699328), // FACGEv8f16
2720 UINT64_C(2126523392), // FACGT16
2721 UINT64_C(2124475392), // FACGT32
2722 UINT64_C(2128669696), // FACGT64
2723 UINT64_C(1707139088), // FACGT_PPzZZ_D
2724 UINT64_C(1698750480), // FACGT_PPzZZ_H
2725 UINT64_C(1702944784), // FACGT_PPzZZ_S
2726 UINT64_C(782298112), // FACGTv2f32
2727 UINT64_C(1860234240), // FACGTv2f64
2728 UINT64_C(784346112), // FACGTv4f16
2729 UINT64_C(1856039936), // FACGTv4f32
2730 UINT64_C(1858087936), // FACGTv8f16
2731 UINT64_C(1708662784), // FADDA_VPZ_D
2732 UINT64_C(1700274176), // FADDA_VPZ_H
2733 UINT64_C(1704468480), // FADDA_VPZ_S
2734 UINT64_C(509618176), // FADDDrr
2735 UINT64_C(518006784), // FADDHrr
2736 UINT64_C(1691385856), // FADDP_ZPmZZ_D
2737 UINT64_C(1682997248), // FADDP_ZPmZZ_H
2738 UINT64_C(1687191552), // FADDP_ZPmZZ_S
2739 UINT64_C(773903360), // FADDPv2f32
2740 UINT64_C(1851839488), // FADDPv2f64
2741 UINT64_C(1580259328), // FADDPv2i16p
2742 UINT64_C(2117130240), // FADDPv2i32p
2743 UINT64_C(2121324544), // FADDPv2i64p
2744 UINT64_C(775951360), // FADDPv4f16
2745 UINT64_C(1847645184), // FADDPv4f32
2746 UINT64_C(1849693184), // FADDPv8f16
2747 UINT64_C(1691394048), // FADDQV_D
2748 UINT64_C(1683005440), // FADDQV_H
2749 UINT64_C(1687199744), // FADDQV_S
2750 UINT64_C(505423872), // FADDSrr
2751 UINT64_C(1707089920), // FADDV_VPZ_D
2752 UINT64_C(1698701312), // FADDV_VPZ_H
2753 UINT64_C(1702895616), // FADDV_VPZ_S
2754 UINT64_C(3252689920), // FADD_VG2_M2Z_D
2755 UINT64_C(3248757760), // FADD_VG2_M2Z_H
2756 UINT64_C(3248495616), // FADD_VG2_M2Z_S
2757 UINT64_C(3252755456), // FADD_VG4_M4Z_D
2758 UINT64_C(3248823296), // FADD_VG4_M4Z_H
2759 UINT64_C(3248561152), // FADD_VG4_M4Z_S
2760 UINT64_C(1708687360), // FADD_ZPmI_D
2761 UINT64_C(1700298752), // FADD_ZPmI_H
2762 UINT64_C(1704493056), // FADD_ZPmI_S
2763 UINT64_C(1707114496), // FADD_ZPmZ_D
2764 UINT64_C(1698725888), // FADD_ZPmZ_H
2765 UINT64_C(1702920192), // FADD_ZPmZ_S
2766 UINT64_C(1707081728), // FADD_ZZZ_D
2767 UINT64_C(1698693120), // FADD_ZZZ_H
2768 UINT64_C(1702887424), // FADD_ZZZ_S
2769 UINT64_C(237032448), // FADDv2f32
2770 UINT64_C(1314968576), // FADDv2f64
2771 UINT64_C(239080448), // FADDv4f16
2772 UINT64_C(1310774272), // FADDv4f32
2773 UINT64_C(1312822272), // FADDv8f16
2774 UINT64_C(3252728128), // FAMAX_2Z2Z_D
2775 UINT64_C(3244339520), // FAMAX_2Z2Z_H
2776 UINT64_C(3248533824), // FAMAX_2Z2Z_S
2777 UINT64_C(3252730176), // FAMAX_4Z4Z_D
2778 UINT64_C(3244341568), // FAMAX_4Z4Z_H
2779 UINT64_C(3248535872), // FAMAX_4Z4Z_S
2780 UINT64_C(1708032000), // FAMAX_ZPmZ_D
2781 UINT64_C(1699643392), // FAMAX_ZPmZ_H
2782 UINT64_C(1703837696), // FAMAX_ZPmZ_S
2783 UINT64_C(245423104), // FAMAXv2f32
2784 UINT64_C(1323359232), // FAMAXv2f64
2785 UINT64_C(247471104), // FAMAXv4f16
2786 UINT64_C(1319164928), // FAMAXv4f32
2787 UINT64_C(1321212928), // FAMAXv8f16
2788 UINT64_C(3252728129), // FAMIN_2Z2Z_D
2789 UINT64_C(3244339521), // FAMIN_2Z2Z_H
2790 UINT64_C(3248533825), // FAMIN_2Z2Z_S
2791 UINT64_C(3252730177), // FAMIN_4Z4Z_D
2792 UINT64_C(3244341569), // FAMIN_4Z4Z_H
2793 UINT64_C(3248535873), // FAMIN_4Z4Z_S
2794 UINT64_C(1708097536), // FAMIN_ZPmZ_D
2795 UINT64_C(1699708928), // FAMIN_ZPmZ_H
2796 UINT64_C(1703903232), // FAMIN_ZPmZ_S
2797 UINT64_C(782294016), // FAMINv2f32
2798 UINT64_C(1860230144), // FAMINv2f64
2799 UINT64_C(784342016), // FAMINv4f16
2800 UINT64_C(1856035840), // FAMINv4f32
2801 UINT64_C(1858083840), // FAMINv8f16
2802 UINT64_C(1690337280), // FCADD_ZPmZ_D
2803 UINT64_C(1681948672), // FCADD_ZPmZ_H
2804 UINT64_C(1686142976), // FCADD_ZPmZ_S
2805 UINT64_C(780198912), // FCADDv2f32
2806 UINT64_C(1858135040), // FCADDv2f64
2807 UINT64_C(776004608), // FCADDv4f16
2808 UINT64_C(1853940736), // FCADDv4f32
2809 UINT64_C(1849746432), // FCADDv8f16
2810 UINT64_C(509608960), // FCCMPDrr
2811 UINT64_C(509608976), // FCCMPEDrr
2812 UINT64_C(517997584), // FCCMPEHrr
2813 UINT64_C(505414672), // FCCMPESrr
2814 UINT64_C(517997568), // FCCMPHrr
2815 UINT64_C(505414656), // FCCMPSrr
2816 UINT64_C(3252731904), // FCLAMP_VG2_2Z2Z_D
2817 UINT64_C(3244343296), // FCLAMP_VG2_2Z2Z_H
2818 UINT64_C(3248537600), // FCLAMP_VG2_2Z2Z_S
2819 UINT64_C(3252733952), // FCLAMP_VG4_4Z4Z_D
2820 UINT64_C(3244345344), // FCLAMP_VG4_4Z4Z_H
2821 UINT64_C(3248539648), // FCLAMP_VG4_4Z4Z_S
2822 UINT64_C(1692410880), // FCLAMP_ZZZ_D
2823 UINT64_C(1684022272), // FCLAMP_ZZZ_H
2824 UINT64_C(1688216576), // FCLAMP_ZZZ_S
2825 UINT64_C(1581261824), // FCMEQ16
2826 UINT64_C(1579213824), // FCMEQ32
2827 UINT64_C(1583408128), // FCMEQ64
2828 UINT64_C(1708269568), // FCMEQ_PPzZ0_D
2829 UINT64_C(1699880960), // FCMEQ_PPzZ0_H
2830 UINT64_C(1704075264), // FCMEQ_PPzZ0_S
2831 UINT64_C(1707106304), // FCMEQ_PPzZZ_D
2832 UINT64_C(1698717696), // FCMEQ_PPzZZ_H
2833 UINT64_C(1702912000), // FCMEQ_PPzZZ_S
2834 UINT64_C(1593366528), // FCMEQv1i16rz
2835 UINT64_C(1587599360), // FCMEQv1i32rz
2836 UINT64_C(1591793664), // FCMEQv1i64rz
2837 UINT64_C(237036544), // FCMEQv2f32
2838 UINT64_C(1314972672), // FCMEQv2f64
2839 UINT64_C(245422080), // FCMEQv2i32rz
2840 UINT64_C(1323358208), // FCMEQv2i64rz
2841 UINT64_C(239084544), // FCMEQv4f16
2842 UINT64_C(1310778368), // FCMEQv4f32
2843 UINT64_C(251189248), // FCMEQv4i16rz
2844 UINT64_C(1319163904), // FCMEQv4i32rz
2845 UINT64_C(1312826368), // FCMEQv8f16
2846 UINT64_C(1324931072), // FCMEQv8i16rz
2847 UINT64_C(2118132736), // FCMGE16
2848 UINT64_C(2116084736), // FCMGE32
2849 UINT64_C(2120279040), // FCMGE64
2850 UINT64_C(1708138496), // FCMGE_PPzZ0_D
2851 UINT64_C(1699749888), // FCMGE_PPzZ0_H
2852 UINT64_C(1703944192), // FCMGE_PPzZ0_S
2853 UINT64_C(1707098112), // FCMGE_PPzZZ_D
2854 UINT64_C(1698709504), // FCMGE_PPzZZ_H
2855 UINT64_C(1702903808), // FCMGE_PPzZZ_S
2856 UINT64_C(2130233344), // FCMGEv1i16rz
2857 UINT64_C(2124466176), // FCMGEv1i32rz
2858 UINT64_C(2128660480), // FCMGEv1i64rz
2859 UINT64_C(773907456), // FCMGEv2f32
2860 UINT64_C(1851843584), // FCMGEv2f64
2861 UINT64_C(782288896), // FCMGEv2i32rz
2862 UINT64_C(1860225024), // FCMGEv2i64rz
2863 UINT64_C(775955456), // FCMGEv4f16
2864 UINT64_C(1847649280), // FCMGEv4f32
2865 UINT64_C(788056064), // FCMGEv4i16rz
2866 UINT64_C(1856030720), // FCMGEv4i32rz
2867 UINT64_C(1849697280), // FCMGEv8f16
2868 UINT64_C(1861797888), // FCMGEv8i16rz
2869 UINT64_C(2126521344), // FCMGT16
2870 UINT64_C(2124473344), // FCMGT32
2871 UINT64_C(2128667648), // FCMGT64
2872 UINT64_C(1708138512), // FCMGT_PPzZ0_D
2873 UINT64_C(1699749904), // FCMGT_PPzZ0_H
2874 UINT64_C(1703944208), // FCMGT_PPzZ0_S
2875 UINT64_C(1707098128), // FCMGT_PPzZZ_D
2876 UINT64_C(1698709520), // FCMGT_PPzZZ_H
2877 UINT64_C(1702903824), // FCMGT_PPzZZ_S
2878 UINT64_C(1593362432), // FCMGTv1i16rz
2879 UINT64_C(1587595264), // FCMGTv1i32rz
2880 UINT64_C(1591789568), // FCMGTv1i64rz
2881 UINT64_C(782296064), // FCMGTv2f32
2882 UINT64_C(1860232192), // FCMGTv2f64
2883 UINT64_C(245417984), // FCMGTv2i32rz
2884 UINT64_C(1323354112), // FCMGTv2i64rz
2885 UINT64_C(784344064), // FCMGTv4f16
2886 UINT64_C(1856037888), // FCMGTv4f32
2887 UINT64_C(251185152), // FCMGTv4i16rz
2888 UINT64_C(1319159808), // FCMGTv4i32rz
2889 UINT64_C(1858085888), // FCMGTv8f16
2890 UINT64_C(1324926976), // FCMGTv8i16rz
2891 UINT64_C(1690304512), // FCMLA_ZPmZZ_D
2892 UINT64_C(1681915904), // FCMLA_ZPmZZ_H
2893 UINT64_C(1686110208), // FCMLA_ZPmZZ_S
2894 UINT64_C(1688211456), // FCMLA_ZZZI_H
2895 UINT64_C(1692405760), // FCMLA_ZZZI_S
2896 UINT64_C(780190720), // FCMLAv2f32
2897 UINT64_C(1858126848), // FCMLAv2f64
2898 UINT64_C(775996416), // FCMLAv4f16
2899 UINT64_C(792727552), // FCMLAv4f16_indexed
2900 UINT64_C(1853932544), // FCMLAv4f32
2901 UINT64_C(1870663680), // FCMLAv4f32_indexed
2902 UINT64_C(1849738240), // FCMLAv8f16
2903 UINT64_C(1866469376), // FCMLAv8f16_indexed
2904 UINT64_C(1708204048), // FCMLE_PPzZ0_D
2905 UINT64_C(1699815440), // FCMLE_PPzZ0_H
2906 UINT64_C(1704009744), // FCMLE_PPzZ0_S
2907 UINT64_C(2130237440), // FCMLEv1i16rz
2908 UINT64_C(2124470272), // FCMLEv1i32rz
2909 UINT64_C(2128664576), // FCMLEv1i64rz
2910 UINT64_C(782292992), // FCMLEv2i32rz
2911 UINT64_C(1860229120), // FCMLEv2i64rz
2912 UINT64_C(788060160), // FCMLEv4i16rz
2913 UINT64_C(1856034816), // FCMLEv4i32rz
2914 UINT64_C(1861801984), // FCMLEv8i16rz
2915 UINT64_C(1708204032), // FCMLT_PPzZ0_D
2916 UINT64_C(1699815424), // FCMLT_PPzZ0_H
2917 UINT64_C(1704009728), // FCMLT_PPzZ0_S
2918 UINT64_C(1593370624), // FCMLTv1i16rz
2919 UINT64_C(1587603456), // FCMLTv1i32rz
2920 UINT64_C(1591797760), // FCMLTv1i64rz
2921 UINT64_C(245426176), // FCMLTv2i32rz
2922 UINT64_C(1323362304), // FCMLTv2i64rz
2923 UINT64_C(251193344), // FCMLTv4i16rz
2924 UINT64_C(1319168000), // FCMLTv4i32rz
2925 UINT64_C(1324935168), // FCMLTv8i16rz
2926 UINT64_C(1708335104), // FCMNE_PPzZ0_D
2927 UINT64_C(1699946496), // FCMNE_PPzZ0_H
2928 UINT64_C(1704140800), // FCMNE_PPzZ0_S
2929 UINT64_C(1707106320), // FCMNE_PPzZZ_D
2930 UINT64_C(1698717712), // FCMNE_PPzZZ_H
2931 UINT64_C(1702912016), // FCMNE_PPzZZ_S
2932 UINT64_C(509616136), // FCMPDri
2933 UINT64_C(509616128), // FCMPDrr
2934 UINT64_C(509616152), // FCMPEDri
2935 UINT64_C(509616144), // FCMPEDrr
2936 UINT64_C(518004760), // FCMPEHri
2937 UINT64_C(518004752), // FCMPEHrr
2938 UINT64_C(505421848), // FCMPESri
2939 UINT64_C(505421840), // FCMPESrr
2940 UINT64_C(518004744), // FCMPHri
2941 UINT64_C(518004736), // FCMPHrr
2942 UINT64_C(505421832), // FCMPSri
2943 UINT64_C(505421824), // FCMPSrr
2944 UINT64_C(1707130880), // FCMUO_PPzZZ_D
2945 UINT64_C(1698742272), // FCMUO_PPzZZ_H
2946 UINT64_C(1702936576), // FCMUO_PPzZZ_S
2947 UINT64_C(97566720), // FCPY_ZPmI_D
2948 UINT64_C(89178112), // FCPY_ZPmI_H
2949 UINT64_C(93372416), // FCPY_ZPmI_S
2950 UINT64_C(509611008), // FCSELDrrr
2951 UINT64_C(517999616), // FCSELHrrr
2952 UINT64_C(505416704), // FCSELSrrr
2953 UINT64_C(2667184128), // FCVTASDHr
2954 UINT64_C(2654601216), // FCVTASDSr
2955 UINT64_C(511311872), // FCVTASSDr
2956 UINT64_C(519700480), // FCVTASSHr
2957 UINT64_C(509870080), // FCVTASUWDr
2958 UINT64_C(518258688), // FCVTASUWHr
2959 UINT64_C(505675776), // FCVTASUWSr
2960 UINT64_C(2657353728), // FCVTASUXDr
2961 UINT64_C(2665742336), // FCVTASUXHr
2962 UINT64_C(2653159424), // FCVTASUXSr
2963 UINT64_C(1585039360), // FCVTASv1f16
2964 UINT64_C(1579272192), // FCVTASv1i32
2965 UINT64_C(1583466496), // FCVTASv1i64
2966 UINT64_C(237094912), // FCVTASv2f32
2967 UINT64_C(1315031040), // FCVTASv2f64
2968 UINT64_C(242862080), // FCVTASv4f16
2969 UINT64_C(1310836736), // FCVTASv4f32
2970 UINT64_C(1316603904), // FCVTASv8f16
2971 UINT64_C(2667249664), // FCVTAUDHr
2972 UINT64_C(2654666752), // FCVTAUDSr
2973 UINT64_C(511377408), // FCVTAUSDr
2974 UINT64_C(519766016), // FCVTAUSHr
2975 UINT64_C(509935616), // FCVTAUUWDr
2976 UINT64_C(518324224), // FCVTAUUWHr
2977 UINT64_C(505741312), // FCVTAUUWSr
2978 UINT64_C(2657419264), // FCVTAUUXDr
2979 UINT64_C(2665807872), // FCVTAUUXHr
2980 UINT64_C(2653224960), // FCVTAUUXSr
2981 UINT64_C(2121910272), // FCVTAUv1f16
2982 UINT64_C(2116143104), // FCVTAUv1i32
2983 UINT64_C(2120337408), // FCVTAUv1i64
2984 UINT64_C(773965824), // FCVTAUv2f32
2985 UINT64_C(1851901952), // FCVTAUv2f64
2986 UINT64_C(779732992), // FCVTAUv4f16
2987 UINT64_C(1847707648), // FCVTAUv4f32
2988 UINT64_C(1853474816), // FCVTAUv8f16
2989 UINT64_C(518176768), // FCVTDHr
2990 UINT64_C(505593856), // FCVTDSr
2991 UINT64_C(509853696), // FCVTHDr
2992 UINT64_C(505659392), // FCVTHSr
2993 UINT64_C(1686740992), // FCVTLT_ZPmZ_HtoS
2994 UINT64_C(1691066368), // FCVTLT_ZPmZ_StoD
2995 UINT64_C(1686216704), // FCVTLT_ZPzZ_HtoS
2996 UINT64_C(1690542080), // FCVTLT_ZPzZ_StoD
2997 UINT64_C(3248545793), // FCVTL_2ZZ_H_S
2998 UINT64_C(241268736), // FCVTLv2i32
2999 UINT64_C(237074432), // FCVTLv4i16
3000 UINT64_C(1315010560), // FCVTLv4i32
3001 UINT64_C(1310816256), // FCVTLv8i16
3002 UINT64_C(2666790912), // FCVTMSDHr
3003 UINT64_C(2654208000), // FCVTMSDSr
3004 UINT64_C(510918656), // FCVTMSSDr
3005 UINT64_C(519307264), // FCVTMSSHr
3006 UINT64_C(510656512), // FCVTMSUWDr
3007 UINT64_C(519045120), // FCVTMSUWHr
3008 UINT64_C(506462208), // FCVTMSUWSr
3009 UINT64_C(2658140160), // FCVTMSUXDr
3010 UINT64_C(2666528768), // FCVTMSUXHr
3011 UINT64_C(2653945856), // FCVTMSUXSr
3012 UINT64_C(1585035264), // FCVTMSv1f16
3013 UINT64_C(1579268096), // FCVTMSv1i32
3014 UINT64_C(1583462400), // FCVTMSv1i64
3015 UINT64_C(237090816), // FCVTMSv2f32
3016 UINT64_C(1315026944), // FCVTMSv2f64
3017 UINT64_C(242857984), // FCVTMSv4f16
3018 UINT64_C(1310832640), // FCVTMSv4f32
3019 UINT64_C(1316599808), // FCVTMSv8f16
3020 UINT64_C(2666856448), // FCVTMUDHr
3021 UINT64_C(2654273536), // FCVTMUDSr
3022 UINT64_C(510984192), // FCVTMUSDr
3023 UINT64_C(519372800), // FCVTMUSHr
3024 UINT64_C(510722048), // FCVTMUUWDr
3025 UINT64_C(519110656), // FCVTMUUWHr
3026 UINT64_C(506527744), // FCVTMUUWSr
3027 UINT64_C(2658205696), // FCVTMUUXDr
3028 UINT64_C(2666594304), // FCVTMUUXHr
3029 UINT64_C(2654011392), // FCVTMUUXSr
3030 UINT64_C(2121906176), // FCVTMUv1f16
3031 UINT64_C(2116139008), // FCVTMUv1i32
3032 UINT64_C(2120333312), // FCVTMUv1i64
3033 UINT64_C(773961728), // FCVTMUv2f32
3034 UINT64_C(1851897856), // FCVTMUv2f64
3035 UINT64_C(779728896), // FCVTMUv4f16
3036 UINT64_C(1847703552), // FCVTMUv4f32
3037 UINT64_C(1853470720), // FCVTMUv8f16
3038 UINT64_C(1695167488), // FCVTNB_Z2Z_StoB
3039 UINT64_C(2666135552), // FCVTNSDHr
3040 UINT64_C(2653552640), // FCVTNSDSr
3041 UINT64_C(510263296), // FCVTNSSDr
3042 UINT64_C(518651904), // FCVTNSSHr
3043 UINT64_C(509607936), // FCVTNSUWDr
3044 UINT64_C(517996544), // FCVTNSUWHr
3045 UINT64_C(505413632), // FCVTNSUWSr
3046 UINT64_C(2657091584), // FCVTNSUXDr
3047 UINT64_C(2665480192), // FCVTNSUXHr
3048 UINT64_C(2652897280), // FCVTNSUXSr
3049 UINT64_C(1585031168), // FCVTNSv1f16
3050 UINT64_C(1579264000), // FCVTNSv1i32
3051 UINT64_C(1583458304), // FCVTNSv1i64
3052 UINT64_C(237086720), // FCVTNSv2f32
3053 UINT64_C(1315022848), // FCVTNSv2f64
3054 UINT64_C(242853888), // FCVTNSv4f16
3055 UINT64_C(1310828544), // FCVTNSv4f32
3056 UINT64_C(1316595712), // FCVTNSv8f16
3057 UINT64_C(1695169536), // FCVTNT_Z2Z_StoB
3058 UINT64_C(1691000832), // FCVTNT_ZPmZ_DtoS
3059 UINT64_C(1686675456), // FCVTNT_ZPmZ_StoH
3060 UINT64_C(1690476544), // FCVTNT_ZPzZ_DtoS
3061 UINT64_C(1686151168), // FCVTNT_ZPzZ_StoH
3062 UINT64_C(2666201088), // FCVTNUDHr
3063 UINT64_C(2653618176), // FCVTNUDSr
3064 UINT64_C(510328832), // FCVTNUSDr
3065 UINT64_C(518717440), // FCVTNUSHr
3066 UINT64_C(509673472), // FCVTNUUWDr
3067 UINT64_C(518062080), // FCVTNUUWHr
3068 UINT64_C(505479168), // FCVTNUUWSr
3069 UINT64_C(2657157120), // FCVTNUUXDr
3070 UINT64_C(2665545728), // FCVTNUUXHr
3071 UINT64_C(2652962816), // FCVTNUUXSr
3072 UINT64_C(2121902080), // FCVTNUv1f16
3073 UINT64_C(2116134912), // FCVTNUv1i32
3074 UINT64_C(2120329216), // FCVTNUv1i64
3075 UINT64_C(773957632), // FCVTNUv2f32
3076 UINT64_C(1851893760), // FCVTNUv2f64
3077 UINT64_C(779724800), // FCVTNUv4f16
3078 UINT64_C(1847699456), // FCVTNUv4f32
3079 UINT64_C(1853466624), // FCVTNUv8f16
3080 UINT64_C(1312879616), // FCVTN_F16v16f8
3081 UINT64_C(239137792), // FCVTN_F16v8f8
3082 UINT64_C(1308685312), // FCVTN_F322v16f8
3083 UINT64_C(234943488), // FCVTN_F32v8f8
3084 UINT64_C(1695166464), // FCVTN_Z2Z_HtoB
3085 UINT64_C(3240157216), // FCVTN_Z2Z_StoH
3086 UINT64_C(3241467936), // FCVTN_Z4Z_StoB
3087 UINT64_C(241264640), // FCVTNv2i32
3088 UINT64_C(237070336), // FCVTNv4i16
3089 UINT64_C(1315006464), // FCVTNv4i32
3090 UINT64_C(1310812160), // FCVTNv8i16
3091 UINT64_C(2666659840), // FCVTPSDHr
3092 UINT64_C(2654076928), // FCVTPSDSr
3093 UINT64_C(510787584), // FCVTPSSDr
3094 UINT64_C(519176192), // FCVTPSSHr
3095 UINT64_C(510132224), // FCVTPSUWDr
3096 UINT64_C(518520832), // FCVTPSUWHr
3097 UINT64_C(505937920), // FCVTPSUWSr
3098 UINT64_C(2657615872), // FCVTPSUXDr
3099 UINT64_C(2666004480), // FCVTPSUXHr
3100 UINT64_C(2653421568), // FCVTPSUXSr
3101 UINT64_C(1593419776), // FCVTPSv1f16
3102 UINT64_C(1587652608), // FCVTPSv1i32
3103 UINT64_C(1591846912), // FCVTPSv1i64
3104 UINT64_C(245475328), // FCVTPSv2f32
3105 UINT64_C(1323411456), // FCVTPSv2f64
3106 UINT64_C(251242496), // FCVTPSv4f16
3107 UINT64_C(1319217152), // FCVTPSv4f32
3108 UINT64_C(1324984320), // FCVTPSv8f16
3109 UINT64_C(2666725376), // FCVTPUDHr
3110 UINT64_C(2654142464), // FCVTPUDSr
3111 UINT64_C(510853120), // FCVTPUSDr
3112 UINT64_C(519241728), // FCVTPUSHr
3113 UINT64_C(510197760), // FCVTPUUWDr
3114 UINT64_C(518586368), // FCVTPUUWHr
3115 UINT64_C(506003456), // FCVTPUUWSr
3116 UINT64_C(2657681408), // FCVTPUUXDr
3117 UINT64_C(2666070016), // FCVTPUUXHr
3118 UINT64_C(2653487104), // FCVTPUUXSr
3119 UINT64_C(2130290688), // FCVTPUv1f16
3120 UINT64_C(2124523520), // FCVTPUv1i32
3121 UINT64_C(2128717824), // FCVTPUv1i64
3122 UINT64_C(782346240), // FCVTPUv2f32
3123 UINT64_C(1860282368), // FCVTPUv2f64
3124 UINT64_C(788113408), // FCVTPUv4f16
3125 UINT64_C(1856088064), // FCVTPUv4f32
3126 UINT64_C(1861855232), // FCVTPUv8f16
3127 UINT64_C(509755392), // FCVTSDr
3128 UINT64_C(518144000), // FCVTSHr
3129 UINT64_C(1678417920), // FCVTXNT_ZPmZ_DtoS
3130 UINT64_C(1677893632), // FCVTXNT_ZPzZ
3131 UINT64_C(2120312832), // FCVTXNv1i64
3132 UINT64_C(778135552), // FCVTXNv2f32
3133 UINT64_C(1851877376), // FCVTXNv4f32
3134 UINT64_C(1695195136), // FCVTX_ZPmZ_DtoS
3135 UINT64_C(1679474688), // FCVTX_ZPzZ_DtoS
3136 UINT64_C(2666921984), // FCVTZSDHr
3137 UINT64_C(2654339072), // FCVTZSDSr
3138 UINT64_C(511049728), // FCVTZSSDr
3139 UINT64_C(519438336), // FCVTZSSHr
3140 UINT64_C(509116416), // FCVTZSSWDri
3141 UINT64_C(517505024), // FCVTZSSWHri
3142 UINT64_C(504922112), // FCVTZSSWSri
3143 UINT64_C(2656567296), // FCVTZSSXDri
3144 UINT64_C(2664955904), // FCVTZSSXHri
3145 UINT64_C(2652372992), // FCVTZSSXSri
3146 UINT64_C(511180800), // FCVTZSUWDr
3147 UINT64_C(519569408), // FCVTZSUWHr
3148 UINT64_C(506986496), // FCVTZSUWSr
3149 UINT64_C(2658664448), // FCVTZSUXDr
3150 UINT64_C(2667053056), // FCVTZSUXHr
3151 UINT64_C(2654470144), // FCVTZSUXSr
3152 UINT64_C(3240222720), // FCVTZS_2Z2Z_StoS
3153 UINT64_C(3241271296), // FCVTZS_4Z4Z_StoS
3154 UINT64_C(1709088768), // FCVTZS_ZPmZ_DtoD
3155 UINT64_C(1708695552), // FCVTZS_ZPmZ_DtoS
3156 UINT64_C(1700700160), // FCVTZS_ZPmZ_HtoD
3157 UINT64_C(1700438016), // FCVTZS_ZPmZ_HtoH
3158 UINT64_C(1700569088), // FCVTZS_ZPmZ_HtoS
3159 UINT64_C(1708957696), // FCVTZS_ZPmZ_StoD
3160 UINT64_C(1704763392), // FCVTZS_ZPmZ_StoS
3161 UINT64_C(1692385280), // FCVTZS_ZPzZ_DtoD
3162 UINT64_C(1692303360), // FCVTZS_ZPzZ_DtoS
3163 UINT64_C(1683996672), // FCVTZS_ZPzZ_HtoD
3164 UINT64_C(1683931136), // FCVTZS_ZPzZ_HtoH
3165 UINT64_C(1683980288), // FCVTZS_ZPzZ_HtoS
3166 UINT64_C(1692368896), // FCVTZS_ZPzZ_StoD
3167 UINT64_C(1688174592), // FCVTZS_ZPzZ_StoS
3168 UINT64_C(1598094336), // FCVTZSd
3169 UINT64_C(1594948608), // FCVTZSh
3170 UINT64_C(1595997184), // FCVTZSs
3171 UINT64_C(1593423872), // FCVTZSv1f16
3172 UINT64_C(1587656704), // FCVTZSv1i32
3173 UINT64_C(1591851008), // FCVTZSv1i64
3174 UINT64_C(245479424), // FCVTZSv2f32
3175 UINT64_C(1323415552), // FCVTZSv2f64
3176 UINT64_C(253819904), // FCVTZSv2i32_shift
3177 UINT64_C(1329658880), // FCVTZSv2i64_shift
3178 UINT64_C(251246592), // FCVTZSv4f16
3179 UINT64_C(1319221248), // FCVTZSv4f32
3180 UINT64_C(252771328), // FCVTZSv4i16_shift
3181 UINT64_C(1327561728), // FCVTZSv4i32_shift
3182 UINT64_C(1324988416), // FCVTZSv8f16
3183 UINT64_C(1326513152), // FCVTZSv8i16_shift
3184 UINT64_C(2666987520), // FCVTZUDHr
3185 UINT64_C(2654404608), // FCVTZUDSr
3186 UINT64_C(511115264), // FCVTZUSDr
3187 UINT64_C(519503872), // FCVTZUSHr
3188 UINT64_C(509181952), // FCVTZUSWDri
3189 UINT64_C(517570560), // FCVTZUSWHri
3190 UINT64_C(504987648), // FCVTZUSWSri
3191 UINT64_C(2656632832), // FCVTZUSXDri
3192 UINT64_C(2665021440), // FCVTZUSXHri
3193 UINT64_C(2652438528), // FCVTZUSXSri
3194 UINT64_C(511246336), // FCVTZUUWDr
3195 UINT64_C(519634944), // FCVTZUUWHr
3196 UINT64_C(507052032), // FCVTZUUWSr
3197 UINT64_C(2658729984), // FCVTZUUXDr
3198 UINT64_C(2667118592), // FCVTZUUXHr
3199 UINT64_C(2654535680), // FCVTZUUXSr
3200 UINT64_C(3240222752), // FCVTZU_2Z2Z_StoS
3201 UINT64_C(3241271328), // FCVTZU_4Z4Z_StoS
3202 UINT64_C(1709154304), // FCVTZU_ZPmZ_DtoD
3203 UINT64_C(1708761088), // FCVTZU_ZPmZ_DtoS
3204 UINT64_C(1700765696), // FCVTZU_ZPmZ_HtoD
3205 UINT64_C(1700503552), // FCVTZU_ZPmZ_HtoH
3206 UINT64_C(1700634624), // FCVTZU_ZPmZ_HtoS
3207 UINT64_C(1709023232), // FCVTZU_ZPmZ_StoD
3208 UINT64_C(1704828928), // FCVTZU_ZPmZ_StoS
3209 UINT64_C(1692393472), // FCVTZU_ZPzZ_DtoD
3210 UINT64_C(1692311552), // FCVTZU_ZPzZ_DtoS
3211 UINT64_C(1684004864), // FCVTZU_ZPzZ_HtoD
3212 UINT64_C(1683939328), // FCVTZU_ZPzZ_HtoH
3213 UINT64_C(1683988480), // FCVTZU_ZPzZ_HtoS
3214 UINT64_C(1692377088), // FCVTZU_ZPzZ_StoD
3215 UINT64_C(1688182784), // FCVTZU_ZPzZ_StoS
3216 UINT64_C(2134965248), // FCVTZUd
3217 UINT64_C(2131819520), // FCVTZUh
3218 UINT64_C(2132868096), // FCVTZUs
3219 UINT64_C(2130294784), // FCVTZUv1f16
3220 UINT64_C(2124527616), // FCVTZUv1i32
3221 UINT64_C(2128721920), // FCVTZUv1i64
3222 UINT64_C(782350336), // FCVTZUv2f32
3223 UINT64_C(1860286464), // FCVTZUv2f64
3224 UINT64_C(790690816), // FCVTZUv2i32_shift
3225 UINT64_C(1866529792), // FCVTZUv2i64_shift
3226 UINT64_C(788117504), // FCVTZUv4f16
3227 UINT64_C(1856092160), // FCVTZUv4f32
3228 UINT64_C(789642240), // FCVTZUv4i16_shift
3229 UINT64_C(1864432640), // FCVTZUv4i32_shift
3230 UINT64_C(1861859328), // FCVTZUv8f16
3231 UINT64_C(1863384064), // FCVTZUv8i16_shift
3232 UINT64_C(3248545792), // FCVT_2ZZ_H_S
3233 UINT64_C(3240419328), // FCVT_Z2Z_HtoB
3234 UINT64_C(3240157184), // FCVT_Z2Z_StoH
3235 UINT64_C(3241467904), // FCVT_Z4Z_StoB
3236 UINT64_C(1707646976), // FCVT_ZPmZ_DtoH
3237 UINT64_C(1707778048), // FCVT_ZPmZ_DtoS
3238 UINT64_C(1707712512), // FCVT_ZPmZ_HtoD
3239 UINT64_C(1703518208), // FCVT_ZPmZ_HtoS
3240 UINT64_C(1707843584), // FCVT_ZPmZ_StoD
3241 UINT64_C(1703452672), // FCVT_ZPmZ_StoH
3242 UINT64_C(1692041216), // FCVT_ZPzZ_DtoH
3243 UINT64_C(1692057600), // FCVT_ZPzZ_DtoS
3244 UINT64_C(1692049408), // FCVT_ZPzZ_HtoD
3245 UINT64_C(1687855104), // FCVT_ZPzZ_HtoS
3246 UINT64_C(1692065792), // FCVT_ZPzZ_StoD
3247 UINT64_C(1687846912), // FCVT_ZPzZ_StoH
3248 UINT64_C(509614080), // FDIVDrr
3249 UINT64_C(518002688), // FDIVHrr
3250 UINT64_C(1707900928), // FDIVR_ZPmZ_D
3251 UINT64_C(1699512320), // FDIVR_ZPmZ_H
3252 UINT64_C(1703706624), // FDIVR_ZPmZ_S
3253 UINT64_C(505419776), // FDIVSrr
3254 UINT64_C(1707966464), // FDIV_ZPmZ_D
3255 UINT64_C(1699577856), // FDIV_ZPmZ_H
3256 UINT64_C(1703772160), // FDIV_ZPmZ_S
3257 UINT64_C(773913600), // FDIVv2f32
3258 UINT64_C(1851849728), // FDIVv2f64
3259 UINT64_C(775961600), // FDIVv4f16
3260 UINT64_C(1847655424), // FDIVv4f32
3261 UINT64_C(1849703424), // FDIVv8f16
3262 UINT64_C(3248492576), // FDOT_VG2_M2Z2Z_BtoH
3263 UINT64_C(3248492592), // FDOT_VG2_M2Z2Z_BtoS
3264 UINT64_C(3248492544), // FDOT_VG2_M2Z2Z_HtoS
3265 UINT64_C(3251634208), // FDOT_VG2_M2ZZI_BtoH
3266 UINT64_C(3243245624), // FDOT_VG2_M2ZZI_BtoS
3267 UINT64_C(3243249672), // FDOT_VG2_M2ZZI_HtoS
3268 UINT64_C(3240103944), // FDOT_VG2_M2ZZ_BtoH
3269 UINT64_C(3240103960), // FDOT_VG2_M2ZZ_BtoS
3270 UINT64_C(3240103936), // FDOT_VG2_M2ZZ_HtoS
3271 UINT64_C(3248558112), // FDOT_VG4_M4Z4Z_BtoH
3272 UINT64_C(3248558128), // FDOT_VG4_M4Z4Z_BtoS
3273 UINT64_C(3248558080), // FDOT_VG4_M4Z4Z_HtoS
3274 UINT64_C(3239088192), // FDOT_VG4_M4ZZI_BtoH
3275 UINT64_C(3243278344), // FDOT_VG4_M4ZZI_BtoS
3276 UINT64_C(3243282440), // FDOT_VG4_M4ZZI_HtoS
3277 UINT64_C(3241152520), // FDOT_VG4_M4ZZ_BtoH
3278 UINT64_C(3241152536), // FDOT_VG4_M4ZZ_BtoS
3279 UINT64_C(3241152512), // FDOT_VG4_M4ZZ_HtoS
3280 UINT64_C(1679836160), // FDOT_ZZZI_BtoH
3281 UINT64_C(1684030464), // FDOT_ZZZI_BtoS
3282 UINT64_C(1679835136), // FDOT_ZZZI_S
3283 UINT64_C(1679852544), // FDOT_ZZZ_BtoH
3284 UINT64_C(1684046848), // FDOT_ZZZ_BtoS
3285 UINT64_C(1679851520), // FDOT_ZZZ_S
3286 UINT64_C(251658240), // FDOTlanev2f32
3287 UINT64_C(255852544), // FDOTlanev4f16
3288 UINT64_C(1325400064), // FDOTlanev4f32
3289 UINT64_C(1329594368), // FDOTlanev8f16
3290 UINT64_C(234945536), // FDOTv2f32
3291 UINT64_C(239139840), // FDOTv4f16
3292 UINT64_C(1308687360), // FDOTv4f32
3293 UINT64_C(1312881664), // FDOTv8f16
3294 UINT64_C(637124608), // FDUP_ZI_D
3295 UINT64_C(628736000), // FDUP_ZI_H
3296 UINT64_C(632930304), // FDUP_ZI_S
3297 UINT64_C(81836032), // FEXPA_ZZ_D
3298 UINT64_C(73447424), // FEXPA_ZZ_H
3299 UINT64_C(77641728), // FEXPA_ZZ_S
3300 UINT64_C(622952448), // FIRSTP_XPP_B
3301 UINT64_C(635535360), // FIRSTP_XPP_D
3302 UINT64_C(627146752), // FIRSTP_XPP_H
3303 UINT64_C(631341056), // FIRSTP_XPP_S
3304 UINT64_C(511574016), // FJCVTZS
3305 UINT64_C(1696505856), // FLOGB_ZPmZ_D
3306 UINT64_C(1696243712), // FLOGB_ZPmZ_H
3307 UINT64_C(1696374784), // FLOGB_ZPmZ_S
3308 UINT64_C(1679745024), // FLOGB_ZPzZ_D
3309 UINT64_C(1679728640), // FLOGB_ZPzZ_H
3310 UINT64_C(1679736832), // FLOGB_ZPzZ_S
3311 UINT64_C(524288000), // FMADDDrrr
3312 UINT64_C(532676608), // FMADDHrrr
3313 UINT64_C(520093696), // FMADDSrrr
3314 UINT64_C(1709211648), // FMAD_ZPmZZ_D
3315 UINT64_C(1700823040), // FMAD_ZPmZZ_H
3316 UINT64_C(1705017344), // FMAD_ZPmZZ_S
3317 UINT64_C(509626368), // FMAXDrr
3318 UINT64_C(518014976), // FMAXHrr
3319 UINT64_C(509634560), // FMAXNMDrr
3320 UINT64_C(518023168), // FMAXNMHrr
3321 UINT64_C(1691648000), // FMAXNMP_ZPmZZ_D
3322 UINT64_C(1683259392), // FMAXNMP_ZPmZZ_H
3323 UINT64_C(1687453696), // FMAXNMP_ZPmZZ_S
3324 UINT64_C(773899264), // FMAXNMPv2f32
3325 UINT64_C(1851835392), // FMAXNMPv2f64
3326 UINT64_C(1580255232), // FMAXNMPv2i16p
3327 UINT64_C(2117126144), // FMAXNMPv2i32p
3328 UINT64_C(2121320448), // FMAXNMPv2i64p
3329 UINT64_C(775947264), // FMAXNMPv4f16
3330 UINT64_C(1847641088), // FMAXNMPv4f32
3331 UINT64_C(1849689088), // FMAXNMPv8f16
3332 UINT64_C(1691656192), // FMAXNMQV_D
3333 UINT64_C(1683267584), // FMAXNMQV_H
3334 UINT64_C(1687461888), // FMAXNMQV_S
3335 UINT64_C(505440256), // FMAXNMSrr
3336 UINT64_C(1707352064), // FMAXNMV_VPZ_D
3337 UINT64_C(1698963456), // FMAXNMV_VPZ_H
3338 UINT64_C(1703157760), // FMAXNMV_VPZ_S
3339 UINT64_C(238077952), // FMAXNMVv4i16v
3340 UINT64_C(1848690688), // FMAXNMVv4i32v
3341 UINT64_C(1311819776), // FMAXNMVv8i16v
3342 UINT64_C(3252728096), // FMAXNM_VG2_2Z2Z_D
3343 UINT64_C(3244339488), // FMAXNM_VG2_2Z2Z_H
3344 UINT64_C(3248533792), // FMAXNM_VG2_2Z2Z_S
3345 UINT64_C(3252724000), // FMAXNM_VG2_2ZZ_D
3346 UINT64_C(3244335392), // FMAXNM_VG2_2ZZ_H
3347 UINT64_C(3248529696), // FMAXNM_VG2_2ZZ_S
3348 UINT64_C(3252730144), // FMAXNM_VG4_4Z4Z_D
3349 UINT64_C(3244341536), // FMAXNM_VG4_4Z4Z_H
3350 UINT64_C(3248535840), // FMAXNM_VG4_4Z4Z_S
3351 UINT64_C(3252726048), // FMAXNM_VG4_4ZZ_D
3352 UINT64_C(3244337440), // FMAXNM_VG4_4ZZ_H
3353 UINT64_C(3248531744), // FMAXNM_VG4_4ZZ_S
3354 UINT64_C(1708949504), // FMAXNM_ZPmI_D
3355 UINT64_C(1700560896), // FMAXNM_ZPmI_H
3356 UINT64_C(1704755200), // FMAXNM_ZPmI_S
3357 UINT64_C(1707376640), // FMAXNM_ZPmZ_D
3358 UINT64_C(1698988032), // FMAXNM_ZPmZ_H
3359 UINT64_C(1703182336), // FMAXNM_ZPmZ_S
3360 UINT64_C(237028352), // FMAXNMv2f32
3361 UINT64_C(1314964480), // FMAXNMv2f64
3362 UINT64_C(239076352), // FMAXNMv4f16
3363 UINT64_C(1310770176), // FMAXNMv4f32
3364 UINT64_C(1312818176), // FMAXNMv8f16
3365 UINT64_C(1691779072), // FMAXP_ZPmZZ_D
3366 UINT64_C(1683390464), // FMAXP_ZPmZZ_H
3367 UINT64_C(1687584768), // FMAXP_ZPmZZ_S
3368 UINT64_C(773911552), // FMAXPv2f32
3369 UINT64_C(1851847680), // FMAXPv2f64
3370 UINT64_C(1580267520), // FMAXPv2i16p
3371 UINT64_C(2117138432), // FMAXPv2i32p
3372 UINT64_C(2121332736), // FMAXPv2i64p
3373 UINT64_C(775959552), // FMAXPv4f16
3374 UINT64_C(1847653376), // FMAXPv4f32
3375 UINT64_C(1849701376), // FMAXPv8f16
3376 UINT64_C(1691787264), // FMAXQV_D
3377 UINT64_C(1683398656), // FMAXQV_H
3378 UINT64_C(1687592960), // FMAXQV_S
3379 UINT64_C(505432064), // FMAXSrr
3380 UINT64_C(1707483136), // FMAXV_VPZ_D
3381 UINT64_C(1699094528), // FMAXV_VPZ_H
3382 UINT64_C(1703288832), // FMAXV_VPZ_S
3383 UINT64_C(238090240), // FMAXVv4i16v
3384 UINT64_C(1848702976), // FMAXVv4i32v
3385 UINT64_C(1311832064), // FMAXVv8i16v
3386 UINT64_C(3252728064), // FMAX_VG2_2Z2Z_D
3387 UINT64_C(3244339456), // FMAX_VG2_2Z2Z_H
3388 UINT64_C(3248533760), // FMAX_VG2_2Z2Z_S
3389 UINT64_C(3252723968), // FMAX_VG2_2ZZ_D
3390 UINT64_C(3244335360), // FMAX_VG2_2ZZ_H
3391 UINT64_C(3248529664), // FMAX_VG2_2ZZ_S
3392 UINT64_C(3252730112), // FMAX_VG4_4Z4Z_D
3393 UINT64_C(3244341504), // FMAX_VG4_4Z4Z_H
3394 UINT64_C(3248535808), // FMAX_VG4_4Z4Z_S
3395 UINT64_C(3252726016), // FMAX_VG4_4ZZ_D
3396 UINT64_C(3244337408), // FMAX_VG4_4ZZ_H
3397 UINT64_C(3248531712), // FMAX_VG4_4ZZ_S
3398 UINT64_C(1709080576), // FMAX_ZPmI_D
3399 UINT64_C(1700691968), // FMAX_ZPmI_H
3400 UINT64_C(1704886272), // FMAX_ZPmI_S
3401 UINT64_C(1707507712), // FMAX_ZPmZ_D
3402 UINT64_C(1699119104), // FMAX_ZPmZ_H
3403 UINT64_C(1703313408), // FMAX_ZPmZ_S
3404 UINT64_C(237040640), // FMAXv2f32
3405 UINT64_C(1314976768), // FMAXv2f64
3406 UINT64_C(239088640), // FMAXv4f16
3407 UINT64_C(1310782464), // FMAXv4f32
3408 UINT64_C(1312830464), // FMAXv8f16
3409 UINT64_C(509630464), // FMINDrr
3410 UINT64_C(518019072), // FMINHrr
3411 UINT64_C(509638656), // FMINNMDrr
3412 UINT64_C(518027264), // FMINNMHrr
3413 UINT64_C(1691713536), // FMINNMP_ZPmZZ_D
3414 UINT64_C(1683324928), // FMINNMP_ZPmZZ_H
3415 UINT64_C(1687519232), // FMINNMP_ZPmZZ_S
3416 UINT64_C(782287872), // FMINNMPv2f32
3417 UINT64_C(1860224000), // FMINNMPv2f64
3418 UINT64_C(1588643840), // FMINNMPv2i16p
3419 UINT64_C(2125514752), // FMINNMPv2i32p
3420 UINT64_C(2129709056), // FMINNMPv2i64p
3421 UINT64_C(784335872), // FMINNMPv4f16
3422 UINT64_C(1856029696), // FMINNMPv4f32
3423 UINT64_C(1858077696), // FMINNMPv8f16
3424 UINT64_C(1691721728), // FMINNMQV_D
3425 UINT64_C(1683333120), // FMINNMQV_H
3426 UINT64_C(1687527424), // FMINNMQV_S
3427 UINT64_C(505444352), // FMINNMSrr
3428 UINT64_C(1707417600), // FMINNMV_VPZ_D
3429 UINT64_C(1699028992), // FMINNMV_VPZ_H
3430 UINT64_C(1703223296), // FMINNMV_VPZ_S
3431 UINT64_C(246466560), // FMINNMVv4i16v
3432 UINT64_C(1857079296), // FMINNMVv4i32v
3433 UINT64_C(1320208384), // FMINNMVv8i16v
3434 UINT64_C(3252728097), // FMINNM_VG2_2Z2Z_D
3435 UINT64_C(3244339489), // FMINNM_VG2_2Z2Z_H
3436 UINT64_C(3248533793), // FMINNM_VG2_2Z2Z_S
3437 UINT64_C(3252724001), // FMINNM_VG2_2ZZ_D
3438 UINT64_C(3244335393), // FMINNM_VG2_2ZZ_H
3439 UINT64_C(3248529697), // FMINNM_VG2_2ZZ_S
3440 UINT64_C(3252730145), // FMINNM_VG4_4Z4Z_D
3441 UINT64_C(3244341537), // FMINNM_VG4_4Z4Z_H
3442 UINT64_C(3248535841), // FMINNM_VG4_4Z4Z_S
3443 UINT64_C(3252726049), // FMINNM_VG4_4ZZ_D
3444 UINT64_C(3244337441), // FMINNM_VG4_4ZZ_H
3445 UINT64_C(3248531745), // FMINNM_VG4_4ZZ_S
3446 UINT64_C(1709015040), // FMINNM_ZPmI_D
3447 UINT64_C(1700626432), // FMINNM_ZPmI_H
3448 UINT64_C(1704820736), // FMINNM_ZPmI_S
3449 UINT64_C(1707442176), // FMINNM_ZPmZ_D
3450 UINT64_C(1699053568), // FMINNM_ZPmZ_H
3451 UINT64_C(1703247872), // FMINNM_ZPmZ_S
3452 UINT64_C(245416960), // FMINNMv2f32
3453 UINT64_C(1323353088), // FMINNMv2f64
3454 UINT64_C(247464960), // FMINNMv4f16
3455 UINT64_C(1319158784), // FMINNMv4f32
3456 UINT64_C(1321206784), // FMINNMv8f16
3457 UINT64_C(1691844608), // FMINP_ZPmZZ_D
3458 UINT64_C(1683456000), // FMINP_ZPmZZ_H
3459 UINT64_C(1687650304), // FMINP_ZPmZZ_S
3460 UINT64_C(782300160), // FMINPv2f32
3461 UINT64_C(1860236288), // FMINPv2f64
3462 UINT64_C(1588656128), // FMINPv2i16p
3463 UINT64_C(2125527040), // FMINPv2i32p
3464 UINT64_C(2129721344), // FMINPv2i64p
3465 UINT64_C(784348160), // FMINPv4f16
3466 UINT64_C(1856041984), // FMINPv4f32
3467 UINT64_C(1858089984), // FMINPv8f16
3468 UINT64_C(1691852800), // FMINQV_D
3469 UINT64_C(1683464192), // FMINQV_H
3470 UINT64_C(1687658496), // FMINQV_S
3471 UINT64_C(505436160), // FMINSrr
3472 UINT64_C(1707548672), // FMINV_VPZ_D
3473 UINT64_C(1699160064), // FMINV_VPZ_H
3474 UINT64_C(1703354368), // FMINV_VPZ_S
3475 UINT64_C(246478848), // FMINVv4i16v
3476 UINT64_C(1857091584), // FMINVv4i32v
3477 UINT64_C(1320220672), // FMINVv8i16v
3478 UINT64_C(3252728065), // FMIN_VG2_2Z2Z_D
3479 UINT64_C(3244339457), // FMIN_VG2_2Z2Z_H
3480 UINT64_C(3248533761), // FMIN_VG2_2Z2Z_S
3481 UINT64_C(3252723969), // FMIN_VG2_2ZZ_D
3482 UINT64_C(3244335361), // FMIN_VG2_2ZZ_H
3483 UINT64_C(3248529665), // FMIN_VG2_2ZZ_S
3484 UINT64_C(3252730113), // FMIN_VG4_4Z4Z_D
3485 UINT64_C(3244341505), // FMIN_VG4_4Z4Z_H
3486 UINT64_C(3248535809), // FMIN_VG4_4Z4Z_S
3487 UINT64_C(3252726017), // FMIN_VG4_4ZZ_D
3488 UINT64_C(3244337409), // FMIN_VG4_4ZZ_H
3489 UINT64_C(3248531713), // FMIN_VG4_4ZZ_S
3490 UINT64_C(1709146112), // FMIN_ZPmI_D
3491 UINT64_C(1700757504), // FMIN_ZPmI_H
3492 UINT64_C(1704951808), // FMIN_ZPmI_S
3493 UINT64_C(1707573248), // FMIN_ZPmZ_D
3494 UINT64_C(1699184640), // FMIN_ZPmZ_H
3495 UINT64_C(1703378944), // FMIN_ZPmZ_S
3496 UINT64_C(245429248), // FMINv2f32
3497 UINT64_C(1323365376), // FMINv2f64
3498 UINT64_C(247477248), // FMINv4f16
3499 UINT64_C(1319171072), // FMINv4f32
3500 UINT64_C(1321219072), // FMINv8f16
3501 UINT64_C(796950528), // FMLAL2lanev4f16
3502 UINT64_C(1870692352), // FMLAL2lanev8f16
3503 UINT64_C(773901312), // FMLAL2v4f16
3504 UINT64_C(1847643136), // FMLAL2v8f16
3505 UINT64_C(1688242176), // FMLALB_ZZZ
3506 UINT64_C(1679839232), // FMLALB_ZZZI
3507 UINT64_C(1688223744), // FMLALB_ZZZI_SHH
3508 UINT64_C(1688240128), // FMLALB_ZZZ_SHH
3509 UINT64_C(264241152), // FMLALBlanev8f16
3510 UINT64_C(247528448), // FMLALBv8f16
3511 UINT64_C(1679853568), // FMLALLBB_ZZZ
3512 UINT64_C(1679867904), // FMLALLBB_ZZZI
3513 UINT64_C(788561920), // FMLALLBBlanev4f32
3514 UINT64_C(234931200), // FMLALLBBv4f32
3515 UINT64_C(1679857664), // FMLALLBT_ZZZ
3516 UINT64_C(1684062208), // FMLALLBT_ZZZI
3517 UINT64_C(792756224), // FMLALLBTlanev4f32
3518 UINT64_C(239125504), // FMLALLBTv4f32
3519 UINT64_C(1679861760), // FMLALLTB_ZZZ
3520 UINT64_C(1688256512), // FMLALLTB_ZZZI
3521 UINT64_C(1862303744), // FMLALLTBlanev4f32
3522 UINT64_C(1308673024), // FMLALLTBv4f32
3523 UINT64_C(1679865856), // FMLALLTT_ZZZ
3524 UINT64_C(1692450816), // FMLALLTT_ZZZI
3525 UINT64_C(1866498048), // FMLALLTTlanev4f32
3526 UINT64_C(1312867328), // FMLALLTTv4f32
3527 UINT64_C(3242196992), // FMLALL_MZZI_BtoS
3528 UINT64_C(3241149440), // FMLALL_MZZ_BtoS
3529 UINT64_C(3248488480), // FMLALL_VG2_M2Z2Z_BtoS
3530 UINT64_C(3247439904), // FMLALL_VG2_M2ZZI_BtoS
3531 UINT64_C(3240099842), // FMLALL_VG2_M2ZZ_BtoS
3532 UINT64_C(3248554016), // FMLALL_VG4_M4Z4Z_BtoS
3533 UINT64_C(3239084096), // FMLALL_VG4_M4ZZI_BtoS
3534 UINT64_C(3241148418), // FMLALL_VG4_M4ZZ_BtoS
3535 UINT64_C(1688246272), // FMLALT_ZZZ
3536 UINT64_C(1688227840), // FMLALT_ZZZI
3537 UINT64_C(1688224768), // FMLALT_ZZZI_SHH
3538 UINT64_C(1688241152), // FMLALT_ZZZ_SHH
3539 UINT64_C(1337982976), // FMLALTlanev8f16
3540 UINT64_C(1321270272), // FMLALTv8f16
3541 UINT64_C(3250585600), // FMLAL_MZZI_BtoH
3542 UINT64_C(3246395392), // FMLAL_MZZI_HtoS
3543 UINT64_C(3240102912), // FMLAL_MZZ_HtoS
3544 UINT64_C(3248490528), // FMLAL_VG2_M2Z2Z_BtoH
3545 UINT64_C(3248490496), // FMLAL_VG2_M2Z2Z_HtoS
3546 UINT64_C(3247444016), // FMLAL_VG2_M2ZZI_BtoH
3547 UINT64_C(3247443968), // FMLAL_VG2_M2ZZI_HtoS
3548 UINT64_C(3240101892), // FMLAL_VG2_M2ZZ_BtoH
3549 UINT64_C(3240101888), // FMLAL_VG2_M2ZZ_HtoS
3550 UINT64_C(3241151488), // FMLAL_VG2_MZZ_BtoH
3551 UINT64_C(3248556064), // FMLAL_VG4_M4Z4Z_BtoH
3552 UINT64_C(3248556032), // FMLAL_VG4_M4Z4Z_HtoS
3553 UINT64_C(3247476768), // FMLAL_VG4_M4ZZI_BtoH
3554 UINT64_C(3247476736), // FMLAL_VG4_M4ZZI_HtoS
3555 UINT64_C(3241150468), // FMLAL_VG4_M4ZZ_BtoH
3556 UINT64_C(3241150464), // FMLAL_VG4_M4ZZ_HtoS
3557 UINT64_C(260046848), // FMLALlanev4f16
3558 UINT64_C(1333788672), // FMLALlanev8f16
3559 UINT64_C(237038592), // FMLALv4f16
3560 UINT64_C(1310780416), // FMLALv8f16
3561 UINT64_C(3252688896), // FMLA_VG2_M2Z2Z_D
3562 UINT64_C(3248492552), // FMLA_VG2_M2Z2Z_H
3563 UINT64_C(3248494592), // FMLA_VG2_M2Z2Z_S
3564 UINT64_C(3251634176), // FMLA_VG2_M2ZZI_D
3565 UINT64_C(3239055360), // FMLA_VG2_M2ZZI_H
3566 UINT64_C(3243245568), // FMLA_VG2_M2ZZI_S
3567 UINT64_C(3244300288), // FMLA_VG2_M2ZZ_D
3568 UINT64_C(3240107008), // FMLA_VG2_M2ZZ_H
3569 UINT64_C(3240105984), // FMLA_VG2_M2ZZ_S
3570 UINT64_C(3252754432), // FMLA_VG4_M4Z4Z_D
3571 UINT64_C(3248558088), // FMLA_VG4_M4Z4Z_H
3572 UINT64_C(3248560128), // FMLA_VG4_M4Z4Z_S
3573 UINT64_C(3251666944), // FMLA_VG4_M4ZZI_D
3574 UINT64_C(3239088128), // FMLA_VG4_M4ZZI_H
3575 UINT64_C(3243278336), // FMLA_VG4_M4ZZI_S
3576 UINT64_C(3245348864), // FMLA_VG4_M4ZZ_D
3577 UINT64_C(3241155584), // FMLA_VG4_M4ZZ_H
3578 UINT64_C(3241154560), // FMLA_VG4_M4ZZ_S
3579 UINT64_C(1709178880), // FMLA_ZPmZZ_D
3580 UINT64_C(1700790272), // FMLA_ZPmZZ_H
3581 UINT64_C(1704984576), // FMLA_ZPmZZ_S
3582 UINT64_C(1692401664), // FMLA_ZZZI_D
3583 UINT64_C(1679818752), // FMLA_ZZZI_H
3584 UINT64_C(1688207360), // FMLA_ZZZI_S
3585 UINT64_C(1593839616), // FMLAv1i16_indexed
3586 UINT64_C(1602228224), // FMLAv1i32_indexed
3587 UINT64_C(1606422528), // FMLAv1i64_indexed
3588 UINT64_C(237030400), // FMLAv2f32
3589 UINT64_C(1314966528), // FMLAv2f64
3590 UINT64_C(260050944), // FMLAv2i32_indexed
3591 UINT64_C(1337987072), // FMLAv2i64_indexed
3592 UINT64_C(239078400), // FMLAv4f16
3593 UINT64_C(1310772224), // FMLAv4f32
3594 UINT64_C(251662336), // FMLAv4i16_indexed
3595 UINT64_C(1333792768), // FMLAv4i32_indexed
3596 UINT64_C(1312820224), // FMLAv8f16
3597 UINT64_C(1325404160), // FMLAv8i16_indexed
3598 UINT64_C(1679877120), // FMLLA_ZZZ_HtoS
3599 UINT64_C(796966912), // FMLSL2lanev4f16
3600 UINT64_C(1870708736), // FMLSL2lanev8f16
3601 UINT64_C(782289920), // FMLSL2v4f16
3602 UINT64_C(1856031744), // FMLSL2v8f16
3603 UINT64_C(1688231936), // FMLSLB_ZZZI_SHH
3604 UINT64_C(1688248320), // FMLSLB_ZZZ_SHH
3605 UINT64_C(1688232960), // FMLSLT_ZZZI_SHH
3606 UINT64_C(1688249344), // FMLSLT_ZZZ_SHH
3607 UINT64_C(3246395400), // FMLSL_MZZI_HtoS
3608 UINT64_C(3240102920), // FMLSL_MZZ_HtoS
3609 UINT64_C(3248490504), // FMLSL_VG2_M2Z2Z_HtoS
3610 UINT64_C(3247443976), // FMLSL_VG2_M2ZZI_HtoS
3611 UINT64_C(3240101896), // FMLSL_VG2_M2ZZ_HtoS
3612 UINT64_C(3248556040), // FMLSL_VG4_M4Z4Z_HtoS
3613 UINT64_C(3247476744), // FMLSL_VG4_M4ZZI_HtoS
3614 UINT64_C(3241150472), // FMLSL_VG4_M4ZZ_HtoS
3615 UINT64_C(260063232), // FMLSLlanev4f16
3616 UINT64_C(1333805056), // FMLSLlanev8f16
3617 UINT64_C(245427200), // FMLSLv4f16
3618 UINT64_C(1319169024), // FMLSLv8f16
3619 UINT64_C(3252688904), // FMLS_VG2_M2Z2Z_D
3620 UINT64_C(3248492568), // FMLS_VG2_M2Z2Z_H
3621 UINT64_C(3248494600), // FMLS_VG2_M2Z2Z_S
3622 UINT64_C(3251634192), // FMLS_VG2_M2ZZI_D
3623 UINT64_C(3239055376), // FMLS_VG2_M2ZZI_H
3624 UINT64_C(3243245584), // FMLS_VG2_M2ZZI_S
3625 UINT64_C(3244300296), // FMLS_VG2_M2ZZ_D
3626 UINT64_C(3240107016), // FMLS_VG2_M2ZZ_H
3627 UINT64_C(3240105992), // FMLS_VG2_M2ZZ_S
3628 UINT64_C(3252754440), // FMLS_VG4_M4Z4Z_D
3629 UINT64_C(3248558104), // FMLS_VG4_M4Z4Z_H
3630 UINT64_C(3248560136), // FMLS_VG4_M4Z4Z_S
3631 UINT64_C(3251666960), // FMLS_VG4_M4ZZI_D
3632 UINT64_C(3239088144), // FMLS_VG4_M4ZZI_H
3633 UINT64_C(3243278352), // FMLS_VG4_M4ZZI_S
3634 UINT64_C(3245348872), // FMLS_VG4_M4ZZ_D
3635 UINT64_C(3241155592), // FMLS_VG4_M4ZZ_H
3636 UINT64_C(3241154568), // FMLS_VG4_M4ZZ_S
3637 UINT64_C(1709187072), // FMLS_ZPmZZ_D
3638 UINT64_C(1700798464), // FMLS_ZPmZZ_H
3639 UINT64_C(1704992768), // FMLS_ZPmZZ_S
3640 UINT64_C(1692402688), // FMLS_ZZZI_D
3641 UINT64_C(1679819776), // FMLS_ZZZI_H
3642 UINT64_C(1688208384), // FMLS_ZZZI_S
3643 UINT64_C(1593856000), // FMLSv1i16_indexed
3644 UINT64_C(1602244608), // FMLSv1i32_indexed
3645 UINT64_C(1606438912), // FMLSv1i64_indexed
3646 UINT64_C(245419008), // FMLSv2f32
3647 UINT64_C(1323355136), // FMLSv2f64
3648 UINT64_C(260067328), // FMLSv2i32_indexed
3649 UINT64_C(1338003456), // FMLSv2i64_indexed
3650 UINT64_C(247467008), // FMLSv4f16
3651 UINT64_C(1319160832), // FMLSv4f32
3652 UINT64_C(251678720), // FMLSv4i16_indexed
3653 UINT64_C(1333809152), // FMLSv4i32_indexed
3654 UINT64_C(1321208832), // FMLSv8f16
3655 UINT64_C(1325420544), // FMLSv8i16_indexed
3656 UINT64_C(1684070400), // FMMLA_ZZZ_BtoH
3657 UINT64_C(1679876096), // FMMLA_ZZZ_BtoS
3658 UINT64_C(1692460032), // FMMLA_ZZZ_D
3659 UINT64_C(1688265728), // FMMLA_ZZZ_S
3660 UINT64_C(1853942784), // FMMLAv4f32
3661 UINT64_C(1845554176), // FMMLAv8f16
3662 UINT64_C(2150629896), // FMOP4A_M2Z2Z_BtoH
3663 UINT64_C(2150629888), // FMOP4A_M2Z2Z_BtoS
3664 UINT64_C(2161115656), // FMOP4A_M2Z2Z_D
3665 UINT64_C(2165309960), // FMOP4A_M2Z2Z_H
3666 UINT64_C(2167407104), // FMOP4A_M2Z2Z_HtoS
3667 UINT64_C(2148532736), // FMOP4A_M2Z2Z_S
3668 UINT64_C(2149581320), // FMOP4A_M2ZZ_BtoH
3669 UINT64_C(2149581312), // FMOP4A_M2ZZ_BtoS
3670 UINT64_C(2160067080), // FMOP4A_M2ZZ_D
3671 UINT64_C(2164261384), // FMOP4A_M2ZZ_H
3672 UINT64_C(2166358528), // FMOP4A_M2ZZ_HtoS
3673 UINT64_C(2147484160), // FMOP4A_M2ZZ_S
3674 UINT64_C(2150629384), // FMOP4A_MZ2Z_BtoH
3675 UINT64_C(2150629376), // FMOP4A_MZ2Z_BtoS
3676 UINT64_C(2161115144), // FMOP4A_MZ2Z_D
3677 UINT64_C(2165309448), // FMOP4A_MZ2Z_H
3678 UINT64_C(2167406592), // FMOP4A_MZ2Z_HtoS
3679 UINT64_C(2148532224), // FMOP4A_MZ2Z_S
3680 UINT64_C(2149580808), // FMOP4A_MZZ_BtoH
3681 UINT64_C(2149580800), // FMOP4A_MZZ_BtoS
3682 UINT64_C(2160066568), // FMOP4A_MZZ_D
3683 UINT64_C(2164260872), // FMOP4A_MZZ_H
3684 UINT64_C(2166358016), // FMOP4A_MZZ_HtoS
3685 UINT64_C(2147483648), // FMOP4A_MZZ_S
3686 UINT64_C(2161115672), // FMOP4S_M2Z2Z_D
3687 UINT64_C(2165309976), // FMOP4S_M2Z2Z_H
3688 UINT64_C(2167407120), // FMOP4S_M2Z2Z_HtoS
3689 UINT64_C(2148532752), // FMOP4S_M2Z2Z_S
3690 UINT64_C(2160067096), // FMOP4S_M2ZZ_D
3691 UINT64_C(2164261400), // FMOP4S_M2ZZ_H
3692 UINT64_C(2166358544), // FMOP4S_M2ZZ_HtoS
3693 UINT64_C(2147484176), // FMOP4S_M2ZZ_S
3694 UINT64_C(2161115160), // FMOP4S_MZ2Z_D
3695 UINT64_C(2165309464), // FMOP4S_MZ2Z_H
3696 UINT64_C(2167406608), // FMOP4S_MZ2Z_HtoS
3697 UINT64_C(2148532240), // FMOP4S_MZ2Z_S
3698 UINT64_C(2160066584), // FMOP4S_MZZ_D
3699 UINT64_C(2164260888), // FMOP4S_MZZ_H
3700 UINT64_C(2166358032), // FMOP4S_MZZ_HtoS
3701 UINT64_C(2147483664), // FMOP4S_MZZ_S
3702 UINT64_C(2174746624), // FMOPAL_MPPZZ
3703 UINT64_C(2157969416), // FMOPA_MPPZZ_BtoH
3704 UINT64_C(2157969408), // FMOPA_MPPZZ_BtoS
3705 UINT64_C(2160066560), // FMOPA_MPPZZ_D
3706 UINT64_C(2172649480), // FMOPA_MPPZZ_H
3707 UINT64_C(2155872256), // FMOPA_MPPZZ_S
3708 UINT64_C(2174746640), // FMOPSL_MPPZZ
3709 UINT64_C(2160066576), // FMOPS_MPPZZ_D
3710 UINT64_C(2172649496), // FMOPS_MPPZZ_H
3711 UINT64_C(2155872272), // FMOPS_MPPZZ_S
3712 UINT64_C(2662203392), // FMOVDXHighr
3713 UINT64_C(2657484800), // FMOVDXr
3714 UINT64_C(509612032), // FMOVDi
3715 UINT64_C(509624320), // FMOVDr
3716 UINT64_C(518389760), // FMOVHWr
3717 UINT64_C(2665873408), // FMOVHXr
3718 UINT64_C(518000640), // FMOVHi
3719 UINT64_C(518012928), // FMOVHr
3720 UINT64_C(505806848), // FMOVSWr
3721 UINT64_C(505417728), // FMOVSi
3722 UINT64_C(505430016), // FMOVSr
3723 UINT64_C(518455296), // FMOVWHr
3724 UINT64_C(505872384), // FMOVWSr
3725 UINT64_C(2662268928), // FMOVXDHighr
3726 UINT64_C(2657550336), // FMOVXDr
3727 UINT64_C(2665938944), // FMOVXHr
3728 UINT64_C(251720704), // FMOVv2f32_ns
3729 UINT64_C(1862333440), // FMOVv2f64_ns
3730 UINT64_C(251722752), // FMOVv4f16_ns
3731 UINT64_C(1325462528), // FMOVv4f32_ns
3732 UINT64_C(1325464576), // FMOVv8f16_ns
3733 UINT64_C(1709219840), // FMSB_ZPmZZ_D
3734 UINT64_C(1700831232), // FMSB_ZPmZZ_H
3735 UINT64_C(1705025536), // FMSB_ZPmZZ_S
3736 UINT64_C(524320768), // FMSUBDrrr
3737 UINT64_C(532709376), // FMSUBHrrr
3738 UINT64_C(520126464), // FMSUBSrrr
3739 UINT64_C(509609984), // FMULDrr
3740 UINT64_C(517998592), // FMULHrr
3741 UINT64_C(505415680), // FMULSrr
3742 UINT64_C(1581259776), // FMULX16
3743 UINT64_C(1579211776), // FMULX32
3744 UINT64_C(1583406080), // FMULX64
3745 UINT64_C(1707769856), // FMULX_ZPmZ_D
3746 UINT64_C(1699381248), // FMULX_ZPmZ_H
3747 UINT64_C(1703575552), // FMULX_ZPmZ_S
3748 UINT64_C(2130743296), // FMULXv1i16_indexed
3749 UINT64_C(2139131904), // FMULXv1i32_indexed
3750 UINT64_C(2143326208), // FMULXv1i64_indexed
3751 UINT64_C(237034496), // FMULXv2f32
3752 UINT64_C(1314970624), // FMULXv2f64
3753 UINT64_C(796954624), // FMULXv2i32_indexed
3754 UINT64_C(1874890752), // FMULXv2i64_indexed
3755 UINT64_C(239082496), // FMULXv4f16
3756 UINT64_C(1310776320), // FMULXv4f32
3757 UINT64_C(788566016), // FMULXv4i16_indexed
3758 UINT64_C(1870696448), // FMULXv4i32_indexed
3759 UINT64_C(1312824320), // FMULXv8f16
3760 UINT64_C(1862307840), // FMULXv8i16_indexed
3761 UINT64_C(3252741120), // FMUL_2Z2Z_D
3762 UINT64_C(3244352512), // FMUL_2Z2Z_H
3763 UINT64_C(3248546816), // FMUL_2Z2Z_S
3764 UINT64_C(3252742144), // FMUL_2ZZ_D
3765 UINT64_C(3244353536), // FMUL_2ZZ_H
3766 UINT64_C(3248547840), // FMUL_2ZZ_S
3767 UINT64_C(3252806656), // FMUL_4Z4Z_D
3768 UINT64_C(3244418048), // FMUL_4Z4Z_H
3769 UINT64_C(3248612352), // FMUL_4Z4Z_S
3770 UINT64_C(3252807680), // FMUL_4ZZ_D
3771 UINT64_C(3244419072), // FMUL_4ZZ_H
3772 UINT64_C(3248613376), // FMUL_4ZZ_S
3773 UINT64_C(1708818432), // FMUL_ZPmI_D
3774 UINT64_C(1700429824), // FMUL_ZPmI_H
3775 UINT64_C(1704624128), // FMUL_ZPmI_S
3776 UINT64_C(1707245568), // FMUL_ZPmZ_D
3777 UINT64_C(1698856960), // FMUL_ZPmZ_H
3778 UINT64_C(1703051264), // FMUL_ZPmZ_S
3779 UINT64_C(1692409856), // FMUL_ZZZI_D
3780 UINT64_C(1679826944), // FMUL_ZZZI_H
3781 UINT64_C(1688215552), // FMUL_ZZZI_S
3782 UINT64_C(1707083776), // FMUL_ZZZ_D
3783 UINT64_C(1698695168), // FMUL_ZZZ_H
3784 UINT64_C(1702889472), // FMUL_ZZZ_S
3785 UINT64_C(1593872384), // FMULv1i16_indexed
3786 UINT64_C(1602260992), // FMULv1i32_indexed
3787 UINT64_C(1606455296), // FMULv1i64_indexed
3788 UINT64_C(773905408), // FMULv2f32
3789 UINT64_C(1851841536), // FMULv2f64
3790 UINT64_C(260083712), // FMULv2i32_indexed
3791 UINT64_C(1338019840), // FMULv2i64_indexed
3792 UINT64_C(775953408), // FMULv4f16
3793 UINT64_C(1847647232), // FMULv4f32
3794 UINT64_C(251695104), // FMULv4i16_indexed
3795 UINT64_C(1333825536), // FMULv4i32_indexed
3796 UINT64_C(1849695232), // FMULv8f16
3797 UINT64_C(1325436928), // FMULv8i16_indexed
3798 UINT64_C(509689856), // FNEGDr
3799 UINT64_C(518078464), // FNEGHr
3800 UINT64_C(505495552), // FNEGSr
3801 UINT64_C(81633280), // FNEG_ZPmZ_D
3802 UINT64_C(73244672), // FNEG_ZPmZ_H
3803 UINT64_C(77438976), // FNEG_ZPmZ_S
3804 UINT64_C(80584704), // FNEG_ZPzZ_D
3805 UINT64_C(72196096), // FNEG_ZPzZ_H
3806 UINT64_C(76390400), // FNEG_ZPzZ_S
3807 UINT64_C(782301184), // FNEGv2f32
3808 UINT64_C(1860237312), // FNEGv2f64
3809 UINT64_C(788068352), // FNEGv4f16
3810 UINT64_C(1856043008), // FNEGv4f32
3811 UINT64_C(1861810176), // FNEGv8f16
3812 UINT64_C(526385152), // FNMADDDrrr
3813 UINT64_C(534773760), // FNMADDHrrr
3814 UINT64_C(522190848), // FNMADDSrrr
3815 UINT64_C(1709228032), // FNMAD_ZPmZZ_D
3816 UINT64_C(1700839424), // FNMAD_ZPmZZ_H
3817 UINT64_C(1705033728), // FNMAD_ZPmZZ_S
3818 UINT64_C(1709195264), // FNMLA_ZPmZZ_D
3819 UINT64_C(1700806656), // FNMLA_ZPmZZ_H
3820 UINT64_C(1705000960), // FNMLA_ZPmZZ_S
3821 UINT64_C(1709203456), // FNMLS_ZPmZZ_D
3822 UINT64_C(1700814848), // FNMLS_ZPmZZ_H
3823 UINT64_C(1705009152), // FNMLS_ZPmZZ_S
3824 UINT64_C(1709236224), // FNMSB_ZPmZZ_D
3825 UINT64_C(1700847616), // FNMSB_ZPmZZ_H
3826 UINT64_C(1705041920), // FNMSB_ZPmZZ_S
3827 UINT64_C(526417920), // FNMSUBDrrr
3828 UINT64_C(534806528), // FNMSUBHrrr
3829 UINT64_C(522223616), // FNMSUBSrrr
3830 UINT64_C(509642752), // FNMULDrr
3831 UINT64_C(518031360), // FNMULHrr
3832 UINT64_C(505448448), // FNMULSrr
3833 UINT64_C(1708011520), // FRECPE_ZZ_D
3834 UINT64_C(1699622912), // FRECPE_ZZ_H
3835 UINT64_C(1703817216), // FRECPE_ZZ_S
3836 UINT64_C(1593432064), // FRECPEv1f16
3837 UINT64_C(1587664896), // FRECPEv1i32
3838 UINT64_C(1591859200), // FRECPEv1i64
3839 UINT64_C(245487616), // FRECPEv2f32
3840 UINT64_C(1323423744), // FRECPEv2f64
3841 UINT64_C(251254784), // FRECPEv4f16
3842 UINT64_C(1319229440), // FRECPEv4f32
3843 UINT64_C(1324996608), // FRECPEv8f16
3844 UINT64_C(1581267968), // FRECPS16
3845 UINT64_C(1579219968), // FRECPS32
3846 UINT64_C(1583414272), // FRECPS64
3847 UINT64_C(1707087872), // FRECPS_ZZZ_D
3848 UINT64_C(1698699264), // FRECPS_ZZZ_H
3849 UINT64_C(1702893568), // FRECPS_ZZZ_S
3850 UINT64_C(237042688), // FRECPSv2f32
3851 UINT64_C(1314978816), // FRECPSv2f64
3852 UINT64_C(239090688), // FRECPSv4f16
3853 UINT64_C(1310784512), // FRECPSv4f32
3854 UINT64_C(1312832512), // FRECPSv8f16
3855 UINT64_C(1707909120), // FRECPX_ZPmZ_D
3856 UINT64_C(1699520512), // FRECPX_ZPmZ_H
3857 UINT64_C(1703714816), // FRECPX_ZPmZ_S
3858 UINT64_C(1692106752), // FRECPX_ZPzZ_D
3859 UINT64_C(1683718144), // FRECPX_ZPzZ_H
3860 UINT64_C(1687912448), // FRECPX_ZPzZ_S
3861 UINT64_C(1593440256), // FRECPXv1f16
3862 UINT64_C(1587673088), // FRECPXv1i32
3863 UINT64_C(1591867392), // FRECPXv1i64
3864 UINT64_C(510181376), // FRINT32XDr
3865 UINT64_C(505987072), // FRINT32XSr
3866 UINT64_C(1695784960), // FRINT32X_ZPmZ_D
3867 UINT64_C(1695653888), // FRINT32X_ZPmZ_S
3868 UINT64_C(1679613952), // FRINT32X_ZPzZ_D
3869 UINT64_C(1679597568), // FRINT32X_ZPzZ_S
3870 UINT64_C(773974016), // FRINT32Xv2f32
3871 UINT64_C(1851910144), // FRINT32Xv2f64
3872 UINT64_C(1847715840), // FRINT32Xv4f32
3873 UINT64_C(510148608), // FRINT32ZDr
3874 UINT64_C(505954304), // FRINT32ZSr
3875 UINT64_C(1695719424), // FRINT32Z_ZPmZ_D
3876 UINT64_C(1695588352), // FRINT32Z_ZPmZ_S
3877 UINT64_C(1679605760), // FRINT32Z_ZPzZ_D
3878 UINT64_C(1679589376), // FRINT32Z_ZPzZ_S
3879 UINT64_C(237103104), // FRINT32Zv2f32
3880 UINT64_C(1315039232), // FRINT32Zv2f64
3881 UINT64_C(1310844928), // FRINT32Zv4f32
3882 UINT64_C(510246912), // FRINT64XDr
3883 UINT64_C(506052608), // FRINT64XSr
3884 UINT64_C(1695981568), // FRINT64X_ZPmZ_D
3885 UINT64_C(1695850496), // FRINT64X_ZPmZ_S
3886 UINT64_C(1679679488), // FRINT64X_ZPzZ_D
3887 UINT64_C(1679663104), // FRINT64X_ZPzZ_S
3888 UINT64_C(773978112), // FRINT64Xv2f32
3889 UINT64_C(1851914240), // FRINT64Xv2f64
3890 UINT64_C(1847719936), // FRINT64Xv4f32
3891 UINT64_C(510214144), // FRINT64ZDr
3892 UINT64_C(506019840), // FRINT64ZSr
3893 UINT64_C(1696047104), // FRINT64Z_ZPmZ_D
3894 UINT64_C(1695916032), // FRINT64Z_ZPmZ_S
3895 UINT64_C(1679671296), // FRINT64Z_ZPzZ_D
3896 UINT64_C(1679654912), // FRINT64Z_ZPzZ_S
3897 UINT64_C(237107200), // FRINT64Zv2f32
3898 UINT64_C(1315043328), // FRINT64Zv2f64
3899 UINT64_C(1310849024), // FRINT64Zv4f32
3900 UINT64_C(510017536), // FRINTADr
3901 UINT64_C(518406144), // FRINTAHr
3902 UINT64_C(505823232), // FRINTASr
3903 UINT64_C(3249332224), // FRINTA_2Z2Z_S
3904 UINT64_C(3250380800), // FRINTA_4Z4Z_S
3905 UINT64_C(1707384832), // FRINTA_ZPmZ_D
3906 UINT64_C(1698996224), // FRINTA_ZPmZ_H
3907 UINT64_C(1703190528), // FRINTA_ZPmZ_S
3908 UINT64_C(1691975680), // FRINTA_ZPzZ_D
3909 UINT64_C(1683587072), // FRINTA_ZPzZ_H
3910 UINT64_C(1687781376), // FRINTA_ZPzZ_S
3911 UINT64_C(773949440), // FRINTAv2f32
3912 UINT64_C(1851885568), // FRINTAv2f64
3913 UINT64_C(779716608), // FRINTAv4f16
3914 UINT64_C(1847691264), // FRINTAv4f32
3915 UINT64_C(1853458432), // FRINTAv8f16
3916 UINT64_C(510115840), // FRINTIDr
3917 UINT64_C(518504448), // FRINTIHr
3918 UINT64_C(505921536), // FRINTISr
3919 UINT64_C(1707581440), // FRINTI_ZPmZ_D
3920 UINT64_C(1699192832), // FRINTI_ZPmZ_H
3921 UINT64_C(1703387136), // FRINTI_ZPmZ_S
3922 UINT64_C(1692000256), // FRINTI_ZPzZ_D
3923 UINT64_C(1683611648), // FRINTI_ZPzZ_H
3924 UINT64_C(1687805952), // FRINTI_ZPzZ_S
3925 UINT64_C(782342144), // FRINTIv2f32
3926 UINT64_C(1860278272), // FRINTIv2f64
3927 UINT64_C(788109312), // FRINTIv4f16
3928 UINT64_C(1856083968), // FRINTIv4f32
3929 UINT64_C(1861851136), // FRINTIv8f16
3930 UINT64_C(509952000), // FRINTMDr
3931 UINT64_C(518340608), // FRINTMHr
3932 UINT64_C(505757696), // FRINTMSr
3933 UINT64_C(3249201152), // FRINTM_2Z2Z_S
3934 UINT64_C(3250249728), // FRINTM_4Z4Z_S
3935 UINT64_C(1707253760), // FRINTM_ZPmZ_D
3936 UINT64_C(1698865152), // FRINTM_ZPmZ_H
3937 UINT64_C(1703059456), // FRINTM_ZPmZ_S
3938 UINT64_C(1691926528), // FRINTM_ZPzZ_D
3939 UINT64_C(1683537920), // FRINTM_ZPzZ_H
3940 UINT64_C(1687732224), // FRINTM_ZPzZ_S
3941 UINT64_C(237082624), // FRINTMv2f32
3942 UINT64_C(1315018752), // FRINTMv2f64
3943 UINT64_C(242849792), // FRINTMv4f16
3944 UINT64_C(1310824448), // FRINTMv4f32
3945 UINT64_C(1316591616), // FRINTMv8f16
3946 UINT64_C(509886464), // FRINTNDr
3947 UINT64_C(518275072), // FRINTNHr
3948 UINT64_C(505692160), // FRINTNSr
3949 UINT64_C(3249070080), // FRINTN_2Z2Z_S
3950 UINT64_C(3250118656), // FRINTN_4Z4Z_S
3951 UINT64_C(1707122688), // FRINTN_ZPmZ_D
3952 UINT64_C(1698734080), // FRINTN_ZPmZ_H
3953 UINT64_C(1702928384), // FRINTN_ZPmZ_S
3954 UINT64_C(1691910144), // FRINTN_ZPzZ_D
3955 UINT64_C(1683521536), // FRINTN_ZPzZ_H
3956 UINT64_C(1687715840), // FRINTN_ZPzZ_S
3957 UINT64_C(237078528), // FRINTNv2f32
3958 UINT64_C(1315014656), // FRINTNv2f64
3959 UINT64_C(242845696), // FRINTNv4f16
3960 UINT64_C(1310820352), // FRINTNv4f32
3961 UINT64_C(1316587520), // FRINTNv8f16
3962 UINT64_C(509919232), // FRINTPDr
3963 UINT64_C(518307840), // FRINTPHr
3964 UINT64_C(505724928), // FRINTPSr
3965 UINT64_C(3249135616), // FRINTP_2Z2Z_S
3966 UINT64_C(3250184192), // FRINTP_4Z4Z_S
3967 UINT64_C(1707188224), // FRINTP_ZPmZ_D
3968 UINT64_C(1698799616), // FRINTP_ZPmZ_H
3969 UINT64_C(1702993920), // FRINTP_ZPmZ_S
3970 UINT64_C(1691918336), // FRINTP_ZPzZ_D
3971 UINT64_C(1683529728), // FRINTP_ZPzZ_H
3972 UINT64_C(1687724032), // FRINTP_ZPzZ_S
3973 UINT64_C(245467136), // FRINTPv2f32
3974 UINT64_C(1323403264), // FRINTPv2f64
3975 UINT64_C(251234304), // FRINTPv4f16
3976 UINT64_C(1319208960), // FRINTPv4f32
3977 UINT64_C(1324976128), // FRINTPv8f16
3978 UINT64_C(510083072), // FRINTXDr
3979 UINT64_C(518471680), // FRINTXHr
3980 UINT64_C(505888768), // FRINTXSr
3981 UINT64_C(1707515904), // FRINTX_ZPmZ_D
3982 UINT64_C(1699127296), // FRINTX_ZPmZ_H
3983 UINT64_C(1703321600), // FRINTX_ZPmZ_S
3984 UINT64_C(1691992064), // FRINTX_ZPzZ_D
3985 UINT64_C(1683603456), // FRINTX_ZPzZ_H
3986 UINT64_C(1687797760), // FRINTX_ZPzZ_S
3987 UINT64_C(773953536), // FRINTXv2f32
3988 UINT64_C(1851889664), // FRINTXv2f64
3989 UINT64_C(779720704), // FRINTXv4f16
3990 UINT64_C(1847695360), // FRINTXv4f32
3991 UINT64_C(1853462528), // FRINTXv8f16
3992 UINT64_C(509984768), // FRINTZDr
3993 UINT64_C(518373376), // FRINTZHr
3994 UINT64_C(505790464), // FRINTZSr
3995 UINT64_C(1707319296), // FRINTZ_ZPmZ_D
3996 UINT64_C(1698930688), // FRINTZ_ZPmZ_H
3997 UINT64_C(1703124992), // FRINTZ_ZPmZ_S
3998 UINT64_C(1691934720), // FRINTZ_ZPzZ_D
3999 UINT64_C(1683546112), // FRINTZ_ZPzZ_H
4000 UINT64_C(1687740416), // FRINTZ_ZPzZ_S
4001 UINT64_C(245471232), // FRINTZv2f32
4002 UINT64_C(1323407360), // FRINTZv2f64
4003 UINT64_C(251238400), // FRINTZv4f16
4004 UINT64_C(1319213056), // FRINTZv4f32
4005 UINT64_C(1324980224), // FRINTZv8f16
4006 UINT64_C(1708077056), // FRSQRTE_ZZ_D
4007 UINT64_C(1699688448), // FRSQRTE_ZZ_H
4008 UINT64_C(1703882752), // FRSQRTE_ZZ_S
4009 UINT64_C(2130302976), // FRSQRTEv1f16
4010 UINT64_C(2124535808), // FRSQRTEv1i32
4011 UINT64_C(2128730112), // FRSQRTEv1i64
4012 UINT64_C(782358528), // FRSQRTEv2f32
4013 UINT64_C(1860294656), // FRSQRTEv2f64
4014 UINT64_C(788125696), // FRSQRTEv4f16
4015 UINT64_C(1856100352), // FRSQRTEv4f32
4016 UINT64_C(1861867520), // FRSQRTEv8f16
4017 UINT64_C(1589656576), // FRSQRTS16
4018 UINT64_C(1587608576), // FRSQRTS32
4019 UINT64_C(1591802880), // FRSQRTS64
4020 UINT64_C(1707088896), // FRSQRTS_ZZZ_D
4021 UINT64_C(1698700288), // FRSQRTS_ZZZ_H
4022 UINT64_C(1702894592), // FRSQRTS_ZZZ_S
4023 UINT64_C(245431296), // FRSQRTSv2f32
4024 UINT64_C(1323367424), // FRSQRTSv2f64
4025 UINT64_C(247479296), // FRSQRTSv4f16
4026 UINT64_C(1319173120), // FRSQRTSv4f32
4027 UINT64_C(1321221120), // FRSQRTSv8f16
4028 UINT64_C(3252728192), // FSCALE_2Z2Z_D
4029 UINT64_C(3244339584), // FSCALE_2Z2Z_H
4030 UINT64_C(3248533888), // FSCALE_2Z2Z_S
4031 UINT64_C(3252724096), // FSCALE_2ZZ_D
4032 UINT64_C(3244335488), // FSCALE_2ZZ_H
4033 UINT64_C(3248529792), // FSCALE_2ZZ_S
4034 UINT64_C(3252730240), // FSCALE_4Z4Z_D
4035 UINT64_C(3244341632), // FSCALE_4Z4Z_H
4036 UINT64_C(3248535936), // FSCALE_4Z4Z_S
4037 UINT64_C(3252726144), // FSCALE_4ZZ_D
4038 UINT64_C(3244337536), // FSCALE_4ZZ_H
4039 UINT64_C(3248531840), // FSCALE_4ZZ_S
4040 UINT64_C(1707704320), // FSCALE_ZPmZ_D
4041 UINT64_C(1699315712), // FSCALE_ZPmZ_H
4042 UINT64_C(1703510016), // FSCALE_ZPmZ_S
4043 UINT64_C(782302208), // FSCALEv2f32
4044 UINT64_C(1860238336), // FSCALEv2f64
4045 UINT64_C(784350208), // FSCALEv4f16
4046 UINT64_C(1856044032), // FSCALEv4f32
4047 UINT64_C(1858092032), // FSCALEv8f16
4048 UINT64_C(509722624), // FSQRTDr
4049 UINT64_C(518111232), // FSQRTHr
4050 UINT64_C(505528320), // FSQRTSr
4051 UINT64_C(1692114944), // FSQRT_ZPZz_D
4052 UINT64_C(1683726336), // FSQRT_ZPZz_H
4053 UINT64_C(1687920640), // FSQRT_ZPZz_S
4054 UINT64_C(1707974656), // FSQRT_ZPmZ_D
4055 UINT64_C(1699586048), // FSQRT_ZPmZ_H
4056 UINT64_C(1703780352), // FSQRT_ZPmZ_S
4057 UINT64_C(782366720), // FSQRTv2f32
4058 UINT64_C(1860302848), // FSQRTv2f64
4059 UINT64_C(788133888), // FSQRTv4f16
4060 UINT64_C(1856108544), // FSQRTv4f32
4061 UINT64_C(1861875712), // FSQRTv8f16
4062 UINT64_C(509622272), // FSUBDrr
4063 UINT64_C(518010880), // FSUBHrr
4064 UINT64_C(1708883968), // FSUBR_ZPmI_D
4065 UINT64_C(1700495360), // FSUBR_ZPmI_H
4066 UINT64_C(1704689664), // FSUBR_ZPmI_S
4067 UINT64_C(1707311104), // FSUBR_ZPmZ_D
4068 UINT64_C(1698922496), // FSUBR_ZPmZ_H
4069 UINT64_C(1703116800), // FSUBR_ZPmZ_S
4070 UINT64_C(505427968), // FSUBSrr
4071 UINT64_C(3252689928), // FSUB_VG2_M2Z_D
4072 UINT64_C(3248757768), // FSUB_VG2_M2Z_H
4073 UINT64_C(3248495624), // FSUB_VG2_M2Z_S
4074 UINT64_C(3252755464), // FSUB_VG4_M4Z_D
4075 UINT64_C(3248823304), // FSUB_VG4_M4Z_H
4076 UINT64_C(3248561160), // FSUB_VG4_M4Z_S
4077 UINT64_C(1708752896), // FSUB_ZPmI_D
4078 UINT64_C(1700364288), // FSUB_ZPmI_H
4079 UINT64_C(1704558592), // FSUB_ZPmI_S
4080 UINT64_C(1707180032), // FSUB_ZPmZ_D
4081 UINT64_C(1698791424), // FSUB_ZPmZ_H
4082 UINT64_C(1702985728), // FSUB_ZPmZ_S
4083 UINT64_C(1707082752), // FSUB_ZZZ_D
4084 UINT64_C(1698694144), // FSUB_ZZZ_H
4085 UINT64_C(1702888448), // FSUB_ZZZ_S
4086 UINT64_C(245421056), // FSUBv2f32
4087 UINT64_C(1323357184), // FSUBv2f64
4088 UINT64_C(247469056), // FSUBv4f16
4089 UINT64_C(1319162880), // FSUBv4f32
4090 UINT64_C(1321210880), // FSUBv8f16
4091 UINT64_C(1708163072), // FTMAD_ZZI_D
4092 UINT64_C(1699774464), // FTMAD_ZZI_H
4093 UINT64_C(1703968768), // FTMAD_ZZI_S
4094 UINT64_C(2153775112), // FTMOPA_M2ZZZI_BtoH
4095 UINT64_C(2153775104), // FTMOPA_M2ZZZI_BtoS
4096 UINT64_C(2168455176), // FTMOPA_M2ZZZI_HtoH
4097 UINT64_C(2170552320), // FTMOPA_M2ZZZI_HtoS
4098 UINT64_C(2151677952), // FTMOPA_M2ZZZI_StoS
4099 UINT64_C(1707084800), // FTSMUL_ZZZ_D
4100 UINT64_C(1698696192), // FTSMUL_ZZZ_H
4101 UINT64_C(1702890496), // FTSMUL_ZZZ_S
4102 UINT64_C(81833984), // FTSSEL_ZZZ_D
4103 UINT64_C(73445376), // FTSSEL_ZZZ_H
4104 UINT64_C(77639680), // FTSSEL_ZZZ_S
4105 UINT64_C(3251636224), // FVDOTB_VG4_M2ZZI_BtoS
4106 UINT64_C(3251636240), // FVDOTT_VG4_M2ZZI_BtoS
4107 UINT64_C(3251638304), // FVDOT_VG2_M2ZZI_BtoH
4108 UINT64_C(3243245576), // FVDOT_VG2_M2ZZI_HtoS
4109 UINT64_C(3574101951), // GCSPOPCX
4110 UINT64_C(3576395552), // GCSPOPM
4111 UINT64_C(3574101983), // GCSPOPX
4112 UINT64_C(3574298368), // GCSPUSHM
4113 UINT64_C(3574101919), // GCSPUSHX
4114 UINT64_C(3574298432), // GCSSS1
4115 UINT64_C(3576395616), // GCSSS2
4116 UINT64_C(3642690560), // GCSSTR
4117 UINT64_C(3642694656), // GCSSTTR
4118 UINT64_C(3292577792), // GLD1B_D
4119 UINT64_C(3290480640), // GLD1B_D_IMM
4120 UINT64_C(3292545024), // GLD1B_D_SXTW
4121 UINT64_C(3288350720), // GLD1B_D_UXTW
4122 UINT64_C(2216738816), // GLD1B_S_IMM
4123 UINT64_C(2218803200), // GLD1B_S_SXTW
4124 UINT64_C(2214608896), // GLD1B_S_UXTW
4125 UINT64_C(3317743616), // GLD1D
4126 UINT64_C(3315646464), // GLD1D_IMM
4127 UINT64_C(3319840768), // GLD1D_SCALED
4128 UINT64_C(3317710848), // GLD1D_SXTW
4129 UINT64_C(3319808000), // GLD1D_SXTW_SCALED
4130 UINT64_C(3313516544), // GLD1D_UXTW
4131 UINT64_C(3315613696), // GLD1D_UXTW_SCALED
4132 UINT64_C(3300966400), // GLD1H_D
4133 UINT64_C(3298869248), // GLD1H_D_IMM
4134 UINT64_C(3303063552), // GLD1H_D_SCALED
4135 UINT64_C(3300933632), // GLD1H_D_SXTW
4136 UINT64_C(3303030784), // GLD1H_D_SXTW_SCALED
4137 UINT64_C(3296739328), // GLD1H_D_UXTW
4138 UINT64_C(3298836480), // GLD1H_D_UXTW_SCALED
4139 UINT64_C(2225127424), // GLD1H_S_IMM
4140 UINT64_C(2227191808), // GLD1H_S_SXTW
4141 UINT64_C(2229288960), // GLD1H_S_SXTW_SCALED
4142 UINT64_C(2222997504), // GLD1H_S_UXTW
4143 UINT64_C(2225094656), // GLD1H_S_UXTW_SCALED
4144 UINT64_C(3288375296), // GLD1Q
4145 UINT64_C(3292561408), // GLD1SB_D
4146 UINT64_C(3290464256), // GLD1SB_D_IMM
4147 UINT64_C(3292528640), // GLD1SB_D_SXTW
4148 UINT64_C(3288334336), // GLD1SB_D_UXTW
4149 UINT64_C(2216722432), // GLD1SB_S_IMM
4150 UINT64_C(2218786816), // GLD1SB_S_SXTW
4151 UINT64_C(2214592512), // GLD1SB_S_UXTW
4152 UINT64_C(3300950016), // GLD1SH_D
4153 UINT64_C(3298852864), // GLD1SH_D_IMM
4154 UINT64_C(3303047168), // GLD1SH_D_SCALED
4155 UINT64_C(3300917248), // GLD1SH_D_SXTW
4156 UINT64_C(3303014400), // GLD1SH_D_SXTW_SCALED
4157 UINT64_C(3296722944), // GLD1SH_D_UXTW
4158 UINT64_C(3298820096), // GLD1SH_D_UXTW_SCALED
4159 UINT64_C(2225111040), // GLD1SH_S_IMM
4160 UINT64_C(2227175424), // GLD1SH_S_SXTW
4161 UINT64_C(2229272576), // GLD1SH_S_SXTW_SCALED
4162 UINT64_C(2222981120), // GLD1SH_S_UXTW
4163 UINT64_C(2225078272), // GLD1SH_S_UXTW_SCALED
4164 UINT64_C(3309338624), // GLD1SW_D
4165 UINT64_C(3307241472), // GLD1SW_D_IMM
4166 UINT64_C(3311435776), // GLD1SW_D_SCALED
4167 UINT64_C(3309305856), // GLD1SW_D_SXTW
4168 UINT64_C(3311403008), // GLD1SW_D_SXTW_SCALED
4169 UINT64_C(3305111552), // GLD1SW_D_UXTW
4170 UINT64_C(3307208704), // GLD1SW_D_UXTW_SCALED
4171 UINT64_C(3309355008), // GLD1W_D
4172 UINT64_C(3307257856), // GLD1W_D_IMM
4173 UINT64_C(3311452160), // GLD1W_D_SCALED
4174 UINT64_C(3309322240), // GLD1W_D_SXTW
4175 UINT64_C(3311419392), // GLD1W_D_SXTW_SCALED
4176 UINT64_C(3305127936), // GLD1W_D_UXTW
4177 UINT64_C(3307225088), // GLD1W_D_UXTW_SCALED
4178 UINT64_C(2233516032), // GLD1W_IMM
4179 UINT64_C(2235580416), // GLD1W_SXTW
4180 UINT64_C(2237677568), // GLD1W_SXTW_SCALED
4181 UINT64_C(2231386112), // GLD1W_UXTW
4182 UINT64_C(2233483264), // GLD1W_UXTW_SCALED
4183 UINT64_C(3292585984), // GLDFF1B_D
4184 UINT64_C(3290488832), // GLDFF1B_D_IMM
4185 UINT64_C(3292553216), // GLDFF1B_D_SXTW
4186 UINT64_C(3288358912), // GLDFF1B_D_UXTW
4187 UINT64_C(2216747008), // GLDFF1B_S_IMM
4188 UINT64_C(2218811392), // GLDFF1B_S_SXTW
4189 UINT64_C(2214617088), // GLDFF1B_S_UXTW
4190 UINT64_C(3317751808), // GLDFF1D
4191 UINT64_C(3315654656), // GLDFF1D_IMM
4192 UINT64_C(3319848960), // GLDFF1D_SCALED
4193 UINT64_C(3317719040), // GLDFF1D_SXTW
4194 UINT64_C(3319816192), // GLDFF1D_SXTW_SCALED
4195 UINT64_C(3313524736), // GLDFF1D_UXTW
4196 UINT64_C(3315621888), // GLDFF1D_UXTW_SCALED
4197 UINT64_C(3300974592), // GLDFF1H_D
4198 UINT64_C(3298877440), // GLDFF1H_D_IMM
4199 UINT64_C(3303071744), // GLDFF1H_D_SCALED
4200 UINT64_C(3300941824), // GLDFF1H_D_SXTW
4201 UINT64_C(3303038976), // GLDFF1H_D_SXTW_SCALED
4202 UINT64_C(3296747520), // GLDFF1H_D_UXTW
4203 UINT64_C(3298844672), // GLDFF1H_D_UXTW_SCALED
4204 UINT64_C(2225135616), // GLDFF1H_S_IMM
4205 UINT64_C(2227200000), // GLDFF1H_S_SXTW
4206 UINT64_C(2229297152), // GLDFF1H_S_SXTW_SCALED
4207 UINT64_C(2223005696), // GLDFF1H_S_UXTW
4208 UINT64_C(2225102848), // GLDFF1H_S_UXTW_SCALED
4209 UINT64_C(3292569600), // GLDFF1SB_D
4210 UINT64_C(3290472448), // GLDFF1SB_D_IMM
4211 UINT64_C(3292536832), // GLDFF1SB_D_SXTW
4212 UINT64_C(3288342528), // GLDFF1SB_D_UXTW
4213 UINT64_C(2216730624), // GLDFF1SB_S_IMM
4214 UINT64_C(2218795008), // GLDFF1SB_S_SXTW
4215 UINT64_C(2214600704), // GLDFF1SB_S_UXTW
4216 UINT64_C(3300958208), // GLDFF1SH_D
4217 UINT64_C(3298861056), // GLDFF1SH_D_IMM
4218 UINT64_C(3303055360), // GLDFF1SH_D_SCALED
4219 UINT64_C(3300925440), // GLDFF1SH_D_SXTW
4220 UINT64_C(3303022592), // GLDFF1SH_D_SXTW_SCALED
4221 UINT64_C(3296731136), // GLDFF1SH_D_UXTW
4222 UINT64_C(3298828288), // GLDFF1SH_D_UXTW_SCALED
4223 UINT64_C(2225119232), // GLDFF1SH_S_IMM
4224 UINT64_C(2227183616), // GLDFF1SH_S_SXTW
4225 UINT64_C(2229280768), // GLDFF1SH_S_SXTW_SCALED
4226 UINT64_C(2222989312), // GLDFF1SH_S_UXTW
4227 UINT64_C(2225086464), // GLDFF1SH_S_UXTW_SCALED
4228 UINT64_C(3309346816), // GLDFF1SW_D
4229 UINT64_C(3307249664), // GLDFF1SW_D_IMM
4230 UINT64_C(3311443968), // GLDFF1SW_D_SCALED
4231 UINT64_C(3309314048), // GLDFF1SW_D_SXTW
4232 UINT64_C(3311411200), // GLDFF1SW_D_SXTW_SCALED
4233 UINT64_C(3305119744), // GLDFF1SW_D_UXTW
4234 UINT64_C(3307216896), // GLDFF1SW_D_UXTW_SCALED
4235 UINT64_C(3309363200), // GLDFF1W_D
4236 UINT64_C(3307266048), // GLDFF1W_D_IMM
4237 UINT64_C(3311460352), // GLDFF1W_D_SCALED
4238 UINT64_C(3309330432), // GLDFF1W_D_SXTW
4239 UINT64_C(3311427584), // GLDFF1W_D_SXTW_SCALED
4240 UINT64_C(3305136128), // GLDFF1W_D_UXTW
4241 UINT64_C(3307233280), // GLDFF1W_D_UXTW_SCALED
4242 UINT64_C(2233524224), // GLDFF1W_IMM
4243 UINT64_C(2235588608), // GLDFF1W_SXTW
4244 UINT64_C(2237685760), // GLDFF1W_SXTW_SCALED
4245 UINT64_C(2231394304), // GLDFF1W_UXTW
4246 UINT64_C(2233491456), // GLDFF1W_UXTW_SCALED
4247 UINT64_C(2596279296), // GMI
4248 UINT64_C(3573751839), // HINT
4249 UINT64_C(1172357120), // HISTCNT_ZPzZZ_D
4250 UINT64_C(1168162816), // HISTCNT_ZPzZZ_S
4251 UINT64_C(1159766016), // HISTSEG_ZZZ
4252 UINT64_C(3560964096), // HLT
4253 UINT64_C(3556769794), // HVC
4254 UINT64_C(70311936), // INCB_XPiI
4255 UINT64_C(82894848), // INCD_XPiI
4256 UINT64_C(82886656), // INCD_ZPiI
4257 UINT64_C(74506240), // INCH_XPiI
4258 UINT64_C(74498048), // INCH_ZPiI
4259 UINT64_C(623675392), // INCP_XP_B
4260 UINT64_C(636258304), // INCP_XP_D
4261 UINT64_C(627869696), // INCP_XP_H
4262 UINT64_C(632064000), // INCP_XP_S
4263 UINT64_C(636256256), // INCP_ZP_D
4264 UINT64_C(627867648), // INCP_ZP_H
4265 UINT64_C(632061952), // INCP_ZP_S
4266 UINT64_C(78700544), // INCW_XPiI
4267 UINT64_C(78692352), // INCW_ZPiI
4268 UINT64_C(69222400), // INDEX_II_B
4269 UINT64_C(81805312), // INDEX_II_D
4270 UINT64_C(73416704), // INDEX_II_H
4271 UINT64_C(77611008), // INDEX_II_S
4272 UINT64_C(69224448), // INDEX_IR_B
4273 UINT64_C(81807360), // INDEX_IR_D
4274 UINT64_C(73418752), // INDEX_IR_H
4275 UINT64_C(77613056), // INDEX_IR_S
4276 UINT64_C(69223424), // INDEX_RI_B
4277 UINT64_C(81806336), // INDEX_RI_D
4278 UINT64_C(73417728), // INDEX_RI_H
4279 UINT64_C(77612032), // INDEX_RI_S
4280 UINT64_C(69225472), // INDEX_RR_B
4281 UINT64_C(81808384), // INDEX_RR_D
4282 UINT64_C(73419776), // INDEX_RR_H
4283 UINT64_C(77614080), // INDEX_RR_S
4284 UINT64_C(3221225472), // INSERT_MXIPZ_H_B
4285 UINT64_C(3233808384), // INSERT_MXIPZ_H_D
4286 UINT64_C(3225419776), // INSERT_MXIPZ_H_H
4287 UINT64_C(3233873920), // INSERT_MXIPZ_H_Q
4288 UINT64_C(3229614080), // INSERT_MXIPZ_H_S
4289 UINT64_C(3221258240), // INSERT_MXIPZ_V_B
4290 UINT64_C(3233841152), // INSERT_MXIPZ_V_D
4291 UINT64_C(3225452544), // INSERT_MXIPZ_V_H
4292 UINT64_C(3233906688), // INSERT_MXIPZ_V_Q
4293 UINT64_C(3229646848), // INSERT_MXIPZ_V_S
4294 UINT64_C(86259712), // INSR_ZR_B
4295 UINT64_C(98842624), // INSR_ZR_D
4296 UINT64_C(90454016), // INSR_ZR_H
4297 UINT64_C(94648320), // INSR_ZR_S
4298 UINT64_C(87308288), // INSR_ZV_B
4299 UINT64_C(99891200), // INSR_ZV_D
4300 UINT64_C(91502592), // INSR_ZV_H
4301 UINT64_C(95696896), // INSR_ZV_S
4302 UINT64_C(1308761088), // INSvi16gpr
4303 UINT64_C(1845625856), // INSvi16lane
4304 UINT64_C(1308892160), // INSvi32gpr
4305 UINT64_C(1845756928), // INSvi32lane
4306 UINT64_C(1309154304), // INSvi64gpr
4307 UINT64_C(1846019072), // INSvi64lane
4308 UINT64_C(1308695552), // INSvi8gpr
4309 UINT64_C(1845560320), // INSvi8lane
4310 UINT64_C(2596278272), // IRG
4311 UINT64_C(3573756127), // ISB
4312 UINT64_C(86024192), // LASTA_RPZ_B
4313 UINT64_C(98607104), // LASTA_RPZ_D
4314 UINT64_C(90218496), // LASTA_RPZ_H
4315 UINT64_C(94412800), // LASTA_RPZ_S
4316 UINT64_C(86147072), // LASTA_VPZ_B
4317 UINT64_C(98729984), // LASTA_VPZ_D
4318 UINT64_C(90341376), // LASTA_VPZ_H
4319 UINT64_C(94535680), // LASTA_VPZ_S
4320 UINT64_C(86089728), // LASTB_RPZ_B
4321 UINT64_C(98672640), // LASTB_RPZ_D
4322 UINT64_C(90284032), // LASTB_RPZ_H
4323 UINT64_C(94478336), // LASTB_RPZ_S
4324 UINT64_C(86212608), // LASTB_VPZ_B
4325 UINT64_C(98795520), // LASTB_VPZ_D
4326 UINT64_C(90406912), // LASTB_VPZ_H
4327 UINT64_C(94601216), // LASTB_VPZ_S
4328 UINT64_C(623017984), // LASTP_XPP_B
4329 UINT64_C(635600896), // LASTP_XPP_D
4330 UINT64_C(627212288), // LASTP_XPP_H
4331 UINT64_C(631406592), // LASTP_XPP_S
4332 UINT64_C(2751479808), // LD1B
4333 UINT64_C(2684354560), // LD1B_2Z
4334 UINT64_C(2688548864), // LD1B_2Z_IMM
4335 UINT64_C(2701131776), // LD1B_2Z_STRIDED
4336 UINT64_C(2705326080), // LD1B_2Z_STRIDED_IMM
4337 UINT64_C(2684387328), // LD1B_4Z
4338 UINT64_C(2688581632), // LD1B_4Z_IMM
4339 UINT64_C(2701164544), // LD1B_4Z_STRIDED
4340 UINT64_C(2705358848), // LD1B_4Z_STRIDED_IMM
4341 UINT64_C(2757771264), // LD1B_D
4342 UINT64_C(2757795840), // LD1B_D_IMM
4343 UINT64_C(2753576960), // LD1B_H
4344 UINT64_C(2753601536), // LD1B_H_IMM
4345 UINT64_C(2751504384), // LD1B_IMM
4346 UINT64_C(2755674112), // LD1B_S
4347 UINT64_C(2755698688), // LD1B_S_IMM
4348 UINT64_C(2782937088), // LD1D
4349 UINT64_C(2684379136), // LD1D_2Z
4350 UINT64_C(2688573440), // LD1D_2Z_IMM
4351 UINT64_C(2701156352), // LD1D_2Z_STRIDED
4352 UINT64_C(2705350656), // LD1D_2Z_STRIDED_IMM
4353 UINT64_C(2684411904), // LD1D_4Z
4354 UINT64_C(2688606208), // LD1D_4Z_IMM
4355 UINT64_C(2701189120), // LD1D_4Z_STRIDED
4356 UINT64_C(2705383424), // LD1D_4Z_STRIDED_IMM
4357 UINT64_C(2782961664), // LD1D_IMM
4358 UINT64_C(2776662016), // LD1D_Q
4359 UINT64_C(2777686016), // LD1D_Q_IMM
4360 UINT64_C(1279270912), // LD1Fourv16b
4361 UINT64_C(1287659520), // LD1Fourv16b_POST
4362 UINT64_C(205532160), // LD1Fourv1d
4363 UINT64_C(213920768), // LD1Fourv1d_POST
4364 UINT64_C(1279273984), // LD1Fourv2d
4365 UINT64_C(1287662592), // LD1Fourv2d_POST
4366 UINT64_C(205531136), // LD1Fourv2s
4367 UINT64_C(213919744), // LD1Fourv2s_POST
4368 UINT64_C(205530112), // LD1Fourv4h
4369 UINT64_C(213918720), // LD1Fourv4h_POST
4370 UINT64_C(1279272960), // LD1Fourv4s
4371 UINT64_C(1287661568), // LD1Fourv4s_POST
4372 UINT64_C(205529088), // LD1Fourv8b
4373 UINT64_C(213917696), // LD1Fourv8b_POST
4374 UINT64_C(1279271936), // LD1Fourv8h
4375 UINT64_C(1287660544), // LD1Fourv8h_POST
4376 UINT64_C(2761965568), // LD1H
4377 UINT64_C(2684362752), // LD1H_2Z
4378 UINT64_C(2688557056), // LD1H_2Z_IMM
4379 UINT64_C(2701139968), // LD1H_2Z_STRIDED
4380 UINT64_C(2705334272), // LD1H_2Z_STRIDED_IMM
4381 UINT64_C(2684395520), // LD1H_4Z
4382 UINT64_C(2688589824), // LD1H_4Z_IMM
4383 UINT64_C(2701172736), // LD1H_4Z_STRIDED
4384 UINT64_C(2705367040), // LD1H_4Z_STRIDED_IMM
4385 UINT64_C(2766159872), // LD1H_D
4386 UINT64_C(2766184448), // LD1H_D_IMM
4387 UINT64_C(2761990144), // LD1H_IMM
4388 UINT64_C(2764062720), // LD1H_S
4389 UINT64_C(2764087296), // LD1H_S_IMM
4390 UINT64_C(1279291392), // LD1Onev16b
4391 UINT64_C(1287680000), // LD1Onev16b_POST
4392 UINT64_C(205552640), // LD1Onev1d
4393 UINT64_C(213941248), // LD1Onev1d_POST
4394 UINT64_C(1279294464), // LD1Onev2d
4395 UINT64_C(1287683072), // LD1Onev2d_POST
4396 UINT64_C(205551616), // LD1Onev2s
4397 UINT64_C(213940224), // LD1Onev2s_POST
4398 UINT64_C(205550592), // LD1Onev4h
4399 UINT64_C(213939200), // LD1Onev4h_POST
4400 UINT64_C(1279293440), // LD1Onev4s
4401 UINT64_C(1287682048), // LD1Onev4s_POST
4402 UINT64_C(205549568), // LD1Onev8b
4403 UINT64_C(213938176), // LD1Onev8b_POST
4404 UINT64_C(1279292416), // LD1Onev8h
4405 UINT64_C(1287681024), // LD1Onev8h_POST
4406 UINT64_C(2218844160), // LD1RB_D_IMM
4407 UINT64_C(2218827776), // LD1RB_H_IMM
4408 UINT64_C(2218819584), // LD1RB_IMM
4409 UINT64_C(2218835968), // LD1RB_S_IMM
4410 UINT64_C(2244009984), // LD1RD_IMM
4411 UINT64_C(2227232768), // LD1RH_D_IMM
4412 UINT64_C(2227216384), // LD1RH_IMM
4413 UINT64_C(2227224576), // LD1RH_S_IMM
4414 UINT64_C(2753560576), // LD1RO_B
4415 UINT64_C(2753568768), // LD1RO_B_IMM
4416 UINT64_C(2778726400), // LD1RO_D
4417 UINT64_C(2778734592), // LD1RO_D_IMM
4418 UINT64_C(2761949184), // LD1RO_H
4419 UINT64_C(2761957376), // LD1RO_H_IMM
4420 UINT64_C(2770337792), // LD1RO_W
4421 UINT64_C(2770345984), // LD1RO_W_IMM
4422 UINT64_C(2751463424), // LD1RQ_B
4423 UINT64_C(2751471616), // LD1RQ_B_IMM
4424 UINT64_C(2776629248), // LD1RQ_D
4425 UINT64_C(2776637440), // LD1RQ_D_IMM
4426 UINT64_C(2759852032), // LD1RQ_H
4427 UINT64_C(2759860224), // LD1RQ_H_IMM
4428 UINT64_C(2768240640), // LD1RQ_W
4429 UINT64_C(2768248832), // LD1RQ_W_IMM
4430 UINT64_C(2243985408), // LD1RSB_D_IMM
4431 UINT64_C(2244001792), // LD1RSB_H_IMM
4432 UINT64_C(2243993600), // LD1RSB_S_IMM
4433 UINT64_C(2235596800), // LD1RSH_D_IMM
4434 UINT64_C(2235604992), // LD1RSH_S_IMM
4435 UINT64_C(2227208192), // LD1RSW_IMM
4436 UINT64_C(2235621376), // LD1RW_D_IMM
4437 UINT64_C(2235613184), // LD1RW_IMM
4438 UINT64_C(1296089088), // LD1Rv16b
4439 UINT64_C(1304477696), // LD1Rv16b_POST
4440 UINT64_C(222350336), // LD1Rv1d
4441 UINT64_C(230738944), // LD1Rv1d_POST
4442 UINT64_C(1296092160), // LD1Rv2d
4443 UINT64_C(1304480768), // LD1Rv2d_POST
4444 UINT64_C(222349312), // LD1Rv2s
4445 UINT64_C(230737920), // LD1Rv2s_POST
4446 UINT64_C(222348288), // LD1Rv4h
4447 UINT64_C(230736896), // LD1Rv4h_POST
4448 UINT64_C(1296091136), // LD1Rv4s
4449 UINT64_C(1304479744), // LD1Rv4s_POST
4450 UINT64_C(222347264), // LD1Rv8b
4451 UINT64_C(230735872), // LD1Rv8b_POST
4452 UINT64_C(1296090112), // LD1Rv8h
4453 UINT64_C(1304478720), // LD1Rv8h_POST
4454 UINT64_C(2776645632), // LD1SB_D
4455 UINT64_C(2776670208), // LD1SB_D_IMM
4456 UINT64_C(2780839936), // LD1SB_H
4457 UINT64_C(2780864512), // LD1SB_H_IMM
4458 UINT64_C(2778742784), // LD1SB_S
4459 UINT64_C(2778767360), // LD1SB_S_IMM
4460 UINT64_C(2768257024), // LD1SH_D
4461 UINT64_C(2768281600), // LD1SH_D_IMM
4462 UINT64_C(2770354176), // LD1SH_S
4463 UINT64_C(2770378752), // LD1SH_S_IMM
4464 UINT64_C(2759868416), // LD1SW_D
4465 UINT64_C(2759892992), // LD1SW_D_IMM
4466 UINT64_C(1279287296), // LD1Threev16b
4467 UINT64_C(1287675904), // LD1Threev16b_POST
4468 UINT64_C(205548544), // LD1Threev1d
4469 UINT64_C(213937152), // LD1Threev1d_POST
4470 UINT64_C(1279290368), // LD1Threev2d
4471 UINT64_C(1287678976), // LD1Threev2d_POST
4472 UINT64_C(205547520), // LD1Threev2s
4473 UINT64_C(213936128), // LD1Threev2s_POST
4474 UINT64_C(205546496), // LD1Threev4h
4475 UINT64_C(213935104), // LD1Threev4h_POST
4476 UINT64_C(1279289344), // LD1Threev4s
4477 UINT64_C(1287677952), // LD1Threev4s_POST
4478 UINT64_C(205545472), // LD1Threev8b
4479 UINT64_C(213934080), // LD1Threev8b_POST
4480 UINT64_C(1279288320), // LD1Threev8h
4481 UINT64_C(1287676928), // LD1Threev8h_POST
4482 UINT64_C(1279303680), // LD1Twov16b
4483 UINT64_C(1287692288), // LD1Twov16b_POST
4484 UINT64_C(205564928), // LD1Twov1d
4485 UINT64_C(213953536), // LD1Twov1d_POST
4486 UINT64_C(1279306752), // LD1Twov2d
4487 UINT64_C(1287695360), // LD1Twov2d_POST
4488 UINT64_C(205563904), // LD1Twov2s
4489 UINT64_C(213952512), // LD1Twov2s_POST
4490 UINT64_C(205562880), // LD1Twov4h
4491 UINT64_C(213951488), // LD1Twov4h_POST
4492 UINT64_C(1279305728), // LD1Twov4s
4493 UINT64_C(1287694336), // LD1Twov4s_POST
4494 UINT64_C(205561856), // LD1Twov8b
4495 UINT64_C(213950464), // LD1Twov8b_POST
4496 UINT64_C(1279304704), // LD1Twov8h
4497 UINT64_C(1287693312), // LD1Twov8h_POST
4498 UINT64_C(2772451328), // LD1W
4499 UINT64_C(2684370944), // LD1W_2Z
4500 UINT64_C(2688565248), // LD1W_2Z_IMM
4501 UINT64_C(2701148160), // LD1W_2Z_STRIDED
4502 UINT64_C(2705342464), // LD1W_2Z_STRIDED_IMM
4503 UINT64_C(2684403712), // LD1W_4Z
4504 UINT64_C(2688598016), // LD1W_4Z_IMM
4505 UINT64_C(2701180928), // LD1W_4Z_STRIDED
4506 UINT64_C(2705375232), // LD1W_4Z_STRIDED_IMM
4507 UINT64_C(2774548480), // LD1W_D
4508 UINT64_C(2774573056), // LD1W_D_IMM
4509 UINT64_C(2772475904), // LD1W_IMM
4510 UINT64_C(2768273408), // LD1W_Q
4511 UINT64_C(2769297408), // LD1W_Q_IMM
4512 UINT64_C(3758096384), // LD1_MXIPXX_H_B
4513 UINT64_C(3770679296), // LD1_MXIPXX_H_D
4514 UINT64_C(3762290688), // LD1_MXIPXX_H_H
4515 UINT64_C(3787456512), // LD1_MXIPXX_H_Q
4516 UINT64_C(3766484992), // LD1_MXIPXX_H_S
4517 UINT64_C(3758129152), // LD1_MXIPXX_V_B
4518 UINT64_C(3770712064), // LD1_MXIPXX_V_D
4519 UINT64_C(3762323456), // LD1_MXIPXX_V_H
4520 UINT64_C(3787489280), // LD1_MXIPXX_V_Q
4521 UINT64_C(3766517760), // LD1_MXIPXX_V_S
4522 UINT64_C(222314496), // LD1i16
4523 UINT64_C(230703104), // LD1i16_POST
4524 UINT64_C(222330880), // LD1i32
4525 UINT64_C(230719488), // LD1i32_POST
4526 UINT64_C(222331904), // LD1i64
4527 UINT64_C(230720512), // LD1i64_POST
4528 UINT64_C(222298112), // LD1i8
4529 UINT64_C(230686720), // LD1i8_POST
4530 UINT64_C(2753609728), // LD2B
4531 UINT64_C(2753617920), // LD2B_IMM
4532 UINT64_C(2778775552), // LD2D
4533 UINT64_C(2778783744), // LD2D_IMM
4534 UINT64_C(2761998336), // LD2H
4535 UINT64_C(2762006528), // LD2H_IMM
4536 UINT64_C(2761981952), // LD2Q
4537 UINT64_C(2760957952), // LD2Q_IMM
4538 UINT64_C(1298186240), // LD2Rv16b
4539 UINT64_C(1306574848), // LD2Rv16b_POST
4540 UINT64_C(224447488), // LD2Rv1d
4541 UINT64_C(232836096), // LD2Rv1d_POST
4542 UINT64_C(1298189312), // LD2Rv2d
4543 UINT64_C(1306577920), // LD2Rv2d_POST
4544 UINT64_C(224446464), // LD2Rv2s
4545 UINT64_C(232835072), // LD2Rv2s_POST
4546 UINT64_C(224445440), // LD2Rv4h
4547 UINT64_C(232834048), // LD2Rv4h_POST
4548 UINT64_C(1298188288), // LD2Rv4s
4549 UINT64_C(1306576896), // LD2Rv4s_POST
4550 UINT64_C(224444416), // LD2Rv8b
4551 UINT64_C(232833024), // LD2Rv8b_POST
4552 UINT64_C(1298187264), // LD2Rv8h
4553 UINT64_C(1306575872), // LD2Rv8h_POST
4554 UINT64_C(1279295488), // LD2Twov16b
4555 UINT64_C(1287684096), // LD2Twov16b_POST
4556 UINT64_C(1279298560), // LD2Twov2d
4557 UINT64_C(1287687168), // LD2Twov2d_POST
4558 UINT64_C(205555712), // LD2Twov2s
4559 UINT64_C(213944320), // LD2Twov2s_POST
4560 UINT64_C(205554688), // LD2Twov4h
4561 UINT64_C(213943296), // LD2Twov4h_POST
4562 UINT64_C(1279297536), // LD2Twov4s
4563 UINT64_C(1287686144), // LD2Twov4s_POST
4564 UINT64_C(205553664), // LD2Twov8b
4565 UINT64_C(213942272), // LD2Twov8b_POST
4566 UINT64_C(1279296512), // LD2Twov8h
4567 UINT64_C(1287685120), // LD2Twov8h_POST
4568 UINT64_C(2770386944), // LD2W
4569 UINT64_C(2770395136), // LD2W_IMM
4570 UINT64_C(224411648), // LD2i16
4571 UINT64_C(232800256), // LD2i16_POST
4572 UINT64_C(224428032), // LD2i32
4573 UINT64_C(232816640), // LD2i32_POST
4574 UINT64_C(224429056), // LD2i64
4575 UINT64_C(232817664), // LD2i64_POST
4576 UINT64_C(224395264), // LD2i8
4577 UINT64_C(232783872), // LD2i8_POST
4578 UINT64_C(2755706880), // LD3B
4579 UINT64_C(2755715072), // LD3B_IMM
4580 UINT64_C(2780872704), // LD3D
4581 UINT64_C(2780880896), // LD3D_IMM
4582 UINT64_C(2764095488), // LD3H
4583 UINT64_C(2764103680), // LD3H_IMM
4584 UINT64_C(2770370560), // LD3Q
4585 UINT64_C(2769346560), // LD3Q_IMM
4586 UINT64_C(1296097280), // LD3Rv16b
4587 UINT64_C(1304485888), // LD3Rv16b_POST
4588 UINT64_C(222358528), // LD3Rv1d
4589 UINT64_C(230747136), // LD3Rv1d_POST
4590 UINT64_C(1296100352), // LD3Rv2d
4591 UINT64_C(1304488960), // LD3Rv2d_POST
4592 UINT64_C(222357504), // LD3Rv2s
4593 UINT64_C(230746112), // LD3Rv2s_POST
4594 UINT64_C(222356480), // LD3Rv4h
4595 UINT64_C(230745088), // LD3Rv4h_POST
4596 UINT64_C(1296099328), // LD3Rv4s
4597 UINT64_C(1304487936), // LD3Rv4s_POST
4598 UINT64_C(222355456), // LD3Rv8b
4599 UINT64_C(230744064), // LD3Rv8b_POST
4600 UINT64_C(1296098304), // LD3Rv8h
4601 UINT64_C(1304486912), // LD3Rv8h_POST
4602 UINT64_C(1279279104), // LD3Threev16b
4603 UINT64_C(1287667712), // LD3Threev16b_POST
4604 UINT64_C(1279282176), // LD3Threev2d
4605 UINT64_C(1287670784), // LD3Threev2d_POST
4606 UINT64_C(205539328), // LD3Threev2s
4607 UINT64_C(213927936), // LD3Threev2s_POST
4608 UINT64_C(205538304), // LD3Threev4h
4609 UINT64_C(213926912), // LD3Threev4h_POST
4610 UINT64_C(1279281152), // LD3Threev4s
4611 UINT64_C(1287669760), // LD3Threev4s_POST
4612 UINT64_C(205537280), // LD3Threev8b
4613 UINT64_C(213925888), // LD3Threev8b_POST
4614 UINT64_C(1279280128), // LD3Threev8h
4615 UINT64_C(1287668736), // LD3Threev8h_POST
4616 UINT64_C(2772484096), // LD3W
4617 UINT64_C(2772492288), // LD3W_IMM
4618 UINT64_C(222322688), // LD3i16
4619 UINT64_C(230711296), // LD3i16_POST
4620 UINT64_C(222339072), // LD3i32
4621 UINT64_C(230727680), // LD3i32_POST
4622 UINT64_C(222340096), // LD3i64
4623 UINT64_C(230728704), // LD3i64_POST
4624 UINT64_C(222306304), // LD3i8
4625 UINT64_C(230694912), // LD3i8_POST
4626 UINT64_C(2757804032), // LD4B
4627 UINT64_C(2757812224), // LD4B_IMM
4628 UINT64_C(2782969856), // LD4D
4629 UINT64_C(2782978048), // LD4D_IMM
4630 UINT64_C(1279262720), // LD4Fourv16b
4631 UINT64_C(1287651328), // LD4Fourv16b_POST
4632 UINT64_C(1279265792), // LD4Fourv2d
4633 UINT64_C(1287654400), // LD4Fourv2d_POST
4634 UINT64_C(205522944), // LD4Fourv2s
4635 UINT64_C(213911552), // LD4Fourv2s_POST
4636 UINT64_C(205521920), // LD4Fourv4h
4637 UINT64_C(213910528), // LD4Fourv4h_POST
4638 UINT64_C(1279264768), // LD4Fourv4s
4639 UINT64_C(1287653376), // LD4Fourv4s_POST
4640 UINT64_C(205520896), // LD4Fourv8b
4641 UINT64_C(213909504), // LD4Fourv8b_POST
4642 UINT64_C(1279263744), // LD4Fourv8h
4643 UINT64_C(1287652352), // LD4Fourv8h_POST
4644 UINT64_C(2766192640), // LD4H
4645 UINT64_C(2766200832), // LD4H_IMM
4646 UINT64_C(2778759168), // LD4Q
4647 UINT64_C(2777735168), // LD4Q_IMM
4648 UINT64_C(1298194432), // LD4Rv16b
4649 UINT64_C(1306583040), // LD4Rv16b_POST
4650 UINT64_C(224455680), // LD4Rv1d
4651 UINT64_C(232844288), // LD4Rv1d_POST
4652 UINT64_C(1298197504), // LD4Rv2d
4653 UINT64_C(1306586112), // LD4Rv2d_POST
4654 UINT64_C(224454656), // LD4Rv2s
4655 UINT64_C(232843264), // LD4Rv2s_POST
4656 UINT64_C(224453632), // LD4Rv4h
4657 UINT64_C(232842240), // LD4Rv4h_POST
4658 UINT64_C(1298196480), // LD4Rv4s
4659 UINT64_C(1306585088), // LD4Rv4s_POST
4660 UINT64_C(224452608), // LD4Rv8b
4661 UINT64_C(232841216), // LD4Rv8b_POST
4662 UINT64_C(1298195456), // LD4Rv8h
4663 UINT64_C(1306584064), // LD4Rv8h_POST
4664 UINT64_C(2774581248), // LD4W
4665 UINT64_C(2774589440), // LD4W_IMM
4666 UINT64_C(224419840), // LD4i16
4667 UINT64_C(232808448), // LD4i16_POST
4668 UINT64_C(224436224), // LD4i32
4669 UINT64_C(232824832), // LD4i32_POST
4670 UINT64_C(224437248), // LD4i64
4671 UINT64_C(232825856), // LD4i64_POST
4672 UINT64_C(224403456), // LD4i8
4673 UINT64_C(232792064), // LD4i8_POST
4674 UINT64_C(4164931584), // LD64B
4675 UINT64_C(950009856), // LDADDAB
4676 UINT64_C(2023751680), // LDADDAH
4677 UINT64_C(954204160), // LDADDALB
4678 UINT64_C(2027945984), // LDADDALH
4679 UINT64_C(3101687808), // LDADDALW
4680 UINT64_C(4175429632), // LDADDALX
4681 UINT64_C(3097493504), // LDADDAW
4682 UINT64_C(4171235328), // LDADDAX
4683 UINT64_C(941621248), // LDADDB
4684 UINT64_C(2015363072), // LDADDH
4685 UINT64_C(945815552), // LDADDLB
4686 UINT64_C(2019557376), // LDADDLH
4687 UINT64_C(3093299200), // LDADDLW
4688 UINT64_C(4167041024), // LDADDLX
4689 UINT64_C(3089104896), // LDADDW
4690 UINT64_C(4162846720), // LDADDX
4691 UINT64_C(222397440), // LDAP1
4692 UINT64_C(952090624), // LDAPRB
4693 UINT64_C(2025832448), // LDAPRH
4694 UINT64_C(3099574272), // LDAPRW
4695 UINT64_C(2579499008), // LDAPRWpost
4696 UINT64_C(4173316096), // LDAPRX
4697 UINT64_C(3653240832), // LDAPRXpost
4698 UINT64_C(423624704), // LDAPURBi
4699 UINT64_C(1497366528), // LDAPURHi
4700 UINT64_C(432013312), // LDAPURSBWi
4701 UINT64_C(427819008), // LDAPURSBXi
4702 UINT64_C(1505755136), // LDAPURSHWi
4703 UINT64_C(1501560832), // LDAPURSHXi
4704 UINT64_C(2575302656), // LDAPURSWi
4705 UINT64_C(3644850176), // LDAPURXi
4706 UINT64_C(490735616), // LDAPURbi
4707 UINT64_C(3711961088), // LDAPURdi
4708 UINT64_C(1564477440), // LDAPURhi
4709 UINT64_C(2571108352), // LDAPURi
4710 UINT64_C(499124224), // LDAPURqi
4711 UINT64_C(2638219264), // LDAPURsi
4712 UINT64_C(148896768), // LDARB
4713 UINT64_C(1222638592), // LDARH
4714 UINT64_C(2296380416), // LDARW
4715 UINT64_C(3370122240), // LDARX
4716 UINT64_C(2304769024), // LDATXRW
4717 UINT64_C(3378510848), // LDATXRX
4718 UINT64_C(2290057216), // LDAXPW
4719 UINT64_C(3363799040), // LDAXPX
4720 UINT64_C(140508160), // LDAXRB
4721 UINT64_C(1214249984), // LDAXRH
4722 UINT64_C(2287991808), // LDAXRW
4723 UINT64_C(3361733632), // LDAXRX
4724 UINT64_C(1008730112), // LDBFADD
4725 UINT64_C(1017118720), // LDBFADDA
4726 UINT64_C(1021313024), // LDBFADDAL
4727 UINT64_C(1012924416), // LDBFADDL
4728 UINT64_C(1008746496), // LDBFMAX
4729 UINT64_C(1017135104), // LDBFMAXA
4730 UINT64_C(1021329408), // LDBFMAXAL
4731 UINT64_C(1012940800), // LDBFMAXL
4732 UINT64_C(1008754688), // LDBFMAXNM
4733 UINT64_C(1017143296), // LDBFMAXNMA
4734 UINT64_C(1021337600), // LDBFMAXNMAL
4735 UINT64_C(1012948992), // LDBFMAXNML
4736 UINT64_C(1008750592), // LDBFMIN
4737 UINT64_C(1017139200), // LDBFMINA
4738 UINT64_C(1021333504), // LDBFMINAL
4739 UINT64_C(1012944896), // LDBFMINL
4740 UINT64_C(1008758784), // LDBFMINNM
4741 UINT64_C(1017147392), // LDBFMINNMA
4742 UINT64_C(1021341696), // LDBFMINNMAL
4743 UINT64_C(1012953088), // LDBFMINNML
4744 UINT64_C(950013952), // LDCLRAB
4745 UINT64_C(2023755776), // LDCLRAH
4746 UINT64_C(954208256), // LDCLRALB
4747 UINT64_C(2027950080), // LDCLRALH
4748 UINT64_C(3101691904), // LDCLRALW
4749 UINT64_C(4175433728), // LDCLRALX
4750 UINT64_C(3097497600), // LDCLRAW
4751 UINT64_C(4171239424), // LDCLRAX
4752 UINT64_C(941625344), // LDCLRB
4753 UINT64_C(2015367168), // LDCLRH
4754 UINT64_C(945819648), // LDCLRLB
4755 UINT64_C(2019561472), // LDCLRLH
4756 UINT64_C(3093303296), // LDCLRLW
4757 UINT64_C(4167045120), // LDCLRLX
4758 UINT64_C(421531648), // LDCLRP
4759 UINT64_C(429920256), // LDCLRPA
4760 UINT64_C(434114560), // LDCLRPAL
4761 UINT64_C(425725952), // LDCLRPL
4762 UINT64_C(3089108992), // LDCLRW
4763 UINT64_C(4162850816), // LDCLRX
4764 UINT64_C(950018048), // LDEORAB
4765 UINT64_C(2023759872), // LDEORAH
4766 UINT64_C(954212352), // LDEORALB
4767 UINT64_C(2027954176), // LDEORALH
4768 UINT64_C(3101696000), // LDEORALW
4769 UINT64_C(4175437824), // LDEORALX
4770 UINT64_C(3097501696), // LDEORAW
4771 UINT64_C(4171243520), // LDEORAX
4772 UINT64_C(941629440), // LDEORB
4773 UINT64_C(2015371264), // LDEORH
4774 UINT64_C(945823744), // LDEORLB
4775 UINT64_C(2019565568), // LDEORLH
4776 UINT64_C(3093307392), // LDEORLW
4777 UINT64_C(4167049216), // LDEORLX
4778 UINT64_C(3089113088), // LDEORW
4779 UINT64_C(4162854912), // LDEORX
4780 UINT64_C(4238344192), // LDFADDAD
4781 UINT64_C(2090860544), // LDFADDAH
4782 UINT64_C(4242538496), // LDFADDALD
4783 UINT64_C(2095054848), // LDFADDALH
4784 UINT64_C(3168796672), // LDFADDALS
4785 UINT64_C(3164602368), // LDFADDAS
4786 UINT64_C(4229955584), // LDFADDD
4787 UINT64_C(2082471936), // LDFADDH
4788 UINT64_C(4234149888), // LDFADDLD
4789 UINT64_C(2086666240), // LDFADDLH
4790 UINT64_C(3160408064), // LDFADDLS
4791 UINT64_C(3156213760), // LDFADDS
4792 UINT64_C(2751488000), // LDFF1B
4793 UINT64_C(2757779456), // LDFF1B_D
4794 UINT64_C(2753585152), // LDFF1B_H
4795 UINT64_C(2755682304), // LDFF1B_S
4796 UINT64_C(2782945280), // LDFF1D
4797 UINT64_C(2761973760), // LDFF1H
4798 UINT64_C(2766168064), // LDFF1H_D
4799 UINT64_C(2764070912), // LDFF1H_S
4800 UINT64_C(2776653824), // LDFF1SB_D
4801 UINT64_C(2780848128), // LDFF1SB_H
4802 UINT64_C(2778750976), // LDFF1SB_S
4803 UINT64_C(2768265216), // LDFF1SH_D
4804 UINT64_C(2770362368), // LDFF1SH_S
4805 UINT64_C(2759876608), // LDFF1SW_D
4806 UINT64_C(2772459520), // LDFF1W
4807 UINT64_C(2774556672), // LDFF1W_D
4808 UINT64_C(4238360576), // LDFMAXAD
4809 UINT64_C(2090876928), // LDFMAXAH
4810 UINT64_C(4242554880), // LDFMAXALD
4811 UINT64_C(2095071232), // LDFMAXALH
4812 UINT64_C(3168813056), // LDFMAXALS
4813 UINT64_C(3164618752), // LDFMAXAS
4814 UINT64_C(4229971968), // LDFMAXD
4815 UINT64_C(2082488320), // LDFMAXH
4816 UINT64_C(4234166272), // LDFMAXLD
4817 UINT64_C(2086682624), // LDFMAXLH
4818 UINT64_C(3160424448), // LDFMAXLS
4819 UINT64_C(4238368768), // LDFMAXNMAD
4820 UINT64_C(2090885120), // LDFMAXNMAH
4821 UINT64_C(4242563072), // LDFMAXNMALD
4822 UINT64_C(2095079424), // LDFMAXNMALH
4823 UINT64_C(3168821248), // LDFMAXNMALS
4824 UINT64_C(3164626944), // LDFMAXNMAS
4825 UINT64_C(4229980160), // LDFMAXNMD
4826 UINT64_C(2082496512), // LDFMAXNMH
4827 UINT64_C(4234174464), // LDFMAXNMLD
4828 UINT64_C(2086690816), // LDFMAXNMLH
4829 UINT64_C(3160432640), // LDFMAXNMLS
4830 UINT64_C(3156238336), // LDFMAXNMS
4831 UINT64_C(3156230144), // LDFMAXS
4832 UINT64_C(4238364672), // LDFMINAD
4833 UINT64_C(2090881024), // LDFMINAH
4834 UINT64_C(4242558976), // LDFMINALD
4835 UINT64_C(2095075328), // LDFMINALH
4836 UINT64_C(3168817152), // LDFMINALS
4837 UINT64_C(3164622848), // LDFMINAS
4838 UINT64_C(4229976064), // LDFMIND
4839 UINT64_C(2082492416), // LDFMINH
4840 UINT64_C(4234170368), // LDFMINLD
4841 UINT64_C(2086686720), // LDFMINLH
4842 UINT64_C(3160428544), // LDFMINLS
4843 UINT64_C(4238372864), // LDFMINNMAD
4844 UINT64_C(2090889216), // LDFMINNMAH
4845 UINT64_C(4242567168), // LDFMINNMALD
4846 UINT64_C(2095083520), // LDFMINNMALH
4847 UINT64_C(3168825344), // LDFMINNMALS
4848 UINT64_C(3164631040), // LDFMINNMAS
4849 UINT64_C(4229984256), // LDFMINNMD
4850 UINT64_C(2082500608), // LDFMINNMH
4851 UINT64_C(4234178560), // LDFMINNMLD
4852 UINT64_C(2086694912), // LDFMINNMLH
4853 UINT64_C(3160436736), // LDFMINNMLS
4854 UINT64_C(3156242432), // LDFMINNMS
4855 UINT64_C(3156234240), // LDFMINS
4856 UINT64_C(3646947328), // LDG
4857 UINT64_C(3655335936), // LDGM
4858 UINT64_C(2571114496), // LDIAPPW
4859 UINT64_C(2571110400), // LDIAPPWpost
4860 UINT64_C(3644856320), // LDIAPPX
4861 UINT64_C(3644852224), // LDIAPPXpost
4862 UINT64_C(148864000), // LDLARB
4863 UINT64_C(1222605824), // LDLARH
4864 UINT64_C(2296347648), // LDLARW
4865 UINT64_C(3370089472), // LDLARX
4866 UINT64_C(2758844416), // LDNF1B_D_IMM
4867 UINT64_C(2754650112), // LDNF1B_H_IMM
4868 UINT64_C(2752552960), // LDNF1B_IMM
4869 UINT64_C(2756747264), // LDNF1B_S_IMM
4870 UINT64_C(2784010240), // LDNF1D_IMM
4871 UINT64_C(2767233024), // LDNF1H_D_IMM
4872 UINT64_C(2763038720), // LDNF1H_IMM
4873 UINT64_C(2765135872), // LDNF1H_S_IMM
4874 UINT64_C(2777718784), // LDNF1SB_D_IMM
4875 UINT64_C(2781913088), // LDNF1SB_H_IMM
4876 UINT64_C(2779815936), // LDNF1SB_S_IMM
4877 UINT64_C(2769330176), // LDNF1SH_D_IMM
4878 UINT64_C(2771427328), // LDNF1SH_S_IMM
4879 UINT64_C(2760941568), // LDNF1SW_D_IMM
4880 UINT64_C(2775621632), // LDNF1W_D_IMM
4881 UINT64_C(2773524480), // LDNF1W_IMM
4882 UINT64_C(1816133632), // LDNPDi
4883 UINT64_C(2889875456), // LDNPQi
4884 UINT64_C(742391808), // LDNPSi
4885 UINT64_C(675282944), // LDNPWi
4886 UINT64_C(2822766592), // LDNPXi
4887 UINT64_C(2684354561), // LDNT1B_2Z
4888 UINT64_C(2688548865), // LDNT1B_2Z_IMM
4889 UINT64_C(2701131784), // LDNT1B_2Z_STRIDED
4890 UINT64_C(2705326088), // LDNT1B_2Z_STRIDED_IMM
4891 UINT64_C(2684387329), // LDNT1B_4Z
4892 UINT64_C(2688581633), // LDNT1B_4Z_IMM
4893 UINT64_C(2701164552), // LDNT1B_4Z_STRIDED
4894 UINT64_C(2705358856), // LDNT1B_4Z_STRIDED_IMM
4895 UINT64_C(2751520768), // LDNT1B_ZRI
4896 UINT64_C(2751512576), // LDNT1B_ZRR
4897 UINT64_C(3288383488), // LDNT1B_ZZR_D
4898 UINT64_C(2214633472), // LDNT1B_ZZR_S
4899 UINT64_C(2684379137), // LDNT1D_2Z
4900 UINT64_C(2688573441), // LDNT1D_2Z_IMM
4901 UINT64_C(2701156360), // LDNT1D_2Z_STRIDED
4902 UINT64_C(2705350664), // LDNT1D_2Z_STRIDED_IMM
4903 UINT64_C(2684411905), // LDNT1D_4Z
4904 UINT64_C(2688606209), // LDNT1D_4Z_IMM
4905 UINT64_C(2701189128), // LDNT1D_4Z_STRIDED
4906 UINT64_C(2705383432), // LDNT1D_4Z_STRIDED_IMM
4907 UINT64_C(2776686592), // LDNT1D_ZRI
4908 UINT64_C(2776678400), // LDNT1D_ZRR
4909 UINT64_C(3313549312), // LDNT1D_ZZR_D
4910 UINT64_C(2684362753), // LDNT1H_2Z
4911 UINT64_C(2688557057), // LDNT1H_2Z_IMM
4912 UINT64_C(2701139976), // LDNT1H_2Z_STRIDED
4913 UINT64_C(2705334280), // LDNT1H_2Z_STRIDED_IMM
4914 UINT64_C(2684395521), // LDNT1H_4Z
4915 UINT64_C(2688589825), // LDNT1H_4Z_IMM
4916 UINT64_C(2701172744), // LDNT1H_4Z_STRIDED
4917 UINT64_C(2705367048), // LDNT1H_4Z_STRIDED_IMM
4918 UINT64_C(2759909376), // LDNT1H_ZRI
4919 UINT64_C(2759901184), // LDNT1H_ZRR
4920 UINT64_C(3296772096), // LDNT1H_ZZR_D
4921 UINT64_C(2223022080), // LDNT1H_ZZR_S
4922 UINT64_C(3288367104), // LDNT1SB_ZZR_D
4923 UINT64_C(2214625280), // LDNT1SB_ZZR_S
4924 UINT64_C(3296755712), // LDNT1SH_ZZR_D
4925 UINT64_C(2223013888), // LDNT1SH_ZZR_S
4926 UINT64_C(3305144320), // LDNT1SW_ZZR_D
4927 UINT64_C(2684370945), // LDNT1W_2Z
4928 UINT64_C(2688565249), // LDNT1W_2Z_IMM
4929 UINT64_C(2701148168), // LDNT1W_2Z_STRIDED
4930 UINT64_C(2705342472), // LDNT1W_2Z_STRIDED_IMM
4931 UINT64_C(2684403713), // LDNT1W_4Z
4932 UINT64_C(2688598017), // LDNT1W_4Z_IMM
4933 UINT64_C(2701180936), // LDNT1W_4Z_STRIDED
4934 UINT64_C(2705375240), // LDNT1W_4Z_STRIDED_IMM
4935 UINT64_C(2768297984), // LDNT1W_ZRI
4936 UINT64_C(2768289792), // LDNT1W_ZRR
4937 UINT64_C(3305160704), // LDNT1W_ZZR_D
4938 UINT64_C(2231410688), // LDNT1W_ZZR_S
4939 UINT64_C(1832910848), // LDPDi
4940 UINT64_C(1824522240), // LDPDpost
4941 UINT64_C(1841299456), // LDPDpre
4942 UINT64_C(2906652672), // LDPQi
4943 UINT64_C(2898264064), // LDPQpost
4944 UINT64_C(2915041280), // LDPQpre
4945 UINT64_C(1765801984), // LDPSWi
4946 UINT64_C(1757413376), // LDPSWpost
4947 UINT64_C(1774190592), // LDPSWpre
4948 UINT64_C(759169024), // LDPSi
4949 UINT64_C(750780416), // LDPSpost
4950 UINT64_C(767557632), // LDPSpre
4951 UINT64_C(692060160), // LDPWi
4952 UINT64_C(683671552), // LDPWpost
4953 UINT64_C(700448768), // LDPWpre
4954 UINT64_C(2839543808), // LDPXi
4955 UINT64_C(2831155200), // LDPXpost
4956 UINT64_C(2847932416), // LDPXpre
4957 UINT64_C(4162847744), // LDRAAindexed
4958 UINT64_C(4162849792), // LDRAAwriteback
4959 UINT64_C(4171236352), // LDRABindexed
4960 UINT64_C(4171238400), // LDRABwriteback
4961 UINT64_C(943719424), // LDRBBpost
4962 UINT64_C(943721472), // LDRBBpre
4963 UINT64_C(945833984), // LDRBBroW
4964 UINT64_C(945842176), // LDRBBroX
4965 UINT64_C(960495616), // LDRBBui
4966 UINT64_C(1010828288), // LDRBpost
4967 UINT64_C(1010830336), // LDRBpre
4968 UINT64_C(1012942848), // LDRBroW
4969 UINT64_C(1012951040), // LDRBroX
4970 UINT64_C(1027604480), // LDRBui
4971 UINT64_C(1543503872), // LDRDl
4972 UINT64_C(4232053760), // LDRDpost
4973 UINT64_C(4232055808), // LDRDpre
4974 UINT64_C(4234168320), // LDRDroW
4975 UINT64_C(4234176512), // LDRDroX
4976 UINT64_C(4248829952), // LDRDui
4977 UINT64_C(2017461248), // LDRHHpost
4978 UINT64_C(2017463296), // LDRHHpre
4979 UINT64_C(2019575808), // LDRHHroW
4980 UINT64_C(2019584000), // LDRHHroX
4981 UINT64_C(2034237440), // LDRHHui
4982 UINT64_C(2084570112), // LDRHpost
4983 UINT64_C(2084572160), // LDRHpre
4984 UINT64_C(2086684672), // LDRHroW
4985 UINT64_C(2086692864), // LDRHroX
4986 UINT64_C(2101346304), // LDRHui
4987 UINT64_C(2617245696), // LDRQl
4988 UINT64_C(1019216896), // LDRQpost
4989 UINT64_C(1019218944), // LDRQpre
4990 UINT64_C(1021331456), // LDRQroW
4991 UINT64_C(1021339648), // LDRQroX
4992 UINT64_C(1035993088), // LDRQui
4993 UINT64_C(952108032), // LDRSBWpost
4994 UINT64_C(952110080), // LDRSBWpre
4995 UINT64_C(954222592), // LDRSBWroW
4996 UINT64_C(954230784), // LDRSBWroX
4997 UINT64_C(968884224), // LDRSBWui
4998 UINT64_C(947913728), // LDRSBXpost
4999 UINT64_C(947915776), // LDRSBXpre
5000 UINT64_C(950028288), // LDRSBXroW
5001 UINT64_C(950036480), // LDRSBXroX
5002 UINT64_C(964689920), // LDRSBXui
5003 UINT64_C(2025849856), // LDRSHWpost
5004 UINT64_C(2025851904), // LDRSHWpre
5005 UINT64_C(2027964416), // LDRSHWroW
5006 UINT64_C(2027972608), // LDRSHWroX
5007 UINT64_C(2042626048), // LDRSHWui
5008 UINT64_C(2021655552), // LDRSHXpost
5009 UINT64_C(2021657600), // LDRSHXpre
5010 UINT64_C(2023770112), // LDRSHXroW
5011 UINT64_C(2023778304), // LDRSHXroX
5012 UINT64_C(2038431744), // LDRSHXui
5013 UINT64_C(2550136832), // LDRSWl
5014 UINT64_C(3095397376), // LDRSWpost
5015 UINT64_C(3095399424), // LDRSWpre
5016 UINT64_C(3097511936), // LDRSWroW
5017 UINT64_C(3097520128), // LDRSWroX
5018 UINT64_C(3112173568), // LDRSWui
5019 UINT64_C(469762048), // LDRSl
5020 UINT64_C(3158311936), // LDRSpost
5021 UINT64_C(3158313984), // LDRSpre
5022 UINT64_C(3160426496), // LDRSroW
5023 UINT64_C(3160434688), // LDRSroX
5024 UINT64_C(3175088128), // LDRSui
5025 UINT64_C(402653184), // LDRWl
5026 UINT64_C(3091203072), // LDRWpost
5027 UINT64_C(3091205120), // LDRWpre
5028 UINT64_C(3093317632), // LDRWroW
5029 UINT64_C(3093325824), // LDRWroX
5030 UINT64_C(3107979264), // LDRWui
5031 UINT64_C(1476395008), // LDRXl
5032 UINT64_C(4164944896), // LDRXpost
5033 UINT64_C(4164946944), // LDRXpre
5034 UINT64_C(4167059456), // LDRXroW
5035 UINT64_C(4167067648), // LDRXroX
5036 UINT64_C(4181721088), // LDRXui
5037 UINT64_C(2239758336), // LDR_PXI
5038 UINT64_C(3776937984), // LDR_TX
5039 UINT64_C(3774873600), // LDR_ZA
5040 UINT64_C(2239774720), // LDR_ZXI
5041 UINT64_C(950022144), // LDSETAB
5042 UINT64_C(2023763968), // LDSETAH
5043 UINT64_C(954216448), // LDSETALB
5044 UINT64_C(2027958272), // LDSETALH
5045 UINT64_C(3101700096), // LDSETALW
5046 UINT64_C(4175441920), // LDSETALX
5047 UINT64_C(3097505792), // LDSETAW
5048 UINT64_C(4171247616), // LDSETAX
5049 UINT64_C(941633536), // LDSETB
5050 UINT64_C(2015375360), // LDSETH
5051 UINT64_C(945827840), // LDSETLB
5052 UINT64_C(2019569664), // LDSETLH
5053 UINT64_C(3093311488), // LDSETLW
5054 UINT64_C(4167053312), // LDSETLX
5055 UINT64_C(421539840), // LDSETP
5056 UINT64_C(429928448), // LDSETPA
5057 UINT64_C(434122752), // LDSETPAL
5058 UINT64_C(425734144), // LDSETPL
5059 UINT64_C(3089117184), // LDSETW
5060 UINT64_C(4162859008), // LDSETX
5061 UINT64_C(950026240), // LDSMAXAB
5062 UINT64_C(2023768064), // LDSMAXAH
5063 UINT64_C(954220544), // LDSMAXALB
5064 UINT64_C(2027962368), // LDSMAXALH
5065 UINT64_C(3101704192), // LDSMAXALW
5066 UINT64_C(4175446016), // LDSMAXALX
5067 UINT64_C(3097509888), // LDSMAXAW
5068 UINT64_C(4171251712), // LDSMAXAX
5069 UINT64_C(941637632), // LDSMAXB
5070 UINT64_C(2015379456), // LDSMAXH
5071 UINT64_C(945831936), // LDSMAXLB
5072 UINT64_C(2019573760), // LDSMAXLH
5073 UINT64_C(3093315584), // LDSMAXLW
5074 UINT64_C(4167057408), // LDSMAXLX
5075 UINT64_C(3089121280), // LDSMAXW
5076 UINT64_C(4162863104), // LDSMAXX
5077 UINT64_C(950030336), // LDSMINAB
5078 UINT64_C(2023772160), // LDSMINAH
5079 UINT64_C(954224640), // LDSMINALB
5080 UINT64_C(2027966464), // LDSMINALH
5081 UINT64_C(3101708288), // LDSMINALW
5082 UINT64_C(4175450112), // LDSMINALX
5083 UINT64_C(3097513984), // LDSMINAW
5084 UINT64_C(4171255808), // LDSMINAX
5085 UINT64_C(941641728), // LDSMINB
5086 UINT64_C(2015383552), // LDSMINH
5087 UINT64_C(945836032), // LDSMINLB
5088 UINT64_C(2019577856), // LDSMINLH
5089 UINT64_C(3093319680), // LDSMINLW
5090 UINT64_C(4167061504), // LDSMINLX
5091 UINT64_C(3089125376), // LDSMINW
5092 UINT64_C(4162867200), // LDSMINX
5093 UINT64_C(434111488), // LDTADDALW
5094 UINT64_C(1507853312), // LDTADDALX
5095 UINT64_C(429917184), // LDTADDAW
5096 UINT64_C(1503659008), // LDTADDAX
5097 UINT64_C(425722880), // LDTADDLW
5098 UINT64_C(1499464704), // LDTADDLX
5099 UINT64_C(421528576), // LDTADDW
5100 UINT64_C(1495270400), // LDTADDX
5101 UINT64_C(434115584), // LDTCLRALW
5102 UINT64_C(1507857408), // LDTCLRALX
5103 UINT64_C(429921280), // LDTCLRAW
5104 UINT64_C(1503663104), // LDTCLRAX
5105 UINT64_C(425726976), // LDTCLRLW
5106 UINT64_C(1499468800), // LDTCLRLX
5107 UINT64_C(421532672), // LDTCLRW
5108 UINT64_C(1495274496), // LDTCLRX
5109 UINT64_C(3963617280), // LDTNPQi
5110 UINT64_C(3896508416), // LDTNPXi
5111 UINT64_C(3980394496), // LDTPQi
5112 UINT64_C(3972005888), // LDTPQpost
5113 UINT64_C(3988783104), // LDTPQpre
5114 UINT64_C(3913285632), // LDTPi
5115 UINT64_C(3904897024), // LDTPpost
5116 UINT64_C(3921674240), // LDTPpre
5117 UINT64_C(943720448), // LDTRBi
5118 UINT64_C(2017462272), // LDTRHi
5119 UINT64_C(952109056), // LDTRSBWi
5120 UINT64_C(947914752), // LDTRSBXi
5121 UINT64_C(2025850880), // LDTRSHWi
5122 UINT64_C(2021656576), // LDTRSHXi
5123 UINT64_C(3095398400), // LDTRSWi
5124 UINT64_C(3091204096), // LDTRWi
5125 UINT64_C(4164945920), // LDTRXi
5126 UINT64_C(434123776), // LDTSETALW
5127 UINT64_C(1507865600), // LDTSETALX
5128 UINT64_C(429929472), // LDTSETAW
5129 UINT64_C(1503671296), // LDTSETAX
5130 UINT64_C(425735168), // LDTSETLW
5131 UINT64_C(1499476992), // LDTSETLX
5132 UINT64_C(421540864), // LDTSETW
5133 UINT64_C(1495282688), // LDTSETX
5134 UINT64_C(2304736256), // LDTXRWr
5135 UINT64_C(3378478080), // LDTXRXr
5136 UINT64_C(950034432), // LDUMAXAB
5137 UINT64_C(2023776256), // LDUMAXAH
5138 UINT64_C(954228736), // LDUMAXALB
5139 UINT64_C(2027970560), // LDUMAXALH
5140 UINT64_C(3101712384), // LDUMAXALW
5141 UINT64_C(4175454208), // LDUMAXALX
5142 UINT64_C(3097518080), // LDUMAXAW
5143 UINT64_C(4171259904), // LDUMAXAX
5144 UINT64_C(941645824), // LDUMAXB
5145 UINT64_C(2015387648), // LDUMAXH
5146 UINT64_C(945840128), // LDUMAXLB
5147 UINT64_C(2019581952), // LDUMAXLH
5148 UINT64_C(3093323776), // LDUMAXLW
5149 UINT64_C(4167065600), // LDUMAXLX
5150 UINT64_C(3089129472), // LDUMAXW
5151 UINT64_C(4162871296), // LDUMAXX
5152 UINT64_C(950038528), // LDUMINAB
5153 UINT64_C(2023780352), // LDUMINAH
5154 UINT64_C(954232832), // LDUMINALB
5155 UINT64_C(2027974656), // LDUMINALH
5156 UINT64_C(3101716480), // LDUMINALW
5157 UINT64_C(4175458304), // LDUMINALX
5158 UINT64_C(3097522176), // LDUMINAW
5159 UINT64_C(4171264000), // LDUMINAX
5160 UINT64_C(941649920), // LDUMINB
5161 UINT64_C(2015391744), // LDUMINH
5162 UINT64_C(945844224), // LDUMINLB
5163 UINT64_C(2019586048), // LDUMINLH
5164 UINT64_C(3093327872), // LDUMINLW
5165 UINT64_C(4167069696), // LDUMINLX
5166 UINT64_C(3089133568), // LDUMINW
5167 UINT64_C(4162875392), // LDUMINX
5168 UINT64_C(943718400), // LDURBBi
5169 UINT64_C(1010827264), // LDURBi
5170 UINT64_C(4232052736), // LDURDi
5171 UINT64_C(2017460224), // LDURHHi
5172 UINT64_C(2084569088), // LDURHi
5173 UINT64_C(1019215872), // LDURQi
5174 UINT64_C(952107008), // LDURSBWi
5175 UINT64_C(947912704), // LDURSBXi
5176 UINT64_C(2025848832), // LDURSHWi
5177 UINT64_C(2021654528), // LDURSHXi
5178 UINT64_C(3095396352), // LDURSWi
5179 UINT64_C(3158310912), // LDURSi
5180 UINT64_C(3091202048), // LDURWi
5181 UINT64_C(4164943872), // LDURXi
5182 UINT64_C(2290024448), // LDXPW
5183 UINT64_C(3363766272), // LDXPX
5184 UINT64_C(140475392), // LDXRB
5185 UINT64_C(1214217216), // LDXRH
5186 UINT64_C(2287959040), // LDXRW
5187 UINT64_C(3361700864), // LDXRX
5188 UINT64_C(68648960), // LSLR_ZPmZ_B
5189 UINT64_C(81231872), // LSLR_ZPmZ_D
5190 UINT64_C(72843264), // LSLR_ZPmZ_H
5191 UINT64_C(77037568), // LSLR_ZPmZ_S
5192 UINT64_C(448798720), // LSLVWr
5193 UINT64_C(2596282368), // LSLVXr
5194 UINT64_C(68911104), // LSL_WIDE_ZPmZ_B
5195 UINT64_C(73105408), // LSL_WIDE_ZPmZ_H
5196 UINT64_C(77299712), // LSL_WIDE_ZPmZ_S
5197 UINT64_C(69241856), // LSL_WIDE_ZZZ_B
5198 UINT64_C(73436160), // LSL_WIDE_ZZZ_H
5199 UINT64_C(77630464), // LSL_WIDE_ZZZ_S
5200 UINT64_C(67338496), // LSL_ZPmI_B
5201 UINT64_C(75726848), // LSL_ZPmI_D
5202 UINT64_C(67338752), // LSL_ZPmI_H
5203 UINT64_C(71532544), // LSL_ZPmI_S
5204 UINT64_C(68386816), // LSL_ZPmZ_B
5205 UINT64_C(80969728), // LSL_ZPmZ_D
5206 UINT64_C(72581120), // LSL_ZPmZ_H
5207 UINT64_C(76775424), // LSL_ZPmZ_S
5208 UINT64_C(69770240), // LSL_ZZI_B
5209 UINT64_C(77634560), // LSL_ZZI_D
5210 UINT64_C(70294528), // LSL_ZZI_H
5211 UINT64_C(73440256), // LSL_ZZI_S
5212 UINT64_C(68517888), // LSRR_ZPmZ_B
5213 UINT64_C(81100800), // LSRR_ZPmZ_D
5214 UINT64_C(72712192), // LSRR_ZPmZ_H
5215 UINT64_C(76906496), // LSRR_ZPmZ_S
5216 UINT64_C(448799744), // LSRVWr
5217 UINT64_C(2596283392), // LSRVXr
5218 UINT64_C(68780032), // LSR_WIDE_ZPmZ_B
5219 UINT64_C(72974336), // LSR_WIDE_ZPmZ_H
5220 UINT64_C(77168640), // LSR_WIDE_ZPmZ_S
5221 UINT64_C(69239808), // LSR_WIDE_ZZZ_B
5222 UINT64_C(73434112), // LSR_WIDE_ZZZ_H
5223 UINT64_C(77628416), // LSR_WIDE_ZZZ_S
5224 UINT64_C(67207424), // LSR_ZPmI_B
5225 UINT64_C(75595776), // LSR_ZPmI_D
5226 UINT64_C(67207680), // LSR_ZPmI_H
5227 UINT64_C(71401472), // LSR_ZPmI_S
5228 UINT64_C(68255744), // LSR_ZPmZ_B
5229 UINT64_C(80838656), // LSR_ZPmZ_D
5230 UINT64_C(72450048), // LSR_ZPmZ_H
5231 UINT64_C(76644352), // LSR_ZPmZ_S
5232 UINT64_C(69768192), // LSR_ZZI_B
5233 UINT64_C(77632512), // LSR_ZZI_D
5234 UINT64_C(70292480), // LSR_ZZI_H
5235 UINT64_C(73438208), // LSR_ZZI_S
5236 UINT64_C(1317015552), // LUT2_B
5237 UINT64_C(1321205760), // LUT2_H
5238 UINT64_C(1312825344), // LUT4_B
5239 UINT64_C(1312821248), // LUT4_H
5240 UINT64_C(3230416896), // LUTI2_2ZTZI_B
5241 UINT64_C(3230420992), // LUTI2_2ZTZI_H
5242 UINT64_C(3230425088), // LUTI2_2ZTZI_S
5243 UINT64_C(3230433280), // LUTI2_4ZTZI_B
5244 UINT64_C(3230437376), // LUTI2_4ZTZI_H
5245 UINT64_C(3230441472), // LUTI2_4ZTZI_S
5246 UINT64_C(3231465472), // LUTI2_S_2ZTZI_B
5247 UINT64_C(3231469568), // LUTI2_S_2ZTZI_H
5248 UINT64_C(3231481856), // LUTI2_S_4ZTZI_B
5249 UINT64_C(3231485952), // LUTI2_S_4ZTZI_H
5250 UINT64_C(3234594816), // LUTI2_ZTZI_B
5251 UINT64_C(3234598912), // LUTI2_ZTZI_H
5252 UINT64_C(3234603008), // LUTI2_ZTZI_S
5253 UINT64_C(1159770112), // LUTI2_ZZZI_B
5254 UINT64_C(1159768064), // LUTI2_ZZZI_H
5255 UINT64_C(3230285824), // LUTI4_2ZTZI_B
5256 UINT64_C(3230289920), // LUTI4_2ZTZI_H
5257 UINT64_C(3230294016), // LUTI4_2ZTZI_S
5258 UINT64_C(3230306304), // LUTI4_4ZTZI_H
5259 UINT64_C(3230310400), // LUTI4_4ZTZI_S
5260 UINT64_C(3230334976), // LUTI4_4ZZT2Z
5261 UINT64_C(3231334400), // LUTI4_S_2ZTZI_B
5262 UINT64_C(3231338496), // LUTI4_S_2ZTZI_H
5263 UINT64_C(3231354880), // LUTI4_S_4ZTZI_H
5264 UINT64_C(3231383552), // LUTI4_S_4ZZT2Z
5265 UINT64_C(1159771136), // LUTI4_Z2ZZI
5266 UINT64_C(3234463744), // LUTI4_ZTZI_B
5267 UINT64_C(3234467840), // LUTI4_ZTZI_H
5268 UINT64_C(3234471936), // LUTI4_ZTZI_S
5269 UINT64_C(1163961344), // LUTI4_ZZZI_B
5270 UINT64_C(1159773184), // LUTI4_ZZZI_H
5271 UINT64_C(2606759936), // MADDPT
5272 UINT64_C(452984832), // MADDWrrr
5273 UINT64_C(2600468480), // MADDXrrr
5274 UINT64_C(1153488896), // MAD_CPA
5275 UINT64_C(67158016), // MAD_ZPmZZ_B
5276 UINT64_C(79740928), // MAD_ZPmZZ_D
5277 UINT64_C(71352320), // MAD_ZPmZZ_H
5278 UINT64_C(75546624), // MAD_ZPmZZ_S
5279 UINT64_C(1159757824), // MATCH_PPzZZ_B
5280 UINT64_C(1163952128), // MATCH_PPzZZ_H
5281 UINT64_C(1153486848), // MLA_CPA
5282 UINT64_C(67125248), // MLA_ZPmZZ_B
5283 UINT64_C(79708160), // MLA_ZPmZZ_D
5284 UINT64_C(71319552), // MLA_ZPmZZ_H
5285 UINT64_C(75513856), // MLA_ZPmZZ_S
5286 UINT64_C(1155532800), // MLA_ZZZI_D
5287 UINT64_C(1142949888), // MLA_ZZZI_H
5288 UINT64_C(1151338496), // MLA_ZZZI_S
5289 UINT64_C(1310757888), // MLAv16i8
5290 UINT64_C(245404672), // MLAv2i32
5291 UINT64_C(796917760), // MLAv2i32_indexed
5292 UINT64_C(241210368), // MLAv4i16
5293 UINT64_C(792723456), // MLAv4i16_indexed
5294 UINT64_C(1319146496), // MLAv4i32
5295 UINT64_C(1870659584), // MLAv4i32_indexed
5296 UINT64_C(1314952192), // MLAv8i16
5297 UINT64_C(1866465280), // MLAv8i16_indexed
5298 UINT64_C(237016064), // MLAv8i8
5299 UINT64_C(67133440), // MLS_ZPmZZ_B
5300 UINT64_C(79716352), // MLS_ZPmZZ_D
5301 UINT64_C(71327744), // MLS_ZPmZZ_H
5302 UINT64_C(75522048), // MLS_ZPmZZ_S
5303 UINT64_C(1155533824), // MLS_ZZZI_D
5304 UINT64_C(1142950912), // MLS_ZZZI_H
5305 UINT64_C(1151339520), // MLS_ZZZI_S
5306 UINT64_C(1847628800), // MLSv16i8
5307 UINT64_C(782275584), // MLSv2i32
5308 UINT64_C(796934144), // MLSv2i32_indexed
5309 UINT64_C(778081280), // MLSv4i16
5310 UINT64_C(792739840), // MLSv4i16_indexed
5311 UINT64_C(1856017408), // MLSv4i32
5312 UINT64_C(1870675968), // MLSv4i32_indexed
5313 UINT64_C(1851823104), // MLSv8i16
5314 UINT64_C(1866481664), // MLSv8i16_indexed
5315 UINT64_C(773886976), // MLSv8i8
5316 UINT64_C(499155968), // MOPSSETGE
5317 UINT64_C(499164160), // MOPSSETGEN
5318 UINT64_C(499160064), // MOPSSETGET
5319 UINT64_C(499168256), // MOPSSETGETN
5320 UINT64_C(3221619200), // MOVAZ_2ZMI_H_B
5321 UINT64_C(3234202112), // MOVAZ_2ZMI_H_D
5322 UINT64_C(3225813504), // MOVAZ_2ZMI_H_H
5323 UINT64_C(3230007808), // MOVAZ_2ZMI_H_S
5324 UINT64_C(3221651968), // MOVAZ_2ZMI_V_B
5325 UINT64_C(3234234880), // MOVAZ_2ZMI_V_D
5326 UINT64_C(3225846272), // MOVAZ_2ZMI_V_H
5327 UINT64_C(3230040576), // MOVAZ_2ZMI_V_S
5328 UINT64_C(3221620224), // MOVAZ_4ZMI_H_B
5329 UINT64_C(3234203136), // MOVAZ_4ZMI_H_D
5330 UINT64_C(3225814528), // MOVAZ_4ZMI_H_H
5331 UINT64_C(3230008832), // MOVAZ_4ZMI_H_S
5332 UINT64_C(3221652992), // MOVAZ_4ZMI_V_B
5333 UINT64_C(3234235904), // MOVAZ_4ZMI_V_D
5334 UINT64_C(3225847296), // MOVAZ_4ZMI_V_H
5335 UINT64_C(3230041600), // MOVAZ_4ZMI_V_S
5336 UINT64_C(3221621248), // MOVAZ_VG2_2ZMXI
5337 UINT64_C(3221622272), // MOVAZ_VG4_4ZMXI
5338 UINT64_C(3221357056), // MOVAZ_ZMI_H_B
5339 UINT64_C(3233939968), // MOVAZ_ZMI_H_D
5340 UINT64_C(3225551360), // MOVAZ_ZMI_H_H
5341 UINT64_C(3234005504), // MOVAZ_ZMI_H_Q
5342 UINT64_C(3229745664), // MOVAZ_ZMI_H_S
5343 UINT64_C(3221389824), // MOVAZ_ZMI_V_B
5344 UINT64_C(3233972736), // MOVAZ_ZMI_V_D
5345 UINT64_C(3225584128), // MOVAZ_ZMI_V_H
5346 UINT64_C(3234038272), // MOVAZ_ZMI_V_Q
5347 UINT64_C(3229778432), // MOVAZ_ZMI_V_S
5348 UINT64_C(3221618688), // MOVA_2ZMXI_H_B
5349 UINT64_C(3234201600), // MOVA_2ZMXI_H_D
5350 UINT64_C(3225812992), // MOVA_2ZMXI_H_H
5351 UINT64_C(3230007296), // MOVA_2ZMXI_H_S
5352 UINT64_C(3221651456), // MOVA_2ZMXI_V_B
5353 UINT64_C(3234234368), // MOVA_2ZMXI_V_D
5354 UINT64_C(3225845760), // MOVA_2ZMXI_V_H
5355 UINT64_C(3230040064), // MOVA_2ZMXI_V_S
5356 UINT64_C(3221619712), // MOVA_4ZMXI_H_B
5357 UINT64_C(3234202624), // MOVA_4ZMXI_H_D
5358 UINT64_C(3225814016), // MOVA_4ZMXI_H_H
5359 UINT64_C(3230008320), // MOVA_4ZMXI_H_S
5360 UINT64_C(3221652480), // MOVA_4ZMXI_V_B
5361 UINT64_C(3234235392), // MOVA_4ZMXI_V_D
5362 UINT64_C(3225846784), // MOVA_4ZMXI_V_H
5363 UINT64_C(3230041088), // MOVA_4ZMXI_V_S
5364 UINT64_C(3221487616), // MOVA_MXI2Z_H_B
5365 UINT64_C(3234070528), // MOVA_MXI2Z_H_D
5366 UINT64_C(3225681920), // MOVA_MXI2Z_H_H
5367 UINT64_C(3229876224), // MOVA_MXI2Z_H_S
5368 UINT64_C(3221520384), // MOVA_MXI2Z_V_B
5369 UINT64_C(3234103296), // MOVA_MXI2Z_V_D
5370 UINT64_C(3225714688), // MOVA_MXI2Z_V_H
5371 UINT64_C(3229908992), // MOVA_MXI2Z_V_S
5372 UINT64_C(3221488640), // MOVA_MXI4Z_H_B
5373 UINT64_C(3234071552), // MOVA_MXI4Z_H_D
5374 UINT64_C(3225682944), // MOVA_MXI4Z_H_H
5375 UINT64_C(3229877248), // MOVA_MXI4Z_H_S
5376 UINT64_C(3221521408), // MOVA_MXI4Z_V_B
5377 UINT64_C(3234104320), // MOVA_MXI4Z_V_D
5378 UINT64_C(3225715712), // MOVA_MXI4Z_V_H
5379 UINT64_C(3229910016), // MOVA_MXI4Z_V_S
5380 UINT64_C(3221620736), // MOVA_VG2_2ZMXI
5381 UINT64_C(3221489664), // MOVA_VG2_MXI2Z
5382 UINT64_C(3221621760), // MOVA_VG4_4ZMXI
5383 UINT64_C(3221490688), // MOVA_VG4_MXI4Z
5384 UINT64_C(788587520), // MOVID
5385 UINT64_C(1325458432), // MOVIv16b_ns
5386 UINT64_C(1862329344), // MOVIv2d_ns
5387 UINT64_C(251659264), // MOVIv2i32
5388 UINT64_C(251708416), // MOVIv2s_msl
5389 UINT64_C(251692032), // MOVIv4i16
5390 UINT64_C(1325401088), // MOVIv4i32
5391 UINT64_C(1325450240), // MOVIv4s_msl
5392 UINT64_C(251716608), // MOVIv8b_ns
5393 UINT64_C(1325433856), // MOVIv8i16
5394 UINT64_C(1920991232), // MOVKWi
5395 UINT64_C(4068474880), // MOVKXi
5396 UINT64_C(310378496), // MOVNWi
5397 UINT64_C(2457862144), // MOVNXi
5398 UINT64_C(68231168), // MOVPRFX_ZPmZ_B
5399 UINT64_C(80814080), // MOVPRFX_ZPmZ_D
5400 UINT64_C(72425472), // MOVPRFX_ZPmZ_H
5401 UINT64_C(76619776), // MOVPRFX_ZPmZ_S
5402 UINT64_C(68165632), // MOVPRFX_ZPzZ_B
5403 UINT64_C(80748544), // MOVPRFX_ZPzZ_D
5404 UINT64_C(72359936), // MOVPRFX_ZPzZ_H
5405 UINT64_C(76554240), // MOVPRFX_ZPzZ_S
5406 UINT64_C(69254144), // MOVPRFX_ZZ
5407 UINT64_C(3226338272), // MOVT_TIX
5408 UINT64_C(3226403808), // MOVT_TIZ
5409 UINT64_C(3226207200), // MOVT_XTI
5410 UINT64_C(1384120320), // MOVZWi
5411 UINT64_C(3531603968), // MOVZXi
5412 UINT64_C(3579838464), // MRRS
5413 UINT64_C(3575644160), // MRS
5414 UINT64_C(67166208), // MSB_ZPmZZ_B
5415 UINT64_C(79749120), // MSB_ZPmZZ_D
5416 UINT64_C(71360512), // MSB_ZPmZZ_H
5417 UINT64_C(75554816), // MSB_ZPmZZ_S
5418 UINT64_C(3573547008), // MSR
5419 UINT64_C(3577741312), // MSRR
5420 UINT64_C(3573563423), // MSRpstateImm1
5421 UINT64_C(3573563423), // MSRpstateImm4
5422 UINT64_C(3573760127), // MSRpstatesvcrImm1
5423 UINT64_C(2606792704), // MSUBPT
5424 UINT64_C(453017600), // MSUBWrrr
5425 UINT64_C(2600501248), // MSUBXrrr
5426 UINT64_C(623951872), // MUL_ZI_B
5427 UINT64_C(636534784), // MUL_ZI_D
5428 UINT64_C(628146176), // MUL_ZI_H
5429 UINT64_C(632340480), // MUL_ZI_S
5430 UINT64_C(68157440), // MUL_ZPmZ_B
5431 UINT64_C(80740352), // MUL_ZPmZ_D
5432 UINT64_C(72351744), // MUL_ZPmZ_H
5433 UINT64_C(76546048), // MUL_ZPmZ_S
5434 UINT64_C(1155594240), // MUL_ZZZI_D
5435 UINT64_C(1143011328), // MUL_ZZZI_H
5436 UINT64_C(1151399936), // MUL_ZZZI_S
5437 UINT64_C(69230592), // MUL_ZZZ_B
5438 UINT64_C(81813504), // MUL_ZZZ_D
5439 UINT64_C(73424896), // MUL_ZZZ_H
5440 UINT64_C(77619200), // MUL_ZZZ_S
5441 UINT64_C(1310759936), // MULv16i8
5442 UINT64_C(245406720), // MULv2i32
5443 UINT64_C(260079616), // MULv2i32_indexed
5444 UINT64_C(241212416), // MULv4i16
5445 UINT64_C(255885312), // MULv4i16_indexed
5446 UINT64_C(1319148544), // MULv4i32
5447 UINT64_C(1333821440), // MULv4i32_indexed
5448 UINT64_C(1314954240), // MULv8i16
5449 UINT64_C(1329627136), // MULv8i16_indexed
5450 UINT64_C(237018112), // MULv8i8
5451 UINT64_C(788530176), // MVNIv2i32
5452 UINT64_C(788579328), // MVNIv2s_msl
5453 UINT64_C(788562944), // MVNIv4i16
5454 UINT64_C(1862272000), // MVNIv4i32
5455 UINT64_C(1862321152), // MVNIv4s_msl
5456 UINT64_C(1862304768), // MVNIv8i16
5457 UINT64_C(633356816), // NANDS_PPzPP
5458 UINT64_C(629162512), // NAND_PPzPP
5459 UINT64_C(81804288), // NBSL_ZZZZ
5460 UINT64_C(68657152), // NEG_ZPmZ_B
5461 UINT64_C(81240064), // NEG_ZPmZ_D
5462 UINT64_C(72851456), // NEG_ZPmZ_H
5463 UINT64_C(77045760), // NEG_ZPmZ_S
5464 UINT64_C(67608576), // NEG_ZPzZ_B
5465 UINT64_C(80191488), // NEG_ZPzZ_D
5466 UINT64_C(71802880), // NEG_ZPzZ_H
5467 UINT64_C(75997184), // NEG_ZPzZ_S
5468 UINT64_C(1847638016), // NEGv16i8
5469 UINT64_C(2128656384), // NEGv1i64
5470 UINT64_C(782284800), // NEGv2i32
5471 UINT64_C(1860220928), // NEGv2i64
5472 UINT64_C(778090496), // NEGv4i16
5473 UINT64_C(1856026624), // NEGv4i32
5474 UINT64_C(1851832320), // NEGv8i16
5475 UINT64_C(773896192), // NEGv8i8
5476 UINT64_C(1159757840), // NMATCH_PPzZZ_B
5477 UINT64_C(1163952144), // NMATCH_PPzZZ_H
5478 UINT64_C(633356800), // NORS_PPzPP
5479 UINT64_C(629162496), // NOR_PPzPP
5480 UINT64_C(69115904), // NOT_ZPmZ_B
5481 UINT64_C(81698816), // NOT_ZPmZ_D
5482 UINT64_C(73310208), // NOT_ZPmZ_H
5483 UINT64_C(77504512), // NOT_ZPmZ_S
5484 UINT64_C(68067328), // NOT_ZPzZ_B
5485 UINT64_C(80650240), // NOT_ZPzZ_D
5486 UINT64_C(72261632), // NOT_ZPzZ_H
5487 UINT64_C(76455936), // NOT_ZPzZ_S
5488 UINT64_C(1847613440), // NOTv16i8
5489 UINT64_C(773871616), // NOTv8i8
5490 UINT64_C(633356304), // ORNS_PPzPP
5491 UINT64_C(706740224), // ORNWrs
5492 UINT64_C(2854223872), // ORNXrs
5493 UINT64_C(629162000), // ORN_PPzPP
5494 UINT64_C(1323310080), // ORNv16i8
5495 UINT64_C(249568256), // ORNv8i8
5496 UINT64_C(68952064), // ORQV_VPZ_B
5497 UINT64_C(81534976), // ORQV_VPZ_D
5498 UINT64_C(73146368), // ORQV_VPZ_H
5499 UINT64_C(77340672), // ORQV_VPZ_S
5500 UINT64_C(633356288), // ORRS_PPzPP
5501 UINT64_C(838860800), // ORRWri
5502 UINT64_C(704643072), // ORRWrs
5503 UINT64_C(2986344448), // ORRXri
5504 UINT64_C(2852126720), // ORRXrs
5505 UINT64_C(629161984), // ORR_PPzPP
5506 UINT64_C(83886080), // ORR_ZI
5507 UINT64_C(68681728), // ORR_ZPmZ_B
5508 UINT64_C(81264640), // ORR_ZPmZ_D
5509 UINT64_C(72876032), // ORR_ZPmZ_H
5510 UINT64_C(77070336), // ORR_ZPmZ_S
5511 UINT64_C(73412608), // ORR_ZZZ
5512 UINT64_C(1319115776), // ORRv16i8
5513 UINT64_C(251663360), // ORRv2i32
5514 UINT64_C(251696128), // ORRv4i16
5515 UINT64_C(1325405184), // ORRv4i32
5516 UINT64_C(1325437952), // ORRv8i16
5517 UINT64_C(245373952), // ORRv8i8
5518 UINT64_C(68689920), // ORV_VPZ_B
5519 UINT64_C(81272832), // ORV_VPZ_D
5520 UINT64_C(72884224), // ORV_VPZ_H
5521 UINT64_C(77078528), // ORV_VPZ_S
5522 UINT64_C(3670083584), // PACDA
5523 UINT64_C(3670084608), // PACDB
5524 UINT64_C(3670092768), // PACDZA
5525 UINT64_C(3670093792), // PACDZB
5526 UINT64_C(2596286464), // PACGA
5527 UINT64_C(3670081536), // PACIA
5528 UINT64_C(3573752095), // PACIA1716
5529 UINT64_C(3670117374), // PACIA171615
5530 UINT64_C(3573752639), // PACIASP
5531 UINT64_C(3670123518), // PACIASPPC
5532 UINT64_C(3573752607), // PACIAZ
5533 UINT64_C(3670082560), // PACIB
5534 UINT64_C(3573752159), // PACIB1716
5535 UINT64_C(3670118398), // PACIB171615
5536 UINT64_C(3573752703), // PACIBSP
5537 UINT64_C(3670124542), // PACIBSPPC
5538 UINT64_C(3573752671), // PACIBZ
5539 UINT64_C(3670090720), // PACIZA
5540 UINT64_C(3670091744), // PACIZB
5541 UINT64_C(3573753087), // PACM
5542 UINT64_C(3670115326), // PACNBIASPPC
5543 UINT64_C(3670116350), // PACNBIBSPPC
5544 UINT64_C(622883856), // PEXT_2PCI_B
5545 UINT64_C(635466768), // PEXT_2PCI_D
5546 UINT64_C(627078160), // PEXT_2PCI_H
5547 UINT64_C(631272464), // PEXT_2PCI_S
5548 UINT64_C(622882832), // PEXT_PCI_B
5549 UINT64_C(635465744), // PEXT_PCI_D
5550 UINT64_C(627077136), // PEXT_PCI_H
5551 UINT64_C(631271440), // PEXT_PCI_S
5552 UINT64_C(622388224), // PFALSE
5553 UINT64_C(626573312), // PFIRST_B
5554 UINT64_C(1159789568), // PMLAL_2ZZZ_Q
5555 UINT64_C(86652928), // PMOV_PZI_B
5556 UINT64_C(94910464), // PMOV_PZI_D
5557 UINT64_C(86784000), // PMOV_PZI_H
5558 UINT64_C(90716160), // PMOV_PZI_S
5559 UINT64_C(86718464), // PMOV_ZIP_B
5560 UINT64_C(94976000), // PMOV_ZIP_D
5561 UINT64_C(86849536), // PMOV_ZIP_H
5562 UINT64_C(90781696), // PMOV_ZIP_S
5563 UINT64_C(1170237440), // PMULLB_ZZZ_D
5564 UINT64_C(1161848832), // PMULLB_ZZZ_H
5565 UINT64_C(1157654528), // PMULLB_ZZZ_Q
5566 UINT64_C(1170238464), // PMULLT_ZZZ_D
5567 UINT64_C(1161849856), // PMULLT_ZZZ_H
5568 UINT64_C(1157655552), // PMULLT_ZZZ_Q
5569 UINT64_C(1159788544), // PMULL_2ZZZ_Q
5570 UINT64_C(1310777344), // PMULLv16i8
5571 UINT64_C(249618432), // PMULLv1i64
5572 UINT64_C(1323360256), // PMULLv2i64
5573 UINT64_C(237035520), // PMULLv8i8
5574 UINT64_C(69231616), // PMUL_ZZZ_B
5575 UINT64_C(1847630848), // PMULv16i8
5576 UINT64_C(773889024), // PMULv8i8
5577 UINT64_C(622445568), // PNEXT_B
5578 UINT64_C(635028480), // PNEXT_D
5579 UINT64_C(626639872), // PNEXT_H
5580 UINT64_C(630834176), // PNEXT_S
5581 UINT64_C(3288391680), // PRFB_D_PZI
5582 UINT64_C(3294658560), // PRFB_D_SCALED
5583 UINT64_C(3294625792), // PRFB_D_SXTW_SCALED
5584 UINT64_C(3290431488), // PRFB_D_UXTW_SCALED
5585 UINT64_C(2243952640), // PRFB_PRI
5586 UINT64_C(2214641664), // PRFB_PRR
5587 UINT64_C(2214649856), // PRFB_S_PZI
5588 UINT64_C(2220883968), // PRFB_S_SXTW_SCALED
5589 UINT64_C(2216689664), // PRFB_S_UXTW_SCALED
5590 UINT64_C(3313557504), // PRFD_D_PZI
5591 UINT64_C(3294683136), // PRFD_D_SCALED
5592 UINT64_C(3294650368), // PRFD_D_SXTW_SCALED
5593 UINT64_C(3290456064), // PRFD_D_UXTW_SCALED
5594 UINT64_C(2243977216), // PRFD_PRI
5595 UINT64_C(2239807488), // PRFD_PRR
5596 UINT64_C(2239815680), // PRFD_S_PZI
5597 UINT64_C(2220908544), // PRFD_S_SXTW_SCALED
5598 UINT64_C(2216714240), // PRFD_S_UXTW_SCALED
5599 UINT64_C(3296780288), // PRFH_D_PZI
5600 UINT64_C(3294666752), // PRFH_D_SCALED
5601 UINT64_C(3294633984), // PRFH_D_SXTW_SCALED
5602 UINT64_C(3290439680), // PRFH_D_UXTW_SCALED
5603 UINT64_C(2243960832), // PRFH_PRI
5604 UINT64_C(2223030272), // PRFH_PRR
5605 UINT64_C(2223038464), // PRFH_S_PZI
5606 UINT64_C(2220892160), // PRFH_S_SXTW_SCALED
5607 UINT64_C(2216697856), // PRFH_S_UXTW_SCALED
5608 UINT64_C(3623878656), // PRFMl
5609 UINT64_C(4171253760), // PRFMroW
5610 UINT64_C(4171261952), // PRFMroX
5611 UINT64_C(4185915392), // PRFMui
5612 UINT64_C(4169138176), // PRFUMi
5613 UINT64_C(3305168896), // PRFW_D_PZI
5614 UINT64_C(3294674944), // PRFW_D_SCALED
5615 UINT64_C(3294642176), // PRFW_D_SXTW_SCALED
5616 UINT64_C(3290447872), // PRFW_D_UXTW_SCALED
5617 UINT64_C(2243969024), // PRFW_PRI
5618 UINT64_C(2231418880), // PRFW_PRR
5619 UINT64_C(2231427072), // PRFW_S_PZI
5620 UINT64_C(2220900352), // PRFW_S_SXTW_SCALED
5621 UINT64_C(2216706048), // PRFW_S_UXTW_SCALED
5622 UINT64_C(623132672), // PSEL_PPPRI_B
5623 UINT64_C(627064832), // PSEL_PPPRI_D
5624 UINT64_C(623394816), // PSEL_PPPRI_H
5625 UINT64_C(623919104), // PSEL_PPPRI_S
5626 UINT64_C(626049024), // PTEST_PP
5627 UINT64_C(622452736), // PTRUES_B
5628 UINT64_C(635035648), // PTRUES_D
5629 UINT64_C(626647040), // PTRUES_H
5630 UINT64_C(630841344), // PTRUES_S
5631 UINT64_C(622387200), // PTRUE_B
5632 UINT64_C(622884880), // PTRUE_C_B
5633 UINT64_C(635467792), // PTRUE_C_D
5634 UINT64_C(627079184), // PTRUE_C_H
5635 UINT64_C(631273488), // PTRUE_C_S
5636 UINT64_C(634970112), // PTRUE_D
5637 UINT64_C(626581504), // PTRUE_H
5638 UINT64_C(630775808), // PTRUE_S
5639 UINT64_C(87113728), // PUNPKHI_PP
5640 UINT64_C(87048192), // PUNPKLO_PP
5641 UINT64_C(1163945984), // RADDHNB_ZZZ_B
5642 UINT64_C(1168140288), // RADDHNB_ZZZ_H
5643 UINT64_C(1172334592), // RADDHNB_ZZZ_S
5644 UINT64_C(1163947008), // RADDHNT_ZZZ_B
5645 UINT64_C(1168141312), // RADDHNT_ZZZ_H
5646 UINT64_C(1172335616), // RADDHNT_ZZZ_S
5647 UINT64_C(782254080), // RADDHNv2i64_v2i32
5648 UINT64_C(1855995904), // RADDHNv2i64_v4i32
5649 UINT64_C(778059776), // RADDHNv4i32_v4i16
5650 UINT64_C(1851801600), // RADDHNv4i32_v8i16
5651 UINT64_C(1847607296), // RADDHNv8i16_v16i8
5652 UINT64_C(773865472), // RADDHNv8i16_v8i8
5653 UINT64_C(3462433792), // RAX1
5654 UINT64_C(1159787520), // RAX1_ZZZ_D
5655 UINT64_C(1522532352), // RBITWr
5656 UINT64_C(3670016000), // RBITXr
5657 UINT64_C(86474752), // RBIT_ZPmZ_B
5658 UINT64_C(99057664), // RBIT_ZPmZ_D
5659 UINT64_C(90669056), // RBIT_ZPmZ_H
5660 UINT64_C(94863360), // RBIT_ZPmZ_S
5661 UINT64_C(86482944), // RBIT_ZPzZ_B
5662 UINT64_C(99065856), // RBIT_ZPzZ_D
5663 UINT64_C(90677248), // RBIT_ZPzZ_H
5664 UINT64_C(94871552), // RBIT_ZPzZ_S
5665 UINT64_C(1851807744), // RBITv16i8
5666 UINT64_C(778065920), // RBITv8i8
5667 UINT64_C(421529600), // RCWCAS
5668 UINT64_C(429918208), // RCWCASA
5669 UINT64_C(434112512), // RCWCASAL
5670 UINT64_C(425723904), // RCWCASL
5671 UINT64_C(421530624), // RCWCASP
5672 UINT64_C(429919232), // RCWCASPA
5673 UINT64_C(434113536), // RCWCASPAL
5674 UINT64_C(425724928), // RCWCASPL
5675 UINT64_C(941658112), // RCWCLR
5676 UINT64_C(950046720), // RCWCLRA
5677 UINT64_C(954241024), // RCWCLRAL
5678 UINT64_C(945852416), // RCWCLRL
5679 UINT64_C(421564416), // RCWCLRP
5680 UINT64_C(429953024), // RCWCLRPA
5681 UINT64_C(434147328), // RCWCLRPAL
5682 UINT64_C(425758720), // RCWCLRPL
5683 UINT64_C(2015399936), // RCWCLRS
5684 UINT64_C(2023788544), // RCWCLRSA
5685 UINT64_C(2027982848), // RCWCLRSAL
5686 UINT64_C(2019594240), // RCWCLRSL
5687 UINT64_C(1495306240), // RCWCLRSP
5688 UINT64_C(1503694848), // RCWCLRSPA
5689 UINT64_C(1507889152), // RCWCLRSPAL
5690 UINT64_C(1499500544), // RCWCLRSPL
5691 UINT64_C(1495271424), // RCWSCAS
5692 UINT64_C(1503660032), // RCWSCASA
5693 UINT64_C(1507854336), // RCWSCASAL
5694 UINT64_C(1499465728), // RCWSCASL
5695 UINT64_C(1495272448), // RCWSCASP
5696 UINT64_C(1503661056), // RCWSCASPA
5697 UINT64_C(1507855360), // RCWSCASPAL
5698 UINT64_C(1499466752), // RCWSCASPL
5699 UINT64_C(941666304), // RCWSET
5700 UINT64_C(950054912), // RCWSETA
5701 UINT64_C(954249216), // RCWSETAL
5702 UINT64_C(945860608), // RCWSETL
5703 UINT64_C(421572608), // RCWSETP
5704 UINT64_C(429961216), // RCWSETPA
5705 UINT64_C(434155520), // RCWSETPAL
5706 UINT64_C(425766912), // RCWSETPL
5707 UINT64_C(2015408128), // RCWSETS
5708 UINT64_C(2023796736), // RCWSETSA
5709 UINT64_C(2027991040), // RCWSETSAL
5710 UINT64_C(2019602432), // RCWSETSL
5711 UINT64_C(1495314432), // RCWSETSP
5712 UINT64_C(1503703040), // RCWSETSPA
5713 UINT64_C(1507897344), // RCWSETSPAL
5714 UINT64_C(1499508736), // RCWSETSPL
5715 UINT64_C(941662208), // RCWSWP
5716 UINT64_C(950050816), // RCWSWPA
5717 UINT64_C(954245120), // RCWSWPAL
5718 UINT64_C(945856512), // RCWSWPL
5719 UINT64_C(421568512), // RCWSWPP
5720 UINT64_C(429957120), // RCWSWPPA
5721 UINT64_C(434151424), // RCWSWPPAL
5722 UINT64_C(425762816), // RCWSWPPL
5723 UINT64_C(2015404032), // RCWSWPS
5724 UINT64_C(2023792640), // RCWSWPSA
5725 UINT64_C(2027986944), // RCWSWPSAL
5726 UINT64_C(2019598336), // RCWSWPSL
5727 UINT64_C(1495310336), // RCWSWPSP
5728 UINT64_C(1503698944), // RCWSWPSPA
5729 UINT64_C(1507893248), // RCWSWPSPAL
5730 UINT64_C(1499504640), // RCWSWPSPL
5731 UINT64_C(626585600), // RDFFRS_PPz
5732 UINT64_C(622456832), // RDFFR_P
5733 UINT64_C(622391296), // RDFFR_PPz
5734 UINT64_C(79648768), // RDSVLI_XI
5735 UINT64_C(79646720), // RDVLI_XI
5736 UINT64_C(3596550144), // RET
5737 UINT64_C(3596553215), // RETAA
5738 UINT64_C(1426063391), // RETAASPPCi
5739 UINT64_C(3596553184), // RETAASPPCr
5740 UINT64_C(3596554239), // RETAB
5741 UINT64_C(1428160543), // RETABSPPCi
5742 UINT64_C(3596554208), // RETABSPPCr
5743 UINT64_C(1522533376), // REV16Wr
5744 UINT64_C(3670017024), // REV16Xr
5745 UINT64_C(1310726144), // REV16v16i8
5746 UINT64_C(236984320), // REV16v8i8
5747 UINT64_C(3670018048), // REV32Xr
5748 UINT64_C(1847592960), // REV32v16i8
5749 UINT64_C(778045440), // REV32v4i16
5750 UINT64_C(1851787264), // REV32v8i16
5751 UINT64_C(773851136), // REV32v8i8
5752 UINT64_C(1310722048), // REV64v16i8
5753 UINT64_C(245368832), // REV64v2i32
5754 UINT64_C(241174528), // REV64v4i16
5755 UINT64_C(1319110656), // REV64v4i32
5756 UINT64_C(1314916352), // REV64v8i16
5757 UINT64_C(236980224), // REV64v8i8
5758 UINT64_C(98861056), // REVB_ZPmZ_D
5759 UINT64_C(90472448), // REVB_ZPmZ_H
5760 UINT64_C(94666752), // REVB_ZPmZ_S
5761 UINT64_C(98869248), // REVB_ZPzZ_D
5762 UINT64_C(90480640), // REVB_ZPzZ_H
5763 UINT64_C(94674944), // REVB_ZPzZ_S
5764 UINT64_C(86933504), // REVD_ZPmZ
5765 UINT64_C(86941696), // REVD_ZPzZ
5766 UINT64_C(98926592), // REVH_ZPmZ_D
5767 UINT64_C(94732288), // REVH_ZPmZ_S
5768 UINT64_C(98934784), // REVH_ZPzZ_D
5769 UINT64_C(94740480), // REVH_ZPzZ_S
5770 UINT64_C(98992128), // REVW_ZPmZ_D
5771 UINT64_C(99000320), // REVW_ZPzZ_D
5772 UINT64_C(1522534400), // REVWr
5773 UINT64_C(3670019072), // REVXr
5774 UINT64_C(87310336), // REV_PP_B
5775 UINT64_C(99893248), // REV_PP_D
5776 UINT64_C(91504640), // REV_PP_H
5777 UINT64_C(95698944), // REV_PP_S
5778 UINT64_C(87570432), // REV_ZZ_B
5779 UINT64_C(100153344), // REV_ZZ_D
5780 UINT64_C(91764736), // REV_ZZ_H
5781 UINT64_C(95959040), // REV_ZZ_S
5782 UINT64_C(3120563200), // RMIF
5783 UINT64_C(448801792), // RORVWr
5784 UINT64_C(2596285440), // RORVXr
5785 UINT64_C(4171253784), // RPRFM
5786 UINT64_C(1160255488), // RSHRNB_ZZI_B
5787 UINT64_C(1160779776), // RSHRNB_ZZI_H
5788 UINT64_C(1163925504), // RSHRNB_ZZI_S
5789 UINT64_C(1160256512), // RSHRNT_ZZI_B
5790 UINT64_C(1160780800), // RSHRNT_ZZI_H
5791 UINT64_C(1163926528), // RSHRNT_ZZI_S
5792 UINT64_C(1325960192), // RSHRNv16i8_shift
5793 UINT64_C(253791232), // RSHRNv2i32_shift
5794 UINT64_C(252742656), // RSHRNv4i16_shift
5795 UINT64_C(1327533056), // RSHRNv4i32_shift
5796 UINT64_C(1326484480), // RSHRNv8i16_shift
5797 UINT64_C(252218368), // RSHRNv8i8_shift
5798 UINT64_C(1163950080), // RSUBHNB_ZZZ_B
5799 UINT64_C(1168144384), // RSUBHNB_ZZZ_H
5800 UINT64_C(1172338688), // RSUBHNB_ZZZ_S
5801 UINT64_C(1163951104), // RSUBHNT_ZZZ_B
5802 UINT64_C(1168145408), // RSUBHNT_ZZZ_H
5803 UINT64_C(1172339712), // RSUBHNT_ZZZ_S
5804 UINT64_C(782262272), // RSUBHNv2i64_v2i32
5805 UINT64_C(1856004096), // RSUBHNv2i64_v4i32
5806 UINT64_C(778067968), // RSUBHNv4i32_v4i16
5807 UINT64_C(1851809792), // RSUBHNv4i32_v8i16
5808 UINT64_C(1847615488), // RSUBHNv8i16_v16i8
5809 UINT64_C(773873664), // RSUBHNv8i16_v8i8
5810 UINT64_C(1170259968), // SABALB_ZZZ_D
5811 UINT64_C(1161871360), // SABALB_ZZZ_H
5812 UINT64_C(1166065664), // SABALB_ZZZ_S
5813 UINT64_C(1170260992), // SABALT_ZZZ_D
5814 UINT64_C(1161872384), // SABALT_ZZZ_H
5815 UINT64_C(1166066688), // SABALT_ZZZ_S
5816 UINT64_C(1310740480), // SABALv16i8_v8i16
5817 UINT64_C(245387264), // SABALv2i32_v2i64
5818 UINT64_C(241192960), // SABALv4i16_v4i32
5819 UINT64_C(1319129088), // SABALv4i32_v2i64
5820 UINT64_C(1314934784), // SABALv8i16_v4i32
5821 UINT64_C(236998656), // SABALv8i8_v8i16
5822 UINT64_C(1157691392), // SABA_ZZZ_B
5823 UINT64_C(1170274304), // SABA_ZZZ_D
5824 UINT64_C(1161885696), // SABA_ZZZ_H
5825 UINT64_C(1166080000), // SABA_ZZZ_S
5826 UINT64_C(1310751744), // SABAv16i8
5827 UINT64_C(245398528), // SABAv2i32
5828 UINT64_C(241204224), // SABAv4i16
5829 UINT64_C(1319140352), // SABAv4i32
5830 UINT64_C(1314946048), // SABAv8i16
5831 UINT64_C(237009920), // SABAv8i8
5832 UINT64_C(1170223104), // SABDLB_ZZZ_D
5833 UINT64_C(1161834496), // SABDLB_ZZZ_H
5834 UINT64_C(1166028800), // SABDLB_ZZZ_S
5835 UINT64_C(1170224128), // SABDLT_ZZZ_D
5836 UINT64_C(1161835520), // SABDLT_ZZZ_H
5837 UINT64_C(1166029824), // SABDLT_ZZZ_S
5838 UINT64_C(1310748672), // SABDLv16i8_v8i16
5839 UINT64_C(245395456), // SABDLv2i32_v2i64
5840 UINT64_C(241201152), // SABDLv4i16_v4i32
5841 UINT64_C(1319137280), // SABDLv4i32_v2i64
5842 UINT64_C(1314942976), // SABDLv8i16_v4i32
5843 UINT64_C(237006848), // SABDLv8i8_v8i16
5844 UINT64_C(67895296), // SABD_ZPmZ_B
5845 UINT64_C(80478208), // SABD_ZPmZ_D
5846 UINT64_C(72089600), // SABD_ZPmZ_H
5847 UINT64_C(76283904), // SABD_ZPmZ_S
5848 UINT64_C(1310749696), // SABDv16i8
5849 UINT64_C(245396480), // SABDv2i32
5850 UINT64_C(241202176), // SABDv4i16
5851 UINT64_C(1319138304), // SABDv4i32
5852 UINT64_C(1314944000), // SABDv8i16
5853 UINT64_C(237007872), // SABDv8i8
5854 UINT64_C(1153736704), // SADALP_ZPmZ_D
5855 UINT64_C(1145348096), // SADALP_ZPmZ_H
5856 UINT64_C(1149542400), // SADALP_ZPmZ_S
5857 UINT64_C(1310746624), // SADALPv16i8_v8i16
5858 UINT64_C(245393408), // SADALPv2i32_v1i64
5859 UINT64_C(241199104), // SADALPv4i16_v2i32
5860 UINT64_C(1319135232), // SADALPv4i32_v2i64
5861 UINT64_C(1314940928), // SADALPv8i16_v4i32
5862 UINT64_C(237004800), // SADALPv8i8_v4i16
5863 UINT64_C(1170243584), // SADDLBT_ZZZ_D
5864 UINT64_C(1161854976), // SADDLBT_ZZZ_H
5865 UINT64_C(1166049280), // SADDLBT_ZZZ_S
5866 UINT64_C(1170210816), // SADDLB_ZZZ_D
5867 UINT64_C(1161822208), // SADDLB_ZZZ_H
5868 UINT64_C(1166016512), // SADDLB_ZZZ_S
5869 UINT64_C(1310730240), // SADDLPv16i8_v8i16
5870 UINT64_C(245377024), // SADDLPv2i32_v1i64
5871 UINT64_C(241182720), // SADDLPv4i16_v2i32
5872 UINT64_C(1319118848), // SADDLPv4i32_v2i64
5873 UINT64_C(1314924544), // SADDLPv8i16_v4i32
5874 UINT64_C(236988416), // SADDLPv8i8_v4i16
5875 UINT64_C(1170211840), // SADDLT_ZZZ_D
5876 UINT64_C(1161823232), // SADDLT_ZZZ_H
5877 UINT64_C(1166017536), // SADDLT_ZZZ_S
5878 UINT64_C(1311782912), // SADDLVv16i8v
5879 UINT64_C(242235392), // SADDLVv4i16v
5880 UINT64_C(1320171520), // SADDLVv4i32v
5881 UINT64_C(1315977216), // SADDLVv8i16v
5882 UINT64_C(238041088), // SADDLVv8i8v
5883 UINT64_C(1310720000), // SADDLv16i8_v8i16
5884 UINT64_C(245366784), // SADDLv2i32_v2i64
5885 UINT64_C(241172480), // SADDLv4i16_v4i32
5886 UINT64_C(1319108608), // SADDLv4i32_v2i64
5887 UINT64_C(1314914304), // SADDLv8i16_v4i32
5888 UINT64_C(236978176), // SADDLv8i8_v8i16
5889 UINT64_C(67117056), // SADDV_VPZ_B
5890 UINT64_C(71311360), // SADDV_VPZ_H
5891 UINT64_C(75505664), // SADDV_VPZ_S
5892 UINT64_C(1170227200), // SADDWB_ZZZ_D
5893 UINT64_C(1161838592), // SADDWB_ZZZ_H
5894 UINT64_C(1166032896), // SADDWB_ZZZ_S
5895 UINT64_C(1170228224), // SADDWT_ZZZ_D
5896 UINT64_C(1161839616), // SADDWT_ZZZ_H
5897 UINT64_C(1166033920), // SADDWT_ZZZ_S
5898 UINT64_C(1310724096), // SADDWv16i8_v8i16
5899 UINT64_C(245370880), // SADDWv2i32_v2i64
5900 UINT64_C(241176576), // SADDWv4i16_v4i32
5901 UINT64_C(1319112704), // SADDWv4i32_v2i64
5902 UINT64_C(1314918400), // SADDWv8i16_v4i32
5903 UINT64_C(236982272), // SADDWv8i8_v8i16
5904 UINT64_C(3573756159), // SB
5905 UINT64_C(1170264064), // SBCLB_ZZZ_D
5906 UINT64_C(1166069760), // SBCLB_ZZZ_S
5907 UINT64_C(1170265088), // SBCLT_ZZZ_D
5908 UINT64_C(1166070784), // SBCLT_ZZZ_S
5909 UINT64_C(2046820352), // SBCSWr
5910 UINT64_C(4194304000), // SBCSXr
5911 UINT64_C(1509949440), // SBCWr
5912 UINT64_C(3657433088), // SBCXr
5913 UINT64_C(318767104), // SBFMWri
5914 UINT64_C(2470445056), // SBFMXri
5915 UINT64_C(3240150016), // SCLAMP_VG2_2Z2Z_B
5916 UINT64_C(3252732928), // SCLAMP_VG2_2Z2Z_D
5917 UINT64_C(3244344320), // SCLAMP_VG2_2Z2Z_H
5918 UINT64_C(3248538624), // SCLAMP_VG2_2Z2Z_S
5919 UINT64_C(3240152064), // SCLAMP_VG4_4Z4Z_B
5920 UINT64_C(3252734976), // SCLAMP_VG4_4Z4Z_D
5921 UINT64_C(3244346368), // SCLAMP_VG4_4Z4Z_H
5922 UINT64_C(3248540672), // SCLAMP_VG4_4Z4Z_S
5923 UINT64_C(1140899840), // SCLAMP_ZZZ_B
5924 UINT64_C(1153482752), // SCLAMP_ZZZ_D
5925 UINT64_C(1145094144), // SCLAMP_ZZZ_H
5926 UINT64_C(1149288448), // SCLAMP_ZZZ_S
5927 UINT64_C(511442944), // SCVTFDSr
5928 UINT64_C(2667315200), // SCVTFHDr
5929 UINT64_C(519831552), // SCVTFHSr
5930 UINT64_C(2654732288), // SCVTFSDr
5931 UINT64_C(507674624), // SCVTFSWDri
5932 UINT64_C(516063232), // SCVTFSWHri
5933 UINT64_C(503480320), // SCVTFSWSri
5934 UINT64_C(2655125504), // SCVTFSXDri
5935 UINT64_C(2663514112), // SCVTFSXHri
5936 UINT64_C(2650931200), // SCVTFSXSri
5937 UINT64_C(509739008), // SCVTFUWDri
5938 UINT64_C(518127616), // SCVTFUWHri
5939 UINT64_C(505544704), // SCVTFUWSri
5940 UINT64_C(2657222656), // SCVTFUXDri
5941 UINT64_C(2665611264), // SCVTFUXHri
5942 UINT64_C(2653028352), // SCVTFUXSri
5943 UINT64_C(3240288256), // SCVTF_2Z2Z_StoS
5944 UINT64_C(3241336832), // SCVTF_4Z4Z_StoS
5945 UINT64_C(1708564480), // SCVTF_ZPmZ_DtoD
5946 UINT64_C(1700175872), // SCVTF_ZPmZ_DtoH
5947 UINT64_C(1708433408), // SCVTF_ZPmZ_DtoS
5948 UINT64_C(1699913728), // SCVTF_ZPmZ_HtoH
5949 UINT64_C(1708171264), // SCVTF_ZPmZ_StoD
5950 UINT64_C(1700044800), // SCVTF_ZPmZ_StoH
5951 UINT64_C(1704239104), // SCVTF_ZPmZ_StoS
5952 UINT64_C(1692254208), // SCVTF_ZPzZ_DtoD
5953 UINT64_C(1683865600), // SCVTF_ZPzZ_DtoH
5954 UINT64_C(1692237824), // SCVTF_ZPzZ_DtoS
5955 UINT64_C(1683800064), // SCVTF_ZPzZ_HtoH
5956 UINT64_C(1692172288), // SCVTF_ZPzZ_StoD
5957 UINT64_C(1683849216), // SCVTF_ZPzZ_StoH
5958 UINT64_C(1688043520), // SCVTF_ZPzZ_StoS
5959 UINT64_C(1598088192), // SCVTFd
5960 UINT64_C(1594942464), // SCVTFh
5961 UINT64_C(1595991040), // SCVTFs
5962 UINT64_C(1585043456), // SCVTFv1i16
5963 UINT64_C(1579276288), // SCVTFv1i32
5964 UINT64_C(1583470592), // SCVTFv1i64
5965 UINT64_C(237099008), // SCVTFv2f32
5966 UINT64_C(1315035136), // SCVTFv2f64
5967 UINT64_C(253813760), // SCVTFv2i32_shift
5968 UINT64_C(1329652736), // SCVTFv2i64_shift
5969 UINT64_C(242866176), // SCVTFv4f16
5970 UINT64_C(1310840832), // SCVTFv4f32
5971 UINT64_C(252765184), // SCVTFv4i16_shift
5972 UINT64_C(1327555584), // SCVTFv4i32_shift
5973 UINT64_C(1316608000), // SCVTFv8f16
5974 UINT64_C(1326507008), // SCVTFv8i16_shift
5975 UINT64_C(81133568), // SDIVR_ZPmZ_D
5976 UINT64_C(76939264), // SDIVR_ZPmZ_S
5977 UINT64_C(448793600), // SDIVWr
5978 UINT64_C(2596277248), // SDIVXr
5979 UINT64_C(81002496), // SDIV_ZPmZ_D
5980 UINT64_C(76808192), // SDIV_ZPmZ_S
5981 UINT64_C(3248493568), // SDOT_VG2_M2Z2Z_BtoS
5982 UINT64_C(3252687872), // SDOT_VG2_M2Z2Z_HtoD
5983 UINT64_C(3252687880), // SDOT_VG2_M2Z2Z_HtoS
5984 UINT64_C(3243249696), // SDOT_VG2_M2ZZI_BToS
5985 UINT64_C(3243249664), // SDOT_VG2_M2ZZI_HToS
5986 UINT64_C(3251634184), // SDOT_VG2_M2ZZI_HtoD
5987 UINT64_C(3240104960), // SDOT_VG2_M2ZZ_BtoS
5988 UINT64_C(3244299264), // SDOT_VG2_M2ZZ_HtoD
5989 UINT64_C(3244299272), // SDOT_VG2_M2ZZ_HtoS
5990 UINT64_C(3248559104), // SDOT_VG4_M4Z4Z_BtoS
5991 UINT64_C(3252753408), // SDOT_VG4_M4Z4Z_HtoD
5992 UINT64_C(3252753416), // SDOT_VG4_M4Z4Z_HtoS
5993 UINT64_C(3243282464), // SDOT_VG4_M4ZZI_BToS
5994 UINT64_C(3243282432), // SDOT_VG4_M4ZZI_HToS
5995 UINT64_C(3251666952), // SDOT_VG4_M4ZZI_HtoD
5996 UINT64_C(3241153536), // SDOT_VG4_M4ZZ_BtoS
5997 UINT64_C(3245347840), // SDOT_VG4_M4ZZ_HtoD
5998 UINT64_C(3245347848), // SDOT_VG4_M4ZZ_HtoS
5999 UINT64_C(1155530752), // SDOT_ZZZI_D
6000 UINT64_C(1149290496), // SDOT_ZZZI_HtoS
6001 UINT64_C(1151336448), // SDOT_ZZZI_S
6002 UINT64_C(1153433600), // SDOT_ZZZ_D
6003 UINT64_C(1140901888), // SDOT_ZZZ_HtoS
6004 UINT64_C(1149239296), // SDOT_ZZZ_S
6005 UINT64_C(1333846016), // SDOTlanev16i8
6006 UINT64_C(260104192), // SDOTlanev8i8
6007 UINT64_C(1317049344), // SDOTv16i8
6008 UINT64_C(243307520), // SDOTv8i8
6009 UINT64_C(620773904), // SEL_PPPP
6010 UINT64_C(3240132608), // SEL_VG2_2ZC2Z2Z_B
6011 UINT64_C(3252715520), // SEL_VG2_2ZC2Z2Z_D
6012 UINT64_C(3244326912), // SEL_VG2_2ZC2Z2Z_H
6013 UINT64_C(3248521216), // SEL_VG2_2ZC2Z2Z_S
6014 UINT64_C(3240198144), // SEL_VG4_4ZC4Z4Z_B
6015 UINT64_C(3252781056), // SEL_VG4_4ZC4Z4Z_D
6016 UINT64_C(3244392448), // SEL_VG4_4ZC4Z4Z_H
6017 UINT64_C(3248586752), // SEL_VG4_4ZC4Z4Z_S
6018 UINT64_C(86032384), // SEL_ZPZZ_B
6019 UINT64_C(98615296), // SEL_ZPZZ_D
6020 UINT64_C(90226688), // SEL_ZPZZ_H
6021 UINT64_C(94420992), // SEL_ZPZZ_S
6022 UINT64_C(432047104), // SETE
6023 UINT64_C(432055296), // SETEN
6024 UINT64_C(432051200), // SETET
6025 UINT64_C(432059392), // SETETN
6026 UINT64_C(973096973), // SETF16
6027 UINT64_C(973080589), // SETF8
6028 UINT64_C(623677440), // SETFFR
6029 UINT64_C(499139584), // SETGM
6030 UINT64_C(499147776), // SETGMN
6031 UINT64_C(499143680), // SETGMT
6032 UINT64_C(499151872), // SETGMTN
6033 UINT64_C(499123200), // SETGP
6034 UINT64_C(499131392), // SETGPN
6035 UINT64_C(499127296), // SETGPT
6036 UINT64_C(499135488), // SETGPTN
6037 UINT64_C(432030720), // SETM
6038 UINT64_C(432038912), // SETMN
6039 UINT64_C(432034816), // SETMT
6040 UINT64_C(432043008), // SETMTN
6041 UINT64_C(432014336), // SETP
6042 UINT64_C(432022528), // SETPN
6043 UINT64_C(432018432), // SETPT
6044 UINT64_C(432026624), // SETPTN
6045 UINT64_C(1577058304), // SHA1Crrr
6046 UINT64_C(1579681792), // SHA1Hrr
6047 UINT64_C(1577066496), // SHA1Mrrr
6048 UINT64_C(1577062400), // SHA1Prrr
6049 UINT64_C(1577070592), // SHA1SU0rrr
6050 UINT64_C(1579685888), // SHA1SU1rr
6051 UINT64_C(1577078784), // SHA256H2rrr
6052 UINT64_C(1577074688), // SHA256Hrrr
6053 UINT64_C(1579689984), // SHA256SU0rr
6054 UINT64_C(1577082880), // SHA256SU1rrr
6055 UINT64_C(3462430720), // SHA512H
6056 UINT64_C(3462431744), // SHA512H2
6057 UINT64_C(3468722176), // SHA512SU0
6058 UINT64_C(3462432768), // SHA512SU1
6059 UINT64_C(1141932032), // SHADD_ZPmZ_B
6060 UINT64_C(1154514944), // SHADD_ZPmZ_D
6061 UINT64_C(1146126336), // SHADD_ZPmZ_H
6062 UINT64_C(1150320640), // SHADD_ZPmZ_S
6063 UINT64_C(1310721024), // SHADDv16i8
6064 UINT64_C(245367808), // SHADDv2i32
6065 UINT64_C(241173504), // SHADDv4i16
6066 UINT64_C(1319109632), // SHADDv4i32
6067 UINT64_C(1314915328), // SHADDv8i16
6068 UINT64_C(236979200), // SHADDv8i8
6069 UINT64_C(1847670784), // SHLLv16i8
6070 UINT64_C(782317568), // SHLLv2i32
6071 UINT64_C(778123264), // SHLLv4i16
6072 UINT64_C(1856059392), // SHLLv4i32
6073 UINT64_C(1851865088), // SHLLv8i16
6074 UINT64_C(773928960), // SHLLv8i8
6075 UINT64_C(1598051328), // SHLd
6076 UINT64_C(1325945856), // SHLv16i8_shift
6077 UINT64_C(253776896), // SHLv2i32_shift
6078 UINT64_C(1329615872), // SHLv2i64_shift
6079 UINT64_C(252728320), // SHLv4i16_shift
6080 UINT64_C(1327518720), // SHLv4i32_shift
6081 UINT64_C(1326470144), // SHLv8i16_shift
6082 UINT64_C(252204032), // SHLv8i8_shift
6083 UINT64_C(1160253440), // SHRNB_ZZI_B
6084 UINT64_C(1160777728), // SHRNB_ZZI_H
6085 UINT64_C(1163923456), // SHRNB_ZZI_S
6086 UINT64_C(1160254464), // SHRNT_ZZI_B
6087 UINT64_C(1160778752), // SHRNT_ZZI_H
6088 UINT64_C(1163924480), // SHRNT_ZZI_S
6089 UINT64_C(1325958144), // SHRNv16i8_shift
6090 UINT64_C(253789184), // SHRNv2i32_shift
6091 UINT64_C(252740608), // SHRNv4i16_shift
6092 UINT64_C(1327531008), // SHRNv4i32_shift
6093 UINT64_C(1326482432), // SHRNv8i16_shift
6094 UINT64_C(252216320), // SHRNv8i8_shift
6095 UINT64_C(1142325248), // SHSUBR_ZPmZ_B
6096 UINT64_C(1154908160), // SHSUBR_ZPmZ_D
6097 UINT64_C(1146519552), // SHSUBR_ZPmZ_H
6098 UINT64_C(1150713856), // SHSUBR_ZPmZ_S
6099 UINT64_C(1142063104), // SHSUB_ZPmZ_B
6100 UINT64_C(1154646016), // SHSUB_ZPmZ_D
6101 UINT64_C(1146257408), // SHSUB_ZPmZ_H
6102 UINT64_C(1150451712), // SHSUB_ZPmZ_S
6103 UINT64_C(1310729216), // SHSUBv16i8
6104 UINT64_C(245376000), // SHSUBv2i32
6105 UINT64_C(241181696), // SHSUBv4i16
6106 UINT64_C(1319117824), // SHSUBv4i32
6107 UINT64_C(1314923520), // SHSUBv8i16
6108 UINT64_C(236987392), // SHSUBv8i8
6109 UINT64_C(1158214656), // SLI_ZZI_B
6110 UINT64_C(1166078976), // SLI_ZZI_D
6111 UINT64_C(1158738944), // SLI_ZZI_H
6112 UINT64_C(1161884672), // SLI_ZZI_S
6113 UINT64_C(2134922240), // SLId
6114 UINT64_C(1862816768), // SLIv16i8_shift
6115 UINT64_C(790647808), // SLIv2i32_shift
6116 UINT64_C(1866486784), // SLIv2i64_shift
6117 UINT64_C(789599232), // SLIv4i16_shift
6118 UINT64_C(1864389632), // SLIv4i32_shift
6119 UINT64_C(1863341056), // SLIv8i16_shift
6120 UINT64_C(789074944), // SLIv8i8_shift
6121 UINT64_C(3462447104), // SM3PARTW1
6122 UINT64_C(3462448128), // SM3PARTW2
6123 UINT64_C(3460300800), // SM3SS1
6124 UINT64_C(3460333568), // SM3TT1A
6125 UINT64_C(3460334592), // SM3TT1B
6126 UINT64_C(3460335616), // SM3TT2A
6127 UINT64_C(3460336640), // SM3TT2B
6128 UINT64_C(3468723200), // SM4E
6129 UINT64_C(1159786496), // SM4EKEY_ZZZ_S
6130 UINT64_C(3462449152), // SM4ENCKEY
6131 UINT64_C(1159979008), // SM4E_ZZZ_S
6132 UINT64_C(2602565632), // SMADDLrrr
6133 UINT64_C(1142202368), // SMAXP_ZPmZ_B
6134 UINT64_C(1154785280), // SMAXP_ZPmZ_D
6135 UINT64_C(1146396672), // SMAXP_ZPmZ_H
6136 UINT64_C(1150590976), // SMAXP_ZPmZ_S
6137 UINT64_C(1310761984), // SMAXPv16i8
6138 UINT64_C(245408768), // SMAXPv2i32
6139 UINT64_C(241214464), // SMAXPv4i16
6140 UINT64_C(1319150592), // SMAXPv4i32
6141 UINT64_C(1314956288), // SMAXPv8i16
6142 UINT64_C(237020160), // SMAXPv8i8
6143 UINT64_C(67903488), // SMAXQV_VPZ_B
6144 UINT64_C(80486400), // SMAXQV_VPZ_D
6145 UINT64_C(72097792), // SMAXQV_VPZ_H
6146 UINT64_C(76292096), // SMAXQV_VPZ_S
6147 UINT64_C(67641344), // SMAXV_VPZ_B
6148 UINT64_C(80224256), // SMAXV_VPZ_D
6149 UINT64_C(71835648), // SMAXV_VPZ_H
6150 UINT64_C(76029952), // SMAXV_VPZ_S
6151 UINT64_C(1311811584), // SMAXVv16i8v
6152 UINT64_C(242264064), // SMAXVv4i16v
6153 UINT64_C(1320200192), // SMAXVv4i32v
6154 UINT64_C(1316005888), // SMAXVv8i16v
6155 UINT64_C(238069760), // SMAXVv8i8v
6156 UINT64_C(297795584), // SMAXWri
6157 UINT64_C(448815104), // SMAXWrr
6158 UINT64_C(2445279232), // SMAXXri
6159 UINT64_C(2596298752), // SMAXXrr
6160 UINT64_C(3240144896), // SMAX_VG2_2Z2Z_B
6161 UINT64_C(3252727808), // SMAX_VG2_2Z2Z_D
6162 UINT64_C(3244339200), // SMAX_VG2_2Z2Z_H
6163 UINT64_C(3248533504), // SMAX_VG2_2Z2Z_S
6164 UINT64_C(3240140800), // SMAX_VG2_2ZZ_B
6165 UINT64_C(3252723712), // SMAX_VG2_2ZZ_D
6166 UINT64_C(3244335104), // SMAX_VG2_2ZZ_H
6167 UINT64_C(3248529408), // SMAX_VG2_2ZZ_S
6168 UINT64_C(3240146944), // SMAX_VG4_4Z4Z_B
6169 UINT64_C(3252729856), // SMAX_VG4_4Z4Z_D
6170 UINT64_C(3244341248), // SMAX_VG4_4Z4Z_H
6171 UINT64_C(3248535552), // SMAX_VG4_4Z4Z_S
6172 UINT64_C(3240142848), // SMAX_VG4_4ZZ_B
6173 UINT64_C(3252725760), // SMAX_VG4_4ZZ_D
6174 UINT64_C(3244337152), // SMAX_VG4_4ZZ_H
6175 UINT64_C(3248531456), // SMAX_VG4_4ZZ_S
6176 UINT64_C(623427584), // SMAX_ZI_B
6177 UINT64_C(636010496), // SMAX_ZI_D
6178 UINT64_C(627621888), // SMAX_ZI_H
6179 UINT64_C(631816192), // SMAX_ZI_S
6180 UINT64_C(67633152), // SMAX_ZPmZ_B
6181 UINT64_C(80216064), // SMAX_ZPmZ_D
6182 UINT64_C(71827456), // SMAX_ZPmZ_H
6183 UINT64_C(76021760), // SMAX_ZPmZ_S
6184 UINT64_C(1310745600), // SMAXv16i8
6185 UINT64_C(245392384), // SMAXv2i32
6186 UINT64_C(241198080), // SMAXv4i16
6187 UINT64_C(1319134208), // SMAXv4i32
6188 UINT64_C(1314939904), // SMAXv8i16
6189 UINT64_C(237003776), // SMAXv8i8
6190 UINT64_C(3556769795), // SMC
6191 UINT64_C(1142333440), // SMINP_ZPmZ_B
6192 UINT64_C(1154916352), // SMINP_ZPmZ_D
6193 UINT64_C(1146527744), // SMINP_ZPmZ_H
6194 UINT64_C(1150722048), // SMINP_ZPmZ_S
6195 UINT64_C(1310764032), // SMINPv16i8
6196 UINT64_C(245410816), // SMINPv2i32
6197 UINT64_C(241216512), // SMINPv4i16
6198 UINT64_C(1319152640), // SMINPv4i32
6199 UINT64_C(1314958336), // SMINPv8i16
6200 UINT64_C(237022208), // SMINPv8i8
6201 UINT64_C(68034560), // SMINQV_VPZ_B
6202 UINT64_C(80617472), // SMINQV_VPZ_D
6203 UINT64_C(72228864), // SMINQV_VPZ_H
6204 UINT64_C(76423168), // SMINQV_VPZ_S
6205 UINT64_C(67772416), // SMINV_VPZ_B
6206 UINT64_C(80355328), // SMINV_VPZ_D
6207 UINT64_C(71966720), // SMINV_VPZ_H
6208 UINT64_C(76161024), // SMINV_VPZ_S
6209 UINT64_C(1311877120), // SMINVv16i8v
6210 UINT64_C(242329600), // SMINVv4i16v
6211 UINT64_C(1320265728), // SMINVv4i32v
6212 UINT64_C(1316071424), // SMINVv8i16v
6213 UINT64_C(238135296), // SMINVv8i8v
6214 UINT64_C(298319872), // SMINWri
6215 UINT64_C(448817152), // SMINWrr
6216 UINT64_C(2445803520), // SMINXri
6217 UINT64_C(2596300800), // SMINXrr
6218 UINT64_C(3240144928), // SMIN_VG2_2Z2Z_B
6219 UINT64_C(3252727840), // SMIN_VG2_2Z2Z_D
6220 UINT64_C(3244339232), // SMIN_VG2_2Z2Z_H
6221 UINT64_C(3248533536), // SMIN_VG2_2Z2Z_S
6222 UINT64_C(3240140832), // SMIN_VG2_2ZZ_B
6223 UINT64_C(3252723744), // SMIN_VG2_2ZZ_D
6224 UINT64_C(3244335136), // SMIN_VG2_2ZZ_H
6225 UINT64_C(3248529440), // SMIN_VG2_2ZZ_S
6226 UINT64_C(3240146976), // SMIN_VG4_4Z4Z_B
6227 UINT64_C(3252729888), // SMIN_VG4_4Z4Z_D
6228 UINT64_C(3244341280), // SMIN_VG4_4Z4Z_H
6229 UINT64_C(3248535584), // SMIN_VG4_4Z4Z_S
6230 UINT64_C(3240142880), // SMIN_VG4_4ZZ_B
6231 UINT64_C(3252725792), // SMIN_VG4_4ZZ_D
6232 UINT64_C(3244337184), // SMIN_VG4_4ZZ_H
6233 UINT64_C(3248531488), // SMIN_VG4_4ZZ_S
6234 UINT64_C(623558656), // SMIN_ZI_B
6235 UINT64_C(636141568), // SMIN_ZI_D
6236 UINT64_C(627752960), // SMIN_ZI_H
6237 UINT64_C(631947264), // SMIN_ZI_S
6238 UINT64_C(67764224), // SMIN_ZPmZ_B
6239 UINT64_C(80347136), // SMIN_ZPmZ_D
6240 UINT64_C(71958528), // SMIN_ZPmZ_H
6241 UINT64_C(76152832), // SMIN_ZPmZ_S
6242 UINT64_C(1310747648), // SMINv16i8
6243 UINT64_C(245394432), // SMINv2i32
6244 UINT64_C(241200128), // SMINv4i16
6245 UINT64_C(1319136256), // SMINv4i32
6246 UINT64_C(1314941952), // SMINv8i16
6247 UINT64_C(237005824), // SMINv8i8
6248 UINT64_C(1155563520), // SMLALB_ZZZI_D
6249 UINT64_C(1151369216), // SMLALB_ZZZI_S
6250 UINT64_C(1153449984), // SMLALB_ZZZ_D
6251 UINT64_C(1145061376), // SMLALB_ZZZ_H
6252 UINT64_C(1149255680), // SMLALB_ZZZ_S
6253 UINT64_C(3238002688), // SMLALL_MZZI_BtoS
6254 UINT64_C(3246391296), // SMLALL_MZZI_HtoD
6255 UINT64_C(3240100864), // SMLALL_MZZ_BtoS
6256 UINT64_C(3244295168), // SMLALL_MZZ_HtoD
6257 UINT64_C(3248488448), // SMLALL_VG2_M2Z2Z_BtoS
6258 UINT64_C(3252682752), // SMLALL_VG2_M2Z2Z_HtoD
6259 UINT64_C(3239051264), // SMLALL_VG2_M2ZZI_BtoS
6260 UINT64_C(3247439872), // SMLALL_VG2_M2ZZI_HtoD
6261 UINT64_C(3240099840), // SMLALL_VG2_M2ZZ_BtoS
6262 UINT64_C(3244294144), // SMLALL_VG2_M2ZZ_HtoD
6263 UINT64_C(3248553984), // SMLALL_VG4_M4Z4Z_BtoS
6264 UINT64_C(3252748288), // SMLALL_VG4_M4Z4Z_HtoD
6265 UINT64_C(3239084032), // SMLALL_VG4_M4ZZI_BtoS
6266 UINT64_C(3247472640), // SMLALL_VG4_M4ZZI_HtoD
6267 UINT64_C(3241148416), // SMLALL_VG4_M4ZZ_BtoS
6268 UINT64_C(3245342720), // SMLALL_VG4_M4ZZ_HtoD
6269 UINT64_C(1155564544), // SMLALT_ZZZI_D
6270 UINT64_C(1151370240), // SMLALT_ZZZI_S
6271 UINT64_C(1153451008), // SMLALT_ZZZ_D
6272 UINT64_C(1145062400), // SMLALT_ZZZ_H
6273 UINT64_C(1149256704), // SMLALT_ZZZ_S
6274 UINT64_C(3250589696), // SMLAL_MZZI_HtoS
6275 UINT64_C(3244297216), // SMLAL_MZZ_HtoS
6276 UINT64_C(3252684800), // SMLAL_VG2_M2Z2Z_HtoS
6277 UINT64_C(3251638272), // SMLAL_VG2_M2ZZI_S
6278 UINT64_C(3244296192), // SMLAL_VG2_M2ZZ_HtoS
6279 UINT64_C(3252750336), // SMLAL_VG4_M4Z4Z_HtoS
6280 UINT64_C(3251671040), // SMLAL_VG4_M4ZZI_HtoS
6281 UINT64_C(3245344768), // SMLAL_VG4_M4ZZ_HtoS
6282 UINT64_C(1310752768), // SMLALv16i8_v8i16
6283 UINT64_C(260055040), // SMLALv2i32_indexed
6284 UINT64_C(245399552), // SMLALv2i32_v2i64
6285 UINT64_C(255860736), // SMLALv4i16_indexed
6286 UINT64_C(241205248), // SMLALv4i16_v4i32
6287 UINT64_C(1333796864), // SMLALv4i32_indexed
6288 UINT64_C(1319141376), // SMLALv4i32_v2i64
6289 UINT64_C(1329602560), // SMLALv8i16_indexed
6290 UINT64_C(1314947072), // SMLALv8i16_v4i32
6291 UINT64_C(237010944), // SMLALv8i8_v8i16
6292 UINT64_C(1155571712), // SMLSLB_ZZZI_D
6293 UINT64_C(1151377408), // SMLSLB_ZZZI_S
6294 UINT64_C(1153454080), // SMLSLB_ZZZ_D
6295 UINT64_C(1145065472), // SMLSLB_ZZZ_H
6296 UINT64_C(1149259776), // SMLSLB_ZZZ_S
6297 UINT64_C(3238002696), // SMLSLL_MZZI_BtoS
6298 UINT64_C(3246391304), // SMLSLL_MZZI_HtoD
6299 UINT64_C(3240100872), // SMLSLL_MZZ_BtoS
6300 UINT64_C(3244295176), // SMLSLL_MZZ_HtoD
6301 UINT64_C(3248488456), // SMLSLL_VG2_M2Z2Z_BtoS
6302 UINT64_C(3252682760), // SMLSLL_VG2_M2Z2Z_HtoD
6303 UINT64_C(3239051272), // SMLSLL_VG2_M2ZZI_BtoS
6304 UINT64_C(3247439880), // SMLSLL_VG2_M2ZZI_HtoD
6305 UINT64_C(3240099848), // SMLSLL_VG2_M2ZZ_BtoS
6306 UINT64_C(3244294152), // SMLSLL_VG2_M2ZZ_HtoD
6307 UINT64_C(3248553992), // SMLSLL_VG4_M4Z4Z_BtoS
6308 UINT64_C(3252748296), // SMLSLL_VG4_M4Z4Z_HtoD
6309 UINT64_C(3239084040), // SMLSLL_VG4_M4ZZI_BtoS
6310 UINT64_C(3247472648), // SMLSLL_VG4_M4ZZI_HtoD
6311 UINT64_C(3241148424), // SMLSLL_VG4_M4ZZ_BtoS
6312 UINT64_C(3245342728), // SMLSLL_VG4_M4ZZ_HtoD
6313 UINT64_C(1155572736), // SMLSLT_ZZZI_D
6314 UINT64_C(1151378432), // SMLSLT_ZZZI_S
6315 UINT64_C(1153455104), // SMLSLT_ZZZ_D
6316 UINT64_C(1145066496), // SMLSLT_ZZZ_H
6317 UINT64_C(1149260800), // SMLSLT_ZZZ_S
6318 UINT64_C(3250589704), // SMLSL_MZZI_HtoS
6319 UINT64_C(3244297224), // SMLSL_MZZ_HtoS
6320 UINT64_C(3252684808), // SMLSL_VG2_M2Z2Z_HtoS
6321 UINT64_C(3251638280), // SMLSL_VG2_M2ZZI_S
6322 UINT64_C(3244296200), // SMLSL_VG2_M2ZZ_HtoS
6323 UINT64_C(3252750344), // SMLSL_VG4_M4Z4Z_HtoS
6324 UINT64_C(3251671048), // SMLSL_VG4_M4ZZI_HtoS
6325 UINT64_C(3245344776), // SMLSL_VG4_M4ZZ_HtoS
6326 UINT64_C(1310760960), // SMLSLv16i8_v8i16
6327 UINT64_C(260071424), // SMLSLv2i32_indexed
6328 UINT64_C(245407744), // SMLSLv2i32_v2i64
6329 UINT64_C(255877120), // SMLSLv4i16_indexed
6330 UINT64_C(241213440), // SMLSLv4i16_v4i32
6331 UINT64_C(1333813248), // SMLSLv4i32_indexed
6332 UINT64_C(1319149568), // SMLSLv4i32_v2i64
6333 UINT64_C(1329618944), // SMLSLv8i16_indexed
6334 UINT64_C(1314955264), // SMLSLv8i16_v4i32
6335 UINT64_C(237019136), // SMLSLv8i8_v8i16
6336 UINT64_C(1317053440), // SMMLA
6337 UINT64_C(1157666816), // SMMLA_ZZZ
6338 UINT64_C(2148565504), // SMOP4A_M2Z2Z_BToS
6339 UINT64_C(2148565512), // SMOP4A_M2Z2Z_HToS
6340 UINT64_C(2697986568), // SMOP4A_M2Z2Z_HtoD
6341 UINT64_C(2147516928), // SMOP4A_M2ZZ_BToS
6342 UINT64_C(2147516936), // SMOP4A_M2ZZ_HToS
6343 UINT64_C(2696937992), // SMOP4A_M2ZZ_HtoD
6344 UINT64_C(2148564992), // SMOP4A_MZ2Z_BToS
6345 UINT64_C(2148565000), // SMOP4A_MZ2Z_HToS
6346 UINT64_C(2697986056), // SMOP4A_MZ2Z_HtoD
6347 UINT64_C(2147516416), // SMOP4A_MZZ_BToS
6348 UINT64_C(2147516424), // SMOP4A_MZZ_HToS
6349 UINT64_C(2696937480), // SMOP4A_MZZ_HtoD
6350 UINT64_C(2148565520), // SMOP4S_M2Z2Z_BToS
6351 UINT64_C(2148565528), // SMOP4S_M2Z2Z_HToS
6352 UINT64_C(2697986584), // SMOP4S_M2Z2Z_HtoD
6353 UINT64_C(2147516944), // SMOP4S_M2ZZ_BToS
6354 UINT64_C(2147516952), // SMOP4S_M2ZZ_HToS
6355 UINT64_C(2696938008), // SMOP4S_M2ZZ_HtoD
6356 UINT64_C(2148565008), // SMOP4S_MZ2Z_BToS
6357 UINT64_C(2148565016), // SMOP4S_MZ2Z_HToS
6358 UINT64_C(2697986072), // SMOP4S_MZ2Z_HtoD
6359 UINT64_C(2147516432), // SMOP4S_MZZ_BToS
6360 UINT64_C(2147516440), // SMOP4S_MZZ_HToS
6361 UINT64_C(2696937496), // SMOP4S_MZZ_HtoD
6362 UINT64_C(2696937472), // SMOPA_MPPZZ_D
6363 UINT64_C(2692743176), // SMOPA_MPPZZ_HtoS
6364 UINT64_C(2692743168), // SMOPA_MPPZZ_S
6365 UINT64_C(2696937488), // SMOPS_MPPZZ_D
6366 UINT64_C(2692743192), // SMOPS_MPPZZ_HtoS
6367 UINT64_C(2692743184), // SMOPS_MPPZZ_S
6368 UINT64_C(235023360), // SMOVvi16to32
6369 UINT64_C(235023360), // SMOVvi16to32_idx0
6370 UINT64_C(1308765184), // SMOVvi16to64
6371 UINT64_C(1308765184), // SMOVvi16to64_idx0
6372 UINT64_C(1308896256), // SMOVvi32to64
6373 UINT64_C(1308896256), // SMOVvi32to64_idx0
6374 UINT64_C(234957824), // SMOVvi8to32
6375 UINT64_C(234957824), // SMOVvi8to32_idx0
6376 UINT64_C(1308699648), // SMOVvi8to64
6377 UINT64_C(1308699648), // SMOVvi8to64_idx0
6378 UINT64_C(2602598400), // SMSUBLrrr
6379 UINT64_C(68288512), // SMULH_ZPmZ_B
6380 UINT64_C(80871424), // SMULH_ZPmZ_D
6381 UINT64_C(72482816), // SMULH_ZPmZ_H
6382 UINT64_C(76677120), // SMULH_ZPmZ_S
6383 UINT64_C(69232640), // SMULH_ZZZ_B
6384 UINT64_C(81815552), // SMULH_ZZZ_D
6385 UINT64_C(73426944), // SMULH_ZZZ_H
6386 UINT64_C(77621248), // SMULH_ZZZ_S
6387 UINT64_C(2604694528), // SMULHrr
6388 UINT64_C(1155579904), // SMULLB_ZZZI_D
6389 UINT64_C(1151385600), // SMULLB_ZZZI_S
6390 UINT64_C(1170239488), // SMULLB_ZZZ_D
6391 UINT64_C(1161850880), // SMULLB_ZZZ_H
6392 UINT64_C(1166045184), // SMULLB_ZZZ_S
6393 UINT64_C(1155580928), // SMULLT_ZZZI_D
6394 UINT64_C(1151386624), // SMULLT_ZZZI_S
6395 UINT64_C(1170240512), // SMULLT_ZZZ_D
6396 UINT64_C(1161851904), // SMULLT_ZZZ_H
6397 UINT64_C(1166046208), // SMULLT_ZZZ_S
6398 UINT64_C(1310769152), // SMULLv16i8_v8i16
6399 UINT64_C(260087808), // SMULLv2i32_indexed
6400 UINT64_C(245415936), // SMULLv2i32_v2i64
6401 UINT64_C(255893504), // SMULLv4i16_indexed
6402 UINT64_C(241221632), // SMULLv4i16_v4i32
6403 UINT64_C(1333829632), // SMULLv4i32_indexed
6404 UINT64_C(1319157760), // SMULLv4i32_v2i64
6405 UINT64_C(1329635328), // SMULLv8i16_indexed
6406 UINT64_C(1314963456), // SMULLv8i16_v4i32
6407 UINT64_C(237027328), // SMULLv8i8_v8i16
6408 UINT64_C(86867968), // SPLICE_ZPZZ_B
6409 UINT64_C(99450880), // SPLICE_ZPZZ_D
6410 UINT64_C(91062272), // SPLICE_ZPZZ_H
6411 UINT64_C(95256576), // SPLICE_ZPZZ_S
6412 UINT64_C(86802432), // SPLICE_ZPZ_B
6413 UINT64_C(99385344), // SPLICE_ZPZ_D
6414 UINT64_C(90996736), // SPLICE_ZPZ_H
6415 UINT64_C(95191040), // SPLICE_ZPZ_S
6416 UINT64_C(1141415936), // SQABS_ZPmZ_B
6417 UINT64_C(1153998848), // SQABS_ZPmZ_D
6418 UINT64_C(1145610240), // SQABS_ZPmZ_H
6419 UINT64_C(1149804544), // SQABS_ZPmZ_S
6420 UINT64_C(1141547008), // SQABS_ZPzZ_B
6421 UINT64_C(1154129920), // SQABS_ZPzZ_D
6422 UINT64_C(1145741312), // SQABS_ZPzZ_H
6423 UINT64_C(1149935616), // SQABS_ZPzZ_S
6424 UINT64_C(1310750720), // SQABSv16i8
6425 UINT64_C(1583380480), // SQABSv1i16
6426 UINT64_C(1587574784), // SQABSv1i32
6427 UINT64_C(1591769088), // SQABSv1i64
6428 UINT64_C(1579186176), // SQABSv1i8
6429 UINT64_C(245397504), // SQABSv2i32
6430 UINT64_C(1323333632), // SQABSv2i64
6431 UINT64_C(241203200), // SQABSv4i16
6432 UINT64_C(1319139328), // SQABSv4i32
6433 UINT64_C(1314945024), // SQABSv8i16
6434 UINT64_C(237008896), // SQABSv8i8
6435 UINT64_C(623165440), // SQADD_ZI_B
6436 UINT64_C(635748352), // SQADD_ZI_D
6437 UINT64_C(627359744), // SQADD_ZI_H
6438 UINT64_C(631554048), // SQADD_ZI_S
6439 UINT64_C(1142456320), // SQADD_ZPmZ_B
6440 UINT64_C(1155039232), // SQADD_ZPmZ_D
6441 UINT64_C(1146650624), // SQADD_ZPmZ_H
6442 UINT64_C(1150844928), // SQADD_ZPmZ_S
6443 UINT64_C(69210112), // SQADD_ZZZ_B
6444 UINT64_C(81793024), // SQADD_ZZZ_D
6445 UINT64_C(73404416), // SQADD_ZZZ_H
6446 UINT64_C(77598720), // SQADD_ZZZ_S
6447 UINT64_C(1310723072), // SQADDv16i8
6448 UINT64_C(1583352832), // SQADDv1i16
6449 UINT64_C(1587547136), // SQADDv1i32
6450 UINT64_C(1591741440), // SQADDv1i64
6451 UINT64_C(1579158528), // SQADDv1i8
6452 UINT64_C(245369856), // SQADDv2i32
6453 UINT64_C(1323305984), // SQADDv2i64
6454 UINT64_C(241175552), // SQADDv4i16
6455 UINT64_C(1319111680), // SQADDv4i32
6456 UINT64_C(1314917376), // SQADDv8i16
6457 UINT64_C(236981248), // SQADDv8i8
6458 UINT64_C(1157748736), // SQCADD_ZZI_B
6459 UINT64_C(1170331648), // SQCADD_ZZI_D
6460 UINT64_C(1161943040), // SQCADD_ZZI_H
6461 UINT64_C(1166137344), // SQCADD_ZZI_S
6462 UINT64_C(1160855552), // SQCVTN_Z2Z_StoH
6463 UINT64_C(3249791040), // SQCVTN_Z4Z_DtoH
6464 UINT64_C(3241402432), // SQCVTN_Z4Z_StoB
6465 UINT64_C(1160859648), // SQCVTUN_Z2Z_StoH
6466 UINT64_C(3253985344), // SQCVTUN_Z4Z_DtoH
6467 UINT64_C(3245596736), // SQCVTUN_Z4Z_StoB
6468 UINT64_C(3244548096), // SQCVTU_Z2Z_StoH
6469 UINT64_C(3253985280), // SQCVTU_Z4Z_DtoH
6470 UINT64_C(3245596672), // SQCVTU_Z4Z_StoB
6471 UINT64_C(3240353792), // SQCVT_Z2Z_StoH
6472 UINT64_C(3249790976), // SQCVT_Z4Z_DtoH
6473 UINT64_C(3241402368), // SQCVT_Z4Z_StoB
6474 UINT64_C(70318080), // SQDECB_XPiI
6475 UINT64_C(69269504), // SQDECB_XPiWdI
6476 UINT64_C(82900992), // SQDECD_XPiI
6477 UINT64_C(81852416), // SQDECD_XPiWdI
6478 UINT64_C(81840128), // SQDECD_ZPiI
6479 UINT64_C(74512384), // SQDECH_XPiI
6480 UINT64_C(73463808), // SQDECH_XPiWdI
6481 UINT64_C(73451520), // SQDECH_ZPiI
6482 UINT64_C(623544320), // SQDECP_XPWd_B
6483 UINT64_C(636127232), // SQDECP_XPWd_D
6484 UINT64_C(627738624), // SQDECP_XPWd_H
6485 UINT64_C(631932928), // SQDECP_XPWd_S
6486 UINT64_C(623545344), // SQDECP_XP_B
6487 UINT64_C(636128256), // SQDECP_XP_D
6488 UINT64_C(627739648), // SQDECP_XP_H
6489 UINT64_C(631933952), // SQDECP_XP_S
6490 UINT64_C(636125184), // SQDECP_ZP_D
6491 UINT64_C(627736576), // SQDECP_ZP_H
6492 UINT64_C(631930880), // SQDECP_ZP_S
6493 UINT64_C(78706688), // SQDECW_XPiI
6494 UINT64_C(77658112), // SQDECW_XPiWdI
6495 UINT64_C(77645824), // SQDECW_ZPiI
6496 UINT64_C(1153435648), // SQDMLALBT_ZZZ_D
6497 UINT64_C(1145047040), // SQDMLALBT_ZZZ_H
6498 UINT64_C(1149241344), // SQDMLALBT_ZZZ_S
6499 UINT64_C(1155538944), // SQDMLALB_ZZZI_D
6500 UINT64_C(1151344640), // SQDMLALB_ZZZI_S
6501 UINT64_C(1153458176), // SQDMLALB_ZZZ_D
6502 UINT64_C(1145069568), // SQDMLALB_ZZZ_H
6503 UINT64_C(1149263872), // SQDMLALB_ZZZ_S
6504 UINT64_C(1155539968), // SQDMLALT_ZZZI_D
6505 UINT64_C(1151345664), // SQDMLALT_ZZZI_S
6506 UINT64_C(1153459200), // SQDMLALT_ZZZ_D
6507 UINT64_C(1145070592), // SQDMLALT_ZZZ_H
6508 UINT64_C(1149264896), // SQDMLALT_ZZZ_S
6509 UINT64_C(1583386624), // SQDMLALi16
6510 UINT64_C(1587580928), // SQDMLALi32
6511 UINT64_C(1598042112), // SQDMLALv1i32_indexed
6512 UINT64_C(1602236416), // SQDMLALv1i64_indexed
6513 UINT64_C(260059136), // SQDMLALv2i32_indexed
6514 UINT64_C(245403648), // SQDMLALv2i32_v2i64
6515 UINT64_C(255864832), // SQDMLALv4i16_indexed
6516 UINT64_C(241209344), // SQDMLALv4i16_v4i32
6517 UINT64_C(1333800960), // SQDMLALv4i32_indexed
6518 UINT64_C(1319145472), // SQDMLALv4i32_v2i64
6519 UINT64_C(1329606656), // SQDMLALv8i16_indexed
6520 UINT64_C(1314951168), // SQDMLALv8i16_v4i32
6521 UINT64_C(1153436672), // SQDMLSLBT_ZZZ_D
6522 UINT64_C(1145048064), // SQDMLSLBT_ZZZ_H
6523 UINT64_C(1149242368), // SQDMLSLBT_ZZZ_S
6524 UINT64_C(1155543040), // SQDMLSLB_ZZZI_D
6525 UINT64_C(1151348736), // SQDMLSLB_ZZZI_S
6526 UINT64_C(1153460224), // SQDMLSLB_ZZZ_D
6527 UINT64_C(1145071616), // SQDMLSLB_ZZZ_H
6528 UINT64_C(1149265920), // SQDMLSLB_ZZZ_S
6529 UINT64_C(1155544064), // SQDMLSLT_ZZZI_D
6530 UINT64_C(1151349760), // SQDMLSLT_ZZZI_S
6531 UINT64_C(1153461248), // SQDMLSLT_ZZZ_D
6532 UINT64_C(1145072640), // SQDMLSLT_ZZZ_H
6533 UINT64_C(1149266944), // SQDMLSLT_ZZZ_S
6534 UINT64_C(1583394816), // SQDMLSLi16
6535 UINT64_C(1587589120), // SQDMLSLi32
6536 UINT64_C(1598058496), // SQDMLSLv1i32_indexed
6537 UINT64_C(1602252800), // SQDMLSLv1i64_indexed
6538 UINT64_C(260075520), // SQDMLSLv2i32_indexed
6539 UINT64_C(245411840), // SQDMLSLv2i32_v2i64
6540 UINT64_C(255881216), // SQDMLSLv4i16_indexed
6541 UINT64_C(241217536), // SQDMLSLv4i16_v4i32
6542 UINT64_C(1333817344), // SQDMLSLv4i32_indexed
6543 UINT64_C(1319153664), // SQDMLSLv4i32_v2i64
6544 UINT64_C(1329623040), // SQDMLSLv8i16_indexed
6545 UINT64_C(1314959360), // SQDMLSLv8i16_v4i32
6546 UINT64_C(3240145920), // SQDMULH_VG2_2Z2Z_B
6547 UINT64_C(3252728832), // SQDMULH_VG2_2Z2Z_D
6548 UINT64_C(3244340224), // SQDMULH_VG2_2Z2Z_H
6549 UINT64_C(3248534528), // SQDMULH_VG2_2Z2Z_S
6550 UINT64_C(3240141824), // SQDMULH_VG2_2ZZ_B
6551 UINT64_C(3252724736), // SQDMULH_VG2_2ZZ_D
6552 UINT64_C(3244336128), // SQDMULH_VG2_2ZZ_H
6553 UINT64_C(3248530432), // SQDMULH_VG2_2ZZ_S
6554 UINT64_C(3240147968), // SQDMULH_VG4_4Z4Z_B
6555 UINT64_C(3252730880), // SQDMULH_VG4_4Z4Z_D
6556 UINT64_C(3244342272), // SQDMULH_VG4_4Z4Z_H
6557 UINT64_C(3248536576), // SQDMULH_VG4_4Z4Z_S
6558 UINT64_C(3240143872), // SQDMULH_VG4_4ZZ_B
6559 UINT64_C(3252726784), // SQDMULH_VG4_4ZZ_D
6560 UINT64_C(3244338176), // SQDMULH_VG4_4ZZ_H
6561 UINT64_C(3248532480), // SQDMULH_VG4_4ZZ_S
6562 UINT64_C(1155592192), // SQDMULH_ZZZI_D
6563 UINT64_C(1143009280), // SQDMULH_ZZZI_H
6564 UINT64_C(1151397888), // SQDMULH_ZZZI_S
6565 UINT64_C(69234688), // SQDMULH_ZZZ_B
6566 UINT64_C(81817600), // SQDMULH_ZZZ_D
6567 UINT64_C(73428992), // SQDMULH_ZZZ_H
6568 UINT64_C(77623296), // SQDMULH_ZZZ_S
6569 UINT64_C(1583395840), // SQDMULHv1i16
6570 UINT64_C(1598078976), // SQDMULHv1i16_indexed
6571 UINT64_C(1587590144), // SQDMULHv1i32
6572 UINT64_C(1602273280), // SQDMULHv1i32_indexed
6573 UINT64_C(245412864), // SQDMULHv2i32
6574 UINT64_C(260096000), // SQDMULHv2i32_indexed
6575 UINT64_C(241218560), // SQDMULHv4i16
6576 UINT64_C(255901696), // SQDMULHv4i16_indexed
6577 UINT64_C(1319154688), // SQDMULHv4i32
6578 UINT64_C(1333837824), // SQDMULHv4i32_indexed
6579 UINT64_C(1314960384), // SQDMULHv8i16
6580 UINT64_C(1329643520), // SQDMULHv8i16_indexed
6581 UINT64_C(1155588096), // SQDMULLB_ZZZI_D
6582 UINT64_C(1151393792), // SQDMULLB_ZZZI_S
6583 UINT64_C(1170235392), // SQDMULLB_ZZZ_D
6584 UINT64_C(1161846784), // SQDMULLB_ZZZ_H
6585 UINT64_C(1166041088), // SQDMULLB_ZZZ_S
6586 UINT64_C(1155589120), // SQDMULLT_ZZZI_D
6587 UINT64_C(1151394816), // SQDMULLT_ZZZI_S
6588 UINT64_C(1170236416), // SQDMULLT_ZZZ_D
6589 UINT64_C(1161847808), // SQDMULLT_ZZZ_H
6590 UINT64_C(1166042112), // SQDMULLT_ZZZ_S
6591 UINT64_C(1583403008), // SQDMULLi16
6592 UINT64_C(1587597312), // SQDMULLi32
6593 UINT64_C(1598074880), // SQDMULLv1i32_indexed
6594 UINT64_C(1602269184), // SQDMULLv1i64_indexed
6595 UINT64_C(260091904), // SQDMULLv2i32_indexed
6596 UINT64_C(245420032), // SQDMULLv2i32_v2i64
6597 UINT64_C(255897600), // SQDMULLv4i16_indexed
6598 UINT64_C(241225728), // SQDMULLv4i16_v4i32
6599 UINT64_C(1333833728), // SQDMULLv4i32_indexed
6600 UINT64_C(1319161856), // SQDMULLv4i32_v2i64
6601 UINT64_C(1329639424), // SQDMULLv8i16_indexed
6602 UINT64_C(1314967552), // SQDMULLv8i16_v4i32
6603 UINT64_C(70316032), // SQINCB_XPiI
6604 UINT64_C(69267456), // SQINCB_XPiWdI
6605 UINT64_C(82898944), // SQINCD_XPiI
6606 UINT64_C(81850368), // SQINCD_XPiWdI
6607 UINT64_C(81838080), // SQINCD_ZPiI
6608 UINT64_C(74510336), // SQINCH_XPiI
6609 UINT64_C(73461760), // SQINCH_XPiWdI
6610 UINT64_C(73449472), // SQINCH_ZPiI
6611 UINT64_C(623413248), // SQINCP_XPWd_B
6612 UINT64_C(635996160), // SQINCP_XPWd_D
6613 UINT64_C(627607552), // SQINCP_XPWd_H
6614 UINT64_C(631801856), // SQINCP_XPWd_S
6615 UINT64_C(623414272), // SQINCP_XP_B
6616 UINT64_C(635997184), // SQINCP_XP_D
6617 UINT64_C(627608576), // SQINCP_XP_H
6618 UINT64_C(631802880), // SQINCP_XP_S
6619 UINT64_C(635994112), // SQINCP_ZP_D
6620 UINT64_C(627605504), // SQINCP_ZP_H
6621 UINT64_C(631799808), // SQINCP_ZP_S
6622 UINT64_C(78704640), // SQINCW_XPiI
6623 UINT64_C(77656064), // SQINCW_XPiWdI
6624 UINT64_C(77643776), // SQINCW_ZPiI
6625 UINT64_C(1141481472), // SQNEG_ZPmZ_B
6626 UINT64_C(1154064384), // SQNEG_ZPmZ_D
6627 UINT64_C(1145675776), // SQNEG_ZPmZ_H
6628 UINT64_C(1149870080), // SQNEG_ZPmZ_S
6629 UINT64_C(1141612544), // SQNEG_ZPzZ_B
6630 UINT64_C(1154195456), // SQNEG_ZPzZ_D
6631 UINT64_C(1145806848), // SQNEG_ZPzZ_H
6632 UINT64_C(1150001152), // SQNEG_ZPzZ_S
6633 UINT64_C(1847621632), // SQNEGv16i8
6634 UINT64_C(2120251392), // SQNEGv1i16
6635 UINT64_C(2124445696), // SQNEGv1i32
6636 UINT64_C(2128640000), // SQNEGv1i64
6637 UINT64_C(2116057088), // SQNEGv1i8
6638 UINT64_C(782268416), // SQNEGv2i32
6639 UINT64_C(1860204544), // SQNEGv2i64
6640 UINT64_C(778074112), // SQNEGv4i16
6641 UINT64_C(1856010240), // SQNEGv4i32
6642 UINT64_C(1851815936), // SQNEGv8i16
6643 UINT64_C(773879808), // SQNEGv8i8
6644 UINT64_C(1151365120), // SQRDCMLAH_ZZZI_H
6645 UINT64_C(1155559424), // SQRDCMLAH_ZZZI_S
6646 UINT64_C(1140862976), // SQRDCMLAH_ZZZ_B
6647 UINT64_C(1153445888), // SQRDCMLAH_ZZZ_D
6648 UINT64_C(1145057280), // SQRDCMLAH_ZZZ_H
6649 UINT64_C(1149251584), // SQRDCMLAH_ZZZ_S
6650 UINT64_C(1155534848), // SQRDMLAH_ZZZI_D
6651 UINT64_C(1142951936), // SQRDMLAH_ZZZI_H
6652 UINT64_C(1151340544), // SQRDMLAH_ZZZI_S
6653 UINT64_C(1140879360), // SQRDMLAH_ZZZ_B
6654 UINT64_C(1153462272), // SQRDMLAH_ZZZ_D
6655 UINT64_C(1145073664), // SQRDMLAH_ZZZ_H
6656 UINT64_C(1149267968), // SQRDMLAH_ZZZ_S
6657 UINT64_C(2118157312), // SQRDMLAHv1i16
6658 UINT64_C(2134953984), // SQRDMLAHv1i16_indexed
6659 UINT64_C(2122351616), // SQRDMLAHv1i32
6660 UINT64_C(2139148288), // SQRDMLAHv1i32_indexed
6661 UINT64_C(780174336), // SQRDMLAHv2i32
6662 UINT64_C(796971008), // SQRDMLAHv2i32_indexed
6663 UINT64_C(775980032), // SQRDMLAHv4i16
6664 UINT64_C(792776704), // SQRDMLAHv4i16_indexed
6665 UINT64_C(1853916160), // SQRDMLAHv4i32
6666 UINT64_C(1870712832), // SQRDMLAHv4i32_indexed
6667 UINT64_C(1849721856), // SQRDMLAHv8i16
6668 UINT64_C(1866518528), // SQRDMLAHv8i16_indexed
6669 UINT64_C(1155535872), // SQRDMLSH_ZZZI_D
6670 UINT64_C(1142952960), // SQRDMLSH_ZZZI_H
6671 UINT64_C(1151341568), // SQRDMLSH_ZZZI_S
6672 UINT64_C(1140880384), // SQRDMLSH_ZZZ_B
6673 UINT64_C(1153463296), // SQRDMLSH_ZZZ_D
6674 UINT64_C(1145074688), // SQRDMLSH_ZZZ_H
6675 UINT64_C(1149268992), // SQRDMLSH_ZZZ_S
6676 UINT64_C(2118159360), // SQRDMLSHv1i16
6677 UINT64_C(2134962176), // SQRDMLSHv1i16_indexed
6678 UINT64_C(2122353664), // SQRDMLSHv1i32
6679 UINT64_C(2139156480), // SQRDMLSHv1i32_indexed
6680 UINT64_C(780176384), // SQRDMLSHv2i32
6681 UINT64_C(796979200), // SQRDMLSHv2i32_indexed
6682 UINT64_C(775982080), // SQRDMLSHv4i16
6683 UINT64_C(792784896), // SQRDMLSHv4i16_indexed
6684 UINT64_C(1853918208), // SQRDMLSHv4i32
6685 UINT64_C(1870721024), // SQRDMLSHv4i32_indexed
6686 UINT64_C(1849723904), // SQRDMLSHv8i16
6687 UINT64_C(1866526720), // SQRDMLSHv8i16_indexed
6688 UINT64_C(1155593216), // SQRDMULH_ZZZI_D
6689 UINT64_C(1143010304), // SQRDMULH_ZZZI_H
6690 UINT64_C(1151398912), // SQRDMULH_ZZZI_S
6691 UINT64_C(69235712), // SQRDMULH_ZZZ_B
6692 UINT64_C(81818624), // SQRDMULH_ZZZ_D
6693 UINT64_C(73430016), // SQRDMULH_ZZZ_H
6694 UINT64_C(77624320), // SQRDMULH_ZZZ_S
6695 UINT64_C(2120266752), // SQRDMULHv1i16
6696 UINT64_C(1598083072), // SQRDMULHv1i16_indexed
6697 UINT64_C(2124461056), // SQRDMULHv1i32
6698 UINT64_C(1602277376), // SQRDMULHv1i32_indexed
6699 UINT64_C(782283776), // SQRDMULHv2i32
6700 UINT64_C(260100096), // SQRDMULHv2i32_indexed
6701 UINT64_C(778089472), // SQRDMULHv4i16
6702 UINT64_C(255905792), // SQRDMULHv4i16_indexed
6703 UINT64_C(1856025600), // SQRDMULHv4i32
6704 UINT64_C(1333841920), // SQRDMULHv4i32_indexed
6705 UINT64_C(1851831296), // SQRDMULHv8i16
6706 UINT64_C(1329647616), // SQRDMULHv8i16_indexed
6707 UINT64_C(1141800960), // SQRSHLR_ZPmZ_B
6708 UINT64_C(1154383872), // SQRSHLR_ZPmZ_D
6709 UINT64_C(1145995264), // SQRSHLR_ZPmZ_H
6710 UINT64_C(1150189568), // SQRSHLR_ZPmZ_S
6711 UINT64_C(1141538816), // SQRSHL_ZPmZ_B
6712 UINT64_C(1154121728), // SQRSHL_ZPmZ_D
6713 UINT64_C(1145733120), // SQRSHL_ZPmZ_H
6714 UINT64_C(1149927424), // SQRSHL_ZPmZ_S
6715 UINT64_C(1310743552), // SQRSHLv16i8
6716 UINT64_C(1583373312), // SQRSHLv1i16
6717 UINT64_C(1587567616), // SQRSHLv1i32
6718 UINT64_C(1591761920), // SQRSHLv1i64
6719 UINT64_C(1579179008), // SQRSHLv1i8
6720 UINT64_C(245390336), // SQRSHLv2i32
6721 UINT64_C(1323326464), // SQRSHLv2i64
6722 UINT64_C(241196032), // SQRSHLv4i16
6723 UINT64_C(1319132160), // SQRSHLv4i32
6724 UINT64_C(1314937856), // SQRSHLv8i16
6725 UINT64_C(237001728), // SQRSHLv8i8
6726 UINT64_C(1160259584), // SQRSHRNB_ZZI_B
6727 UINT64_C(1160783872), // SQRSHRNB_ZZI_H
6728 UINT64_C(1163929600), // SQRSHRNB_ZZI_S
6729 UINT64_C(1160260608), // SQRSHRNT_ZZI_B
6730 UINT64_C(1160784896), // SQRSHRNT_ZZI_H
6731 UINT64_C(1163930624), // SQRSHRNT_ZZI_S
6732 UINT64_C(3244350464), // SQRSHRN_VG4_Z4ZI_B
6733 UINT64_C(3248544768), // SQRSHRN_VG4_Z4ZI_H
6734 UINT64_C(1169172480), // SQRSHRN_Z2ZI_StoH
6735 UINT64_C(1594399744), // SQRSHRNb
6736 UINT64_C(1594924032), // SQRSHRNh
6737 UINT64_C(1595972608), // SQRSHRNs
6738 UINT64_C(1325964288), // SQRSHRNv16i8_shift
6739 UINT64_C(253795328), // SQRSHRNv2i32_shift
6740 UINT64_C(252746752), // SQRSHRNv4i16_shift
6741 UINT64_C(1327537152), // SQRSHRNv4i32_shift
6742 UINT64_C(1326488576), // SQRSHRNv8i16_shift
6743 UINT64_C(252222464), // SQRSHRNv8i8_shift
6744 UINT64_C(1160251392), // SQRSHRUNB_ZZI_B
6745 UINT64_C(1160775680), // SQRSHRUNB_ZZI_H
6746 UINT64_C(1163921408), // SQRSHRUNB_ZZI_S
6747 UINT64_C(1160252416), // SQRSHRUNT_ZZI_B
6748 UINT64_C(1160776704), // SQRSHRUNT_ZZI_H
6749 UINT64_C(1163922432), // SQRSHRUNT_ZZI_S
6750 UINT64_C(3244350528), // SQRSHRUN_VG4_Z4ZI_B
6751 UINT64_C(3248544832), // SQRSHRUN_VG4_Z4ZI_H
6752 UINT64_C(1169164288), // SQRSHRUN_Z2ZI_StoH
6753 UINT64_C(2131266560), // SQRSHRUNb
6754 UINT64_C(2131790848), // SQRSHRUNh
6755 UINT64_C(2132839424), // SQRSHRUNs
6756 UINT64_C(1862831104), // SQRSHRUNv16i8_shift
6757 UINT64_C(790662144), // SQRSHRUNv2i32_shift
6758 UINT64_C(789613568), // SQRSHRUNv4i16_shift
6759 UINT64_C(1864403968), // SQRSHRUNv4i32_shift
6760 UINT64_C(1863355392), // SQRSHRUNv8i16_shift
6761 UINT64_C(789089280), // SQRSHRUNv8i8_shift
6762 UINT64_C(3253785600), // SQRSHRU_VG2_Z2ZI_H
6763 UINT64_C(3244349504), // SQRSHRU_VG4_Z4ZI_B
6764 UINT64_C(3248543808), // SQRSHRU_VG4_Z4ZI_H
6765 UINT64_C(3252737024), // SQRSHR_VG2_Z2ZI_H
6766 UINT64_C(3244349440), // SQRSHR_VG4_Z4ZI_B
6767 UINT64_C(3248543744), // SQRSHR_VG4_Z4ZI_H
6768 UINT64_C(1141669888), // SQSHLR_ZPmZ_B
6769 UINT64_C(1154252800), // SQSHLR_ZPmZ_D
6770 UINT64_C(1145864192), // SQSHLR_ZPmZ_H
6771 UINT64_C(1150058496), // SQSHLR_ZPmZ_S
6772 UINT64_C(68124928), // SQSHLU_ZPmI_B
6773 UINT64_C(76513280), // SQSHLU_ZPmI_D
6774 UINT64_C(68125184), // SQSHLU_ZPmI_H
6775 UINT64_C(72318976), // SQSHLU_ZPmI_S
6776 UINT64_C(2131256320), // SQSHLUb
6777 UINT64_C(2134926336), // SQSHLUd
6778 UINT64_C(2131780608), // SQSHLUh
6779 UINT64_C(2132829184), // SQSHLUs
6780 UINT64_C(1862820864), // SQSHLUv16i8_shift
6781 UINT64_C(790651904), // SQSHLUv2i32_shift
6782 UINT64_C(1866490880), // SQSHLUv2i64_shift
6783 UINT64_C(789603328), // SQSHLUv4i16_shift
6784 UINT64_C(1864393728), // SQSHLUv4i32_shift
6785 UINT64_C(1863345152), // SQSHLUv8i16_shift
6786 UINT64_C(789079040), // SQSHLUv8i8_shift
6787 UINT64_C(67535104), // SQSHL_ZPmI_B
6788 UINT64_C(75923456), // SQSHL_ZPmI_D
6789 UINT64_C(67535360), // SQSHL_ZPmI_H
6790 UINT64_C(71729152), // SQSHL_ZPmI_S
6791 UINT64_C(1141407744), // SQSHL_ZPmZ_B
6792 UINT64_C(1153990656), // SQSHL_ZPmZ_D
6793 UINT64_C(1145602048), // SQSHL_ZPmZ_H
6794 UINT64_C(1149796352), // SQSHL_ZPmZ_S
6795 UINT64_C(1594389504), // SQSHLb
6796 UINT64_C(1598059520), // SQSHLd
6797 UINT64_C(1594913792), // SQSHLh
6798 UINT64_C(1595962368), // SQSHLs
6799 UINT64_C(1310739456), // SQSHLv16i8
6800 UINT64_C(1325954048), // SQSHLv16i8_shift
6801 UINT64_C(1583369216), // SQSHLv1i16
6802 UINT64_C(1587563520), // SQSHLv1i32
6803 UINT64_C(1591757824), // SQSHLv1i64
6804 UINT64_C(1579174912), // SQSHLv1i8
6805 UINT64_C(245386240), // SQSHLv2i32
6806 UINT64_C(253785088), // SQSHLv2i32_shift
6807 UINT64_C(1323322368), // SQSHLv2i64
6808 UINT64_C(1329624064), // SQSHLv2i64_shift
6809 UINT64_C(241191936), // SQSHLv4i16
6810 UINT64_C(252736512), // SQSHLv4i16_shift
6811 UINT64_C(1319128064), // SQSHLv4i32
6812 UINT64_C(1327526912), // SQSHLv4i32_shift
6813 UINT64_C(1314933760), // SQSHLv8i16
6814 UINT64_C(1326478336), // SQSHLv8i16_shift
6815 UINT64_C(236997632), // SQSHLv8i8
6816 UINT64_C(252212224), // SQSHLv8i8_shift
6817 UINT64_C(1160257536), // SQSHRNB_ZZI_B
6818 UINT64_C(1160781824), // SQSHRNB_ZZI_H
6819 UINT64_C(1163927552), // SQSHRNB_ZZI_S
6820 UINT64_C(1160258560), // SQSHRNT_ZZI_B
6821 UINT64_C(1160782848), // SQSHRNT_ZZI_H
6822 UINT64_C(1163928576), // SQSHRNT_ZZI_S
6823 UINT64_C(1594397696), // SQSHRNb
6824 UINT64_C(1594921984), // SQSHRNh
6825 UINT64_C(1595970560), // SQSHRNs
6826 UINT64_C(1325962240), // SQSHRNv16i8_shift
6827 UINT64_C(253793280), // SQSHRNv2i32_shift
6828 UINT64_C(252744704), // SQSHRNv4i16_shift
6829 UINT64_C(1327535104), // SQSHRNv4i32_shift
6830 UINT64_C(1326486528), // SQSHRNv8i16_shift
6831 UINT64_C(252220416), // SQSHRNv8i8_shift
6832 UINT64_C(1160249344), // SQSHRUNB_ZZI_B
6833 UINT64_C(1160773632), // SQSHRUNB_ZZI_H
6834 UINT64_C(1163919360), // SQSHRUNB_ZZI_S
6835 UINT64_C(1160250368), // SQSHRUNT_ZZI_B
6836 UINT64_C(1160774656), // SQSHRUNT_ZZI_H
6837 UINT64_C(1163920384), // SQSHRUNT_ZZI_S
6838 UINT64_C(2131264512), // SQSHRUNb
6839 UINT64_C(2131788800), // SQSHRUNh
6840 UINT64_C(2132837376), // SQSHRUNs
6841 UINT64_C(1862829056), // SQSHRUNv16i8_shift
6842 UINT64_C(790660096), // SQSHRUNv2i32_shift
6843 UINT64_C(789611520), // SQSHRUNv4i16_shift
6844 UINT64_C(1864401920), // SQSHRUNv4i32_shift
6845 UINT64_C(1863353344), // SQSHRUNv8i16_shift
6846 UINT64_C(789087232), // SQSHRUNv8i8_shift
6847 UINT64_C(1142849536), // SQSUBR_ZPmZ_B
6848 UINT64_C(1155432448), // SQSUBR_ZPmZ_D
6849 UINT64_C(1147043840), // SQSUBR_ZPmZ_H
6850 UINT64_C(1151238144), // SQSUBR_ZPmZ_S
6851 UINT64_C(623296512), // SQSUB_ZI_B
6852 UINT64_C(635879424), // SQSUB_ZI_D
6853 UINT64_C(627490816), // SQSUB_ZI_H
6854 UINT64_C(631685120), // SQSUB_ZI_S
6855 UINT64_C(1142587392), // SQSUB_ZPmZ_B
6856 UINT64_C(1155170304), // SQSUB_ZPmZ_D
6857 UINT64_C(1146781696), // SQSUB_ZPmZ_H
6858 UINT64_C(1150976000), // SQSUB_ZPmZ_S
6859 UINT64_C(69212160), // SQSUB_ZZZ_B
6860 UINT64_C(81795072), // SQSUB_ZZZ_D
6861 UINT64_C(73406464), // SQSUB_ZZZ_H
6862 UINT64_C(77600768), // SQSUB_ZZZ_S
6863 UINT64_C(1310731264), // SQSUBv16i8
6864 UINT64_C(1583361024), // SQSUBv1i16
6865 UINT64_C(1587555328), // SQSUBv1i32
6866 UINT64_C(1591749632), // SQSUBv1i64
6867 UINT64_C(1579166720), // SQSUBv1i8
6868 UINT64_C(245378048), // SQSUBv2i32
6869 UINT64_C(1323314176), // SQSUBv2i64
6870 UINT64_C(241183744), // SQSUBv4i16
6871 UINT64_C(1319119872), // SQSUBv4i32
6872 UINT64_C(1314925568), // SQSUBv8i16
6873 UINT64_C(236989440), // SQSUBv8i8
6874 UINT64_C(1160265728), // SQXTNB_ZZ_B
6875 UINT64_C(1160790016), // SQXTNB_ZZ_H
6876 UINT64_C(1163935744), // SQXTNB_ZZ_S
6877 UINT64_C(1160266752), // SQXTNT_ZZ_B
6878 UINT64_C(1160791040), // SQXTNT_ZZ_H
6879 UINT64_C(1163936768), // SQXTNT_ZZ_S
6880 UINT64_C(1310803968), // SQXTNv16i8
6881 UINT64_C(1583433728), // SQXTNv1i16
6882 UINT64_C(1587628032), // SQXTNv1i32
6883 UINT64_C(1579239424), // SQXTNv1i8
6884 UINT64_C(245450752), // SQXTNv2i32
6885 UINT64_C(241256448), // SQXTNv4i16
6886 UINT64_C(1319192576), // SQXTNv4i32
6887 UINT64_C(1314998272), // SQXTNv8i16
6888 UINT64_C(237062144), // SQXTNv8i8
6889 UINT64_C(1160269824), // SQXTUNB_ZZ_B
6890 UINT64_C(1160794112), // SQXTUNB_ZZ_H
6891 UINT64_C(1163939840), // SQXTUNB_ZZ_S
6892 UINT64_C(1160270848), // SQXTUNT_ZZ_B
6893 UINT64_C(1160795136), // SQXTUNT_ZZ_H
6894 UINT64_C(1163940864), // SQXTUNT_ZZ_S
6895 UINT64_C(1847666688), // SQXTUNv16i8
6896 UINT64_C(2120296448), // SQXTUNv1i16
6897 UINT64_C(2124490752), // SQXTUNv1i32
6898 UINT64_C(2116102144), // SQXTUNv1i8
6899 UINT64_C(782313472), // SQXTUNv2i32
6900 UINT64_C(778119168), // SQXTUNv4i16
6901 UINT64_C(1856055296), // SQXTUNv4i32
6902 UINT64_C(1851860992), // SQXTUNv8i16
6903 UINT64_C(773924864), // SQXTUNv8i8
6904 UINT64_C(1142194176), // SRHADD_ZPmZ_B
6905 UINT64_C(1154777088), // SRHADD_ZPmZ_D
6906 UINT64_C(1146388480), // SRHADD_ZPmZ_H
6907 UINT64_C(1150582784), // SRHADD_ZPmZ_S
6908 UINT64_C(1310725120), // SRHADDv16i8
6909 UINT64_C(245371904), // SRHADDv2i32
6910 UINT64_C(241177600), // SRHADDv4i16
6911 UINT64_C(1319113728), // SRHADDv4i32
6912 UINT64_C(1314919424), // SRHADDv8i16
6913 UINT64_C(236983296), // SRHADDv8i8
6914 UINT64_C(1158213632), // SRI_ZZI_B
6915 UINT64_C(1166077952), // SRI_ZZI_D
6916 UINT64_C(1158737920), // SRI_ZZI_H
6917 UINT64_C(1161883648), // SRI_ZZI_S
6918 UINT64_C(2134918144), // SRId
6919 UINT64_C(1862812672), // SRIv16i8_shift
6920 UINT64_C(790643712), // SRIv2i32_shift
6921 UINT64_C(1866482688), // SRIv2i64_shift
6922 UINT64_C(789595136), // SRIv4i16_shift
6923 UINT64_C(1864385536), // SRIv4i32_shift
6924 UINT64_C(1863336960), // SRIv8i16_shift
6925 UINT64_C(789070848), // SRIv8i8_shift
6926 UINT64_C(1141276672), // SRSHLR_ZPmZ_B
6927 UINT64_C(1153859584), // SRSHLR_ZPmZ_D
6928 UINT64_C(1145470976), // SRSHLR_ZPmZ_H
6929 UINT64_C(1149665280), // SRSHLR_ZPmZ_S
6930 UINT64_C(3240145440), // SRSHL_VG2_2Z2Z_B
6931 UINT64_C(3252728352), // SRSHL_VG2_2Z2Z_D
6932 UINT64_C(3244339744), // SRSHL_VG2_2Z2Z_H
6933 UINT64_C(3248534048), // SRSHL_VG2_2Z2Z_S
6934 UINT64_C(3240141344), // SRSHL_VG2_2ZZ_B
6935 UINT64_C(3252724256), // SRSHL_VG2_2ZZ_D
6936 UINT64_C(3244335648), // SRSHL_VG2_2ZZ_H
6937 UINT64_C(3248529952), // SRSHL_VG2_2ZZ_S
6938 UINT64_C(3240147488), // SRSHL_VG4_4Z4Z_B
6939 UINT64_C(3252730400), // SRSHL_VG4_4Z4Z_D
6940 UINT64_C(3244341792), // SRSHL_VG4_4Z4Z_H
6941 UINT64_C(3248536096), // SRSHL_VG4_4Z4Z_S
6942 UINT64_C(3240143392), // SRSHL_VG4_4ZZ_B
6943 UINT64_C(3252726304), // SRSHL_VG4_4ZZ_D
6944 UINT64_C(3244337696), // SRSHL_VG4_4ZZ_H
6945 UINT64_C(3248532000), // SRSHL_VG4_4ZZ_S
6946 UINT64_C(1141014528), // SRSHL_ZPmZ_B
6947 UINT64_C(1153597440), // SRSHL_ZPmZ_D
6948 UINT64_C(1145208832), // SRSHL_ZPmZ_H
6949 UINT64_C(1149403136), // SRSHL_ZPmZ_S
6950 UINT64_C(1310741504), // SRSHLv16i8
6951 UINT64_C(1591759872), // SRSHLv1i64
6952 UINT64_C(245388288), // SRSHLv2i32
6953 UINT64_C(1323324416), // SRSHLv2i64
6954 UINT64_C(241193984), // SRSHLv4i16
6955 UINT64_C(1319130112), // SRSHLv4i32
6956 UINT64_C(1314935808), // SRSHLv8i16
6957 UINT64_C(236999680), // SRSHLv8i8
6958 UINT64_C(67928320), // SRSHR_ZPmI_B
6959 UINT64_C(76316672), // SRSHR_ZPmI_D
6960 UINT64_C(67928576), // SRSHR_ZPmI_H
6961 UINT64_C(72122368), // SRSHR_ZPmI_S
6962 UINT64_C(1598039040), // SRSHRd
6963 UINT64_C(1325933568), // SRSHRv16i8_shift
6964 UINT64_C(253764608), // SRSHRv2i32_shift
6965 UINT64_C(1329603584), // SRSHRv2i64_shift
6966 UINT64_C(252716032), // SRSHRv4i16_shift
6967 UINT64_C(1327506432), // SRSHRv4i32_shift
6968 UINT64_C(1326457856), // SRSHRv8i16_shift
6969 UINT64_C(252191744), // SRSHRv8i8_shift
6970 UINT64_C(1158211584), // SRSRA_ZZI_B
6971 UINT64_C(1166075904), // SRSRA_ZZI_D
6972 UINT64_C(1158735872), // SRSRA_ZZI_H
6973 UINT64_C(1161881600), // SRSRA_ZZI_S
6974 UINT64_C(1598043136), // SRSRAd
6975 UINT64_C(1325937664), // SRSRAv16i8_shift
6976 UINT64_C(253768704), // SRSRAv2i32_shift
6977 UINT64_C(1329607680), // SRSRAv2i64_shift
6978 UINT64_C(252720128), // SRSRAv4i16_shift
6979 UINT64_C(1327510528), // SRSRAv4i32_shift
6980 UINT64_C(1326461952), // SRSRAv8i16_shift
6981 UINT64_C(252195840), // SRSRAv8i8_shift
6982 UINT64_C(1161863168), // SSHLLB_ZZI_D
6983 UINT64_C(1158193152), // SSHLLB_ZZI_H
6984 UINT64_C(1158717440), // SSHLLB_ZZI_S
6985 UINT64_C(1161864192), // SSHLLT_ZZI_D
6986 UINT64_C(1158194176), // SSHLLT_ZZI_H
6987 UINT64_C(1158718464), // SSHLLT_ZZI_S
6988 UINT64_C(1325966336), // SSHLLv16i8_shift
6989 UINT64_C(253797376), // SSHLLv2i32_shift
6990 UINT64_C(252748800), // SSHLLv4i16_shift
6991 UINT64_C(1327539200), // SSHLLv4i32_shift
6992 UINT64_C(1326490624), // SSHLLv8i16_shift
6993 UINT64_C(252224512), // SSHLLv8i8_shift
6994 UINT64_C(1310737408), // SSHLv16i8
6995 UINT64_C(1591755776), // SSHLv1i64
6996 UINT64_C(245384192), // SSHLv2i32
6997 UINT64_C(1323320320), // SSHLv2i64
6998 UINT64_C(241189888), // SSHLv4i16
6999 UINT64_C(1319126016), // SSHLv4i32
7000 UINT64_C(1314931712), // SSHLv8i16
7001 UINT64_C(236995584), // SSHLv8i8
7002 UINT64_C(1598030848), // SSHRd
7003 UINT64_C(1325925376), // SSHRv16i8_shift
7004 UINT64_C(253756416), // SSHRv2i32_shift
7005 UINT64_C(1329595392), // SSHRv2i64_shift
7006 UINT64_C(252707840), // SSHRv4i16_shift
7007 UINT64_C(1327498240), // SSHRv4i32_shift
7008 UINT64_C(1326449664), // SSHRv8i16_shift
7009 UINT64_C(252183552), // SSHRv8i8_shift
7010 UINT64_C(1158209536), // SSRA_ZZI_B
7011 UINT64_C(1166073856), // SSRA_ZZI_D
7012 UINT64_C(1158733824), // SSRA_ZZI_H
7013 UINT64_C(1161879552), // SSRA_ZZI_S
7014 UINT64_C(1598034944), // SSRAd
7015 UINT64_C(1325929472), // SSRAv16i8_shift
7016 UINT64_C(253760512), // SSRAv2i32_shift
7017 UINT64_C(1329599488), // SSRAv2i64_shift
7018 UINT64_C(252711936), // SSRAv4i16_shift
7019 UINT64_C(1327502336), // SSRAv4i32_shift
7020 UINT64_C(1326453760), // SSRAv8i16_shift
7021 UINT64_C(252187648), // SSRAv8i8_shift
7022 UINT64_C(3825246208), // SST1B_D
7023 UINT64_C(3829440512), // SST1B_D_IMM
7024 UINT64_C(3825254400), // SST1B_D_SXTW
7025 UINT64_C(3825238016), // SST1B_D_UXTW
7026 UINT64_C(3831537664), // SST1B_S_IMM
7027 UINT64_C(3829448704), // SST1B_S_SXTW
7028 UINT64_C(3829432320), // SST1B_S_UXTW
7029 UINT64_C(3850412032), // SST1D
7030 UINT64_C(3854606336), // SST1D_IMM
7031 UINT64_C(3852509184), // SST1D_SCALED
7032 UINT64_C(3850420224), // SST1D_SXTW
7033 UINT64_C(3852517376), // SST1D_SXTW_SCALED
7034 UINT64_C(3850403840), // SST1D_UXTW
7035 UINT64_C(3852500992), // SST1D_UXTW_SCALED
7036 UINT64_C(3833634816), // SST1H_D
7037 UINT64_C(3837829120), // SST1H_D_IMM
7038 UINT64_C(3835731968), // SST1H_D_SCALED
7039 UINT64_C(3833643008), // SST1H_D_SXTW
7040 UINT64_C(3835740160), // SST1H_D_SXTW_SCALED
7041 UINT64_C(3833626624), // SST1H_D_UXTW
7042 UINT64_C(3835723776), // SST1H_D_UXTW_SCALED
7043 UINT64_C(3839926272), // SST1H_S_IMM
7044 UINT64_C(3837837312), // SST1H_S_SXTW
7045 UINT64_C(3839934464), // SST1H_S_SXTW_SCALED
7046 UINT64_C(3837820928), // SST1H_S_UXTW
7047 UINT64_C(3839918080), // SST1H_S_UXTW_SCALED
7048 UINT64_C(3827310592), // SST1Q
7049 UINT64_C(3842023424), // SST1W_D
7050 UINT64_C(3846217728), // SST1W_D_IMM
7051 UINT64_C(3844120576), // SST1W_D_SCALED
7052 UINT64_C(3842031616), // SST1W_D_SXTW
7053 UINT64_C(3844128768), // SST1W_D_SXTW_SCALED
7054 UINT64_C(3842015232), // SST1W_D_UXTW
7055 UINT64_C(3844112384), // SST1W_D_UXTW_SCALED
7056 UINT64_C(3848314880), // SST1W_IMM
7057 UINT64_C(3846225920), // SST1W_SXTW
7058 UINT64_C(3848323072), // SST1W_SXTW_SCALED
7059 UINT64_C(3846209536), // SST1W_UXTW
7060 UINT64_C(3848306688), // SST1W_UXTW_SCALED
7061 UINT64_C(1170245632), // SSUBLBT_ZZZ_D
7062 UINT64_C(1161857024), // SSUBLBT_ZZZ_H
7063 UINT64_C(1166051328), // SSUBLBT_ZZZ_S
7064 UINT64_C(1170214912), // SSUBLB_ZZZ_D
7065 UINT64_C(1161826304), // SSUBLB_ZZZ_H
7066 UINT64_C(1166020608), // SSUBLB_ZZZ_S
7067 UINT64_C(1170246656), // SSUBLTB_ZZZ_D
7068 UINT64_C(1161858048), // SSUBLTB_ZZZ_H
7069 UINT64_C(1166052352), // SSUBLTB_ZZZ_S
7070 UINT64_C(1170215936), // SSUBLT_ZZZ_D
7071 UINT64_C(1161827328), // SSUBLT_ZZZ_H
7072 UINT64_C(1166021632), // SSUBLT_ZZZ_S
7073 UINT64_C(1310728192), // SSUBLv16i8_v8i16
7074 UINT64_C(245374976), // SSUBLv2i32_v2i64
7075 UINT64_C(241180672), // SSUBLv4i16_v4i32
7076 UINT64_C(1319116800), // SSUBLv4i32_v2i64
7077 UINT64_C(1314922496), // SSUBLv8i16_v4i32
7078 UINT64_C(236986368), // SSUBLv8i8_v8i16
7079 UINT64_C(1170231296), // SSUBWB_ZZZ_D
7080 UINT64_C(1161842688), // SSUBWB_ZZZ_H
7081 UINT64_C(1166036992), // SSUBWB_ZZZ_S
7082 UINT64_C(1170232320), // SSUBWT_ZZZ_D
7083 UINT64_C(1161843712), // SSUBWT_ZZZ_H
7084 UINT64_C(1166038016), // SSUBWT_ZZZ_S
7085 UINT64_C(1310732288), // SSUBWv16i8_v8i16
7086 UINT64_C(245379072), // SSUBWv2i32_v2i64
7087 UINT64_C(241184768), // SSUBWv4i16_v4i32
7088 UINT64_C(1319120896), // SSUBWv4i32_v2i64
7089 UINT64_C(1314926592), // SSUBWv8i16_v4i32
7090 UINT64_C(236990464), // SSUBWv8i8_v8i16
7091 UINT64_C(3825221632), // ST1B
7092 UINT64_C(2686451712), // ST1B_2Z
7093 UINT64_C(2690646016), // ST1B_2Z_IMM
7094 UINT64_C(2703228928), // ST1B_2Z_STRIDED
7095 UINT64_C(2707423232), // ST1B_2Z_STRIDED_IMM
7096 UINT64_C(2686484480), // ST1B_4Z
7097 UINT64_C(2690678784), // ST1B_4Z_IMM
7098 UINT64_C(2703261696), // ST1B_4Z_STRIDED
7099 UINT64_C(2707456000), // ST1B_4Z_STRIDED_IMM
7100 UINT64_C(3831513088), // ST1B_D
7101 UINT64_C(3831554048), // ST1B_D_IMM
7102 UINT64_C(3827318784), // ST1B_H
7103 UINT64_C(3827359744), // ST1B_H_IMM
7104 UINT64_C(3825262592), // ST1B_IMM
7105 UINT64_C(3829415936), // ST1B_S
7106 UINT64_C(3829456896), // ST1B_S_IMM
7107 UINT64_C(3856678912), // ST1D
7108 UINT64_C(2686476288), // ST1D_2Z
7109 UINT64_C(2690670592), // ST1D_2Z_IMM
7110 UINT64_C(2703253504), // ST1D_2Z_STRIDED
7111 UINT64_C(2707447808), // ST1D_2Z_STRIDED_IMM
7112 UINT64_C(2686509056), // ST1D_4Z
7113 UINT64_C(2690703360), // ST1D_4Z_IMM
7114 UINT64_C(2703286272), // ST1D_4Z_STRIDED
7115 UINT64_C(2707480576), // ST1D_4Z_STRIDED_IMM
7116 UINT64_C(3856719872), // ST1D_IMM
7117 UINT64_C(3854581760), // ST1D_Q
7118 UINT64_C(3854622720), // ST1D_Q_IMM
7119 UINT64_C(1275076608), // ST1Fourv16b
7120 UINT64_C(1283465216), // ST1Fourv16b_POST
7121 UINT64_C(201337856), // ST1Fourv1d
7122 UINT64_C(209726464), // ST1Fourv1d_POST
7123 UINT64_C(1275079680), // ST1Fourv2d
7124 UINT64_C(1283468288), // ST1Fourv2d_POST
7125 UINT64_C(201336832), // ST1Fourv2s
7126 UINT64_C(209725440), // ST1Fourv2s_POST
7127 UINT64_C(201335808), // ST1Fourv4h
7128 UINT64_C(209724416), // ST1Fourv4h_POST
7129 UINT64_C(1275078656), // ST1Fourv4s
7130 UINT64_C(1283467264), // ST1Fourv4s_POST
7131 UINT64_C(201334784), // ST1Fourv8b
7132 UINT64_C(209723392), // ST1Fourv8b_POST
7133 UINT64_C(1275077632), // ST1Fourv8h
7134 UINT64_C(1283466240), // ST1Fourv8h_POST
7135 UINT64_C(3835707392), // ST1H
7136 UINT64_C(2686459904), // ST1H_2Z
7137 UINT64_C(2690654208), // ST1H_2Z_IMM
7138 UINT64_C(2703237120), // ST1H_2Z_STRIDED
7139 UINT64_C(2707431424), // ST1H_2Z_STRIDED_IMM
7140 UINT64_C(2686492672), // ST1H_4Z
7141 UINT64_C(2690686976), // ST1H_4Z_IMM
7142 UINT64_C(2703269888), // ST1H_4Z_STRIDED
7143 UINT64_C(2707464192), // ST1H_4Z_STRIDED_IMM
7144 UINT64_C(3839901696), // ST1H_D
7145 UINT64_C(3839942656), // ST1H_D_IMM
7146 UINT64_C(3835748352), // ST1H_IMM
7147 UINT64_C(3837804544), // ST1H_S
7148 UINT64_C(3837845504), // ST1H_S_IMM
7149 UINT64_C(1275097088), // ST1Onev16b
7150 UINT64_C(1283485696), // ST1Onev16b_POST
7151 UINT64_C(201358336), // ST1Onev1d
7152 UINT64_C(209746944), // ST1Onev1d_POST
7153 UINT64_C(1275100160), // ST1Onev2d
7154 UINT64_C(1283488768), // ST1Onev2d_POST
7155 UINT64_C(201357312), // ST1Onev2s
7156 UINT64_C(209745920), // ST1Onev2s_POST
7157 UINT64_C(201356288), // ST1Onev4h
7158 UINT64_C(209744896), // ST1Onev4h_POST
7159 UINT64_C(1275099136), // ST1Onev4s
7160 UINT64_C(1283487744), // ST1Onev4s_POST
7161 UINT64_C(201355264), // ST1Onev8b
7162 UINT64_C(209743872), // ST1Onev8b_POST
7163 UINT64_C(1275098112), // ST1Onev8h
7164 UINT64_C(1283486720), // ST1Onev8h_POST
7165 UINT64_C(1275092992), // ST1Threev16b
7166 UINT64_C(1283481600), // ST1Threev16b_POST
7167 UINT64_C(201354240), // ST1Threev1d
7168 UINT64_C(209742848), // ST1Threev1d_POST
7169 UINT64_C(1275096064), // ST1Threev2d
7170 UINT64_C(1283484672), // ST1Threev2d_POST
7171 UINT64_C(201353216), // ST1Threev2s
7172 UINT64_C(209741824), // ST1Threev2s_POST
7173 UINT64_C(201352192), // ST1Threev4h
7174 UINT64_C(209740800), // ST1Threev4h_POST
7175 UINT64_C(1275095040), // ST1Threev4s
7176 UINT64_C(1283483648), // ST1Threev4s_POST
7177 UINT64_C(201351168), // ST1Threev8b
7178 UINT64_C(209739776), // ST1Threev8b_POST
7179 UINT64_C(1275094016), // ST1Threev8h
7180 UINT64_C(1283482624), // ST1Threev8h_POST
7181 UINT64_C(1275109376), // ST1Twov16b
7182 UINT64_C(1283497984), // ST1Twov16b_POST
7183 UINT64_C(201370624), // ST1Twov1d
7184 UINT64_C(209759232), // ST1Twov1d_POST
7185 UINT64_C(1275112448), // ST1Twov2d
7186 UINT64_C(1283501056), // ST1Twov2d_POST
7187 UINT64_C(201369600), // ST1Twov2s
7188 UINT64_C(209758208), // ST1Twov2s_POST
7189 UINT64_C(201368576), // ST1Twov4h
7190 UINT64_C(209757184), // ST1Twov4h_POST
7191 UINT64_C(1275111424), // ST1Twov4s
7192 UINT64_C(1283500032), // ST1Twov4s_POST
7193 UINT64_C(201367552), // ST1Twov8b
7194 UINT64_C(209756160), // ST1Twov8b_POST
7195 UINT64_C(1275110400), // ST1Twov8h
7196 UINT64_C(1283499008), // ST1Twov8h_POST
7197 UINT64_C(3846193152), // ST1W
7198 UINT64_C(2686468096), // ST1W_2Z
7199 UINT64_C(2690662400), // ST1W_2Z_IMM
7200 UINT64_C(2703245312), // ST1W_2Z_STRIDED
7201 UINT64_C(2707439616), // ST1W_2Z_STRIDED_IMM
7202 UINT64_C(2686500864), // ST1W_4Z
7203 UINT64_C(2690695168), // ST1W_4Z_IMM
7204 UINT64_C(2703278080), // ST1W_4Z_STRIDED
7205 UINT64_C(2707472384), // ST1W_4Z_STRIDED_IMM
7206 UINT64_C(3848290304), // ST1W_D
7207 UINT64_C(3848331264), // ST1W_D_IMM
7208 UINT64_C(3846234112), // ST1W_IMM
7209 UINT64_C(3841998848), // ST1W_Q
7210 UINT64_C(3842039808), // ST1W_Q_IMM
7211 UINT64_C(3760193536), // ST1_MXIPXX_H_B
7212 UINT64_C(3772776448), // ST1_MXIPXX_H_D
7213 UINT64_C(3764387840), // ST1_MXIPXX_H_H
7214 UINT64_C(3789553664), // ST1_MXIPXX_H_Q
7215 UINT64_C(3768582144), // ST1_MXIPXX_H_S
7216 UINT64_C(3760226304), // ST1_MXIPXX_V_B
7217 UINT64_C(3772809216), // ST1_MXIPXX_V_D
7218 UINT64_C(3764420608), // ST1_MXIPXX_V_H
7219 UINT64_C(3789586432), // ST1_MXIPXX_V_Q
7220 UINT64_C(3768614912), // ST1_MXIPXX_V_S
7221 UINT64_C(218120192), // ST1i16
7222 UINT64_C(226508800), // ST1i16_POST
7223 UINT64_C(218136576), // ST1i32
7224 UINT64_C(226525184), // ST1i32_POST
7225 UINT64_C(218137600), // ST1i64
7226 UINT64_C(226526208), // ST1i64_POST
7227 UINT64_C(218103808), // ST1i8
7228 UINT64_C(226492416), // ST1i8_POST
7229 UINT64_C(3827326976), // ST2B
7230 UINT64_C(3828408320), // ST2B_IMM
7231 UINT64_C(3852492800), // ST2D
7232 UINT64_C(3853574144), // ST2D_IMM
7233 UINT64_C(3651142656), // ST2GPostIndex
7234 UINT64_C(3651144704), // ST2GPreIndex
7235 UINT64_C(3651143680), // ST2Gi
7236 UINT64_C(3835715584), // ST2H
7237 UINT64_C(3836796928), // ST2H_IMM
7238 UINT64_C(3831496704), // ST2Q
7239 UINT64_C(3829399552), // ST2Q_IMM
7240 UINT64_C(1275101184), // ST2Twov16b
7241 UINT64_C(1283489792), // ST2Twov16b_POST
7242 UINT64_C(1275104256), // ST2Twov2d
7243 UINT64_C(1283492864), // ST2Twov2d_POST
7244 UINT64_C(201361408), // ST2Twov2s
7245 UINT64_C(209750016), // ST2Twov2s_POST
7246 UINT64_C(201360384), // ST2Twov4h
7247 UINT64_C(209748992), // ST2Twov4h_POST
7248 UINT64_C(1275103232), // ST2Twov4s
7249 UINT64_C(1283491840), // ST2Twov4s_POST
7250 UINT64_C(201359360), // ST2Twov8b
7251 UINT64_C(209747968), // ST2Twov8b_POST
7252 UINT64_C(1275102208), // ST2Twov8h
7253 UINT64_C(1283490816), // ST2Twov8h_POST
7254 UINT64_C(3844104192), // ST2W
7255 UINT64_C(3845185536), // ST2W_IMM
7256 UINT64_C(220217344), // ST2i16
7257 UINT64_C(228605952), // ST2i16_POST
7258 UINT64_C(220233728), // ST2i32
7259 UINT64_C(228622336), // ST2i32_POST
7260 UINT64_C(220234752), // ST2i64
7261 UINT64_C(228623360), // ST2i64_POST
7262 UINT64_C(220200960), // ST2i8
7263 UINT64_C(228589568), // ST2i8_POST
7264 UINT64_C(3829424128), // ST3B
7265 UINT64_C(3830505472), // ST3B_IMM
7266 UINT64_C(3854589952), // ST3D
7267 UINT64_C(3855671296), // ST3D_IMM
7268 UINT64_C(3837812736), // ST3H
7269 UINT64_C(3838894080), // ST3H_IMM
7270 UINT64_C(3835691008), // ST3Q
7271 UINT64_C(3833593856), // ST3Q_IMM
7272 UINT64_C(1275084800), // ST3Threev16b
7273 UINT64_C(1283473408), // ST3Threev16b_POST
7274 UINT64_C(1275087872), // ST3Threev2d
7275 UINT64_C(1283476480), // ST3Threev2d_POST
7276 UINT64_C(201345024), // ST3Threev2s
7277 UINT64_C(209733632), // ST3Threev2s_POST
7278 UINT64_C(201344000), // ST3Threev4h
7279 UINT64_C(209732608), // ST3Threev4h_POST
7280 UINT64_C(1275086848), // ST3Threev4s
7281 UINT64_C(1283475456), // ST3Threev4s_POST
7282 UINT64_C(201342976), // ST3Threev8b
7283 UINT64_C(209731584), // ST3Threev8b_POST
7284 UINT64_C(1275085824), // ST3Threev8h
7285 UINT64_C(1283474432), // ST3Threev8h_POST
7286 UINT64_C(3846201344), // ST3W
7287 UINT64_C(3847282688), // ST3W_IMM
7288 UINT64_C(218128384), // ST3i16
7289 UINT64_C(226516992), // ST3i16_POST
7290 UINT64_C(218144768), // ST3i32
7291 UINT64_C(226533376), // ST3i32_POST
7292 UINT64_C(218145792), // ST3i64
7293 UINT64_C(226534400), // ST3i64_POST
7294 UINT64_C(218112000), // ST3i8
7295 UINT64_C(226500608), // ST3i8_POST
7296 UINT64_C(3831521280), // ST4B
7297 UINT64_C(3832602624), // ST4B_IMM
7298 UINT64_C(3856687104), // ST4D
7299 UINT64_C(3857768448), // ST4D_IMM
7300 UINT64_C(1275068416), // ST4Fourv16b
7301 UINT64_C(1283457024), // ST4Fourv16b_POST
7302 UINT64_C(1275071488), // ST4Fourv2d
7303 UINT64_C(1283460096), // ST4Fourv2d_POST
7304 UINT64_C(201328640), // ST4Fourv2s
7305 UINT64_C(209717248), // ST4Fourv2s_POST
7306 UINT64_C(201327616), // ST4Fourv4h
7307 UINT64_C(209716224), // ST4Fourv4h_POST
7308 UINT64_C(1275070464), // ST4Fourv4s
7309 UINT64_C(1283459072), // ST4Fourv4s_POST
7310 UINT64_C(201326592), // ST4Fourv8b
7311 UINT64_C(209715200), // ST4Fourv8b_POST
7312 UINT64_C(1275069440), // ST4Fourv8h
7313 UINT64_C(1283458048), // ST4Fourv8h_POST
7314 UINT64_C(3839909888), // ST4H
7315 UINT64_C(3840991232), // ST4H_IMM
7316 UINT64_C(3839885312), // ST4Q
7317 UINT64_C(3837788160), // ST4Q_IMM
7318 UINT64_C(3848298496), // ST4W
7319 UINT64_C(3849379840), // ST4W_IMM
7320 UINT64_C(220225536), // ST4i16
7321 UINT64_C(228614144), // ST4i16_POST
7322 UINT64_C(220241920), // ST4i32
7323 UINT64_C(228630528), // ST4i32_POST
7324 UINT64_C(220242944), // ST4i64
7325 UINT64_C(228631552), // ST4i64_POST
7326 UINT64_C(220209152), // ST4i8
7327 UINT64_C(228597760), // ST4i8_POST
7328 UINT64_C(4164915200), // ST64B
7329 UINT64_C(4162891776), // ST64BV
7330 UINT64_C(4162887680), // ST64BV0
7331 UINT64_C(1008762911), // STBFADD
7332 UINT64_C(1012957215), // STBFADDL
7333 UINT64_C(1008779295), // STBFMAX
7334 UINT64_C(1012973599), // STBFMAXL
7335 UINT64_C(1008787487), // STBFMAXNM
7336 UINT64_C(1012981791), // STBFMAXNML
7337 UINT64_C(1008783391), // STBFMIN
7338 UINT64_C(1012977695), // STBFMINL
7339 UINT64_C(1008791583), // STBFMINNM
7340 UINT64_C(1012985887), // STBFMINNML
7341 UINT64_C(4229988383), // STFADDD
7342 UINT64_C(2082504735), // STFADDH
7343 UINT64_C(4234182687), // STFADDLD
7344 UINT64_C(2086699039), // STFADDLH
7345 UINT64_C(3160440863), // STFADDLS
7346 UINT64_C(3156246559), // STFADDS
7347 UINT64_C(4230004767), // STFMAXD
7348 UINT64_C(2082521119), // STFMAXH
7349 UINT64_C(4234199071), // STFMAXLD
7350 UINT64_C(2086715423), // STFMAXLH
7351 UINT64_C(3160457247), // STFMAXLS
7352 UINT64_C(4230012959), // STFMAXNMD
7353 UINT64_C(2082529311), // STFMAXNMH
7354 UINT64_C(4234207263), // STFMAXNMLD
7355 UINT64_C(2086723615), // STFMAXNMLH
7356 UINT64_C(3160465439), // STFMAXNMLS
7357 UINT64_C(3156271135), // STFMAXNMS
7358 UINT64_C(3156262943), // STFMAXS
7359 UINT64_C(4230008863), // STFMIND
7360 UINT64_C(2082525215), // STFMINH
7361 UINT64_C(4234203167), // STFMINLD
7362 UINT64_C(2086719519), // STFMINLH
7363 UINT64_C(3160461343), // STFMINLS
7364 UINT64_C(4230017055), // STFMINNMD
7365 UINT64_C(2082533407), // STFMINNMH
7366 UINT64_C(4234211359), // STFMINNMLD
7367 UINT64_C(2086727711), // STFMINNMLH
7368 UINT64_C(3160469535), // STFMINNMLS
7369 UINT64_C(3156275231), // STFMINNMS
7370 UINT64_C(3156267039), // STFMINS
7371 UINT64_C(3651141632), // STGM
7372 UINT64_C(1761607680), // STGPi
7373 UINT64_C(3642754048), // STGPostIndex
7374 UINT64_C(1753219072), // STGPpost
7375 UINT64_C(1769996288), // STGPpre
7376 UINT64_C(3642756096), // STGPreIndex
7377 UINT64_C(3642755072), // STGi
7378 UINT64_C(2566920192), // STILPW
7379 UINT64_C(2566916096), // STILPWpre
7380 UINT64_C(3640662016), // STILPX
7381 UINT64_C(3640657920), // STILPXpre
7382 UINT64_C(218203136), // STL1
7383 UINT64_C(144669696), // STLLRB
7384 UINT64_C(1218411520), // STLLRH
7385 UINT64_C(2292153344), // STLLRW
7386 UINT64_C(3365895168), // STLLRX
7387 UINT64_C(144702464), // STLRB
7388 UINT64_C(1218444288), // STLRH
7389 UINT64_C(2292186112), // STLRW
7390 UINT64_C(2575304704), // STLRWpre
7391 UINT64_C(3365927936), // STLRX
7392 UINT64_C(3649046528), // STLRXpre
7393 UINT64_C(2298543104), // STLTXRW
7394 UINT64_C(3372284928), // STLTXRX
7395 UINT64_C(419430400), // STLURBi
7396 UINT64_C(1493172224), // STLURHi
7397 UINT64_C(2566914048), // STLURWi
7398 UINT64_C(3640655872), // STLURXi
7399 UINT64_C(486541312), // STLURbi
7400 UINT64_C(3707766784), // STLURdi
7401 UINT64_C(1560283136), // STLURhi
7402 UINT64_C(494929920), // STLURqi
7403 UINT64_C(2634024960), // STLURsi
7404 UINT64_C(2283831296), // STLXPW
7405 UINT64_C(3357573120), // STLXPX
7406 UINT64_C(134250496), // STLXRB
7407 UINT64_C(1207992320), // STLXRH
7408 UINT64_C(2281734144), // STLXRW
7409 UINT64_C(3355475968), // STLXRX
7410 UINT64_C(2151710720), // STMOPA_M2ZZZI_BtoS
7411 UINT64_C(2151710728), // STMOPA_M2ZZZI_HtoS
7412 UINT64_C(1811939328), // STNPDi
7413 UINT64_C(2885681152), // STNPQi
7414 UINT64_C(738197504), // STNPSi
7415 UINT64_C(671088640), // STNPWi
7416 UINT64_C(2818572288), // STNPXi
7417 UINT64_C(2686451713), // STNT1B_2Z
7418 UINT64_C(2690646017), // STNT1B_2Z_IMM
7419 UINT64_C(2703228936), // STNT1B_2Z_STRIDED
7420 UINT64_C(2707423240), // STNT1B_2Z_STRIDED_IMM
7421 UINT64_C(2686484481), // STNT1B_4Z
7422 UINT64_C(2690678785), // STNT1B_4Z_IMM
7423 UINT64_C(2703261704), // STNT1B_4Z_STRIDED
7424 UINT64_C(2707456008), // STNT1B_4Z_STRIDED_IMM
7425 UINT64_C(3826311168), // STNT1B_ZRI
7426 UINT64_C(3825229824), // STNT1B_ZRR
7427 UINT64_C(3825213440), // STNT1B_ZZR_D
7428 UINT64_C(3829407744), // STNT1B_ZZR_S
7429 UINT64_C(2686476289), // STNT1D_2Z
7430 UINT64_C(2690670593), // STNT1D_2Z_IMM
7431 UINT64_C(2703253512), // STNT1D_2Z_STRIDED
7432 UINT64_C(2707447816), // STNT1D_2Z_STRIDED_IMM
7433 UINT64_C(2686509057), // STNT1D_4Z
7434 UINT64_C(2690703361), // STNT1D_4Z_IMM
7435 UINT64_C(2703286280), // STNT1D_4Z_STRIDED
7436 UINT64_C(2707480584), // STNT1D_4Z_STRIDED_IMM
7437 UINT64_C(3851476992), // STNT1D_ZRI
7438 UINT64_C(3850395648), // STNT1D_ZRR
7439 UINT64_C(3850379264), // STNT1D_ZZR_D
7440 UINT64_C(2686459905), // STNT1H_2Z
7441 UINT64_C(2690654209), // STNT1H_2Z_IMM
7442 UINT64_C(2703237128), // STNT1H_2Z_STRIDED
7443 UINT64_C(2707431432), // STNT1H_2Z_STRIDED_IMM
7444 UINT64_C(2686492673), // STNT1H_4Z
7445 UINT64_C(2690686977), // STNT1H_4Z_IMM
7446 UINT64_C(2703269896), // STNT1H_4Z_STRIDED
7447 UINT64_C(2707464200), // STNT1H_4Z_STRIDED_IMM
7448 UINT64_C(3834699776), // STNT1H_ZRI
7449 UINT64_C(3833618432), // STNT1H_ZRR
7450 UINT64_C(3833602048), // STNT1H_ZZR_D
7451 UINT64_C(3837796352), // STNT1H_ZZR_S
7452 UINT64_C(2686468097), // STNT1W_2Z
7453 UINT64_C(2690662401), // STNT1W_2Z_IMM
7454 UINT64_C(2703245320), // STNT1W_2Z_STRIDED
7455 UINT64_C(2707439624), // STNT1W_2Z_STRIDED_IMM
7456 UINT64_C(2686500865), // STNT1W_4Z
7457 UINT64_C(2690695169), // STNT1W_4Z_IMM
7458 UINT64_C(2703278088), // STNT1W_4Z_STRIDED
7459 UINT64_C(2707472392), // STNT1W_4Z_STRIDED_IMM
7460 UINT64_C(3843088384), // STNT1W_ZRI
7461 UINT64_C(3842007040), // STNT1W_ZRR
7462 UINT64_C(3841990656), // STNT1W_ZZR_D
7463 UINT64_C(3846184960), // STNT1W_ZZR_S
7464 UINT64_C(1828716544), // STPDi
7465 UINT64_C(1820327936), // STPDpost
7466 UINT64_C(1837105152), // STPDpre
7467 UINT64_C(2902458368), // STPQi
7468 UINT64_C(2894069760), // STPQpost
7469 UINT64_C(2910846976), // STPQpre
7470 UINT64_C(754974720), // STPSi
7471 UINT64_C(746586112), // STPSpost
7472 UINT64_C(763363328), // STPSpre
7473 UINT64_C(687865856), // STPWi
7474 UINT64_C(679477248), // STPWpost
7475 UINT64_C(696254464), // STPWpre
7476 UINT64_C(2835349504), // STPXi
7477 UINT64_C(2826960896), // STPXpost
7478 UINT64_C(2843738112), // STPXpre
7479 UINT64_C(939525120), // STRBBpost
7480 UINT64_C(939527168), // STRBBpre
7481 UINT64_C(941639680), // STRBBroW
7482 UINT64_C(941647872), // STRBBroX
7483 UINT64_C(956301312), // STRBBui
7484 UINT64_C(1006633984), // STRBpost
7485 UINT64_C(1006636032), // STRBpre
7486 UINT64_C(1008748544), // STRBroW
7487 UINT64_C(1008756736), // STRBroX
7488 UINT64_C(1023410176), // STRBui
7489 UINT64_C(4227859456), // STRDpost
7490 UINT64_C(4227861504), // STRDpre
7491 UINT64_C(4229974016), // STRDroW
7492 UINT64_C(4229982208), // STRDroX
7493 UINT64_C(4244635648), // STRDui
7494 UINT64_C(2013266944), // STRHHpost
7495 UINT64_C(2013268992), // STRHHpre
7496 UINT64_C(2015381504), // STRHHroW
7497 UINT64_C(2015389696), // STRHHroX
7498 UINT64_C(2030043136), // STRHHui
7499 UINT64_C(2080375808), // STRHpost
7500 UINT64_C(2080377856), // STRHpre
7501 UINT64_C(2082490368), // STRHroW
7502 UINT64_C(2082498560), // STRHroX
7503 UINT64_C(2097152000), // STRHui
7504 UINT64_C(1015022592), // STRQpost
7505 UINT64_C(1015024640), // STRQpre
7506 UINT64_C(1017137152), // STRQroW
7507 UINT64_C(1017145344), // STRQroX
7508 UINT64_C(1031798784), // STRQui
7509 UINT64_C(3154117632), // STRSpost
7510 UINT64_C(3154119680), // STRSpre
7511 UINT64_C(3156232192), // STRSroW
7512 UINT64_C(3156240384), // STRSroX
7513 UINT64_C(3170893824), // STRSui
7514 UINT64_C(3087008768), // STRWpost
7515 UINT64_C(3087010816), // STRWpre
7516 UINT64_C(3089123328), // STRWroW
7517 UINT64_C(3089131520), // STRWroX
7518 UINT64_C(3103784960), // STRWui
7519 UINT64_C(4160750592), // STRXpost
7520 UINT64_C(4160752640), // STRXpre
7521 UINT64_C(4162865152), // STRXroW
7522 UINT64_C(4162873344), // STRXroX
7523 UINT64_C(4177526784), // STRXui
7524 UINT64_C(3850371072), // STR_PXI
7525 UINT64_C(3779035136), // STR_TX
7526 UINT64_C(3776970752), // STR_ZA
7527 UINT64_C(3850387456), // STR_ZXI
7528 UINT64_C(3573650975), // STSHH
7529 UINT64_C(3959422976), // STTNPQi
7530 UINT64_C(3892314112), // STTNPXi
7531 UINT64_C(3976200192), // STTPQi
7532 UINT64_C(3967811584), // STTPQpost
7533 UINT64_C(3984588800), // STTPQpre
7534 UINT64_C(3909091328), // STTPi
7535 UINT64_C(3900702720), // STTPpost
7536 UINT64_C(3917479936), // STTPpre
7537 UINT64_C(939526144), // STTRBi
7538 UINT64_C(2013267968), // STTRHi
7539 UINT64_C(3087009792), // STTRWi
7540 UINT64_C(4160751616), // STTRXi
7541 UINT64_C(2298510336), // STTXRWr
7542 UINT64_C(3372252160), // STTXRXr
7543 UINT64_C(939524096), // STURBBi
7544 UINT64_C(1006632960), // STURBi
7545 UINT64_C(4227858432), // STURDi
7546 UINT64_C(2013265920), // STURHHi
7547 UINT64_C(2080374784), // STURHi
7548 UINT64_C(1015021568), // STURQi
7549 UINT64_C(3154116608), // STURSi
7550 UINT64_C(3087007744), // STURWi
7551 UINT64_C(4160749568), // STURXi
7552 UINT64_C(2283798528), // STXPW
7553 UINT64_C(3357540352), // STXPX
7554 UINT64_C(134217728), // STXRB
7555 UINT64_C(1207959552), // STXRH
7556 UINT64_C(2281701376), // STXRW
7557 UINT64_C(3355443200), // STXRX
7558 UINT64_C(3655336960), // STZ2GPostIndex
7559 UINT64_C(3655339008), // STZ2GPreIndex
7560 UINT64_C(3655337984), // STZ2Gi
7561 UINT64_C(3642753024), // STZGM
7562 UINT64_C(3646948352), // STZGPostIndex
7563 UINT64_C(3646950400), // STZGPreIndex
7564 UINT64_C(3646949376), // STZGi
7565 UINT64_C(3514826752), // SUBG
7566 UINT64_C(1163948032), // SUBHNB_ZZZ_B
7567 UINT64_C(1168142336), // SUBHNB_ZZZ_H
7568 UINT64_C(1172336640), // SUBHNB_ZZZ_S
7569 UINT64_C(1163949056), // SUBHNT_ZZZ_B
7570 UINT64_C(1168143360), // SUBHNT_ZZZ_H
7571 UINT64_C(1172337664), // SUBHNT_ZZZ_S
7572 UINT64_C(245391360), // SUBHNv2i64_v2i32
7573 UINT64_C(1319133184), // SUBHNv2i64_v4i32
7574 UINT64_C(241197056), // SUBHNv4i32_v4i16
7575 UINT64_C(1314938880), // SUBHNv4i32_v8i16
7576 UINT64_C(1310744576), // SUBHNv8i16_v16i8
7577 UINT64_C(237002752), // SUBHNv8i16_v8i8
7578 UINT64_C(2596274176), // SUBP
7579 UINT64_C(3133145088), // SUBPS
7580 UINT64_C(3657441280), // SUBPT_shift
7581 UINT64_C(623099904), // SUBR_ZI_B
7582 UINT64_C(635682816), // SUBR_ZI_D
7583 UINT64_C(627294208), // SUBR_ZI_H
7584 UINT64_C(631488512), // SUBR_ZI_S
7585 UINT64_C(67305472), // SUBR_ZPmZ_B
7586 UINT64_C(79888384), // SUBR_ZPmZ_D
7587 UINT64_C(71499776), // SUBR_ZPmZ_H
7588 UINT64_C(75694080), // SUBR_ZPmZ_S
7589 UINT64_C(1895825408), // SUBSWri
7590 UINT64_C(1795162112), // SUBSWrs
7591 UINT64_C(1797259264), // SUBSWrx
7592 UINT64_C(4043309056), // SUBSXri
7593 UINT64_C(3942645760), // SUBSXrs
7594 UINT64_C(3944742912), // SUBSXrx
7595 UINT64_C(3944767488), // SUBSXrx64
7596 UINT64_C(1358954496), // SUBWri
7597 UINT64_C(1258291200), // SUBWrs
7598 UINT64_C(1260388352), // SUBWrx
7599 UINT64_C(3506438144), // SUBXri
7600 UINT64_C(3405774848), // SUBXrs
7601 UINT64_C(3407872000), // SUBXrx
7602 UINT64_C(3407896576), // SUBXrx64
7603 UINT64_C(3252688920), // SUB_VG2_M2Z2Z_D
7604 UINT64_C(3248494616), // SUB_VG2_M2Z2Z_S
7605 UINT64_C(3244300312), // SUB_VG2_M2ZZ_D
7606 UINT64_C(3240106008), // SUB_VG2_M2ZZ_S
7607 UINT64_C(3252689944), // SUB_VG2_M2Z_D
7608 UINT64_C(3248495640), // SUB_VG2_M2Z_S
7609 UINT64_C(3252754456), // SUB_VG4_M4Z4Z_D
7610 UINT64_C(3248560152), // SUB_VG4_M4Z4Z_S
7611 UINT64_C(3245348888), // SUB_VG4_M4ZZ_D
7612 UINT64_C(3241154584), // SUB_VG4_M4ZZ_S
7613 UINT64_C(3252755480), // SUB_VG4_M4Z_D
7614 UINT64_C(3248561176), // SUB_VG4_M4Z_S
7615 UINT64_C(622968832), // SUB_ZI_B
7616 UINT64_C(635551744), // SUB_ZI_D
7617 UINT64_C(627163136), // SUB_ZI_H
7618 UINT64_C(631357440), // SUB_ZI_S
7619 UINT64_C(67174400), // SUB_ZPmZ_B
7620 UINT64_C(80019456), // SUB_ZPmZ_CPA
7621 UINT64_C(79757312), // SUB_ZPmZ_D
7622 UINT64_C(71368704), // SUB_ZPmZ_H
7623 UINT64_C(75563008), // SUB_ZPmZ_S
7624 UINT64_C(69207040), // SUB_ZZZ_B
7625 UINT64_C(81792000), // SUB_ZZZ_CPA
7626 UINT64_C(81789952), // SUB_ZZZ_D
7627 UINT64_C(73401344), // SUB_ZZZ_H
7628 UINT64_C(77595648), // SUB_ZZZ_S
7629 UINT64_C(1847624704), // SUBv16i8
7630 UINT64_C(2128643072), // SUBv1i64
7631 UINT64_C(782271488), // SUBv2i32
7632 UINT64_C(1860207616), // SUBv2i64
7633 UINT64_C(778077184), // SUBv4i16
7634 UINT64_C(1856013312), // SUBv4i32
7635 UINT64_C(1851819008), // SUBv8i16
7636 UINT64_C(773882880), // SUBv8i8
7637 UINT64_C(3243249720), // SUDOT_VG2_M2ZZI_BToS
7638 UINT64_C(3240104984), // SUDOT_VG2_M2ZZ_BToS
7639 UINT64_C(3243282488), // SUDOT_VG4_M4ZZI_BToS
7640 UINT64_C(3241153560), // SUDOT_VG4_M4ZZ_BToS
7641 UINT64_C(1151343616), // SUDOT_ZZZI
7642 UINT64_C(1325461504), // SUDOTlanev16i8
7643 UINT64_C(251719680), // SUDOTlanev8i8
7644 UINT64_C(3238002708), // SUMLALL_MZZI_BtoS
7645 UINT64_C(3239051312), // SUMLALL_VG2_M2ZZI_BtoS
7646 UINT64_C(3240099860), // SUMLALL_VG2_M2ZZ_BtoS
7647 UINT64_C(3239084080), // SUMLALL_VG4_M4ZZI_BtoS
7648 UINT64_C(3241148436), // SUMLALL_VG4_M4ZZ_BtoS
7649 UINT64_C(2150662656), // SUMOP4A_M2Z2Z_BToS
7650 UINT64_C(2700083720), // SUMOP4A_M2Z2Z_HtoD
7651 UINT64_C(2149614080), // SUMOP4A_M2ZZ_BToS
7652 UINT64_C(2699035144), // SUMOP4A_M2ZZ_HtoD
7653 UINT64_C(2150662144), // SUMOP4A_MZ2Z_BToS
7654 UINT64_C(2700083208), // SUMOP4A_MZ2Z_HtoD
7655 UINT64_C(2149613568), // SUMOP4A_MZZ_BToS
7656 UINT64_C(2699034632), // SUMOP4A_MZZ_HtoD
7657 UINT64_C(2150662672), // SUMOP4S_M2Z2Z_BToS
7658 UINT64_C(2700083736), // SUMOP4S_M2Z2Z_HtoD
7659 UINT64_C(2149614096), // SUMOP4S_M2ZZ_BToS
7660 UINT64_C(2699035160), // SUMOP4S_M2ZZ_HtoD
7661 UINT64_C(2150662160), // SUMOP4S_MZ2Z_BToS
7662 UINT64_C(2700083224), // SUMOP4S_MZ2Z_HtoD
7663 UINT64_C(2149613584), // SUMOP4S_MZZ_BToS
7664 UINT64_C(2699034648), // SUMOP4S_MZZ_HtoD
7665 UINT64_C(2699034624), // SUMOPA_MPPZZ_D
7666 UINT64_C(2694840320), // SUMOPA_MPPZZ_S
7667 UINT64_C(2699034640), // SUMOPS_MPPZZ_D
7668 UINT64_C(2694840336), // SUMOPS_MPPZZ_S
7669 UINT64_C(99694592), // SUNPKHI_ZZ_D
7670 UINT64_C(91305984), // SUNPKHI_ZZ_H
7671 UINT64_C(95500288), // SUNPKHI_ZZ_S
7672 UINT64_C(99629056), // SUNPKLO_ZZ_D
7673 UINT64_C(91240448), // SUNPKLO_ZZ_H
7674 UINT64_C(95434752), // SUNPKLO_ZZ_S
7675 UINT64_C(3253067776), // SUNPK_VG2_2ZZ_D
7676 UINT64_C(3244679168), // SUNPK_VG2_2ZZ_H
7677 UINT64_C(3248873472), // SUNPK_VG2_2ZZ_S
7678 UINT64_C(3254116352), // SUNPK_VG4_4Z2Z_D
7679 UINT64_C(3245727744), // SUNPK_VG4_4Z2Z_H
7680 UINT64_C(3249922048), // SUNPK_VG4_4Z2Z_S
7681 UINT64_C(1142718464), // SUQADD_ZPmZ_B
7682 UINT64_C(1155301376), // SUQADD_ZPmZ_D
7683 UINT64_C(1146912768), // SUQADD_ZPmZ_H
7684 UINT64_C(1151107072), // SUQADD_ZPmZ_S
7685 UINT64_C(1310734336), // SUQADDv16i8
7686 UINT64_C(1583364096), // SUQADDv1i16
7687 UINT64_C(1587558400), // SUQADDv1i32
7688 UINT64_C(1591752704), // SUQADDv1i64
7689 UINT64_C(1579169792), // SUQADDv1i8
7690 UINT64_C(245381120), // SUQADDv2i32
7691 UINT64_C(1323317248), // SUQADDv2i64
7692 UINT64_C(241186816), // SUQADDv4i16
7693 UINT64_C(1319122944), // SUQADDv4i32
7694 UINT64_C(1314928640), // SUQADDv8i16
7695 UINT64_C(236992512), // SUQADDv8i8
7696 UINT64_C(2153807872), // SUTMOPA_M2ZZZI_BtoS
7697 UINT64_C(3243278392), // SUVDOT_VG4_M4ZZI_BToS
7698 UINT64_C(3556769793), // SVC
7699 UINT64_C(3243245600), // SVDOT_VG2_M2ZZI_HtoS
7700 UINT64_C(3243278368), // SVDOT_VG4_M4ZZI_BtoS
7701 UINT64_C(3251669000), // SVDOT_VG4_M4ZZI_HtoD
7702 UINT64_C(950042624), // SWPAB
7703 UINT64_C(2023784448), // SWPAH
7704 UINT64_C(954236928), // SWPALB
7705 UINT64_C(2027978752), // SWPALH
7706 UINT64_C(3101720576), // SWPALW
7707 UINT64_C(4175462400), // SWPALX
7708 UINT64_C(3097526272), // SWPAW
7709 UINT64_C(4171268096), // SWPAX
7710 UINT64_C(941654016), // SWPB
7711 UINT64_C(2015395840), // SWPH
7712 UINT64_C(945848320), // SWPLB
7713 UINT64_C(2019590144), // SWPLH
7714 UINT64_C(3093331968), // SWPLW
7715 UINT64_C(4167073792), // SWPLX
7716 UINT64_C(421560320), // SWPP
7717 UINT64_C(429948928), // SWPPA
7718 UINT64_C(434143232), // SWPPAL
7719 UINT64_C(425754624), // SWPPL
7720 UINT64_C(434144256), // SWPTALW
7721 UINT64_C(1507886080), // SWPTALX
7722 UINT64_C(429949952), // SWPTAW
7723 UINT64_C(1503691776), // SWPTAX
7724 UINT64_C(425755648), // SWPTLW
7725 UINT64_C(1499497472), // SWPTLX
7726 UINT64_C(421561344), // SWPTW
7727 UINT64_C(1495303168), // SWPTX
7728 UINT64_C(3089137664), // SWPW
7729 UINT64_C(4162879488), // SWPX
7730 UINT64_C(80781312), // SXTB_ZPmZ_D
7731 UINT64_C(72392704), // SXTB_ZPmZ_H
7732 UINT64_C(76587008), // SXTB_ZPmZ_S
7733 UINT64_C(79732736), // SXTB_ZPzZ_D
7734 UINT64_C(71344128), // SXTB_ZPzZ_H
7735 UINT64_C(75538432), // SXTB_ZPzZ_S
7736 UINT64_C(80912384), // SXTH_ZPmZ_D
7737 UINT64_C(76718080), // SXTH_ZPmZ_S
7738 UINT64_C(79863808), // SXTH_ZPzZ_D
7739 UINT64_C(75669504), // SXTH_ZPzZ_S
7740 UINT64_C(81043456), // SXTW_ZPmZ_D
7741 UINT64_C(79994880), // SXTW_ZPzZ_D
7742 UINT64_C(3576168448), // SYSLxt
7743 UINT64_C(3578265600), // SYSPxt
7744 UINT64_C(3578265631), // SYSPxt_XZR
7745 UINT64_C(3574071296), // SYSxt
7746 UINT64_C(1140914176), // TBLQ_ZZZ_B
7747 UINT64_C(1153497088), // TBLQ_ZZZ_D
7748 UINT64_C(1145108480), // TBLQ_ZZZ_H
7749 UINT64_C(1149302784), // TBLQ_ZZZ_S
7750 UINT64_C(85993472), // TBL_ZZZZ_B
7751 UINT64_C(98576384), // TBL_ZZZZ_D
7752 UINT64_C(90187776), // TBL_ZZZZ_H
7753 UINT64_C(94382080), // TBL_ZZZZ_S
7754 UINT64_C(85995520), // TBL_ZZZ_B
7755 UINT64_C(98578432), // TBL_ZZZ_D
7756 UINT64_C(90189824), // TBL_ZZZ_H
7757 UINT64_C(94384128), // TBL_ZZZ_S
7758 UINT64_C(1308647424), // TBLv16i8Four
7759 UINT64_C(1308622848), // TBLv16i8One
7760 UINT64_C(1308639232), // TBLv16i8Three
7761 UINT64_C(1308631040), // TBLv16i8Two
7762 UINT64_C(234905600), // TBLv8i8Four
7763 UINT64_C(234881024), // TBLv8i8One
7764 UINT64_C(234897408), // TBLv8i8Three
7765 UINT64_C(234889216), // TBLv8i8Two
7766 UINT64_C(922746880), // TBNZW
7767 UINT64_C(3070230528), // TBNZX
7768 UINT64_C(85996544), // TBXQ_ZZZ_B
7769 UINT64_C(98579456), // TBXQ_ZZZ_D
7770 UINT64_C(90190848), // TBXQ_ZZZ_H
7771 UINT64_C(94385152), // TBXQ_ZZZ_S
7772 UINT64_C(85994496), // TBX_ZZZ_B
7773 UINT64_C(98577408), // TBX_ZZZ_D
7774 UINT64_C(90188800), // TBX_ZZZ_H
7775 UINT64_C(94383104), // TBX_ZZZ_S
7776 UINT64_C(1308651520), // TBXv16i8Four
7777 UINT64_C(1308626944), // TBXv16i8One
7778 UINT64_C(1308643328), // TBXv16i8Three
7779 UINT64_C(1308635136), // TBXv16i8Two
7780 UINT64_C(234909696), // TBXv8i8Four
7781 UINT64_C(234885120), // TBXv8i8One
7782 UINT64_C(234901504), // TBXv8i8Three
7783 UINT64_C(234893312), // TBXv8i8Two
7784 UINT64_C(905969664), // TBZW
7785 UINT64_C(3053453312), // TBZX
7786 UINT64_C(3563061248), // TCANCEL
7787 UINT64_C(3573756031), // TCOMMIT
7788 UINT64_C(3574297312), // TRCIT
7789 UINT64_C(86003712), // TRN1_PPP_B
7790 UINT64_C(98586624), // TRN1_PPP_D
7791 UINT64_C(90198016), // TRN1_PPP_H
7792 UINT64_C(94392320), // TRN1_PPP_S
7793 UINT64_C(86011904), // TRN1_ZZZ_B
7794 UINT64_C(98594816), // TRN1_ZZZ_D
7795 UINT64_C(90206208), // TRN1_ZZZ_H
7796 UINT64_C(94377984), // TRN1_ZZZ_Q
7797 UINT64_C(94400512), // TRN1_ZZZ_S
7798 UINT64_C(1308633088), // TRN1v16i8
7799 UINT64_C(243279872), // TRN1v2i32
7800 UINT64_C(1321216000), // TRN1v2i64
7801 UINT64_C(239085568), // TRN1v4i16
7802 UINT64_C(1317021696), // TRN1v4i32
7803 UINT64_C(1312827392), // TRN1v8i16
7804 UINT64_C(234891264), // TRN1v8i8
7805 UINT64_C(86004736), // TRN2_PPP_B
7806 UINT64_C(98587648), // TRN2_PPP_D
7807 UINT64_C(90199040), // TRN2_PPP_H
7808 UINT64_C(94393344), // TRN2_PPP_S
7809 UINT64_C(86012928), // TRN2_ZZZ_B
7810 UINT64_C(98595840), // TRN2_ZZZ_D
7811 UINT64_C(90207232), // TRN2_ZZZ_H
7812 UINT64_C(94379008), // TRN2_ZZZ_Q
7813 UINT64_C(94401536), // TRN2_ZZZ_S
7814 UINT64_C(1308649472), // TRN2v16i8
7815 UINT64_C(243296256), // TRN2v2i32
7816 UINT64_C(1321232384), // TRN2v2i64
7817 UINT64_C(239101952), // TRN2v4i16
7818 UINT64_C(1317038080), // TRN2v4i32
7819 UINT64_C(1312843776), // TRN2v8i16
7820 UINT64_C(234907648), // TRN2v8i8
7821 UINT64_C(3573752415), // TSB
7822 UINT64_C(3575853152), // TSTART
7823 UINT64_C(3575853408), // TTEST
7824 UINT64_C(1170262016), // UABALB_ZZZ_D
7825 UINT64_C(1161873408), // UABALB_ZZZ_H
7826 UINT64_C(1166067712), // UABALB_ZZZ_S
7827 UINT64_C(1170263040), // UABALT_ZZZ_D
7828 UINT64_C(1161874432), // UABALT_ZZZ_H
7829 UINT64_C(1166068736), // UABALT_ZZZ_S
7830 UINT64_C(1847611392), // UABALv16i8_v8i16
7831 UINT64_C(782258176), // UABALv2i32_v2i64
7832 UINT64_C(778063872), // UABALv4i16_v4i32
7833 UINT64_C(1856000000), // UABALv4i32_v2i64
7834 UINT64_C(1851805696), // UABALv8i16_v4i32
7835 UINT64_C(773869568), // UABALv8i8_v8i16
7836 UINT64_C(1157692416), // UABA_ZZZ_B
7837 UINT64_C(1170275328), // UABA_ZZZ_D
7838 UINT64_C(1161886720), // UABA_ZZZ_H
7839 UINT64_C(1166081024), // UABA_ZZZ_S
7840 UINT64_C(1847622656), // UABAv16i8
7841 UINT64_C(782269440), // UABAv2i32
7842 UINT64_C(778075136), // UABAv4i16
7843 UINT64_C(1856011264), // UABAv4i32
7844 UINT64_C(1851816960), // UABAv8i16
7845 UINT64_C(773880832), // UABAv8i8
7846 UINT64_C(1170225152), // UABDLB_ZZZ_D
7847 UINT64_C(1161836544), // UABDLB_ZZZ_H
7848 UINT64_C(1166030848), // UABDLB_ZZZ_S
7849 UINT64_C(1170226176), // UABDLT_ZZZ_D
7850 UINT64_C(1161837568), // UABDLT_ZZZ_H
7851 UINT64_C(1166031872), // UABDLT_ZZZ_S
7852 UINT64_C(1847619584), // UABDLv16i8_v8i16
7853 UINT64_C(782266368), // UABDLv2i32_v2i64
7854 UINT64_C(778072064), // UABDLv4i16_v4i32
7855 UINT64_C(1856008192), // UABDLv4i32_v2i64
7856 UINT64_C(1851813888), // UABDLv8i16_v4i32
7857 UINT64_C(773877760), // UABDLv8i8_v8i16
7858 UINT64_C(67960832), // UABD_ZPmZ_B
7859 UINT64_C(80543744), // UABD_ZPmZ_D
7860 UINT64_C(72155136), // UABD_ZPmZ_H
7861 UINT64_C(76349440), // UABD_ZPmZ_S
7862 UINT64_C(1847620608), // UABDv16i8
7863 UINT64_C(782267392), // UABDv2i32
7864 UINT64_C(778073088), // UABDv4i16
7865 UINT64_C(1856009216), // UABDv4i32
7866 UINT64_C(1851814912), // UABDv8i16
7867 UINT64_C(773878784), // UABDv8i8
7868 UINT64_C(1153802240), // UADALP_ZPmZ_D
7869 UINT64_C(1145413632), // UADALP_ZPmZ_H
7870 UINT64_C(1149607936), // UADALP_ZPmZ_S
7871 UINT64_C(1847617536), // UADALPv16i8_v8i16
7872 UINT64_C(782264320), // UADALPv2i32_v1i64
7873 UINT64_C(778070016), // UADALPv4i16_v2i32
7874 UINT64_C(1856006144), // UADALPv4i32_v2i64
7875 UINT64_C(1851811840), // UADALPv8i16_v4i32
7876 UINT64_C(773875712), // UADALPv8i8_v4i16
7877 UINT64_C(1170212864), // UADDLB_ZZZ_D
7878 UINT64_C(1161824256), // UADDLB_ZZZ_H
7879 UINT64_C(1166018560), // UADDLB_ZZZ_S
7880 UINT64_C(1847601152), // UADDLPv16i8_v8i16
7881 UINT64_C(782247936), // UADDLPv2i32_v1i64
7882 UINT64_C(778053632), // UADDLPv4i16_v2i32
7883 UINT64_C(1855989760), // UADDLPv4i32_v2i64
7884 UINT64_C(1851795456), // UADDLPv8i16_v4i32
7885 UINT64_C(773859328), // UADDLPv8i8_v4i16
7886 UINT64_C(1170213888), // UADDLT_ZZZ_D
7887 UINT64_C(1161825280), // UADDLT_ZZZ_H
7888 UINT64_C(1166019584), // UADDLT_ZZZ_S
7889 UINT64_C(1848653824), // UADDLVv16i8v
7890 UINT64_C(779106304), // UADDLVv4i16v
7891 UINT64_C(1857042432), // UADDLVv4i32v
7892 UINT64_C(1852848128), // UADDLVv8i16v
7893 UINT64_C(774912000), // UADDLVv8i8v
7894 UINT64_C(1847590912), // UADDLv16i8_v8i16
7895 UINT64_C(782237696), // UADDLv2i32_v2i64
7896 UINT64_C(778043392), // UADDLv4i16_v4i32
7897 UINT64_C(1855979520), // UADDLv4i32_v2i64
7898 UINT64_C(1851785216), // UADDLv8i16_v4i32
7899 UINT64_C(773849088), // UADDLv8i8_v8i16
7900 UINT64_C(67182592), // UADDV_VPZ_B
7901 UINT64_C(79765504), // UADDV_VPZ_D
7902 UINT64_C(71376896), // UADDV_VPZ_H
7903 UINT64_C(75571200), // UADDV_VPZ_S
7904 UINT64_C(1170229248), // UADDWB_ZZZ_D
7905 UINT64_C(1161840640), // UADDWB_ZZZ_H
7906 UINT64_C(1166034944), // UADDWB_ZZZ_S
7907 UINT64_C(1170230272), // UADDWT_ZZZ_D
7908 UINT64_C(1161841664), // UADDWT_ZZZ_H
7909 UINT64_C(1166035968), // UADDWT_ZZZ_S
7910 UINT64_C(1847595008), // UADDWv16i8_v8i16
7911 UINT64_C(782241792), // UADDWv2i32_v2i64
7912 UINT64_C(778047488), // UADDWv4i16_v4i32
7913 UINT64_C(1855983616), // UADDWv4i32_v2i64
7914 UINT64_C(1851789312), // UADDWv8i16_v4i32
7915 UINT64_C(773853184), // UADDWv8i8_v8i16
7916 UINT64_C(1392508928), // UBFMWri
7917 UINT64_C(3544186880), // UBFMXri
7918 UINT64_C(3240150017), // UCLAMP_VG2_2Z2Z_B
7919 UINT64_C(3252732929), // UCLAMP_VG2_2Z2Z_D
7920 UINT64_C(3244344321), // UCLAMP_VG2_2Z2Z_H
7921 UINT64_C(3248538625), // UCLAMP_VG2_2Z2Z_S
7922 UINT64_C(3240152065), // UCLAMP_VG4_4Z4Z_B
7923 UINT64_C(3252734977), // UCLAMP_VG4_4Z4Z_D
7924 UINT64_C(3244346369), // UCLAMP_VG4_4Z4Z_H
7925 UINT64_C(3248540673), // UCLAMP_VG4_4Z4Z_S
7926 UINT64_C(1140900864), // UCLAMP_ZZZ_B
7927 UINT64_C(1153483776), // UCLAMP_ZZZ_D
7928 UINT64_C(1145095168), // UCLAMP_ZZZ_H
7929 UINT64_C(1149289472), // UCLAMP_ZZZ_S
7930 UINT64_C(511508480), // UCVTFDSr
7931 UINT64_C(2667380736), // UCVTFHDr
7932 UINT64_C(519897088), // UCVTFHSr
7933 UINT64_C(2654797824), // UCVTFSDr
7934 UINT64_C(507740160), // UCVTFSWDri
7935 UINT64_C(516128768), // UCVTFSWHri
7936 UINT64_C(503545856), // UCVTFSWSri
7937 UINT64_C(2655191040), // UCVTFSXDri
7938 UINT64_C(2663579648), // UCVTFSXHri
7939 UINT64_C(2650996736), // UCVTFSXSri
7940 UINT64_C(509804544), // UCVTFUWDri
7941 UINT64_C(518193152), // UCVTFUWHri
7942 UINT64_C(505610240), // UCVTFUWSri
7943 UINT64_C(2657288192), // UCVTFUXDri
7944 UINT64_C(2665676800), // UCVTFUXHri
7945 UINT64_C(2653093888), // UCVTFUXSri
7946 UINT64_C(3240288288), // UCVTF_2Z2Z_StoS
7947 UINT64_C(3241336864), // UCVTF_4Z4Z_StoS
7948 UINT64_C(1708630016), // UCVTF_ZPmZ_DtoD
7949 UINT64_C(1700241408), // UCVTF_ZPmZ_DtoH
7950 UINT64_C(1708498944), // UCVTF_ZPmZ_DtoS
7951 UINT64_C(1699979264), // UCVTF_ZPmZ_HtoH
7952 UINT64_C(1708236800), // UCVTF_ZPmZ_StoD
7953 UINT64_C(1700110336), // UCVTF_ZPmZ_StoH
7954 UINT64_C(1704304640), // UCVTF_ZPmZ_StoS
7955 UINT64_C(1692262400), // UCVTF_ZPzZ_DtoD
7956 UINT64_C(1683873792), // UCVTF_ZPzZ_DtoH
7957 UINT64_C(1692246016), // UCVTF_ZPzZ_DtoS
7958 UINT64_C(1683808256), // UCVTF_ZPzZ_HtoH
7959 UINT64_C(1692180480), // UCVTF_ZPzZ_StoD
7960 UINT64_C(1683857408), // UCVTF_ZPzZ_StoH
7961 UINT64_C(1688051712), // UCVTF_ZPzZ_StoS
7962 UINT64_C(2134959104), // UCVTFd
7963 UINT64_C(2131813376), // UCVTFh
7964 UINT64_C(2132861952), // UCVTFs
7965 UINT64_C(2121914368), // UCVTFv1i16
7966 UINT64_C(2116147200), // UCVTFv1i32
7967 UINT64_C(2120341504), // UCVTFv1i64
7968 UINT64_C(773969920), // UCVTFv2f32
7969 UINT64_C(1851906048), // UCVTFv2f64
7970 UINT64_C(790684672), // UCVTFv2i32_shift
7971 UINT64_C(1866523648), // UCVTFv2i64_shift
7972 UINT64_C(779737088), // UCVTFv4f16
7973 UINT64_C(1847711744), // UCVTFv4f32
7974 UINT64_C(789636096), // UCVTFv4i16_shift
7975 UINT64_C(1864426496), // UCVTFv4i32_shift
7976 UINT64_C(1853478912), // UCVTFv8f16
7977 UINT64_C(1863377920), // UCVTFv8i16_shift
7978 UINT64_C(0), // UDF
7979 UINT64_C(81199104), // UDIVR_ZPmZ_D
7980 UINT64_C(77004800), // UDIVR_ZPmZ_S
7981 UINT64_C(448792576), // UDIVWr
7982 UINT64_C(2596276224), // UDIVXr
7983 UINT64_C(81068032), // UDIV_ZPmZ_D
7984 UINT64_C(76873728), // UDIV_ZPmZ_S
7985 UINT64_C(3248493584), // UDOT_VG2_M2Z2Z_BtoS
7986 UINT64_C(3252687888), // UDOT_VG2_M2Z2Z_HtoD
7987 UINT64_C(3252687896), // UDOT_VG2_M2Z2Z_HtoS
7988 UINT64_C(3243249712), // UDOT_VG2_M2ZZI_BToS
7989 UINT64_C(3243249680), // UDOT_VG2_M2ZZI_HToS
7990 UINT64_C(3251634200), // UDOT_VG2_M2ZZI_HtoD
7991 UINT64_C(3240104976), // UDOT_VG2_M2ZZ_BtoS
7992 UINT64_C(3244299280), // UDOT_VG2_M2ZZ_HtoD
7993 UINT64_C(3244299288), // UDOT_VG2_M2ZZ_HtoS
7994 UINT64_C(3248559120), // UDOT_VG4_M4Z4Z_BtoS
7995 UINT64_C(3252753424), // UDOT_VG4_M4Z4Z_HtoD
7996 UINT64_C(3252753432), // UDOT_VG4_M4Z4Z_HtoS
7997 UINT64_C(3243282480), // UDOT_VG4_M4ZZI_BtoS
7998 UINT64_C(3243282448), // UDOT_VG4_M4ZZI_HToS
7999 UINT64_C(3251666968), // UDOT_VG4_M4ZZI_HtoD
8000 UINT64_C(3241153552), // UDOT_VG4_M4ZZ_BtoS
8001 UINT64_C(3245347856), // UDOT_VG4_M4ZZ_HtoD
8002 UINT64_C(3245347864), // UDOT_VG4_M4ZZ_HtoS
8003 UINT64_C(1155531776), // UDOT_ZZZI_D
8004 UINT64_C(1149291520), // UDOT_ZZZI_HtoS
8005 UINT64_C(1151337472), // UDOT_ZZZI_S
8006 UINT64_C(1153434624), // UDOT_ZZZ_D
8007 UINT64_C(1140902912), // UDOT_ZZZ_HtoS
8008 UINT64_C(1149240320), // UDOT_ZZZ_S
8009 UINT64_C(1870716928), // UDOTlanev16i8
8010 UINT64_C(796975104), // UDOTlanev8i8
8011 UINT64_C(1853920256), // UDOTv16i8
8012 UINT64_C(780178432), // UDOTv8i8
8013 UINT64_C(1141997568), // UHADD_ZPmZ_B
8014 UINT64_C(1154580480), // UHADD_ZPmZ_D
8015 UINT64_C(1146191872), // UHADD_ZPmZ_H
8016 UINT64_C(1150386176), // UHADD_ZPmZ_S
8017 UINT64_C(1847591936), // UHADDv16i8
8018 UINT64_C(782238720), // UHADDv2i32
8019 UINT64_C(778044416), // UHADDv4i16
8020 UINT64_C(1855980544), // UHADDv4i32
8021 UINT64_C(1851786240), // UHADDv8i16
8022 UINT64_C(773850112), // UHADDv8i8
8023 UINT64_C(1142390784), // UHSUBR_ZPmZ_B
8024 UINT64_C(1154973696), // UHSUBR_ZPmZ_D
8025 UINT64_C(1146585088), // UHSUBR_ZPmZ_H
8026 UINT64_C(1150779392), // UHSUBR_ZPmZ_S
8027 UINT64_C(1142128640), // UHSUB_ZPmZ_B
8028 UINT64_C(1154711552), // UHSUB_ZPmZ_D
8029 UINT64_C(1146322944), // UHSUB_ZPmZ_H
8030 UINT64_C(1150517248), // UHSUB_ZPmZ_S
8031 UINT64_C(1847600128), // UHSUBv16i8
8032 UINT64_C(782246912), // UHSUBv2i32
8033 UINT64_C(778052608), // UHSUBv4i16
8034 UINT64_C(1855988736), // UHSUBv4i32
8035 UINT64_C(1851794432), // UHSUBv8i16
8036 UINT64_C(773858304), // UHSUBv8i8
8037 UINT64_C(2610954240), // UMADDLrrr
8038 UINT64_C(1142267904), // UMAXP_ZPmZ_B
8039 UINT64_C(1154850816), // UMAXP_ZPmZ_D
8040 UINT64_C(1146462208), // UMAXP_ZPmZ_H
8041 UINT64_C(1150656512), // UMAXP_ZPmZ_S
8042 UINT64_C(1847632896), // UMAXPv16i8
8043 UINT64_C(782279680), // UMAXPv2i32
8044 UINT64_C(778085376), // UMAXPv4i16
8045 UINT64_C(1856021504), // UMAXPv4i32
8046 UINT64_C(1851827200), // UMAXPv8i16
8047 UINT64_C(773891072), // UMAXPv8i8
8048 UINT64_C(67969024), // UMAXQV_VPZ_B
8049 UINT64_C(80551936), // UMAXQV_VPZ_D
8050 UINT64_C(72163328), // UMAXQV_VPZ_H
8051 UINT64_C(76357632), // UMAXQV_VPZ_S
8052 UINT64_C(67706880), // UMAXV_VPZ_B
8053 UINT64_C(80289792), // UMAXV_VPZ_D
8054 UINT64_C(71901184), // UMAXV_VPZ_H
8055 UINT64_C(76095488), // UMAXV_VPZ_S
8056 UINT64_C(1848682496), // UMAXVv16i8v
8057 UINT64_C(779134976), // UMAXVv4i16v
8058 UINT64_C(1857071104), // UMAXVv4i32v
8059 UINT64_C(1852876800), // UMAXVv8i16v
8060 UINT64_C(774940672), // UMAXVv8i8v
8061 UINT64_C(298057728), // UMAXWri
8062 UINT64_C(448816128), // UMAXWrr
8063 UINT64_C(2445541376), // UMAXXri
8064 UINT64_C(2596299776), // UMAXXrr
8065 UINT64_C(3240144897), // UMAX_VG2_2Z2Z_B
8066 UINT64_C(3252727809), // UMAX_VG2_2Z2Z_D
8067 UINT64_C(3244339201), // UMAX_VG2_2Z2Z_H
8068 UINT64_C(3248533505), // UMAX_VG2_2Z2Z_S
8069 UINT64_C(3240140801), // UMAX_VG2_2ZZ_B
8070 UINT64_C(3252723713), // UMAX_VG2_2ZZ_D
8071 UINT64_C(3244335105), // UMAX_VG2_2ZZ_H
8072 UINT64_C(3248529409), // UMAX_VG2_2ZZ_S
8073 UINT64_C(3240146945), // UMAX_VG4_4Z4Z_B
8074 UINT64_C(3252729857), // UMAX_VG4_4Z4Z_D
8075 UINT64_C(3244341249), // UMAX_VG4_4Z4Z_H
8076 UINT64_C(3248535553), // UMAX_VG4_4Z4Z_S
8077 UINT64_C(3240142849), // UMAX_VG4_4ZZ_B
8078 UINT64_C(3252725761), // UMAX_VG4_4ZZ_D
8079 UINT64_C(3244337153), // UMAX_VG4_4ZZ_H
8080 UINT64_C(3248531457), // UMAX_VG4_4ZZ_S
8081 UINT64_C(623493120), // UMAX_ZI_B
8082 UINT64_C(636076032), // UMAX_ZI_D
8083 UINT64_C(627687424), // UMAX_ZI_H
8084 UINT64_C(631881728), // UMAX_ZI_S
8085 UINT64_C(67698688), // UMAX_ZPmZ_B
8086 UINT64_C(80281600), // UMAX_ZPmZ_D
8087 UINT64_C(71892992), // UMAX_ZPmZ_H
8088 UINT64_C(76087296), // UMAX_ZPmZ_S
8089 UINT64_C(1847616512), // UMAXv16i8
8090 UINT64_C(782263296), // UMAXv2i32
8091 UINT64_C(778068992), // UMAXv4i16
8092 UINT64_C(1856005120), // UMAXv4i32
8093 UINT64_C(1851810816), // UMAXv8i16
8094 UINT64_C(773874688), // UMAXv8i8
8095 UINT64_C(1142398976), // UMINP_ZPmZ_B
8096 UINT64_C(1154981888), // UMINP_ZPmZ_D
8097 UINT64_C(1146593280), // UMINP_ZPmZ_H
8098 UINT64_C(1150787584), // UMINP_ZPmZ_S
8099 UINT64_C(1847634944), // UMINPv16i8
8100 UINT64_C(782281728), // UMINPv2i32
8101 UINT64_C(778087424), // UMINPv4i16
8102 UINT64_C(1856023552), // UMINPv4i32
8103 UINT64_C(1851829248), // UMINPv8i16
8104 UINT64_C(773893120), // UMINPv8i8
8105 UINT64_C(68100096), // UMINQV_VPZ_B
8106 UINT64_C(80683008), // UMINQV_VPZ_D
8107 UINT64_C(72294400), // UMINQV_VPZ_H
8108 UINT64_C(76488704), // UMINQV_VPZ_S
8109 UINT64_C(67837952), // UMINV_VPZ_B
8110 UINT64_C(80420864), // UMINV_VPZ_D
8111 UINT64_C(72032256), // UMINV_VPZ_H
8112 UINT64_C(76226560), // UMINV_VPZ_S
8113 UINT64_C(1848748032), // UMINVv16i8v
8114 UINT64_C(779200512), // UMINVv4i16v
8115 UINT64_C(1857136640), // UMINVv4i32v
8116 UINT64_C(1852942336), // UMINVv8i16v
8117 UINT64_C(775006208), // UMINVv8i8v
8118 UINT64_C(298582016), // UMINWri
8119 UINT64_C(448818176), // UMINWrr
8120 UINT64_C(2446065664), // UMINXri
8121 UINT64_C(2596301824), // UMINXrr
8122 UINT64_C(3240144929), // UMIN_VG2_2Z2Z_B
8123 UINT64_C(3252727841), // UMIN_VG2_2Z2Z_D
8124 UINT64_C(3244339233), // UMIN_VG2_2Z2Z_H
8125 UINT64_C(3248533537), // UMIN_VG2_2Z2Z_S
8126 UINT64_C(3240140833), // UMIN_VG2_2ZZ_B
8127 UINT64_C(3252723745), // UMIN_VG2_2ZZ_D
8128 UINT64_C(3244335137), // UMIN_VG2_2ZZ_H
8129 UINT64_C(3248529441), // UMIN_VG2_2ZZ_S
8130 UINT64_C(3240146977), // UMIN_VG4_4Z4Z_B
8131 UINT64_C(3252729889), // UMIN_VG4_4Z4Z_D
8132 UINT64_C(3244341281), // UMIN_VG4_4Z4Z_H
8133 UINT64_C(3248535585), // UMIN_VG4_4Z4Z_S
8134 UINT64_C(3240142881), // UMIN_VG4_4ZZ_B
8135 UINT64_C(3252725793), // UMIN_VG4_4ZZ_D
8136 UINT64_C(3244337185), // UMIN_VG4_4ZZ_H
8137 UINT64_C(3248531489), // UMIN_VG4_4ZZ_S
8138 UINT64_C(623624192), // UMIN_ZI_B
8139 UINT64_C(636207104), // UMIN_ZI_D
8140 UINT64_C(627818496), // UMIN_ZI_H
8141 UINT64_C(632012800), // UMIN_ZI_S
8142 UINT64_C(67829760), // UMIN_ZPmZ_B
8143 UINT64_C(80412672), // UMIN_ZPmZ_D
8144 UINT64_C(72024064), // UMIN_ZPmZ_H
8145 UINT64_C(76218368), // UMIN_ZPmZ_S
8146 UINT64_C(1847618560), // UMINv16i8
8147 UINT64_C(782265344), // UMINv2i32
8148 UINT64_C(778071040), // UMINv4i16
8149 UINT64_C(1856007168), // UMINv4i32
8150 UINT64_C(1851812864), // UMINv8i16
8151 UINT64_C(773876736), // UMINv8i8
8152 UINT64_C(1155567616), // UMLALB_ZZZI_D
8153 UINT64_C(1151373312), // UMLALB_ZZZI_S
8154 UINT64_C(1153452032), // UMLALB_ZZZ_D
8155 UINT64_C(1145063424), // UMLALB_ZZZ_H
8156 UINT64_C(1149257728), // UMLALB_ZZZ_S
8157 UINT64_C(3238002704), // UMLALL_MZZI_BtoS
8158 UINT64_C(3246391312), // UMLALL_MZZI_HtoD
8159 UINT64_C(3240100880), // UMLALL_MZZ_BtoS
8160 UINT64_C(3244295184), // UMLALL_MZZ_HtoD
8161 UINT64_C(3248488464), // UMLALL_VG2_M2Z2Z_BtoS
8162 UINT64_C(3252682768), // UMLALL_VG2_M2Z2Z_HtoD
8163 UINT64_C(3239051280), // UMLALL_VG2_M2ZZI_BtoS
8164 UINT64_C(3247439888), // UMLALL_VG2_M2ZZI_HtoD
8165 UINT64_C(3240099856), // UMLALL_VG2_M2ZZ_BtoS
8166 UINT64_C(3244294160), // UMLALL_VG2_M2ZZ_HtoD
8167 UINT64_C(3248554000), // UMLALL_VG4_M4Z4Z_BtoS
8168 UINT64_C(3252748304), // UMLALL_VG4_M4Z4Z_HtoD
8169 UINT64_C(3239084048), // UMLALL_VG4_M4ZZI_BtoS
8170 UINT64_C(3247472656), // UMLALL_VG4_M4ZZI_HtoD
8171 UINT64_C(3241148432), // UMLALL_VG4_M4ZZ_BtoS
8172 UINT64_C(3245342736), // UMLALL_VG4_M4ZZ_HtoD
8173 UINT64_C(1155568640), // UMLALT_ZZZI_D
8174 UINT64_C(1151374336), // UMLALT_ZZZI_S
8175 UINT64_C(1153453056), // UMLALT_ZZZ_D
8176 UINT64_C(1145064448), // UMLALT_ZZZ_H
8177 UINT64_C(1149258752), // UMLALT_ZZZ_S
8178 UINT64_C(3250589712), // UMLAL_MZZI_HtoS
8179 UINT64_C(3244297232), // UMLAL_MZZ_HtoS
8180 UINT64_C(3252684816), // UMLAL_VG2_M2Z2Z_HtoS
8181 UINT64_C(3251638288), // UMLAL_VG2_M2ZZI_S
8182 UINT64_C(3244296208), // UMLAL_VG2_M2ZZ_HtoS
8183 UINT64_C(3252750352), // UMLAL_VG4_M4Z4Z_HtoS
8184 UINT64_C(3251671056), // UMLAL_VG4_M4ZZI_HtoS
8185 UINT64_C(3245344784), // UMLAL_VG4_M4ZZ_HtoS
8186 UINT64_C(1847623680), // UMLALv16i8_v8i16
8187 UINT64_C(796925952), // UMLALv2i32_indexed
8188 UINT64_C(782270464), // UMLALv2i32_v2i64
8189 UINT64_C(792731648), // UMLALv4i16_indexed
8190 UINT64_C(778076160), // UMLALv4i16_v4i32
8191 UINT64_C(1870667776), // UMLALv4i32_indexed
8192 UINT64_C(1856012288), // UMLALv4i32_v2i64
8193 UINT64_C(1866473472), // UMLALv8i16_indexed
8194 UINT64_C(1851817984), // UMLALv8i16_v4i32
8195 UINT64_C(773881856), // UMLALv8i8_v8i16
8196 UINT64_C(1155575808), // UMLSLB_ZZZI_D
8197 UINT64_C(1151381504), // UMLSLB_ZZZI_S
8198 UINT64_C(1153456128), // UMLSLB_ZZZ_D
8199 UINT64_C(1145067520), // UMLSLB_ZZZ_H
8200 UINT64_C(1149261824), // UMLSLB_ZZZ_S
8201 UINT64_C(3238002712), // UMLSLL_MZZI_BtoS
8202 UINT64_C(3246391320), // UMLSLL_MZZI_HtoD
8203 UINT64_C(3240100888), // UMLSLL_MZZ_BtoS
8204 UINT64_C(3244295192), // UMLSLL_MZZ_HtoD
8205 UINT64_C(3248488472), // UMLSLL_VG2_M2Z2Z_BtoS
8206 UINT64_C(3252682776), // UMLSLL_VG2_M2Z2Z_HtoD
8207 UINT64_C(3239051288), // UMLSLL_VG2_M2ZZI_BtoS
8208 UINT64_C(3247439896), // UMLSLL_VG2_M2ZZI_HtoD
8209 UINT64_C(3240099864), // UMLSLL_VG2_M2ZZ_BtoS
8210 UINT64_C(3244294168), // UMLSLL_VG2_M2ZZ_HtoD
8211 UINT64_C(3248554008), // UMLSLL_VG4_M4Z4Z_BtoS
8212 UINT64_C(3252748312), // UMLSLL_VG4_M4Z4Z_HtoD
8213 UINT64_C(3239084056), // UMLSLL_VG4_M4ZZI_BtoS
8214 UINT64_C(3247472664), // UMLSLL_VG4_M4ZZI_HtoD
8215 UINT64_C(3241148440), // UMLSLL_VG4_M4ZZ_BtoS
8216 UINT64_C(3245342744), // UMLSLL_VG4_M4ZZ_HtoD
8217 UINT64_C(1155576832), // UMLSLT_ZZZI_D
8218 UINT64_C(1151382528), // UMLSLT_ZZZI_S
8219 UINT64_C(1153457152), // UMLSLT_ZZZ_D
8220 UINT64_C(1145068544), // UMLSLT_ZZZ_H
8221 UINT64_C(1149262848), // UMLSLT_ZZZ_S
8222 UINT64_C(3250589720), // UMLSL_MZZI_HtoS
8223 UINT64_C(3244297240), // UMLSL_MZZ_HtoS
8224 UINT64_C(3252684824), // UMLSL_VG2_M2Z2Z_HtoS
8225 UINT64_C(3251638296), // UMLSL_VG2_M2ZZI_S
8226 UINT64_C(3244296216), // UMLSL_VG2_M2ZZ_HtoS
8227 UINT64_C(3252750360), // UMLSL_VG4_M4Z4Z_HtoS
8228 UINT64_C(3251671064), // UMLSL_VG4_M4ZZI_HtoS
8229 UINT64_C(3245344792), // UMLSL_VG4_M4ZZ_HtoS
8230 UINT64_C(1847631872), // UMLSLv16i8_v8i16
8231 UINT64_C(796942336), // UMLSLv2i32_indexed
8232 UINT64_C(782278656), // UMLSLv2i32_v2i64
8233 UINT64_C(792748032), // UMLSLv4i16_indexed
8234 UINT64_C(778084352), // UMLSLv4i16_v4i32
8235 UINT64_C(1870684160), // UMLSLv4i32_indexed
8236 UINT64_C(1856020480), // UMLSLv4i32_v2i64
8237 UINT64_C(1866489856), // UMLSLv8i16_indexed
8238 UINT64_C(1851826176), // UMLSLv8i16_v4i32
8239 UINT64_C(773890048), // UMLSLv8i8_v8i16
8240 UINT64_C(1853924352), // UMMLA
8241 UINT64_C(1170249728), // UMMLA_ZZZ
8242 UINT64_C(2167439872), // UMOP4A_M2Z2Z_BToS
8243 UINT64_C(2165342728), // UMOP4A_M2Z2Z_HToS
8244 UINT64_C(2716860936), // UMOP4A_M2Z2Z_HtoD
8245 UINT64_C(2166391296), // UMOP4A_M2ZZ_BToS
8246 UINT64_C(2164294152), // UMOP4A_M2ZZ_HToS
8247 UINT64_C(2715812360), // UMOP4A_M2ZZ_HtoD
8248 UINT64_C(2167439360), // UMOP4A_MZ2Z_BToS
8249 UINT64_C(2165342216), // UMOP4A_MZ2Z_HToS
8250 UINT64_C(2716860424), // UMOP4A_MZ2Z_HtoD
8251 UINT64_C(2166390784), // UMOP4A_MZZ_BToS
8252 UINT64_C(2164293640), // UMOP4A_MZZ_HToS
8253 UINT64_C(2715811848), // UMOP4A_MZZ_HtoD
8254 UINT64_C(2167439888), // UMOP4S_M2Z2Z_BToS
8255 UINT64_C(2165342744), // UMOP4S_M2Z2Z_HToS
8256 UINT64_C(2716860952), // UMOP4S_M2Z2Z_HtoD
8257 UINT64_C(2166391312), // UMOP4S_M2ZZ_BToS
8258 UINT64_C(2164294168), // UMOP4S_M2ZZ_HToS
8259 UINT64_C(2715812376), // UMOP4S_M2ZZ_HtoD
8260 UINT64_C(2167439376), // UMOP4S_MZ2Z_BToS
8261 UINT64_C(2165342232), // UMOP4S_MZ2Z_HToS
8262 UINT64_C(2716860440), // UMOP4S_MZ2Z_HtoD
8263 UINT64_C(2166390800), // UMOP4S_MZZ_BToS
8264 UINT64_C(2164293656), // UMOP4S_MZZ_HToS
8265 UINT64_C(2715811864), // UMOP4S_MZZ_HtoD
8266 UINT64_C(2715811840), // UMOPA_MPPZZ_D
8267 UINT64_C(2709520392), // UMOPA_MPPZZ_HtoS
8268 UINT64_C(2711617536), // UMOPA_MPPZZ_S
8269 UINT64_C(2715811856), // UMOPS_MPPZZ_D
8270 UINT64_C(2709520408), // UMOPS_MPPZZ_HtoS
8271 UINT64_C(2711617552), // UMOPS_MPPZZ_S
8272 UINT64_C(235027456), // UMOVvi16
8273 UINT64_C(235027456), // UMOVvi16_idx0
8274 UINT64_C(235158528), // UMOVvi32
8275 UINT64_C(235158528), // UMOVvi32_idx0
8276 UINT64_C(1309162496), // UMOVvi64
8277 UINT64_C(1309162496), // UMOVvi64_idx0
8278 UINT64_C(234961920), // UMOVvi8
8279 UINT64_C(234961920), // UMOVvi8_idx0
8280 UINT64_C(2610987008), // UMSUBLrrr
8281 UINT64_C(68354048), // UMULH_ZPmZ_B
8282 UINT64_C(80936960), // UMULH_ZPmZ_D
8283 UINT64_C(72548352), // UMULH_ZPmZ_H
8284 UINT64_C(76742656), // UMULH_ZPmZ_S
8285 UINT64_C(69233664), // UMULH_ZZZ_B
8286 UINT64_C(81816576), // UMULH_ZZZ_D
8287 UINT64_C(73427968), // UMULH_ZZZ_H
8288 UINT64_C(77622272), // UMULH_ZZZ_S
8289 UINT64_C(2613083136), // UMULHrr
8290 UINT64_C(1155584000), // UMULLB_ZZZI_D
8291 UINT64_C(1151389696), // UMULLB_ZZZI_S
8292 UINT64_C(1170241536), // UMULLB_ZZZ_D
8293 UINT64_C(1161852928), // UMULLB_ZZZ_H
8294 UINT64_C(1166047232), // UMULLB_ZZZ_S
8295 UINT64_C(1155585024), // UMULLT_ZZZI_D
8296 UINT64_C(1151390720), // UMULLT_ZZZI_S
8297 UINT64_C(1170242560), // UMULLT_ZZZ_D
8298 UINT64_C(1161853952), // UMULLT_ZZZ_H
8299 UINT64_C(1166048256), // UMULLT_ZZZ_S
8300 UINT64_C(1847640064), // UMULLv16i8_v8i16
8301 UINT64_C(796958720), // UMULLv2i32_indexed
8302 UINT64_C(782286848), // UMULLv2i32_v2i64
8303 UINT64_C(792764416), // UMULLv4i16_indexed
8304 UINT64_C(778092544), // UMULLv4i16_v4i32
8305 UINT64_C(1870700544), // UMULLv4i32_indexed
8306 UINT64_C(1856028672), // UMULLv4i32_v2i64
8307 UINT64_C(1866506240), // UMULLv8i16_indexed
8308 UINT64_C(1851834368), // UMULLv8i16_v4i32
8309 UINT64_C(773898240), // UMULLv8i8_v8i16
8310 UINT64_C(623230976), // UQADD_ZI_B
8311 UINT64_C(635813888), // UQADD_ZI_D
8312 UINT64_C(627425280), // UQADD_ZI_H
8313 UINT64_C(631619584), // UQADD_ZI_S
8314 UINT64_C(1142521856), // UQADD_ZPmZ_B
8315 UINT64_C(1155104768), // UQADD_ZPmZ_D
8316 UINT64_C(1146716160), // UQADD_ZPmZ_H
8317 UINT64_C(1150910464), // UQADD_ZPmZ_S
8318 UINT64_C(69211136), // UQADD_ZZZ_B
8319 UINT64_C(81794048), // UQADD_ZZZ_D
8320 UINT64_C(73405440), // UQADD_ZZZ_H
8321 UINT64_C(77599744), // UQADD_ZZZ_S
8322 UINT64_C(1847593984), // UQADDv16i8
8323 UINT64_C(2120223744), // UQADDv1i16
8324 UINT64_C(2124418048), // UQADDv1i32
8325 UINT64_C(2128612352), // UQADDv1i64
8326 UINT64_C(2116029440), // UQADDv1i8
8327 UINT64_C(782240768), // UQADDv2i32
8328 UINT64_C(1860176896), // UQADDv2i64
8329 UINT64_C(778046464), // UQADDv4i16
8330 UINT64_C(1855982592), // UQADDv4i32
8331 UINT64_C(1851788288), // UQADDv8i16
8332 UINT64_C(773852160), // UQADDv8i8
8333 UINT64_C(1160857600), // UQCVTN_Z2Z_StoH
8334 UINT64_C(3249791072), // UQCVTN_Z4Z_DtoH
8335 UINT64_C(3241402464), // UQCVTN_Z4Z_StoB
8336 UINT64_C(3240353824), // UQCVT_Z2Z_StoH
8337 UINT64_C(3249791008), // UQCVT_Z4Z_DtoH
8338 UINT64_C(3241402400), // UQCVT_Z4Z_StoB
8339 UINT64_C(69270528), // UQDECB_WPiI
8340 UINT64_C(70319104), // UQDECB_XPiI
8341 UINT64_C(81853440), // UQDECD_WPiI
8342 UINT64_C(82902016), // UQDECD_XPiI
8343 UINT64_C(81841152), // UQDECD_ZPiI
8344 UINT64_C(73464832), // UQDECH_WPiI
8345 UINT64_C(74513408), // UQDECH_XPiI
8346 UINT64_C(73452544), // UQDECH_ZPiI
8347 UINT64_C(623609856), // UQDECP_WP_B
8348 UINT64_C(636192768), // UQDECP_WP_D
8349 UINT64_C(627804160), // UQDECP_WP_H
8350 UINT64_C(631998464), // UQDECP_WP_S
8351 UINT64_C(623610880), // UQDECP_XP_B
8352 UINT64_C(636193792), // UQDECP_XP_D
8353 UINT64_C(627805184), // UQDECP_XP_H
8354 UINT64_C(631999488), // UQDECP_XP_S
8355 UINT64_C(636190720), // UQDECP_ZP_D
8356 UINT64_C(627802112), // UQDECP_ZP_H
8357 UINT64_C(631996416), // UQDECP_ZP_S
8358 UINT64_C(77659136), // UQDECW_WPiI
8359 UINT64_C(78707712), // UQDECW_XPiI
8360 UINT64_C(77646848), // UQDECW_ZPiI
8361 UINT64_C(69268480), // UQINCB_WPiI
8362 UINT64_C(70317056), // UQINCB_XPiI
8363 UINT64_C(81851392), // UQINCD_WPiI
8364 UINT64_C(82899968), // UQINCD_XPiI
8365 UINT64_C(81839104), // UQINCD_ZPiI
8366 UINT64_C(73462784), // UQINCH_WPiI
8367 UINT64_C(74511360), // UQINCH_XPiI
8368 UINT64_C(73450496), // UQINCH_ZPiI
8369 UINT64_C(623478784), // UQINCP_WP_B
8370 UINT64_C(636061696), // UQINCP_WP_D
8371 UINT64_C(627673088), // UQINCP_WP_H
8372 UINT64_C(631867392), // UQINCP_WP_S
8373 UINT64_C(623479808), // UQINCP_XP_B
8374 UINT64_C(636062720), // UQINCP_XP_D
8375 UINT64_C(627674112), // UQINCP_XP_H
8376 UINT64_C(631868416), // UQINCP_XP_S
8377 UINT64_C(636059648), // UQINCP_ZP_D
8378 UINT64_C(627671040), // UQINCP_ZP_H
8379 UINT64_C(631865344), // UQINCP_ZP_S
8380 UINT64_C(77657088), // UQINCW_WPiI
8381 UINT64_C(78705664), // UQINCW_XPiI
8382 UINT64_C(77644800), // UQINCW_ZPiI
8383 UINT64_C(1141866496), // UQRSHLR_ZPmZ_B
8384 UINT64_C(1154449408), // UQRSHLR_ZPmZ_D
8385 UINT64_C(1146060800), // UQRSHLR_ZPmZ_H
8386 UINT64_C(1150255104), // UQRSHLR_ZPmZ_S
8387 UINT64_C(1141604352), // UQRSHL_ZPmZ_B
8388 UINT64_C(1154187264), // UQRSHL_ZPmZ_D
8389 UINT64_C(1145798656), // UQRSHL_ZPmZ_H
8390 UINT64_C(1149992960), // UQRSHL_ZPmZ_S
8391 UINT64_C(1847614464), // UQRSHLv16i8
8392 UINT64_C(2120244224), // UQRSHLv1i16
8393 UINT64_C(2124438528), // UQRSHLv1i32
8394 UINT64_C(2128632832), // UQRSHLv1i64
8395 UINT64_C(2116049920), // UQRSHLv1i8
8396 UINT64_C(782261248), // UQRSHLv2i32
8397 UINT64_C(1860197376), // UQRSHLv2i64
8398 UINT64_C(778066944), // UQRSHLv4i16
8399 UINT64_C(1856003072), // UQRSHLv4i32
8400 UINT64_C(1851808768), // UQRSHLv8i16
8401 UINT64_C(773872640), // UQRSHLv8i8
8402 UINT64_C(1160263680), // UQRSHRNB_ZZI_B
8403 UINT64_C(1160787968), // UQRSHRNB_ZZI_H
8404 UINT64_C(1163933696), // UQRSHRNB_ZZI_S
8405 UINT64_C(1160264704), // UQRSHRNT_ZZI_B
8406 UINT64_C(1160788992), // UQRSHRNT_ZZI_H
8407 UINT64_C(1163934720), // UQRSHRNT_ZZI_S
8408 UINT64_C(3244350496), // UQRSHRN_VG4_Z4ZI_B
8409 UINT64_C(3248544800), // UQRSHRN_VG4_Z4ZI_H
8410 UINT64_C(1169176576), // UQRSHRN_Z2ZI_StoH
8411 UINT64_C(2131270656), // UQRSHRNb
8412 UINT64_C(2131794944), // UQRSHRNh
8413 UINT64_C(2132843520), // UQRSHRNs
8414 UINT64_C(1862835200), // UQRSHRNv16i8_shift
8415 UINT64_C(790666240), // UQRSHRNv2i32_shift
8416 UINT64_C(789617664), // UQRSHRNv4i16_shift
8417 UINT64_C(1864408064), // UQRSHRNv4i32_shift
8418 UINT64_C(1863359488), // UQRSHRNv8i16_shift
8419 UINT64_C(789093376), // UQRSHRNv8i8_shift
8420 UINT64_C(3252737056), // UQRSHR_VG2_Z2ZI_H
8421 UINT64_C(3244349472), // UQRSHR_VG4_Z4ZI_B
8422 UINT64_C(3248543776), // UQRSHR_VG4_Z4ZI_H
8423 UINT64_C(1141735424), // UQSHLR_ZPmZ_B
8424 UINT64_C(1154318336), // UQSHLR_ZPmZ_D
8425 UINT64_C(1145929728), // UQSHLR_ZPmZ_H
8426 UINT64_C(1150124032), // UQSHLR_ZPmZ_S
8427 UINT64_C(67600640), // UQSHL_ZPmI_B
8428 UINT64_C(75988992), // UQSHL_ZPmI_D
8429 UINT64_C(67600896), // UQSHL_ZPmI_H
8430 UINT64_C(71794688), // UQSHL_ZPmI_S
8431 UINT64_C(1141473280), // UQSHL_ZPmZ_B
8432 UINT64_C(1154056192), // UQSHL_ZPmZ_D
8433 UINT64_C(1145667584), // UQSHL_ZPmZ_H
8434 UINT64_C(1149861888), // UQSHL_ZPmZ_S
8435 UINT64_C(2131260416), // UQSHLb
8436 UINT64_C(2134930432), // UQSHLd
8437 UINT64_C(2131784704), // UQSHLh
8438 UINT64_C(2132833280), // UQSHLs
8439 UINT64_C(1847610368), // UQSHLv16i8
8440 UINT64_C(1862824960), // UQSHLv16i8_shift
8441 UINT64_C(2120240128), // UQSHLv1i16
8442 UINT64_C(2124434432), // UQSHLv1i32
8443 UINT64_C(2128628736), // UQSHLv1i64
8444 UINT64_C(2116045824), // UQSHLv1i8
8445 UINT64_C(782257152), // UQSHLv2i32
8446 UINT64_C(790656000), // UQSHLv2i32_shift
8447 UINT64_C(1860193280), // UQSHLv2i64
8448 UINT64_C(1866494976), // UQSHLv2i64_shift
8449 UINT64_C(778062848), // UQSHLv4i16
8450 UINT64_C(789607424), // UQSHLv4i16_shift
8451 UINT64_C(1855998976), // UQSHLv4i32
8452 UINT64_C(1864397824), // UQSHLv4i32_shift
8453 UINT64_C(1851804672), // UQSHLv8i16
8454 UINT64_C(1863349248), // UQSHLv8i16_shift
8455 UINT64_C(773868544), // UQSHLv8i8
8456 UINT64_C(789083136), // UQSHLv8i8_shift
8457 UINT64_C(1160261632), // UQSHRNB_ZZI_B
8458 UINT64_C(1160785920), // UQSHRNB_ZZI_H
8459 UINT64_C(1163931648), // UQSHRNB_ZZI_S
8460 UINT64_C(1160262656), // UQSHRNT_ZZI_B
8461 UINT64_C(1160786944), // UQSHRNT_ZZI_H
8462 UINT64_C(1163932672), // UQSHRNT_ZZI_S
8463 UINT64_C(2131268608), // UQSHRNb
8464 UINT64_C(2131792896), // UQSHRNh
8465 UINT64_C(2132841472), // UQSHRNs
8466 UINT64_C(1862833152), // UQSHRNv16i8_shift
8467 UINT64_C(790664192), // UQSHRNv2i32_shift
8468 UINT64_C(789615616), // UQSHRNv4i16_shift
8469 UINT64_C(1864406016), // UQSHRNv4i32_shift
8470 UINT64_C(1863357440), // UQSHRNv8i16_shift
8471 UINT64_C(789091328), // UQSHRNv8i8_shift
8472 UINT64_C(1142915072), // UQSUBR_ZPmZ_B
8473 UINT64_C(1155497984), // UQSUBR_ZPmZ_D
8474 UINT64_C(1147109376), // UQSUBR_ZPmZ_H
8475 UINT64_C(1151303680), // UQSUBR_ZPmZ_S
8476 UINT64_C(623362048), // UQSUB_ZI_B
8477 UINT64_C(635944960), // UQSUB_ZI_D
8478 UINT64_C(627556352), // UQSUB_ZI_H
8479 UINT64_C(631750656), // UQSUB_ZI_S
8480 UINT64_C(1142652928), // UQSUB_ZPmZ_B
8481 UINT64_C(1155235840), // UQSUB_ZPmZ_D
8482 UINT64_C(1146847232), // UQSUB_ZPmZ_H
8483 UINT64_C(1151041536), // UQSUB_ZPmZ_S
8484 UINT64_C(69213184), // UQSUB_ZZZ_B
8485 UINT64_C(81796096), // UQSUB_ZZZ_D
8486 UINT64_C(73407488), // UQSUB_ZZZ_H
8487 UINT64_C(77601792), // UQSUB_ZZZ_S
8488 UINT64_C(1847602176), // UQSUBv16i8
8489 UINT64_C(2120231936), // UQSUBv1i16
8490 UINT64_C(2124426240), // UQSUBv1i32
8491 UINT64_C(2128620544), // UQSUBv1i64
8492 UINT64_C(2116037632), // UQSUBv1i8
8493 UINT64_C(782248960), // UQSUBv2i32
8494 UINT64_C(1860185088), // UQSUBv2i64
8495 UINT64_C(778054656), // UQSUBv4i16
8496 UINT64_C(1855990784), // UQSUBv4i32
8497 UINT64_C(1851796480), // UQSUBv8i16
8498 UINT64_C(773860352), // UQSUBv8i8
8499 UINT64_C(1160267776), // UQXTNB_ZZ_B
8500 UINT64_C(1160792064), // UQXTNB_ZZ_H
8501 UINT64_C(1163937792), // UQXTNB_ZZ_S
8502 UINT64_C(1160268800), // UQXTNT_ZZ_B
8503 UINT64_C(1160793088), // UQXTNT_ZZ_H
8504 UINT64_C(1163938816), // UQXTNT_ZZ_S
8505 UINT64_C(1847674880), // UQXTNv16i8
8506 UINT64_C(2120304640), // UQXTNv1i16
8507 UINT64_C(2124498944), // UQXTNv1i32
8508 UINT64_C(2116110336), // UQXTNv1i8
8509 UINT64_C(782321664), // UQXTNv2i32
8510 UINT64_C(778127360), // UQXTNv4i16
8511 UINT64_C(1856063488), // UQXTNv4i32
8512 UINT64_C(1851869184), // UQXTNv8i16
8513 UINT64_C(773933056), // UQXTNv8i8
8514 UINT64_C(1149280256), // URECPE_ZPmZ_S
8515 UINT64_C(1149411328), // URECPE_ZPzZ_S
8516 UINT64_C(245483520), // URECPEv2i32
8517 UINT64_C(1319225344), // URECPEv4i32
8518 UINT64_C(1142259712), // URHADD_ZPmZ_B
8519 UINT64_C(1154842624), // URHADD_ZPmZ_D
8520 UINT64_C(1146454016), // URHADD_ZPmZ_H
8521 UINT64_C(1150648320), // URHADD_ZPmZ_S
8522 UINT64_C(1847596032), // URHADDv16i8
8523 UINT64_C(782242816), // URHADDv2i32
8524 UINT64_C(778048512), // URHADDv4i16
8525 UINT64_C(1855984640), // URHADDv4i32
8526 UINT64_C(1851790336), // URHADDv8i16
8527 UINT64_C(773854208), // URHADDv8i8
8528 UINT64_C(1141342208), // URSHLR_ZPmZ_B
8529 UINT64_C(1153925120), // URSHLR_ZPmZ_D
8530 UINT64_C(1145536512), // URSHLR_ZPmZ_H
8531 UINT64_C(1149730816), // URSHLR_ZPmZ_S
8532 UINT64_C(3240145441), // URSHL_VG2_2Z2Z_B
8533 UINT64_C(3252728353), // URSHL_VG2_2Z2Z_D
8534 UINT64_C(3244339745), // URSHL_VG2_2Z2Z_H
8535 UINT64_C(3248534049), // URSHL_VG2_2Z2Z_S
8536 UINT64_C(3240141345), // URSHL_VG2_2ZZ_B
8537 UINT64_C(3252724257), // URSHL_VG2_2ZZ_D
8538 UINT64_C(3244335649), // URSHL_VG2_2ZZ_H
8539 UINT64_C(3248529953), // URSHL_VG2_2ZZ_S
8540 UINT64_C(3240147489), // URSHL_VG4_4Z4Z_B
8541 UINT64_C(3252730401), // URSHL_VG4_4Z4Z_D
8542 UINT64_C(3244341793), // URSHL_VG4_4Z4Z_H
8543 UINT64_C(3248536097), // URSHL_VG4_4Z4Z_S
8544 UINT64_C(3240143393), // URSHL_VG4_4ZZ_B
8545 UINT64_C(3252726305), // URSHL_VG4_4ZZ_D
8546 UINT64_C(3244337697), // URSHL_VG4_4ZZ_H
8547 UINT64_C(3248532001), // URSHL_VG4_4ZZ_S
8548 UINT64_C(1141080064), // URSHL_ZPmZ_B
8549 UINT64_C(1153662976), // URSHL_ZPmZ_D
8550 UINT64_C(1145274368), // URSHL_ZPmZ_H
8551 UINT64_C(1149468672), // URSHL_ZPmZ_S
8552 UINT64_C(1847612416), // URSHLv16i8
8553 UINT64_C(2128630784), // URSHLv1i64
8554 UINT64_C(782259200), // URSHLv2i32
8555 UINT64_C(1860195328), // URSHLv2i64
8556 UINT64_C(778064896), // URSHLv4i16
8557 UINT64_C(1856001024), // URSHLv4i32
8558 UINT64_C(1851806720), // URSHLv8i16
8559 UINT64_C(773870592), // URSHLv8i8
8560 UINT64_C(67993856), // URSHR_ZPmI_B
8561 UINT64_C(76382208), // URSHR_ZPmI_D
8562 UINT64_C(67994112), // URSHR_ZPmI_H
8563 UINT64_C(72187904), // URSHR_ZPmI_S
8564 UINT64_C(2134909952), // URSHRd
8565 UINT64_C(1862804480), // URSHRv16i8_shift
8566 UINT64_C(790635520), // URSHRv2i32_shift
8567 UINT64_C(1866474496), // URSHRv2i64_shift
8568 UINT64_C(789586944), // URSHRv4i16_shift
8569 UINT64_C(1864377344), // URSHRv4i32_shift
8570 UINT64_C(1863328768), // URSHRv8i16_shift
8571 UINT64_C(789062656), // URSHRv8i8_shift
8572 UINT64_C(1149345792), // URSQRTE_ZPmZ_S
8573 UINT64_C(1149476864), // URSQRTE_ZPzZ_S
8574 UINT64_C(782354432), // URSQRTEv2i32
8575 UINT64_C(1856096256), // URSQRTEv4i32
8576 UINT64_C(1158212608), // URSRA_ZZI_B
8577 UINT64_C(1166076928), // URSRA_ZZI_D
8578 UINT64_C(1158736896), // URSRA_ZZI_H
8579 UINT64_C(1161882624), // URSRA_ZZI_S
8580 UINT64_C(2134914048), // URSRAd
8581 UINT64_C(1862808576), // URSRAv16i8_shift
8582 UINT64_C(790639616), // URSRAv2i32_shift
8583 UINT64_C(1866478592), // URSRAv2i64_shift
8584 UINT64_C(789591040), // URSRAv4i16_shift
8585 UINT64_C(1864381440), // URSRAv4i32_shift
8586 UINT64_C(1863332864), // URSRAv8i16_shift
8587 UINT64_C(789066752), // URSRAv8i8_shift
8588 UINT64_C(3248493576), // USDOT_VG2_M2Z2Z_BToS
8589 UINT64_C(3243249704), // USDOT_VG2_M2ZZI_BToS
8590 UINT64_C(3240104968), // USDOT_VG2_M2ZZ_BToS
8591 UINT64_C(3248559112), // USDOT_VG4_M4Z4Z_BToS
8592 UINT64_C(3243282472), // USDOT_VG4_M4ZZI_BToS
8593 UINT64_C(3241153544), // USDOT_VG4_M4ZZ_BToS
8594 UINT64_C(1149270016), // USDOT_ZZZ
8595 UINT64_C(1151342592), // USDOT_ZZZI
8596 UINT64_C(1333850112), // USDOTlanev16i8
8597 UINT64_C(260108288), // USDOTlanev8i8
8598 UINT64_C(1317051392), // USDOTv16i8
8599 UINT64_C(243309568), // USDOTv8i8
8600 UINT64_C(1161865216), // USHLLB_ZZI_D
8601 UINT64_C(1158195200), // USHLLB_ZZI_H
8602 UINT64_C(1158719488), // USHLLB_ZZI_S
8603 UINT64_C(1161866240), // USHLLT_ZZI_D
8604 UINT64_C(1158196224), // USHLLT_ZZI_H
8605 UINT64_C(1158720512), // USHLLT_ZZI_S
8606 UINT64_C(1862837248), // USHLLv16i8_shift
8607 UINT64_C(790668288), // USHLLv2i32_shift
8608 UINT64_C(789619712), // USHLLv4i16_shift
8609 UINT64_C(1864410112), // USHLLv4i32_shift
8610 UINT64_C(1863361536), // USHLLv8i16_shift
8611 UINT64_C(789095424), // USHLLv8i8_shift
8612 UINT64_C(1847608320), // USHLv16i8
8613 UINT64_C(2128626688), // USHLv1i64
8614 UINT64_C(782255104), // USHLv2i32
8615 UINT64_C(1860191232), // USHLv2i64
8616 UINT64_C(778060800), // USHLv4i16
8617 UINT64_C(1855996928), // USHLv4i32
8618 UINT64_C(1851802624), // USHLv8i16
8619 UINT64_C(773866496), // USHLv8i8
8620 UINT64_C(2134901760), // USHRd
8621 UINT64_C(1862796288), // USHRv16i8_shift
8622 UINT64_C(790627328), // USHRv2i32_shift
8623 UINT64_C(1866466304), // USHRv2i64_shift
8624 UINT64_C(789578752), // USHRv4i16_shift
8625 UINT64_C(1864369152), // USHRv4i32_shift
8626 UINT64_C(1863320576), // USHRv8i16_shift
8627 UINT64_C(789054464), // USHRv8i8_shift
8628 UINT64_C(3238002692), // USMLALL_MZZI_BtoS
8629 UINT64_C(3240100868), // USMLALL_MZZ_BtoS
8630 UINT64_C(3248488452), // USMLALL_VG2_M2Z2Z_BtoS
8631 UINT64_C(3239051296), // USMLALL_VG2_M2ZZI_BtoS
8632 UINT64_C(3240099844), // USMLALL_VG2_M2ZZ_BtoS
8633 UINT64_C(3248553988), // USMLALL_VG4_M4Z4Z_BtoS
8634 UINT64_C(3239084064), // USMLALL_VG4_M4ZZI_BtoS
8635 UINT64_C(3241148420), // USMLALL_VG4_M4ZZ_BtoS
8636 UINT64_C(1317055488), // USMMLA
8637 UINT64_C(1166055424), // USMMLA_ZZZ
8638 UINT64_C(2165342720), // USMOP4A_M2Z2Z_BToS
8639 UINT64_C(2714763784), // USMOP4A_M2Z2Z_HtoD
8640 UINT64_C(2164294144), // USMOP4A_M2ZZ_BToS
8641 UINT64_C(2713715208), // USMOP4A_M2ZZ_HtoD
8642 UINT64_C(2165342208), // USMOP4A_MZ2Z_BToS
8643 UINT64_C(2714763272), // USMOP4A_MZ2Z_HtoD
8644 UINT64_C(2164293632), // USMOP4A_MZZ_BToS
8645 UINT64_C(2713714696), // USMOP4A_MZZ_HtoD
8646 UINT64_C(2165342736), // USMOP4S_M2Z2Z_BToS
8647 UINT64_C(2714763800), // USMOP4S_M2Z2Z_HtoD
8648 UINT64_C(2164294160), // USMOP4S_M2ZZ_BToS
8649 UINT64_C(2713715224), // USMOP4S_M2ZZ_HtoD
8650 UINT64_C(2165342224), // USMOP4S_MZ2Z_BToS
8651 UINT64_C(2714763288), // USMOP4S_MZ2Z_HtoD
8652 UINT64_C(2164293648), // USMOP4S_MZZ_BToS
8653 UINT64_C(2713714712), // USMOP4S_MZZ_HtoD
8654 UINT64_C(2713714688), // USMOPA_MPPZZ_D
8655 UINT64_C(2709520384), // USMOPA_MPPZZ_S
8656 UINT64_C(2713714704), // USMOPS_MPPZZ_D
8657 UINT64_C(2709520400), // USMOPS_MPPZZ_S
8658 UINT64_C(1142784000), // USQADD_ZPmZ_B
8659 UINT64_C(1155366912), // USQADD_ZPmZ_D
8660 UINT64_C(1146978304), // USQADD_ZPmZ_H
8661 UINT64_C(1151172608), // USQADD_ZPmZ_S
8662 UINT64_C(1847605248), // USQADDv16i8
8663 UINT64_C(2120235008), // USQADDv1i16
8664 UINT64_C(2124429312), // USQADDv1i32
8665 UINT64_C(2128623616), // USQADDv1i64
8666 UINT64_C(2116040704), // USQADDv1i8
8667 UINT64_C(782252032), // USQADDv2i32
8668 UINT64_C(1860188160), // USQADDv2i64
8669 UINT64_C(778057728), // USQADDv4i16
8670 UINT64_C(1855993856), // USQADDv4i32
8671 UINT64_C(1851799552), // USQADDv8i16
8672 UINT64_C(773863424), // USQADDv8i8
8673 UINT64_C(1158210560), // USRA_ZZI_B
8674 UINT64_C(1166074880), // USRA_ZZI_D
8675 UINT64_C(1158734848), // USRA_ZZI_H
8676 UINT64_C(1161880576), // USRA_ZZI_S
8677 UINT64_C(2134905856), // USRAd
8678 UINT64_C(1862800384), // USRAv16i8_shift
8679 UINT64_C(790631424), // USRAv2i32_shift
8680 UINT64_C(1866470400), // USRAv2i64_shift
8681 UINT64_C(789582848), // USRAv4i16_shift
8682 UINT64_C(1864373248), // USRAv4i32_shift
8683 UINT64_C(1863324672), // USRAv8i16_shift
8684 UINT64_C(789058560), // USRAv8i8_shift
8685 UINT64_C(2168487936), // USTMOPA_M2ZZZI_BtoS
8686 UINT64_C(1170216960), // USUBLB_ZZZ_D
8687 UINT64_C(1161828352), // USUBLB_ZZZ_H
8688 UINT64_C(1166022656), // USUBLB_ZZZ_S
8689 UINT64_C(1170217984), // USUBLT_ZZZ_D
8690 UINT64_C(1161829376), // USUBLT_ZZZ_H
8691 UINT64_C(1166023680), // USUBLT_ZZZ_S
8692 UINT64_C(1847599104), // USUBLv16i8_v8i16
8693 UINT64_C(782245888), // USUBLv2i32_v2i64
8694 UINT64_C(778051584), // USUBLv4i16_v4i32
8695 UINT64_C(1855987712), // USUBLv4i32_v2i64
8696 UINT64_C(1851793408), // USUBLv8i16_v4i32
8697 UINT64_C(773857280), // USUBLv8i8_v8i16
8698 UINT64_C(1170233344), // USUBWB_ZZZ_D
8699 UINT64_C(1161844736), // USUBWB_ZZZ_H
8700 UINT64_C(1166039040), // USUBWB_ZZZ_S
8701 UINT64_C(1170234368), // USUBWT_ZZZ_D
8702 UINT64_C(1161845760), // USUBWT_ZZZ_H
8703 UINT64_C(1166040064), // USUBWT_ZZZ_S
8704 UINT64_C(1847603200), // USUBWv16i8_v8i16
8705 UINT64_C(782249984), // USUBWv2i32_v2i64
8706 UINT64_C(778055680), // USUBWv4i16_v4i32
8707 UINT64_C(1855991808), // USUBWv4i32_v2i64
8708 UINT64_C(1851797504), // USUBWv8i16_v4i32
8709 UINT64_C(773861376), // USUBWv8i8_v8i16
8710 UINT64_C(3243278376), // USVDOT_VG4_M4ZZI_BToS
8711 UINT64_C(2170585088), // UTMOPA_M2ZZZI_BtoS
8712 UINT64_C(2168487944), // UTMOPA_M2ZZZI_HtoS
8713 UINT64_C(99825664), // UUNPKHI_ZZ_D
8714 UINT64_C(91437056), // UUNPKHI_ZZ_H
8715 UINT64_C(95631360), // UUNPKHI_ZZ_S
8716 UINT64_C(99760128), // UUNPKLO_ZZ_D
8717 UINT64_C(91371520), // UUNPKLO_ZZ_H
8718 UINT64_C(95565824), // UUNPKLO_ZZ_S
8719 UINT64_C(3253067777), // UUNPK_VG2_2ZZ_D
8720 UINT64_C(3244679169), // UUNPK_VG2_2ZZ_H
8721 UINT64_C(3248873473), // UUNPK_VG2_2ZZ_S
8722 UINT64_C(3254116353), // UUNPK_VG4_4Z2Z_D
8723 UINT64_C(3245727745), // UUNPK_VG4_4Z2Z_H
8724 UINT64_C(3249922049), // UUNPK_VG4_4Z2Z_S
8725 UINT64_C(3243245616), // UVDOT_VG2_M2ZZI_HtoS
8726 UINT64_C(3243278384), // UVDOT_VG4_M4ZZI_BtoS
8727 UINT64_C(3251669016), // UVDOT_VG4_M4ZZI_HtoD
8728 UINT64_C(80846848), // UXTB_ZPmZ_D
8729 UINT64_C(72458240), // UXTB_ZPmZ_H
8730 UINT64_C(76652544), // UXTB_ZPmZ_S
8731 UINT64_C(79798272), // UXTB_ZPzZ_D
8732 UINT64_C(71409664), // UXTB_ZPzZ_H
8733 UINT64_C(75603968), // UXTB_ZPzZ_S
8734 UINT64_C(80977920), // UXTH_ZPmZ_D
8735 UINT64_C(76783616), // UXTH_ZPmZ_S
8736 UINT64_C(79929344), // UXTH_ZPzZ_D
8737 UINT64_C(75735040), // UXTH_ZPzZ_S
8738 UINT64_C(81108992), // UXTW_ZPmZ_D
8739 UINT64_C(80060416), // UXTW_ZPzZ_D
8740 UINT64_C(86001664), // UZP1_PPP_B
8741 UINT64_C(98584576), // UZP1_PPP_D
8742 UINT64_C(90195968), // UZP1_PPP_H
8743 UINT64_C(94390272), // UZP1_PPP_S
8744 UINT64_C(86009856), // UZP1_ZZZ_B
8745 UINT64_C(98592768), // UZP1_ZZZ_D
8746 UINT64_C(90204160), // UZP1_ZZZ_H
8747 UINT64_C(94373888), // UZP1_ZZZ_Q
8748 UINT64_C(94398464), // UZP1_ZZZ_S
8749 UINT64_C(1308628992), // UZP1v16i8
8750 UINT64_C(243275776), // UZP1v2i32
8751 UINT64_C(1321211904), // UZP1v2i64
8752 UINT64_C(239081472), // UZP1v4i16
8753 UINT64_C(1317017600), // UZP1v4i32
8754 UINT64_C(1312823296), // UZP1v8i16
8755 UINT64_C(234887168), // UZP1v8i8
8756 UINT64_C(86002688), // UZP2_PPP_B
8757 UINT64_C(98585600), // UZP2_PPP_D
8758 UINT64_C(90196992), // UZP2_PPP_H
8759 UINT64_C(94391296), // UZP2_PPP_S
8760 UINT64_C(86010880), // UZP2_ZZZ_B
8761 UINT64_C(98593792), // UZP2_ZZZ_D
8762 UINT64_C(90205184), // UZP2_ZZZ_H
8763 UINT64_C(94374912), // UZP2_ZZZ_Q
8764 UINT64_C(94399488), // UZP2_ZZZ_S
8765 UINT64_C(1308645376), // UZP2v16i8
8766 UINT64_C(243292160), // UZP2v2i32
8767 UINT64_C(1321228288), // UZP2v2i64
8768 UINT64_C(239097856), // UZP2v4i16
8769 UINT64_C(1317033984), // UZP2v4i32
8770 UINT64_C(1312839680), // UZP2v8i16
8771 UINT64_C(234903552), // UZP2v8i8
8772 UINT64_C(1140910080), // UZPQ1_ZZZ_B
8773 UINT64_C(1153492992), // UZPQ1_ZZZ_D
8774 UINT64_C(1145104384), // UZPQ1_ZZZ_H
8775 UINT64_C(1149298688), // UZPQ1_ZZZ_S
8776 UINT64_C(1140911104), // UZPQ2_ZZZ_B
8777 UINT64_C(1153494016), // UZPQ2_ZZZ_D
8778 UINT64_C(1145105408), // UZPQ2_ZZZ_H
8779 UINT64_C(1149299712), // UZPQ2_ZZZ_S
8780 UINT64_C(3240153089), // UZP_VG2_2ZZZ_B
8781 UINT64_C(3252736001), // UZP_VG2_2ZZZ_D
8782 UINT64_C(3244347393), // UZP_VG2_2ZZZ_H
8783 UINT64_C(3240154113), // UZP_VG2_2ZZZ_Q
8784 UINT64_C(3248541697), // UZP_VG2_2ZZZ_S
8785 UINT64_C(3241598978), // UZP_VG4_4Z4Z_B
8786 UINT64_C(3254181890), // UZP_VG4_4Z4Z_D
8787 UINT64_C(3245793282), // UZP_VG4_4Z4Z_H
8788 UINT64_C(3241664514), // UZP_VG4_4Z4Z_Q
8789 UINT64_C(3249987586), // UZP_VG4_4Z4Z_S
8790 UINT64_C(3573747712), // WFET
8791 UINT64_C(3573747744), // WFIT
8792 UINT64_C(622874640), // WHILEGE_2PXX_B
8793 UINT64_C(635457552), // WHILEGE_2PXX_D
8794 UINT64_C(627068944), // WHILEGE_2PXX_H
8795 UINT64_C(631263248), // WHILEGE_2PXX_S
8796 UINT64_C(622870544), // WHILEGE_CXX_B
8797 UINT64_C(635453456), // WHILEGE_CXX_D
8798 UINT64_C(627064848), // WHILEGE_CXX_H
8799 UINT64_C(631259152), // WHILEGE_CXX_S
8800 UINT64_C(622854144), // WHILEGE_PWW_B
8801 UINT64_C(635437056), // WHILEGE_PWW_D
8802 UINT64_C(627048448), // WHILEGE_PWW_H
8803 UINT64_C(631242752), // WHILEGE_PWW_S
8804 UINT64_C(622858240), // WHILEGE_PXX_B
8805 UINT64_C(635441152), // WHILEGE_PXX_D
8806 UINT64_C(627052544), // WHILEGE_PXX_H
8807 UINT64_C(631246848), // WHILEGE_PXX_S
8808 UINT64_C(622874641), // WHILEGT_2PXX_B
8809 UINT64_C(635457553), // WHILEGT_2PXX_D
8810 UINT64_C(627068945), // WHILEGT_2PXX_H
8811 UINT64_C(631263249), // WHILEGT_2PXX_S
8812 UINT64_C(622870552), // WHILEGT_CXX_B
8813 UINT64_C(635453464), // WHILEGT_CXX_D
8814 UINT64_C(627064856), // WHILEGT_CXX_H
8815 UINT64_C(631259160), // WHILEGT_CXX_S
8816 UINT64_C(622854160), // WHILEGT_PWW_B
8817 UINT64_C(635437072), // WHILEGT_PWW_D
8818 UINT64_C(627048464), // WHILEGT_PWW_H
8819 UINT64_C(631242768), // WHILEGT_PWW_S
8820 UINT64_C(622858256), // WHILEGT_PXX_B
8821 UINT64_C(635441168), // WHILEGT_PXX_D
8822 UINT64_C(627052560), // WHILEGT_PXX_H
8823 UINT64_C(631246864), // WHILEGT_PXX_S
8824 UINT64_C(622876689), // WHILEHI_2PXX_B
8825 UINT64_C(635459601), // WHILEHI_2PXX_D
8826 UINT64_C(627070993), // WHILEHI_2PXX_H
8827 UINT64_C(631265297), // WHILEHI_2PXX_S
8828 UINT64_C(622872600), // WHILEHI_CXX_B
8829 UINT64_C(635455512), // WHILEHI_CXX_D
8830 UINT64_C(627066904), // WHILEHI_CXX_H
8831 UINT64_C(631261208), // WHILEHI_CXX_S
8832 UINT64_C(622856208), // WHILEHI_PWW_B
8833 UINT64_C(635439120), // WHILEHI_PWW_D
8834 UINT64_C(627050512), // WHILEHI_PWW_H
8835 UINT64_C(631244816), // WHILEHI_PWW_S
8836 UINT64_C(622860304), // WHILEHI_PXX_B
8837 UINT64_C(635443216), // WHILEHI_PXX_D
8838 UINT64_C(627054608), // WHILEHI_PXX_H
8839 UINT64_C(631248912), // WHILEHI_PXX_S
8840 UINT64_C(622876688), // WHILEHS_2PXX_B
8841 UINT64_C(635459600), // WHILEHS_2PXX_D
8842 UINT64_C(627070992), // WHILEHS_2PXX_H
8843 UINT64_C(631265296), // WHILEHS_2PXX_S
8844 UINT64_C(622872592), // WHILEHS_CXX_B
8845 UINT64_C(635455504), // WHILEHS_CXX_D
8846 UINT64_C(627066896), // WHILEHS_CXX_H
8847 UINT64_C(631261200), // WHILEHS_CXX_S
8848 UINT64_C(622856192), // WHILEHS_PWW_B
8849 UINT64_C(635439104), // WHILEHS_PWW_D
8850 UINT64_C(627050496), // WHILEHS_PWW_H
8851 UINT64_C(631244800), // WHILEHS_PWW_S
8852 UINT64_C(622860288), // WHILEHS_PXX_B
8853 UINT64_C(635443200), // WHILEHS_PXX_D
8854 UINT64_C(627054592), // WHILEHS_PXX_H
8855 UINT64_C(631248896), // WHILEHS_PXX_S
8856 UINT64_C(622875665), // WHILELE_2PXX_B
8857 UINT64_C(635458577), // WHILELE_2PXX_D
8858 UINT64_C(627069969), // WHILELE_2PXX_H
8859 UINT64_C(631264273), // WHILELE_2PXX_S
8860 UINT64_C(622871576), // WHILELE_CXX_B
8861 UINT64_C(635454488), // WHILELE_CXX_D
8862 UINT64_C(627065880), // WHILELE_CXX_H
8863 UINT64_C(631260184), // WHILELE_CXX_S
8864 UINT64_C(622855184), // WHILELE_PWW_B
8865 UINT64_C(635438096), // WHILELE_PWW_D
8866 UINT64_C(627049488), // WHILELE_PWW_H
8867 UINT64_C(631243792), // WHILELE_PWW_S
8868 UINT64_C(622859280), // WHILELE_PXX_B
8869 UINT64_C(635442192), // WHILELE_PXX_D
8870 UINT64_C(627053584), // WHILELE_PXX_H
8871 UINT64_C(631247888), // WHILELE_PXX_S
8872 UINT64_C(622877712), // WHILELO_2PXX_B
8873 UINT64_C(635460624), // WHILELO_2PXX_D
8874 UINT64_C(627072016), // WHILELO_2PXX_H
8875 UINT64_C(631266320), // WHILELO_2PXX_S
8876 UINT64_C(622873616), // WHILELO_CXX_B
8877 UINT64_C(635456528), // WHILELO_CXX_D
8878 UINT64_C(627067920), // WHILELO_CXX_H
8879 UINT64_C(631262224), // WHILELO_CXX_S
8880 UINT64_C(622857216), // WHILELO_PWW_B
8881 UINT64_C(635440128), // WHILELO_PWW_D
8882 UINT64_C(627051520), // WHILELO_PWW_H
8883 UINT64_C(631245824), // WHILELO_PWW_S
8884 UINT64_C(622861312), // WHILELO_PXX_B
8885 UINT64_C(635444224), // WHILELO_PXX_D
8886 UINT64_C(627055616), // WHILELO_PXX_H
8887 UINT64_C(631249920), // WHILELO_PXX_S
8888 UINT64_C(622877713), // WHILELS_2PXX_B
8889 UINT64_C(635460625), // WHILELS_2PXX_D
8890 UINT64_C(627072017), // WHILELS_2PXX_H
8891 UINT64_C(631266321), // WHILELS_2PXX_S
8892 UINT64_C(622873624), // WHILELS_CXX_B
8893 UINT64_C(635456536), // WHILELS_CXX_D
8894 UINT64_C(627067928), // WHILELS_CXX_H
8895 UINT64_C(631262232), // WHILELS_CXX_S
8896 UINT64_C(622857232), // WHILELS_PWW_B
8897 UINT64_C(635440144), // WHILELS_PWW_D
8898 UINT64_C(627051536), // WHILELS_PWW_H
8899 UINT64_C(631245840), // WHILELS_PWW_S
8900 UINT64_C(622861328), // WHILELS_PXX_B
8901 UINT64_C(635444240), // WHILELS_PXX_D
8902 UINT64_C(627055632), // WHILELS_PXX_H
8903 UINT64_C(631249936), // WHILELS_PXX_S
8904 UINT64_C(622875664), // WHILELT_2PXX_B
8905 UINT64_C(635458576), // WHILELT_2PXX_D
8906 UINT64_C(627069968), // WHILELT_2PXX_H
8907 UINT64_C(631264272), // WHILELT_2PXX_S
8908 UINT64_C(622871568), // WHILELT_CXX_B
8909 UINT64_C(635454480), // WHILELT_CXX_D
8910 UINT64_C(627065872), // WHILELT_CXX_H
8911 UINT64_C(631260176), // WHILELT_CXX_S
8912 UINT64_C(622855168), // WHILELT_PWW_B
8913 UINT64_C(635438080), // WHILELT_PWW_D
8914 UINT64_C(627049472), // WHILELT_PWW_H
8915 UINT64_C(631243776), // WHILELT_PWW_S
8916 UINT64_C(622859264), // WHILELT_PXX_B
8917 UINT64_C(635442176), // WHILELT_PXX_D
8918 UINT64_C(627053568), // WHILELT_PXX_H
8919 UINT64_C(631247872), // WHILELT_PXX_S
8920 UINT64_C(622866448), // WHILERW_PXX_B
8921 UINT64_C(635449360), // WHILERW_PXX_D
8922 UINT64_C(627060752), // WHILERW_PXX_H
8923 UINT64_C(631255056), // WHILERW_PXX_S
8924 UINT64_C(622866432), // WHILEWR_PXX_B
8925 UINT64_C(635449344), // WHILEWR_PXX_D
8926 UINT64_C(627060736), // WHILEWR_PXX_H
8927 UINT64_C(631255040), // WHILEWR_PXX_S
8928 UINT64_C(623415296), // WRFFR
8929 UINT64_C(3573563455), // XAFLAG
8930 UINT64_C(3464495104), // XAR
8931 UINT64_C(69743616), // XAR_ZZZI_B
8932 UINT64_C(77607936), // XAR_ZZZI_D
8933 UINT64_C(70267904), // XAR_ZZZI_H
8934 UINT64_C(73413632), // XAR_ZZZI_S
8935 UINT64_C(3670099936), // XPACD
8936 UINT64_C(3670098912), // XPACI
8937 UINT64_C(3573752063), // XPACLRI
8938 UINT64_C(1310795776), // XTNv16i8
8939 UINT64_C(245442560), // XTNv2i32
8940 UINT64_C(241248256), // XTNv4i16
8941 UINT64_C(1319184384), // XTNv4i32
8942 UINT64_C(1314990080), // XTNv8i16
8943 UINT64_C(237053952), // XTNv8i8
8944 UINT64_C(3221749760), // ZERO_M
8945 UINT64_C(3222044672), // ZERO_MXI_2Z
8946 UINT64_C(3222175744), // ZERO_MXI_4Z
8947 UINT64_C(3222077440), // ZERO_MXI_VG2_2Z
8948 UINT64_C(3222208512), // ZERO_MXI_VG2_4Z
8949 UINT64_C(3222011904), // ZERO_MXI_VG2_Z
8950 UINT64_C(3222110208), // ZERO_MXI_VG4_2Z
8951 UINT64_C(3222241280), // ZERO_MXI_VG4_4Z
8952 UINT64_C(3222142976), // ZERO_MXI_VG4_Z
8953 UINT64_C(3225944065), // ZERO_T
8954 UINT64_C(85999616), // ZIP1_PPP_B
8955 UINT64_C(98582528), // ZIP1_PPP_D
8956 UINT64_C(90193920), // ZIP1_PPP_H
8957 UINT64_C(94388224), // ZIP1_PPP_S
8958 UINT64_C(86007808), // ZIP1_ZZZ_B
8959 UINT64_C(98590720), // ZIP1_ZZZ_D
8960 UINT64_C(90202112), // ZIP1_ZZZ_H
8961 UINT64_C(94371840), // ZIP1_ZZZ_Q
8962 UINT64_C(94396416), // ZIP1_ZZZ_S
8963 UINT64_C(1308637184), // ZIP1v16i8
8964 UINT64_C(243283968), // ZIP1v2i32
8965 UINT64_C(1321220096), // ZIP1v2i64
8966 UINT64_C(239089664), // ZIP1v4i16
8967 UINT64_C(1317025792), // ZIP1v4i32
8968 UINT64_C(1312831488), // ZIP1v8i16
8969 UINT64_C(234895360), // ZIP1v8i8
8970 UINT64_C(86000640), // ZIP2_PPP_B
8971 UINT64_C(98583552), // ZIP2_PPP_D
8972 UINT64_C(90194944), // ZIP2_PPP_H
8973 UINT64_C(94389248), // ZIP2_PPP_S
8974 UINT64_C(86008832), // ZIP2_ZZZ_B
8975 UINT64_C(98591744), // ZIP2_ZZZ_D
8976 UINT64_C(90203136), // ZIP2_ZZZ_H
8977 UINT64_C(94372864), // ZIP2_ZZZ_Q
8978 UINT64_C(94397440), // ZIP2_ZZZ_S
8979 UINT64_C(1308653568), // ZIP2v16i8
8980 UINT64_C(243300352), // ZIP2v2i32
8981 UINT64_C(1321236480), // ZIP2v2i64
8982 UINT64_C(239106048), // ZIP2v4i16
8983 UINT64_C(1317042176), // ZIP2v4i32
8984 UINT64_C(1312847872), // ZIP2v8i16
8985 UINT64_C(234911744), // ZIP2v8i8
8986 UINT64_C(1140908032), // ZIPQ1_ZZZ_B
8987 UINT64_C(1153490944), // ZIPQ1_ZZZ_D
8988 UINT64_C(1145102336), // ZIPQ1_ZZZ_H
8989 UINT64_C(1149296640), // ZIPQ1_ZZZ_S
8990 UINT64_C(1140909056), // ZIPQ2_ZZZ_B
8991 UINT64_C(1153491968), // ZIPQ2_ZZZ_D
8992 UINT64_C(1145103360), // ZIPQ2_ZZZ_H
8993 UINT64_C(1149297664), // ZIPQ2_ZZZ_S
8994 UINT64_C(3240153088), // ZIP_VG2_2ZZZ_B
8995 UINT64_C(3252736000), // ZIP_VG2_2ZZZ_D
8996 UINT64_C(3244347392), // ZIP_VG2_2ZZZ_H
8997 UINT64_C(3240154112), // ZIP_VG2_2ZZZ_Q
8998 UINT64_C(3248541696), // ZIP_VG2_2ZZZ_S
8999 UINT64_C(3241598976), // ZIP_VG4_4Z4Z_B
9000 UINT64_C(3254181888), // ZIP_VG4_4Z4Z_D
9001 UINT64_C(3245793280), // ZIP_VG4_4Z4Z_H
9002 UINT64_C(3241664512), // ZIP_VG4_4Z4Z_Q
9003 UINT64_C(3249987584), // ZIP_VG4_4Z4Z_S
9004 UINT64_C(0)
9005 };
9006 const unsigned opcode = MI.getOpcode();
9007 uint64_t Value = InstBits[opcode];
9008 uint64_t op = 0;
9009 (void)op; // suppress warning
9010 switch (opcode) {
9011 case AArch64::AUTIA1716:
9012 case AArch64::AUTIA171615:
9013 case AArch64::AUTIASP:
9014 case AArch64::AUTIAZ:
9015 case AArch64::AUTIB1716:
9016 case AArch64::AUTIB171615:
9017 case AArch64::AUTIBSP:
9018 case AArch64::AUTIBZ:
9019 case AArch64::AXFLAG:
9020 case AArch64::BRB_IALL:
9021 case AArch64::BRB_INJ:
9022 case AArch64::CFINV:
9023 case AArch64::CHKFEAT:
9024 case AArch64::DRPS:
9025 case AArch64::ERET:
9026 case AArch64::ERETAA:
9027 case AArch64::ERETAB:
9028 case AArch64::GCSPOPCX:
9029 case AArch64::GCSPOPX:
9030 case AArch64::GCSPUSHX:
9031 case AArch64::PACIA1716:
9032 case AArch64::PACIA171615:
9033 case AArch64::PACIASP:
9034 case AArch64::PACIASPPC:
9035 case AArch64::PACIAZ:
9036 case AArch64::PACIB1716:
9037 case AArch64::PACIB171615:
9038 case AArch64::PACIBSP:
9039 case AArch64::PACIBSPPC:
9040 case AArch64::PACIBZ:
9041 case AArch64::PACM:
9042 case AArch64::PACNBIASPPC:
9043 case AArch64::PACNBIBSPPC:
9044 case AArch64::RETAA:
9045 case AArch64::RETAB:
9046 case AArch64::SB:
9047 case AArch64::SETFFR:
9048 case AArch64::TCOMMIT:
9049 case AArch64::TSB:
9050 case AArch64::XAFLAG:
9051 case AArch64::XPACLRI:
9052 case AArch64::ZERO_T: {
9053 break;
9054 }
9055 case AArch64::DSBnXS: {
9056 // op: CRm
9057 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9058 op &= UINT64_C(12);
9059 op <<= 8;
9060 Value |= op;
9061 break;
9062 }
9063 case AArch64::CLREX:
9064 case AArch64::DMB:
9065 case AArch64::DSB:
9066 case AArch64::ISB: {
9067 // op: CRm
9068 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9069 op &= UINT64_C(15);
9070 op <<= 8;
9071 Value |= op;
9072 break;
9073 }
9074 case AArch64::PTRUE_C_B:
9075 case AArch64::PTRUE_C_D:
9076 case AArch64::PTRUE_C_H:
9077 case AArch64::PTRUE_C_S: {
9078 // op: PNd
9079 op = EncodePNR_p8to15(MI, OpIdx: 0, Fixups, STI);
9080 op &= UINT64_C(7);
9081 Value |= op;
9082 break;
9083 }
9084 case AArch64::WHILEGE_CXX_B:
9085 case AArch64::WHILEGE_CXX_D:
9086 case AArch64::WHILEGE_CXX_H:
9087 case AArch64::WHILEGE_CXX_S:
9088 case AArch64::WHILEGT_CXX_B:
9089 case AArch64::WHILEGT_CXX_D:
9090 case AArch64::WHILEGT_CXX_H:
9091 case AArch64::WHILEGT_CXX_S:
9092 case AArch64::WHILEHI_CXX_B:
9093 case AArch64::WHILEHI_CXX_D:
9094 case AArch64::WHILEHI_CXX_H:
9095 case AArch64::WHILEHI_CXX_S:
9096 case AArch64::WHILEHS_CXX_B:
9097 case AArch64::WHILEHS_CXX_D:
9098 case AArch64::WHILEHS_CXX_H:
9099 case AArch64::WHILEHS_CXX_S:
9100 case AArch64::WHILELE_CXX_B:
9101 case AArch64::WHILELE_CXX_D:
9102 case AArch64::WHILELE_CXX_H:
9103 case AArch64::WHILELE_CXX_S:
9104 case AArch64::WHILELO_CXX_B:
9105 case AArch64::WHILELO_CXX_D:
9106 case AArch64::WHILELO_CXX_H:
9107 case AArch64::WHILELO_CXX_S:
9108 case AArch64::WHILELS_CXX_B:
9109 case AArch64::WHILELS_CXX_D:
9110 case AArch64::WHILELS_CXX_H:
9111 case AArch64::WHILELS_CXX_S:
9112 case AArch64::WHILELT_CXX_B:
9113 case AArch64::WHILELT_CXX_D:
9114 case AArch64::WHILELT_CXX_H:
9115 case AArch64::WHILELT_CXX_S: {
9116 // op: PNd
9117 op = EncodePNR_p8to15(MI, OpIdx: 0, Fixups, STI);
9118 op &= UINT64_C(7);
9119 Value |= op;
9120 // op: Rn
9121 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9122 op &= UINT64_C(31);
9123 op <<= 5;
9124 Value |= op;
9125 // op: vl
9126 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9127 op &= UINT64_C(1);
9128 op <<= 13;
9129 Value |= op;
9130 // op: Rm
9131 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9132 op &= UINT64_C(31);
9133 op <<= 16;
9134 Value |= op;
9135 break;
9136 }
9137 case AArch64::SEL_VG2_2ZC2Z2Z_B:
9138 case AArch64::SEL_VG2_2ZC2Z2Z_D:
9139 case AArch64::SEL_VG2_2ZC2Z2Z_H:
9140 case AArch64::SEL_VG2_2ZC2Z2Z_S: {
9141 // op: PNg
9142 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
9143 op &= UINT64_C(7);
9144 op <<= 10;
9145 Value |= op;
9146 // op: Zm
9147 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 3, Fixups, STI);
9148 op &= UINT64_C(15);
9149 op <<= 17;
9150 Value |= op;
9151 // op: Zn
9152 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI);
9153 op &= UINT64_C(15);
9154 op <<= 6;
9155 Value |= op;
9156 // op: Zd
9157 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
9158 op &= UINT64_C(15);
9159 op <<= 1;
9160 Value |= op;
9161 break;
9162 }
9163 case AArch64::SEL_VG4_4ZC4Z4Z_B:
9164 case AArch64::SEL_VG4_4ZC4Z4Z_D:
9165 case AArch64::SEL_VG4_4ZC4Z4Z_H:
9166 case AArch64::SEL_VG4_4ZC4Z4Z_S: {
9167 // op: PNg
9168 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
9169 op &= UINT64_C(7);
9170 op <<= 10;
9171 Value |= op;
9172 // op: Zm
9173 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 3, Fixups, STI);
9174 op &= UINT64_C(7);
9175 op <<= 18;
9176 Value |= op;
9177 // op: Zn
9178 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 2, Fixups, STI);
9179 op &= UINT64_C(7);
9180 op <<= 7;
9181 Value |= op;
9182 // op: Zd
9183 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
9184 op &= UINT64_C(7);
9185 op <<= 2;
9186 Value |= op;
9187 break;
9188 }
9189 case AArch64::WHILEGE_2PXX_B:
9190 case AArch64::WHILEGE_2PXX_D:
9191 case AArch64::WHILEGE_2PXX_H:
9192 case AArch64::WHILEGE_2PXX_S:
9193 case AArch64::WHILEGT_2PXX_B:
9194 case AArch64::WHILEGT_2PXX_D:
9195 case AArch64::WHILEGT_2PXX_H:
9196 case AArch64::WHILEGT_2PXX_S:
9197 case AArch64::WHILEHI_2PXX_B:
9198 case AArch64::WHILEHI_2PXX_D:
9199 case AArch64::WHILEHI_2PXX_H:
9200 case AArch64::WHILEHI_2PXX_S:
9201 case AArch64::WHILEHS_2PXX_B:
9202 case AArch64::WHILEHS_2PXX_D:
9203 case AArch64::WHILEHS_2PXX_H:
9204 case AArch64::WHILEHS_2PXX_S:
9205 case AArch64::WHILELE_2PXX_B:
9206 case AArch64::WHILELE_2PXX_D:
9207 case AArch64::WHILELE_2PXX_H:
9208 case AArch64::WHILELE_2PXX_S:
9209 case AArch64::WHILELO_2PXX_B:
9210 case AArch64::WHILELO_2PXX_D:
9211 case AArch64::WHILELO_2PXX_H:
9212 case AArch64::WHILELO_2PXX_S:
9213 case AArch64::WHILELS_2PXX_B:
9214 case AArch64::WHILELS_2PXX_D:
9215 case AArch64::WHILELS_2PXX_H:
9216 case AArch64::WHILELS_2PXX_S:
9217 case AArch64::WHILELT_2PXX_B:
9218 case AArch64::WHILELT_2PXX_D:
9219 case AArch64::WHILELT_2PXX_H:
9220 case AArch64::WHILELT_2PXX_S: {
9221 // op: Pd
9222 op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 0, Fixups, STI);
9223 op &= UINT64_C(7);
9224 op <<= 1;
9225 Value |= op;
9226 // op: Rn
9227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9228 op &= UINT64_C(31);
9229 op <<= 5;
9230 Value |= op;
9231 // op: Rm
9232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9233 op &= UINT64_C(31);
9234 op <<= 16;
9235 Value |= op;
9236 break;
9237 }
9238 case AArch64::PFALSE:
9239 case AArch64::RDFFR_P: {
9240 // op: Pd
9241 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9242 op &= UINT64_C(15);
9243 Value |= op;
9244 break;
9245 }
9246 case AArch64::PEXT_2PCI_B:
9247 case AArch64::PEXT_2PCI_D:
9248 case AArch64::PEXT_2PCI_H:
9249 case AArch64::PEXT_2PCI_S: {
9250 // op: Pd
9251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9252 op &= UINT64_C(15);
9253 Value |= op;
9254 // op: PNn
9255 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
9256 op &= UINT64_C(7);
9257 op <<= 5;
9258 Value |= op;
9259 // op: index
9260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9261 op &= UINT64_C(1);
9262 op <<= 8;
9263 Value |= op;
9264 break;
9265 }
9266 case AArch64::PEXT_PCI_B:
9267 case AArch64::PEXT_PCI_D:
9268 case AArch64::PEXT_PCI_H:
9269 case AArch64::PEXT_PCI_S: {
9270 // op: Pd
9271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9272 op &= UINT64_C(15);
9273 Value |= op;
9274 // op: PNn
9275 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
9276 op &= UINT64_C(7);
9277 op <<= 5;
9278 Value |= op;
9279 // op: index
9280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9281 op &= UINT64_C(3);
9282 op <<= 8;
9283 Value |= op;
9284 break;
9285 }
9286 case AArch64::ANDS_PPzPP:
9287 case AArch64::AND_PPzPP:
9288 case AArch64::BICS_PPzPP:
9289 case AArch64::BIC_PPzPP:
9290 case AArch64::BRKPAS_PPzPP:
9291 case AArch64::BRKPA_PPzPP:
9292 case AArch64::BRKPBS_PPzPP:
9293 case AArch64::BRKPB_PPzPP:
9294 case AArch64::EORS_PPzPP:
9295 case AArch64::EOR_PPzPP:
9296 case AArch64::NANDS_PPzPP:
9297 case AArch64::NAND_PPzPP:
9298 case AArch64::NORS_PPzPP:
9299 case AArch64::NOR_PPzPP:
9300 case AArch64::ORNS_PPzPP:
9301 case AArch64::ORN_PPzPP:
9302 case AArch64::ORRS_PPzPP:
9303 case AArch64::ORR_PPzPP:
9304 case AArch64::SEL_PPPP: {
9305 // op: Pd
9306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9307 op &= UINT64_C(15);
9308 Value |= op;
9309 // op: Pg
9310 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9311 op &= UINT64_C(15);
9312 op <<= 10;
9313 Value |= op;
9314 // op: Pm
9315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9316 op &= UINT64_C(15);
9317 op <<= 16;
9318 Value |= op;
9319 // op: Pn
9320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9321 op &= UINT64_C(15);
9322 op <<= 5;
9323 Value |= op;
9324 break;
9325 }
9326 case AArch64::BRKAS_PPzP:
9327 case AArch64::BRKA_PPzP:
9328 case AArch64::BRKBS_PPzP:
9329 case AArch64::BRKB_PPzP: {
9330 // op: Pd
9331 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9332 op &= UINT64_C(15);
9333 Value |= op;
9334 // op: Pg
9335 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9336 op &= UINT64_C(15);
9337 op <<= 10;
9338 Value |= op;
9339 // op: Pn
9340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9341 op &= UINT64_C(15);
9342 op <<= 5;
9343 Value |= op;
9344 break;
9345 }
9346 case AArch64::RDFFRS_PPz:
9347 case AArch64::RDFFR_PPz: {
9348 // op: Pd
9349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9350 op &= UINT64_C(15);
9351 Value |= op;
9352 // op: Pg
9353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9354 op &= UINT64_C(15);
9355 op <<= 5;
9356 Value |= op;
9357 break;
9358 }
9359 case AArch64::CMPEQ_PPzZZ_B:
9360 case AArch64::CMPEQ_PPzZZ_D:
9361 case AArch64::CMPEQ_PPzZZ_H:
9362 case AArch64::CMPEQ_PPzZZ_S:
9363 case AArch64::CMPEQ_WIDE_PPzZZ_B:
9364 case AArch64::CMPEQ_WIDE_PPzZZ_H:
9365 case AArch64::CMPEQ_WIDE_PPzZZ_S:
9366 case AArch64::CMPGE_PPzZZ_B:
9367 case AArch64::CMPGE_PPzZZ_D:
9368 case AArch64::CMPGE_PPzZZ_H:
9369 case AArch64::CMPGE_PPzZZ_S:
9370 case AArch64::CMPGE_WIDE_PPzZZ_B:
9371 case AArch64::CMPGE_WIDE_PPzZZ_H:
9372 case AArch64::CMPGE_WIDE_PPzZZ_S:
9373 case AArch64::CMPGT_PPzZZ_B:
9374 case AArch64::CMPGT_PPzZZ_D:
9375 case AArch64::CMPGT_PPzZZ_H:
9376 case AArch64::CMPGT_PPzZZ_S:
9377 case AArch64::CMPGT_WIDE_PPzZZ_B:
9378 case AArch64::CMPGT_WIDE_PPzZZ_H:
9379 case AArch64::CMPGT_WIDE_PPzZZ_S:
9380 case AArch64::CMPHI_PPzZZ_B:
9381 case AArch64::CMPHI_PPzZZ_D:
9382 case AArch64::CMPHI_PPzZZ_H:
9383 case AArch64::CMPHI_PPzZZ_S:
9384 case AArch64::CMPHI_WIDE_PPzZZ_B:
9385 case AArch64::CMPHI_WIDE_PPzZZ_H:
9386 case AArch64::CMPHI_WIDE_PPzZZ_S:
9387 case AArch64::CMPHS_PPzZZ_B:
9388 case AArch64::CMPHS_PPzZZ_D:
9389 case AArch64::CMPHS_PPzZZ_H:
9390 case AArch64::CMPHS_PPzZZ_S:
9391 case AArch64::CMPHS_WIDE_PPzZZ_B:
9392 case AArch64::CMPHS_WIDE_PPzZZ_H:
9393 case AArch64::CMPHS_WIDE_PPzZZ_S:
9394 case AArch64::CMPLE_WIDE_PPzZZ_B:
9395 case AArch64::CMPLE_WIDE_PPzZZ_H:
9396 case AArch64::CMPLE_WIDE_PPzZZ_S:
9397 case AArch64::CMPLO_WIDE_PPzZZ_B:
9398 case AArch64::CMPLO_WIDE_PPzZZ_H:
9399 case AArch64::CMPLO_WIDE_PPzZZ_S:
9400 case AArch64::CMPLS_WIDE_PPzZZ_B:
9401 case AArch64::CMPLS_WIDE_PPzZZ_H:
9402 case AArch64::CMPLS_WIDE_PPzZZ_S:
9403 case AArch64::CMPLT_WIDE_PPzZZ_B:
9404 case AArch64::CMPLT_WIDE_PPzZZ_H:
9405 case AArch64::CMPLT_WIDE_PPzZZ_S:
9406 case AArch64::CMPNE_PPzZZ_B:
9407 case AArch64::CMPNE_PPzZZ_D:
9408 case AArch64::CMPNE_PPzZZ_H:
9409 case AArch64::CMPNE_PPzZZ_S:
9410 case AArch64::CMPNE_WIDE_PPzZZ_B:
9411 case AArch64::CMPNE_WIDE_PPzZZ_H:
9412 case AArch64::CMPNE_WIDE_PPzZZ_S:
9413 case AArch64::FACGE_PPzZZ_D:
9414 case AArch64::FACGE_PPzZZ_H:
9415 case AArch64::FACGE_PPzZZ_S:
9416 case AArch64::FACGT_PPzZZ_D:
9417 case AArch64::FACGT_PPzZZ_H:
9418 case AArch64::FACGT_PPzZZ_S:
9419 case AArch64::FCMEQ_PPzZZ_D:
9420 case AArch64::FCMEQ_PPzZZ_H:
9421 case AArch64::FCMEQ_PPzZZ_S:
9422 case AArch64::FCMGE_PPzZZ_D:
9423 case AArch64::FCMGE_PPzZZ_H:
9424 case AArch64::FCMGE_PPzZZ_S:
9425 case AArch64::FCMGT_PPzZZ_D:
9426 case AArch64::FCMGT_PPzZZ_H:
9427 case AArch64::FCMGT_PPzZZ_S:
9428 case AArch64::FCMNE_PPzZZ_D:
9429 case AArch64::FCMNE_PPzZZ_H:
9430 case AArch64::FCMNE_PPzZZ_S:
9431 case AArch64::FCMUO_PPzZZ_D:
9432 case AArch64::FCMUO_PPzZZ_H:
9433 case AArch64::FCMUO_PPzZZ_S:
9434 case AArch64::MATCH_PPzZZ_B:
9435 case AArch64::MATCH_PPzZZ_H:
9436 case AArch64::NMATCH_PPzZZ_B:
9437 case AArch64::NMATCH_PPzZZ_H: {
9438 // op: Pd
9439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9440 op &= UINT64_C(15);
9441 Value |= op;
9442 // op: Pg
9443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9444 op &= UINT64_C(7);
9445 op <<= 10;
9446 Value |= op;
9447 // op: Zm
9448 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9449 op &= UINT64_C(31);
9450 op <<= 16;
9451 Value |= op;
9452 // op: Zn
9453 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9454 op &= UINT64_C(31);
9455 op <<= 5;
9456 Value |= op;
9457 break;
9458 }
9459 case AArch64::FCMEQ_PPzZ0_D:
9460 case AArch64::FCMEQ_PPzZ0_H:
9461 case AArch64::FCMEQ_PPzZ0_S:
9462 case AArch64::FCMGE_PPzZ0_D:
9463 case AArch64::FCMGE_PPzZ0_H:
9464 case AArch64::FCMGE_PPzZ0_S:
9465 case AArch64::FCMGT_PPzZ0_D:
9466 case AArch64::FCMGT_PPzZ0_H:
9467 case AArch64::FCMGT_PPzZ0_S:
9468 case AArch64::FCMLE_PPzZ0_D:
9469 case AArch64::FCMLE_PPzZ0_H:
9470 case AArch64::FCMLE_PPzZ0_S:
9471 case AArch64::FCMLT_PPzZ0_D:
9472 case AArch64::FCMLT_PPzZ0_H:
9473 case AArch64::FCMLT_PPzZ0_S:
9474 case AArch64::FCMNE_PPzZ0_D:
9475 case AArch64::FCMNE_PPzZ0_H:
9476 case AArch64::FCMNE_PPzZ0_S: {
9477 // op: Pd
9478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9479 op &= UINT64_C(15);
9480 Value |= op;
9481 // op: Pg
9482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9483 op &= UINT64_C(7);
9484 op <<= 10;
9485 Value |= op;
9486 // op: Zn
9487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9488 op &= UINT64_C(31);
9489 op <<= 5;
9490 Value |= op;
9491 break;
9492 }
9493 case AArch64::CMPEQ_PPzZI_B:
9494 case AArch64::CMPEQ_PPzZI_D:
9495 case AArch64::CMPEQ_PPzZI_H:
9496 case AArch64::CMPEQ_PPzZI_S:
9497 case AArch64::CMPGE_PPzZI_B:
9498 case AArch64::CMPGE_PPzZI_D:
9499 case AArch64::CMPGE_PPzZI_H:
9500 case AArch64::CMPGE_PPzZI_S:
9501 case AArch64::CMPGT_PPzZI_B:
9502 case AArch64::CMPGT_PPzZI_D:
9503 case AArch64::CMPGT_PPzZI_H:
9504 case AArch64::CMPGT_PPzZI_S:
9505 case AArch64::CMPLE_PPzZI_B:
9506 case AArch64::CMPLE_PPzZI_D:
9507 case AArch64::CMPLE_PPzZI_H:
9508 case AArch64::CMPLE_PPzZI_S:
9509 case AArch64::CMPLT_PPzZI_B:
9510 case AArch64::CMPLT_PPzZI_D:
9511 case AArch64::CMPLT_PPzZI_H:
9512 case AArch64::CMPLT_PPzZI_S:
9513 case AArch64::CMPNE_PPzZI_B:
9514 case AArch64::CMPNE_PPzZI_D:
9515 case AArch64::CMPNE_PPzZI_H:
9516 case AArch64::CMPNE_PPzZI_S: {
9517 // op: Pd
9518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9519 op &= UINT64_C(15);
9520 Value |= op;
9521 // op: Pg
9522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9523 op &= UINT64_C(7);
9524 op <<= 10;
9525 Value |= op;
9526 // op: Zn
9527 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9528 op &= UINT64_C(31);
9529 op <<= 5;
9530 Value |= op;
9531 // op: imm5
9532 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9533 op &= UINT64_C(31);
9534 op <<= 16;
9535 Value |= op;
9536 break;
9537 }
9538 case AArch64::CMPHI_PPzZI_B:
9539 case AArch64::CMPHI_PPzZI_D:
9540 case AArch64::CMPHI_PPzZI_H:
9541 case AArch64::CMPHI_PPzZI_S:
9542 case AArch64::CMPHS_PPzZI_B:
9543 case AArch64::CMPHS_PPzZI_D:
9544 case AArch64::CMPHS_PPzZI_H:
9545 case AArch64::CMPHS_PPzZI_S:
9546 case AArch64::CMPLO_PPzZI_B:
9547 case AArch64::CMPLO_PPzZI_D:
9548 case AArch64::CMPLO_PPzZI_H:
9549 case AArch64::CMPLO_PPzZI_S:
9550 case AArch64::CMPLS_PPzZI_B:
9551 case AArch64::CMPLS_PPzZI_D:
9552 case AArch64::CMPLS_PPzZI_H:
9553 case AArch64::CMPLS_PPzZI_S: {
9554 // op: Pd
9555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9556 op &= UINT64_C(15);
9557 Value |= op;
9558 // op: Pg
9559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9560 op &= UINT64_C(7);
9561 op <<= 10;
9562 Value |= op;
9563 // op: Zn
9564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9565 op &= UINT64_C(31);
9566 op <<= 5;
9567 Value |= op;
9568 // op: imm7
9569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9570 op &= UINT64_C(127);
9571 op <<= 14;
9572 Value |= op;
9573 break;
9574 }
9575 case AArch64::BRKA_PPmP:
9576 case AArch64::BRKB_PPmP: {
9577 // op: Pd
9578 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9579 op &= UINT64_C(15);
9580 Value |= op;
9581 // op: Pg
9582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9583 op &= UINT64_C(15);
9584 op <<= 10;
9585 Value |= op;
9586 // op: Pn
9587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9588 op &= UINT64_C(15);
9589 op <<= 5;
9590 Value |= op;
9591 break;
9592 }
9593 case AArch64::TRN1_PPP_B:
9594 case AArch64::TRN1_PPP_D:
9595 case AArch64::TRN1_PPP_H:
9596 case AArch64::TRN1_PPP_S:
9597 case AArch64::TRN2_PPP_B:
9598 case AArch64::TRN2_PPP_D:
9599 case AArch64::TRN2_PPP_H:
9600 case AArch64::TRN2_PPP_S:
9601 case AArch64::UZP1_PPP_B:
9602 case AArch64::UZP1_PPP_D:
9603 case AArch64::UZP1_PPP_H:
9604 case AArch64::UZP1_PPP_S:
9605 case AArch64::UZP2_PPP_B:
9606 case AArch64::UZP2_PPP_D:
9607 case AArch64::UZP2_PPP_H:
9608 case AArch64::UZP2_PPP_S:
9609 case AArch64::ZIP1_PPP_B:
9610 case AArch64::ZIP1_PPP_D:
9611 case AArch64::ZIP1_PPP_H:
9612 case AArch64::ZIP1_PPP_S:
9613 case AArch64::ZIP2_PPP_B:
9614 case AArch64::ZIP2_PPP_D:
9615 case AArch64::ZIP2_PPP_H:
9616 case AArch64::ZIP2_PPP_S: {
9617 // op: Pd
9618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9619 op &= UINT64_C(15);
9620 Value |= op;
9621 // op: Pm
9622 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9623 op &= UINT64_C(15);
9624 op <<= 16;
9625 Value |= op;
9626 // op: Pn
9627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9628 op &= UINT64_C(15);
9629 op <<= 5;
9630 Value |= op;
9631 break;
9632 }
9633 case AArch64::PUNPKHI_PP:
9634 case AArch64::PUNPKLO_PP:
9635 case AArch64::REV_PP_B:
9636 case AArch64::REV_PP_D:
9637 case AArch64::REV_PP_H:
9638 case AArch64::REV_PP_S: {
9639 // op: Pd
9640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9641 op &= UINT64_C(15);
9642 Value |= op;
9643 // op: Pn
9644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9645 op &= UINT64_C(15);
9646 op <<= 5;
9647 Value |= op;
9648 break;
9649 }
9650 case AArch64::WHILEGE_PWW_B:
9651 case AArch64::WHILEGE_PWW_D:
9652 case AArch64::WHILEGE_PWW_H:
9653 case AArch64::WHILEGE_PWW_S:
9654 case AArch64::WHILEGE_PXX_B:
9655 case AArch64::WHILEGE_PXX_D:
9656 case AArch64::WHILEGE_PXX_H:
9657 case AArch64::WHILEGE_PXX_S:
9658 case AArch64::WHILEGT_PWW_B:
9659 case AArch64::WHILEGT_PWW_D:
9660 case AArch64::WHILEGT_PWW_H:
9661 case AArch64::WHILEGT_PWW_S:
9662 case AArch64::WHILEGT_PXX_B:
9663 case AArch64::WHILEGT_PXX_D:
9664 case AArch64::WHILEGT_PXX_H:
9665 case AArch64::WHILEGT_PXX_S:
9666 case AArch64::WHILEHI_PWW_B:
9667 case AArch64::WHILEHI_PWW_D:
9668 case AArch64::WHILEHI_PWW_H:
9669 case AArch64::WHILEHI_PWW_S:
9670 case AArch64::WHILEHI_PXX_B:
9671 case AArch64::WHILEHI_PXX_D:
9672 case AArch64::WHILEHI_PXX_H:
9673 case AArch64::WHILEHI_PXX_S:
9674 case AArch64::WHILEHS_PWW_B:
9675 case AArch64::WHILEHS_PWW_D:
9676 case AArch64::WHILEHS_PWW_H:
9677 case AArch64::WHILEHS_PWW_S:
9678 case AArch64::WHILEHS_PXX_B:
9679 case AArch64::WHILEHS_PXX_D:
9680 case AArch64::WHILEHS_PXX_H:
9681 case AArch64::WHILEHS_PXX_S:
9682 case AArch64::WHILELE_PWW_B:
9683 case AArch64::WHILELE_PWW_D:
9684 case AArch64::WHILELE_PWW_H:
9685 case AArch64::WHILELE_PWW_S:
9686 case AArch64::WHILELE_PXX_B:
9687 case AArch64::WHILELE_PXX_D:
9688 case AArch64::WHILELE_PXX_H:
9689 case AArch64::WHILELE_PXX_S:
9690 case AArch64::WHILELO_PWW_B:
9691 case AArch64::WHILELO_PWW_D:
9692 case AArch64::WHILELO_PWW_H:
9693 case AArch64::WHILELO_PWW_S:
9694 case AArch64::WHILELO_PXX_B:
9695 case AArch64::WHILELO_PXX_D:
9696 case AArch64::WHILELO_PXX_H:
9697 case AArch64::WHILELO_PXX_S:
9698 case AArch64::WHILELS_PWW_B:
9699 case AArch64::WHILELS_PWW_D:
9700 case AArch64::WHILELS_PWW_H:
9701 case AArch64::WHILELS_PWW_S:
9702 case AArch64::WHILELS_PXX_B:
9703 case AArch64::WHILELS_PXX_D:
9704 case AArch64::WHILELS_PXX_H:
9705 case AArch64::WHILELS_PXX_S:
9706 case AArch64::WHILELT_PWW_B:
9707 case AArch64::WHILELT_PWW_D:
9708 case AArch64::WHILELT_PWW_H:
9709 case AArch64::WHILELT_PWW_S:
9710 case AArch64::WHILELT_PXX_B:
9711 case AArch64::WHILELT_PXX_D:
9712 case AArch64::WHILELT_PXX_H:
9713 case AArch64::WHILELT_PXX_S:
9714 case AArch64::WHILERW_PXX_B:
9715 case AArch64::WHILERW_PXX_D:
9716 case AArch64::WHILERW_PXX_H:
9717 case AArch64::WHILERW_PXX_S:
9718 case AArch64::WHILEWR_PXX_B:
9719 case AArch64::WHILEWR_PXX_D:
9720 case AArch64::WHILEWR_PXX_H:
9721 case AArch64::WHILEWR_PXX_S: {
9722 // op: Pd
9723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9724 op &= UINT64_C(15);
9725 Value |= op;
9726 // op: Rm
9727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9728 op &= UINT64_C(31);
9729 op <<= 16;
9730 Value |= op;
9731 // op: Rn
9732 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9733 op &= UINT64_C(31);
9734 op <<= 5;
9735 Value |= op;
9736 break;
9737 }
9738 case AArch64::PMOV_PZI_B: {
9739 // op: Pd
9740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9741 op &= UINT64_C(15);
9742 Value |= op;
9743 // op: Zn
9744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9745 op &= UINT64_C(31);
9746 op <<= 5;
9747 Value |= op;
9748 break;
9749 }
9750 case AArch64::PMOV_PZI_D: {
9751 // op: Pd
9752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9753 op &= UINT64_C(15);
9754 Value |= op;
9755 // op: Zn
9756 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9757 op &= UINT64_C(31);
9758 op <<= 5;
9759 Value |= op;
9760 // op: index
9761 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9762 Value |= (op & UINT64_C(4)) << 20;
9763 Value |= (op & UINT64_C(3)) << 17;
9764 break;
9765 }
9766 case AArch64::PMOV_PZI_H: {
9767 // op: Pd
9768 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9769 op &= UINT64_C(15);
9770 Value |= op;
9771 // op: Zn
9772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9773 op &= UINT64_C(31);
9774 op <<= 5;
9775 Value |= op;
9776 // op: index
9777 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9778 op &= UINT64_C(1);
9779 op <<= 17;
9780 Value |= op;
9781 break;
9782 }
9783 case AArch64::PMOV_PZI_S: {
9784 // op: Pd
9785 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9786 op &= UINT64_C(15);
9787 Value |= op;
9788 // op: Zn
9789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9790 op &= UINT64_C(31);
9791 op <<= 5;
9792 Value |= op;
9793 // op: index
9794 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9795 op &= UINT64_C(3);
9796 op <<= 17;
9797 Value |= op;
9798 break;
9799 }
9800 case AArch64::PTRUES_B:
9801 case AArch64::PTRUES_D:
9802 case AArch64::PTRUES_H:
9803 case AArch64::PTRUES_S:
9804 case AArch64::PTRUE_B:
9805 case AArch64::PTRUE_D:
9806 case AArch64::PTRUE_H:
9807 case AArch64::PTRUE_S: {
9808 // op: Pd
9809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9810 op &= UINT64_C(15);
9811 Value |= op;
9812 // op: pattern
9813 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9814 op &= UINT64_C(31);
9815 op <<= 5;
9816 Value |= op;
9817 break;
9818 }
9819 case AArch64::BRKNS_PPzP:
9820 case AArch64::BRKN_PPzP: {
9821 // op: Pdm
9822 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9823 op &= UINT64_C(15);
9824 Value |= op;
9825 // op: Pg
9826 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9827 op &= UINT64_C(15);
9828 op <<= 10;
9829 Value |= op;
9830 // op: Pn
9831 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9832 op &= UINT64_C(15);
9833 op <<= 5;
9834 Value |= op;
9835 break;
9836 }
9837 case AArch64::PFIRST_B:
9838 case AArch64::PNEXT_B:
9839 case AArch64::PNEXT_D:
9840 case AArch64::PNEXT_H:
9841 case AArch64::PNEXT_S: {
9842 // op: Pdn
9843 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9844 op &= UINT64_C(15);
9845 Value |= op;
9846 // op: Pg
9847 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9848 op &= UINT64_C(15);
9849 op <<= 5;
9850 Value |= op;
9851 break;
9852 }
9853 case AArch64::PTEST_PP: {
9854 // op: Pg
9855 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9856 op &= UINT64_C(15);
9857 op <<= 10;
9858 Value |= op;
9859 // op: Pn
9860 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9861 op &= UINT64_C(15);
9862 op <<= 5;
9863 Value |= op;
9864 break;
9865 }
9866 case AArch64::CNTP_XPP_B:
9867 case AArch64::CNTP_XPP_D:
9868 case AArch64::CNTP_XPP_H:
9869 case AArch64::CNTP_XPP_S:
9870 case AArch64::FIRSTP_XPP_B:
9871 case AArch64::FIRSTP_XPP_D:
9872 case AArch64::FIRSTP_XPP_H:
9873 case AArch64::FIRSTP_XPP_S:
9874 case AArch64::LASTP_XPP_B:
9875 case AArch64::LASTP_XPP_D:
9876 case AArch64::LASTP_XPP_H:
9877 case AArch64::LASTP_XPP_S: {
9878 // op: Pg
9879 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9880 op &= UINT64_C(15);
9881 op <<= 10;
9882 Value |= op;
9883 // op: Pn
9884 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9885 op &= UINT64_C(15);
9886 op <<= 5;
9887 Value |= op;
9888 // op: Rd
9889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9890 op &= UINT64_C(31);
9891 Value |= op;
9892 break;
9893 }
9894 case AArch64::SEL_ZPZZ_B:
9895 case AArch64::SEL_ZPZZ_D:
9896 case AArch64::SEL_ZPZZ_H:
9897 case AArch64::SEL_ZPZZ_S: {
9898 // op: Pg
9899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9900 op &= UINT64_C(15);
9901 op <<= 10;
9902 Value |= op;
9903 // op: Zd
9904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9905 op &= UINT64_C(31);
9906 Value |= op;
9907 // op: Zm
9908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9909 op &= UINT64_C(31);
9910 op <<= 16;
9911 Value |= op;
9912 // op: Zn
9913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9914 op &= UINT64_C(31);
9915 op <<= 5;
9916 Value |= op;
9917 break;
9918 }
9919 case AArch64::LASTA_RPZ_B:
9920 case AArch64::LASTA_RPZ_D:
9921 case AArch64::LASTA_RPZ_H:
9922 case AArch64::LASTA_RPZ_S:
9923 case AArch64::LASTB_RPZ_B:
9924 case AArch64::LASTB_RPZ_D:
9925 case AArch64::LASTB_RPZ_H:
9926 case AArch64::LASTB_RPZ_S: {
9927 // op: Pg
9928 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9929 op &= UINT64_C(7);
9930 op <<= 10;
9931 Value |= op;
9932 // op: Rd
9933 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9934 op &= UINT64_C(31);
9935 Value |= op;
9936 // op: Zn
9937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9938 op &= UINT64_C(31);
9939 op <<= 5;
9940 Value |= op;
9941 break;
9942 }
9943 case AArch64::CLASTA_RPZ_B:
9944 case AArch64::CLASTA_RPZ_D:
9945 case AArch64::CLASTA_RPZ_H:
9946 case AArch64::CLASTA_RPZ_S:
9947 case AArch64::CLASTB_RPZ_B:
9948 case AArch64::CLASTB_RPZ_D:
9949 case AArch64::CLASTB_RPZ_H:
9950 case AArch64::CLASTB_RPZ_S: {
9951 // op: Pg
9952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9953 op &= UINT64_C(7);
9954 op <<= 10;
9955 Value |= op;
9956 // op: Rdn
9957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9958 op &= UINT64_C(31);
9959 Value |= op;
9960 // op: Zm
9961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9962 op &= UINT64_C(31);
9963 op <<= 5;
9964 Value |= op;
9965 break;
9966 }
9967 case AArch64::LD2B:
9968 case AArch64::LD2D:
9969 case AArch64::LD2H:
9970 case AArch64::LD2Q:
9971 case AArch64::LD2W:
9972 case AArch64::LD3B:
9973 case AArch64::LD3D:
9974 case AArch64::LD3H:
9975 case AArch64::LD3Q:
9976 case AArch64::LD3W:
9977 case AArch64::LD4B:
9978 case AArch64::LD4D:
9979 case AArch64::LD4H:
9980 case AArch64::LD4Q:
9981 case AArch64::LD4W:
9982 case AArch64::LDNT1B_ZRR:
9983 case AArch64::LDNT1D_ZRR:
9984 case AArch64::LDNT1H_ZRR:
9985 case AArch64::LDNT1W_ZRR:
9986 case AArch64::ST1B:
9987 case AArch64::ST1B_D:
9988 case AArch64::ST1B_H:
9989 case AArch64::ST1B_S:
9990 case AArch64::ST1D:
9991 case AArch64::ST1D_Q:
9992 case AArch64::ST1H:
9993 case AArch64::ST1H_D:
9994 case AArch64::ST1H_S:
9995 case AArch64::ST1W:
9996 case AArch64::ST1W_D:
9997 case AArch64::ST1W_Q:
9998 case AArch64::ST2B:
9999 case AArch64::ST2D:
10000 case AArch64::ST2H:
10001 case AArch64::ST2W:
10002 case AArch64::ST3B:
10003 case AArch64::ST3D:
10004 case AArch64::ST3H:
10005 case AArch64::ST3W:
10006 case AArch64::ST4B:
10007 case AArch64::ST4D:
10008 case AArch64::ST4H:
10009 case AArch64::ST4W:
10010 case AArch64::STNT1B_ZRR:
10011 case AArch64::STNT1D_ZRR:
10012 case AArch64::STNT1H_ZRR:
10013 case AArch64::STNT1W_ZRR: {
10014 // op: Pg
10015 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10016 op &= UINT64_C(7);
10017 op <<= 10;
10018 Value |= op;
10019 // op: Rm
10020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10021 op &= UINT64_C(31);
10022 op <<= 16;
10023 Value |= op;
10024 // op: Rn
10025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10026 op &= UINT64_C(31);
10027 op <<= 5;
10028 Value |= op;
10029 // op: Zt
10030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10031 op &= UINT64_C(31);
10032 Value |= op;
10033 break;
10034 }
10035 case AArch64::LDNT1B_ZZR_D:
10036 case AArch64::LDNT1B_ZZR_S:
10037 case AArch64::LDNT1D_ZZR_D:
10038 case AArch64::LDNT1H_ZZR_D:
10039 case AArch64::LDNT1H_ZZR_S:
10040 case AArch64::LDNT1SB_ZZR_D:
10041 case AArch64::LDNT1SB_ZZR_S:
10042 case AArch64::LDNT1SH_ZZR_D:
10043 case AArch64::LDNT1SH_ZZR_S:
10044 case AArch64::LDNT1SW_ZZR_D:
10045 case AArch64::LDNT1W_ZZR_D:
10046 case AArch64::LDNT1W_ZZR_S:
10047 case AArch64::STNT1B_ZZR_D:
10048 case AArch64::STNT1B_ZZR_S:
10049 case AArch64::STNT1D_ZZR_D:
10050 case AArch64::STNT1H_ZZR_D:
10051 case AArch64::STNT1H_ZZR_S:
10052 case AArch64::STNT1W_ZZR_D:
10053 case AArch64::STNT1W_ZZR_S: {
10054 // op: Pg
10055 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10056 op &= UINT64_C(7);
10057 op <<= 10;
10058 Value |= op;
10059 // op: Rm
10060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10061 op &= UINT64_C(31);
10062 op <<= 16;
10063 Value |= op;
10064 // op: Zn
10065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10066 op &= UINT64_C(31);
10067 op <<= 5;
10068 Value |= op;
10069 // op: Zt
10070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10071 op &= UINT64_C(31);
10072 Value |= op;
10073 break;
10074 }
10075 case AArch64::GLD1B_D:
10076 case AArch64::GLD1B_D_SXTW:
10077 case AArch64::GLD1B_D_UXTW:
10078 case AArch64::GLD1B_S_SXTW:
10079 case AArch64::GLD1B_S_UXTW:
10080 case AArch64::GLD1D:
10081 case AArch64::GLD1D_SCALED:
10082 case AArch64::GLD1D_SXTW:
10083 case AArch64::GLD1D_SXTW_SCALED:
10084 case AArch64::GLD1D_UXTW:
10085 case AArch64::GLD1D_UXTW_SCALED:
10086 case AArch64::GLD1H_D:
10087 case AArch64::GLD1H_D_SCALED:
10088 case AArch64::GLD1H_D_SXTW:
10089 case AArch64::GLD1H_D_SXTW_SCALED:
10090 case AArch64::GLD1H_D_UXTW:
10091 case AArch64::GLD1H_D_UXTW_SCALED:
10092 case AArch64::GLD1H_S_SXTW:
10093 case AArch64::GLD1H_S_SXTW_SCALED:
10094 case AArch64::GLD1H_S_UXTW:
10095 case AArch64::GLD1H_S_UXTW_SCALED:
10096 case AArch64::GLD1SB_D:
10097 case AArch64::GLD1SB_D_SXTW:
10098 case AArch64::GLD1SB_D_UXTW:
10099 case AArch64::GLD1SB_S_SXTW:
10100 case AArch64::GLD1SB_S_UXTW:
10101 case AArch64::GLD1SH_D:
10102 case AArch64::GLD1SH_D_SCALED:
10103 case AArch64::GLD1SH_D_SXTW:
10104 case AArch64::GLD1SH_D_SXTW_SCALED:
10105 case AArch64::GLD1SH_D_UXTW:
10106 case AArch64::GLD1SH_D_UXTW_SCALED:
10107 case AArch64::GLD1SH_S_SXTW:
10108 case AArch64::GLD1SH_S_SXTW_SCALED:
10109 case AArch64::GLD1SH_S_UXTW:
10110 case AArch64::GLD1SH_S_UXTW_SCALED:
10111 case AArch64::GLD1SW_D:
10112 case AArch64::GLD1SW_D_SCALED:
10113 case AArch64::GLD1SW_D_SXTW:
10114 case AArch64::GLD1SW_D_SXTW_SCALED:
10115 case AArch64::GLD1SW_D_UXTW:
10116 case AArch64::GLD1SW_D_UXTW_SCALED:
10117 case AArch64::GLD1W_D:
10118 case AArch64::GLD1W_D_SCALED:
10119 case AArch64::GLD1W_D_SXTW:
10120 case AArch64::GLD1W_D_SXTW_SCALED:
10121 case AArch64::GLD1W_D_UXTW:
10122 case AArch64::GLD1W_D_UXTW_SCALED:
10123 case AArch64::GLD1W_SXTW:
10124 case AArch64::GLD1W_SXTW_SCALED:
10125 case AArch64::GLD1W_UXTW:
10126 case AArch64::GLD1W_UXTW_SCALED:
10127 case AArch64::GLDFF1B_D:
10128 case AArch64::GLDFF1B_D_SXTW:
10129 case AArch64::GLDFF1B_D_UXTW:
10130 case AArch64::GLDFF1B_S_SXTW:
10131 case AArch64::GLDFF1B_S_UXTW:
10132 case AArch64::GLDFF1D:
10133 case AArch64::GLDFF1D_SCALED:
10134 case AArch64::GLDFF1D_SXTW:
10135 case AArch64::GLDFF1D_SXTW_SCALED:
10136 case AArch64::GLDFF1D_UXTW:
10137 case AArch64::GLDFF1D_UXTW_SCALED:
10138 case AArch64::GLDFF1H_D:
10139 case AArch64::GLDFF1H_D_SCALED:
10140 case AArch64::GLDFF1H_D_SXTW:
10141 case AArch64::GLDFF1H_D_SXTW_SCALED:
10142 case AArch64::GLDFF1H_D_UXTW:
10143 case AArch64::GLDFF1H_D_UXTW_SCALED:
10144 case AArch64::GLDFF1H_S_SXTW:
10145 case AArch64::GLDFF1H_S_SXTW_SCALED:
10146 case AArch64::GLDFF1H_S_UXTW:
10147 case AArch64::GLDFF1H_S_UXTW_SCALED:
10148 case AArch64::GLDFF1SB_D:
10149 case AArch64::GLDFF1SB_D_SXTW:
10150 case AArch64::GLDFF1SB_D_UXTW:
10151 case AArch64::GLDFF1SB_S_SXTW:
10152 case AArch64::GLDFF1SB_S_UXTW:
10153 case AArch64::GLDFF1SH_D:
10154 case AArch64::GLDFF1SH_D_SCALED:
10155 case AArch64::GLDFF1SH_D_SXTW:
10156 case AArch64::GLDFF1SH_D_SXTW_SCALED:
10157 case AArch64::GLDFF1SH_D_UXTW:
10158 case AArch64::GLDFF1SH_D_UXTW_SCALED:
10159 case AArch64::GLDFF1SH_S_SXTW:
10160 case AArch64::GLDFF1SH_S_SXTW_SCALED:
10161 case AArch64::GLDFF1SH_S_UXTW:
10162 case AArch64::GLDFF1SH_S_UXTW_SCALED:
10163 case AArch64::GLDFF1SW_D:
10164 case AArch64::GLDFF1SW_D_SCALED:
10165 case AArch64::GLDFF1SW_D_SXTW:
10166 case AArch64::GLDFF1SW_D_SXTW_SCALED:
10167 case AArch64::GLDFF1SW_D_UXTW:
10168 case AArch64::GLDFF1SW_D_UXTW_SCALED:
10169 case AArch64::GLDFF1W_D:
10170 case AArch64::GLDFF1W_D_SCALED:
10171 case AArch64::GLDFF1W_D_SXTW:
10172 case AArch64::GLDFF1W_D_SXTW_SCALED:
10173 case AArch64::GLDFF1W_D_UXTW:
10174 case AArch64::GLDFF1W_D_UXTW_SCALED:
10175 case AArch64::GLDFF1W_SXTW:
10176 case AArch64::GLDFF1W_SXTW_SCALED:
10177 case AArch64::GLDFF1W_UXTW:
10178 case AArch64::GLDFF1W_UXTW_SCALED:
10179 case AArch64::SST1B_D:
10180 case AArch64::SST1B_D_SXTW:
10181 case AArch64::SST1B_D_UXTW:
10182 case AArch64::SST1B_S_SXTW:
10183 case AArch64::SST1B_S_UXTW:
10184 case AArch64::SST1D:
10185 case AArch64::SST1D_SCALED:
10186 case AArch64::SST1D_SXTW:
10187 case AArch64::SST1D_SXTW_SCALED:
10188 case AArch64::SST1D_UXTW:
10189 case AArch64::SST1D_UXTW_SCALED:
10190 case AArch64::SST1H_D:
10191 case AArch64::SST1H_D_SCALED:
10192 case AArch64::SST1H_D_SXTW:
10193 case AArch64::SST1H_D_SXTW_SCALED:
10194 case AArch64::SST1H_D_UXTW:
10195 case AArch64::SST1H_D_UXTW_SCALED:
10196 case AArch64::SST1H_S_SXTW:
10197 case AArch64::SST1H_S_SXTW_SCALED:
10198 case AArch64::SST1H_S_UXTW:
10199 case AArch64::SST1H_S_UXTW_SCALED:
10200 case AArch64::SST1W_D:
10201 case AArch64::SST1W_D_SCALED:
10202 case AArch64::SST1W_D_SXTW:
10203 case AArch64::SST1W_D_SXTW_SCALED:
10204 case AArch64::SST1W_D_UXTW:
10205 case AArch64::SST1W_D_UXTW_SCALED:
10206 case AArch64::SST1W_SXTW:
10207 case AArch64::SST1W_SXTW_SCALED:
10208 case AArch64::SST1W_UXTW:
10209 case AArch64::SST1W_UXTW_SCALED: {
10210 // op: Pg
10211 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10212 op &= UINT64_C(7);
10213 op <<= 10;
10214 Value |= op;
10215 // op: Rn
10216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10217 op &= UINT64_C(31);
10218 op <<= 5;
10219 Value |= op;
10220 // op: Zm
10221 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10222 op &= UINT64_C(31);
10223 op <<= 16;
10224 Value |= op;
10225 // op: Zt
10226 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10227 op &= UINT64_C(31);
10228 Value |= op;
10229 break;
10230 }
10231 case AArch64::PRFB_D_SCALED:
10232 case AArch64::PRFB_D_SXTW_SCALED:
10233 case AArch64::PRFB_D_UXTW_SCALED:
10234 case AArch64::PRFB_S_SXTW_SCALED:
10235 case AArch64::PRFB_S_UXTW_SCALED:
10236 case AArch64::PRFD_D_SCALED:
10237 case AArch64::PRFD_D_SXTW_SCALED:
10238 case AArch64::PRFD_D_UXTW_SCALED:
10239 case AArch64::PRFD_S_SXTW_SCALED:
10240 case AArch64::PRFD_S_UXTW_SCALED:
10241 case AArch64::PRFH_D_SCALED:
10242 case AArch64::PRFH_D_SXTW_SCALED:
10243 case AArch64::PRFH_D_UXTW_SCALED:
10244 case AArch64::PRFH_S_SXTW_SCALED:
10245 case AArch64::PRFH_S_UXTW_SCALED:
10246 case AArch64::PRFW_D_SCALED:
10247 case AArch64::PRFW_D_SXTW_SCALED:
10248 case AArch64::PRFW_D_UXTW_SCALED:
10249 case AArch64::PRFW_S_SXTW_SCALED:
10250 case AArch64::PRFW_S_UXTW_SCALED: {
10251 // op: Pg
10252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10253 op &= UINT64_C(7);
10254 op <<= 10;
10255 Value |= op;
10256 // op: Rn
10257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10258 op &= UINT64_C(31);
10259 op <<= 5;
10260 Value |= op;
10261 // op: Zm
10262 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10263 op &= UINT64_C(31);
10264 op <<= 16;
10265 Value |= op;
10266 // op: prfop
10267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10268 op &= UINT64_C(15);
10269 Value |= op;
10270 break;
10271 }
10272 case AArch64::LD1B_D_IMM:
10273 case AArch64::LD1B_H_IMM:
10274 case AArch64::LD1B_IMM:
10275 case AArch64::LD1B_S_IMM:
10276 case AArch64::LD1D_IMM:
10277 case AArch64::LD1H_D_IMM:
10278 case AArch64::LD1H_IMM:
10279 case AArch64::LD1H_S_IMM:
10280 case AArch64::LD1SB_D_IMM:
10281 case AArch64::LD1SB_H_IMM:
10282 case AArch64::LD1SB_S_IMM:
10283 case AArch64::LD1SH_D_IMM:
10284 case AArch64::LD1SH_S_IMM:
10285 case AArch64::LD1SW_D_IMM:
10286 case AArch64::LD1W_D_IMM:
10287 case AArch64::LD1W_IMM:
10288 case AArch64::LDNF1B_D_IMM:
10289 case AArch64::LDNF1B_H_IMM:
10290 case AArch64::LDNF1B_IMM:
10291 case AArch64::LDNF1B_S_IMM:
10292 case AArch64::LDNF1D_IMM:
10293 case AArch64::LDNF1H_D_IMM:
10294 case AArch64::LDNF1H_IMM:
10295 case AArch64::LDNF1H_S_IMM:
10296 case AArch64::LDNF1SB_D_IMM:
10297 case AArch64::LDNF1SB_H_IMM:
10298 case AArch64::LDNF1SB_S_IMM:
10299 case AArch64::LDNF1SH_D_IMM:
10300 case AArch64::LDNF1SH_S_IMM:
10301 case AArch64::LDNF1SW_D_IMM:
10302 case AArch64::LDNF1W_D_IMM:
10303 case AArch64::LDNF1W_IMM:
10304 case AArch64::ST1B_D_IMM:
10305 case AArch64::ST1B_H_IMM:
10306 case AArch64::ST1B_IMM:
10307 case AArch64::ST1B_S_IMM:
10308 case AArch64::ST1D_IMM:
10309 case AArch64::ST1D_Q_IMM:
10310 case AArch64::ST1H_D_IMM:
10311 case AArch64::ST1H_IMM:
10312 case AArch64::ST1H_S_IMM:
10313 case AArch64::ST1W_D_IMM:
10314 case AArch64::ST1W_IMM:
10315 case AArch64::ST1W_Q_IMM:
10316 case AArch64::ST2B_IMM:
10317 case AArch64::ST2D_IMM:
10318 case AArch64::ST2H_IMM:
10319 case AArch64::ST2W_IMM:
10320 case AArch64::ST3B_IMM:
10321 case AArch64::ST3D_IMM:
10322 case AArch64::ST3H_IMM:
10323 case AArch64::ST3W_IMM:
10324 case AArch64::ST4B_IMM:
10325 case AArch64::ST4D_IMM:
10326 case AArch64::ST4H_IMM:
10327 case AArch64::ST4W_IMM:
10328 case AArch64::STNT1B_ZRI:
10329 case AArch64::STNT1D_ZRI:
10330 case AArch64::STNT1H_ZRI:
10331 case AArch64::STNT1W_ZRI: {
10332 // op: Pg
10333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10334 op &= UINT64_C(7);
10335 op <<= 10;
10336 Value |= op;
10337 // op: Rn
10338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10339 op &= UINT64_C(31);
10340 op <<= 5;
10341 Value |= op;
10342 // op: Zt
10343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10344 op &= UINT64_C(31);
10345 Value |= op;
10346 // op: imm4
10347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10348 op &= UINT64_C(15);
10349 op <<= 16;
10350 Value |= op;
10351 break;
10352 }
10353 case AArch64::LD1RB_D_IMM:
10354 case AArch64::LD1RB_H_IMM:
10355 case AArch64::LD1RB_IMM:
10356 case AArch64::LD1RB_S_IMM:
10357 case AArch64::LD1RD_IMM:
10358 case AArch64::LD1RH_D_IMM:
10359 case AArch64::LD1RH_IMM:
10360 case AArch64::LD1RH_S_IMM:
10361 case AArch64::LD1RSB_D_IMM:
10362 case AArch64::LD1RSB_H_IMM:
10363 case AArch64::LD1RSB_S_IMM:
10364 case AArch64::LD1RSH_D_IMM:
10365 case AArch64::LD1RSH_S_IMM:
10366 case AArch64::LD1RSW_IMM:
10367 case AArch64::LD1RW_D_IMM:
10368 case AArch64::LD1RW_IMM: {
10369 // op: Pg
10370 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10371 op &= UINT64_C(7);
10372 op <<= 10;
10373 Value |= op;
10374 // op: Rn
10375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10376 op &= UINT64_C(31);
10377 op <<= 5;
10378 Value |= op;
10379 // op: Zt
10380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10381 op &= UINT64_C(31);
10382 Value |= op;
10383 // op: imm6
10384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10385 op &= UINT64_C(63);
10386 op <<= 16;
10387 Value |= op;
10388 break;
10389 }
10390 case AArch64::ANDV_VPZ_B:
10391 case AArch64::ANDV_VPZ_D:
10392 case AArch64::ANDV_VPZ_H:
10393 case AArch64::ANDV_VPZ_S:
10394 case AArch64::EORV_VPZ_B:
10395 case AArch64::EORV_VPZ_D:
10396 case AArch64::EORV_VPZ_H:
10397 case AArch64::EORV_VPZ_S:
10398 case AArch64::LASTA_VPZ_B:
10399 case AArch64::LASTA_VPZ_D:
10400 case AArch64::LASTA_VPZ_H:
10401 case AArch64::LASTA_VPZ_S:
10402 case AArch64::LASTB_VPZ_B:
10403 case AArch64::LASTB_VPZ_D:
10404 case AArch64::LASTB_VPZ_H:
10405 case AArch64::LASTB_VPZ_S:
10406 case AArch64::ORV_VPZ_B:
10407 case AArch64::ORV_VPZ_D:
10408 case AArch64::ORV_VPZ_H:
10409 case AArch64::ORV_VPZ_S:
10410 case AArch64::SADDV_VPZ_B:
10411 case AArch64::SADDV_VPZ_H:
10412 case AArch64::SADDV_VPZ_S:
10413 case AArch64::SMAXV_VPZ_B:
10414 case AArch64::SMAXV_VPZ_D:
10415 case AArch64::SMAXV_VPZ_H:
10416 case AArch64::SMAXV_VPZ_S:
10417 case AArch64::SMINV_VPZ_B:
10418 case AArch64::SMINV_VPZ_D:
10419 case AArch64::SMINV_VPZ_H:
10420 case AArch64::SMINV_VPZ_S:
10421 case AArch64::UADDV_VPZ_B:
10422 case AArch64::UADDV_VPZ_D:
10423 case AArch64::UADDV_VPZ_H:
10424 case AArch64::UADDV_VPZ_S:
10425 case AArch64::UMAXV_VPZ_B:
10426 case AArch64::UMAXV_VPZ_D:
10427 case AArch64::UMAXV_VPZ_H:
10428 case AArch64::UMAXV_VPZ_S:
10429 case AArch64::UMINV_VPZ_B:
10430 case AArch64::UMINV_VPZ_D:
10431 case AArch64::UMINV_VPZ_H:
10432 case AArch64::UMINV_VPZ_S: {
10433 // op: Pg
10434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10435 op &= UINT64_C(7);
10436 op <<= 10;
10437 Value |= op;
10438 // op: Vd
10439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10440 op &= UINT64_C(31);
10441 Value |= op;
10442 // op: Zn
10443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10444 op &= UINT64_C(31);
10445 op <<= 5;
10446 Value |= op;
10447 break;
10448 }
10449 case AArch64::CLASTA_VPZ_B:
10450 case AArch64::CLASTA_VPZ_D:
10451 case AArch64::CLASTA_VPZ_H:
10452 case AArch64::CLASTA_VPZ_S:
10453 case AArch64::CLASTB_VPZ_B:
10454 case AArch64::CLASTB_VPZ_D:
10455 case AArch64::CLASTB_VPZ_H:
10456 case AArch64::CLASTB_VPZ_S:
10457 case AArch64::FADDA_VPZ_D:
10458 case AArch64::FADDA_VPZ_H:
10459 case AArch64::FADDA_VPZ_S: {
10460 // op: Pg
10461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10462 op &= UINT64_C(7);
10463 op <<= 10;
10464 Value |= op;
10465 // op: Vdn
10466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10467 op &= UINT64_C(31);
10468 Value |= op;
10469 // op: Zm
10470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10471 op &= UINT64_C(31);
10472 op <<= 5;
10473 Value |= op;
10474 break;
10475 }
10476 case AArch64::FMAD_ZPmZZ_D:
10477 case AArch64::FMAD_ZPmZZ_H:
10478 case AArch64::FMAD_ZPmZZ_S:
10479 case AArch64::FMSB_ZPmZZ_D:
10480 case AArch64::FMSB_ZPmZZ_H:
10481 case AArch64::FMSB_ZPmZZ_S:
10482 case AArch64::FNMAD_ZPmZZ_D:
10483 case AArch64::FNMAD_ZPmZZ_H:
10484 case AArch64::FNMAD_ZPmZZ_S:
10485 case AArch64::FNMSB_ZPmZZ_D:
10486 case AArch64::FNMSB_ZPmZZ_H:
10487 case AArch64::FNMSB_ZPmZZ_S: {
10488 // op: Pg
10489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10490 op &= UINT64_C(7);
10491 op <<= 10;
10492 Value |= op;
10493 // op: Za
10494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
10495 op &= UINT64_C(31);
10496 op <<= 16;
10497 Value |= op;
10498 // op: Zdn
10499 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10500 op &= UINT64_C(31);
10501 Value |= op;
10502 // op: Zm
10503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10504 op &= UINT64_C(31);
10505 op <<= 5;
10506 Value |= op;
10507 break;
10508 }
10509 case AArch64::ABS_ZPzZ_B:
10510 case AArch64::ABS_ZPzZ_D:
10511 case AArch64::ABS_ZPzZ_H:
10512 case AArch64::ABS_ZPzZ_S:
10513 case AArch64::BFCVT_ZPzZ_StoH:
10514 case AArch64::CLS_ZPzZ_B:
10515 case AArch64::CLS_ZPzZ_D:
10516 case AArch64::CLS_ZPzZ_H:
10517 case AArch64::CLS_ZPzZ_S:
10518 case AArch64::CLZ_ZPzZ_B:
10519 case AArch64::CLZ_ZPzZ_D:
10520 case AArch64::CLZ_ZPzZ_H:
10521 case AArch64::CLZ_ZPzZ_S:
10522 case AArch64::CNOT_ZPzZ_B:
10523 case AArch64::CNOT_ZPzZ_D:
10524 case AArch64::CNOT_ZPzZ_H:
10525 case AArch64::CNOT_ZPzZ_S:
10526 case AArch64::CNT_ZPzZ_B:
10527 case AArch64::CNT_ZPzZ_D:
10528 case AArch64::CNT_ZPzZ_H:
10529 case AArch64::CNT_ZPzZ_S:
10530 case AArch64::COMPACT_ZPZ_B:
10531 case AArch64::COMPACT_ZPZ_D:
10532 case AArch64::COMPACT_ZPZ_H:
10533 case AArch64::COMPACT_ZPZ_S:
10534 case AArch64::FABS_ZPzZ_D:
10535 case AArch64::FABS_ZPzZ_H:
10536 case AArch64::FABS_ZPzZ_S:
10537 case AArch64::FCVTX_ZPzZ_DtoS:
10538 case AArch64::FCVTZS_ZPzZ_DtoD:
10539 case AArch64::FCVTZS_ZPzZ_DtoS:
10540 case AArch64::FCVTZS_ZPzZ_HtoD:
10541 case AArch64::FCVTZS_ZPzZ_HtoH:
10542 case AArch64::FCVTZS_ZPzZ_HtoS:
10543 case AArch64::FCVTZS_ZPzZ_StoD:
10544 case AArch64::FCVTZS_ZPzZ_StoS:
10545 case AArch64::FCVTZU_ZPzZ_DtoD:
10546 case AArch64::FCVTZU_ZPzZ_DtoS:
10547 case AArch64::FCVTZU_ZPzZ_HtoD:
10548 case AArch64::FCVTZU_ZPzZ_HtoH:
10549 case AArch64::FCVTZU_ZPzZ_HtoS:
10550 case AArch64::FCVTZU_ZPzZ_StoD:
10551 case AArch64::FCVTZU_ZPzZ_StoS:
10552 case AArch64::FCVT_ZPzZ_DtoH:
10553 case AArch64::FCVT_ZPzZ_DtoS:
10554 case AArch64::FCVT_ZPzZ_HtoD:
10555 case AArch64::FCVT_ZPzZ_HtoS:
10556 case AArch64::FCVT_ZPzZ_StoD:
10557 case AArch64::FCVT_ZPzZ_StoH:
10558 case AArch64::FLOGB_ZPzZ_D:
10559 case AArch64::FLOGB_ZPzZ_H:
10560 case AArch64::FLOGB_ZPzZ_S:
10561 case AArch64::FNEG_ZPzZ_D:
10562 case AArch64::FNEG_ZPzZ_H:
10563 case AArch64::FNEG_ZPzZ_S:
10564 case AArch64::FRECPX_ZPzZ_D:
10565 case AArch64::FRECPX_ZPzZ_H:
10566 case AArch64::FRECPX_ZPzZ_S:
10567 case AArch64::FRINT32X_ZPzZ_D:
10568 case AArch64::FRINT32X_ZPzZ_S:
10569 case AArch64::FRINT32Z_ZPzZ_D:
10570 case AArch64::FRINT32Z_ZPzZ_S:
10571 case AArch64::FRINT64X_ZPzZ_D:
10572 case AArch64::FRINT64X_ZPzZ_S:
10573 case AArch64::FRINT64Z_ZPzZ_D:
10574 case AArch64::FRINT64Z_ZPzZ_S:
10575 case AArch64::FRINTA_ZPzZ_D:
10576 case AArch64::FRINTA_ZPzZ_H:
10577 case AArch64::FRINTA_ZPzZ_S:
10578 case AArch64::FRINTI_ZPzZ_D:
10579 case AArch64::FRINTI_ZPzZ_H:
10580 case AArch64::FRINTI_ZPzZ_S:
10581 case AArch64::FRINTM_ZPzZ_D:
10582 case AArch64::FRINTM_ZPzZ_H:
10583 case AArch64::FRINTM_ZPzZ_S:
10584 case AArch64::FRINTN_ZPzZ_D:
10585 case AArch64::FRINTN_ZPzZ_H:
10586 case AArch64::FRINTN_ZPzZ_S:
10587 case AArch64::FRINTP_ZPzZ_D:
10588 case AArch64::FRINTP_ZPzZ_H:
10589 case AArch64::FRINTP_ZPzZ_S:
10590 case AArch64::FRINTX_ZPzZ_D:
10591 case AArch64::FRINTX_ZPzZ_H:
10592 case AArch64::FRINTX_ZPzZ_S:
10593 case AArch64::FRINTZ_ZPzZ_D:
10594 case AArch64::FRINTZ_ZPzZ_H:
10595 case AArch64::FRINTZ_ZPzZ_S:
10596 case AArch64::FSQRT_ZPZz_D:
10597 case AArch64::FSQRT_ZPZz_H:
10598 case AArch64::FSQRT_ZPZz_S:
10599 case AArch64::MOVPRFX_ZPzZ_B:
10600 case AArch64::MOVPRFX_ZPzZ_D:
10601 case AArch64::MOVPRFX_ZPzZ_H:
10602 case AArch64::MOVPRFX_ZPzZ_S:
10603 case AArch64::NEG_ZPzZ_B:
10604 case AArch64::NEG_ZPzZ_D:
10605 case AArch64::NEG_ZPzZ_H:
10606 case AArch64::NEG_ZPzZ_S:
10607 case AArch64::NOT_ZPzZ_B:
10608 case AArch64::NOT_ZPzZ_D:
10609 case AArch64::NOT_ZPzZ_H:
10610 case AArch64::NOT_ZPzZ_S:
10611 case AArch64::SCVTF_ZPzZ_DtoD:
10612 case AArch64::SCVTF_ZPzZ_DtoH:
10613 case AArch64::SCVTF_ZPzZ_DtoS:
10614 case AArch64::SCVTF_ZPzZ_HtoH:
10615 case AArch64::SCVTF_ZPzZ_StoD:
10616 case AArch64::SCVTF_ZPzZ_StoH:
10617 case AArch64::SCVTF_ZPzZ_StoS:
10618 case AArch64::SQABS_ZPzZ_B:
10619 case AArch64::SQABS_ZPzZ_D:
10620 case AArch64::SQABS_ZPzZ_H:
10621 case AArch64::SQABS_ZPzZ_S:
10622 case AArch64::SQNEG_ZPzZ_B:
10623 case AArch64::SQNEG_ZPzZ_D:
10624 case AArch64::SQNEG_ZPzZ_H:
10625 case AArch64::SQNEG_ZPzZ_S:
10626 case AArch64::SXTB_ZPzZ_D:
10627 case AArch64::SXTB_ZPzZ_H:
10628 case AArch64::SXTB_ZPzZ_S:
10629 case AArch64::SXTH_ZPzZ_D:
10630 case AArch64::SXTH_ZPzZ_S:
10631 case AArch64::SXTW_ZPzZ_D:
10632 case AArch64::UCVTF_ZPzZ_DtoD:
10633 case AArch64::UCVTF_ZPzZ_DtoH:
10634 case AArch64::UCVTF_ZPzZ_DtoS:
10635 case AArch64::UCVTF_ZPzZ_HtoH:
10636 case AArch64::UCVTF_ZPzZ_StoD:
10637 case AArch64::UCVTF_ZPzZ_StoH:
10638 case AArch64::UCVTF_ZPzZ_StoS:
10639 case AArch64::URECPE_ZPzZ_S:
10640 case AArch64::URSQRTE_ZPzZ_S:
10641 case AArch64::UXTB_ZPzZ_D:
10642 case AArch64::UXTB_ZPzZ_H:
10643 case AArch64::UXTB_ZPzZ_S:
10644 case AArch64::UXTH_ZPzZ_D:
10645 case AArch64::UXTH_ZPzZ_S:
10646 case AArch64::UXTW_ZPzZ_D: {
10647 // op: Pg
10648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10649 op &= UINT64_C(7);
10650 op <<= 10;
10651 Value |= op;
10652 // op: Zd
10653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10654 op &= UINT64_C(31);
10655 Value |= op;
10656 // op: Zn
10657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10658 op &= UINT64_C(31);
10659 op <<= 5;
10660 Value |= op;
10661 break;
10662 }
10663 case AArch64::BFMLA_ZPmZZ:
10664 case AArch64::BFMLS_ZPmZZ:
10665 case AArch64::FMLA_ZPmZZ_D:
10666 case AArch64::FMLA_ZPmZZ_H:
10667 case AArch64::FMLA_ZPmZZ_S:
10668 case AArch64::FMLS_ZPmZZ_D:
10669 case AArch64::FMLS_ZPmZZ_H:
10670 case AArch64::FMLS_ZPmZZ_S:
10671 case AArch64::FNMLA_ZPmZZ_D:
10672 case AArch64::FNMLA_ZPmZZ_H:
10673 case AArch64::FNMLA_ZPmZZ_S:
10674 case AArch64::FNMLS_ZPmZZ_D:
10675 case AArch64::FNMLS_ZPmZZ_H:
10676 case AArch64::FNMLS_ZPmZZ_S:
10677 case AArch64::MLA_ZPmZZ_B:
10678 case AArch64::MLA_ZPmZZ_D:
10679 case AArch64::MLA_ZPmZZ_H:
10680 case AArch64::MLA_ZPmZZ_S:
10681 case AArch64::MLS_ZPmZZ_B:
10682 case AArch64::MLS_ZPmZZ_D:
10683 case AArch64::MLS_ZPmZZ_H:
10684 case AArch64::MLS_ZPmZZ_S: {
10685 // op: Pg
10686 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10687 op &= UINT64_C(7);
10688 op <<= 10;
10689 Value |= op;
10690 // op: Zda
10691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10692 op &= UINT64_C(31);
10693 Value |= op;
10694 // op: Zm
10695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
10696 op &= UINT64_C(31);
10697 op <<= 16;
10698 Value |= op;
10699 // op: Zn
10700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10701 op &= UINT64_C(31);
10702 op <<= 5;
10703 Value |= op;
10704 break;
10705 }
10706 case AArch64::MAD_ZPmZZ_B:
10707 case AArch64::MAD_ZPmZZ_D:
10708 case AArch64::MAD_ZPmZZ_H:
10709 case AArch64::MAD_ZPmZZ_S:
10710 case AArch64::MSB_ZPmZZ_B:
10711 case AArch64::MSB_ZPmZZ_D:
10712 case AArch64::MSB_ZPmZZ_H:
10713 case AArch64::MSB_ZPmZZ_S: {
10714 // op: Pg
10715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10716 op &= UINT64_C(7);
10717 op <<= 10;
10718 Value |= op;
10719 // op: Zdn
10720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10721 op &= UINT64_C(31);
10722 Value |= op;
10723 // op: Za
10724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
10725 op &= UINT64_C(31);
10726 op <<= 5;
10727 Value |= op;
10728 // op: Zm
10729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10730 op &= UINT64_C(31);
10731 op <<= 16;
10732 Value |= op;
10733 break;
10734 }
10735 case AArch64::ADD_ZPmZ_B:
10736 case AArch64::ADD_ZPmZ_CPA:
10737 case AArch64::ADD_ZPmZ_D:
10738 case AArch64::ADD_ZPmZ_H:
10739 case AArch64::ADD_ZPmZ_S:
10740 case AArch64::AND_ZPmZ_B:
10741 case AArch64::AND_ZPmZ_D:
10742 case AArch64::AND_ZPmZ_H:
10743 case AArch64::AND_ZPmZ_S:
10744 case AArch64::ASRR_ZPmZ_B:
10745 case AArch64::ASRR_ZPmZ_D:
10746 case AArch64::ASRR_ZPmZ_H:
10747 case AArch64::ASRR_ZPmZ_S:
10748 case AArch64::ASR_WIDE_ZPmZ_B:
10749 case AArch64::ASR_WIDE_ZPmZ_H:
10750 case AArch64::ASR_WIDE_ZPmZ_S:
10751 case AArch64::ASR_ZPmZ_B:
10752 case AArch64::ASR_ZPmZ_D:
10753 case AArch64::ASR_ZPmZ_H:
10754 case AArch64::ASR_ZPmZ_S:
10755 case AArch64::BFADD_ZPmZZ:
10756 case AArch64::BFMAXNM_ZPmZZ:
10757 case AArch64::BFMAX_ZPmZZ:
10758 case AArch64::BFMINNM_ZPmZZ:
10759 case AArch64::BFMIN_ZPmZZ:
10760 case AArch64::BFMUL_ZPmZZ:
10761 case AArch64::BFSCALE_ZPZZ:
10762 case AArch64::BFSUB_ZPmZZ:
10763 case AArch64::BIC_ZPmZ_B:
10764 case AArch64::BIC_ZPmZ_D:
10765 case AArch64::BIC_ZPmZ_H:
10766 case AArch64::BIC_ZPmZ_S:
10767 case AArch64::CLASTA_ZPZ_B:
10768 case AArch64::CLASTA_ZPZ_D:
10769 case AArch64::CLASTA_ZPZ_H:
10770 case AArch64::CLASTA_ZPZ_S:
10771 case AArch64::CLASTB_ZPZ_B:
10772 case AArch64::CLASTB_ZPZ_D:
10773 case AArch64::CLASTB_ZPZ_H:
10774 case AArch64::CLASTB_ZPZ_S:
10775 case AArch64::EOR_ZPmZ_B:
10776 case AArch64::EOR_ZPmZ_D:
10777 case AArch64::EOR_ZPmZ_H:
10778 case AArch64::EOR_ZPmZ_S:
10779 case AArch64::FABD_ZPmZ_D:
10780 case AArch64::FABD_ZPmZ_H:
10781 case AArch64::FABD_ZPmZ_S:
10782 case AArch64::FADD_ZPmZ_D:
10783 case AArch64::FADD_ZPmZ_H:
10784 case AArch64::FADD_ZPmZ_S:
10785 case AArch64::FAMAX_ZPmZ_D:
10786 case AArch64::FAMAX_ZPmZ_H:
10787 case AArch64::FAMAX_ZPmZ_S:
10788 case AArch64::FAMIN_ZPmZ_D:
10789 case AArch64::FAMIN_ZPmZ_H:
10790 case AArch64::FAMIN_ZPmZ_S:
10791 case AArch64::FDIVR_ZPmZ_D:
10792 case AArch64::FDIVR_ZPmZ_H:
10793 case AArch64::FDIVR_ZPmZ_S:
10794 case AArch64::FDIV_ZPmZ_D:
10795 case AArch64::FDIV_ZPmZ_H:
10796 case AArch64::FDIV_ZPmZ_S:
10797 case AArch64::FMAXNM_ZPmZ_D:
10798 case AArch64::FMAXNM_ZPmZ_H:
10799 case AArch64::FMAXNM_ZPmZ_S:
10800 case AArch64::FMAX_ZPmZ_D:
10801 case AArch64::FMAX_ZPmZ_H:
10802 case AArch64::FMAX_ZPmZ_S:
10803 case AArch64::FMINNM_ZPmZ_D:
10804 case AArch64::FMINNM_ZPmZ_H:
10805 case AArch64::FMINNM_ZPmZ_S:
10806 case AArch64::FMIN_ZPmZ_D:
10807 case AArch64::FMIN_ZPmZ_H:
10808 case AArch64::FMIN_ZPmZ_S:
10809 case AArch64::FMULX_ZPmZ_D:
10810 case AArch64::FMULX_ZPmZ_H:
10811 case AArch64::FMULX_ZPmZ_S:
10812 case AArch64::FMUL_ZPmZ_D:
10813 case AArch64::FMUL_ZPmZ_H:
10814 case AArch64::FMUL_ZPmZ_S:
10815 case AArch64::FSCALE_ZPmZ_D:
10816 case AArch64::FSCALE_ZPmZ_H:
10817 case AArch64::FSCALE_ZPmZ_S:
10818 case AArch64::FSUBR_ZPmZ_D:
10819 case AArch64::FSUBR_ZPmZ_H:
10820 case AArch64::FSUBR_ZPmZ_S:
10821 case AArch64::FSUB_ZPmZ_D:
10822 case AArch64::FSUB_ZPmZ_H:
10823 case AArch64::FSUB_ZPmZ_S:
10824 case AArch64::LSLR_ZPmZ_B:
10825 case AArch64::LSLR_ZPmZ_D:
10826 case AArch64::LSLR_ZPmZ_H:
10827 case AArch64::LSLR_ZPmZ_S:
10828 case AArch64::LSL_WIDE_ZPmZ_B:
10829 case AArch64::LSL_WIDE_ZPmZ_H:
10830 case AArch64::LSL_WIDE_ZPmZ_S:
10831 case AArch64::LSL_ZPmZ_B:
10832 case AArch64::LSL_ZPmZ_D:
10833 case AArch64::LSL_ZPmZ_H:
10834 case AArch64::LSL_ZPmZ_S:
10835 case AArch64::LSRR_ZPmZ_B:
10836 case AArch64::LSRR_ZPmZ_D:
10837 case AArch64::LSRR_ZPmZ_H:
10838 case AArch64::LSRR_ZPmZ_S:
10839 case AArch64::LSR_WIDE_ZPmZ_B:
10840 case AArch64::LSR_WIDE_ZPmZ_H:
10841 case AArch64::LSR_WIDE_ZPmZ_S:
10842 case AArch64::LSR_ZPmZ_B:
10843 case AArch64::LSR_ZPmZ_D:
10844 case AArch64::LSR_ZPmZ_H:
10845 case AArch64::LSR_ZPmZ_S:
10846 case AArch64::MUL_ZPmZ_B:
10847 case AArch64::MUL_ZPmZ_D:
10848 case AArch64::MUL_ZPmZ_H:
10849 case AArch64::MUL_ZPmZ_S:
10850 case AArch64::ORR_ZPmZ_B:
10851 case AArch64::ORR_ZPmZ_D:
10852 case AArch64::ORR_ZPmZ_H:
10853 case AArch64::ORR_ZPmZ_S:
10854 case AArch64::SABD_ZPmZ_B:
10855 case AArch64::SABD_ZPmZ_D:
10856 case AArch64::SABD_ZPmZ_H:
10857 case AArch64::SABD_ZPmZ_S:
10858 case AArch64::SDIVR_ZPmZ_D:
10859 case AArch64::SDIVR_ZPmZ_S:
10860 case AArch64::SDIV_ZPmZ_D:
10861 case AArch64::SDIV_ZPmZ_S:
10862 case AArch64::SMAX_ZPmZ_B:
10863 case AArch64::SMAX_ZPmZ_D:
10864 case AArch64::SMAX_ZPmZ_H:
10865 case AArch64::SMAX_ZPmZ_S:
10866 case AArch64::SMIN_ZPmZ_B:
10867 case AArch64::SMIN_ZPmZ_D:
10868 case AArch64::SMIN_ZPmZ_H:
10869 case AArch64::SMIN_ZPmZ_S:
10870 case AArch64::SMULH_ZPmZ_B:
10871 case AArch64::SMULH_ZPmZ_D:
10872 case AArch64::SMULH_ZPmZ_H:
10873 case AArch64::SMULH_ZPmZ_S:
10874 case AArch64::SPLICE_ZPZ_B:
10875 case AArch64::SPLICE_ZPZ_D:
10876 case AArch64::SPLICE_ZPZ_H:
10877 case AArch64::SPLICE_ZPZ_S:
10878 case AArch64::SUBR_ZPmZ_B:
10879 case AArch64::SUBR_ZPmZ_D:
10880 case AArch64::SUBR_ZPmZ_H:
10881 case AArch64::SUBR_ZPmZ_S:
10882 case AArch64::SUB_ZPmZ_B:
10883 case AArch64::SUB_ZPmZ_CPA:
10884 case AArch64::SUB_ZPmZ_D:
10885 case AArch64::SUB_ZPmZ_H:
10886 case AArch64::SUB_ZPmZ_S:
10887 case AArch64::UABD_ZPmZ_B:
10888 case AArch64::UABD_ZPmZ_D:
10889 case AArch64::UABD_ZPmZ_H:
10890 case AArch64::UABD_ZPmZ_S:
10891 case AArch64::UDIVR_ZPmZ_D:
10892 case AArch64::UDIVR_ZPmZ_S:
10893 case AArch64::UDIV_ZPmZ_D:
10894 case AArch64::UDIV_ZPmZ_S:
10895 case AArch64::UMAX_ZPmZ_B:
10896 case AArch64::UMAX_ZPmZ_D:
10897 case AArch64::UMAX_ZPmZ_H:
10898 case AArch64::UMAX_ZPmZ_S:
10899 case AArch64::UMIN_ZPmZ_B:
10900 case AArch64::UMIN_ZPmZ_D:
10901 case AArch64::UMIN_ZPmZ_H:
10902 case AArch64::UMIN_ZPmZ_S:
10903 case AArch64::UMULH_ZPmZ_B:
10904 case AArch64::UMULH_ZPmZ_D:
10905 case AArch64::UMULH_ZPmZ_H:
10906 case AArch64::UMULH_ZPmZ_S: {
10907 // op: Pg
10908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10909 op &= UINT64_C(7);
10910 op <<= 10;
10911 Value |= op;
10912 // op: Zdn
10913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10914 op &= UINT64_C(31);
10915 Value |= op;
10916 // op: Zm
10917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10918 op &= UINT64_C(31);
10919 op <<= 5;
10920 Value |= op;
10921 break;
10922 }
10923 case AArch64::FADD_ZPmI_D:
10924 case AArch64::FADD_ZPmI_H:
10925 case AArch64::FADD_ZPmI_S:
10926 case AArch64::FMAXNM_ZPmI_D:
10927 case AArch64::FMAXNM_ZPmI_H:
10928 case AArch64::FMAXNM_ZPmI_S:
10929 case AArch64::FMAX_ZPmI_D:
10930 case AArch64::FMAX_ZPmI_H:
10931 case AArch64::FMAX_ZPmI_S:
10932 case AArch64::FMINNM_ZPmI_D:
10933 case AArch64::FMINNM_ZPmI_H:
10934 case AArch64::FMINNM_ZPmI_S:
10935 case AArch64::FMIN_ZPmI_D:
10936 case AArch64::FMIN_ZPmI_H:
10937 case AArch64::FMIN_ZPmI_S:
10938 case AArch64::FMUL_ZPmI_D:
10939 case AArch64::FMUL_ZPmI_H:
10940 case AArch64::FMUL_ZPmI_S:
10941 case AArch64::FSUBR_ZPmI_D:
10942 case AArch64::FSUBR_ZPmI_H:
10943 case AArch64::FSUBR_ZPmI_S:
10944 case AArch64::FSUB_ZPmI_D:
10945 case AArch64::FSUB_ZPmI_H:
10946 case AArch64::FSUB_ZPmI_S: {
10947 // op: Pg
10948 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10949 op &= UINT64_C(7);
10950 op <<= 10;
10951 Value |= op;
10952 // op: Zdn
10953 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10954 op &= UINT64_C(31);
10955 Value |= op;
10956 // op: i1
10957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10958 op &= UINT64_C(1);
10959 op <<= 5;
10960 Value |= op;
10961 break;
10962 }
10963 case AArch64::LSL_ZPmI_H:
10964 case AArch64::SQSHLU_ZPmI_H:
10965 case AArch64::SQSHL_ZPmI_H:
10966 case AArch64::UQSHL_ZPmI_H: {
10967 // op: Pg
10968 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10969 op &= UINT64_C(7);
10970 op <<= 10;
10971 Value |= op;
10972 // op: Zdn
10973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10974 op &= UINT64_C(31);
10975 Value |= op;
10976 // op: imm
10977 op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI);
10978 op &= UINT64_C(15);
10979 op <<= 5;
10980 Value |= op;
10981 break;
10982 }
10983 case AArch64::LSL_ZPmI_S:
10984 case AArch64::SQSHLU_ZPmI_S:
10985 case AArch64::SQSHL_ZPmI_S:
10986 case AArch64::UQSHL_ZPmI_S: {
10987 // op: Pg
10988 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10989 op &= UINT64_C(7);
10990 op <<= 10;
10991 Value |= op;
10992 // op: Zdn
10993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10994 op &= UINT64_C(31);
10995 Value |= op;
10996 // op: imm
10997 op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI);
10998 op &= UINT64_C(31);
10999 op <<= 5;
11000 Value |= op;
11001 break;
11002 }
11003 case AArch64::LSL_ZPmI_D:
11004 case AArch64::SQSHLU_ZPmI_D:
11005 case AArch64::SQSHL_ZPmI_D:
11006 case AArch64::UQSHL_ZPmI_D: {
11007 // op: Pg
11008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11009 op &= UINT64_C(7);
11010 op <<= 10;
11011 Value |= op;
11012 // op: Zdn
11013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11014 op &= UINT64_C(31);
11015 Value |= op;
11016 // op: imm
11017 op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI);
11018 Value |= (op & UINT64_C(32)) << 17;
11019 Value |= (op & UINT64_C(31)) << 5;
11020 break;
11021 }
11022 case AArch64::LSL_ZPmI_B:
11023 case AArch64::SQSHLU_ZPmI_B:
11024 case AArch64::SQSHL_ZPmI_B:
11025 case AArch64::UQSHL_ZPmI_B: {
11026 // op: Pg
11027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11028 op &= UINT64_C(7);
11029 op <<= 10;
11030 Value |= op;
11031 // op: Zdn
11032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11033 op &= UINT64_C(31);
11034 Value |= op;
11035 // op: imm
11036 op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI);
11037 op &= UINT64_C(7);
11038 op <<= 5;
11039 Value |= op;
11040 break;
11041 }
11042 case AArch64::ASRD_ZPmI_H:
11043 case AArch64::ASR_ZPmI_H:
11044 case AArch64::LSR_ZPmI_H:
11045 case AArch64::SRSHR_ZPmI_H:
11046 case AArch64::URSHR_ZPmI_H: {
11047 // op: Pg
11048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11049 op &= UINT64_C(7);
11050 op <<= 10;
11051 Value |= op;
11052 // op: Zdn
11053 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11054 op &= UINT64_C(31);
11055 Value |= op;
11056 // op: imm
11057 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
11058 op &= UINT64_C(15);
11059 op <<= 5;
11060 Value |= op;
11061 break;
11062 }
11063 case AArch64::ASRD_ZPmI_S:
11064 case AArch64::ASR_ZPmI_S:
11065 case AArch64::LSR_ZPmI_S:
11066 case AArch64::SRSHR_ZPmI_S:
11067 case AArch64::URSHR_ZPmI_S: {
11068 // op: Pg
11069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11070 op &= UINT64_C(7);
11071 op <<= 10;
11072 Value |= op;
11073 // op: Zdn
11074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11075 op &= UINT64_C(31);
11076 Value |= op;
11077 // op: imm
11078 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
11079 op &= UINT64_C(31);
11080 op <<= 5;
11081 Value |= op;
11082 break;
11083 }
11084 case AArch64::ASRD_ZPmI_D:
11085 case AArch64::ASR_ZPmI_D:
11086 case AArch64::LSR_ZPmI_D:
11087 case AArch64::SRSHR_ZPmI_D:
11088 case AArch64::URSHR_ZPmI_D: {
11089 // op: Pg
11090 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11091 op &= UINT64_C(7);
11092 op <<= 10;
11093 Value |= op;
11094 // op: Zdn
11095 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11096 op &= UINT64_C(31);
11097 Value |= op;
11098 // op: imm
11099 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
11100 Value |= (op & UINT64_C(32)) << 17;
11101 Value |= (op & UINT64_C(31)) << 5;
11102 break;
11103 }
11104 case AArch64::ASRD_ZPmI_B:
11105 case AArch64::ASR_ZPmI_B:
11106 case AArch64::LSR_ZPmI_B:
11107 case AArch64::SRSHR_ZPmI_B:
11108 case AArch64::URSHR_ZPmI_B: {
11109 // op: Pg
11110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11111 op &= UINT64_C(7);
11112 op <<= 10;
11113 Value |= op;
11114 // op: Zdn
11115 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11116 op &= UINT64_C(31);
11117 Value |= op;
11118 // op: imm
11119 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
11120 op &= UINT64_C(7);
11121 op <<= 5;
11122 Value |= op;
11123 break;
11124 }
11125 case AArch64::ADDP_ZPmZ_B:
11126 case AArch64::ADDP_ZPmZ_D:
11127 case AArch64::ADDP_ZPmZ_H:
11128 case AArch64::ADDP_ZPmZ_S:
11129 case AArch64::FADDP_ZPmZZ_D:
11130 case AArch64::FADDP_ZPmZZ_H:
11131 case AArch64::FADDP_ZPmZZ_S:
11132 case AArch64::FMAXNMP_ZPmZZ_D:
11133 case AArch64::FMAXNMP_ZPmZZ_H:
11134 case AArch64::FMAXNMP_ZPmZZ_S:
11135 case AArch64::FMAXP_ZPmZZ_D:
11136 case AArch64::FMAXP_ZPmZZ_H:
11137 case AArch64::FMAXP_ZPmZZ_S:
11138 case AArch64::FMINNMP_ZPmZZ_D:
11139 case AArch64::FMINNMP_ZPmZZ_H:
11140 case AArch64::FMINNMP_ZPmZZ_S:
11141 case AArch64::FMINP_ZPmZZ_D:
11142 case AArch64::FMINP_ZPmZZ_H:
11143 case AArch64::FMINP_ZPmZZ_S:
11144 case AArch64::SHADD_ZPmZ_B:
11145 case AArch64::SHADD_ZPmZ_D:
11146 case AArch64::SHADD_ZPmZ_H:
11147 case AArch64::SHADD_ZPmZ_S:
11148 case AArch64::SHSUBR_ZPmZ_B:
11149 case AArch64::SHSUBR_ZPmZ_D:
11150 case AArch64::SHSUBR_ZPmZ_H:
11151 case AArch64::SHSUBR_ZPmZ_S:
11152 case AArch64::SHSUB_ZPmZ_B:
11153 case AArch64::SHSUB_ZPmZ_D:
11154 case AArch64::SHSUB_ZPmZ_H:
11155 case AArch64::SHSUB_ZPmZ_S:
11156 case AArch64::SMAXP_ZPmZ_B:
11157 case AArch64::SMAXP_ZPmZ_D:
11158 case AArch64::SMAXP_ZPmZ_H:
11159 case AArch64::SMAXP_ZPmZ_S:
11160 case AArch64::SMINP_ZPmZ_B:
11161 case AArch64::SMINP_ZPmZ_D:
11162 case AArch64::SMINP_ZPmZ_H:
11163 case AArch64::SMINP_ZPmZ_S:
11164 case AArch64::SQADD_ZPmZ_B:
11165 case AArch64::SQADD_ZPmZ_D:
11166 case AArch64::SQADD_ZPmZ_H:
11167 case AArch64::SQADD_ZPmZ_S:
11168 case AArch64::SQRSHLR_ZPmZ_B:
11169 case AArch64::SQRSHLR_ZPmZ_D:
11170 case AArch64::SQRSHLR_ZPmZ_H:
11171 case AArch64::SQRSHLR_ZPmZ_S:
11172 case AArch64::SQRSHL_ZPmZ_B:
11173 case AArch64::SQRSHL_ZPmZ_D:
11174 case AArch64::SQRSHL_ZPmZ_H:
11175 case AArch64::SQRSHL_ZPmZ_S:
11176 case AArch64::SQSHLR_ZPmZ_B:
11177 case AArch64::SQSHLR_ZPmZ_D:
11178 case AArch64::SQSHLR_ZPmZ_H:
11179 case AArch64::SQSHLR_ZPmZ_S:
11180 case AArch64::SQSHL_ZPmZ_B:
11181 case AArch64::SQSHL_ZPmZ_D:
11182 case AArch64::SQSHL_ZPmZ_H:
11183 case AArch64::SQSHL_ZPmZ_S:
11184 case AArch64::SQSUBR_ZPmZ_B:
11185 case AArch64::SQSUBR_ZPmZ_D:
11186 case AArch64::SQSUBR_ZPmZ_H:
11187 case AArch64::SQSUBR_ZPmZ_S:
11188 case AArch64::SQSUB_ZPmZ_B:
11189 case AArch64::SQSUB_ZPmZ_D:
11190 case AArch64::SQSUB_ZPmZ_H:
11191 case AArch64::SQSUB_ZPmZ_S:
11192 case AArch64::SRHADD_ZPmZ_B:
11193 case AArch64::SRHADD_ZPmZ_D:
11194 case AArch64::SRHADD_ZPmZ_H:
11195 case AArch64::SRHADD_ZPmZ_S:
11196 case AArch64::SRSHLR_ZPmZ_B:
11197 case AArch64::SRSHLR_ZPmZ_D:
11198 case AArch64::SRSHLR_ZPmZ_H:
11199 case AArch64::SRSHLR_ZPmZ_S:
11200 case AArch64::SRSHL_ZPmZ_B:
11201 case AArch64::SRSHL_ZPmZ_D:
11202 case AArch64::SRSHL_ZPmZ_H:
11203 case AArch64::SRSHL_ZPmZ_S:
11204 case AArch64::SUQADD_ZPmZ_B:
11205 case AArch64::SUQADD_ZPmZ_D:
11206 case AArch64::SUQADD_ZPmZ_H:
11207 case AArch64::SUQADD_ZPmZ_S:
11208 case AArch64::UHADD_ZPmZ_B:
11209 case AArch64::UHADD_ZPmZ_D:
11210 case AArch64::UHADD_ZPmZ_H:
11211 case AArch64::UHADD_ZPmZ_S:
11212 case AArch64::UHSUBR_ZPmZ_B:
11213 case AArch64::UHSUBR_ZPmZ_D:
11214 case AArch64::UHSUBR_ZPmZ_H:
11215 case AArch64::UHSUBR_ZPmZ_S:
11216 case AArch64::UHSUB_ZPmZ_B:
11217 case AArch64::UHSUB_ZPmZ_D:
11218 case AArch64::UHSUB_ZPmZ_H:
11219 case AArch64::UHSUB_ZPmZ_S:
11220 case AArch64::UMAXP_ZPmZ_B:
11221 case AArch64::UMAXP_ZPmZ_D:
11222 case AArch64::UMAXP_ZPmZ_H:
11223 case AArch64::UMAXP_ZPmZ_S:
11224 case AArch64::UMINP_ZPmZ_B:
11225 case AArch64::UMINP_ZPmZ_D:
11226 case AArch64::UMINP_ZPmZ_H:
11227 case AArch64::UMINP_ZPmZ_S:
11228 case AArch64::UQADD_ZPmZ_B:
11229 case AArch64::UQADD_ZPmZ_D:
11230 case AArch64::UQADD_ZPmZ_H:
11231 case AArch64::UQADD_ZPmZ_S:
11232 case AArch64::UQRSHLR_ZPmZ_B:
11233 case AArch64::UQRSHLR_ZPmZ_D:
11234 case AArch64::UQRSHLR_ZPmZ_H:
11235 case AArch64::UQRSHLR_ZPmZ_S:
11236 case AArch64::UQRSHL_ZPmZ_B:
11237 case AArch64::UQRSHL_ZPmZ_D:
11238 case AArch64::UQRSHL_ZPmZ_H:
11239 case AArch64::UQRSHL_ZPmZ_S:
11240 case AArch64::UQSHLR_ZPmZ_B:
11241 case AArch64::UQSHLR_ZPmZ_D:
11242 case AArch64::UQSHLR_ZPmZ_H:
11243 case AArch64::UQSHLR_ZPmZ_S:
11244 case AArch64::UQSHL_ZPmZ_B:
11245 case AArch64::UQSHL_ZPmZ_D:
11246 case AArch64::UQSHL_ZPmZ_H:
11247 case AArch64::UQSHL_ZPmZ_S:
11248 case AArch64::UQSUBR_ZPmZ_B:
11249 case AArch64::UQSUBR_ZPmZ_D:
11250 case AArch64::UQSUBR_ZPmZ_H:
11251 case AArch64::UQSUBR_ZPmZ_S:
11252 case AArch64::UQSUB_ZPmZ_B:
11253 case AArch64::UQSUB_ZPmZ_D:
11254 case AArch64::UQSUB_ZPmZ_H:
11255 case AArch64::UQSUB_ZPmZ_S:
11256 case AArch64::URHADD_ZPmZ_B:
11257 case AArch64::URHADD_ZPmZ_D:
11258 case AArch64::URHADD_ZPmZ_H:
11259 case AArch64::URHADD_ZPmZ_S:
11260 case AArch64::URSHLR_ZPmZ_B:
11261 case AArch64::URSHLR_ZPmZ_D:
11262 case AArch64::URSHLR_ZPmZ_H:
11263 case AArch64::URSHLR_ZPmZ_S:
11264 case AArch64::URSHL_ZPmZ_B:
11265 case AArch64::URSHL_ZPmZ_D:
11266 case AArch64::URSHL_ZPmZ_H:
11267 case AArch64::URSHL_ZPmZ_S:
11268 case AArch64::USQADD_ZPmZ_B:
11269 case AArch64::USQADD_ZPmZ_D:
11270 case AArch64::USQADD_ZPmZ_H:
11271 case AArch64::USQADD_ZPmZ_S: {
11272 // op: Pg
11273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11274 op &= UINT64_C(7);
11275 op <<= 10;
11276 Value |= op;
11277 // op: Zm
11278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11279 op &= UINT64_C(31);
11280 op <<= 5;
11281 Value |= op;
11282 // op: Zdn
11283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11284 op &= UINT64_C(31);
11285 Value |= op;
11286 break;
11287 }
11288 case AArch64::EXPAND_ZPZ_B:
11289 case AArch64::EXPAND_ZPZ_D:
11290 case AArch64::EXPAND_ZPZ_H:
11291 case AArch64::EXPAND_ZPZ_S:
11292 case AArch64::SPLICE_ZPZZ_B:
11293 case AArch64::SPLICE_ZPZZ_D:
11294 case AArch64::SPLICE_ZPZZ_H:
11295 case AArch64::SPLICE_ZPZZ_S: {
11296 // op: Pg
11297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11298 op &= UINT64_C(7);
11299 op <<= 10;
11300 Value |= op;
11301 // op: Zn
11302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11303 op &= UINT64_C(31);
11304 op <<= 5;
11305 Value |= op;
11306 // op: Zd
11307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11308 op &= UINT64_C(31);
11309 Value |= op;
11310 break;
11311 }
11312 case AArch64::GLD1B_D_IMM:
11313 case AArch64::GLD1B_S_IMM:
11314 case AArch64::GLD1D_IMM:
11315 case AArch64::GLD1H_D_IMM:
11316 case AArch64::GLD1H_S_IMM:
11317 case AArch64::GLD1SB_D_IMM:
11318 case AArch64::GLD1SB_S_IMM:
11319 case AArch64::GLD1SH_D_IMM:
11320 case AArch64::GLD1SH_S_IMM:
11321 case AArch64::GLD1SW_D_IMM:
11322 case AArch64::GLD1W_D_IMM:
11323 case AArch64::GLD1W_IMM:
11324 case AArch64::GLDFF1B_D_IMM:
11325 case AArch64::GLDFF1B_S_IMM:
11326 case AArch64::GLDFF1D_IMM:
11327 case AArch64::GLDFF1H_D_IMM:
11328 case AArch64::GLDFF1H_S_IMM:
11329 case AArch64::GLDFF1SB_D_IMM:
11330 case AArch64::GLDFF1SB_S_IMM:
11331 case AArch64::GLDFF1SH_D_IMM:
11332 case AArch64::GLDFF1SH_S_IMM:
11333 case AArch64::GLDFF1SW_D_IMM:
11334 case AArch64::GLDFF1W_D_IMM:
11335 case AArch64::GLDFF1W_IMM: {
11336 // op: Pg
11337 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11338 op &= UINT64_C(7);
11339 op <<= 10;
11340 Value |= op;
11341 // op: Zn
11342 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11343 op &= UINT64_C(31);
11344 op <<= 5;
11345 Value |= op;
11346 // op: Zt
11347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11348 op &= UINT64_C(31);
11349 Value |= op;
11350 // op: imm5
11351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11352 op &= UINT64_C(31);
11353 op <<= 16;
11354 Value |= op;
11355 break;
11356 }
11357 case AArch64::PRFB_D_PZI:
11358 case AArch64::PRFB_S_PZI:
11359 case AArch64::PRFD_D_PZI:
11360 case AArch64::PRFD_S_PZI:
11361 case AArch64::PRFH_D_PZI:
11362 case AArch64::PRFH_S_PZI:
11363 case AArch64::PRFW_D_PZI:
11364 case AArch64::PRFW_S_PZI: {
11365 // op: Pg
11366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11367 op &= UINT64_C(7);
11368 op <<= 10;
11369 Value |= op;
11370 // op: Zn
11371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11372 op &= UINT64_C(31);
11373 op <<= 5;
11374 Value |= op;
11375 // op: imm5
11376 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11377 op &= UINT64_C(31);
11378 op <<= 16;
11379 Value |= op;
11380 // op: prfop
11381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11382 op &= UINT64_C(15);
11383 Value |= op;
11384 break;
11385 }
11386 case AArch64::SADALP_ZPmZ_D:
11387 case AArch64::SADALP_ZPmZ_H:
11388 case AArch64::SADALP_ZPmZ_S:
11389 case AArch64::UADALP_ZPmZ_D:
11390 case AArch64::UADALP_ZPmZ_H:
11391 case AArch64::UADALP_ZPmZ_S: {
11392 // op: Pg
11393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11394 op &= UINT64_C(7);
11395 op <<= 10;
11396 Value |= op;
11397 // op: Zn
11398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11399 op &= UINT64_C(31);
11400 op <<= 5;
11401 Value |= op;
11402 // op: Zda
11403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11404 op &= UINT64_C(31);
11405 Value |= op;
11406 break;
11407 }
11408 case AArch64::SST1B_D_IMM:
11409 case AArch64::SST1B_S_IMM:
11410 case AArch64::SST1D_IMM:
11411 case AArch64::SST1H_D_IMM:
11412 case AArch64::SST1H_S_IMM:
11413 case AArch64::SST1W_D_IMM:
11414 case AArch64::SST1W_IMM: {
11415 // op: Pg
11416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11417 op &= UINT64_C(7);
11418 op <<= 10;
11419 Value |= op;
11420 // op: imm5
11421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11422 op &= UINT64_C(31);
11423 op <<= 16;
11424 Value |= op;
11425 // op: Zn
11426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11427 op &= UINT64_C(31);
11428 op <<= 5;
11429 Value |= op;
11430 // op: Zt
11431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11432 op &= UINT64_C(31);
11433 Value |= op;
11434 break;
11435 }
11436 case AArch64::FCPY_ZPmI_D:
11437 case AArch64::FCPY_ZPmI_H:
11438 case AArch64::FCPY_ZPmI_S: {
11439 // op: Pg
11440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11441 op &= UINT64_C(15);
11442 op <<= 16;
11443 Value |= op;
11444 // op: Zd
11445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11446 op &= UINT64_C(31);
11447 Value |= op;
11448 // op: imm8
11449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11450 op &= UINT64_C(255);
11451 op <<= 5;
11452 Value |= op;
11453 break;
11454 }
11455 case AArch64::CPY_ZPmR_B:
11456 case AArch64::CPY_ZPmR_D:
11457 case AArch64::CPY_ZPmR_H:
11458 case AArch64::CPY_ZPmR_S: {
11459 // op: Pg
11460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11461 op &= UINT64_C(7);
11462 op <<= 10;
11463 Value |= op;
11464 // op: Rn
11465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11466 op &= UINT64_C(31);
11467 op <<= 5;
11468 Value |= op;
11469 // op: Zd
11470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11471 op &= UINT64_C(31);
11472 Value |= op;
11473 break;
11474 }
11475 case AArch64::CPY_ZPmV_B:
11476 case AArch64::CPY_ZPmV_D:
11477 case AArch64::CPY_ZPmV_H:
11478 case AArch64::CPY_ZPmV_S: {
11479 // op: Pg
11480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11481 op &= UINT64_C(7);
11482 op <<= 10;
11483 Value |= op;
11484 // op: Vn
11485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11486 op &= UINT64_C(31);
11487 op <<= 5;
11488 Value |= op;
11489 // op: Zd
11490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11491 op &= UINT64_C(31);
11492 Value |= op;
11493 break;
11494 }
11495 case AArch64::ABS_ZPmZ_B:
11496 case AArch64::ABS_ZPmZ_D:
11497 case AArch64::ABS_ZPmZ_H:
11498 case AArch64::ABS_ZPmZ_S:
11499 case AArch64::BFCVT_ZPmZ:
11500 case AArch64::CLS_ZPmZ_B:
11501 case AArch64::CLS_ZPmZ_D:
11502 case AArch64::CLS_ZPmZ_H:
11503 case AArch64::CLS_ZPmZ_S:
11504 case AArch64::CLZ_ZPmZ_B:
11505 case AArch64::CLZ_ZPmZ_D:
11506 case AArch64::CLZ_ZPmZ_H:
11507 case AArch64::CLZ_ZPmZ_S:
11508 case AArch64::CNOT_ZPmZ_B:
11509 case AArch64::CNOT_ZPmZ_D:
11510 case AArch64::CNOT_ZPmZ_H:
11511 case AArch64::CNOT_ZPmZ_S:
11512 case AArch64::CNT_ZPmZ_B:
11513 case AArch64::CNT_ZPmZ_D:
11514 case AArch64::CNT_ZPmZ_H:
11515 case AArch64::CNT_ZPmZ_S:
11516 case AArch64::FABS_ZPmZ_D:
11517 case AArch64::FABS_ZPmZ_H:
11518 case AArch64::FABS_ZPmZ_S:
11519 case AArch64::FCVTX_ZPmZ_DtoS:
11520 case AArch64::FCVTZS_ZPmZ_DtoD:
11521 case AArch64::FCVTZS_ZPmZ_DtoS:
11522 case AArch64::FCVTZS_ZPmZ_HtoD:
11523 case AArch64::FCVTZS_ZPmZ_HtoH:
11524 case AArch64::FCVTZS_ZPmZ_HtoS:
11525 case AArch64::FCVTZS_ZPmZ_StoD:
11526 case AArch64::FCVTZS_ZPmZ_StoS:
11527 case AArch64::FCVTZU_ZPmZ_DtoD:
11528 case AArch64::FCVTZU_ZPmZ_DtoS:
11529 case AArch64::FCVTZU_ZPmZ_HtoD:
11530 case AArch64::FCVTZU_ZPmZ_HtoH:
11531 case AArch64::FCVTZU_ZPmZ_HtoS:
11532 case AArch64::FCVTZU_ZPmZ_StoD:
11533 case AArch64::FCVTZU_ZPmZ_StoS:
11534 case AArch64::FCVT_ZPmZ_DtoH:
11535 case AArch64::FCVT_ZPmZ_DtoS:
11536 case AArch64::FCVT_ZPmZ_HtoD:
11537 case AArch64::FCVT_ZPmZ_HtoS:
11538 case AArch64::FCVT_ZPmZ_StoD:
11539 case AArch64::FCVT_ZPmZ_StoH:
11540 case AArch64::FLOGB_ZPmZ_D:
11541 case AArch64::FLOGB_ZPmZ_H:
11542 case AArch64::FLOGB_ZPmZ_S:
11543 case AArch64::FNEG_ZPmZ_D:
11544 case AArch64::FNEG_ZPmZ_H:
11545 case AArch64::FNEG_ZPmZ_S:
11546 case AArch64::FRECPX_ZPmZ_D:
11547 case AArch64::FRECPX_ZPmZ_H:
11548 case AArch64::FRECPX_ZPmZ_S:
11549 case AArch64::FRINT32X_ZPmZ_D:
11550 case AArch64::FRINT32X_ZPmZ_S:
11551 case AArch64::FRINT32Z_ZPmZ_D:
11552 case AArch64::FRINT32Z_ZPmZ_S:
11553 case AArch64::FRINT64X_ZPmZ_D:
11554 case AArch64::FRINT64X_ZPmZ_S:
11555 case AArch64::FRINT64Z_ZPmZ_D:
11556 case AArch64::FRINT64Z_ZPmZ_S:
11557 case AArch64::FRINTA_ZPmZ_D:
11558 case AArch64::FRINTA_ZPmZ_H:
11559 case AArch64::FRINTA_ZPmZ_S:
11560 case AArch64::FRINTI_ZPmZ_D:
11561 case AArch64::FRINTI_ZPmZ_H:
11562 case AArch64::FRINTI_ZPmZ_S:
11563 case AArch64::FRINTM_ZPmZ_D:
11564 case AArch64::FRINTM_ZPmZ_H:
11565 case AArch64::FRINTM_ZPmZ_S:
11566 case AArch64::FRINTN_ZPmZ_D:
11567 case AArch64::FRINTN_ZPmZ_H:
11568 case AArch64::FRINTN_ZPmZ_S:
11569 case AArch64::FRINTP_ZPmZ_D:
11570 case AArch64::FRINTP_ZPmZ_H:
11571 case AArch64::FRINTP_ZPmZ_S:
11572 case AArch64::FRINTX_ZPmZ_D:
11573 case AArch64::FRINTX_ZPmZ_H:
11574 case AArch64::FRINTX_ZPmZ_S:
11575 case AArch64::FRINTZ_ZPmZ_D:
11576 case AArch64::FRINTZ_ZPmZ_H:
11577 case AArch64::FRINTZ_ZPmZ_S:
11578 case AArch64::FSQRT_ZPmZ_D:
11579 case AArch64::FSQRT_ZPmZ_H:
11580 case AArch64::FSQRT_ZPmZ_S:
11581 case AArch64::MOVPRFX_ZPmZ_B:
11582 case AArch64::MOVPRFX_ZPmZ_D:
11583 case AArch64::MOVPRFX_ZPmZ_H:
11584 case AArch64::MOVPRFX_ZPmZ_S:
11585 case AArch64::NEG_ZPmZ_B:
11586 case AArch64::NEG_ZPmZ_D:
11587 case AArch64::NEG_ZPmZ_H:
11588 case AArch64::NEG_ZPmZ_S:
11589 case AArch64::NOT_ZPmZ_B:
11590 case AArch64::NOT_ZPmZ_D:
11591 case AArch64::NOT_ZPmZ_H:
11592 case AArch64::NOT_ZPmZ_S:
11593 case AArch64::SCVTF_ZPmZ_DtoD:
11594 case AArch64::SCVTF_ZPmZ_DtoH:
11595 case AArch64::SCVTF_ZPmZ_DtoS:
11596 case AArch64::SCVTF_ZPmZ_HtoH:
11597 case AArch64::SCVTF_ZPmZ_StoD:
11598 case AArch64::SCVTF_ZPmZ_StoH:
11599 case AArch64::SCVTF_ZPmZ_StoS:
11600 case AArch64::SQABS_ZPmZ_B:
11601 case AArch64::SQABS_ZPmZ_D:
11602 case AArch64::SQABS_ZPmZ_H:
11603 case AArch64::SQABS_ZPmZ_S:
11604 case AArch64::SQNEG_ZPmZ_B:
11605 case AArch64::SQNEG_ZPmZ_D:
11606 case AArch64::SQNEG_ZPmZ_H:
11607 case AArch64::SQNEG_ZPmZ_S:
11608 case AArch64::SXTB_ZPmZ_D:
11609 case AArch64::SXTB_ZPmZ_H:
11610 case AArch64::SXTB_ZPmZ_S:
11611 case AArch64::SXTH_ZPmZ_D:
11612 case AArch64::SXTH_ZPmZ_S:
11613 case AArch64::SXTW_ZPmZ_D:
11614 case AArch64::UCVTF_ZPmZ_DtoD:
11615 case AArch64::UCVTF_ZPmZ_DtoH:
11616 case AArch64::UCVTF_ZPmZ_DtoS:
11617 case AArch64::UCVTF_ZPmZ_HtoH:
11618 case AArch64::UCVTF_ZPmZ_StoD:
11619 case AArch64::UCVTF_ZPmZ_StoH:
11620 case AArch64::UCVTF_ZPmZ_StoS:
11621 case AArch64::URECPE_ZPmZ_S:
11622 case AArch64::URSQRTE_ZPmZ_S:
11623 case AArch64::UXTB_ZPmZ_D:
11624 case AArch64::UXTB_ZPmZ_H:
11625 case AArch64::UXTB_ZPmZ_S:
11626 case AArch64::UXTH_ZPmZ_D:
11627 case AArch64::UXTH_ZPmZ_S:
11628 case AArch64::UXTW_ZPmZ_D: {
11629 // op: Pg
11630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11631 op &= UINT64_C(7);
11632 op <<= 10;
11633 Value |= op;
11634 // op: Zd
11635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11636 op &= UINT64_C(31);
11637 Value |= op;
11638 // op: Zn
11639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11640 op &= UINT64_C(31);
11641 op <<= 5;
11642 Value |= op;
11643 break;
11644 }
11645 case AArch64::DECP_ZP_D:
11646 case AArch64::DECP_ZP_H:
11647 case AArch64::DECP_ZP_S:
11648 case AArch64::INCP_ZP_D:
11649 case AArch64::INCP_ZP_H:
11650 case AArch64::INCP_ZP_S:
11651 case AArch64::SQDECP_ZP_D:
11652 case AArch64::SQDECP_ZP_H:
11653 case AArch64::SQDECP_ZP_S:
11654 case AArch64::SQINCP_ZP_D:
11655 case AArch64::SQINCP_ZP_H:
11656 case AArch64::SQINCP_ZP_S:
11657 case AArch64::UQDECP_ZP_D:
11658 case AArch64::UQDECP_ZP_H:
11659 case AArch64::UQDECP_ZP_S:
11660 case AArch64::UQINCP_ZP_D:
11661 case AArch64::UQINCP_ZP_H:
11662 case AArch64::UQINCP_ZP_S: {
11663 // op: Pm
11664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11665 op &= UINT64_C(15);
11666 op <<= 5;
11667 Value |= op;
11668 // op: Zdn
11669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11670 op &= UINT64_C(31);
11671 Value |= op;
11672 break;
11673 }
11674 case AArch64::ADDHA_MPPZ_S:
11675 case AArch64::ADDVA_MPPZ_S: {
11676 // op: Pm
11677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11678 op &= UINT64_C(7);
11679 op <<= 13;
11680 Value |= op;
11681 // op: Pn
11682 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11683 op &= UINT64_C(7);
11684 op <<= 10;
11685 Value |= op;
11686 // op: Zn
11687 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11688 op &= UINT64_C(31);
11689 op <<= 5;
11690 Value |= op;
11691 // op: ZAda
11692 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11693 op &= UINT64_C(3);
11694 Value |= op;
11695 break;
11696 }
11697 case AArch64::ADDHA_MPPZ_D:
11698 case AArch64::ADDVA_MPPZ_D: {
11699 // op: Pm
11700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11701 op &= UINT64_C(7);
11702 op <<= 13;
11703 Value |= op;
11704 // op: Pn
11705 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11706 op &= UINT64_C(7);
11707 op <<= 10;
11708 Value |= op;
11709 // op: Zn
11710 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
11711 op &= UINT64_C(31);
11712 op <<= 5;
11713 Value |= op;
11714 // op: ZAda
11715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11716 op &= UINT64_C(7);
11717 Value |= op;
11718 break;
11719 }
11720 case AArch64::WRFFR: {
11721 // op: Pn
11722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11723 op &= UINT64_C(15);
11724 op <<= 5;
11725 Value |= op;
11726 break;
11727 }
11728 case AArch64::LDR_PXI:
11729 case AArch64::STR_PXI: {
11730 // op: Pt
11731 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11732 op &= UINT64_C(15);
11733 Value |= op;
11734 // op: Rn
11735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11736 op &= UINT64_C(31);
11737 op <<= 5;
11738 Value |= op;
11739 // op: imm9
11740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11741 Value |= (op & UINT64_C(504)) << 13;
11742 Value |= (op & UINT64_C(7)) << 10;
11743 break;
11744 }
11745 case AArch64::XPACD:
11746 case AArch64::XPACI: {
11747 // op: Rd
11748 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11749 op &= UINT64_C(31);
11750 Value |= op;
11751 break;
11752 }
11753 case AArch64::CNTP_XCI_B:
11754 case AArch64::CNTP_XCI_D:
11755 case AArch64::CNTP_XCI_H:
11756 case AArch64::CNTP_XCI_S: {
11757 // op: Rd
11758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11759 op &= UINT64_C(31);
11760 Value |= op;
11761 // op: PNn
11762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11763 op &= UINT64_C(15);
11764 op <<= 5;
11765 Value |= op;
11766 // op: vl
11767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11768 op &= UINT64_C(1);
11769 op <<= 10;
11770 Value |= op;
11771 break;
11772 }
11773 case AArch64::ADDPL_XXI:
11774 case AArch64::ADDSPL_XXI:
11775 case AArch64::ADDSVL_XXI:
11776 case AArch64::ADDVL_XXI: {
11777 // op: Rd
11778 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11779 op &= UINT64_C(31);
11780 Value |= op;
11781 // op: Rn
11782 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11783 op &= UINT64_C(31);
11784 op <<= 16;
11785 Value |= op;
11786 // op: imm6
11787 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11788 op &= UINT64_C(63);
11789 op <<= 5;
11790 Value |= op;
11791 break;
11792 }
11793 case AArch64::ABSWr:
11794 case AArch64::ABSXr:
11795 case AArch64::ABSv1i64:
11796 case AArch64::ABSv2i32:
11797 case AArch64::ABSv2i64:
11798 case AArch64::ABSv4i16:
11799 case AArch64::ABSv4i32:
11800 case AArch64::ABSv8i8:
11801 case AArch64::ABSv8i16:
11802 case AArch64::ABSv16i8:
11803 case AArch64::ADDPv2i64p:
11804 case AArch64::ADDVv4i16v:
11805 case AArch64::ADDVv4i32v:
11806 case AArch64::ADDVv8i8v:
11807 case AArch64::ADDVv8i16v:
11808 case AArch64::ADDVv16i8v:
11809 case AArch64::AESIMCrr:
11810 case AArch64::AESMCrr:
11811 case AArch64::BF1CVTL:
11812 case AArch64::BF1CVTL2:
11813 case AArch64::BF2CVTL:
11814 case AArch64::BF2CVTL2:
11815 case AArch64::BFCVT:
11816 case AArch64::BFCVTN:
11817 case AArch64::CLSWr:
11818 case AArch64::CLSXr:
11819 case AArch64::CLSv2i32:
11820 case AArch64::CLSv4i16:
11821 case AArch64::CLSv4i32:
11822 case AArch64::CLSv8i8:
11823 case AArch64::CLSv8i16:
11824 case AArch64::CLSv16i8:
11825 case AArch64::CLZWr:
11826 case AArch64::CLZXr:
11827 case AArch64::CLZv2i32:
11828 case AArch64::CLZv4i16:
11829 case AArch64::CLZv4i32:
11830 case AArch64::CLZv8i8:
11831 case AArch64::CLZv8i16:
11832 case AArch64::CLZv16i8:
11833 case AArch64::CMEQv1i64rz:
11834 case AArch64::CMEQv2i32rz:
11835 case AArch64::CMEQv2i64rz:
11836 case AArch64::CMEQv4i16rz:
11837 case AArch64::CMEQv4i32rz:
11838 case AArch64::CMEQv8i8rz:
11839 case AArch64::CMEQv8i16rz:
11840 case AArch64::CMEQv16i8rz:
11841 case AArch64::CMGEv1i64rz:
11842 case AArch64::CMGEv2i32rz:
11843 case AArch64::CMGEv2i64rz:
11844 case AArch64::CMGEv4i16rz:
11845 case AArch64::CMGEv4i32rz:
11846 case AArch64::CMGEv8i8rz:
11847 case AArch64::CMGEv8i16rz:
11848 case AArch64::CMGEv16i8rz:
11849 case AArch64::CMGTv1i64rz:
11850 case AArch64::CMGTv2i32rz:
11851 case AArch64::CMGTv2i64rz:
11852 case AArch64::CMGTv4i16rz:
11853 case AArch64::CMGTv4i32rz:
11854 case AArch64::CMGTv8i8rz:
11855 case AArch64::CMGTv8i16rz:
11856 case AArch64::CMGTv16i8rz:
11857 case AArch64::CMLEv1i64rz:
11858 case AArch64::CMLEv2i32rz:
11859 case AArch64::CMLEv2i64rz:
11860 case AArch64::CMLEv4i16rz:
11861 case AArch64::CMLEv4i32rz:
11862 case AArch64::CMLEv8i8rz:
11863 case AArch64::CMLEv8i16rz:
11864 case AArch64::CMLEv16i8rz:
11865 case AArch64::CMLTv1i64rz:
11866 case AArch64::CMLTv2i32rz:
11867 case AArch64::CMLTv2i64rz:
11868 case AArch64::CMLTv4i16rz:
11869 case AArch64::CMLTv4i32rz:
11870 case AArch64::CMLTv8i8rz:
11871 case AArch64::CMLTv8i16rz:
11872 case AArch64::CMLTv16i8rz:
11873 case AArch64::CNTWr:
11874 case AArch64::CNTXr:
11875 case AArch64::CNTv8i8:
11876 case AArch64::CNTv16i8:
11877 case AArch64::CTZWr:
11878 case AArch64::CTZXr:
11879 case AArch64::DUPv2i32gpr:
11880 case AArch64::DUPv2i64gpr:
11881 case AArch64::DUPv4i16gpr:
11882 case AArch64::DUPv4i32gpr:
11883 case AArch64::DUPv8i8gpr:
11884 case AArch64::DUPv8i16gpr:
11885 case AArch64::DUPv16i8gpr:
11886 case AArch64::F1CVTL:
11887 case AArch64::F1CVTL2:
11888 case AArch64::F2CVTL:
11889 case AArch64::F2CVTL2:
11890 case AArch64::FABSDr:
11891 case AArch64::FABSHr:
11892 case AArch64::FABSSr:
11893 case AArch64::FABSv2f32:
11894 case AArch64::FABSv2f64:
11895 case AArch64::FABSv4f16:
11896 case AArch64::FABSv4f32:
11897 case AArch64::FABSv8f16:
11898 case AArch64::FADDPv2i16p:
11899 case AArch64::FADDPv2i32p:
11900 case AArch64::FADDPv2i64p:
11901 case AArch64::FCMEQv1i16rz:
11902 case AArch64::FCMEQv1i32rz:
11903 case AArch64::FCMEQv1i64rz:
11904 case AArch64::FCMEQv2i32rz:
11905 case AArch64::FCMEQv2i64rz:
11906 case AArch64::FCMEQv4i16rz:
11907 case AArch64::FCMEQv4i32rz:
11908 case AArch64::FCMEQv8i16rz:
11909 case AArch64::FCMGEv1i16rz:
11910 case AArch64::FCMGEv1i32rz:
11911 case AArch64::FCMGEv1i64rz:
11912 case AArch64::FCMGEv2i32rz:
11913 case AArch64::FCMGEv2i64rz:
11914 case AArch64::FCMGEv4i16rz:
11915 case AArch64::FCMGEv4i32rz:
11916 case AArch64::FCMGEv8i16rz:
11917 case AArch64::FCMGTv1i16rz:
11918 case AArch64::FCMGTv1i32rz:
11919 case AArch64::FCMGTv1i64rz:
11920 case AArch64::FCMGTv2i32rz:
11921 case AArch64::FCMGTv2i64rz:
11922 case AArch64::FCMGTv4i16rz:
11923 case AArch64::FCMGTv4i32rz:
11924 case AArch64::FCMGTv8i16rz:
11925 case AArch64::FCMLEv1i16rz:
11926 case AArch64::FCMLEv1i32rz:
11927 case AArch64::FCMLEv1i64rz:
11928 case AArch64::FCMLEv2i32rz:
11929 case AArch64::FCMLEv2i64rz:
11930 case AArch64::FCMLEv4i16rz:
11931 case AArch64::FCMLEv4i32rz:
11932 case AArch64::FCMLEv8i16rz:
11933 case AArch64::FCMLTv1i16rz:
11934 case AArch64::FCMLTv1i32rz:
11935 case AArch64::FCMLTv1i64rz:
11936 case AArch64::FCMLTv2i32rz:
11937 case AArch64::FCMLTv2i64rz:
11938 case AArch64::FCMLTv4i16rz:
11939 case AArch64::FCMLTv4i32rz:
11940 case AArch64::FCMLTv8i16rz:
11941 case AArch64::FCVTASDHr:
11942 case AArch64::FCVTASDSr:
11943 case AArch64::FCVTASSDr:
11944 case AArch64::FCVTASSHr:
11945 case AArch64::FCVTASUWDr:
11946 case AArch64::FCVTASUWHr:
11947 case AArch64::FCVTASUWSr:
11948 case AArch64::FCVTASUXDr:
11949 case AArch64::FCVTASUXHr:
11950 case AArch64::FCVTASUXSr:
11951 case AArch64::FCVTASv1f16:
11952 case AArch64::FCVTASv1i32:
11953 case AArch64::FCVTASv1i64:
11954 case AArch64::FCVTASv2f32:
11955 case AArch64::FCVTASv2f64:
11956 case AArch64::FCVTASv4f16:
11957 case AArch64::FCVTASv4f32:
11958 case AArch64::FCVTASv8f16:
11959 case AArch64::FCVTAUDHr:
11960 case AArch64::FCVTAUDSr:
11961 case AArch64::FCVTAUSDr:
11962 case AArch64::FCVTAUSHr:
11963 case AArch64::FCVTAUUWDr:
11964 case AArch64::FCVTAUUWHr:
11965 case AArch64::FCVTAUUWSr:
11966 case AArch64::FCVTAUUXDr:
11967 case AArch64::FCVTAUUXHr:
11968 case AArch64::FCVTAUUXSr:
11969 case AArch64::FCVTAUv1f16:
11970 case AArch64::FCVTAUv1i32:
11971 case AArch64::FCVTAUv1i64:
11972 case AArch64::FCVTAUv2f32:
11973 case AArch64::FCVTAUv2f64:
11974 case AArch64::FCVTAUv4f16:
11975 case AArch64::FCVTAUv4f32:
11976 case AArch64::FCVTAUv8f16:
11977 case AArch64::FCVTDHr:
11978 case AArch64::FCVTDSr:
11979 case AArch64::FCVTHDr:
11980 case AArch64::FCVTHSr:
11981 case AArch64::FCVTLv2i32:
11982 case AArch64::FCVTLv4i16:
11983 case AArch64::FCVTLv4i32:
11984 case AArch64::FCVTLv8i16:
11985 case AArch64::FCVTMSDHr:
11986 case AArch64::FCVTMSDSr:
11987 case AArch64::FCVTMSSDr:
11988 case AArch64::FCVTMSSHr:
11989 case AArch64::FCVTMSUWDr:
11990 case AArch64::FCVTMSUWHr:
11991 case AArch64::FCVTMSUWSr:
11992 case AArch64::FCVTMSUXDr:
11993 case AArch64::FCVTMSUXHr:
11994 case AArch64::FCVTMSUXSr:
11995 case AArch64::FCVTMSv1f16:
11996 case AArch64::FCVTMSv1i32:
11997 case AArch64::FCVTMSv1i64:
11998 case AArch64::FCVTMSv2f32:
11999 case AArch64::FCVTMSv2f64:
12000 case AArch64::FCVTMSv4f16:
12001 case AArch64::FCVTMSv4f32:
12002 case AArch64::FCVTMSv8f16:
12003 case AArch64::FCVTMUDHr:
12004 case AArch64::FCVTMUDSr:
12005 case AArch64::FCVTMUSDr:
12006 case AArch64::FCVTMUSHr:
12007 case AArch64::FCVTMUUWDr:
12008 case AArch64::FCVTMUUWHr:
12009 case AArch64::FCVTMUUWSr:
12010 case AArch64::FCVTMUUXDr:
12011 case AArch64::FCVTMUUXHr:
12012 case AArch64::FCVTMUUXSr:
12013 case AArch64::FCVTMUv1f16:
12014 case AArch64::FCVTMUv1i32:
12015 case AArch64::FCVTMUv1i64:
12016 case AArch64::FCVTMUv2f32:
12017 case AArch64::FCVTMUv2f64:
12018 case AArch64::FCVTMUv4f16:
12019 case AArch64::FCVTMUv4f32:
12020 case AArch64::FCVTMUv8f16:
12021 case AArch64::FCVTNSDHr:
12022 case AArch64::FCVTNSDSr:
12023 case AArch64::FCVTNSSDr:
12024 case AArch64::FCVTNSSHr:
12025 case AArch64::FCVTNSUWDr:
12026 case AArch64::FCVTNSUWHr:
12027 case AArch64::FCVTNSUWSr:
12028 case AArch64::FCVTNSUXDr:
12029 case AArch64::FCVTNSUXHr:
12030 case AArch64::FCVTNSUXSr:
12031 case AArch64::FCVTNSv1f16:
12032 case AArch64::FCVTNSv1i32:
12033 case AArch64::FCVTNSv1i64:
12034 case AArch64::FCVTNSv2f32:
12035 case AArch64::FCVTNSv2f64:
12036 case AArch64::FCVTNSv4f16:
12037 case AArch64::FCVTNSv4f32:
12038 case AArch64::FCVTNSv8f16:
12039 case AArch64::FCVTNUDHr:
12040 case AArch64::FCVTNUDSr:
12041 case AArch64::FCVTNUSDr:
12042 case AArch64::FCVTNUSHr:
12043 case AArch64::FCVTNUUWDr:
12044 case AArch64::FCVTNUUWHr:
12045 case AArch64::FCVTNUUWSr:
12046 case AArch64::FCVTNUUXDr:
12047 case AArch64::FCVTNUUXHr:
12048 case AArch64::FCVTNUUXSr:
12049 case AArch64::FCVTNUv1f16:
12050 case AArch64::FCVTNUv1i32:
12051 case AArch64::FCVTNUv1i64:
12052 case AArch64::FCVTNUv2f32:
12053 case AArch64::FCVTNUv2f64:
12054 case AArch64::FCVTNUv4f16:
12055 case AArch64::FCVTNUv4f32:
12056 case AArch64::FCVTNUv8f16:
12057 case AArch64::FCVTNv2i32:
12058 case AArch64::FCVTNv4i16:
12059 case AArch64::FCVTPSDHr:
12060 case AArch64::FCVTPSDSr:
12061 case AArch64::FCVTPSSDr:
12062 case AArch64::FCVTPSSHr:
12063 case AArch64::FCVTPSUWDr:
12064 case AArch64::FCVTPSUWHr:
12065 case AArch64::FCVTPSUWSr:
12066 case AArch64::FCVTPSUXDr:
12067 case AArch64::FCVTPSUXHr:
12068 case AArch64::FCVTPSUXSr:
12069 case AArch64::FCVTPSv1f16:
12070 case AArch64::FCVTPSv1i32:
12071 case AArch64::FCVTPSv1i64:
12072 case AArch64::FCVTPSv2f32:
12073 case AArch64::FCVTPSv2f64:
12074 case AArch64::FCVTPSv4f16:
12075 case AArch64::FCVTPSv4f32:
12076 case AArch64::FCVTPSv8f16:
12077 case AArch64::FCVTPUDHr:
12078 case AArch64::FCVTPUDSr:
12079 case AArch64::FCVTPUSDr:
12080 case AArch64::FCVTPUSHr:
12081 case AArch64::FCVTPUUWDr:
12082 case AArch64::FCVTPUUWHr:
12083 case AArch64::FCVTPUUWSr:
12084 case AArch64::FCVTPUUXDr:
12085 case AArch64::FCVTPUUXHr:
12086 case AArch64::FCVTPUUXSr:
12087 case AArch64::FCVTPUv1f16:
12088 case AArch64::FCVTPUv1i32:
12089 case AArch64::FCVTPUv1i64:
12090 case AArch64::FCVTPUv2f32:
12091 case AArch64::FCVTPUv2f64:
12092 case AArch64::FCVTPUv4f16:
12093 case AArch64::FCVTPUv4f32:
12094 case AArch64::FCVTPUv8f16:
12095 case AArch64::FCVTSDr:
12096 case AArch64::FCVTSHr:
12097 case AArch64::FCVTXNv1i64:
12098 case AArch64::FCVTXNv2f32:
12099 case AArch64::FCVTZSDHr:
12100 case AArch64::FCVTZSDSr:
12101 case AArch64::FCVTZSSDr:
12102 case AArch64::FCVTZSSHr:
12103 case AArch64::FCVTZSUWDr:
12104 case AArch64::FCVTZSUWHr:
12105 case AArch64::FCVTZSUWSr:
12106 case AArch64::FCVTZSUXDr:
12107 case AArch64::FCVTZSUXHr:
12108 case AArch64::FCVTZSUXSr:
12109 case AArch64::FCVTZSv1f16:
12110 case AArch64::FCVTZSv1i32:
12111 case AArch64::FCVTZSv1i64:
12112 case AArch64::FCVTZSv2f32:
12113 case AArch64::FCVTZSv2f64:
12114 case AArch64::FCVTZSv4f16:
12115 case AArch64::FCVTZSv4f32:
12116 case AArch64::FCVTZSv8f16:
12117 case AArch64::FCVTZUDHr:
12118 case AArch64::FCVTZUDSr:
12119 case AArch64::FCVTZUSDr:
12120 case AArch64::FCVTZUSHr:
12121 case AArch64::FCVTZUUWDr:
12122 case AArch64::FCVTZUUWHr:
12123 case AArch64::FCVTZUUWSr:
12124 case AArch64::FCVTZUUXDr:
12125 case AArch64::FCVTZUUXHr:
12126 case AArch64::FCVTZUUXSr:
12127 case AArch64::FCVTZUv1f16:
12128 case AArch64::FCVTZUv1i32:
12129 case AArch64::FCVTZUv1i64:
12130 case AArch64::FCVTZUv2f32:
12131 case AArch64::FCVTZUv2f64:
12132 case AArch64::FCVTZUv4f16:
12133 case AArch64::FCVTZUv4f32:
12134 case AArch64::FCVTZUv8f16:
12135 case AArch64::FJCVTZS:
12136 case AArch64::FMAXNMPv2i16p:
12137 case AArch64::FMAXNMPv2i32p:
12138 case AArch64::FMAXNMPv2i64p:
12139 case AArch64::FMAXNMVv4i16v:
12140 case AArch64::FMAXNMVv4i32v:
12141 case AArch64::FMAXNMVv8i16v:
12142 case AArch64::FMAXPv2i16p:
12143 case AArch64::FMAXPv2i32p:
12144 case AArch64::FMAXPv2i64p:
12145 case AArch64::FMAXVv4i16v:
12146 case AArch64::FMAXVv4i32v:
12147 case AArch64::FMAXVv8i16v:
12148 case AArch64::FMINNMPv2i16p:
12149 case AArch64::FMINNMPv2i32p:
12150 case AArch64::FMINNMPv2i64p:
12151 case AArch64::FMINNMVv4i16v:
12152 case AArch64::FMINNMVv4i32v:
12153 case AArch64::FMINNMVv8i16v:
12154 case AArch64::FMINPv2i16p:
12155 case AArch64::FMINPv2i32p:
12156 case AArch64::FMINPv2i64p:
12157 case AArch64::FMINVv4i16v:
12158 case AArch64::FMINVv4i32v:
12159 case AArch64::FMINVv8i16v:
12160 case AArch64::FMOVDXHighr:
12161 case AArch64::FMOVDXr:
12162 case AArch64::FMOVDr:
12163 case AArch64::FMOVHWr:
12164 case AArch64::FMOVHXr:
12165 case AArch64::FMOVHr:
12166 case AArch64::FMOVSWr:
12167 case AArch64::FMOVSr:
12168 case AArch64::FMOVWHr:
12169 case AArch64::FMOVWSr:
12170 case AArch64::FMOVXDHighr:
12171 case AArch64::FMOVXDr:
12172 case AArch64::FMOVXHr:
12173 case AArch64::FNEGDr:
12174 case AArch64::FNEGHr:
12175 case AArch64::FNEGSr:
12176 case AArch64::FNEGv2f32:
12177 case AArch64::FNEGv2f64:
12178 case AArch64::FNEGv4f16:
12179 case AArch64::FNEGv4f32:
12180 case AArch64::FNEGv8f16:
12181 case AArch64::FRECPEv1f16:
12182 case AArch64::FRECPEv1i32:
12183 case AArch64::FRECPEv1i64:
12184 case AArch64::FRECPEv2f32:
12185 case AArch64::FRECPEv2f64:
12186 case AArch64::FRECPEv4f16:
12187 case AArch64::FRECPEv4f32:
12188 case AArch64::FRECPEv8f16:
12189 case AArch64::FRECPXv1f16:
12190 case AArch64::FRECPXv1i32:
12191 case AArch64::FRECPXv1i64:
12192 case AArch64::FRINT32XDr:
12193 case AArch64::FRINT32XSr:
12194 case AArch64::FRINT32Xv2f32:
12195 case AArch64::FRINT32Xv2f64:
12196 case AArch64::FRINT32Xv4f32:
12197 case AArch64::FRINT32ZDr:
12198 case AArch64::FRINT32ZSr:
12199 case AArch64::FRINT32Zv2f32:
12200 case AArch64::FRINT32Zv2f64:
12201 case AArch64::FRINT32Zv4f32:
12202 case AArch64::FRINT64XDr:
12203 case AArch64::FRINT64XSr:
12204 case AArch64::FRINT64Xv2f32:
12205 case AArch64::FRINT64Xv2f64:
12206 case AArch64::FRINT64Xv4f32:
12207 case AArch64::FRINT64ZDr:
12208 case AArch64::FRINT64ZSr:
12209 case AArch64::FRINT64Zv2f32:
12210 case AArch64::FRINT64Zv2f64:
12211 case AArch64::FRINT64Zv4f32:
12212 case AArch64::FRINTADr:
12213 case AArch64::FRINTAHr:
12214 case AArch64::FRINTASr:
12215 case AArch64::FRINTAv2f32:
12216 case AArch64::FRINTAv2f64:
12217 case AArch64::FRINTAv4f16:
12218 case AArch64::FRINTAv4f32:
12219 case AArch64::FRINTAv8f16:
12220 case AArch64::FRINTIDr:
12221 case AArch64::FRINTIHr:
12222 case AArch64::FRINTISr:
12223 case AArch64::FRINTIv2f32:
12224 case AArch64::FRINTIv2f64:
12225 case AArch64::FRINTIv4f16:
12226 case AArch64::FRINTIv4f32:
12227 case AArch64::FRINTIv8f16:
12228 case AArch64::FRINTMDr:
12229 case AArch64::FRINTMHr:
12230 case AArch64::FRINTMSr:
12231 case AArch64::FRINTMv2f32:
12232 case AArch64::FRINTMv2f64:
12233 case AArch64::FRINTMv4f16:
12234 case AArch64::FRINTMv4f32:
12235 case AArch64::FRINTMv8f16:
12236 case AArch64::FRINTNDr:
12237 case AArch64::FRINTNHr:
12238 case AArch64::FRINTNSr:
12239 case AArch64::FRINTNv2f32:
12240 case AArch64::FRINTNv2f64:
12241 case AArch64::FRINTNv4f16:
12242 case AArch64::FRINTNv4f32:
12243 case AArch64::FRINTNv8f16:
12244 case AArch64::FRINTPDr:
12245 case AArch64::FRINTPHr:
12246 case AArch64::FRINTPSr:
12247 case AArch64::FRINTPv2f32:
12248 case AArch64::FRINTPv2f64:
12249 case AArch64::FRINTPv4f16:
12250 case AArch64::FRINTPv4f32:
12251 case AArch64::FRINTPv8f16:
12252 case AArch64::FRINTXDr:
12253 case AArch64::FRINTXHr:
12254 case AArch64::FRINTXSr:
12255 case AArch64::FRINTXv2f32:
12256 case AArch64::FRINTXv2f64:
12257 case AArch64::FRINTXv4f16:
12258 case AArch64::FRINTXv4f32:
12259 case AArch64::FRINTXv8f16:
12260 case AArch64::FRINTZDr:
12261 case AArch64::FRINTZHr:
12262 case AArch64::FRINTZSr:
12263 case AArch64::FRINTZv2f32:
12264 case AArch64::FRINTZv2f64:
12265 case AArch64::FRINTZv4f16:
12266 case AArch64::FRINTZv4f32:
12267 case AArch64::FRINTZv8f16:
12268 case AArch64::FRSQRTEv1f16:
12269 case AArch64::FRSQRTEv1i32:
12270 case AArch64::FRSQRTEv1i64:
12271 case AArch64::FRSQRTEv2f32:
12272 case AArch64::FRSQRTEv2f64:
12273 case AArch64::FRSQRTEv4f16:
12274 case AArch64::FRSQRTEv4f32:
12275 case AArch64::FRSQRTEv8f16:
12276 case AArch64::FSQRTDr:
12277 case AArch64::FSQRTHr:
12278 case AArch64::FSQRTSr:
12279 case AArch64::FSQRTv2f32:
12280 case AArch64::FSQRTv2f64:
12281 case AArch64::FSQRTv4f16:
12282 case AArch64::FSQRTv4f32:
12283 case AArch64::FSQRTv8f16:
12284 case AArch64::NEGv1i64:
12285 case AArch64::NEGv2i32:
12286 case AArch64::NEGv2i64:
12287 case AArch64::NEGv4i16:
12288 case AArch64::NEGv4i32:
12289 case AArch64::NEGv8i8:
12290 case AArch64::NEGv8i16:
12291 case AArch64::NEGv16i8:
12292 case AArch64::NOTv8i8:
12293 case AArch64::NOTv16i8:
12294 case AArch64::RBITWr:
12295 case AArch64::RBITXr:
12296 case AArch64::RBITv8i8:
12297 case AArch64::RBITv16i8:
12298 case AArch64::REV16Wr:
12299 case AArch64::REV16Xr:
12300 case AArch64::REV16v8i8:
12301 case AArch64::REV16v16i8:
12302 case AArch64::REV32Xr:
12303 case AArch64::REV32v4i16:
12304 case AArch64::REV32v8i8:
12305 case AArch64::REV32v8i16:
12306 case AArch64::REV32v16i8:
12307 case AArch64::REV64v2i32:
12308 case AArch64::REV64v4i16:
12309 case AArch64::REV64v4i32:
12310 case AArch64::REV64v8i8:
12311 case AArch64::REV64v8i16:
12312 case AArch64::REV64v16i8:
12313 case AArch64::REVWr:
12314 case AArch64::REVXr:
12315 case AArch64::SADDLPv2i32_v1i64:
12316 case AArch64::SADDLPv4i16_v2i32:
12317 case AArch64::SADDLPv4i32_v2i64:
12318 case AArch64::SADDLPv8i8_v4i16:
12319 case AArch64::SADDLPv8i16_v4i32:
12320 case AArch64::SADDLPv16i8_v8i16:
12321 case AArch64::SADDLVv4i16v:
12322 case AArch64::SADDLVv4i32v:
12323 case AArch64::SADDLVv8i8v:
12324 case AArch64::SADDLVv8i16v:
12325 case AArch64::SADDLVv16i8v:
12326 case AArch64::SCVTFDSr:
12327 case AArch64::SCVTFHDr:
12328 case AArch64::SCVTFHSr:
12329 case AArch64::SCVTFSDr:
12330 case AArch64::SCVTFUWDri:
12331 case AArch64::SCVTFUWHri:
12332 case AArch64::SCVTFUWSri:
12333 case AArch64::SCVTFUXDri:
12334 case AArch64::SCVTFUXHri:
12335 case AArch64::SCVTFUXSri:
12336 case AArch64::SCVTFv1i16:
12337 case AArch64::SCVTFv1i32:
12338 case AArch64::SCVTFv1i64:
12339 case AArch64::SCVTFv2f32:
12340 case AArch64::SCVTFv2f64:
12341 case AArch64::SCVTFv4f16:
12342 case AArch64::SCVTFv4f32:
12343 case AArch64::SCVTFv8f16:
12344 case AArch64::SHA1Hrr:
12345 case AArch64::SHLLv2i32:
12346 case AArch64::SHLLv4i16:
12347 case AArch64::SHLLv4i32:
12348 case AArch64::SHLLv8i8:
12349 case AArch64::SHLLv8i16:
12350 case AArch64::SHLLv16i8:
12351 case AArch64::SMAXVv4i16v:
12352 case AArch64::SMAXVv4i32v:
12353 case AArch64::SMAXVv8i8v:
12354 case AArch64::SMAXVv8i16v:
12355 case AArch64::SMAXVv16i8v:
12356 case AArch64::SMINVv4i16v:
12357 case AArch64::SMINVv4i32v:
12358 case AArch64::SMINVv8i8v:
12359 case AArch64::SMINVv8i16v:
12360 case AArch64::SMINVv16i8v:
12361 case AArch64::SMOVvi8to32_idx0:
12362 case AArch64::SMOVvi8to64_idx0:
12363 case AArch64::SMOVvi16to32_idx0:
12364 case AArch64::SMOVvi16to64_idx0:
12365 case AArch64::SMOVvi32to64_idx0:
12366 case AArch64::SQABSv1i8:
12367 case AArch64::SQABSv1i16:
12368 case AArch64::SQABSv1i32:
12369 case AArch64::SQABSv1i64:
12370 case AArch64::SQABSv2i32:
12371 case AArch64::SQABSv2i64:
12372 case AArch64::SQABSv4i16:
12373 case AArch64::SQABSv4i32:
12374 case AArch64::SQABSv8i8:
12375 case AArch64::SQABSv8i16:
12376 case AArch64::SQABSv16i8:
12377 case AArch64::SQNEGv1i8:
12378 case AArch64::SQNEGv1i16:
12379 case AArch64::SQNEGv1i32:
12380 case AArch64::SQNEGv1i64:
12381 case AArch64::SQNEGv2i32:
12382 case AArch64::SQNEGv2i64:
12383 case AArch64::SQNEGv4i16:
12384 case AArch64::SQNEGv4i32:
12385 case AArch64::SQNEGv8i8:
12386 case AArch64::SQNEGv8i16:
12387 case AArch64::SQNEGv16i8:
12388 case AArch64::SQXTNv1i8:
12389 case AArch64::SQXTNv1i16:
12390 case AArch64::SQXTNv1i32:
12391 case AArch64::SQXTNv2i32:
12392 case AArch64::SQXTNv4i16:
12393 case AArch64::SQXTNv8i8:
12394 case AArch64::SQXTUNv1i8:
12395 case AArch64::SQXTUNv1i16:
12396 case AArch64::SQXTUNv1i32:
12397 case AArch64::SQXTUNv2i32:
12398 case AArch64::SQXTUNv4i16:
12399 case AArch64::SQXTUNv8i8:
12400 case AArch64::UADDLPv2i32_v1i64:
12401 case AArch64::UADDLPv4i16_v2i32:
12402 case AArch64::UADDLPv4i32_v2i64:
12403 case AArch64::UADDLPv8i8_v4i16:
12404 case AArch64::UADDLPv8i16_v4i32:
12405 case AArch64::UADDLPv16i8_v8i16:
12406 case AArch64::UADDLVv4i16v:
12407 case AArch64::UADDLVv4i32v:
12408 case AArch64::UADDLVv8i8v:
12409 case AArch64::UADDLVv8i16v:
12410 case AArch64::UADDLVv16i8v:
12411 case AArch64::UCVTFDSr:
12412 case AArch64::UCVTFHDr:
12413 case AArch64::UCVTFHSr:
12414 case AArch64::UCVTFSDr:
12415 case AArch64::UCVTFUWDri:
12416 case AArch64::UCVTFUWHri:
12417 case AArch64::UCVTFUWSri:
12418 case AArch64::UCVTFUXDri:
12419 case AArch64::UCVTFUXHri:
12420 case AArch64::UCVTFUXSri:
12421 case AArch64::UCVTFv1i16:
12422 case AArch64::UCVTFv1i32:
12423 case AArch64::UCVTFv1i64:
12424 case AArch64::UCVTFv2f32:
12425 case AArch64::UCVTFv2f64:
12426 case AArch64::UCVTFv4f16:
12427 case AArch64::UCVTFv4f32:
12428 case AArch64::UCVTFv8f16:
12429 case AArch64::UMAXVv4i16v:
12430 case AArch64::UMAXVv4i32v:
12431 case AArch64::UMAXVv8i8v:
12432 case AArch64::UMAXVv8i16v:
12433 case AArch64::UMAXVv16i8v:
12434 case AArch64::UMINVv4i16v:
12435 case AArch64::UMINVv4i32v:
12436 case AArch64::UMINVv8i8v:
12437 case AArch64::UMINVv8i16v:
12438 case AArch64::UMINVv16i8v:
12439 case AArch64::UMOVvi8_idx0:
12440 case AArch64::UMOVvi16_idx0:
12441 case AArch64::UMOVvi32_idx0:
12442 case AArch64::UMOVvi64_idx0:
12443 case AArch64::UQXTNv1i8:
12444 case AArch64::UQXTNv1i16:
12445 case AArch64::UQXTNv1i32:
12446 case AArch64::UQXTNv2i32:
12447 case AArch64::UQXTNv4i16:
12448 case AArch64::UQXTNv8i8:
12449 case AArch64::URECPEv2i32:
12450 case AArch64::URECPEv4i32:
12451 case AArch64::URSQRTEv2i32:
12452 case AArch64::URSQRTEv4i32:
12453 case AArch64::XTNv2i32:
12454 case AArch64::XTNv4i16:
12455 case AArch64::XTNv8i8: {
12456 // op: Rd
12457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12458 op &= UINT64_C(31);
12459 Value |= op;
12460 // op: Rn
12461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12462 op &= UINT64_C(31);
12463 op <<= 5;
12464 Value |= op;
12465 break;
12466 }
12467 case AArch64::FMULXv1i16_indexed:
12468 case AArch64::FMULXv4i16_indexed:
12469 case AArch64::FMULXv8i16_indexed:
12470 case AArch64::FMULv1i16_indexed:
12471 case AArch64::FMULv4i16_indexed:
12472 case AArch64::FMULv8i16_indexed:
12473 case AArch64::MULv4i16_indexed:
12474 case AArch64::MULv8i16_indexed:
12475 case AArch64::SMULLv4i16_indexed:
12476 case AArch64::SMULLv8i16_indexed:
12477 case AArch64::SQDMULHv1i16_indexed:
12478 case AArch64::SQDMULHv4i16_indexed:
12479 case AArch64::SQDMULHv8i16_indexed:
12480 case AArch64::SQDMULLv1i32_indexed:
12481 case AArch64::SQDMULLv4i16_indexed:
12482 case AArch64::SQDMULLv8i16_indexed:
12483 case AArch64::SQRDMULHv1i16_indexed:
12484 case AArch64::SQRDMULHv4i16_indexed:
12485 case AArch64::SQRDMULHv8i16_indexed:
12486 case AArch64::UMULLv4i16_indexed:
12487 case AArch64::UMULLv8i16_indexed: {
12488 // op: Rd
12489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12490 op &= UINT64_C(31);
12491 Value |= op;
12492 // op: Rn
12493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12494 op &= UINT64_C(31);
12495 op <<= 5;
12496 Value |= op;
12497 // op: Rm
12498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12499 op &= UINT64_C(15);
12500 op <<= 16;
12501 Value |= op;
12502 // op: idx
12503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12504 Value |= (op & UINT64_C(3)) << 20;
12505 Value |= (op & UINT64_C(4)) << 9;
12506 break;
12507 }
12508 case AArch64::ADCSWr:
12509 case AArch64::ADCSXr:
12510 case AArch64::ADCWr:
12511 case AArch64::ADCXr:
12512 case AArch64::ADDHNv2i64_v2i32:
12513 case AArch64::ADDHNv4i32_v4i16:
12514 case AArch64::ADDHNv8i16_v8i8:
12515 case AArch64::ADDPv2i32:
12516 case AArch64::ADDPv2i64:
12517 case AArch64::ADDPv4i16:
12518 case AArch64::ADDPv4i32:
12519 case AArch64::ADDPv8i8:
12520 case AArch64::ADDPv8i16:
12521 case AArch64::ADDPv16i8:
12522 case AArch64::ADDv1i64:
12523 case AArch64::ADDv2i32:
12524 case AArch64::ADDv2i64:
12525 case AArch64::ADDv4i16:
12526 case AArch64::ADDv4i32:
12527 case AArch64::ADDv8i8:
12528 case AArch64::ADDv8i16:
12529 case AArch64::ADDv16i8:
12530 case AArch64::ANDv8i8:
12531 case AArch64::ANDv16i8:
12532 case AArch64::ASRVWr:
12533 case AArch64::ASRVXr:
12534 case AArch64::BICv8i8:
12535 case AArch64::BICv16i8:
12536 case AArch64::CMEQv1i64:
12537 case AArch64::CMEQv2i32:
12538 case AArch64::CMEQv2i64:
12539 case AArch64::CMEQv4i16:
12540 case AArch64::CMEQv4i32:
12541 case AArch64::CMEQv8i8:
12542 case AArch64::CMEQv8i16:
12543 case AArch64::CMEQv16i8:
12544 case AArch64::CMGEv1i64:
12545 case AArch64::CMGEv2i32:
12546 case AArch64::CMGEv2i64:
12547 case AArch64::CMGEv4i16:
12548 case AArch64::CMGEv4i32:
12549 case AArch64::CMGEv8i8:
12550 case AArch64::CMGEv8i16:
12551 case AArch64::CMGEv16i8:
12552 case AArch64::CMGTv1i64:
12553 case AArch64::CMGTv2i32:
12554 case AArch64::CMGTv2i64:
12555 case AArch64::CMGTv4i16:
12556 case AArch64::CMGTv4i32:
12557 case AArch64::CMGTv8i8:
12558 case AArch64::CMGTv8i16:
12559 case AArch64::CMGTv16i8:
12560 case AArch64::CMHIv1i64:
12561 case AArch64::CMHIv2i32:
12562 case AArch64::CMHIv2i64:
12563 case AArch64::CMHIv4i16:
12564 case AArch64::CMHIv4i32:
12565 case AArch64::CMHIv8i8:
12566 case AArch64::CMHIv8i16:
12567 case AArch64::CMHIv16i8:
12568 case AArch64::CMHSv1i64:
12569 case AArch64::CMHSv2i32:
12570 case AArch64::CMHSv2i64:
12571 case AArch64::CMHSv4i16:
12572 case AArch64::CMHSv4i32:
12573 case AArch64::CMHSv8i8:
12574 case AArch64::CMHSv8i16:
12575 case AArch64::CMHSv16i8:
12576 case AArch64::CMTSTv1i64:
12577 case AArch64::CMTSTv2i32:
12578 case AArch64::CMTSTv2i64:
12579 case AArch64::CMTSTv4i16:
12580 case AArch64::CMTSTv4i32:
12581 case AArch64::CMTSTv8i8:
12582 case AArch64::CMTSTv8i16:
12583 case AArch64::CMTSTv16i8:
12584 case AArch64::CRC32Brr:
12585 case AArch64::CRC32CBrr:
12586 case AArch64::CRC32CHrr:
12587 case AArch64::CRC32CWrr:
12588 case AArch64::CRC32CXrr:
12589 case AArch64::CRC32Hrr:
12590 case AArch64::CRC32Wrr:
12591 case AArch64::CRC32Xrr:
12592 case AArch64::EORv8i8:
12593 case AArch64::EORv16i8:
12594 case AArch64::FABD16:
12595 case AArch64::FABD32:
12596 case AArch64::FABD64:
12597 case AArch64::FABDv2f32:
12598 case AArch64::FABDv2f64:
12599 case AArch64::FABDv4f16:
12600 case AArch64::FABDv4f32:
12601 case AArch64::FABDv8f16:
12602 case AArch64::FACGE16:
12603 case AArch64::FACGE32:
12604 case AArch64::FACGE64:
12605 case AArch64::FACGEv2f32:
12606 case AArch64::FACGEv2f64:
12607 case AArch64::FACGEv4f16:
12608 case AArch64::FACGEv4f32:
12609 case AArch64::FACGEv8f16:
12610 case AArch64::FACGT16:
12611 case AArch64::FACGT32:
12612 case AArch64::FACGT64:
12613 case AArch64::FACGTv2f32:
12614 case AArch64::FACGTv2f64:
12615 case AArch64::FACGTv4f16:
12616 case AArch64::FACGTv4f32:
12617 case AArch64::FACGTv8f16:
12618 case AArch64::FADDDrr:
12619 case AArch64::FADDHrr:
12620 case AArch64::FADDPv2f32:
12621 case AArch64::FADDPv2f64:
12622 case AArch64::FADDPv4f16:
12623 case AArch64::FADDPv4f32:
12624 case AArch64::FADDPv8f16:
12625 case AArch64::FADDSrr:
12626 case AArch64::FADDv2f32:
12627 case AArch64::FADDv2f64:
12628 case AArch64::FADDv4f16:
12629 case AArch64::FADDv4f32:
12630 case AArch64::FADDv8f16:
12631 case AArch64::FAMAXv2f32:
12632 case AArch64::FAMAXv2f64:
12633 case AArch64::FAMAXv4f16:
12634 case AArch64::FAMAXv4f32:
12635 case AArch64::FAMAXv8f16:
12636 case AArch64::FAMINv2f32:
12637 case AArch64::FAMINv2f64:
12638 case AArch64::FAMINv4f16:
12639 case AArch64::FAMINv4f32:
12640 case AArch64::FAMINv8f16:
12641 case AArch64::FCMEQ16:
12642 case AArch64::FCMEQ32:
12643 case AArch64::FCMEQ64:
12644 case AArch64::FCMEQv2f32:
12645 case AArch64::FCMEQv2f64:
12646 case AArch64::FCMEQv4f16:
12647 case AArch64::FCMEQv4f32:
12648 case AArch64::FCMEQv8f16:
12649 case AArch64::FCMGE16:
12650 case AArch64::FCMGE32:
12651 case AArch64::FCMGE64:
12652 case AArch64::FCMGEv2f32:
12653 case AArch64::FCMGEv2f64:
12654 case AArch64::FCMGEv4f16:
12655 case AArch64::FCMGEv4f32:
12656 case AArch64::FCMGEv8f16:
12657 case AArch64::FCMGT16:
12658 case AArch64::FCMGT32:
12659 case AArch64::FCMGT64:
12660 case AArch64::FCMGTv2f32:
12661 case AArch64::FCMGTv2f64:
12662 case AArch64::FCMGTv4f16:
12663 case AArch64::FCMGTv4f32:
12664 case AArch64::FCMGTv8f16:
12665 case AArch64::FCVTN_F16v8f8:
12666 case AArch64::FCVTN_F16v16f8:
12667 case AArch64::FCVTN_F32v8f8:
12668 case AArch64::FDIVDrr:
12669 case AArch64::FDIVHrr:
12670 case AArch64::FDIVSrr:
12671 case AArch64::FDIVv2f32:
12672 case AArch64::FDIVv2f64:
12673 case AArch64::FDIVv4f16:
12674 case AArch64::FDIVv4f32:
12675 case AArch64::FDIVv8f16:
12676 case AArch64::FMAXDrr:
12677 case AArch64::FMAXHrr:
12678 case AArch64::FMAXNMDrr:
12679 case AArch64::FMAXNMHrr:
12680 case AArch64::FMAXNMPv2f32:
12681 case AArch64::FMAXNMPv2f64:
12682 case AArch64::FMAXNMPv4f16:
12683 case AArch64::FMAXNMPv4f32:
12684 case AArch64::FMAXNMPv8f16:
12685 case AArch64::FMAXNMSrr:
12686 case AArch64::FMAXNMv2f32:
12687 case AArch64::FMAXNMv2f64:
12688 case AArch64::FMAXNMv4f16:
12689 case AArch64::FMAXNMv4f32:
12690 case AArch64::FMAXNMv8f16:
12691 case AArch64::FMAXPv2f32:
12692 case AArch64::FMAXPv2f64:
12693 case AArch64::FMAXPv4f16:
12694 case AArch64::FMAXPv4f32:
12695 case AArch64::FMAXPv8f16:
12696 case AArch64::FMAXSrr:
12697 case AArch64::FMAXv2f32:
12698 case AArch64::FMAXv2f64:
12699 case AArch64::FMAXv4f16:
12700 case AArch64::FMAXv4f32:
12701 case AArch64::FMAXv8f16:
12702 case AArch64::FMINDrr:
12703 case AArch64::FMINHrr:
12704 case AArch64::FMINNMDrr:
12705 case AArch64::FMINNMHrr:
12706 case AArch64::FMINNMPv2f32:
12707 case AArch64::FMINNMPv2f64:
12708 case AArch64::FMINNMPv4f16:
12709 case AArch64::FMINNMPv4f32:
12710 case AArch64::FMINNMPv8f16:
12711 case AArch64::FMINNMSrr:
12712 case AArch64::FMINNMv2f32:
12713 case AArch64::FMINNMv2f64:
12714 case AArch64::FMINNMv4f16:
12715 case AArch64::FMINNMv4f32:
12716 case AArch64::FMINNMv8f16:
12717 case AArch64::FMINPv2f32:
12718 case AArch64::FMINPv2f64:
12719 case AArch64::FMINPv4f16:
12720 case AArch64::FMINPv4f32:
12721 case AArch64::FMINPv8f16:
12722 case AArch64::FMINSrr:
12723 case AArch64::FMINv2f32:
12724 case AArch64::FMINv2f64:
12725 case AArch64::FMINv4f16:
12726 case AArch64::FMINv4f32:
12727 case AArch64::FMINv8f16:
12728 case AArch64::FMULDrr:
12729 case AArch64::FMULHrr:
12730 case AArch64::FMULSrr:
12731 case AArch64::FMULX16:
12732 case AArch64::FMULX32:
12733 case AArch64::FMULX64:
12734 case AArch64::FMULXv2f32:
12735 case AArch64::FMULXv2f64:
12736 case AArch64::FMULXv4f16:
12737 case AArch64::FMULXv4f32:
12738 case AArch64::FMULXv8f16:
12739 case AArch64::FMULv2f32:
12740 case AArch64::FMULv2f64:
12741 case AArch64::FMULv4f16:
12742 case AArch64::FMULv4f32:
12743 case AArch64::FMULv8f16:
12744 case AArch64::FNMULDrr:
12745 case AArch64::FNMULHrr:
12746 case AArch64::FNMULSrr:
12747 case AArch64::FRECPS16:
12748 case AArch64::FRECPS32:
12749 case AArch64::FRECPS64:
12750 case AArch64::FRECPSv2f32:
12751 case AArch64::FRECPSv2f64:
12752 case AArch64::FRECPSv4f16:
12753 case AArch64::FRECPSv4f32:
12754 case AArch64::FRECPSv8f16:
12755 case AArch64::FRSQRTS16:
12756 case AArch64::FRSQRTS32:
12757 case AArch64::FRSQRTS64:
12758 case AArch64::FRSQRTSv2f32:
12759 case AArch64::FRSQRTSv2f64:
12760 case AArch64::FRSQRTSv4f16:
12761 case AArch64::FRSQRTSv4f32:
12762 case AArch64::FRSQRTSv8f16:
12763 case AArch64::FSCALEv2f32:
12764 case AArch64::FSCALEv2f64:
12765 case AArch64::FSCALEv4f16:
12766 case AArch64::FSCALEv4f32:
12767 case AArch64::FSCALEv8f16:
12768 case AArch64::FSUBDrr:
12769 case AArch64::FSUBHrr:
12770 case AArch64::FSUBSrr:
12771 case AArch64::FSUBv2f32:
12772 case AArch64::FSUBv2f64:
12773 case AArch64::FSUBv4f16:
12774 case AArch64::FSUBv4f32:
12775 case AArch64::FSUBv8f16:
12776 case AArch64::GMI:
12777 case AArch64::IRG:
12778 case AArch64::LSLVWr:
12779 case AArch64::LSLVXr:
12780 case AArch64::LSRVWr:
12781 case AArch64::LSRVXr:
12782 case AArch64::MULv2i32:
12783 case AArch64::MULv4i16:
12784 case AArch64::MULv4i32:
12785 case AArch64::MULv8i8:
12786 case AArch64::MULv8i16:
12787 case AArch64::MULv16i8:
12788 case AArch64::ORNv8i8:
12789 case AArch64::ORNv16i8:
12790 case AArch64::ORRv8i8:
12791 case AArch64::ORRv16i8:
12792 case AArch64::PACGA:
12793 case AArch64::PMULLv1i64:
12794 case AArch64::PMULLv2i64:
12795 case AArch64::PMULLv8i8:
12796 case AArch64::PMULLv16i8:
12797 case AArch64::PMULv8i8:
12798 case AArch64::PMULv16i8:
12799 case AArch64::RADDHNv2i64_v2i32:
12800 case AArch64::RADDHNv4i32_v4i16:
12801 case AArch64::RADDHNv8i16_v8i8:
12802 case AArch64::RORVWr:
12803 case AArch64::RORVXr:
12804 case AArch64::RSUBHNv2i64_v2i32:
12805 case AArch64::RSUBHNv4i32_v4i16:
12806 case AArch64::RSUBHNv8i16_v8i8:
12807 case AArch64::SABDLv2i32_v2i64:
12808 case AArch64::SABDLv4i16_v4i32:
12809 case AArch64::SABDLv4i32_v2i64:
12810 case AArch64::SABDLv8i8_v8i16:
12811 case AArch64::SABDLv8i16_v4i32:
12812 case AArch64::SABDLv16i8_v8i16:
12813 case AArch64::SABDv2i32:
12814 case AArch64::SABDv4i16:
12815 case AArch64::SABDv4i32:
12816 case AArch64::SABDv8i8:
12817 case AArch64::SABDv8i16:
12818 case AArch64::SABDv16i8:
12819 case AArch64::SADDLv2i32_v2i64:
12820 case AArch64::SADDLv4i16_v4i32:
12821 case AArch64::SADDLv4i32_v2i64:
12822 case AArch64::SADDLv8i8_v8i16:
12823 case AArch64::SADDLv8i16_v4i32:
12824 case AArch64::SADDLv16i8_v8i16:
12825 case AArch64::SADDWv2i32_v2i64:
12826 case AArch64::SADDWv4i16_v4i32:
12827 case AArch64::SADDWv4i32_v2i64:
12828 case AArch64::SADDWv8i8_v8i16:
12829 case AArch64::SADDWv8i16_v4i32:
12830 case AArch64::SADDWv16i8_v8i16:
12831 case AArch64::SBCSWr:
12832 case AArch64::SBCSXr:
12833 case AArch64::SBCWr:
12834 case AArch64::SBCXr:
12835 case AArch64::SDIVWr:
12836 case AArch64::SDIVXr:
12837 case AArch64::SHADDv2i32:
12838 case AArch64::SHADDv4i16:
12839 case AArch64::SHADDv4i32:
12840 case AArch64::SHADDv8i8:
12841 case AArch64::SHADDv8i16:
12842 case AArch64::SHADDv16i8:
12843 case AArch64::SHSUBv2i32:
12844 case AArch64::SHSUBv4i16:
12845 case AArch64::SHSUBv4i32:
12846 case AArch64::SHSUBv8i8:
12847 case AArch64::SHSUBv8i16:
12848 case AArch64::SHSUBv16i8:
12849 case AArch64::SMAXPv2i32:
12850 case AArch64::SMAXPv4i16:
12851 case AArch64::SMAXPv4i32:
12852 case AArch64::SMAXPv8i8:
12853 case AArch64::SMAXPv8i16:
12854 case AArch64::SMAXPv16i8:
12855 case AArch64::SMAXWrr:
12856 case AArch64::SMAXXrr:
12857 case AArch64::SMAXv2i32:
12858 case AArch64::SMAXv4i16:
12859 case AArch64::SMAXv4i32:
12860 case AArch64::SMAXv8i8:
12861 case AArch64::SMAXv8i16:
12862 case AArch64::SMAXv16i8:
12863 case AArch64::SMINPv2i32:
12864 case AArch64::SMINPv4i16:
12865 case AArch64::SMINPv4i32:
12866 case AArch64::SMINPv8i8:
12867 case AArch64::SMINPv8i16:
12868 case AArch64::SMINPv16i8:
12869 case AArch64::SMINWrr:
12870 case AArch64::SMINXrr:
12871 case AArch64::SMINv2i32:
12872 case AArch64::SMINv4i16:
12873 case AArch64::SMINv4i32:
12874 case AArch64::SMINv8i8:
12875 case AArch64::SMINv8i16:
12876 case AArch64::SMINv16i8:
12877 case AArch64::SMULLv2i32_v2i64:
12878 case AArch64::SMULLv4i16_v4i32:
12879 case AArch64::SMULLv4i32_v2i64:
12880 case AArch64::SMULLv8i8_v8i16:
12881 case AArch64::SMULLv8i16_v4i32:
12882 case AArch64::SMULLv16i8_v8i16:
12883 case AArch64::SQADDv1i8:
12884 case AArch64::SQADDv1i16:
12885 case AArch64::SQADDv1i32:
12886 case AArch64::SQADDv1i64:
12887 case AArch64::SQADDv2i32:
12888 case AArch64::SQADDv2i64:
12889 case AArch64::SQADDv4i16:
12890 case AArch64::SQADDv4i32:
12891 case AArch64::SQADDv8i8:
12892 case AArch64::SQADDv8i16:
12893 case AArch64::SQADDv16i8:
12894 case AArch64::SQDMULHv1i16:
12895 case AArch64::SQDMULHv1i32:
12896 case AArch64::SQDMULHv2i32:
12897 case AArch64::SQDMULHv4i16:
12898 case AArch64::SQDMULHv4i32:
12899 case AArch64::SQDMULHv8i16:
12900 case AArch64::SQDMULLi16:
12901 case AArch64::SQDMULLi32:
12902 case AArch64::SQDMULLv2i32_v2i64:
12903 case AArch64::SQDMULLv4i16_v4i32:
12904 case AArch64::SQDMULLv4i32_v2i64:
12905 case AArch64::SQDMULLv8i16_v4i32:
12906 case AArch64::SQRDMULHv1i16:
12907 case AArch64::SQRDMULHv1i32:
12908 case AArch64::SQRDMULHv2i32:
12909 case AArch64::SQRDMULHv4i16:
12910 case AArch64::SQRDMULHv4i32:
12911 case AArch64::SQRDMULHv8i16:
12912 case AArch64::SQRSHLv1i8:
12913 case AArch64::SQRSHLv1i16:
12914 case AArch64::SQRSHLv1i32:
12915 case AArch64::SQRSHLv1i64:
12916 case AArch64::SQRSHLv2i32:
12917 case AArch64::SQRSHLv2i64:
12918 case AArch64::SQRSHLv4i16:
12919 case AArch64::SQRSHLv4i32:
12920 case AArch64::SQRSHLv8i8:
12921 case AArch64::SQRSHLv8i16:
12922 case AArch64::SQRSHLv16i8:
12923 case AArch64::SQSHLv1i8:
12924 case AArch64::SQSHLv1i16:
12925 case AArch64::SQSHLv1i32:
12926 case AArch64::SQSHLv1i64:
12927 case AArch64::SQSHLv2i32:
12928 case AArch64::SQSHLv2i64:
12929 case AArch64::SQSHLv4i16:
12930 case AArch64::SQSHLv4i32:
12931 case AArch64::SQSHLv8i8:
12932 case AArch64::SQSHLv8i16:
12933 case AArch64::SQSHLv16i8:
12934 case AArch64::SQSUBv1i8:
12935 case AArch64::SQSUBv1i16:
12936 case AArch64::SQSUBv1i32:
12937 case AArch64::SQSUBv1i64:
12938 case AArch64::SQSUBv2i32:
12939 case AArch64::SQSUBv2i64:
12940 case AArch64::SQSUBv4i16:
12941 case AArch64::SQSUBv4i32:
12942 case AArch64::SQSUBv8i8:
12943 case AArch64::SQSUBv8i16:
12944 case AArch64::SQSUBv16i8:
12945 case AArch64::SRHADDv2i32:
12946 case AArch64::SRHADDv4i16:
12947 case AArch64::SRHADDv4i32:
12948 case AArch64::SRHADDv8i8:
12949 case AArch64::SRHADDv8i16:
12950 case AArch64::SRHADDv16i8:
12951 case AArch64::SRSHLv1i64:
12952 case AArch64::SRSHLv2i32:
12953 case AArch64::SRSHLv2i64:
12954 case AArch64::SRSHLv4i16:
12955 case AArch64::SRSHLv4i32:
12956 case AArch64::SRSHLv8i8:
12957 case AArch64::SRSHLv8i16:
12958 case AArch64::SRSHLv16i8:
12959 case AArch64::SSHLv1i64:
12960 case AArch64::SSHLv2i32:
12961 case AArch64::SSHLv2i64:
12962 case AArch64::SSHLv4i16:
12963 case AArch64::SSHLv4i32:
12964 case AArch64::SSHLv8i8:
12965 case AArch64::SSHLv8i16:
12966 case AArch64::SSHLv16i8:
12967 case AArch64::SSUBLv2i32_v2i64:
12968 case AArch64::SSUBLv4i16_v4i32:
12969 case AArch64::SSUBLv4i32_v2i64:
12970 case AArch64::SSUBLv8i8_v8i16:
12971 case AArch64::SSUBLv8i16_v4i32:
12972 case AArch64::SSUBLv16i8_v8i16:
12973 case AArch64::SSUBWv2i32_v2i64:
12974 case AArch64::SSUBWv4i16_v4i32:
12975 case AArch64::SSUBWv4i32_v2i64:
12976 case AArch64::SSUBWv8i8_v8i16:
12977 case AArch64::SSUBWv8i16_v4i32:
12978 case AArch64::SSUBWv16i8_v8i16:
12979 case AArch64::SUBHNv2i64_v2i32:
12980 case AArch64::SUBHNv4i32_v4i16:
12981 case AArch64::SUBHNv8i16_v8i8:
12982 case AArch64::SUBP:
12983 case AArch64::SUBPS:
12984 case AArch64::SUBv1i64:
12985 case AArch64::SUBv2i32:
12986 case AArch64::SUBv2i64:
12987 case AArch64::SUBv4i16:
12988 case AArch64::SUBv4i32:
12989 case AArch64::SUBv8i8:
12990 case AArch64::SUBv8i16:
12991 case AArch64::SUBv16i8:
12992 case AArch64::TRN1v2i32:
12993 case AArch64::TRN1v2i64:
12994 case AArch64::TRN1v4i16:
12995 case AArch64::TRN1v4i32:
12996 case AArch64::TRN1v8i8:
12997 case AArch64::TRN1v8i16:
12998 case AArch64::TRN1v16i8:
12999 case AArch64::TRN2v2i32:
13000 case AArch64::TRN2v2i64:
13001 case AArch64::TRN2v4i16:
13002 case AArch64::TRN2v4i32:
13003 case AArch64::TRN2v8i8:
13004 case AArch64::TRN2v8i16:
13005 case AArch64::TRN2v16i8:
13006 case AArch64::UABDLv2i32_v2i64:
13007 case AArch64::UABDLv4i16_v4i32:
13008 case AArch64::UABDLv4i32_v2i64:
13009 case AArch64::UABDLv8i8_v8i16:
13010 case AArch64::UABDLv8i16_v4i32:
13011 case AArch64::UABDLv16i8_v8i16:
13012 case AArch64::UABDv2i32:
13013 case AArch64::UABDv4i16:
13014 case AArch64::UABDv4i32:
13015 case AArch64::UABDv8i8:
13016 case AArch64::UABDv8i16:
13017 case AArch64::UABDv16i8:
13018 case AArch64::UADDLv2i32_v2i64:
13019 case AArch64::UADDLv4i16_v4i32:
13020 case AArch64::UADDLv4i32_v2i64:
13021 case AArch64::UADDLv8i8_v8i16:
13022 case AArch64::UADDLv8i16_v4i32:
13023 case AArch64::UADDLv16i8_v8i16:
13024 case AArch64::UADDWv2i32_v2i64:
13025 case AArch64::UADDWv4i16_v4i32:
13026 case AArch64::UADDWv4i32_v2i64:
13027 case AArch64::UADDWv8i8_v8i16:
13028 case AArch64::UADDWv8i16_v4i32:
13029 case AArch64::UADDWv16i8_v8i16:
13030 case AArch64::UDIVWr:
13031 case AArch64::UDIVXr:
13032 case AArch64::UHADDv2i32:
13033 case AArch64::UHADDv4i16:
13034 case AArch64::UHADDv4i32:
13035 case AArch64::UHADDv8i8:
13036 case AArch64::UHADDv8i16:
13037 case AArch64::UHADDv16i8:
13038 case AArch64::UHSUBv2i32:
13039 case AArch64::UHSUBv4i16:
13040 case AArch64::UHSUBv4i32:
13041 case AArch64::UHSUBv8i8:
13042 case AArch64::UHSUBv8i16:
13043 case AArch64::UHSUBv16i8:
13044 case AArch64::UMAXPv2i32:
13045 case AArch64::UMAXPv4i16:
13046 case AArch64::UMAXPv4i32:
13047 case AArch64::UMAXPv8i8:
13048 case AArch64::UMAXPv8i16:
13049 case AArch64::UMAXPv16i8:
13050 case AArch64::UMAXWrr:
13051 case AArch64::UMAXXrr:
13052 case AArch64::UMAXv2i32:
13053 case AArch64::UMAXv4i16:
13054 case AArch64::UMAXv4i32:
13055 case AArch64::UMAXv8i8:
13056 case AArch64::UMAXv8i16:
13057 case AArch64::UMAXv16i8:
13058 case AArch64::UMINPv2i32:
13059 case AArch64::UMINPv4i16:
13060 case AArch64::UMINPv4i32:
13061 case AArch64::UMINPv8i8:
13062 case AArch64::UMINPv8i16:
13063 case AArch64::UMINPv16i8:
13064 case AArch64::UMINWrr:
13065 case AArch64::UMINXrr:
13066 case AArch64::UMINv2i32:
13067 case AArch64::UMINv4i16:
13068 case AArch64::UMINv4i32:
13069 case AArch64::UMINv8i8:
13070 case AArch64::UMINv8i16:
13071 case AArch64::UMINv16i8:
13072 case AArch64::UMULLv2i32_v2i64:
13073 case AArch64::UMULLv4i16_v4i32:
13074 case AArch64::UMULLv4i32_v2i64:
13075 case AArch64::UMULLv8i8_v8i16:
13076 case AArch64::UMULLv8i16_v4i32:
13077 case AArch64::UMULLv16i8_v8i16:
13078 case AArch64::UQADDv1i8:
13079 case AArch64::UQADDv1i16:
13080 case AArch64::UQADDv1i32:
13081 case AArch64::UQADDv1i64:
13082 case AArch64::UQADDv2i32:
13083 case AArch64::UQADDv2i64:
13084 case AArch64::UQADDv4i16:
13085 case AArch64::UQADDv4i32:
13086 case AArch64::UQADDv8i8:
13087 case AArch64::UQADDv8i16:
13088 case AArch64::UQADDv16i8:
13089 case AArch64::UQRSHLv1i8:
13090 case AArch64::UQRSHLv1i16:
13091 case AArch64::UQRSHLv1i32:
13092 case AArch64::UQRSHLv1i64:
13093 case AArch64::UQRSHLv2i32:
13094 case AArch64::UQRSHLv2i64:
13095 case AArch64::UQRSHLv4i16:
13096 case AArch64::UQRSHLv4i32:
13097 case AArch64::UQRSHLv8i8:
13098 case AArch64::UQRSHLv8i16:
13099 case AArch64::UQRSHLv16i8:
13100 case AArch64::UQSHLv1i8:
13101 case AArch64::UQSHLv1i16:
13102 case AArch64::UQSHLv1i32:
13103 case AArch64::UQSHLv1i64:
13104 case AArch64::UQSHLv2i32:
13105 case AArch64::UQSHLv2i64:
13106 case AArch64::UQSHLv4i16:
13107 case AArch64::UQSHLv4i32:
13108 case AArch64::UQSHLv8i8:
13109 case AArch64::UQSHLv8i16:
13110 case AArch64::UQSHLv16i8:
13111 case AArch64::UQSUBv1i8:
13112 case AArch64::UQSUBv1i16:
13113 case AArch64::UQSUBv1i32:
13114 case AArch64::UQSUBv1i64:
13115 case AArch64::UQSUBv2i32:
13116 case AArch64::UQSUBv2i64:
13117 case AArch64::UQSUBv4i16:
13118 case AArch64::UQSUBv4i32:
13119 case AArch64::UQSUBv8i8:
13120 case AArch64::UQSUBv8i16:
13121 case AArch64::UQSUBv16i8:
13122 case AArch64::URHADDv2i32:
13123 case AArch64::URHADDv4i16:
13124 case AArch64::URHADDv4i32:
13125 case AArch64::URHADDv8i8:
13126 case AArch64::URHADDv8i16:
13127 case AArch64::URHADDv16i8:
13128 case AArch64::URSHLv1i64:
13129 case AArch64::URSHLv2i32:
13130 case AArch64::URSHLv2i64:
13131 case AArch64::URSHLv4i16:
13132 case AArch64::URSHLv4i32:
13133 case AArch64::URSHLv8i8:
13134 case AArch64::URSHLv8i16:
13135 case AArch64::URSHLv16i8:
13136 case AArch64::USHLv1i64:
13137 case AArch64::USHLv2i32:
13138 case AArch64::USHLv2i64:
13139 case AArch64::USHLv4i16:
13140 case AArch64::USHLv4i32:
13141 case AArch64::USHLv8i8:
13142 case AArch64::USHLv8i16:
13143 case AArch64::USHLv16i8:
13144 case AArch64::USUBLv2i32_v2i64:
13145 case AArch64::USUBLv4i16_v4i32:
13146 case AArch64::USUBLv4i32_v2i64:
13147 case AArch64::USUBLv8i8_v8i16:
13148 case AArch64::USUBLv8i16_v4i32:
13149 case AArch64::USUBLv16i8_v8i16:
13150 case AArch64::USUBWv2i32_v2i64:
13151 case AArch64::USUBWv4i16_v4i32:
13152 case AArch64::USUBWv4i32_v2i64:
13153 case AArch64::USUBWv8i8_v8i16:
13154 case AArch64::USUBWv8i16_v4i32:
13155 case AArch64::USUBWv16i8_v8i16:
13156 case AArch64::UZP1v2i32:
13157 case AArch64::UZP1v2i64:
13158 case AArch64::UZP1v4i16:
13159 case AArch64::UZP1v4i32:
13160 case AArch64::UZP1v8i8:
13161 case AArch64::UZP1v8i16:
13162 case AArch64::UZP1v16i8:
13163 case AArch64::UZP2v2i32:
13164 case AArch64::UZP2v2i64:
13165 case AArch64::UZP2v4i16:
13166 case AArch64::UZP2v4i32:
13167 case AArch64::UZP2v8i8:
13168 case AArch64::UZP2v8i16:
13169 case AArch64::UZP2v16i8:
13170 case AArch64::ZIP1v2i32:
13171 case AArch64::ZIP1v2i64:
13172 case AArch64::ZIP1v4i16:
13173 case AArch64::ZIP1v4i32:
13174 case AArch64::ZIP1v8i8:
13175 case AArch64::ZIP1v8i16:
13176 case AArch64::ZIP1v16i8:
13177 case AArch64::ZIP2v2i32:
13178 case AArch64::ZIP2v2i64:
13179 case AArch64::ZIP2v4i16:
13180 case AArch64::ZIP2v4i32:
13181 case AArch64::ZIP2v8i8:
13182 case AArch64::ZIP2v8i16:
13183 case AArch64::ZIP2v16i8: {
13184 // op: Rd
13185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13186 op &= UINT64_C(31);
13187 Value |= op;
13188 // op: Rn
13189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13190 op &= UINT64_C(31);
13191 op <<= 5;
13192 Value |= op;
13193 // op: Rm
13194 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13195 op &= UINT64_C(31);
13196 op <<= 16;
13197 Value |= op;
13198 break;
13199 }
13200 case AArch64::FMADDDrrr:
13201 case AArch64::FMADDHrrr:
13202 case AArch64::FMADDSrrr:
13203 case AArch64::FMSUBDrrr:
13204 case AArch64::FMSUBHrrr:
13205 case AArch64::FMSUBSrrr:
13206 case AArch64::FNMADDDrrr:
13207 case AArch64::FNMADDHrrr:
13208 case AArch64::FNMADDSrrr:
13209 case AArch64::FNMSUBDrrr:
13210 case AArch64::FNMSUBHrrr:
13211 case AArch64::FNMSUBSrrr:
13212 case AArch64::MADDPT:
13213 case AArch64::MADDWrrr:
13214 case AArch64::MADDXrrr:
13215 case AArch64::MSUBPT:
13216 case AArch64::MSUBWrrr:
13217 case AArch64::MSUBXrrr:
13218 case AArch64::SMADDLrrr:
13219 case AArch64::SMSUBLrrr:
13220 case AArch64::UMADDLrrr:
13221 case AArch64::UMSUBLrrr: {
13222 // op: Rd
13223 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13224 op &= UINT64_C(31);
13225 Value |= op;
13226 // op: Rn
13227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13228 op &= UINT64_C(31);
13229 op <<= 5;
13230 Value |= op;
13231 // op: Rm
13232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13233 op &= UINT64_C(31);
13234 op <<= 16;
13235 Value |= op;
13236 // op: Ra
13237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13238 op &= UINT64_C(31);
13239 op <<= 10;
13240 Value |= op;
13241 break;
13242 }
13243 case AArch64::CSELWr:
13244 case AArch64::CSELXr:
13245 case AArch64::CSINCWr:
13246 case AArch64::CSINCXr:
13247 case AArch64::CSINVWr:
13248 case AArch64::CSINVXr:
13249 case AArch64::CSNEGWr:
13250 case AArch64::CSNEGXr:
13251 case AArch64::FCSELDrrr:
13252 case AArch64::FCSELHrrr:
13253 case AArch64::FCSELSrrr: {
13254 // op: Rd
13255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13256 op &= UINT64_C(31);
13257 Value |= op;
13258 // op: Rn
13259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13260 op &= UINT64_C(31);
13261 op <<= 5;
13262 Value |= op;
13263 // op: Rm
13264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13265 op &= UINT64_C(31);
13266 op <<= 16;
13267 Value |= op;
13268 // op: cond
13269 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13270 op &= UINT64_C(15);
13271 op <<= 12;
13272 Value |= op;
13273 break;
13274 }
13275 case AArch64::ADDSXrx64:
13276 case AArch64::ADDXrx64:
13277 case AArch64::SUBSXrx64:
13278 case AArch64::SUBXrx64: {
13279 // op: Rd
13280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13281 op &= UINT64_C(31);
13282 Value |= op;
13283 // op: Rn
13284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13285 op &= UINT64_C(31);
13286 op <<= 5;
13287 Value |= op;
13288 // op: Rm
13289 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13290 op &= UINT64_C(31);
13291 op <<= 16;
13292 Value |= op;
13293 // op: ext
13294 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13295 Value |= (op & UINT64_C(32)) << 10;
13296 Value |= (op & UINT64_C(7)) << 10;
13297 break;
13298 }
13299 case AArch64::ADDSWrx:
13300 case AArch64::ADDSXrx:
13301 case AArch64::ADDWrx:
13302 case AArch64::ADDXrx:
13303 case AArch64::SUBSWrx:
13304 case AArch64::SUBSXrx:
13305 case AArch64::SUBWrx:
13306 case AArch64::SUBXrx: {
13307 // op: Rd
13308 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13309 op &= UINT64_C(31);
13310 Value |= op;
13311 // op: Rn
13312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13313 op &= UINT64_C(31);
13314 op <<= 5;
13315 Value |= op;
13316 // op: Rm
13317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13318 op &= UINT64_C(31);
13319 op <<= 16;
13320 Value |= op;
13321 // op: extend
13322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13323 op &= UINT64_C(63);
13324 op <<= 10;
13325 Value |= op;
13326 break;
13327 }
13328 case AArch64::FMULXv1i32_indexed:
13329 case AArch64::FMULXv2i32_indexed:
13330 case AArch64::FMULXv4i32_indexed:
13331 case AArch64::FMULv1i32_indexed:
13332 case AArch64::FMULv2i32_indexed:
13333 case AArch64::FMULv4i32_indexed:
13334 case AArch64::MULv2i32_indexed:
13335 case AArch64::MULv4i32_indexed:
13336 case AArch64::SMULLv2i32_indexed:
13337 case AArch64::SMULLv4i32_indexed:
13338 case AArch64::SQDMULHv1i32_indexed:
13339 case AArch64::SQDMULHv2i32_indexed:
13340 case AArch64::SQDMULHv4i32_indexed:
13341 case AArch64::SQDMULLv1i64_indexed:
13342 case AArch64::SQDMULLv2i32_indexed:
13343 case AArch64::SQDMULLv4i32_indexed:
13344 case AArch64::SQRDMULHv1i32_indexed:
13345 case AArch64::SQRDMULHv2i32_indexed:
13346 case AArch64::SQRDMULHv4i32_indexed:
13347 case AArch64::UMULLv2i32_indexed:
13348 case AArch64::UMULLv4i32_indexed: {
13349 // op: Rd
13350 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13351 op &= UINT64_C(31);
13352 Value |= op;
13353 // op: Rn
13354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13355 op &= UINT64_C(31);
13356 op <<= 5;
13357 Value |= op;
13358 // op: Rm
13359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13360 op &= UINT64_C(31);
13361 op <<= 16;
13362 Value |= op;
13363 // op: idx
13364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13365 Value |= (op & UINT64_C(1)) << 21;
13366 Value |= (op & UINT64_C(2)) << 10;
13367 break;
13368 }
13369 case AArch64::FMULXv1i64_indexed:
13370 case AArch64::FMULXv2i64_indexed:
13371 case AArch64::FMULv1i64_indexed:
13372 case AArch64::FMULv2i64_indexed: {
13373 // op: Rd
13374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13375 op &= UINT64_C(31);
13376 Value |= op;
13377 // op: Rn
13378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13379 op &= UINT64_C(31);
13380 op <<= 5;
13381 Value |= op;
13382 // op: Rm
13383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13384 op &= UINT64_C(31);
13385 op <<= 16;
13386 Value |= op;
13387 // op: idx
13388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13389 op &= UINT64_C(1);
13390 op <<= 11;
13391 Value |= op;
13392 break;
13393 }
13394 case AArch64::LUT4_B: {
13395 // op: Rd
13396 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13397 op &= UINT64_C(31);
13398 Value |= op;
13399 // op: Rn
13400 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13401 op &= UINT64_C(31);
13402 op <<= 5;
13403 Value |= op;
13404 // op: Rm
13405 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13406 op &= UINT64_C(31);
13407 op <<= 16;
13408 Value |= op;
13409 // op: idx
13410 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13411 op &= UINT64_C(1);
13412 op <<= 14;
13413 Value |= op;
13414 break;
13415 }
13416 case AArch64::LUT2_B:
13417 case AArch64::LUT4_H: {
13418 // op: Rd
13419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13420 op &= UINT64_C(31);
13421 Value |= op;
13422 // op: Rn
13423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13424 op &= UINT64_C(31);
13425 op <<= 5;
13426 Value |= op;
13427 // op: Rm
13428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13429 op &= UINT64_C(31);
13430 op <<= 16;
13431 Value |= op;
13432 // op: idx
13433 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13434 op &= UINT64_C(3);
13435 op <<= 13;
13436 Value |= op;
13437 break;
13438 }
13439 case AArch64::LUT2_H: {
13440 // op: Rd
13441 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13442 op &= UINT64_C(31);
13443 Value |= op;
13444 // op: Rn
13445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13446 op &= UINT64_C(31);
13447 op <<= 5;
13448 Value |= op;
13449 // op: Rm
13450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13451 op &= UINT64_C(31);
13452 op <<= 16;
13453 Value |= op;
13454 // op: idx
13455 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13456 op &= UINT64_C(7);
13457 op <<= 12;
13458 Value |= op;
13459 break;
13460 }
13461 case AArch64::EXTv16i8: {
13462 // op: Rd
13463 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13464 op &= UINT64_C(31);
13465 Value |= op;
13466 // op: Rn
13467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13468 op &= UINT64_C(31);
13469 op <<= 5;
13470 Value |= op;
13471 // op: Rm
13472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13473 op &= UINT64_C(31);
13474 op <<= 16;
13475 Value |= op;
13476 // op: imm
13477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13478 op &= UINT64_C(15);
13479 op <<= 11;
13480 Value |= op;
13481 break;
13482 }
13483 case AArch64::EXTRWrri: {
13484 // op: Rd
13485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13486 op &= UINT64_C(31);
13487 Value |= op;
13488 // op: Rn
13489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13490 op &= UINT64_C(31);
13491 op <<= 5;
13492 Value |= op;
13493 // op: Rm
13494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13495 op &= UINT64_C(31);
13496 op <<= 16;
13497 Value |= op;
13498 // op: imm
13499 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13500 op &= UINT64_C(31);
13501 op <<= 10;
13502 Value |= op;
13503 break;
13504 }
13505 case AArch64::EXTRXrri: {
13506 // op: Rd
13507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13508 op &= UINT64_C(31);
13509 Value |= op;
13510 // op: Rn
13511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13512 op &= UINT64_C(31);
13513 op <<= 5;
13514 Value |= op;
13515 // op: Rm
13516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13517 op &= UINT64_C(31);
13518 op <<= 16;
13519 Value |= op;
13520 // op: imm
13521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13522 op &= UINT64_C(63);
13523 op <<= 10;
13524 Value |= op;
13525 break;
13526 }
13527 case AArch64::EXTv8i8: {
13528 // op: Rd
13529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13530 op &= UINT64_C(31);
13531 Value |= op;
13532 // op: Rn
13533 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13534 op &= UINT64_C(31);
13535 op <<= 5;
13536 Value |= op;
13537 // op: Rm
13538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13539 op &= UINT64_C(31);
13540 op <<= 16;
13541 Value |= op;
13542 // op: imm
13543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13544 op &= UINT64_C(7);
13545 op <<= 11;
13546 Value |= op;
13547 break;
13548 }
13549 case AArch64::FCADDv2f32:
13550 case AArch64::FCADDv2f64:
13551 case AArch64::FCADDv4f16:
13552 case AArch64::FCADDv4f32:
13553 case AArch64::FCADDv8f16: {
13554 // op: Rd
13555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13556 op &= UINT64_C(31);
13557 Value |= op;
13558 // op: Rn
13559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13560 op &= UINT64_C(31);
13561 op <<= 5;
13562 Value |= op;
13563 // op: Rm
13564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13565 op &= UINT64_C(31);
13566 op <<= 16;
13567 Value |= op;
13568 // op: rot
13569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13570 op &= UINT64_C(1);
13571 op <<= 12;
13572 Value |= op;
13573 break;
13574 }
13575 case AArch64::ADDSWrs:
13576 case AArch64::ADDSXrs:
13577 case AArch64::ADDWrs:
13578 case AArch64::ADDXrs:
13579 case AArch64::ANDSWrs:
13580 case AArch64::ANDSXrs:
13581 case AArch64::ANDWrs:
13582 case AArch64::ANDXrs:
13583 case AArch64::BICSWrs:
13584 case AArch64::BICSXrs:
13585 case AArch64::BICWrs:
13586 case AArch64::BICXrs:
13587 case AArch64::EONWrs:
13588 case AArch64::EONXrs:
13589 case AArch64::EORWrs:
13590 case AArch64::EORXrs:
13591 case AArch64::ORNWrs:
13592 case AArch64::ORNXrs:
13593 case AArch64::ORRWrs:
13594 case AArch64::ORRXrs:
13595 case AArch64::SUBSWrs:
13596 case AArch64::SUBSXrs:
13597 case AArch64::SUBWrs:
13598 case AArch64::SUBXrs: {
13599 // op: Rd
13600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13601 op &= UINT64_C(31);
13602 Value |= op;
13603 // op: Rn
13604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13605 op &= UINT64_C(31);
13606 op <<= 5;
13607 Value |= op;
13608 // op: Rm
13609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13610 op &= UINT64_C(31);
13611 op <<= 16;
13612 Value |= op;
13613 // op: shift
13614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13615 Value |= (op & UINT64_C(192)) << 16;
13616 Value |= (op & UINT64_C(63)) << 10;
13617 break;
13618 }
13619 case AArch64::ADDPT_shift:
13620 case AArch64::SUBPT_shift: {
13621 // op: Rd
13622 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13623 op &= UINT64_C(31);
13624 Value |= op;
13625 // op: Rn
13626 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13627 op &= UINT64_C(31);
13628 op <<= 5;
13629 Value |= op;
13630 // op: Rm
13631 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13632 op &= UINT64_C(31);
13633 op <<= 16;
13634 Value |= op;
13635 // op: shift_imm
13636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13637 op &= UINT64_C(7);
13638 op <<= 10;
13639 Value |= op;
13640 break;
13641 }
13642 case AArch64::SMULHrr:
13643 case AArch64::UMULHrr: {
13644 // op: Rd
13645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13646 op &= UINT64_C(31);
13647 Value |= op;
13648 // op: Rn
13649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13650 op &= UINT64_C(31);
13651 op <<= 5;
13652 Value |= op;
13653 // op: Rm
13654 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13655 op &= UINT64_C(31);
13656 op <<= 16;
13657 Value |= op;
13658 Value = fixMulHigh(MI, EncodedValue: Value, STI);
13659 break;
13660 }
13661 case AArch64::DUPv2i64lane:
13662 case AArch64::UMOVvi64: {
13663 // op: Rd
13664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13665 op &= UINT64_C(31);
13666 Value |= op;
13667 // op: Rn
13668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13669 op &= UINT64_C(31);
13670 op <<= 5;
13671 Value |= op;
13672 // op: idx
13673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13674 op &= UINT64_C(1);
13675 op <<= 20;
13676 Value |= op;
13677 break;
13678 }
13679 case AArch64::DUPv8i8lane:
13680 case AArch64::DUPv16i8lane:
13681 case AArch64::SMOVvi8to32:
13682 case AArch64::SMOVvi8to64:
13683 case AArch64::UMOVvi8: {
13684 // op: Rd
13685 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13686 op &= UINT64_C(31);
13687 Value |= op;
13688 // op: Rn
13689 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13690 op &= UINT64_C(31);
13691 op <<= 5;
13692 Value |= op;
13693 // op: idx
13694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13695 op &= UINT64_C(15);
13696 op <<= 17;
13697 Value |= op;
13698 break;
13699 }
13700 case AArch64::DUPv2i32lane:
13701 case AArch64::DUPv4i32lane:
13702 case AArch64::SMOVvi32to64:
13703 case AArch64::UMOVvi32: {
13704 // op: Rd
13705 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13706 op &= UINT64_C(31);
13707 Value |= op;
13708 // op: Rn
13709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13710 op &= UINT64_C(31);
13711 op <<= 5;
13712 Value |= op;
13713 // op: idx
13714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13715 op &= UINT64_C(3);
13716 op <<= 19;
13717 Value |= op;
13718 break;
13719 }
13720 case AArch64::DUPv4i16lane:
13721 case AArch64::DUPv8i16lane:
13722 case AArch64::SMOVvi16to32:
13723 case AArch64::SMOVvi16to64:
13724 case AArch64::UMOVvi16: {
13725 // op: Rd
13726 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13727 op &= UINT64_C(31);
13728 Value |= op;
13729 // op: Rn
13730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13731 op &= UINT64_C(31);
13732 op <<= 5;
13733 Value |= op;
13734 // op: idx
13735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13736 op &= UINT64_C(7);
13737 op <<= 18;
13738 Value |= op;
13739 break;
13740 }
13741 case AArch64::ADDSWri:
13742 case AArch64::ADDSXri:
13743 case AArch64::ADDWri:
13744 case AArch64::ADDXri:
13745 case AArch64::SUBSWri:
13746 case AArch64::SUBSXri:
13747 case AArch64::SUBWri:
13748 case AArch64::SUBXri: {
13749 // op: Rd
13750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13751 op &= UINT64_C(31);
13752 Value |= op;
13753 // op: Rn
13754 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13755 op &= UINT64_C(31);
13756 op <<= 5;
13757 Value |= op;
13758 // op: imm
13759 op = getAddSubImmOpValue(MI, OpIdx: 2, Fixups, STI);
13760 op &= UINT64_C(16383);
13761 op <<= 10;
13762 Value |= op;
13763 break;
13764 }
13765 case AArch64::SMAXWri:
13766 case AArch64::SMAXXri:
13767 case AArch64::SMINWri:
13768 case AArch64::SMINXri:
13769 case AArch64::UMAXWri:
13770 case AArch64::UMAXXri:
13771 case AArch64::UMINWri:
13772 case AArch64::UMINXri: {
13773 // op: Rd
13774 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13775 op &= UINT64_C(31);
13776 Value |= op;
13777 // op: Rn
13778 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13779 op &= UINT64_C(31);
13780 op <<= 5;
13781 Value |= op;
13782 // op: imm
13783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13784 op &= UINT64_C(255);
13785 op <<= 10;
13786 Value |= op;
13787 break;
13788 }
13789 case AArch64::ANDSWri:
13790 case AArch64::ANDWri:
13791 case AArch64::EORWri:
13792 case AArch64::ORRWri: {
13793 // op: Rd
13794 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13795 op &= UINT64_C(31);
13796 Value |= op;
13797 // op: Rn
13798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13799 op &= UINT64_C(31);
13800 op <<= 5;
13801 Value |= op;
13802 // op: imm
13803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13804 op &= UINT64_C(4095);
13805 op <<= 10;
13806 Value |= op;
13807 break;
13808 }
13809 case AArch64::ANDSXri:
13810 case AArch64::ANDXri:
13811 case AArch64::EORXri:
13812 case AArch64::ORRXri: {
13813 // op: Rd
13814 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13815 op &= UINT64_C(31);
13816 Value |= op;
13817 // op: Rn
13818 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13819 op &= UINT64_C(31);
13820 op <<= 5;
13821 Value |= op;
13822 // op: imm
13823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13824 op &= UINT64_C(8191);
13825 op <<= 10;
13826 Value |= op;
13827 break;
13828 }
13829 case AArch64::SHLv4i16_shift:
13830 case AArch64::SHLv8i16_shift:
13831 case AArch64::SQSHLUh:
13832 case AArch64::SQSHLUv4i16_shift:
13833 case AArch64::SQSHLUv8i16_shift:
13834 case AArch64::SQSHLh:
13835 case AArch64::SQSHLv4i16_shift:
13836 case AArch64::SQSHLv8i16_shift:
13837 case AArch64::SSHLLv4i16_shift:
13838 case AArch64::SSHLLv8i16_shift:
13839 case AArch64::UQSHLh:
13840 case AArch64::UQSHLv4i16_shift:
13841 case AArch64::UQSHLv8i16_shift:
13842 case AArch64::USHLLv4i16_shift:
13843 case AArch64::USHLLv8i16_shift: {
13844 // op: Rd
13845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13846 op &= UINT64_C(31);
13847 Value |= op;
13848 // op: Rn
13849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13850 op &= UINT64_C(31);
13851 op <<= 5;
13852 Value |= op;
13853 // op: imm
13854 op = getVecShiftL16OpValue(MI, OpIdx: 2, Fixups, STI);
13855 op &= UINT64_C(15);
13856 op <<= 16;
13857 Value |= op;
13858 break;
13859 }
13860 case AArch64::SHLv2i32_shift:
13861 case AArch64::SHLv4i32_shift:
13862 case AArch64::SQSHLUs:
13863 case AArch64::SQSHLUv2i32_shift:
13864 case AArch64::SQSHLUv4i32_shift:
13865 case AArch64::SQSHLs:
13866 case AArch64::SQSHLv2i32_shift:
13867 case AArch64::SQSHLv4i32_shift:
13868 case AArch64::SSHLLv2i32_shift:
13869 case AArch64::SSHLLv4i32_shift:
13870 case AArch64::UQSHLs:
13871 case AArch64::UQSHLv2i32_shift:
13872 case AArch64::UQSHLv4i32_shift:
13873 case AArch64::USHLLv2i32_shift:
13874 case AArch64::USHLLv4i32_shift: {
13875 // op: Rd
13876 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13877 op &= UINT64_C(31);
13878 Value |= op;
13879 // op: Rn
13880 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13881 op &= UINT64_C(31);
13882 op <<= 5;
13883 Value |= op;
13884 // op: imm
13885 op = getVecShiftL32OpValue(MI, OpIdx: 2, Fixups, STI);
13886 op &= UINT64_C(31);
13887 op <<= 16;
13888 Value |= op;
13889 break;
13890 }
13891 case AArch64::SHLd:
13892 case AArch64::SHLv2i64_shift:
13893 case AArch64::SQSHLUd:
13894 case AArch64::SQSHLUv2i64_shift:
13895 case AArch64::SQSHLd:
13896 case AArch64::SQSHLv2i64_shift:
13897 case AArch64::UQSHLd:
13898 case AArch64::UQSHLv2i64_shift: {
13899 // op: Rd
13900 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13901 op &= UINT64_C(31);
13902 Value |= op;
13903 // op: Rn
13904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13905 op &= UINT64_C(31);
13906 op <<= 5;
13907 Value |= op;
13908 // op: imm
13909 op = getVecShiftL64OpValue(MI, OpIdx: 2, Fixups, STI);
13910 op &= UINT64_C(63);
13911 op <<= 16;
13912 Value |= op;
13913 break;
13914 }
13915 case AArch64::SHLv8i8_shift:
13916 case AArch64::SHLv16i8_shift:
13917 case AArch64::SQSHLUb:
13918 case AArch64::SQSHLUv8i8_shift:
13919 case AArch64::SQSHLUv16i8_shift:
13920 case AArch64::SQSHLb:
13921 case AArch64::SQSHLv8i8_shift:
13922 case AArch64::SQSHLv16i8_shift:
13923 case AArch64::SSHLLv8i8_shift:
13924 case AArch64::SSHLLv16i8_shift:
13925 case AArch64::UQSHLb:
13926 case AArch64::UQSHLv8i8_shift:
13927 case AArch64::UQSHLv16i8_shift:
13928 case AArch64::USHLLv8i8_shift:
13929 case AArch64::USHLLv16i8_shift: {
13930 // op: Rd
13931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13932 op &= UINT64_C(31);
13933 Value |= op;
13934 // op: Rn
13935 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13936 op &= UINT64_C(31);
13937 op <<= 5;
13938 Value |= op;
13939 // op: imm
13940 op = getVecShiftL8OpValue(MI, OpIdx: 2, Fixups, STI);
13941 op &= UINT64_C(7);
13942 op <<= 16;
13943 Value |= op;
13944 break;
13945 }
13946 case AArch64::FCVTZSh:
13947 case AArch64::FCVTZSv4i16_shift:
13948 case AArch64::FCVTZSv8i16_shift:
13949 case AArch64::FCVTZUh:
13950 case AArch64::FCVTZUv4i16_shift:
13951 case AArch64::FCVTZUv8i16_shift:
13952 case AArch64::SCVTFh:
13953 case AArch64::SCVTFv4i16_shift:
13954 case AArch64::SCVTFv8i16_shift:
13955 case AArch64::SQRSHRNh:
13956 case AArch64::SQRSHRUNh:
13957 case AArch64::SQSHRNh:
13958 case AArch64::SQSHRUNh:
13959 case AArch64::SRSHRv4i16_shift:
13960 case AArch64::SRSHRv8i16_shift:
13961 case AArch64::SSHRv4i16_shift:
13962 case AArch64::SSHRv8i16_shift:
13963 case AArch64::UCVTFh:
13964 case AArch64::UCVTFv4i16_shift:
13965 case AArch64::UCVTFv8i16_shift:
13966 case AArch64::UQRSHRNh:
13967 case AArch64::UQSHRNh:
13968 case AArch64::URSHRv4i16_shift:
13969 case AArch64::URSHRv8i16_shift:
13970 case AArch64::USHRv4i16_shift:
13971 case AArch64::USHRv8i16_shift: {
13972 // op: Rd
13973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13974 op &= UINT64_C(31);
13975 Value |= op;
13976 // op: Rn
13977 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13978 op &= UINT64_C(31);
13979 op <<= 5;
13980 Value |= op;
13981 // op: imm
13982 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
13983 op &= UINT64_C(15);
13984 op <<= 16;
13985 Value |= op;
13986 break;
13987 }
13988 case AArch64::RSHRNv8i8_shift:
13989 case AArch64::SHRNv8i8_shift:
13990 case AArch64::SQRSHRNv8i8_shift:
13991 case AArch64::SQRSHRUNv8i8_shift:
13992 case AArch64::SQSHRNv8i8_shift:
13993 case AArch64::SQSHRUNv8i8_shift:
13994 case AArch64::UQRSHRNv8i8_shift:
13995 case AArch64::UQSHRNv8i8_shift: {
13996 // op: Rd
13997 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13998 op &= UINT64_C(31);
13999 Value |= op;
14000 // op: Rn
14001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14002 op &= UINT64_C(31);
14003 op <<= 5;
14004 Value |= op;
14005 // op: imm
14006 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
14007 op &= UINT64_C(7);
14008 op <<= 16;
14009 Value |= op;
14010 break;
14011 }
14012 case AArch64::RSHRNv4i16_shift:
14013 case AArch64::SHRNv4i16_shift:
14014 case AArch64::SQRSHRNv4i16_shift:
14015 case AArch64::SQRSHRUNv4i16_shift:
14016 case AArch64::SQSHRNv4i16_shift:
14017 case AArch64::SQSHRUNv4i16_shift:
14018 case AArch64::UQRSHRNv4i16_shift:
14019 case AArch64::UQSHRNv4i16_shift: {
14020 // op: Rd
14021 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14022 op &= UINT64_C(31);
14023 Value |= op;
14024 // op: Rn
14025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14026 op &= UINT64_C(31);
14027 op <<= 5;
14028 Value |= op;
14029 // op: imm
14030 op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI);
14031 op &= UINT64_C(15);
14032 op <<= 16;
14033 Value |= op;
14034 break;
14035 }
14036 case AArch64::FCVTZSs:
14037 case AArch64::FCVTZSv2i32_shift:
14038 case AArch64::FCVTZSv4i32_shift:
14039 case AArch64::FCVTZUs:
14040 case AArch64::FCVTZUv2i32_shift:
14041 case AArch64::FCVTZUv4i32_shift:
14042 case AArch64::SCVTFs:
14043 case AArch64::SCVTFv2i32_shift:
14044 case AArch64::SCVTFv4i32_shift:
14045 case AArch64::SQRSHRNs:
14046 case AArch64::SQRSHRUNs:
14047 case AArch64::SQSHRNs:
14048 case AArch64::SQSHRUNs:
14049 case AArch64::SRSHRv2i32_shift:
14050 case AArch64::SRSHRv4i32_shift:
14051 case AArch64::SSHRv2i32_shift:
14052 case AArch64::SSHRv4i32_shift:
14053 case AArch64::UCVTFs:
14054 case AArch64::UCVTFv2i32_shift:
14055 case AArch64::UCVTFv4i32_shift:
14056 case AArch64::UQRSHRNs:
14057 case AArch64::UQSHRNs:
14058 case AArch64::URSHRv2i32_shift:
14059 case AArch64::URSHRv4i32_shift:
14060 case AArch64::USHRv2i32_shift:
14061 case AArch64::USHRv4i32_shift: {
14062 // op: Rd
14063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14064 op &= UINT64_C(31);
14065 Value |= op;
14066 // op: Rn
14067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14068 op &= UINT64_C(31);
14069 op <<= 5;
14070 Value |= op;
14071 // op: imm
14072 op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI);
14073 op &= UINT64_C(31);
14074 op <<= 16;
14075 Value |= op;
14076 break;
14077 }
14078 case AArch64::RSHRNv2i32_shift:
14079 case AArch64::SHRNv2i32_shift:
14080 case AArch64::SQRSHRNv2i32_shift:
14081 case AArch64::SQRSHRUNv2i32_shift:
14082 case AArch64::SQSHRNv2i32_shift:
14083 case AArch64::SQSHRUNv2i32_shift:
14084 case AArch64::UQRSHRNv2i32_shift:
14085 case AArch64::UQSHRNv2i32_shift: {
14086 // op: Rd
14087 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14088 op &= UINT64_C(31);
14089 Value |= op;
14090 // op: Rn
14091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14092 op &= UINT64_C(31);
14093 op <<= 5;
14094 Value |= op;
14095 // op: imm
14096 op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI);
14097 op &= UINT64_C(31);
14098 op <<= 16;
14099 Value |= op;
14100 break;
14101 }
14102 case AArch64::FCVTZSd:
14103 case AArch64::FCVTZSv2i64_shift:
14104 case AArch64::FCVTZUd:
14105 case AArch64::FCVTZUv2i64_shift:
14106 case AArch64::SCVTFd:
14107 case AArch64::SCVTFv2i64_shift:
14108 case AArch64::SRSHRd:
14109 case AArch64::SRSHRv2i64_shift:
14110 case AArch64::SSHRd:
14111 case AArch64::SSHRv2i64_shift:
14112 case AArch64::UCVTFd:
14113 case AArch64::UCVTFv2i64_shift:
14114 case AArch64::URSHRd:
14115 case AArch64::URSHRv2i64_shift:
14116 case AArch64::USHRd:
14117 case AArch64::USHRv2i64_shift: {
14118 // op: Rd
14119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14120 op &= UINT64_C(31);
14121 Value |= op;
14122 // op: Rn
14123 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14124 op &= UINT64_C(31);
14125 op <<= 5;
14126 Value |= op;
14127 // op: imm
14128 op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI);
14129 op &= UINT64_C(63);
14130 op <<= 16;
14131 Value |= op;
14132 break;
14133 }
14134 case AArch64::SQRSHRNb:
14135 case AArch64::SQRSHRUNb:
14136 case AArch64::SQSHRNb:
14137 case AArch64::SQSHRUNb:
14138 case AArch64::SRSHRv8i8_shift:
14139 case AArch64::SRSHRv16i8_shift:
14140 case AArch64::SSHRv8i8_shift:
14141 case AArch64::SSHRv16i8_shift:
14142 case AArch64::UQRSHRNb:
14143 case AArch64::UQSHRNb:
14144 case AArch64::URSHRv8i8_shift:
14145 case AArch64::URSHRv16i8_shift:
14146 case AArch64::USHRv8i8_shift:
14147 case AArch64::USHRv16i8_shift: {
14148 // op: Rd
14149 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14150 op &= UINT64_C(31);
14151 Value |= op;
14152 // op: Rn
14153 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14154 op &= UINT64_C(31);
14155 op <<= 5;
14156 Value |= op;
14157 // op: imm
14158 op = getVecShiftR8OpValue(MI, OpIdx: 2, Fixups, STI);
14159 op &= UINT64_C(7);
14160 op <<= 16;
14161 Value |= op;
14162 break;
14163 }
14164 case AArch64::ADDG:
14165 case AArch64::SUBG: {
14166 // op: Rd
14167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14168 op &= UINT64_C(31);
14169 Value |= op;
14170 // op: Rn
14171 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14172 op &= UINT64_C(31);
14173 op <<= 5;
14174 Value |= op;
14175 // op: imm6
14176 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14177 op &= UINT64_C(63);
14178 op <<= 16;
14179 Value |= op;
14180 // op: imm4
14181 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14182 op &= UINT64_C(15);
14183 op <<= 10;
14184 Value |= op;
14185 break;
14186 }
14187 case AArch64::SBFMWri:
14188 case AArch64::UBFMWri: {
14189 // op: Rd
14190 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14191 op &= UINT64_C(31);
14192 Value |= op;
14193 // op: Rn
14194 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14195 op &= UINT64_C(31);
14196 op <<= 5;
14197 Value |= op;
14198 // op: immr
14199 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14200 op &= UINT64_C(31);
14201 op <<= 16;
14202 Value |= op;
14203 // op: imms
14204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14205 op &= UINT64_C(31);
14206 op <<= 10;
14207 Value |= op;
14208 break;
14209 }
14210 case AArch64::SBFMXri:
14211 case AArch64::UBFMXri: {
14212 // op: Rd
14213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14214 op &= UINT64_C(31);
14215 Value |= op;
14216 // op: Rn
14217 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14218 op &= UINT64_C(31);
14219 op <<= 5;
14220 Value |= op;
14221 // op: immr
14222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14223 op &= UINT64_C(63);
14224 op <<= 16;
14225 Value |= op;
14226 // op: imms
14227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14228 op &= UINT64_C(63);
14229 op <<= 10;
14230 Value |= op;
14231 break;
14232 }
14233 case AArch64::FCVTZSSWDri:
14234 case AArch64::FCVTZSSWHri:
14235 case AArch64::FCVTZSSWSri:
14236 case AArch64::FCVTZUSWDri:
14237 case AArch64::FCVTZUSWHri:
14238 case AArch64::FCVTZUSWSri:
14239 case AArch64::SCVTFSWDri:
14240 case AArch64::SCVTFSWHri:
14241 case AArch64::SCVTFSWSri:
14242 case AArch64::UCVTFSWDri:
14243 case AArch64::UCVTFSWHri:
14244 case AArch64::UCVTFSWSri: {
14245 // op: Rd
14246 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14247 op &= UINT64_C(31);
14248 Value |= op;
14249 // op: Rn
14250 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14251 op &= UINT64_C(31);
14252 op <<= 5;
14253 Value |= op;
14254 // op: scale
14255 op = getFixedPointScaleOpValue(MI, OpIdx: 2, Fixups, STI);
14256 op &= UINT64_C(31);
14257 op <<= 10;
14258 Value |= op;
14259 break;
14260 }
14261 case AArch64::FCVTZSSXDri:
14262 case AArch64::FCVTZSSXHri:
14263 case AArch64::FCVTZSSXSri:
14264 case AArch64::FCVTZUSXDri:
14265 case AArch64::FCVTZUSXHri:
14266 case AArch64::FCVTZUSXSri:
14267 case AArch64::SCVTFSXDri:
14268 case AArch64::SCVTFSXHri:
14269 case AArch64::SCVTFSXSri:
14270 case AArch64::UCVTFSXDri:
14271 case AArch64::UCVTFSXHri:
14272 case AArch64::UCVTFSXSri: {
14273 // op: Rd
14274 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14275 op &= UINT64_C(31);
14276 Value |= op;
14277 // op: Rn
14278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14279 op &= UINT64_C(31);
14280 op <<= 5;
14281 Value |= op;
14282 // op: scale
14283 op = getFixedPointScaleOpValue(MI, OpIdx: 2, Fixups, STI);
14284 op &= UINT64_C(63);
14285 op <<= 10;
14286 Value |= op;
14287 break;
14288 }
14289 case AArch64::BFMWri: {
14290 // op: Rd
14291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14292 op &= UINT64_C(31);
14293 Value |= op;
14294 // op: Rn
14295 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14296 op &= UINT64_C(31);
14297 op <<= 5;
14298 Value |= op;
14299 // op: immr
14300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14301 op &= UINT64_C(31);
14302 op <<= 16;
14303 Value |= op;
14304 // op: imms
14305 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14306 op &= UINT64_C(31);
14307 op <<= 10;
14308 Value |= op;
14309 break;
14310 }
14311 case AArch64::BFMXri: {
14312 // op: Rd
14313 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14314 op &= UINT64_C(31);
14315 Value |= op;
14316 // op: Rn
14317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14318 op &= UINT64_C(31);
14319 op <<= 5;
14320 Value |= op;
14321 // op: immr
14322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14323 op &= UINT64_C(63);
14324 op <<= 16;
14325 Value |= op;
14326 // op: imms
14327 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14328 op &= UINT64_C(63);
14329 op <<= 10;
14330 Value |= op;
14331 break;
14332 }
14333 case AArch64::FMOVDi:
14334 case AArch64::FMOVHi:
14335 case AArch64::FMOVSi: {
14336 // op: Rd
14337 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14338 op &= UINT64_C(31);
14339 Value |= op;
14340 // op: imm
14341 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14342 op &= UINT64_C(255);
14343 op <<= 13;
14344 Value |= op;
14345 break;
14346 }
14347 case AArch64::MOVNWi:
14348 case AArch64::MOVNXi: {
14349 // op: Rd
14350 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14351 op &= UINT64_C(31);
14352 Value |= op;
14353 // op: imm
14354 op = getMoveWideImmOpValue(MI, OpIdx: 1, Fixups, STI);
14355 op &= UINT64_C(65535);
14356 op <<= 5;
14357 Value |= op;
14358 // op: shift
14359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14360 op &= UINT64_C(48);
14361 op <<= 17;
14362 Value |= op;
14363 break;
14364 }
14365 case AArch64::MOVZWi:
14366 case AArch64::MOVZXi: {
14367 // op: Rd
14368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14369 op &= UINT64_C(31);
14370 Value |= op;
14371 // op: imm
14372 op = getMoveWideImmOpValue(MI, OpIdx: 1, Fixups, STI);
14373 op &= UINT64_C(65535);
14374 op <<= 5;
14375 Value |= op;
14376 // op: shift
14377 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14378 op &= UINT64_C(48);
14379 op <<= 17;
14380 Value |= op;
14381 Value = fixMOVZ(MI, EncodedValue: Value, STI);
14382 break;
14383 }
14384 case AArch64::MOVKWi:
14385 case AArch64::MOVKXi: {
14386 // op: Rd
14387 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14388 op &= UINT64_C(31);
14389 Value |= op;
14390 // op: imm
14391 op = getMoveWideImmOpValue(MI, OpIdx: 2, Fixups, STI);
14392 op &= UINT64_C(65535);
14393 op <<= 5;
14394 Value |= op;
14395 // op: shift
14396 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14397 op &= UINT64_C(48);
14398 op <<= 17;
14399 Value |= op;
14400 break;
14401 }
14402 case AArch64::CNTB_XPiI:
14403 case AArch64::CNTD_XPiI:
14404 case AArch64::CNTH_XPiI:
14405 case AArch64::CNTW_XPiI: {
14406 // op: Rd
14407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14408 op &= UINT64_C(31);
14409 Value |= op;
14410 // op: imm4
14411 op = getSVEIncDecImm(MI, OpIdx: 2, Fixups, STI);
14412 op &= UINT64_C(15);
14413 op <<= 16;
14414 Value |= op;
14415 // op: pattern
14416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14417 op &= UINT64_C(31);
14418 op <<= 5;
14419 Value |= op;
14420 break;
14421 }
14422 case AArch64::RDSVLI_XI:
14423 case AArch64::RDVLI_XI: {
14424 // op: Rd
14425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14426 op &= UINT64_C(31);
14427 Value |= op;
14428 // op: imm6
14429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14430 op &= UINT64_C(63);
14431 op <<= 5;
14432 Value |= op;
14433 break;
14434 }
14435 case AArch64::FMOVv2f32_ns:
14436 case AArch64::FMOVv2f64_ns:
14437 case AArch64::FMOVv4f16_ns:
14438 case AArch64::FMOVv4f32_ns:
14439 case AArch64::FMOVv8f16_ns:
14440 case AArch64::MOVID:
14441 case AArch64::MOVIv2d_ns:
14442 case AArch64::MOVIv8b_ns:
14443 case AArch64::MOVIv16b_ns: {
14444 // op: Rd
14445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14446 op &= UINT64_C(31);
14447 Value |= op;
14448 // op: imm8
14449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14450 Value |= (op & UINT64_C(224)) << 11;
14451 Value |= (op & UINT64_C(31)) << 5;
14452 break;
14453 }
14454 case AArch64::MOVIv2s_msl:
14455 case AArch64::MOVIv4s_msl:
14456 case AArch64::MVNIv2s_msl:
14457 case AArch64::MVNIv4s_msl: {
14458 // op: Rd
14459 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14460 op &= UINT64_C(31);
14461 Value |= op;
14462 // op: imm8
14463 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14464 Value |= (op & UINT64_C(224)) << 11;
14465 Value |= (op & UINT64_C(31)) << 5;
14466 // op: shift
14467 op = getMoveVecShifterOpValue(MI, OpIdx: 2, Fixups, STI);
14468 op &= UINT64_C(1);
14469 op <<= 12;
14470 Value |= op;
14471 break;
14472 }
14473 case AArch64::MOVIv4i16:
14474 case AArch64::MOVIv8i16:
14475 case AArch64::MVNIv4i16:
14476 case AArch64::MVNIv8i16: {
14477 // op: Rd
14478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14479 op &= UINT64_C(31);
14480 Value |= op;
14481 // op: imm8
14482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14483 Value |= (op & UINT64_C(224)) << 11;
14484 Value |= (op & UINT64_C(31)) << 5;
14485 // op: shift
14486 op = getVecShifterOpValue(MI, OpIdx: 2, Fixups, STI);
14487 op &= UINT64_C(1);
14488 op <<= 13;
14489 Value |= op;
14490 break;
14491 }
14492 case AArch64::MOVIv2i32:
14493 case AArch64::MOVIv4i32:
14494 case AArch64::MVNIv2i32:
14495 case AArch64::MVNIv4i32: {
14496 // op: Rd
14497 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14498 op &= UINT64_C(31);
14499 Value |= op;
14500 // op: imm8
14501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14502 Value |= (op & UINT64_C(224)) << 11;
14503 Value |= (op & UINT64_C(31)) << 5;
14504 // op: shift
14505 op = getVecShifterOpValue(MI, OpIdx: 2, Fixups, STI);
14506 op &= UINT64_C(3);
14507 op <<= 13;
14508 Value |= op;
14509 break;
14510 }
14511 case AArch64::AUTDZA:
14512 case AArch64::AUTDZB:
14513 case AArch64::AUTIZA:
14514 case AArch64::AUTIZB:
14515 case AArch64::PACDZA:
14516 case AArch64::PACDZB:
14517 case AArch64::PACIZA:
14518 case AArch64::PACIZB: {
14519 // op: Rd
14520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14521 op &= UINT64_C(31);
14522 Value |= op;
14523 break;
14524 }
14525 case AArch64::AESDrr:
14526 case AArch64::AESErr:
14527 case AArch64::AUTDA:
14528 case AArch64::AUTDB:
14529 case AArch64::AUTIA:
14530 case AArch64::AUTIB:
14531 case AArch64::BFCVTN2:
14532 case AArch64::FCVTNv4i32:
14533 case AArch64::FCVTNv8i16:
14534 case AArch64::FCVTXNv4f32:
14535 case AArch64::PACDA:
14536 case AArch64::PACDB:
14537 case AArch64::PACIA:
14538 case AArch64::PACIB:
14539 case AArch64::SADALPv2i32_v1i64:
14540 case AArch64::SADALPv4i16_v2i32:
14541 case AArch64::SADALPv4i32_v2i64:
14542 case AArch64::SADALPv8i8_v4i16:
14543 case AArch64::SADALPv8i16_v4i32:
14544 case AArch64::SADALPv16i8_v8i16:
14545 case AArch64::SHA1SU1rr:
14546 case AArch64::SHA256SU0rr:
14547 case AArch64::SQXTNv4i32:
14548 case AArch64::SQXTNv8i16:
14549 case AArch64::SQXTNv16i8:
14550 case AArch64::SQXTUNv4i32:
14551 case AArch64::SQXTUNv8i16:
14552 case AArch64::SQXTUNv16i8:
14553 case AArch64::SUQADDv1i8:
14554 case AArch64::SUQADDv1i16:
14555 case AArch64::SUQADDv1i32:
14556 case AArch64::SUQADDv1i64:
14557 case AArch64::SUQADDv2i32:
14558 case AArch64::SUQADDv2i64:
14559 case AArch64::SUQADDv4i16:
14560 case AArch64::SUQADDv4i32:
14561 case AArch64::SUQADDv8i8:
14562 case AArch64::SUQADDv8i16:
14563 case AArch64::SUQADDv16i8:
14564 case AArch64::UADALPv2i32_v1i64:
14565 case AArch64::UADALPv4i16_v2i32:
14566 case AArch64::UADALPv4i32_v2i64:
14567 case AArch64::UADALPv8i8_v4i16:
14568 case AArch64::UADALPv8i16_v4i32:
14569 case AArch64::UADALPv16i8_v8i16:
14570 case AArch64::UQXTNv4i32:
14571 case AArch64::UQXTNv8i16:
14572 case AArch64::UQXTNv16i8:
14573 case AArch64::USQADDv1i8:
14574 case AArch64::USQADDv1i16:
14575 case AArch64::USQADDv1i32:
14576 case AArch64::USQADDv1i64:
14577 case AArch64::USQADDv2i32:
14578 case AArch64::USQADDv2i64:
14579 case AArch64::USQADDv4i16:
14580 case AArch64::USQADDv4i32:
14581 case AArch64::USQADDv8i8:
14582 case AArch64::USQADDv8i16:
14583 case AArch64::USQADDv16i8:
14584 case AArch64::XTNv4i32:
14585 case AArch64::XTNv8i16:
14586 case AArch64::XTNv16i8: {
14587 // op: Rd
14588 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14589 op &= UINT64_C(31);
14590 Value |= op;
14591 // op: Rn
14592 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14593 op &= UINT64_C(31);
14594 op <<= 5;
14595 Value |= op;
14596 break;
14597 }
14598 case AArch64::BFMLALBIdx:
14599 case AArch64::BFMLALTIdx:
14600 case AArch64::FDOTlanev4f16:
14601 case AArch64::FDOTlanev8f16:
14602 case AArch64::FMLAL2lanev4f16:
14603 case AArch64::FMLAL2lanev8f16:
14604 case AArch64::FMLALlanev4f16:
14605 case AArch64::FMLALlanev8f16:
14606 case AArch64::FMLAv1i16_indexed:
14607 case AArch64::FMLAv4i16_indexed:
14608 case AArch64::FMLAv8i16_indexed:
14609 case AArch64::FMLSL2lanev4f16:
14610 case AArch64::FMLSL2lanev8f16:
14611 case AArch64::FMLSLlanev4f16:
14612 case AArch64::FMLSLlanev8f16:
14613 case AArch64::FMLSv1i16_indexed:
14614 case AArch64::FMLSv4i16_indexed:
14615 case AArch64::FMLSv8i16_indexed:
14616 case AArch64::MLAv4i16_indexed:
14617 case AArch64::MLAv8i16_indexed:
14618 case AArch64::MLSv4i16_indexed:
14619 case AArch64::MLSv8i16_indexed:
14620 case AArch64::SMLALv4i16_indexed:
14621 case AArch64::SMLALv8i16_indexed:
14622 case AArch64::SMLSLv4i16_indexed:
14623 case AArch64::SMLSLv8i16_indexed:
14624 case AArch64::SQDMLALv1i32_indexed:
14625 case AArch64::SQDMLALv4i16_indexed:
14626 case AArch64::SQDMLALv8i16_indexed:
14627 case AArch64::SQDMLSLv1i32_indexed:
14628 case AArch64::SQDMLSLv4i16_indexed:
14629 case AArch64::SQDMLSLv8i16_indexed:
14630 case AArch64::SQRDMLAHv1i16_indexed:
14631 case AArch64::SQRDMLAHv4i16_indexed:
14632 case AArch64::SQRDMLAHv8i16_indexed:
14633 case AArch64::SQRDMLSHv1i16_indexed:
14634 case AArch64::SQRDMLSHv4i16_indexed:
14635 case AArch64::SQRDMLSHv8i16_indexed:
14636 case AArch64::UMLALv4i16_indexed:
14637 case AArch64::UMLALv8i16_indexed:
14638 case AArch64::UMLSLv4i16_indexed:
14639 case AArch64::UMLSLv8i16_indexed: {
14640 // op: Rd
14641 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14642 op &= UINT64_C(31);
14643 Value |= op;
14644 // op: Rn
14645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14646 op &= UINT64_C(31);
14647 op <<= 5;
14648 Value |= op;
14649 // op: Rm
14650 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14651 op &= UINT64_C(15);
14652 op <<= 16;
14653 Value |= op;
14654 // op: idx
14655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14656 Value |= (op & UINT64_C(3)) << 20;
14657 Value |= (op & UINT64_C(4)) << 9;
14658 break;
14659 }
14660 case AArch64::ADDHNv2i64_v4i32:
14661 case AArch64::ADDHNv4i32_v8i16:
14662 case AArch64::ADDHNv8i16_v16i8:
14663 case AArch64::BFDOTv4bf16:
14664 case AArch64::BFDOTv8bf16:
14665 case AArch64::BFMLALB:
14666 case AArch64::BFMLALT:
14667 case AArch64::BFMMLA:
14668 case AArch64::BIFv8i8:
14669 case AArch64::BIFv16i8:
14670 case AArch64::BITv8i8:
14671 case AArch64::BITv16i8:
14672 case AArch64::BSLv8i8:
14673 case AArch64::BSLv16i8:
14674 case AArch64::FCVTN_F322v16f8:
14675 case AArch64::FDOTv2f32:
14676 case AArch64::FDOTv4f16:
14677 case AArch64::FDOTv4f32:
14678 case AArch64::FDOTv8f16:
14679 case AArch64::FMLAL2v4f16:
14680 case AArch64::FMLAL2v8f16:
14681 case AArch64::FMLALBv8f16:
14682 case AArch64::FMLALLBBv4f32:
14683 case AArch64::FMLALLBTv4f32:
14684 case AArch64::FMLALLTBv4f32:
14685 case AArch64::FMLALLTTv4f32:
14686 case AArch64::FMLALTv8f16:
14687 case AArch64::FMLALv4f16:
14688 case AArch64::FMLALv8f16:
14689 case AArch64::FMLAv2f32:
14690 case AArch64::FMLAv2f64:
14691 case AArch64::FMLAv4f16:
14692 case AArch64::FMLAv4f32:
14693 case AArch64::FMLAv8f16:
14694 case AArch64::FMLSL2v4f16:
14695 case AArch64::FMLSL2v8f16:
14696 case AArch64::FMLSLv4f16:
14697 case AArch64::FMLSLv8f16:
14698 case AArch64::FMLSv2f32:
14699 case AArch64::FMLSv2f64:
14700 case AArch64::FMLSv4f16:
14701 case AArch64::FMLSv4f32:
14702 case AArch64::FMLSv8f16:
14703 case AArch64::FMMLAv4f32:
14704 case AArch64::FMMLAv8f16:
14705 case AArch64::MLAv2i32:
14706 case AArch64::MLAv4i16:
14707 case AArch64::MLAv4i32:
14708 case AArch64::MLAv8i8:
14709 case AArch64::MLAv8i16:
14710 case AArch64::MLAv16i8:
14711 case AArch64::MLSv2i32:
14712 case AArch64::MLSv4i16:
14713 case AArch64::MLSv4i32:
14714 case AArch64::MLSv8i8:
14715 case AArch64::MLSv8i16:
14716 case AArch64::MLSv16i8:
14717 case AArch64::RADDHNv2i64_v4i32:
14718 case AArch64::RADDHNv4i32_v8i16:
14719 case AArch64::RADDHNv8i16_v16i8:
14720 case AArch64::RSUBHNv2i64_v4i32:
14721 case AArch64::RSUBHNv4i32_v8i16:
14722 case AArch64::RSUBHNv8i16_v16i8:
14723 case AArch64::SABALv2i32_v2i64:
14724 case AArch64::SABALv4i16_v4i32:
14725 case AArch64::SABALv4i32_v2i64:
14726 case AArch64::SABALv8i8_v8i16:
14727 case AArch64::SABALv8i16_v4i32:
14728 case AArch64::SABALv16i8_v8i16:
14729 case AArch64::SABAv2i32:
14730 case AArch64::SABAv4i16:
14731 case AArch64::SABAv4i32:
14732 case AArch64::SABAv8i8:
14733 case AArch64::SABAv8i16:
14734 case AArch64::SABAv16i8:
14735 case AArch64::SDOTv8i8:
14736 case AArch64::SDOTv16i8:
14737 case AArch64::SHA1Crrr:
14738 case AArch64::SHA1Mrrr:
14739 case AArch64::SHA1Prrr:
14740 case AArch64::SHA1SU0rrr:
14741 case AArch64::SHA256H2rrr:
14742 case AArch64::SHA256Hrrr:
14743 case AArch64::SHA256SU1rrr:
14744 case AArch64::SMLALv2i32_v2i64:
14745 case AArch64::SMLALv4i16_v4i32:
14746 case AArch64::SMLALv4i32_v2i64:
14747 case AArch64::SMLALv8i8_v8i16:
14748 case AArch64::SMLALv8i16_v4i32:
14749 case AArch64::SMLALv16i8_v8i16:
14750 case AArch64::SMLSLv2i32_v2i64:
14751 case AArch64::SMLSLv4i16_v4i32:
14752 case AArch64::SMLSLv4i32_v2i64:
14753 case AArch64::SMLSLv8i8_v8i16:
14754 case AArch64::SMLSLv8i16_v4i32:
14755 case AArch64::SMLSLv16i8_v8i16:
14756 case AArch64::SMMLA:
14757 case AArch64::SQDMLALi16:
14758 case AArch64::SQDMLALi32:
14759 case AArch64::SQDMLALv2i32_v2i64:
14760 case AArch64::SQDMLALv4i16_v4i32:
14761 case AArch64::SQDMLALv4i32_v2i64:
14762 case AArch64::SQDMLALv8i16_v4i32:
14763 case AArch64::SQDMLSLi16:
14764 case AArch64::SQDMLSLi32:
14765 case AArch64::SQDMLSLv2i32_v2i64:
14766 case AArch64::SQDMLSLv4i16_v4i32:
14767 case AArch64::SQDMLSLv4i32_v2i64:
14768 case AArch64::SQDMLSLv8i16_v4i32:
14769 case AArch64::SQRDMLAHv1i16:
14770 case AArch64::SQRDMLAHv1i32:
14771 case AArch64::SQRDMLAHv2i32:
14772 case AArch64::SQRDMLAHv4i16:
14773 case AArch64::SQRDMLAHv4i32:
14774 case AArch64::SQRDMLAHv8i16:
14775 case AArch64::SQRDMLSHv1i16:
14776 case AArch64::SQRDMLSHv1i32:
14777 case AArch64::SQRDMLSHv2i32:
14778 case AArch64::SQRDMLSHv4i16:
14779 case AArch64::SQRDMLSHv4i32:
14780 case AArch64::SQRDMLSHv8i16:
14781 case AArch64::SUBHNv2i64_v4i32:
14782 case AArch64::SUBHNv4i32_v8i16:
14783 case AArch64::SUBHNv8i16_v16i8:
14784 case AArch64::UABALv2i32_v2i64:
14785 case AArch64::UABALv4i16_v4i32:
14786 case AArch64::UABALv4i32_v2i64:
14787 case AArch64::UABALv8i8_v8i16:
14788 case AArch64::UABALv8i16_v4i32:
14789 case AArch64::UABALv16i8_v8i16:
14790 case AArch64::UABAv2i32:
14791 case AArch64::UABAv4i16:
14792 case AArch64::UABAv4i32:
14793 case AArch64::UABAv8i8:
14794 case AArch64::UABAv8i16:
14795 case AArch64::UABAv16i8:
14796 case AArch64::UDOTv8i8:
14797 case AArch64::UDOTv16i8:
14798 case AArch64::UMLALv2i32_v2i64:
14799 case AArch64::UMLALv4i16_v4i32:
14800 case AArch64::UMLALv4i32_v2i64:
14801 case AArch64::UMLALv8i8_v8i16:
14802 case AArch64::UMLALv8i16_v4i32:
14803 case AArch64::UMLALv16i8_v8i16:
14804 case AArch64::UMLSLv2i32_v2i64:
14805 case AArch64::UMLSLv4i16_v4i32:
14806 case AArch64::UMLSLv4i32_v2i64:
14807 case AArch64::UMLSLv8i8_v8i16:
14808 case AArch64::UMLSLv8i16_v4i32:
14809 case AArch64::UMLSLv16i8_v8i16:
14810 case AArch64::UMMLA:
14811 case AArch64::USDOTv8i8:
14812 case AArch64::USDOTv16i8:
14813 case AArch64::USMMLA: {
14814 // op: Rd
14815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14816 op &= UINT64_C(31);
14817 Value |= op;
14818 // op: Rn
14819 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14820 op &= UINT64_C(31);
14821 op <<= 5;
14822 Value |= op;
14823 // op: Rm
14824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14825 op &= UINT64_C(31);
14826 op <<= 16;
14827 Value |= op;
14828 break;
14829 }
14830 case AArch64::BF16DOTlanev4bf16:
14831 case AArch64::BF16DOTlanev8bf16:
14832 case AArch64::FDOTlanev2f32:
14833 case AArch64::FDOTlanev4f32:
14834 case AArch64::FMLAv1i32_indexed:
14835 case AArch64::FMLAv2i32_indexed:
14836 case AArch64::FMLAv4i32_indexed:
14837 case AArch64::FMLSv1i32_indexed:
14838 case AArch64::FMLSv2i32_indexed:
14839 case AArch64::FMLSv4i32_indexed:
14840 case AArch64::MLAv2i32_indexed:
14841 case AArch64::MLAv4i32_indexed:
14842 case AArch64::MLSv2i32_indexed:
14843 case AArch64::MLSv4i32_indexed:
14844 case AArch64::SDOTlanev8i8:
14845 case AArch64::SDOTlanev16i8:
14846 case AArch64::SMLALv2i32_indexed:
14847 case AArch64::SMLALv4i32_indexed:
14848 case AArch64::SMLSLv2i32_indexed:
14849 case AArch64::SMLSLv4i32_indexed:
14850 case AArch64::SQDMLALv1i64_indexed:
14851 case AArch64::SQDMLALv2i32_indexed:
14852 case AArch64::SQDMLALv4i32_indexed:
14853 case AArch64::SQDMLSLv1i64_indexed:
14854 case AArch64::SQDMLSLv2i32_indexed:
14855 case AArch64::SQDMLSLv4i32_indexed:
14856 case AArch64::SQRDMLAHv1i32_indexed:
14857 case AArch64::SQRDMLAHv2i32_indexed:
14858 case AArch64::SQRDMLAHv4i32_indexed:
14859 case AArch64::SQRDMLSHv1i32_indexed:
14860 case AArch64::SQRDMLSHv2i32_indexed:
14861 case AArch64::SQRDMLSHv4i32_indexed:
14862 case AArch64::SUDOTlanev8i8:
14863 case AArch64::SUDOTlanev16i8:
14864 case AArch64::UDOTlanev8i8:
14865 case AArch64::UDOTlanev16i8:
14866 case AArch64::UMLALv2i32_indexed:
14867 case AArch64::UMLALv4i32_indexed:
14868 case AArch64::UMLSLv2i32_indexed:
14869 case AArch64::UMLSLv4i32_indexed:
14870 case AArch64::USDOTlanev8i8:
14871 case AArch64::USDOTlanev16i8: {
14872 // op: Rd
14873 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14874 op &= UINT64_C(31);
14875 Value |= op;
14876 // op: Rn
14877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14878 op &= UINT64_C(31);
14879 op <<= 5;
14880 Value |= op;
14881 // op: Rm
14882 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14883 op &= UINT64_C(31);
14884 op <<= 16;
14885 Value |= op;
14886 // op: idx
14887 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14888 Value |= (op & UINT64_C(1)) << 21;
14889 Value |= (op & UINT64_C(2)) << 10;
14890 break;
14891 }
14892 case AArch64::FMLAv1i64_indexed:
14893 case AArch64::FMLAv2i64_indexed:
14894 case AArch64::FMLSv1i64_indexed:
14895 case AArch64::FMLSv2i64_indexed: {
14896 // op: Rd
14897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14898 op &= UINT64_C(31);
14899 Value |= op;
14900 // op: Rn
14901 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14902 op &= UINT64_C(31);
14903 op <<= 5;
14904 Value |= op;
14905 // op: Rm
14906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14907 op &= UINT64_C(31);
14908 op <<= 16;
14909 Value |= op;
14910 // op: idx
14911 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14912 op &= UINT64_C(1);
14913 op <<= 11;
14914 Value |= op;
14915 break;
14916 }
14917 case AArch64::FCMLAv2f32:
14918 case AArch64::FCMLAv2f64:
14919 case AArch64::FCMLAv4f16:
14920 case AArch64::FCMLAv4f32:
14921 case AArch64::FCMLAv8f16: {
14922 // op: Rd
14923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14924 op &= UINT64_C(31);
14925 Value |= op;
14926 // op: Rn
14927 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14928 op &= UINT64_C(31);
14929 op <<= 5;
14930 Value |= op;
14931 // op: Rm
14932 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14933 op &= UINT64_C(31);
14934 op <<= 16;
14935 Value |= op;
14936 // op: rot
14937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14938 op &= UINT64_C(3);
14939 op <<= 11;
14940 Value |= op;
14941 break;
14942 }
14943 case AArch64::FCMLAv8f16_indexed: {
14944 // op: Rd
14945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14946 op &= UINT64_C(31);
14947 Value |= op;
14948 // op: Rn
14949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14950 op &= UINT64_C(31);
14951 op <<= 5;
14952 Value |= op;
14953 // op: Rm
14954 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14955 op &= UINT64_C(31);
14956 op <<= 16;
14957 Value |= op;
14958 // op: rot
14959 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14960 op &= UINT64_C(3);
14961 op <<= 13;
14962 Value |= op;
14963 // op: idx
14964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14965 Value |= (op & UINT64_C(1)) << 21;
14966 Value |= (op & UINT64_C(2)) << 10;
14967 break;
14968 }
14969 case AArch64::FCMLAv4f32_indexed: {
14970 // op: Rd
14971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14972 op &= UINT64_C(31);
14973 Value |= op;
14974 // op: Rn
14975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14976 op &= UINT64_C(31);
14977 op <<= 5;
14978 Value |= op;
14979 // op: Rm
14980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14981 op &= UINT64_C(31);
14982 op <<= 16;
14983 Value |= op;
14984 // op: rot
14985 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14986 op &= UINT64_C(3);
14987 op <<= 13;
14988 Value |= op;
14989 // op: idx
14990 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14991 op &= UINT64_C(1);
14992 op <<= 11;
14993 Value |= op;
14994 break;
14995 }
14996 case AArch64::FCMLAv4f16_indexed: {
14997 // op: Rd
14998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14999 op &= UINT64_C(31);
15000 Value |= op;
15001 // op: Rn
15002 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15003 op &= UINT64_C(31);
15004 op <<= 5;
15005 Value |= op;
15006 // op: Rm
15007 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15008 op &= UINT64_C(31);
15009 op <<= 16;
15010 Value |= op;
15011 // op: rot
15012 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
15013 op &= UINT64_C(3);
15014 op <<= 13;
15015 Value |= op;
15016 // op: idx
15017 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15018 op &= UINT64_C(1);
15019 op <<= 21;
15020 Value |= op;
15021 break;
15022 }
15023 case AArch64::FMLALBlanev8f16:
15024 case AArch64::FMLALLBBlanev4f32:
15025 case AArch64::FMLALLBTlanev4f32:
15026 case AArch64::FMLALLTBlanev4f32:
15027 case AArch64::FMLALLTTlanev4f32:
15028 case AArch64::FMLALTlanev8f16: {
15029 // op: Rd
15030 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15031 op &= UINT64_C(31);
15032 Value |= op;
15033 // op: Rn
15034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15035 op &= UINT64_C(31);
15036 op <<= 5;
15037 Value |= op;
15038 // op: Rm
15039 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15040 op &= UINT64_C(7);
15041 op <<= 16;
15042 Value |= op;
15043 // op: idx
15044 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15045 Value |= (op & UINT64_C(7)) << 19;
15046 Value |= (op & UINT64_C(8)) << 8;
15047 break;
15048 }
15049 case AArch64::SLIv4i16_shift:
15050 case AArch64::SLIv8i16_shift: {
15051 // op: Rd
15052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15053 op &= UINT64_C(31);
15054 Value |= op;
15055 // op: Rn
15056 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15057 op &= UINT64_C(31);
15058 op <<= 5;
15059 Value |= op;
15060 // op: imm
15061 op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI);
15062 op &= UINT64_C(15);
15063 op <<= 16;
15064 Value |= op;
15065 break;
15066 }
15067 case AArch64::SLIv2i32_shift:
15068 case AArch64::SLIv4i32_shift: {
15069 // op: Rd
15070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15071 op &= UINT64_C(31);
15072 Value |= op;
15073 // op: Rn
15074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15075 op &= UINT64_C(31);
15076 op <<= 5;
15077 Value |= op;
15078 // op: imm
15079 op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI);
15080 op &= UINT64_C(31);
15081 op <<= 16;
15082 Value |= op;
15083 break;
15084 }
15085 case AArch64::SLId:
15086 case AArch64::SLIv2i64_shift: {
15087 // op: Rd
15088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15089 op &= UINT64_C(31);
15090 Value |= op;
15091 // op: Rn
15092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15093 op &= UINT64_C(31);
15094 op <<= 5;
15095 Value |= op;
15096 // op: imm
15097 op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI);
15098 op &= UINT64_C(63);
15099 op <<= 16;
15100 Value |= op;
15101 break;
15102 }
15103 case AArch64::SLIv8i8_shift:
15104 case AArch64::SLIv16i8_shift: {
15105 // op: Rd
15106 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15107 op &= UINT64_C(31);
15108 Value |= op;
15109 // op: Rn
15110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15111 op &= UINT64_C(31);
15112 op <<= 5;
15113 Value |= op;
15114 // op: imm
15115 op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI);
15116 op &= UINT64_C(7);
15117 op <<= 16;
15118 Value |= op;
15119 break;
15120 }
15121 case AArch64::SRIv4i16_shift:
15122 case AArch64::SRIv8i16_shift:
15123 case AArch64::SRSRAv4i16_shift:
15124 case AArch64::SRSRAv8i16_shift:
15125 case AArch64::SSRAv4i16_shift:
15126 case AArch64::SSRAv8i16_shift:
15127 case AArch64::URSRAv4i16_shift:
15128 case AArch64::URSRAv8i16_shift:
15129 case AArch64::USRAv4i16_shift:
15130 case AArch64::USRAv8i16_shift: {
15131 // op: Rd
15132 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15133 op &= UINT64_C(31);
15134 Value |= op;
15135 // op: Rn
15136 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15137 op &= UINT64_C(31);
15138 op <<= 5;
15139 Value |= op;
15140 // op: imm
15141 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
15142 op &= UINT64_C(15);
15143 op <<= 16;
15144 Value |= op;
15145 break;
15146 }
15147 case AArch64::RSHRNv16i8_shift:
15148 case AArch64::SHRNv16i8_shift:
15149 case AArch64::SQRSHRNv16i8_shift:
15150 case AArch64::SQRSHRUNv16i8_shift:
15151 case AArch64::SQSHRNv16i8_shift:
15152 case AArch64::SQSHRUNv16i8_shift:
15153 case AArch64::UQRSHRNv16i8_shift:
15154 case AArch64::UQSHRNv16i8_shift: {
15155 // op: Rd
15156 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15157 op &= UINT64_C(31);
15158 Value |= op;
15159 // op: Rn
15160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15161 op &= UINT64_C(31);
15162 op <<= 5;
15163 Value |= op;
15164 // op: imm
15165 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
15166 op &= UINT64_C(7);
15167 op <<= 16;
15168 Value |= op;
15169 break;
15170 }
15171 case AArch64::RSHRNv8i16_shift:
15172 case AArch64::SHRNv8i16_shift:
15173 case AArch64::SQRSHRNv8i16_shift:
15174 case AArch64::SQRSHRUNv8i16_shift:
15175 case AArch64::SQSHRNv8i16_shift:
15176 case AArch64::SQSHRUNv8i16_shift:
15177 case AArch64::UQRSHRNv8i16_shift:
15178 case AArch64::UQSHRNv8i16_shift: {
15179 // op: Rd
15180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15181 op &= UINT64_C(31);
15182 Value |= op;
15183 // op: Rn
15184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15185 op &= UINT64_C(31);
15186 op <<= 5;
15187 Value |= op;
15188 // op: imm
15189 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
15190 op &= UINT64_C(15);
15191 op <<= 16;
15192 Value |= op;
15193 break;
15194 }
15195 case AArch64::SRIv2i32_shift:
15196 case AArch64::SRIv4i32_shift:
15197 case AArch64::SRSRAv2i32_shift:
15198 case AArch64::SRSRAv4i32_shift:
15199 case AArch64::SSRAv2i32_shift:
15200 case AArch64::SSRAv4i32_shift:
15201 case AArch64::URSRAv2i32_shift:
15202 case AArch64::URSRAv4i32_shift:
15203 case AArch64::USRAv2i32_shift:
15204 case AArch64::USRAv4i32_shift: {
15205 // op: Rd
15206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15207 op &= UINT64_C(31);
15208 Value |= op;
15209 // op: Rn
15210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15211 op &= UINT64_C(31);
15212 op <<= 5;
15213 Value |= op;
15214 // op: imm
15215 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
15216 op &= UINT64_C(31);
15217 op <<= 16;
15218 Value |= op;
15219 break;
15220 }
15221 case AArch64::RSHRNv4i32_shift:
15222 case AArch64::SHRNv4i32_shift:
15223 case AArch64::SQRSHRNv4i32_shift:
15224 case AArch64::SQRSHRUNv4i32_shift:
15225 case AArch64::SQSHRNv4i32_shift:
15226 case AArch64::SQSHRUNv4i32_shift:
15227 case AArch64::UQRSHRNv4i32_shift:
15228 case AArch64::UQSHRNv4i32_shift: {
15229 // op: Rd
15230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15231 op &= UINT64_C(31);
15232 Value |= op;
15233 // op: Rn
15234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15235 op &= UINT64_C(31);
15236 op <<= 5;
15237 Value |= op;
15238 // op: imm
15239 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
15240 op &= UINT64_C(31);
15241 op <<= 16;
15242 Value |= op;
15243 break;
15244 }
15245 case AArch64::SRId:
15246 case AArch64::SRIv2i64_shift:
15247 case AArch64::SRSRAd:
15248 case AArch64::SRSRAv2i64_shift:
15249 case AArch64::SSRAd:
15250 case AArch64::SSRAv2i64_shift:
15251 case AArch64::URSRAd:
15252 case AArch64::URSRAv2i64_shift:
15253 case AArch64::USRAd:
15254 case AArch64::USRAv2i64_shift: {
15255 // op: Rd
15256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15257 op &= UINT64_C(31);
15258 Value |= op;
15259 // op: Rn
15260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15261 op &= UINT64_C(31);
15262 op <<= 5;
15263 Value |= op;
15264 // op: imm
15265 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
15266 op &= UINT64_C(63);
15267 op <<= 16;
15268 Value |= op;
15269 break;
15270 }
15271 case AArch64::SRIv8i8_shift:
15272 case AArch64::SRIv16i8_shift:
15273 case AArch64::SRSRAv8i8_shift:
15274 case AArch64::SRSRAv16i8_shift:
15275 case AArch64::SSRAv8i8_shift:
15276 case AArch64::SSRAv16i8_shift:
15277 case AArch64::URSRAv8i8_shift:
15278 case AArch64::URSRAv16i8_shift:
15279 case AArch64::USRAv8i8_shift:
15280 case AArch64::USRAv16i8_shift: {
15281 // op: Rd
15282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15283 op &= UINT64_C(31);
15284 Value |= op;
15285 // op: Rn
15286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15287 op &= UINT64_C(31);
15288 op <<= 5;
15289 Value |= op;
15290 // op: imm
15291 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
15292 op &= UINT64_C(7);
15293 op <<= 16;
15294 Value |= op;
15295 break;
15296 }
15297 case AArch64::INSvi64gpr: {
15298 // op: Rd
15299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15300 op &= UINT64_C(31);
15301 Value |= op;
15302 // op: Rn
15303 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15304 op &= UINT64_C(31);
15305 op <<= 5;
15306 Value |= op;
15307 // op: idx
15308 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15309 op &= UINT64_C(1);
15310 op <<= 20;
15311 Value |= op;
15312 break;
15313 }
15314 case AArch64::INSvi64lane: {
15315 // op: Rd
15316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15317 op &= UINT64_C(31);
15318 Value |= op;
15319 // op: Rn
15320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15321 op &= UINT64_C(31);
15322 op <<= 5;
15323 Value |= op;
15324 // op: idx
15325 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15326 op &= UINT64_C(1);
15327 op <<= 20;
15328 Value |= op;
15329 // op: idx2
15330 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15331 op &= UINT64_C(1);
15332 op <<= 14;
15333 Value |= op;
15334 break;
15335 }
15336 case AArch64::INSvi8gpr: {
15337 // op: Rd
15338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15339 op &= UINT64_C(31);
15340 Value |= op;
15341 // op: Rn
15342 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15343 op &= UINT64_C(31);
15344 op <<= 5;
15345 Value |= op;
15346 // op: idx
15347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15348 op &= UINT64_C(15);
15349 op <<= 17;
15350 Value |= op;
15351 break;
15352 }
15353 case AArch64::INSvi8lane: {
15354 // op: Rd
15355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15356 op &= UINT64_C(31);
15357 Value |= op;
15358 // op: Rn
15359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15360 op &= UINT64_C(31);
15361 op <<= 5;
15362 Value |= op;
15363 // op: idx
15364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15365 op &= UINT64_C(15);
15366 op <<= 17;
15367 Value |= op;
15368 // op: idx2
15369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15370 op &= UINT64_C(15);
15371 op <<= 11;
15372 Value |= op;
15373 break;
15374 }
15375 case AArch64::INSvi32gpr: {
15376 // op: Rd
15377 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15378 op &= UINT64_C(31);
15379 Value |= op;
15380 // op: Rn
15381 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15382 op &= UINT64_C(31);
15383 op <<= 5;
15384 Value |= op;
15385 // op: idx
15386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15387 op &= UINT64_C(3);
15388 op <<= 19;
15389 Value |= op;
15390 break;
15391 }
15392 case AArch64::INSvi32lane: {
15393 // op: Rd
15394 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15395 op &= UINT64_C(31);
15396 Value |= op;
15397 // op: Rn
15398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15399 op &= UINT64_C(31);
15400 op <<= 5;
15401 Value |= op;
15402 // op: idx
15403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15404 op &= UINT64_C(3);
15405 op <<= 19;
15406 Value |= op;
15407 // op: idx2
15408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15409 op &= UINT64_C(3);
15410 op <<= 13;
15411 Value |= op;
15412 break;
15413 }
15414 case AArch64::INSvi16gpr: {
15415 // op: Rd
15416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15417 op &= UINT64_C(31);
15418 Value |= op;
15419 // op: Rn
15420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15421 op &= UINT64_C(31);
15422 op <<= 5;
15423 Value |= op;
15424 // op: idx
15425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15426 op &= UINT64_C(7);
15427 op <<= 18;
15428 Value |= op;
15429 break;
15430 }
15431 case AArch64::INSvi16lane: {
15432 // op: Rd
15433 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15434 op &= UINT64_C(31);
15435 Value |= op;
15436 // op: Rn
15437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15438 op &= UINT64_C(31);
15439 op <<= 5;
15440 Value |= op;
15441 // op: idx
15442 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15443 op &= UINT64_C(7);
15444 op <<= 18;
15445 Value |= op;
15446 // op: idx2
15447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15448 op &= UINT64_C(7);
15449 op <<= 12;
15450 Value |= op;
15451 break;
15452 }
15453 case AArch64::BICv4i16:
15454 case AArch64::BICv8i16:
15455 case AArch64::ORRv4i16:
15456 case AArch64::ORRv8i16: {
15457 // op: Rd
15458 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15459 op &= UINT64_C(31);
15460 Value |= op;
15461 // op: imm8
15462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15463 Value |= (op & UINT64_C(224)) << 11;
15464 Value |= (op & UINT64_C(31)) << 5;
15465 // op: shift
15466 op = getVecShifterOpValue(MI, OpIdx: 3, Fixups, STI);
15467 op &= UINT64_C(1);
15468 op <<= 13;
15469 Value |= op;
15470 break;
15471 }
15472 case AArch64::BICv2i32:
15473 case AArch64::BICv4i32:
15474 case AArch64::ORRv2i32:
15475 case AArch64::ORRv4i32: {
15476 // op: Rd
15477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15478 op &= UINT64_C(31);
15479 Value |= op;
15480 // op: imm8
15481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15482 Value |= (op & UINT64_C(224)) << 11;
15483 Value |= (op & UINT64_C(31)) << 5;
15484 // op: shift
15485 op = getVecShifterOpValue(MI, OpIdx: 3, Fixups, STI);
15486 op &= UINT64_C(3);
15487 op <<= 13;
15488 Value |= op;
15489 break;
15490 }
15491 case AArch64::MOPSSETGE:
15492 case AArch64::MOPSSETGEN:
15493 case AArch64::MOPSSETGET:
15494 case AArch64::MOPSSETGETN:
15495 case AArch64::SETE:
15496 case AArch64::SETEN:
15497 case AArch64::SETET:
15498 case AArch64::SETETN:
15499 case AArch64::SETGM:
15500 case AArch64::SETGMN:
15501 case AArch64::SETGMT:
15502 case AArch64::SETGMTN:
15503 case AArch64::SETGP:
15504 case AArch64::SETGPN:
15505 case AArch64::SETGPT:
15506 case AArch64::SETGPTN:
15507 case AArch64::SETM:
15508 case AArch64::SETMN:
15509 case AArch64::SETMT:
15510 case AArch64::SETMTN:
15511 case AArch64::SETP:
15512 case AArch64::SETPN:
15513 case AArch64::SETPT:
15514 case AArch64::SETPTN: {
15515 // op: Rd
15516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15517 op &= UINT64_C(31);
15518 Value |= op;
15519 // op: Rn
15520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15521 op &= UINT64_C(31);
15522 op <<= 5;
15523 Value |= op;
15524 // op: Rm
15525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15526 op &= UINT64_C(31);
15527 op <<= 16;
15528 Value |= op;
15529 break;
15530 }
15531 case AArch64::CPYE:
15532 case AArch64::CPYEN:
15533 case AArch64::CPYERN:
15534 case AArch64::CPYERT:
15535 case AArch64::CPYERTN:
15536 case AArch64::CPYERTRN:
15537 case AArch64::CPYERTWN:
15538 case AArch64::CPYET:
15539 case AArch64::CPYETN:
15540 case AArch64::CPYETRN:
15541 case AArch64::CPYETWN:
15542 case AArch64::CPYEWN:
15543 case AArch64::CPYEWT:
15544 case AArch64::CPYEWTN:
15545 case AArch64::CPYEWTRN:
15546 case AArch64::CPYEWTWN:
15547 case AArch64::CPYFE:
15548 case AArch64::CPYFEN:
15549 case AArch64::CPYFERN:
15550 case AArch64::CPYFERT:
15551 case AArch64::CPYFERTN:
15552 case AArch64::CPYFERTRN:
15553 case AArch64::CPYFERTWN:
15554 case AArch64::CPYFET:
15555 case AArch64::CPYFETN:
15556 case AArch64::CPYFETRN:
15557 case AArch64::CPYFETWN:
15558 case AArch64::CPYFEWN:
15559 case AArch64::CPYFEWT:
15560 case AArch64::CPYFEWTN:
15561 case AArch64::CPYFEWTRN:
15562 case AArch64::CPYFEWTWN:
15563 case AArch64::CPYFM:
15564 case AArch64::CPYFMN:
15565 case AArch64::CPYFMRN:
15566 case AArch64::CPYFMRT:
15567 case AArch64::CPYFMRTN:
15568 case AArch64::CPYFMRTRN:
15569 case AArch64::CPYFMRTWN:
15570 case AArch64::CPYFMT:
15571 case AArch64::CPYFMTN:
15572 case AArch64::CPYFMTRN:
15573 case AArch64::CPYFMTWN:
15574 case AArch64::CPYFMWN:
15575 case AArch64::CPYFMWT:
15576 case AArch64::CPYFMWTN:
15577 case AArch64::CPYFMWTRN:
15578 case AArch64::CPYFMWTWN:
15579 case AArch64::CPYFP:
15580 case AArch64::CPYFPN:
15581 case AArch64::CPYFPRN:
15582 case AArch64::CPYFPRT:
15583 case AArch64::CPYFPRTN:
15584 case AArch64::CPYFPRTRN:
15585 case AArch64::CPYFPRTWN:
15586 case AArch64::CPYFPT:
15587 case AArch64::CPYFPTN:
15588 case AArch64::CPYFPTRN:
15589 case AArch64::CPYFPTWN:
15590 case AArch64::CPYFPWN:
15591 case AArch64::CPYFPWT:
15592 case AArch64::CPYFPWTN:
15593 case AArch64::CPYFPWTRN:
15594 case AArch64::CPYFPWTWN:
15595 case AArch64::CPYM:
15596 case AArch64::CPYMN:
15597 case AArch64::CPYMRN:
15598 case AArch64::CPYMRT:
15599 case AArch64::CPYMRTN:
15600 case AArch64::CPYMRTRN:
15601 case AArch64::CPYMRTWN:
15602 case AArch64::CPYMT:
15603 case AArch64::CPYMTN:
15604 case AArch64::CPYMTRN:
15605 case AArch64::CPYMTWN:
15606 case AArch64::CPYMWN:
15607 case AArch64::CPYMWT:
15608 case AArch64::CPYMWTN:
15609 case AArch64::CPYMWTRN:
15610 case AArch64::CPYMWTWN:
15611 case AArch64::CPYP:
15612 case AArch64::CPYPN:
15613 case AArch64::CPYPRN:
15614 case AArch64::CPYPRT:
15615 case AArch64::CPYPRTN:
15616 case AArch64::CPYPRTRN:
15617 case AArch64::CPYPRTWN:
15618 case AArch64::CPYPT:
15619 case AArch64::CPYPTN:
15620 case AArch64::CPYPTRN:
15621 case AArch64::CPYPTWN:
15622 case AArch64::CPYPWN:
15623 case AArch64::CPYPWT:
15624 case AArch64::CPYPWTN:
15625 case AArch64::CPYPWTRN:
15626 case AArch64::CPYPWTWN: {
15627 // op: Rd
15628 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15629 op &= UINT64_C(31);
15630 Value |= op;
15631 // op: Rs
15632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15633 op &= UINT64_C(31);
15634 op <<= 16;
15635 Value |= op;
15636 // op: Rn
15637 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
15638 op &= UINT64_C(31);
15639 op <<= 5;
15640 Value |= op;
15641 break;
15642 }
15643 case AArch64::DECP_XP_B:
15644 case AArch64::DECP_XP_D:
15645 case AArch64::DECP_XP_H:
15646 case AArch64::DECP_XP_S:
15647 case AArch64::INCP_XP_B:
15648 case AArch64::INCP_XP_D:
15649 case AArch64::INCP_XP_H:
15650 case AArch64::INCP_XP_S:
15651 case AArch64::SQDECP_XPWd_B:
15652 case AArch64::SQDECP_XPWd_D:
15653 case AArch64::SQDECP_XPWd_H:
15654 case AArch64::SQDECP_XPWd_S:
15655 case AArch64::SQDECP_XP_B:
15656 case AArch64::SQDECP_XP_D:
15657 case AArch64::SQDECP_XP_H:
15658 case AArch64::SQDECP_XP_S:
15659 case AArch64::SQINCP_XPWd_B:
15660 case AArch64::SQINCP_XPWd_D:
15661 case AArch64::SQINCP_XPWd_H:
15662 case AArch64::SQINCP_XPWd_S:
15663 case AArch64::SQINCP_XP_B:
15664 case AArch64::SQINCP_XP_D:
15665 case AArch64::SQINCP_XP_H:
15666 case AArch64::SQINCP_XP_S:
15667 case AArch64::UQDECP_WP_B:
15668 case AArch64::UQDECP_WP_D:
15669 case AArch64::UQDECP_WP_H:
15670 case AArch64::UQDECP_WP_S:
15671 case AArch64::UQDECP_XP_B:
15672 case AArch64::UQDECP_XP_D:
15673 case AArch64::UQDECP_XP_H:
15674 case AArch64::UQDECP_XP_S:
15675 case AArch64::UQINCP_WP_B:
15676 case AArch64::UQINCP_WP_D:
15677 case AArch64::UQINCP_WP_H:
15678 case AArch64::UQINCP_WP_S:
15679 case AArch64::UQINCP_XP_B:
15680 case AArch64::UQINCP_XP_D:
15681 case AArch64::UQINCP_XP_H:
15682 case AArch64::UQINCP_XP_S: {
15683 // op: Rdn
15684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15685 op &= UINT64_C(31);
15686 Value |= op;
15687 // op: Pg
15688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15689 op &= UINT64_C(15);
15690 op <<= 5;
15691 Value |= op;
15692 break;
15693 }
15694 case AArch64::DECB_XPiI:
15695 case AArch64::DECD_XPiI:
15696 case AArch64::DECH_XPiI:
15697 case AArch64::DECW_XPiI:
15698 case AArch64::INCB_XPiI:
15699 case AArch64::INCD_XPiI:
15700 case AArch64::INCH_XPiI:
15701 case AArch64::INCW_XPiI:
15702 case AArch64::SQDECB_XPiI:
15703 case AArch64::SQDECB_XPiWdI:
15704 case AArch64::SQDECD_XPiI:
15705 case AArch64::SQDECD_XPiWdI:
15706 case AArch64::SQDECH_XPiI:
15707 case AArch64::SQDECH_XPiWdI:
15708 case AArch64::SQDECW_XPiI:
15709 case AArch64::SQDECW_XPiWdI:
15710 case AArch64::SQINCB_XPiI:
15711 case AArch64::SQINCB_XPiWdI:
15712 case AArch64::SQINCD_XPiI:
15713 case AArch64::SQINCD_XPiWdI:
15714 case AArch64::SQINCH_XPiI:
15715 case AArch64::SQINCH_XPiWdI:
15716 case AArch64::SQINCW_XPiI:
15717 case AArch64::SQINCW_XPiWdI:
15718 case AArch64::UQDECB_WPiI:
15719 case AArch64::UQDECB_XPiI:
15720 case AArch64::UQDECD_WPiI:
15721 case AArch64::UQDECD_XPiI:
15722 case AArch64::UQDECH_WPiI:
15723 case AArch64::UQDECH_XPiI:
15724 case AArch64::UQDECW_WPiI:
15725 case AArch64::UQDECW_XPiI:
15726 case AArch64::UQINCB_WPiI:
15727 case AArch64::UQINCB_XPiI:
15728 case AArch64::UQINCD_WPiI:
15729 case AArch64::UQINCD_XPiI:
15730 case AArch64::UQINCH_WPiI:
15731 case AArch64::UQINCH_XPiI:
15732 case AArch64::UQINCW_WPiI:
15733 case AArch64::UQINCW_XPiI: {
15734 // op: Rdn
15735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15736 op &= UINT64_C(31);
15737 Value |= op;
15738 // op: pattern
15739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15740 op &= UINT64_C(31);
15741 op <<= 5;
15742 Value |= op;
15743 // op: imm4
15744 op = getSVEIncDecImm(MI, OpIdx: 3, Fixups, STI);
15745 op &= UINT64_C(15);
15746 op <<= 16;
15747 Value |= op;
15748 break;
15749 }
15750 case AArch64::RETAASPPCr:
15751 case AArch64::RETABSPPCr: {
15752 // op: Rm
15753 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15754 op &= UINT64_C(31);
15755 Value |= op;
15756 break;
15757 }
15758 case AArch64::CTERMEQ_WW:
15759 case AArch64::CTERMEQ_XX:
15760 case AArch64::CTERMNE_WW:
15761 case AArch64::CTERMNE_XX:
15762 case AArch64::FCMPDrr:
15763 case AArch64::FCMPEDrr:
15764 case AArch64::FCMPEHrr:
15765 case AArch64::FCMPESrr:
15766 case AArch64::FCMPHrr:
15767 case AArch64::FCMPSrr: {
15768 // op: Rm
15769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15770 op &= UINT64_C(31);
15771 op <<= 16;
15772 Value |= op;
15773 // op: Rn
15774 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15775 op &= UINT64_C(31);
15776 op <<= 5;
15777 Value |= op;
15778 break;
15779 }
15780 case AArch64::CBBEQWrr:
15781 case AArch64::CBBGEWrr:
15782 case AArch64::CBBGTWrr:
15783 case AArch64::CBBHIWrr:
15784 case AArch64::CBBHSWrr:
15785 case AArch64::CBBNEWrr:
15786 case AArch64::CBEQWrr:
15787 case AArch64::CBEQXrr:
15788 case AArch64::CBGEWrr:
15789 case AArch64::CBGEXrr:
15790 case AArch64::CBGTWrr:
15791 case AArch64::CBGTXrr:
15792 case AArch64::CBHEQWrr:
15793 case AArch64::CBHGEWrr:
15794 case AArch64::CBHGTWrr:
15795 case AArch64::CBHHIWrr:
15796 case AArch64::CBHHSWrr:
15797 case AArch64::CBHIWrr:
15798 case AArch64::CBHIXrr:
15799 case AArch64::CBHNEWrr:
15800 case AArch64::CBHSWrr:
15801 case AArch64::CBHSXrr:
15802 case AArch64::CBNEWrr:
15803 case AArch64::CBNEXrr: {
15804 // op: Rm
15805 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15806 op &= UINT64_C(31);
15807 op <<= 16;
15808 Value |= op;
15809 // op: Rt
15810 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15811 op &= UINT64_C(31);
15812 Value |= op;
15813 // op: target
15814 op = getCondCompBranchTargetOpValue(MI, OpIdx: 2, Fixups, STI);
15815 op &= UINT64_C(511);
15816 op <<= 5;
15817 Value |= op;
15818 break;
15819 }
15820 case AArch64::INDEX_IR_B:
15821 case AArch64::INDEX_IR_D:
15822 case AArch64::INDEX_IR_H:
15823 case AArch64::INDEX_IR_S: {
15824 // op: Rm
15825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15826 op &= UINT64_C(31);
15827 op <<= 16;
15828 Value |= op;
15829 // op: Zd
15830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15831 op &= UINT64_C(31);
15832 Value |= op;
15833 // op: imm5
15834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15835 op &= UINT64_C(31);
15836 op <<= 5;
15837 Value |= op;
15838 break;
15839 }
15840 case AArch64::INSR_ZR_B:
15841 case AArch64::INSR_ZR_D:
15842 case AArch64::INSR_ZR_H:
15843 case AArch64::INSR_ZR_S: {
15844 // op: Rm
15845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15846 op &= UINT64_C(31);
15847 op <<= 5;
15848 Value |= op;
15849 // op: Zdn
15850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15851 op &= UINT64_C(31);
15852 Value |= op;
15853 break;
15854 }
15855 case AArch64::LD1B_2Z_STRIDED:
15856 case AArch64::LD1D_2Z_STRIDED:
15857 case AArch64::LD1H_2Z_STRIDED:
15858 case AArch64::LD1W_2Z_STRIDED:
15859 case AArch64::LDNT1B_2Z_STRIDED:
15860 case AArch64::LDNT1D_2Z_STRIDED:
15861 case AArch64::LDNT1H_2Z_STRIDED:
15862 case AArch64::LDNT1W_2Z_STRIDED:
15863 case AArch64::ST1B_2Z_STRIDED:
15864 case AArch64::ST1D_2Z_STRIDED:
15865 case AArch64::ST1H_2Z_STRIDED:
15866 case AArch64::ST1W_2Z_STRIDED:
15867 case AArch64::STNT1B_2Z_STRIDED:
15868 case AArch64::STNT1D_2Z_STRIDED:
15869 case AArch64::STNT1H_2Z_STRIDED:
15870 case AArch64::STNT1W_2Z_STRIDED: {
15871 // op: Rm
15872 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15873 op &= UINT64_C(31);
15874 op <<= 16;
15875 Value |= op;
15876 // op: PNg
15877 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
15878 op &= UINT64_C(7);
15879 op <<= 10;
15880 Value |= op;
15881 // op: Rn
15882 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15883 op &= UINT64_C(31);
15884 op <<= 5;
15885 Value |= op;
15886 // op: Zt
15887 op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
15888 Value |= (op & UINT64_C(8)) << 1;
15889 Value |= (op & UINT64_C(7));
15890 break;
15891 }
15892 case AArch64::LD1B_4Z_STRIDED:
15893 case AArch64::LD1D_4Z_STRIDED:
15894 case AArch64::LD1H_4Z_STRIDED:
15895 case AArch64::LD1W_4Z_STRIDED:
15896 case AArch64::LDNT1B_4Z_STRIDED:
15897 case AArch64::LDNT1D_4Z_STRIDED:
15898 case AArch64::LDNT1H_4Z_STRIDED:
15899 case AArch64::LDNT1W_4Z_STRIDED:
15900 case AArch64::ST1B_4Z_STRIDED:
15901 case AArch64::ST1D_4Z_STRIDED:
15902 case AArch64::ST1H_4Z_STRIDED:
15903 case AArch64::ST1W_4Z_STRIDED:
15904 case AArch64::STNT1B_4Z_STRIDED:
15905 case AArch64::STNT1D_4Z_STRIDED:
15906 case AArch64::STNT1H_4Z_STRIDED:
15907 case AArch64::STNT1W_4Z_STRIDED: {
15908 // op: Rm
15909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15910 op &= UINT64_C(31);
15911 op <<= 16;
15912 Value |= op;
15913 // op: PNg
15914 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
15915 op &= UINT64_C(7);
15916 op <<= 10;
15917 Value |= op;
15918 // op: Rn
15919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15920 op &= UINT64_C(31);
15921 op <<= 5;
15922 Value |= op;
15923 // op: Zt
15924 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
15925 Value |= (op & UINT64_C(4)) << 2;
15926 Value |= (op & UINT64_C(3));
15927 break;
15928 }
15929 case AArch64::PRFB_PRR:
15930 case AArch64::PRFD_PRR:
15931 case AArch64::PRFH_PRR:
15932 case AArch64::PRFW_PRR: {
15933 // op: Rm
15934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15935 op &= UINT64_C(31);
15936 op <<= 16;
15937 Value |= op;
15938 // op: Rn
15939 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15940 op &= UINT64_C(31);
15941 op <<= 5;
15942 Value |= op;
15943 // op: Pg
15944 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15945 op &= UINT64_C(7);
15946 op <<= 10;
15947 Value |= op;
15948 // op: prfop
15949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15950 op &= UINT64_C(15);
15951 Value |= op;
15952 break;
15953 }
15954 case AArch64::LD1_MXIPXX_H_H:
15955 case AArch64::LD1_MXIPXX_V_H:
15956 case AArch64::ST1_MXIPXX_H_H:
15957 case AArch64::ST1_MXIPXX_V_H: {
15958 // op: Rm
15959 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
15960 op &= UINT64_C(31);
15961 op <<= 16;
15962 Value |= op;
15963 // op: Rv
15964 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
15965 op &= UINT64_C(3);
15966 op <<= 13;
15967 Value |= op;
15968 // op: Pg
15969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15970 op &= UINT64_C(7);
15971 op <<= 10;
15972 Value |= op;
15973 // op: Rn
15974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15975 op &= UINT64_C(31);
15976 op <<= 5;
15977 Value |= op;
15978 // op: ZAt
15979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15980 op &= UINT64_C(1);
15981 op <<= 3;
15982 Value |= op;
15983 // op: imm
15984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15985 op &= UINT64_C(7);
15986 Value |= op;
15987 break;
15988 }
15989 case AArch64::LD1_MXIPXX_H_Q:
15990 case AArch64::LD1_MXIPXX_V_Q:
15991 case AArch64::ST1_MXIPXX_H_Q:
15992 case AArch64::ST1_MXIPXX_V_Q: {
15993 // op: Rm
15994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
15995 op &= UINT64_C(31);
15996 op <<= 16;
15997 Value |= op;
15998 // op: Rv
15999 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
16000 op &= UINT64_C(3);
16001 op <<= 13;
16002 Value |= op;
16003 // op: Pg
16004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16005 op &= UINT64_C(7);
16006 op <<= 10;
16007 Value |= op;
16008 // op: Rn
16009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16010 op &= UINT64_C(31);
16011 op <<= 5;
16012 Value |= op;
16013 // op: ZAt
16014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16015 op &= UINT64_C(15);
16016 Value |= op;
16017 break;
16018 }
16019 case AArch64::LD1_MXIPXX_H_S:
16020 case AArch64::LD1_MXIPXX_V_S:
16021 case AArch64::ST1_MXIPXX_H_S:
16022 case AArch64::ST1_MXIPXX_V_S: {
16023 // op: Rm
16024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16025 op &= UINT64_C(31);
16026 op <<= 16;
16027 Value |= op;
16028 // op: Rv
16029 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
16030 op &= UINT64_C(3);
16031 op <<= 13;
16032 Value |= op;
16033 // op: Pg
16034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16035 op &= UINT64_C(7);
16036 op <<= 10;
16037 Value |= op;
16038 // op: Rn
16039 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16040 op &= UINT64_C(31);
16041 op <<= 5;
16042 Value |= op;
16043 // op: ZAt
16044 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16045 op &= UINT64_C(3);
16046 op <<= 2;
16047 Value |= op;
16048 // op: imm
16049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16050 op &= UINT64_C(3);
16051 Value |= op;
16052 break;
16053 }
16054 case AArch64::LD1_MXIPXX_H_D:
16055 case AArch64::LD1_MXIPXX_V_D:
16056 case AArch64::ST1_MXIPXX_H_D:
16057 case AArch64::ST1_MXIPXX_V_D: {
16058 // op: Rm
16059 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16060 op &= UINT64_C(31);
16061 op <<= 16;
16062 Value |= op;
16063 // op: Rv
16064 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
16065 op &= UINT64_C(3);
16066 op <<= 13;
16067 Value |= op;
16068 // op: Pg
16069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16070 op &= UINT64_C(7);
16071 op <<= 10;
16072 Value |= op;
16073 // op: Rn
16074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16075 op &= UINT64_C(31);
16076 op <<= 5;
16077 Value |= op;
16078 // op: ZAt
16079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16080 op &= UINT64_C(7);
16081 op <<= 1;
16082 Value |= op;
16083 // op: imm
16084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16085 op &= UINT64_C(1);
16086 Value |= op;
16087 break;
16088 }
16089 case AArch64::LD1_MXIPXX_H_B:
16090 case AArch64::LD1_MXIPXX_V_B:
16091 case AArch64::ST1_MXIPXX_H_B:
16092 case AArch64::ST1_MXIPXX_V_B: {
16093 // op: Rm
16094 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16095 op &= UINT64_C(31);
16096 op <<= 16;
16097 Value |= op;
16098 // op: Rv
16099 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
16100 op &= UINT64_C(3);
16101 op <<= 13;
16102 Value |= op;
16103 // op: Pg
16104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16105 op &= UINT64_C(7);
16106 op <<= 10;
16107 Value |= op;
16108 // op: Rn
16109 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16110 op &= UINT64_C(31);
16111 op <<= 5;
16112 Value |= op;
16113 // op: imm
16114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16115 op &= UINT64_C(15);
16116 Value |= op;
16117 break;
16118 }
16119 case AArch64::AUTIASPPCr:
16120 case AArch64::AUTIBSPPCr:
16121 case AArch64::BLR:
16122 case AArch64::BLRAAZ:
16123 case AArch64::BLRABZ:
16124 case AArch64::BR:
16125 case AArch64::BRAAZ:
16126 case AArch64::BRABZ:
16127 case AArch64::RET:
16128 case AArch64::SETF8:
16129 case AArch64::SETF16: {
16130 // op: Rn
16131 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16132 op &= UINT64_C(31);
16133 op <<= 5;
16134 Value |= op;
16135 break;
16136 }
16137 case AArch64::BLRAA:
16138 case AArch64::BLRAB:
16139 case AArch64::BRAA:
16140 case AArch64::BRAB: {
16141 // op: Rn
16142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16143 op &= UINT64_C(31);
16144 op <<= 5;
16145 Value |= op;
16146 // op: Rm
16147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16148 op &= UINT64_C(31);
16149 Value |= op;
16150 break;
16151 }
16152 case AArch64::CCMNWr:
16153 case AArch64::CCMNXr:
16154 case AArch64::CCMPWr:
16155 case AArch64::CCMPXr:
16156 case AArch64::FCCMPDrr:
16157 case AArch64::FCCMPEDrr:
16158 case AArch64::FCCMPEHrr:
16159 case AArch64::FCCMPESrr:
16160 case AArch64::FCCMPHrr:
16161 case AArch64::FCCMPSrr: {
16162 // op: Rn
16163 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16164 op &= UINT64_C(31);
16165 op <<= 5;
16166 Value |= op;
16167 // op: Rm
16168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16169 op &= UINT64_C(31);
16170 op <<= 16;
16171 Value |= op;
16172 // op: nzcv
16173 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16174 op &= UINT64_C(15);
16175 Value |= op;
16176 // op: cond
16177 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16178 op &= UINT64_C(15);
16179 op <<= 12;
16180 Value |= op;
16181 break;
16182 }
16183 case AArch64::CCMNWi:
16184 case AArch64::CCMNXi:
16185 case AArch64::CCMPWi:
16186 case AArch64::CCMPXi: {
16187 // op: Rn
16188 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16189 op &= UINT64_C(31);
16190 op <<= 5;
16191 Value |= op;
16192 // op: imm
16193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16194 op &= UINT64_C(31);
16195 op <<= 16;
16196 Value |= op;
16197 // op: nzcv
16198 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16199 op &= UINT64_C(15);
16200 Value |= op;
16201 // op: cond
16202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16203 op &= UINT64_C(15);
16204 op <<= 12;
16205 Value |= op;
16206 break;
16207 }
16208 case AArch64::RMIF: {
16209 // op: Rn
16210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16211 op &= UINT64_C(31);
16212 op <<= 5;
16213 Value |= op;
16214 // op: imm
16215 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16216 op &= UINT64_C(63);
16217 op <<= 15;
16218 Value |= op;
16219 // op: mask
16220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16221 op &= UINT64_C(15);
16222 Value |= op;
16223 break;
16224 }
16225 case AArch64::FCMPDri:
16226 case AArch64::FCMPEDri:
16227 case AArch64::FCMPEHri:
16228 case AArch64::FCMPESri:
16229 case AArch64::FCMPHri:
16230 case AArch64::FCMPSri: {
16231 // op: Rn
16232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16233 op &= UINT64_C(31);
16234 op <<= 5;
16235 Value |= op;
16236 Value = fixOneOperandFPComparison(MI, EncodedValue: Value, STI);
16237 break;
16238 }
16239 case AArch64::LDR_TX:
16240 case AArch64::STR_TX: {
16241 // op: Rn
16242 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16243 op &= UINT64_C(31);
16244 op <<= 5;
16245 Value |= op;
16246 break;
16247 }
16248 case AArch64::LDAPRB:
16249 case AArch64::LDAPRH:
16250 case AArch64::LDAPRW:
16251 case AArch64::LDAPRX:
16252 case AArch64::LDGM:
16253 case AArch64::STGM:
16254 case AArch64::STZGM: {
16255 // op: Rn
16256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16257 op &= UINT64_C(31);
16258 op <<= 5;
16259 Value |= op;
16260 // op: Rt
16261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16262 op &= UINT64_C(31);
16263 Value |= op;
16264 break;
16265 }
16266 case AArch64::ST2Gi:
16267 case AArch64::STGi:
16268 case AArch64::STZ2Gi:
16269 case AArch64::STZGi: {
16270 // op: Rn
16271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16272 op &= UINT64_C(31);
16273 op <<= 5;
16274 Value |= op;
16275 // op: Rt
16276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16277 op &= UINT64_C(31);
16278 Value |= op;
16279 // op: offset
16280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16281 op &= UINT64_C(511);
16282 op <<= 12;
16283 Value |= op;
16284 break;
16285 }
16286 case AArch64::DUP_ZR_B:
16287 case AArch64::DUP_ZR_D:
16288 case AArch64::DUP_ZR_H:
16289 case AArch64::DUP_ZR_S: {
16290 // op: Rn
16291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16292 op &= UINT64_C(31);
16293 op <<= 5;
16294 Value |= op;
16295 // op: Zd
16296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16297 op &= UINT64_C(31);
16298 Value |= op;
16299 break;
16300 }
16301 case AArch64::INDEX_RI_B:
16302 case AArch64::INDEX_RI_D:
16303 case AArch64::INDEX_RI_H:
16304 case AArch64::INDEX_RI_S: {
16305 // op: Rn
16306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16307 op &= UINT64_C(31);
16308 op <<= 5;
16309 Value |= op;
16310 // op: Zd
16311 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16312 op &= UINT64_C(31);
16313 Value |= op;
16314 // op: imm5
16315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16316 op &= UINT64_C(31);
16317 op <<= 16;
16318 Value |= op;
16319 break;
16320 }
16321 case AArch64::LDR_ZXI:
16322 case AArch64::STR_ZXI: {
16323 // op: Rn
16324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16325 op &= UINT64_C(31);
16326 op <<= 5;
16327 Value |= op;
16328 // op: Zt
16329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16330 op &= UINT64_C(31);
16331 Value |= op;
16332 // op: imm9
16333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16334 Value |= (op & UINT64_C(504)) << 13;
16335 Value |= (op & UINT64_C(7)) << 10;
16336 break;
16337 }
16338 case AArch64::PRFB_PRI:
16339 case AArch64::PRFD_PRI:
16340 case AArch64::PRFH_PRI:
16341 case AArch64::PRFW_PRI: {
16342 // op: Rn
16343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16344 op &= UINT64_C(31);
16345 op <<= 5;
16346 Value |= op;
16347 // op: Pg
16348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16349 op &= UINT64_C(7);
16350 op <<= 10;
16351 Value |= op;
16352 // op: imm6
16353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16354 op &= UINT64_C(63);
16355 op <<= 16;
16356 Value |= op;
16357 // op: prfop
16358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16359 op &= UINT64_C(15);
16360 Value |= op;
16361 break;
16362 }
16363 case AArch64::LDG:
16364 case AArch64::ST2GPostIndex:
16365 case AArch64::ST2GPreIndex:
16366 case AArch64::STGPostIndex:
16367 case AArch64::STGPreIndex:
16368 case AArch64::STZ2GPostIndex:
16369 case AArch64::STZ2GPreIndex:
16370 case AArch64::STZGPostIndex:
16371 case AArch64::STZGPreIndex: {
16372 // op: Rn
16373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16374 op &= UINT64_C(31);
16375 op <<= 5;
16376 Value |= op;
16377 // op: Rt
16378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16379 op &= UINT64_C(31);
16380 Value |= op;
16381 // op: offset
16382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16383 op &= UINT64_C(511);
16384 op <<= 12;
16385 Value |= op;
16386 break;
16387 }
16388 case AArch64::MOVA_MXI2Z_H_H:
16389 case AArch64::MOVA_MXI2Z_V_H: {
16390 // op: Rs
16391 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16392 op &= UINT64_C(3);
16393 op <<= 13;
16394 Value |= op;
16395 // op: Zn
16396 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
16397 op &= UINT64_C(15);
16398 op <<= 6;
16399 Value |= op;
16400 // op: ZAd
16401 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16402 op &= UINT64_C(1);
16403 op <<= 2;
16404 Value |= op;
16405 // op: imm
16406 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16407 op &= UINT64_C(3);
16408 Value |= op;
16409 break;
16410 }
16411 case AArch64::MOVA_MXI2Z_H_S:
16412 case AArch64::MOVA_MXI2Z_V_S: {
16413 // op: Rs
16414 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16415 op &= UINT64_C(3);
16416 op <<= 13;
16417 Value |= op;
16418 // op: Zn
16419 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
16420 op &= UINT64_C(15);
16421 op <<= 6;
16422 Value |= op;
16423 // op: ZAd
16424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16425 op &= UINT64_C(3);
16426 op <<= 1;
16427 Value |= op;
16428 // op: imm
16429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16430 op &= UINT64_C(1);
16431 Value |= op;
16432 break;
16433 }
16434 case AArch64::MOVA_MXI2Z_H_D:
16435 case AArch64::MOVA_MXI2Z_V_D: {
16436 // op: Rs
16437 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16438 op &= UINT64_C(3);
16439 op <<= 13;
16440 Value |= op;
16441 // op: Zn
16442 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
16443 op &= UINT64_C(15);
16444 op <<= 6;
16445 Value |= op;
16446 // op: ZAd
16447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16448 op &= UINT64_C(7);
16449 Value |= op;
16450 break;
16451 }
16452 case AArch64::MOVA_MXI2Z_H_B:
16453 case AArch64::MOVA_MXI2Z_V_B: {
16454 // op: Rs
16455 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16456 op &= UINT64_C(3);
16457 op <<= 13;
16458 Value |= op;
16459 // op: Zn
16460 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
16461 op &= UINT64_C(15);
16462 op <<= 6;
16463 Value |= op;
16464 // op: imm
16465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16466 op &= UINT64_C(7);
16467 Value |= op;
16468 break;
16469 }
16470 case AArch64::MOVA_MXI4Z_H_H:
16471 case AArch64::MOVA_MXI4Z_V_H: {
16472 // op: Rs
16473 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16474 op &= UINT64_C(3);
16475 op <<= 13;
16476 Value |= op;
16477 // op: Zn
16478 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
16479 op &= UINT64_C(7);
16480 op <<= 7;
16481 Value |= op;
16482 // op: ZAd
16483 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16484 op &= UINT64_C(1);
16485 op <<= 1;
16486 Value |= op;
16487 // op: imm
16488 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16489 op &= UINT64_C(1);
16490 Value |= op;
16491 break;
16492 }
16493 case AArch64::MOVA_MXI4Z_H_S:
16494 case AArch64::MOVA_MXI4Z_V_S: {
16495 // op: Rs
16496 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16497 op &= UINT64_C(3);
16498 op <<= 13;
16499 Value |= op;
16500 // op: Zn
16501 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
16502 op &= UINT64_C(7);
16503 op <<= 7;
16504 Value |= op;
16505 // op: ZAd
16506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16507 op &= UINT64_C(3);
16508 Value |= op;
16509 break;
16510 }
16511 case AArch64::MOVA_MXI4Z_H_D:
16512 case AArch64::MOVA_MXI4Z_V_D: {
16513 // op: Rs
16514 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16515 op &= UINT64_C(3);
16516 op <<= 13;
16517 Value |= op;
16518 // op: Zn
16519 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
16520 op &= UINT64_C(7);
16521 op <<= 7;
16522 Value |= op;
16523 // op: ZAd
16524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16525 op &= UINT64_C(7);
16526 Value |= op;
16527 break;
16528 }
16529 case AArch64::MOVA_MXI4Z_H_B:
16530 case AArch64::MOVA_MXI4Z_V_B: {
16531 // op: Rs
16532 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16533 op &= UINT64_C(3);
16534 op <<= 13;
16535 Value |= op;
16536 // op: Zn
16537 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
16538 op &= UINT64_C(7);
16539 op <<= 7;
16540 Value |= op;
16541 // op: imm
16542 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16543 op &= UINT64_C(3);
16544 Value |= op;
16545 break;
16546 }
16547 case AArch64::MOVAZ_ZMI_H_H:
16548 case AArch64::MOVAZ_ZMI_V_H: {
16549 // op: Rs
16550 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16551 op &= UINT64_C(3);
16552 op <<= 13;
16553 Value |= op;
16554 // op: Zd
16555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16556 op &= UINT64_C(31);
16557 Value |= op;
16558 // op: ZAn
16559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16560 op &= UINT64_C(1);
16561 op <<= 8;
16562 Value |= op;
16563 // op: imm
16564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16565 op &= UINT64_C(7);
16566 op <<= 5;
16567 Value |= op;
16568 break;
16569 }
16570 case AArch64::MOVAZ_ZMI_H_Q:
16571 case AArch64::MOVAZ_ZMI_V_Q: {
16572 // op: Rs
16573 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16574 op &= UINT64_C(3);
16575 op <<= 13;
16576 Value |= op;
16577 // op: Zd
16578 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16579 op &= UINT64_C(31);
16580 Value |= op;
16581 // op: ZAn
16582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16583 op &= UINT64_C(15);
16584 op <<= 5;
16585 Value |= op;
16586 break;
16587 }
16588 case AArch64::MOVAZ_ZMI_H_S:
16589 case AArch64::MOVAZ_ZMI_V_S: {
16590 // op: Rs
16591 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16592 op &= UINT64_C(3);
16593 op <<= 13;
16594 Value |= op;
16595 // op: Zd
16596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16597 op &= UINT64_C(31);
16598 Value |= op;
16599 // op: ZAn
16600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16601 op &= UINT64_C(3);
16602 op <<= 7;
16603 Value |= op;
16604 // op: imm
16605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16606 op &= UINT64_C(3);
16607 op <<= 5;
16608 Value |= op;
16609 break;
16610 }
16611 case AArch64::MOVAZ_ZMI_H_D:
16612 case AArch64::MOVAZ_ZMI_V_D: {
16613 // op: Rs
16614 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16615 op &= UINT64_C(3);
16616 op <<= 13;
16617 Value |= op;
16618 // op: Zd
16619 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16620 op &= UINT64_C(31);
16621 Value |= op;
16622 // op: ZAn
16623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16624 op &= UINT64_C(7);
16625 op <<= 6;
16626 Value |= op;
16627 // op: imm
16628 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16629 op &= UINT64_C(1);
16630 op <<= 5;
16631 Value |= op;
16632 break;
16633 }
16634 case AArch64::MOVAZ_ZMI_H_B:
16635 case AArch64::MOVAZ_ZMI_V_B: {
16636 // op: Rs
16637 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16638 op &= UINT64_C(3);
16639 op <<= 13;
16640 Value |= op;
16641 // op: Zd
16642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16643 op &= UINT64_C(31);
16644 Value |= op;
16645 // op: imm
16646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16647 op &= UINT64_C(15);
16648 op <<= 5;
16649 Value |= op;
16650 break;
16651 }
16652 case AArch64::MOVA_VG2_MXI2Z: {
16653 // op: Rs
16654 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
16655 op &= UINT64_C(3);
16656 op <<= 13;
16657 Value |= op;
16658 // op: imm
16659 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16660 op &= UINT64_C(7);
16661 Value |= op;
16662 // op: Zn
16663 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
16664 op &= UINT64_C(15);
16665 op <<= 6;
16666 Value |= op;
16667 break;
16668 }
16669 case AArch64::MOVA_VG4_MXI4Z: {
16670 // op: Rs
16671 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
16672 op &= UINT64_C(3);
16673 op <<= 13;
16674 Value |= op;
16675 // op: imm
16676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16677 op &= UINT64_C(7);
16678 Value |= op;
16679 // op: Zn
16680 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
16681 op &= UINT64_C(7);
16682 op <<= 7;
16683 Value |= op;
16684 break;
16685 }
16686 case AArch64::MOVA_VG2_2ZMXI: {
16687 // op: Rs
16688 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
16689 op &= UINT64_C(3);
16690 op <<= 13;
16691 Value |= op;
16692 // op: imm
16693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16694 op &= UINT64_C(7);
16695 op <<= 5;
16696 Value |= op;
16697 // op: Zd
16698 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
16699 op &= UINT64_C(15);
16700 op <<= 1;
16701 Value |= op;
16702 break;
16703 }
16704 case AArch64::MOVA_VG4_4ZMXI: {
16705 // op: Rs
16706 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
16707 op &= UINT64_C(3);
16708 op <<= 13;
16709 Value |= op;
16710 // op: imm
16711 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16712 op &= UINT64_C(7);
16713 op <<= 5;
16714 Value |= op;
16715 // op: Zd
16716 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
16717 op &= UINT64_C(7);
16718 op <<= 2;
16719 Value |= op;
16720 break;
16721 }
16722 case AArch64::MOVAZ_VG2_2ZMXI: {
16723 // op: Rs
16724 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 3, Fixups, STI);
16725 op &= UINT64_C(3);
16726 op <<= 13;
16727 Value |= op;
16728 // op: imm
16729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16730 op &= UINT64_C(7);
16731 op <<= 5;
16732 Value |= op;
16733 // op: Zd
16734 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
16735 op &= UINT64_C(15);
16736 op <<= 1;
16737 Value |= op;
16738 break;
16739 }
16740 case AArch64::MOVAZ_VG4_4ZMXI: {
16741 // op: Rs
16742 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 3, Fixups, STI);
16743 op &= UINT64_C(3);
16744 op <<= 13;
16745 Value |= op;
16746 // op: imm
16747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16748 op &= UINT64_C(7);
16749 op <<= 5;
16750 Value |= op;
16751 // op: Zd
16752 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
16753 op &= UINT64_C(7);
16754 op <<= 2;
16755 Value |= op;
16756 break;
16757 }
16758 case AArch64::STBFADD:
16759 case AArch64::STBFADDL:
16760 case AArch64::STBFMAX:
16761 case AArch64::STBFMAXL:
16762 case AArch64::STBFMAXNM:
16763 case AArch64::STBFMAXNML:
16764 case AArch64::STBFMIN:
16765 case AArch64::STBFMINL:
16766 case AArch64::STBFMINNM:
16767 case AArch64::STBFMINNML:
16768 case AArch64::STFADDD:
16769 case AArch64::STFADDH:
16770 case AArch64::STFADDLD:
16771 case AArch64::STFADDLH:
16772 case AArch64::STFADDLS:
16773 case AArch64::STFADDS:
16774 case AArch64::STFMAXD:
16775 case AArch64::STFMAXH:
16776 case AArch64::STFMAXLD:
16777 case AArch64::STFMAXLH:
16778 case AArch64::STFMAXLS:
16779 case AArch64::STFMAXNMD:
16780 case AArch64::STFMAXNMH:
16781 case AArch64::STFMAXNMLD:
16782 case AArch64::STFMAXNMLH:
16783 case AArch64::STFMAXNMLS:
16784 case AArch64::STFMAXNMS:
16785 case AArch64::STFMAXS:
16786 case AArch64::STFMIND:
16787 case AArch64::STFMINH:
16788 case AArch64::STFMINLD:
16789 case AArch64::STFMINLH:
16790 case AArch64::STFMINLS:
16791 case AArch64::STFMINNMD:
16792 case AArch64::STFMINNMH:
16793 case AArch64::STFMINNMLD:
16794 case AArch64::STFMINNMLH:
16795 case AArch64::STFMINNMLS:
16796 case AArch64::STFMINNMS:
16797 case AArch64::STFMINS: {
16798 // op: Rs
16799 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16800 op &= UINT64_C(31);
16801 op <<= 16;
16802 Value |= op;
16803 // op: Rn
16804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16805 op &= UINT64_C(31);
16806 op <<= 5;
16807 Value |= op;
16808 break;
16809 }
16810 case AArch64::LDADDAB:
16811 case AArch64::LDADDAH:
16812 case AArch64::LDADDALB:
16813 case AArch64::LDADDALH:
16814 case AArch64::LDADDALW:
16815 case AArch64::LDADDALX:
16816 case AArch64::LDADDAW:
16817 case AArch64::LDADDAX:
16818 case AArch64::LDADDB:
16819 case AArch64::LDADDH:
16820 case AArch64::LDADDLB:
16821 case AArch64::LDADDLH:
16822 case AArch64::LDADDLW:
16823 case AArch64::LDADDLX:
16824 case AArch64::LDADDW:
16825 case AArch64::LDADDX:
16826 case AArch64::LDCLRAB:
16827 case AArch64::LDCLRAH:
16828 case AArch64::LDCLRALB:
16829 case AArch64::LDCLRALH:
16830 case AArch64::LDCLRALW:
16831 case AArch64::LDCLRALX:
16832 case AArch64::LDCLRAW:
16833 case AArch64::LDCLRAX:
16834 case AArch64::LDCLRB:
16835 case AArch64::LDCLRH:
16836 case AArch64::LDCLRLB:
16837 case AArch64::LDCLRLH:
16838 case AArch64::LDCLRLW:
16839 case AArch64::LDCLRLX:
16840 case AArch64::LDCLRW:
16841 case AArch64::LDCLRX:
16842 case AArch64::LDEORAB:
16843 case AArch64::LDEORAH:
16844 case AArch64::LDEORALB:
16845 case AArch64::LDEORALH:
16846 case AArch64::LDEORALW:
16847 case AArch64::LDEORALX:
16848 case AArch64::LDEORAW:
16849 case AArch64::LDEORAX:
16850 case AArch64::LDEORB:
16851 case AArch64::LDEORH:
16852 case AArch64::LDEORLB:
16853 case AArch64::LDEORLH:
16854 case AArch64::LDEORLW:
16855 case AArch64::LDEORLX:
16856 case AArch64::LDEORW:
16857 case AArch64::LDEORX:
16858 case AArch64::LDSETAB:
16859 case AArch64::LDSETAH:
16860 case AArch64::LDSETALB:
16861 case AArch64::LDSETALH:
16862 case AArch64::LDSETALW:
16863 case AArch64::LDSETALX:
16864 case AArch64::LDSETAW:
16865 case AArch64::LDSETAX:
16866 case AArch64::LDSETB:
16867 case AArch64::LDSETH:
16868 case AArch64::LDSETLB:
16869 case AArch64::LDSETLH:
16870 case AArch64::LDSETLW:
16871 case AArch64::LDSETLX:
16872 case AArch64::LDSETW:
16873 case AArch64::LDSETX:
16874 case AArch64::LDSMAXAB:
16875 case AArch64::LDSMAXAH:
16876 case AArch64::LDSMAXALB:
16877 case AArch64::LDSMAXALH:
16878 case AArch64::LDSMAXALW:
16879 case AArch64::LDSMAXALX:
16880 case AArch64::LDSMAXAW:
16881 case AArch64::LDSMAXAX:
16882 case AArch64::LDSMAXB:
16883 case AArch64::LDSMAXH:
16884 case AArch64::LDSMAXLB:
16885 case AArch64::LDSMAXLH:
16886 case AArch64::LDSMAXLW:
16887 case AArch64::LDSMAXLX:
16888 case AArch64::LDSMAXW:
16889 case AArch64::LDSMAXX:
16890 case AArch64::LDSMINAB:
16891 case AArch64::LDSMINAH:
16892 case AArch64::LDSMINALB:
16893 case AArch64::LDSMINALH:
16894 case AArch64::LDSMINALW:
16895 case AArch64::LDSMINALX:
16896 case AArch64::LDSMINAW:
16897 case AArch64::LDSMINAX:
16898 case AArch64::LDSMINB:
16899 case AArch64::LDSMINH:
16900 case AArch64::LDSMINLB:
16901 case AArch64::LDSMINLH:
16902 case AArch64::LDSMINLW:
16903 case AArch64::LDSMINLX:
16904 case AArch64::LDSMINW:
16905 case AArch64::LDSMINX:
16906 case AArch64::LDTADDALW:
16907 case AArch64::LDTADDALX:
16908 case AArch64::LDTADDAW:
16909 case AArch64::LDTADDAX:
16910 case AArch64::LDTADDLW:
16911 case AArch64::LDTADDLX:
16912 case AArch64::LDTADDW:
16913 case AArch64::LDTADDX:
16914 case AArch64::LDTCLRALW:
16915 case AArch64::LDTCLRALX:
16916 case AArch64::LDTCLRAW:
16917 case AArch64::LDTCLRAX:
16918 case AArch64::LDTCLRLW:
16919 case AArch64::LDTCLRLX:
16920 case AArch64::LDTCLRW:
16921 case AArch64::LDTCLRX:
16922 case AArch64::LDTSETALW:
16923 case AArch64::LDTSETALX:
16924 case AArch64::LDTSETAW:
16925 case AArch64::LDTSETAX:
16926 case AArch64::LDTSETLW:
16927 case AArch64::LDTSETLX:
16928 case AArch64::LDTSETW:
16929 case AArch64::LDTSETX:
16930 case AArch64::LDUMAXAB:
16931 case AArch64::LDUMAXAH:
16932 case AArch64::LDUMAXALB:
16933 case AArch64::LDUMAXALH:
16934 case AArch64::LDUMAXALW:
16935 case AArch64::LDUMAXALX:
16936 case AArch64::LDUMAXAW:
16937 case AArch64::LDUMAXAX:
16938 case AArch64::LDUMAXB:
16939 case AArch64::LDUMAXH:
16940 case AArch64::LDUMAXLB:
16941 case AArch64::LDUMAXLH:
16942 case AArch64::LDUMAXLW:
16943 case AArch64::LDUMAXLX:
16944 case AArch64::LDUMAXW:
16945 case AArch64::LDUMAXX:
16946 case AArch64::LDUMINAB:
16947 case AArch64::LDUMINAH:
16948 case AArch64::LDUMINALB:
16949 case AArch64::LDUMINALH:
16950 case AArch64::LDUMINALW:
16951 case AArch64::LDUMINALX:
16952 case AArch64::LDUMINAW:
16953 case AArch64::LDUMINAX:
16954 case AArch64::LDUMINB:
16955 case AArch64::LDUMINH:
16956 case AArch64::LDUMINLB:
16957 case AArch64::LDUMINLH:
16958 case AArch64::LDUMINLW:
16959 case AArch64::LDUMINLX:
16960 case AArch64::LDUMINW:
16961 case AArch64::LDUMINX:
16962 case AArch64::RCWCLR:
16963 case AArch64::RCWCLRA:
16964 case AArch64::RCWCLRAL:
16965 case AArch64::RCWCLRL:
16966 case AArch64::RCWCLRS:
16967 case AArch64::RCWCLRSA:
16968 case AArch64::RCWCLRSAL:
16969 case AArch64::RCWCLRSL:
16970 case AArch64::RCWSET:
16971 case AArch64::RCWSETA:
16972 case AArch64::RCWSETAL:
16973 case AArch64::RCWSETL:
16974 case AArch64::RCWSETS:
16975 case AArch64::RCWSETSA:
16976 case AArch64::RCWSETSAL:
16977 case AArch64::RCWSETSL:
16978 case AArch64::RCWSWP:
16979 case AArch64::RCWSWPA:
16980 case AArch64::RCWSWPAL:
16981 case AArch64::RCWSWPL:
16982 case AArch64::RCWSWPS:
16983 case AArch64::RCWSWPSA:
16984 case AArch64::RCWSWPSAL:
16985 case AArch64::RCWSWPSL:
16986 case AArch64::SWPAB:
16987 case AArch64::SWPAH:
16988 case AArch64::SWPALB:
16989 case AArch64::SWPALH:
16990 case AArch64::SWPALW:
16991 case AArch64::SWPALX:
16992 case AArch64::SWPAW:
16993 case AArch64::SWPAX:
16994 case AArch64::SWPB:
16995 case AArch64::SWPH:
16996 case AArch64::SWPLB:
16997 case AArch64::SWPLH:
16998 case AArch64::SWPLW:
16999 case AArch64::SWPLX:
17000 case AArch64::SWPTALW:
17001 case AArch64::SWPTALX:
17002 case AArch64::SWPTAW:
17003 case AArch64::SWPTAX:
17004 case AArch64::SWPTLW:
17005 case AArch64::SWPTLX:
17006 case AArch64::SWPTW:
17007 case AArch64::SWPTX:
17008 case AArch64::SWPW:
17009 case AArch64::SWPX: {
17010 // op: Rs
17011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17012 op &= UINT64_C(31);
17013 op <<= 16;
17014 Value |= op;
17015 // op: Rn
17016 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17017 op &= UINT64_C(31);
17018 op <<= 5;
17019 Value |= op;
17020 // op: Rt
17021 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17022 op &= UINT64_C(31);
17023 Value |= op;
17024 break;
17025 }
17026 case AArch64::CASAB:
17027 case AArch64::CASAH:
17028 case AArch64::CASALB:
17029 case AArch64::CASALH:
17030 case AArch64::CASALTX:
17031 case AArch64::CASALW:
17032 case AArch64::CASALX:
17033 case AArch64::CASATX:
17034 case AArch64::CASAW:
17035 case AArch64::CASAX:
17036 case AArch64::CASB:
17037 case AArch64::CASH:
17038 case AArch64::CASLB:
17039 case AArch64::CASLH:
17040 case AArch64::CASLTX:
17041 case AArch64::CASLW:
17042 case AArch64::CASLX:
17043 case AArch64::CASPALTX:
17044 case AArch64::CASPALW:
17045 case AArch64::CASPALX:
17046 case AArch64::CASPATX:
17047 case AArch64::CASPAW:
17048 case AArch64::CASPAX:
17049 case AArch64::CASPLTX:
17050 case AArch64::CASPLW:
17051 case AArch64::CASPLX:
17052 case AArch64::CASPTX:
17053 case AArch64::CASPW:
17054 case AArch64::CASPX:
17055 case AArch64::CASTX:
17056 case AArch64::CASW:
17057 case AArch64::CASX:
17058 case AArch64::RCWCAS:
17059 case AArch64::RCWCASA:
17060 case AArch64::RCWCASAL:
17061 case AArch64::RCWCASL:
17062 case AArch64::RCWCASP:
17063 case AArch64::RCWCASPA:
17064 case AArch64::RCWCASPAL:
17065 case AArch64::RCWCASPL:
17066 case AArch64::RCWSCAS:
17067 case AArch64::RCWSCASA:
17068 case AArch64::RCWSCASAL:
17069 case AArch64::RCWSCASL:
17070 case AArch64::RCWSCASP:
17071 case AArch64::RCWSCASPA:
17072 case AArch64::RCWSCASPAL:
17073 case AArch64::RCWSCASPL: {
17074 // op: Rs
17075 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17076 op &= UINT64_C(31);
17077 op <<= 16;
17078 Value |= op;
17079 // op: Rn
17080 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17081 op &= UINT64_C(31);
17082 op <<= 5;
17083 Value |= op;
17084 // op: Rt
17085 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17086 op &= UINT64_C(31);
17087 Value |= op;
17088 break;
17089 }
17090 case AArch64::RPRFM: {
17091 // op: Rt
17092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17093 Value |= (op & UINT64_C(32)) << 10;
17094 Value |= (op & UINT64_C(24)) << 9;
17095 Value |= (op & UINT64_C(7));
17096 // op: Rn
17097 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17098 op &= UINT64_C(31);
17099 op <<= 5;
17100 Value |= op;
17101 // op: Rm
17102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17103 op &= UINT64_C(31);
17104 op <<= 16;
17105 Value |= op;
17106 break;
17107 }
17108 case AArch64::GCSPOPM:
17109 case AArch64::GCSPUSHM:
17110 case AArch64::GCSSS1:
17111 case AArch64::GCSSS2:
17112 case AArch64::TRCIT:
17113 case AArch64::TSTART:
17114 case AArch64::TTEST:
17115 case AArch64::WFET:
17116 case AArch64::WFIT: {
17117 // op: Rt
17118 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17119 op &= UINT64_C(31);
17120 Value |= op;
17121 break;
17122 }
17123 case AArch64::GCSSTR:
17124 case AArch64::GCSSTTR:
17125 case AArch64::LD64B:
17126 case AArch64::ST64B: {
17127 // op: Rt
17128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17129 op &= UINT64_C(31);
17130 Value |= op;
17131 // op: Rn
17132 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17133 op &= UINT64_C(31);
17134 op <<= 5;
17135 Value |= op;
17136 break;
17137 }
17138 case AArch64::LDRBBroW:
17139 case AArch64::LDRBBroX:
17140 case AArch64::LDRBroW:
17141 case AArch64::LDRBroX:
17142 case AArch64::LDRDroW:
17143 case AArch64::LDRDroX:
17144 case AArch64::LDRHHroW:
17145 case AArch64::LDRHHroX:
17146 case AArch64::LDRHroW:
17147 case AArch64::LDRHroX:
17148 case AArch64::LDRQroW:
17149 case AArch64::LDRQroX:
17150 case AArch64::LDRSBWroW:
17151 case AArch64::LDRSBWroX:
17152 case AArch64::LDRSBXroW:
17153 case AArch64::LDRSBXroX:
17154 case AArch64::LDRSHWroW:
17155 case AArch64::LDRSHWroX:
17156 case AArch64::LDRSHXroW:
17157 case AArch64::LDRSHXroX:
17158 case AArch64::LDRSWroW:
17159 case AArch64::LDRSWroX:
17160 case AArch64::LDRSroW:
17161 case AArch64::LDRSroX:
17162 case AArch64::LDRWroW:
17163 case AArch64::LDRWroX:
17164 case AArch64::LDRXroW:
17165 case AArch64::LDRXroX:
17166 case AArch64::PRFMroW:
17167 case AArch64::PRFMroX:
17168 case AArch64::STRBBroW:
17169 case AArch64::STRBBroX:
17170 case AArch64::STRBroW:
17171 case AArch64::STRBroX:
17172 case AArch64::STRDroW:
17173 case AArch64::STRDroX:
17174 case AArch64::STRHHroW:
17175 case AArch64::STRHHroX:
17176 case AArch64::STRHroW:
17177 case AArch64::STRHroX:
17178 case AArch64::STRQroW:
17179 case AArch64::STRQroX:
17180 case AArch64::STRSroW:
17181 case AArch64::STRSroX:
17182 case AArch64::STRWroW:
17183 case AArch64::STRWroX:
17184 case AArch64::STRXroW:
17185 case AArch64::STRXroX: {
17186 // op: Rt
17187 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17188 op &= UINT64_C(31);
17189 Value |= op;
17190 // op: Rn
17191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17192 op &= UINT64_C(31);
17193 op <<= 5;
17194 Value |= op;
17195 // op: Rm
17196 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17197 op &= UINT64_C(31);
17198 op <<= 16;
17199 Value |= op;
17200 // op: extend
17201 op = getMemExtendOpValue(MI, OpIdx: 3, Fixups, STI);
17202 Value |= (op & UINT64_C(2)) << 14;
17203 Value |= (op & UINT64_C(1)) << 12;
17204 break;
17205 }
17206 case AArch64::LDRQui:
17207 case AArch64::STRQui: {
17208 // op: Rt
17209 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17210 op &= UINT64_C(31);
17211 Value |= op;
17212 // op: Rn
17213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17214 op &= UINT64_C(31);
17215 op <<= 5;
17216 Value |= op;
17217 // op: offset
17218 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale16>(MI, OpIdx: 2, Fixups, STI);
17219 op &= UINT64_C(4095);
17220 op <<= 10;
17221 Value |= op;
17222 break;
17223 }
17224 case AArch64::LDRBBui:
17225 case AArch64::LDRBui:
17226 case AArch64::LDRSBWui:
17227 case AArch64::LDRSBXui:
17228 case AArch64::STRBBui:
17229 case AArch64::STRBui: {
17230 // op: Rt
17231 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17232 op &= UINT64_C(31);
17233 Value |= op;
17234 // op: Rn
17235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17236 op &= UINT64_C(31);
17237 op <<= 5;
17238 Value |= op;
17239 // op: offset
17240 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale1>(MI, OpIdx: 2, Fixups, STI);
17241 op &= UINT64_C(4095);
17242 op <<= 10;
17243 Value |= op;
17244 break;
17245 }
17246 case AArch64::LDRHHui:
17247 case AArch64::LDRHui:
17248 case AArch64::LDRSHWui:
17249 case AArch64::LDRSHXui:
17250 case AArch64::STRHHui:
17251 case AArch64::STRHui: {
17252 // op: Rt
17253 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17254 op &= UINT64_C(31);
17255 Value |= op;
17256 // op: Rn
17257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17258 op &= UINT64_C(31);
17259 op <<= 5;
17260 Value |= op;
17261 // op: offset
17262 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale2>(MI, OpIdx: 2, Fixups, STI);
17263 op &= UINT64_C(4095);
17264 op <<= 10;
17265 Value |= op;
17266 break;
17267 }
17268 case AArch64::LDRSWui:
17269 case AArch64::LDRSui:
17270 case AArch64::LDRWui:
17271 case AArch64::STRSui:
17272 case AArch64::STRWui: {
17273 // op: Rt
17274 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17275 op &= UINT64_C(31);
17276 Value |= op;
17277 // op: Rn
17278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17279 op &= UINT64_C(31);
17280 op <<= 5;
17281 Value |= op;
17282 // op: offset
17283 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale4>(MI, OpIdx: 2, Fixups, STI);
17284 op &= UINT64_C(4095);
17285 op <<= 10;
17286 Value |= op;
17287 break;
17288 }
17289 case AArch64::LDRDui:
17290 case AArch64::LDRXui:
17291 case AArch64::PRFMui:
17292 case AArch64::STRDui:
17293 case AArch64::STRXui: {
17294 // op: Rt
17295 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17296 op &= UINT64_C(31);
17297 Value |= op;
17298 // op: Rn
17299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17300 op &= UINT64_C(31);
17301 op <<= 5;
17302 Value |= op;
17303 // op: offset
17304 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale8>(MI, OpIdx: 2, Fixups, STI);
17305 op &= UINT64_C(4095);
17306 op <<= 10;
17307 Value |= op;
17308 break;
17309 }
17310 case AArch64::LDAPURBi:
17311 case AArch64::LDAPURHi:
17312 case AArch64::LDAPURSBWi:
17313 case AArch64::LDAPURSBXi:
17314 case AArch64::LDAPURSHWi:
17315 case AArch64::LDAPURSHXi:
17316 case AArch64::LDAPURSWi:
17317 case AArch64::LDAPURXi:
17318 case AArch64::LDAPURi:
17319 case AArch64::LDTRBi:
17320 case AArch64::LDTRHi:
17321 case AArch64::LDTRSBWi:
17322 case AArch64::LDTRSBXi:
17323 case AArch64::LDTRSHWi:
17324 case AArch64::LDTRSHXi:
17325 case AArch64::LDTRSWi:
17326 case AArch64::LDTRWi:
17327 case AArch64::LDTRXi:
17328 case AArch64::LDURBBi:
17329 case AArch64::LDURBi:
17330 case AArch64::LDURDi:
17331 case AArch64::LDURHHi:
17332 case AArch64::LDURHi:
17333 case AArch64::LDURQi:
17334 case AArch64::LDURSBWi:
17335 case AArch64::LDURSBXi:
17336 case AArch64::LDURSHWi:
17337 case AArch64::LDURSHXi:
17338 case AArch64::LDURSWi:
17339 case AArch64::LDURSi:
17340 case AArch64::LDURWi:
17341 case AArch64::LDURXi:
17342 case AArch64::PRFUMi:
17343 case AArch64::STLURBi:
17344 case AArch64::STLURHi:
17345 case AArch64::STLURWi:
17346 case AArch64::STLURXi:
17347 case AArch64::STTRBi:
17348 case AArch64::STTRHi:
17349 case AArch64::STTRWi:
17350 case AArch64::STTRXi:
17351 case AArch64::STURBBi:
17352 case AArch64::STURBi:
17353 case AArch64::STURDi:
17354 case AArch64::STURHHi:
17355 case AArch64::STURHi:
17356 case AArch64::STURQi:
17357 case AArch64::STURSi:
17358 case AArch64::STURWi:
17359 case AArch64::STURXi: {
17360 // op: Rt
17361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17362 op &= UINT64_C(31);
17363 Value |= op;
17364 // op: Rn
17365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17366 op &= UINT64_C(31);
17367 op <<= 5;
17368 Value |= op;
17369 // op: offset
17370 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17371 op &= UINT64_C(511);
17372 op <<= 12;
17373 Value |= op;
17374 break;
17375 }
17376 case AArch64::LDAPURbi:
17377 case AArch64::LDAPURdi:
17378 case AArch64::LDAPURhi:
17379 case AArch64::LDAPURqi:
17380 case AArch64::LDAPURsi:
17381 case AArch64::STLURbi:
17382 case AArch64::STLURdi:
17383 case AArch64::STLURhi:
17384 case AArch64::STLURqi:
17385 case AArch64::STLURsi: {
17386 // op: Rt
17387 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17388 op &= UINT64_C(31);
17389 Value |= op;
17390 // op: Rn
17391 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17392 op &= UINT64_C(31);
17393 op <<= 5;
17394 Value |= op;
17395 // op: simm
17396 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17397 op &= UINT64_C(511);
17398 op <<= 12;
17399 Value |= op;
17400 break;
17401 }
17402 case AArch64::LDARB:
17403 case AArch64::LDARH:
17404 case AArch64::LDARW:
17405 case AArch64::LDARX:
17406 case AArch64::LDATXRW:
17407 case AArch64::LDATXRX:
17408 case AArch64::LDAXRB:
17409 case AArch64::LDAXRH:
17410 case AArch64::LDAXRW:
17411 case AArch64::LDAXRX:
17412 case AArch64::LDLARB:
17413 case AArch64::LDLARH:
17414 case AArch64::LDLARW:
17415 case AArch64::LDLARX:
17416 case AArch64::LDTXRWr:
17417 case AArch64::LDTXRXr:
17418 case AArch64::LDXRB:
17419 case AArch64::LDXRH:
17420 case AArch64::LDXRW:
17421 case AArch64::LDXRX:
17422 case AArch64::STLLRB:
17423 case AArch64::STLLRH:
17424 case AArch64::STLLRW:
17425 case AArch64::STLLRX:
17426 case AArch64::STLRB:
17427 case AArch64::STLRH:
17428 case AArch64::STLRW:
17429 case AArch64::STLRX: {
17430 // op: Rt
17431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17432 op &= UINT64_C(31);
17433 Value |= op;
17434 // op: Rn
17435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17436 op &= UINT64_C(31);
17437 op <<= 5;
17438 Value |= op;
17439 Value = fixLoadStoreExclusive<0,0>(MI, EncodedValue: Value, STI);
17440 break;
17441 }
17442 case AArch64::LDIAPPW:
17443 case AArch64::LDIAPPX:
17444 case AArch64::STILPW:
17445 case AArch64::STILPX: {
17446 // op: Rt
17447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17448 op &= UINT64_C(31);
17449 Value |= op;
17450 // op: Rn
17451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17452 op &= UINT64_C(31);
17453 op <<= 5;
17454 Value |= op;
17455 // op: Rt2
17456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17457 op &= UINT64_C(31);
17458 op <<= 16;
17459 Value |= op;
17460 break;
17461 }
17462 case AArch64::LDBFADD:
17463 case AArch64::LDBFADDA:
17464 case AArch64::LDBFADDAL:
17465 case AArch64::LDBFADDL:
17466 case AArch64::LDBFMAX:
17467 case AArch64::LDBFMAXA:
17468 case AArch64::LDBFMAXAL:
17469 case AArch64::LDBFMAXL:
17470 case AArch64::LDBFMAXNM:
17471 case AArch64::LDBFMAXNMA:
17472 case AArch64::LDBFMAXNMAL:
17473 case AArch64::LDBFMAXNML:
17474 case AArch64::LDBFMIN:
17475 case AArch64::LDBFMINA:
17476 case AArch64::LDBFMINAL:
17477 case AArch64::LDBFMINL:
17478 case AArch64::LDBFMINNM:
17479 case AArch64::LDBFMINNMA:
17480 case AArch64::LDBFMINNMAL:
17481 case AArch64::LDBFMINNML:
17482 case AArch64::LDFADDAD:
17483 case AArch64::LDFADDAH:
17484 case AArch64::LDFADDALD:
17485 case AArch64::LDFADDALH:
17486 case AArch64::LDFADDALS:
17487 case AArch64::LDFADDAS:
17488 case AArch64::LDFADDD:
17489 case AArch64::LDFADDH:
17490 case AArch64::LDFADDLD:
17491 case AArch64::LDFADDLH:
17492 case AArch64::LDFADDLS:
17493 case AArch64::LDFADDS:
17494 case AArch64::LDFMAXAD:
17495 case AArch64::LDFMAXAH:
17496 case AArch64::LDFMAXALD:
17497 case AArch64::LDFMAXALH:
17498 case AArch64::LDFMAXALS:
17499 case AArch64::LDFMAXAS:
17500 case AArch64::LDFMAXD:
17501 case AArch64::LDFMAXH:
17502 case AArch64::LDFMAXLD:
17503 case AArch64::LDFMAXLH:
17504 case AArch64::LDFMAXLS:
17505 case AArch64::LDFMAXNMAD:
17506 case AArch64::LDFMAXNMAH:
17507 case AArch64::LDFMAXNMALD:
17508 case AArch64::LDFMAXNMALH:
17509 case AArch64::LDFMAXNMALS:
17510 case AArch64::LDFMAXNMAS:
17511 case AArch64::LDFMAXNMD:
17512 case AArch64::LDFMAXNMH:
17513 case AArch64::LDFMAXNMLD:
17514 case AArch64::LDFMAXNMLH:
17515 case AArch64::LDFMAXNMLS:
17516 case AArch64::LDFMAXNMS:
17517 case AArch64::LDFMAXS:
17518 case AArch64::LDFMINAD:
17519 case AArch64::LDFMINAH:
17520 case AArch64::LDFMINALD:
17521 case AArch64::LDFMINALH:
17522 case AArch64::LDFMINALS:
17523 case AArch64::LDFMINAS:
17524 case AArch64::LDFMIND:
17525 case AArch64::LDFMINH:
17526 case AArch64::LDFMINLD:
17527 case AArch64::LDFMINLH:
17528 case AArch64::LDFMINLS:
17529 case AArch64::LDFMINNMAD:
17530 case AArch64::LDFMINNMAH:
17531 case AArch64::LDFMINNMALD:
17532 case AArch64::LDFMINNMALH:
17533 case AArch64::LDFMINNMALS:
17534 case AArch64::LDFMINNMAS:
17535 case AArch64::LDFMINNMD:
17536 case AArch64::LDFMINNMH:
17537 case AArch64::LDFMINNMLD:
17538 case AArch64::LDFMINNMLH:
17539 case AArch64::LDFMINNMLS:
17540 case AArch64::LDFMINNMS:
17541 case AArch64::LDFMINS: {
17542 // op: Rt
17543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17544 op &= UINT64_C(31);
17545 Value |= op;
17546 // op: Rs
17547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17548 op &= UINT64_C(31);
17549 op <<= 16;
17550 Value |= op;
17551 // op: Rn
17552 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17553 op &= UINT64_C(31);
17554 op <<= 5;
17555 Value |= op;
17556 break;
17557 }
17558 case AArch64::LDNPDi:
17559 case AArch64::LDNPQi:
17560 case AArch64::LDNPSi:
17561 case AArch64::LDNPWi:
17562 case AArch64::LDNPXi:
17563 case AArch64::LDPDi:
17564 case AArch64::LDPQi:
17565 case AArch64::LDPSWi:
17566 case AArch64::LDPSi:
17567 case AArch64::LDPWi:
17568 case AArch64::LDPXi:
17569 case AArch64::LDTNPQi:
17570 case AArch64::LDTNPXi:
17571 case AArch64::LDTPQi:
17572 case AArch64::LDTPi:
17573 case AArch64::STGPi:
17574 case AArch64::STNPDi:
17575 case AArch64::STNPQi:
17576 case AArch64::STNPSi:
17577 case AArch64::STNPWi:
17578 case AArch64::STNPXi:
17579 case AArch64::STPDi:
17580 case AArch64::STPQi:
17581 case AArch64::STPSi:
17582 case AArch64::STPWi:
17583 case AArch64::STPXi:
17584 case AArch64::STTNPQi:
17585 case AArch64::STTNPXi:
17586 case AArch64::STTPQi:
17587 case AArch64::STTPi: {
17588 // op: Rt
17589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17590 op &= UINT64_C(31);
17591 Value |= op;
17592 // op: Rt2
17593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17594 op &= UINT64_C(31);
17595 op <<= 10;
17596 Value |= op;
17597 // op: Rn
17598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17599 op &= UINT64_C(31);
17600 op <<= 5;
17601 Value |= op;
17602 // op: offset
17603 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17604 op &= UINT64_C(127);
17605 op <<= 15;
17606 Value |= op;
17607 break;
17608 }
17609 case AArch64::LDAXPW:
17610 case AArch64::LDAXPX:
17611 case AArch64::LDXPW:
17612 case AArch64::LDXPX: {
17613 // op: Rt
17614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17615 op &= UINT64_C(31);
17616 Value |= op;
17617 // op: Rt2
17618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17619 op &= UINT64_C(31);
17620 op <<= 10;
17621 Value |= op;
17622 // op: Rn
17623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17624 op &= UINT64_C(31);
17625 op <<= 5;
17626 Value |= op;
17627 Value = fixLoadStoreExclusive<0,1>(MI, EncodedValue: Value, STI);
17628 break;
17629 }
17630 case AArch64::TBNZW:
17631 case AArch64::TBNZX:
17632 case AArch64::TBZW:
17633 case AArch64::TBZX: {
17634 // op: Rt
17635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17636 op &= UINT64_C(31);
17637 Value |= op;
17638 // op: bit_off
17639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17640 op &= UINT64_C(31);
17641 op <<= 19;
17642 Value |= op;
17643 // op: target
17644 op = getTestBranchTargetOpValue(MI, OpIdx: 2, Fixups, STI);
17645 op &= UINT64_C(16383);
17646 op <<= 5;
17647 Value |= op;
17648 break;
17649 }
17650 case AArch64::CBEQWri:
17651 case AArch64::CBEQXri:
17652 case AArch64::CBGTWri:
17653 case AArch64::CBGTXri:
17654 case AArch64::CBHIWri:
17655 case AArch64::CBHIXri:
17656 case AArch64::CBLOWri:
17657 case AArch64::CBLOXri:
17658 case AArch64::CBLTWri:
17659 case AArch64::CBLTXri:
17660 case AArch64::CBNEWri:
17661 case AArch64::CBNEXri: {
17662 // op: Rt
17663 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17664 op &= UINT64_C(31);
17665 Value |= op;
17666 // op: imm
17667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17668 op &= UINT64_C(63);
17669 op <<= 15;
17670 Value |= op;
17671 // op: target
17672 op = getCondCompBranchTargetOpValue(MI, OpIdx: 2, Fixups, STI);
17673 op &= UINT64_C(511);
17674 op <<= 5;
17675 Value |= op;
17676 break;
17677 }
17678 case AArch64::LDRDl:
17679 case AArch64::LDRQl:
17680 case AArch64::LDRSWl:
17681 case AArch64::LDRSl:
17682 case AArch64::LDRWl:
17683 case AArch64::LDRXl:
17684 case AArch64::PRFMl: {
17685 // op: Rt
17686 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17687 op &= UINT64_C(31);
17688 Value |= op;
17689 // op: label
17690 op = getLoadLiteralOpValue(MI, OpIdx: 1, Fixups, STI);
17691 op &= UINT64_C(524287);
17692 op <<= 5;
17693 Value |= op;
17694 break;
17695 }
17696 case AArch64::SYSLxt: {
17697 // op: Rt
17698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17699 op &= UINT64_C(31);
17700 Value |= op;
17701 // op: op1
17702 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17703 op &= UINT64_C(7);
17704 op <<= 16;
17705 Value |= op;
17706 // op: Cn
17707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17708 op &= UINT64_C(15);
17709 op <<= 12;
17710 Value |= op;
17711 // op: Cm
17712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17713 op &= UINT64_C(15);
17714 op <<= 8;
17715 Value |= op;
17716 // op: op2
17717 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17718 op &= UINT64_C(7);
17719 op <<= 5;
17720 Value |= op;
17721 break;
17722 }
17723 case AArch64::MRRS:
17724 case AArch64::MRS: {
17725 // op: Rt
17726 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17727 op &= UINT64_C(31);
17728 Value |= op;
17729 // op: systemreg
17730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17731 op &= UINT64_C(65535);
17732 op <<= 5;
17733 Value |= op;
17734 break;
17735 }
17736 case AArch64::CBNZW:
17737 case AArch64::CBNZX:
17738 case AArch64::CBZW:
17739 case AArch64::CBZX: {
17740 // op: Rt
17741 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17742 op &= UINT64_C(31);
17743 Value |= op;
17744 // op: target
17745 op = getCondBranchTargetOpValue(MI, OpIdx: 1, Fixups, STI);
17746 op &= UINT64_C(524287);
17747 op <<= 5;
17748 Value |= op;
17749 break;
17750 }
17751 case AArch64::LDAPRWpost:
17752 case AArch64::LDAPRXpost:
17753 case AArch64::STLRWpre:
17754 case AArch64::STLRXpre: {
17755 // op: Rt
17756 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17757 op &= UINT64_C(31);
17758 Value |= op;
17759 // op: Rn
17760 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17761 op &= UINT64_C(31);
17762 op <<= 5;
17763 Value |= op;
17764 break;
17765 }
17766 case AArch64::ST64BV:
17767 case AArch64::ST64BV0: {
17768 // op: Rt
17769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17770 op &= UINT64_C(31);
17771 Value |= op;
17772 // op: Rn
17773 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17774 op &= UINT64_C(31);
17775 op <<= 5;
17776 Value |= op;
17777 // op: Rs
17778 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17779 op &= UINT64_C(31);
17780 op <<= 16;
17781 Value |= op;
17782 break;
17783 }
17784 case AArch64::STTXRWr:
17785 case AArch64::STTXRXr: {
17786 // op: Rt
17787 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17788 op &= UINT64_C(31);
17789 Value |= op;
17790 // op: Rn
17791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17792 op &= UINT64_C(31);
17793 op <<= 5;
17794 Value |= op;
17795 // op: Ws
17796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17797 op &= UINT64_C(31);
17798 op <<= 16;
17799 Value |= op;
17800 Value = fixLoadStoreExclusive<1,0>(MI, EncodedValue: Value, STI);
17801 break;
17802 }
17803 case AArch64::LDRBBpost:
17804 case AArch64::LDRBBpre:
17805 case AArch64::LDRBpost:
17806 case AArch64::LDRBpre:
17807 case AArch64::LDRDpost:
17808 case AArch64::LDRDpre:
17809 case AArch64::LDRHHpost:
17810 case AArch64::LDRHHpre:
17811 case AArch64::LDRHpost:
17812 case AArch64::LDRHpre:
17813 case AArch64::LDRQpost:
17814 case AArch64::LDRQpre:
17815 case AArch64::LDRSBWpost:
17816 case AArch64::LDRSBWpre:
17817 case AArch64::LDRSBXpost:
17818 case AArch64::LDRSBXpre:
17819 case AArch64::LDRSHWpost:
17820 case AArch64::LDRSHWpre:
17821 case AArch64::LDRSHXpost:
17822 case AArch64::LDRSHXpre:
17823 case AArch64::LDRSWpost:
17824 case AArch64::LDRSWpre:
17825 case AArch64::LDRSpost:
17826 case AArch64::LDRSpre:
17827 case AArch64::LDRWpost:
17828 case AArch64::LDRWpre:
17829 case AArch64::LDRXpost:
17830 case AArch64::LDRXpre:
17831 case AArch64::STRBBpost:
17832 case AArch64::STRBBpre:
17833 case AArch64::STRBpost:
17834 case AArch64::STRBpre:
17835 case AArch64::STRDpost:
17836 case AArch64::STRDpre:
17837 case AArch64::STRHHpost:
17838 case AArch64::STRHHpre:
17839 case AArch64::STRHpost:
17840 case AArch64::STRHpre:
17841 case AArch64::STRQpost:
17842 case AArch64::STRQpre:
17843 case AArch64::STRSpost:
17844 case AArch64::STRSpre:
17845 case AArch64::STRWpost:
17846 case AArch64::STRWpre:
17847 case AArch64::STRXpost:
17848 case AArch64::STRXpre: {
17849 // op: Rt
17850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17851 op &= UINT64_C(31);
17852 Value |= op;
17853 // op: Rn
17854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17855 op &= UINT64_C(31);
17856 op <<= 5;
17857 Value |= op;
17858 // op: offset
17859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17860 op &= UINT64_C(511);
17861 op <<= 12;
17862 Value |= op;
17863 break;
17864 }
17865 case AArch64::LDIAPPWpost:
17866 case AArch64::LDIAPPXpost:
17867 case AArch64::STILPWpre:
17868 case AArch64::STILPXpre: {
17869 // op: Rt
17870 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17871 op &= UINT64_C(31);
17872 Value |= op;
17873 // op: Rn
17874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17875 op &= UINT64_C(31);
17876 op <<= 5;
17877 Value |= op;
17878 // op: Rt2
17879 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17880 op &= UINT64_C(31);
17881 op <<= 16;
17882 Value |= op;
17883 break;
17884 }
17885 case AArch64::LDPDpost:
17886 case AArch64::LDPDpre:
17887 case AArch64::LDPQpost:
17888 case AArch64::LDPQpre:
17889 case AArch64::LDPSWpost:
17890 case AArch64::LDPSWpre:
17891 case AArch64::LDPSpost:
17892 case AArch64::LDPSpre:
17893 case AArch64::LDPWpost:
17894 case AArch64::LDPWpre:
17895 case AArch64::LDPXpost:
17896 case AArch64::LDPXpre:
17897 case AArch64::LDTPQpost:
17898 case AArch64::LDTPQpre:
17899 case AArch64::LDTPpost:
17900 case AArch64::LDTPpre:
17901 case AArch64::STGPpost:
17902 case AArch64::STGPpre:
17903 case AArch64::STPDpost:
17904 case AArch64::STPDpre:
17905 case AArch64::STPQpost:
17906 case AArch64::STPQpre:
17907 case AArch64::STPSpost:
17908 case AArch64::STPSpre:
17909 case AArch64::STPWpost:
17910 case AArch64::STPWpre:
17911 case AArch64::STPXpost:
17912 case AArch64::STPXpre:
17913 case AArch64::STTPQpost:
17914 case AArch64::STTPQpre:
17915 case AArch64::STTPpost:
17916 case AArch64::STTPpre: {
17917 // op: Rt
17918 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17919 op &= UINT64_C(31);
17920 Value |= op;
17921 // op: Rt2
17922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17923 op &= UINT64_C(31);
17924 op <<= 10;
17925 Value |= op;
17926 // op: Rn
17927 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17928 op &= UINT64_C(31);
17929 op <<= 5;
17930 Value |= op;
17931 // op: offset
17932 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17933 op &= UINT64_C(127);
17934 op <<= 15;
17935 Value |= op;
17936 break;
17937 }
17938 case AArch64::MSR:
17939 case AArch64::MSRR: {
17940 // op: Rt
17941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17942 op &= UINT64_C(31);
17943 Value |= op;
17944 // op: systemreg
17945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17946 op &= UINT64_C(65535);
17947 op <<= 5;
17948 Value |= op;
17949 break;
17950 }
17951 case AArch64::LDCLRP:
17952 case AArch64::LDCLRPA:
17953 case AArch64::LDCLRPAL:
17954 case AArch64::LDCLRPL:
17955 case AArch64::LDSETP:
17956 case AArch64::LDSETPA:
17957 case AArch64::LDSETPAL:
17958 case AArch64::LDSETPL:
17959 case AArch64::SWPP:
17960 case AArch64::SWPPA:
17961 case AArch64::SWPPAL:
17962 case AArch64::SWPPL: {
17963 // op: Rt
17964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17965 op &= UINT64_C(31);
17966 Value |= op;
17967 // op: Rt2
17968 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17969 op &= UINT64_C(31);
17970 op <<= 16;
17971 Value |= op;
17972 // op: Rn
17973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17974 op &= UINT64_C(31);
17975 op <<= 5;
17976 Value |= op;
17977 break;
17978 }
17979 case AArch64::SYSPxt:
17980 case AArch64::SYSxt: {
17981 // op: Rt
17982 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17983 op &= UINT64_C(31);
17984 Value |= op;
17985 // op: op1
17986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17987 op &= UINT64_C(7);
17988 op <<= 16;
17989 Value |= op;
17990 // op: Cn
17991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17992 op &= UINT64_C(15);
17993 op <<= 12;
17994 Value |= op;
17995 // op: Cm
17996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17997 op &= UINT64_C(15);
17998 op <<= 8;
17999 Value |= op;
18000 // op: op2
18001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18002 op &= UINT64_C(7);
18003 op <<= 5;
18004 Value |= op;
18005 break;
18006 }
18007 case AArch64::RCWCLRP:
18008 case AArch64::RCWCLRPA:
18009 case AArch64::RCWCLRPAL:
18010 case AArch64::RCWCLRPL:
18011 case AArch64::RCWCLRSP:
18012 case AArch64::RCWCLRSPA:
18013 case AArch64::RCWCLRSPAL:
18014 case AArch64::RCWCLRSPL:
18015 case AArch64::RCWSETP:
18016 case AArch64::RCWSETPA:
18017 case AArch64::RCWSETPAL:
18018 case AArch64::RCWSETPL:
18019 case AArch64::RCWSETSP:
18020 case AArch64::RCWSETSPA:
18021 case AArch64::RCWSETSPAL:
18022 case AArch64::RCWSETSPL:
18023 case AArch64::RCWSWPP:
18024 case AArch64::RCWSWPPA:
18025 case AArch64::RCWSWPPAL:
18026 case AArch64::RCWSWPPL:
18027 case AArch64::RCWSWPSP:
18028 case AArch64::RCWSWPSPA:
18029 case AArch64::RCWSWPSPAL:
18030 case AArch64::RCWSWPSPL: {
18031 // op: Rt2
18032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18033 op &= UINT64_C(31);
18034 op <<= 16;
18035 Value |= op;
18036 // op: Rn
18037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18038 op &= UINT64_C(31);
18039 op <<= 5;
18040 Value |= op;
18041 // op: Rt
18042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18043 op &= UINT64_C(31);
18044 Value |= op;
18045 break;
18046 }
18047 case AArch64::LDR_ZA:
18048 case AArch64::STR_ZA: {
18049 // op: Rv
18050 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
18051 op &= UINT64_C(3);
18052 op <<= 13;
18053 Value |= op;
18054 // op: Rn
18055 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18056 op &= UINT64_C(31);
18057 op <<= 5;
18058 Value |= op;
18059 // op: imm4
18060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18061 op &= UINT64_C(15);
18062 Value |= op;
18063 break;
18064 }
18065 case AArch64::INSERT_MXIPZ_H_H:
18066 case AArch64::INSERT_MXIPZ_V_H: {
18067 // op: Rv
18068 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18069 op &= UINT64_C(3);
18070 op <<= 13;
18071 Value |= op;
18072 // op: Pg
18073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18074 op &= UINT64_C(7);
18075 op <<= 10;
18076 Value |= op;
18077 // op: Zn
18078 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18079 op &= UINT64_C(31);
18080 op <<= 5;
18081 Value |= op;
18082 // op: ZAd
18083 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18084 op &= UINT64_C(1);
18085 op <<= 3;
18086 Value |= op;
18087 // op: imm
18088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18089 op &= UINT64_C(7);
18090 Value |= op;
18091 break;
18092 }
18093 case AArch64::INSERT_MXIPZ_H_Q:
18094 case AArch64::INSERT_MXIPZ_V_Q: {
18095 // op: Rv
18096 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18097 op &= UINT64_C(3);
18098 op <<= 13;
18099 Value |= op;
18100 // op: Pg
18101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18102 op &= UINT64_C(7);
18103 op <<= 10;
18104 Value |= op;
18105 // op: Zn
18106 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18107 op &= UINT64_C(31);
18108 op <<= 5;
18109 Value |= op;
18110 // op: ZAd
18111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18112 op &= UINT64_C(15);
18113 Value |= op;
18114 break;
18115 }
18116 case AArch64::INSERT_MXIPZ_H_S:
18117 case AArch64::INSERT_MXIPZ_V_S: {
18118 // op: Rv
18119 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18120 op &= UINT64_C(3);
18121 op <<= 13;
18122 Value |= op;
18123 // op: Pg
18124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18125 op &= UINT64_C(7);
18126 op <<= 10;
18127 Value |= op;
18128 // op: Zn
18129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18130 op &= UINT64_C(31);
18131 op <<= 5;
18132 Value |= op;
18133 // op: ZAd
18134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18135 op &= UINT64_C(3);
18136 op <<= 2;
18137 Value |= op;
18138 // op: imm
18139 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18140 op &= UINT64_C(3);
18141 Value |= op;
18142 break;
18143 }
18144 case AArch64::INSERT_MXIPZ_H_D:
18145 case AArch64::INSERT_MXIPZ_V_D: {
18146 // op: Rv
18147 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18148 op &= UINT64_C(3);
18149 op <<= 13;
18150 Value |= op;
18151 // op: Pg
18152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18153 op &= UINT64_C(7);
18154 op <<= 10;
18155 Value |= op;
18156 // op: Zn
18157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18158 op &= UINT64_C(31);
18159 op <<= 5;
18160 Value |= op;
18161 // op: ZAd
18162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18163 op &= UINT64_C(7);
18164 op <<= 1;
18165 Value |= op;
18166 // op: imm
18167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18168 op &= UINT64_C(1);
18169 Value |= op;
18170 break;
18171 }
18172 case AArch64::INSERT_MXIPZ_H_B:
18173 case AArch64::INSERT_MXIPZ_V_B: {
18174 // op: Rv
18175 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18176 op &= UINT64_C(3);
18177 op <<= 13;
18178 Value |= op;
18179 // op: Pg
18180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18181 op &= UINT64_C(7);
18182 op <<= 10;
18183 Value |= op;
18184 // op: Zn
18185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18186 op &= UINT64_C(31);
18187 op <<= 5;
18188 Value |= op;
18189 // op: imm
18190 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18191 op &= UINT64_C(15);
18192 Value |= op;
18193 break;
18194 }
18195 case AArch64::PSEL_PPPRI_B: {
18196 // op: Rv
18197 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18198 op &= UINT64_C(3);
18199 op <<= 16;
18200 Value |= op;
18201 // op: Pn
18202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18203 op &= UINT64_C(15);
18204 op <<= 10;
18205 Value |= op;
18206 // op: Pm
18207 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18208 op &= UINT64_C(15);
18209 op <<= 5;
18210 Value |= op;
18211 // op: Pd
18212 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18213 op &= UINT64_C(15);
18214 Value |= op;
18215 // op: imm
18216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18217 Value |= (op & UINT64_C(12)) << 20;
18218 Value |= (op & UINT64_C(3)) << 19;
18219 break;
18220 }
18221 case AArch64::PSEL_PPPRI_H: {
18222 // op: Rv
18223 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18224 op &= UINT64_C(3);
18225 op <<= 16;
18226 Value |= op;
18227 // op: Pn
18228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18229 op &= UINT64_C(15);
18230 op <<= 10;
18231 Value |= op;
18232 // op: Pm
18233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18234 op &= UINT64_C(15);
18235 op <<= 5;
18236 Value |= op;
18237 // op: Pd
18238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18239 op &= UINT64_C(15);
18240 Value |= op;
18241 // op: imm
18242 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18243 Value |= (op & UINT64_C(6)) << 21;
18244 Value |= (op & UINT64_C(1)) << 20;
18245 break;
18246 }
18247 case AArch64::PSEL_PPPRI_D: {
18248 // op: Rv
18249 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18250 op &= UINT64_C(3);
18251 op <<= 16;
18252 Value |= op;
18253 // op: Pn
18254 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18255 op &= UINT64_C(15);
18256 op <<= 10;
18257 Value |= op;
18258 // op: Pm
18259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18260 op &= UINT64_C(15);
18261 op <<= 5;
18262 Value |= op;
18263 // op: Pd
18264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18265 op &= UINT64_C(15);
18266 Value |= op;
18267 // op: imm
18268 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18269 op &= UINT64_C(1);
18270 op <<= 23;
18271 Value |= op;
18272 break;
18273 }
18274 case AArch64::PSEL_PPPRI_S: {
18275 // op: Rv
18276 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18277 op &= UINT64_C(3);
18278 op <<= 16;
18279 Value |= op;
18280 // op: Pn
18281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18282 op &= UINT64_C(15);
18283 op <<= 10;
18284 Value |= op;
18285 // op: Pm
18286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18287 op &= UINT64_C(15);
18288 op <<= 5;
18289 Value |= op;
18290 // op: Pd
18291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18292 op &= UINT64_C(15);
18293 Value |= op;
18294 // op: imm
18295 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18296 op &= UINT64_C(3);
18297 op <<= 22;
18298 Value |= op;
18299 break;
18300 }
18301 case AArch64::EXTRACT_ZPMXI_H_H:
18302 case AArch64::EXTRACT_ZPMXI_V_H: {
18303 // op: Rv
18304 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
18305 op &= UINT64_C(3);
18306 op <<= 13;
18307 Value |= op;
18308 // op: Pg
18309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18310 op &= UINT64_C(7);
18311 op <<= 10;
18312 Value |= op;
18313 // op: Zd
18314 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18315 op &= UINT64_C(31);
18316 Value |= op;
18317 // op: ZAn
18318 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18319 op &= UINT64_C(1);
18320 op <<= 8;
18321 Value |= op;
18322 // op: imm
18323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18324 op &= UINT64_C(7);
18325 op <<= 5;
18326 Value |= op;
18327 break;
18328 }
18329 case AArch64::EXTRACT_ZPMXI_H_Q:
18330 case AArch64::EXTRACT_ZPMXI_V_Q: {
18331 // op: Rv
18332 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
18333 op &= UINT64_C(3);
18334 op <<= 13;
18335 Value |= op;
18336 // op: Pg
18337 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18338 op &= UINT64_C(7);
18339 op <<= 10;
18340 Value |= op;
18341 // op: Zd
18342 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18343 op &= UINT64_C(31);
18344 Value |= op;
18345 // op: ZAn
18346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18347 op &= UINT64_C(15);
18348 op <<= 5;
18349 Value |= op;
18350 break;
18351 }
18352 case AArch64::EXTRACT_ZPMXI_H_S:
18353 case AArch64::EXTRACT_ZPMXI_V_S: {
18354 // op: Rv
18355 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
18356 op &= UINT64_C(3);
18357 op <<= 13;
18358 Value |= op;
18359 // op: Pg
18360 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18361 op &= UINT64_C(7);
18362 op <<= 10;
18363 Value |= op;
18364 // op: Zd
18365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18366 op &= UINT64_C(31);
18367 Value |= op;
18368 // op: ZAn
18369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18370 op &= UINT64_C(3);
18371 op <<= 7;
18372 Value |= op;
18373 // op: imm
18374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18375 op &= UINT64_C(3);
18376 op <<= 5;
18377 Value |= op;
18378 break;
18379 }
18380 case AArch64::EXTRACT_ZPMXI_H_D:
18381 case AArch64::EXTRACT_ZPMXI_V_D: {
18382 // op: Rv
18383 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
18384 op &= UINT64_C(3);
18385 op <<= 13;
18386 Value |= op;
18387 // op: Pg
18388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18389 op &= UINT64_C(7);
18390 op <<= 10;
18391 Value |= op;
18392 // op: Zd
18393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18394 op &= UINT64_C(31);
18395 Value |= op;
18396 // op: ZAn
18397 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18398 op &= UINT64_C(7);
18399 op <<= 6;
18400 Value |= op;
18401 // op: imm
18402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18403 op &= UINT64_C(1);
18404 op <<= 5;
18405 Value |= op;
18406 break;
18407 }
18408 case AArch64::EXTRACT_ZPMXI_H_B:
18409 case AArch64::EXTRACT_ZPMXI_V_B: {
18410 // op: Rv
18411 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
18412 op &= UINT64_C(3);
18413 op <<= 13;
18414 Value |= op;
18415 // op: Pg
18416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18417 op &= UINT64_C(7);
18418 op <<= 10;
18419 Value |= op;
18420 // op: Zd
18421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18422 op &= UINT64_C(31);
18423 Value |= op;
18424 // op: imm
18425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18426 op &= UINT64_C(15);
18427 op <<= 5;
18428 Value |= op;
18429 break;
18430 }
18431 case AArch64::BFMLAL_VG2_M2Z2Z_HtoS:
18432 case AArch64::BFMLSL_VG2_M2Z2Z_HtoS:
18433 case AArch64::FMLAL_VG2_M2Z2Z_BtoH:
18434 case AArch64::FMLAL_VG2_M2Z2Z_HtoS:
18435 case AArch64::FMLSL_VG2_M2Z2Z_HtoS:
18436 case AArch64::SMLAL_VG2_M2Z2Z_HtoS:
18437 case AArch64::SMLSL_VG2_M2Z2Z_HtoS:
18438 case AArch64::UMLAL_VG2_M2Z2Z_HtoS:
18439 case AArch64::UMLSL_VG2_M2Z2Z_HtoS: {
18440 // op: Rv
18441 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18442 op &= UINT64_C(3);
18443 op <<= 13;
18444 Value |= op;
18445 // op: Zm
18446 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 5, Fixups, STI);
18447 op &= UINT64_C(15);
18448 op <<= 17;
18449 Value |= op;
18450 // op: Zn
18451 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
18452 op &= UINT64_C(15);
18453 op <<= 6;
18454 Value |= op;
18455 // op: imm
18456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18457 op &= UINT64_C(3);
18458 Value |= op;
18459 break;
18460 }
18461 case AArch64::BFMLAL_VG4_M4Z4Z_HtoS:
18462 case AArch64::BFMLSL_VG4_M4Z4Z_HtoS:
18463 case AArch64::FMLAL_VG4_M4Z4Z_BtoH:
18464 case AArch64::FMLAL_VG4_M4Z4Z_HtoS:
18465 case AArch64::FMLSL_VG4_M4Z4Z_HtoS:
18466 case AArch64::SMLAL_VG4_M4Z4Z_HtoS:
18467 case AArch64::SMLSL_VG4_M4Z4Z_HtoS:
18468 case AArch64::UMLAL_VG4_M4Z4Z_HtoS:
18469 case AArch64::UMLSL_VG4_M4Z4Z_HtoS: {
18470 // op: Rv
18471 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18472 op &= UINT64_C(3);
18473 op <<= 13;
18474 Value |= op;
18475 // op: Zm
18476 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 5, Fixups, STI);
18477 op &= UINT64_C(7);
18478 op <<= 18;
18479 Value |= op;
18480 // op: Zn
18481 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
18482 op &= UINT64_C(7);
18483 op <<= 7;
18484 Value |= op;
18485 // op: imm
18486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18487 op &= UINT64_C(3);
18488 Value |= op;
18489 break;
18490 }
18491 case AArch64::BFMLAL_VG2_M2ZZ_HtoS:
18492 case AArch64::BFMLAL_VG4_M4ZZ_HtoS:
18493 case AArch64::BFMLSL_VG2_M2ZZ_HtoS:
18494 case AArch64::BFMLSL_VG4_M4ZZ_HtoS:
18495 case AArch64::FMLAL_VG2_M2ZZ_BtoH:
18496 case AArch64::FMLAL_VG2_M2ZZ_HtoS:
18497 case AArch64::FMLAL_VG4_M4ZZ_BtoH:
18498 case AArch64::FMLAL_VG4_M4ZZ_HtoS:
18499 case AArch64::FMLSL_VG2_M2ZZ_HtoS:
18500 case AArch64::FMLSL_VG4_M4ZZ_HtoS:
18501 case AArch64::SMLAL_VG2_M2ZZ_HtoS:
18502 case AArch64::SMLAL_VG4_M4ZZ_HtoS:
18503 case AArch64::SMLSL_VG2_M2ZZ_HtoS:
18504 case AArch64::SMLSL_VG4_M4ZZ_HtoS:
18505 case AArch64::UMLAL_VG2_M2ZZ_HtoS:
18506 case AArch64::UMLAL_VG4_M4ZZ_HtoS:
18507 case AArch64::UMLSL_VG2_M2ZZ_HtoS:
18508 case AArch64::UMLSL_VG4_M4ZZ_HtoS: {
18509 // op: Rv
18510 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18511 op &= UINT64_C(3);
18512 op <<= 13;
18513 Value |= op;
18514 // op: Zm
18515 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18516 op &= UINT64_C(15);
18517 op <<= 16;
18518 Value |= op;
18519 // op: Zn
18520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18521 op &= UINT64_C(31);
18522 op <<= 5;
18523 Value |= op;
18524 // op: imm
18525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18526 op &= UINT64_C(3);
18527 Value |= op;
18528 break;
18529 }
18530 case AArch64::BFMLAL_MZZ_HtoS:
18531 case AArch64::BFMLSL_MZZ_HtoS:
18532 case AArch64::FMLAL_MZZ_HtoS:
18533 case AArch64::FMLAL_VG2_MZZ_BtoH:
18534 case AArch64::FMLSL_MZZ_HtoS:
18535 case AArch64::SMLAL_MZZ_HtoS:
18536 case AArch64::SMLSL_MZZ_HtoS:
18537 case AArch64::UMLAL_MZZ_HtoS:
18538 case AArch64::UMLSL_MZZ_HtoS: {
18539 // op: Rv
18540 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18541 op &= UINT64_C(3);
18542 op <<= 13;
18543 Value |= op;
18544 // op: Zm
18545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18546 op &= UINT64_C(15);
18547 op <<= 16;
18548 Value |= op;
18549 // op: Zn
18550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18551 op &= UINT64_C(31);
18552 op <<= 5;
18553 Value |= op;
18554 // op: imm
18555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18556 op &= UINT64_C(7);
18557 Value |= op;
18558 break;
18559 }
18560 case AArch64::ZERO_MXI_VG2_4Z:
18561 case AArch64::ZERO_MXI_VG4_4Z: {
18562 // op: Rv
18563 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18564 op &= UINT64_C(3);
18565 op <<= 13;
18566 Value |= op;
18567 // op: imm
18568 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18569 op &= UINT64_C(1);
18570 Value |= op;
18571 break;
18572 }
18573 case AArch64::ZERO_MXI_4Z:
18574 case AArch64::ZERO_MXI_VG2_2Z:
18575 case AArch64::ZERO_MXI_VG4_2Z: {
18576 // op: Rv
18577 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18578 op &= UINT64_C(3);
18579 op <<= 13;
18580 Value |= op;
18581 // op: imm
18582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18583 op &= UINT64_C(3);
18584 Value |= op;
18585 break;
18586 }
18587 case AArch64::ZERO_MXI_2Z:
18588 case AArch64::ZERO_MXI_VG2_Z:
18589 case AArch64::ZERO_MXI_VG4_Z: {
18590 // op: Rv
18591 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18592 op &= UINT64_C(3);
18593 op <<= 13;
18594 Value |= op;
18595 // op: imm
18596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18597 op &= UINT64_C(7);
18598 Value |= op;
18599 break;
18600 }
18601 case AArch64::ADD_VG2_M2Z_D:
18602 case AArch64::ADD_VG2_M2Z_S:
18603 case AArch64::BFADD_VG2_M2Z_H:
18604 case AArch64::BFSUB_VG2_M2Z_H:
18605 case AArch64::FADD_VG2_M2Z_D:
18606 case AArch64::FADD_VG2_M2Z_H:
18607 case AArch64::FADD_VG2_M2Z_S:
18608 case AArch64::FSUB_VG2_M2Z_D:
18609 case AArch64::FSUB_VG2_M2Z_H:
18610 case AArch64::FSUB_VG2_M2Z_S:
18611 case AArch64::SUB_VG2_M2Z_D:
18612 case AArch64::SUB_VG2_M2Z_S: {
18613 // op: Rv
18614 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18615 op &= UINT64_C(3);
18616 op <<= 13;
18617 Value |= op;
18618 // op: imm3
18619 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18620 op &= UINT64_C(7);
18621 Value |= op;
18622 // op: Zm
18623 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
18624 op &= UINT64_C(15);
18625 op <<= 6;
18626 Value |= op;
18627 break;
18628 }
18629 case AArch64::ADD_VG4_M4Z_D:
18630 case AArch64::ADD_VG4_M4Z_S:
18631 case AArch64::BFADD_VG4_M4Z_H:
18632 case AArch64::BFSUB_VG4_M4Z_H:
18633 case AArch64::FADD_VG4_M4Z_D:
18634 case AArch64::FADD_VG4_M4Z_H:
18635 case AArch64::FADD_VG4_M4Z_S:
18636 case AArch64::FSUB_VG4_M4Z_D:
18637 case AArch64::FSUB_VG4_M4Z_H:
18638 case AArch64::FSUB_VG4_M4Z_S:
18639 case AArch64::SUB_VG4_M4Z_D:
18640 case AArch64::SUB_VG4_M4Z_S: {
18641 // op: Rv
18642 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
18643 op &= UINT64_C(3);
18644 op <<= 13;
18645 Value |= op;
18646 // op: imm3
18647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18648 op &= UINT64_C(7);
18649 Value |= op;
18650 // op: Zm
18651 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
18652 op &= UINT64_C(7);
18653 op <<= 7;
18654 Value |= op;
18655 break;
18656 }
18657 case AArch64::RAX1:
18658 case AArch64::SM4ENCKEY:
18659 case AArch64::TBLv8i8Four:
18660 case AArch64::TBLv8i8One:
18661 case AArch64::TBLv8i8Three:
18662 case AArch64::TBLv8i8Two:
18663 case AArch64::TBLv16i8Four:
18664 case AArch64::TBLv16i8One:
18665 case AArch64::TBLv16i8Three:
18666 case AArch64::TBLv16i8Two: {
18667 // op: Vd
18668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18669 op &= UINT64_C(31);
18670 Value |= op;
18671 // op: Vn
18672 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18673 op &= UINT64_C(31);
18674 op <<= 5;
18675 Value |= op;
18676 // op: Vm
18677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18678 op &= UINT64_C(31);
18679 op <<= 16;
18680 Value |= op;
18681 break;
18682 }
18683 case AArch64::BCAX:
18684 case AArch64::EOR3:
18685 case AArch64::SM3SS1: {
18686 // op: Vd
18687 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18688 op &= UINT64_C(31);
18689 Value |= op;
18690 // op: Vn
18691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18692 op &= UINT64_C(31);
18693 op <<= 5;
18694 Value |= op;
18695 // op: Vm
18696 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18697 op &= UINT64_C(31);
18698 op <<= 16;
18699 Value |= op;
18700 // op: Va
18701 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18702 op &= UINT64_C(31);
18703 op <<= 10;
18704 Value |= op;
18705 break;
18706 }
18707 case AArch64::XAR: {
18708 // op: Vd
18709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18710 op &= UINT64_C(31);
18711 Value |= op;
18712 // op: Vn
18713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18714 op &= UINT64_C(31);
18715 op <<= 5;
18716 Value |= op;
18717 // op: imm
18718 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18719 op &= UINT64_C(63);
18720 op <<= 10;
18721 Value |= op;
18722 // op: Vm
18723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18724 op &= UINT64_C(31);
18725 op <<= 16;
18726 Value |= op;
18727 break;
18728 }
18729 case AArch64::ADDQV_VPZ_B:
18730 case AArch64::ADDQV_VPZ_D:
18731 case AArch64::ADDQV_VPZ_H:
18732 case AArch64::ADDQV_VPZ_S:
18733 case AArch64::ANDQV_VPZ_B:
18734 case AArch64::ANDQV_VPZ_D:
18735 case AArch64::ANDQV_VPZ_H:
18736 case AArch64::ANDQV_VPZ_S:
18737 case AArch64::EORQV_VPZ_B:
18738 case AArch64::EORQV_VPZ_D:
18739 case AArch64::EORQV_VPZ_H:
18740 case AArch64::EORQV_VPZ_S:
18741 case AArch64::FADDQV_D:
18742 case AArch64::FADDQV_H:
18743 case AArch64::FADDQV_S:
18744 case AArch64::FMAXNMQV_D:
18745 case AArch64::FMAXNMQV_H:
18746 case AArch64::FMAXNMQV_S:
18747 case AArch64::FMAXQV_D:
18748 case AArch64::FMAXQV_H:
18749 case AArch64::FMAXQV_S:
18750 case AArch64::FMINNMQV_D:
18751 case AArch64::FMINNMQV_H:
18752 case AArch64::FMINNMQV_S:
18753 case AArch64::FMINQV_D:
18754 case AArch64::FMINQV_H:
18755 case AArch64::FMINQV_S:
18756 case AArch64::ORQV_VPZ_B:
18757 case AArch64::ORQV_VPZ_D:
18758 case AArch64::ORQV_VPZ_H:
18759 case AArch64::ORQV_VPZ_S:
18760 case AArch64::SMAXQV_VPZ_B:
18761 case AArch64::SMAXQV_VPZ_D:
18762 case AArch64::SMAXQV_VPZ_H:
18763 case AArch64::SMAXQV_VPZ_S:
18764 case AArch64::SMINQV_VPZ_B:
18765 case AArch64::SMINQV_VPZ_D:
18766 case AArch64::SMINQV_VPZ_H:
18767 case AArch64::SMINQV_VPZ_S:
18768 case AArch64::UMAXQV_VPZ_B:
18769 case AArch64::UMAXQV_VPZ_D:
18770 case AArch64::UMAXQV_VPZ_H:
18771 case AArch64::UMAXQV_VPZ_S:
18772 case AArch64::UMINQV_VPZ_B:
18773 case AArch64::UMINQV_VPZ_D:
18774 case AArch64::UMINQV_VPZ_H:
18775 case AArch64::UMINQV_VPZ_S: {
18776 // op: Vd
18777 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18778 op &= UINT64_C(31);
18779 Value |= op;
18780 // op: Zn
18781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18782 op &= UINT64_C(31);
18783 op <<= 5;
18784 Value |= op;
18785 // op: Pg
18786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18787 op &= UINT64_C(7);
18788 op <<= 10;
18789 Value |= op;
18790 break;
18791 }
18792 case AArch64::SHA512SU0:
18793 case AArch64::SM4E: {
18794 // op: Vd
18795 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18796 op &= UINT64_C(31);
18797 Value |= op;
18798 // op: Vn
18799 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18800 op &= UINT64_C(31);
18801 op <<= 5;
18802 Value |= op;
18803 break;
18804 }
18805 case AArch64::SHA512H:
18806 case AArch64::SHA512H2:
18807 case AArch64::SHA512SU1:
18808 case AArch64::SM3PARTW1:
18809 case AArch64::SM3PARTW2:
18810 case AArch64::TBXv8i8Four:
18811 case AArch64::TBXv8i8One:
18812 case AArch64::TBXv8i8Three:
18813 case AArch64::TBXv8i8Two:
18814 case AArch64::TBXv16i8Four:
18815 case AArch64::TBXv16i8One:
18816 case AArch64::TBXv16i8Three:
18817 case AArch64::TBXv16i8Two: {
18818 // op: Vd
18819 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18820 op &= UINT64_C(31);
18821 Value |= op;
18822 // op: Vn
18823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18824 op &= UINT64_C(31);
18825 op <<= 5;
18826 Value |= op;
18827 // op: Vm
18828 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18829 op &= UINT64_C(31);
18830 op <<= 16;
18831 Value |= op;
18832 break;
18833 }
18834 case AArch64::SM3TT1A:
18835 case AArch64::SM3TT1B:
18836 case AArch64::SM3TT2A:
18837 case AArch64::SM3TT2B: {
18838 // op: Vd
18839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18840 op &= UINT64_C(31);
18841 Value |= op;
18842 // op: Vn
18843 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18844 op &= UINT64_C(31);
18845 op <<= 5;
18846 Value |= op;
18847 // op: imm
18848 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18849 op &= UINT64_C(3);
18850 op <<= 12;
18851 Value |= op;
18852 // op: Vm
18853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18854 op &= UINT64_C(31);
18855 op <<= 16;
18856 Value |= op;
18857 break;
18858 }
18859 case AArch64::INSR_ZV_B:
18860 case AArch64::INSR_ZV_D:
18861 case AArch64::INSR_ZV_H:
18862 case AArch64::INSR_ZV_S: {
18863 // op: Vm
18864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18865 op &= UINT64_C(31);
18866 op <<= 5;
18867 Value |= op;
18868 // op: Zdn
18869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18870 op &= UINT64_C(31);
18871 Value |= op;
18872 break;
18873 }
18874 case AArch64::LD1Fourv1d:
18875 case AArch64::LD1Fourv2d:
18876 case AArch64::LD1Fourv2s:
18877 case AArch64::LD1Fourv4h:
18878 case AArch64::LD1Fourv4s:
18879 case AArch64::LD1Fourv8b:
18880 case AArch64::LD1Fourv8h:
18881 case AArch64::LD1Fourv16b:
18882 case AArch64::LD1Onev1d:
18883 case AArch64::LD1Onev2d:
18884 case AArch64::LD1Onev2s:
18885 case AArch64::LD1Onev4h:
18886 case AArch64::LD1Onev4s:
18887 case AArch64::LD1Onev8b:
18888 case AArch64::LD1Onev8h:
18889 case AArch64::LD1Onev16b:
18890 case AArch64::LD1Rv1d:
18891 case AArch64::LD1Rv2d:
18892 case AArch64::LD1Rv2s:
18893 case AArch64::LD1Rv4h:
18894 case AArch64::LD1Rv4s:
18895 case AArch64::LD1Rv8b:
18896 case AArch64::LD1Rv8h:
18897 case AArch64::LD1Rv16b:
18898 case AArch64::LD1Threev1d:
18899 case AArch64::LD1Threev2d:
18900 case AArch64::LD1Threev2s:
18901 case AArch64::LD1Threev4h:
18902 case AArch64::LD1Threev4s:
18903 case AArch64::LD1Threev8b:
18904 case AArch64::LD1Threev8h:
18905 case AArch64::LD1Threev16b:
18906 case AArch64::LD1Twov1d:
18907 case AArch64::LD1Twov2d:
18908 case AArch64::LD1Twov2s:
18909 case AArch64::LD1Twov4h:
18910 case AArch64::LD1Twov4s:
18911 case AArch64::LD1Twov8b:
18912 case AArch64::LD1Twov8h:
18913 case AArch64::LD1Twov16b:
18914 case AArch64::LD2Rv1d:
18915 case AArch64::LD2Rv2d:
18916 case AArch64::LD2Rv2s:
18917 case AArch64::LD2Rv4h:
18918 case AArch64::LD2Rv4s:
18919 case AArch64::LD2Rv8b:
18920 case AArch64::LD2Rv8h:
18921 case AArch64::LD2Rv16b:
18922 case AArch64::LD2Twov2d:
18923 case AArch64::LD2Twov2s:
18924 case AArch64::LD2Twov4h:
18925 case AArch64::LD2Twov4s:
18926 case AArch64::LD2Twov8b:
18927 case AArch64::LD2Twov8h:
18928 case AArch64::LD2Twov16b:
18929 case AArch64::LD3Rv1d:
18930 case AArch64::LD3Rv2d:
18931 case AArch64::LD3Rv2s:
18932 case AArch64::LD3Rv4h:
18933 case AArch64::LD3Rv4s:
18934 case AArch64::LD3Rv8b:
18935 case AArch64::LD3Rv8h:
18936 case AArch64::LD3Rv16b:
18937 case AArch64::LD3Threev2d:
18938 case AArch64::LD3Threev2s:
18939 case AArch64::LD3Threev4h:
18940 case AArch64::LD3Threev4s:
18941 case AArch64::LD3Threev8b:
18942 case AArch64::LD3Threev8h:
18943 case AArch64::LD3Threev16b:
18944 case AArch64::LD4Fourv2d:
18945 case AArch64::LD4Fourv2s:
18946 case AArch64::LD4Fourv4h:
18947 case AArch64::LD4Fourv4s:
18948 case AArch64::LD4Fourv8b:
18949 case AArch64::LD4Fourv8h:
18950 case AArch64::LD4Fourv16b:
18951 case AArch64::LD4Rv1d:
18952 case AArch64::LD4Rv2d:
18953 case AArch64::LD4Rv2s:
18954 case AArch64::LD4Rv4h:
18955 case AArch64::LD4Rv4s:
18956 case AArch64::LD4Rv8b:
18957 case AArch64::LD4Rv8h:
18958 case AArch64::LD4Rv16b:
18959 case AArch64::ST1Fourv1d:
18960 case AArch64::ST1Fourv2d:
18961 case AArch64::ST1Fourv2s:
18962 case AArch64::ST1Fourv4h:
18963 case AArch64::ST1Fourv4s:
18964 case AArch64::ST1Fourv8b:
18965 case AArch64::ST1Fourv8h:
18966 case AArch64::ST1Fourv16b:
18967 case AArch64::ST1Onev1d:
18968 case AArch64::ST1Onev2d:
18969 case AArch64::ST1Onev2s:
18970 case AArch64::ST1Onev4h:
18971 case AArch64::ST1Onev4s:
18972 case AArch64::ST1Onev8b:
18973 case AArch64::ST1Onev8h:
18974 case AArch64::ST1Onev16b:
18975 case AArch64::ST1Threev1d:
18976 case AArch64::ST1Threev2d:
18977 case AArch64::ST1Threev2s:
18978 case AArch64::ST1Threev4h:
18979 case AArch64::ST1Threev4s:
18980 case AArch64::ST1Threev8b:
18981 case AArch64::ST1Threev8h:
18982 case AArch64::ST1Threev16b:
18983 case AArch64::ST1Twov1d:
18984 case AArch64::ST1Twov2d:
18985 case AArch64::ST1Twov2s:
18986 case AArch64::ST1Twov4h:
18987 case AArch64::ST1Twov4s:
18988 case AArch64::ST1Twov8b:
18989 case AArch64::ST1Twov8h:
18990 case AArch64::ST1Twov16b:
18991 case AArch64::ST2Twov2d:
18992 case AArch64::ST2Twov2s:
18993 case AArch64::ST2Twov4h:
18994 case AArch64::ST2Twov4s:
18995 case AArch64::ST2Twov8b:
18996 case AArch64::ST2Twov8h:
18997 case AArch64::ST2Twov16b:
18998 case AArch64::ST3Threev2d:
18999 case AArch64::ST3Threev2s:
19000 case AArch64::ST3Threev4h:
19001 case AArch64::ST3Threev4s:
19002 case AArch64::ST3Threev8b:
19003 case AArch64::ST3Threev8h:
19004 case AArch64::ST3Threev16b:
19005 case AArch64::ST4Fourv2d:
19006 case AArch64::ST4Fourv2s:
19007 case AArch64::ST4Fourv4h:
19008 case AArch64::ST4Fourv4s:
19009 case AArch64::ST4Fourv8b:
19010 case AArch64::ST4Fourv8h:
19011 case AArch64::ST4Fourv16b: {
19012 // op: Vt
19013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19014 op &= UINT64_C(31);
19015 Value |= op;
19016 // op: Rn
19017 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19018 op &= UINT64_C(31);
19019 op <<= 5;
19020 Value |= op;
19021 break;
19022 }
19023 case AArch64::STL1: {
19024 // op: Vt
19025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19026 op &= UINT64_C(31);
19027 Value |= op;
19028 // op: Rn
19029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19030 op &= UINT64_C(31);
19031 op <<= 5;
19032 Value |= op;
19033 // op: Q
19034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19035 op &= UINT64_C(1);
19036 op <<= 30;
19037 Value |= op;
19038 break;
19039 }
19040 case AArch64::ST1i32:
19041 case AArch64::ST2i32:
19042 case AArch64::ST3i32:
19043 case AArch64::ST4i32: {
19044 // op: Vt
19045 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19046 op &= UINT64_C(31);
19047 Value |= op;
19048 // op: Rn
19049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19050 op &= UINT64_C(31);
19051 op <<= 5;
19052 Value |= op;
19053 // op: idx
19054 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19055 Value |= (op & UINT64_C(2)) << 29;
19056 Value |= (op & UINT64_C(1)) << 12;
19057 break;
19058 }
19059 case AArch64::ST1i16:
19060 case AArch64::ST2i16:
19061 case AArch64::ST3i16:
19062 case AArch64::ST4i16: {
19063 // op: Vt
19064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19065 op &= UINT64_C(31);
19066 Value |= op;
19067 // op: Rn
19068 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19069 op &= UINT64_C(31);
19070 op <<= 5;
19071 Value |= op;
19072 // op: idx
19073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19074 Value |= (op & UINT64_C(4)) << 28;
19075 Value |= (op & UINT64_C(3)) << 11;
19076 break;
19077 }
19078 case AArch64::ST1i8:
19079 case AArch64::ST2i8:
19080 case AArch64::ST3i8:
19081 case AArch64::ST4i8: {
19082 // op: Vt
19083 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19084 op &= UINT64_C(31);
19085 Value |= op;
19086 // op: Rn
19087 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19088 op &= UINT64_C(31);
19089 op <<= 5;
19090 Value |= op;
19091 // op: idx
19092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19093 Value |= (op & UINT64_C(8)) << 27;
19094 Value |= (op & UINT64_C(7)) << 10;
19095 break;
19096 }
19097 case AArch64::ST1i64:
19098 case AArch64::ST2i64:
19099 case AArch64::ST3i64:
19100 case AArch64::ST4i64: {
19101 // op: Vt
19102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19103 op &= UINT64_C(31);
19104 Value |= op;
19105 // op: Rn
19106 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19107 op &= UINT64_C(31);
19108 op <<= 5;
19109 Value |= op;
19110 // op: idx
19111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19112 op &= UINT64_C(1);
19113 op <<= 30;
19114 Value |= op;
19115 break;
19116 }
19117 case AArch64::LD1Fourv1d_POST:
19118 case AArch64::LD1Fourv2d_POST:
19119 case AArch64::LD1Fourv2s_POST:
19120 case AArch64::LD1Fourv4h_POST:
19121 case AArch64::LD1Fourv4s_POST:
19122 case AArch64::LD1Fourv8b_POST:
19123 case AArch64::LD1Fourv8h_POST:
19124 case AArch64::LD1Fourv16b_POST:
19125 case AArch64::LD1Onev1d_POST:
19126 case AArch64::LD1Onev2d_POST:
19127 case AArch64::LD1Onev2s_POST:
19128 case AArch64::LD1Onev4h_POST:
19129 case AArch64::LD1Onev4s_POST:
19130 case AArch64::LD1Onev8b_POST:
19131 case AArch64::LD1Onev8h_POST:
19132 case AArch64::LD1Onev16b_POST:
19133 case AArch64::LD1Rv1d_POST:
19134 case AArch64::LD1Rv2d_POST:
19135 case AArch64::LD1Rv2s_POST:
19136 case AArch64::LD1Rv4h_POST:
19137 case AArch64::LD1Rv4s_POST:
19138 case AArch64::LD1Rv8b_POST:
19139 case AArch64::LD1Rv8h_POST:
19140 case AArch64::LD1Rv16b_POST:
19141 case AArch64::LD1Threev1d_POST:
19142 case AArch64::LD1Threev2d_POST:
19143 case AArch64::LD1Threev2s_POST:
19144 case AArch64::LD1Threev4h_POST:
19145 case AArch64::LD1Threev4s_POST:
19146 case AArch64::LD1Threev8b_POST:
19147 case AArch64::LD1Threev8h_POST:
19148 case AArch64::LD1Threev16b_POST:
19149 case AArch64::LD1Twov1d_POST:
19150 case AArch64::LD1Twov2d_POST:
19151 case AArch64::LD1Twov2s_POST:
19152 case AArch64::LD1Twov4h_POST:
19153 case AArch64::LD1Twov4s_POST:
19154 case AArch64::LD1Twov8b_POST:
19155 case AArch64::LD1Twov8h_POST:
19156 case AArch64::LD1Twov16b_POST:
19157 case AArch64::LD2Rv1d_POST:
19158 case AArch64::LD2Rv2d_POST:
19159 case AArch64::LD2Rv2s_POST:
19160 case AArch64::LD2Rv4h_POST:
19161 case AArch64::LD2Rv4s_POST:
19162 case AArch64::LD2Rv8b_POST:
19163 case AArch64::LD2Rv8h_POST:
19164 case AArch64::LD2Rv16b_POST:
19165 case AArch64::LD2Twov2d_POST:
19166 case AArch64::LD2Twov2s_POST:
19167 case AArch64::LD2Twov4h_POST:
19168 case AArch64::LD2Twov4s_POST:
19169 case AArch64::LD2Twov8b_POST:
19170 case AArch64::LD2Twov8h_POST:
19171 case AArch64::LD2Twov16b_POST:
19172 case AArch64::LD3Rv1d_POST:
19173 case AArch64::LD3Rv2d_POST:
19174 case AArch64::LD3Rv2s_POST:
19175 case AArch64::LD3Rv4h_POST:
19176 case AArch64::LD3Rv4s_POST:
19177 case AArch64::LD3Rv8b_POST:
19178 case AArch64::LD3Rv8h_POST:
19179 case AArch64::LD3Rv16b_POST:
19180 case AArch64::LD3Threev2d_POST:
19181 case AArch64::LD3Threev2s_POST:
19182 case AArch64::LD3Threev4h_POST:
19183 case AArch64::LD3Threev4s_POST:
19184 case AArch64::LD3Threev8b_POST:
19185 case AArch64::LD3Threev8h_POST:
19186 case AArch64::LD3Threev16b_POST:
19187 case AArch64::LD4Fourv2d_POST:
19188 case AArch64::LD4Fourv2s_POST:
19189 case AArch64::LD4Fourv4h_POST:
19190 case AArch64::LD4Fourv4s_POST:
19191 case AArch64::LD4Fourv8b_POST:
19192 case AArch64::LD4Fourv8h_POST:
19193 case AArch64::LD4Fourv16b_POST:
19194 case AArch64::LD4Rv1d_POST:
19195 case AArch64::LD4Rv2d_POST:
19196 case AArch64::LD4Rv2s_POST:
19197 case AArch64::LD4Rv4h_POST:
19198 case AArch64::LD4Rv4s_POST:
19199 case AArch64::LD4Rv8b_POST:
19200 case AArch64::LD4Rv8h_POST:
19201 case AArch64::LD4Rv16b_POST:
19202 case AArch64::ST1Fourv1d_POST:
19203 case AArch64::ST1Fourv2d_POST:
19204 case AArch64::ST1Fourv2s_POST:
19205 case AArch64::ST1Fourv4h_POST:
19206 case AArch64::ST1Fourv4s_POST:
19207 case AArch64::ST1Fourv8b_POST:
19208 case AArch64::ST1Fourv8h_POST:
19209 case AArch64::ST1Fourv16b_POST:
19210 case AArch64::ST1Onev1d_POST:
19211 case AArch64::ST1Onev2d_POST:
19212 case AArch64::ST1Onev2s_POST:
19213 case AArch64::ST1Onev4h_POST:
19214 case AArch64::ST1Onev4s_POST:
19215 case AArch64::ST1Onev8b_POST:
19216 case AArch64::ST1Onev8h_POST:
19217 case AArch64::ST1Onev16b_POST:
19218 case AArch64::ST1Threev1d_POST:
19219 case AArch64::ST1Threev2d_POST:
19220 case AArch64::ST1Threev2s_POST:
19221 case AArch64::ST1Threev4h_POST:
19222 case AArch64::ST1Threev4s_POST:
19223 case AArch64::ST1Threev8b_POST:
19224 case AArch64::ST1Threev8h_POST:
19225 case AArch64::ST1Threev16b_POST:
19226 case AArch64::ST1Twov1d_POST:
19227 case AArch64::ST1Twov2d_POST:
19228 case AArch64::ST1Twov2s_POST:
19229 case AArch64::ST1Twov4h_POST:
19230 case AArch64::ST1Twov4s_POST:
19231 case AArch64::ST1Twov8b_POST:
19232 case AArch64::ST1Twov8h_POST:
19233 case AArch64::ST1Twov16b_POST:
19234 case AArch64::ST2Twov2d_POST:
19235 case AArch64::ST2Twov2s_POST:
19236 case AArch64::ST2Twov4h_POST:
19237 case AArch64::ST2Twov4s_POST:
19238 case AArch64::ST2Twov8b_POST:
19239 case AArch64::ST2Twov8h_POST:
19240 case AArch64::ST2Twov16b_POST:
19241 case AArch64::ST3Threev2d_POST:
19242 case AArch64::ST3Threev2s_POST:
19243 case AArch64::ST3Threev4h_POST:
19244 case AArch64::ST3Threev4s_POST:
19245 case AArch64::ST3Threev8b_POST:
19246 case AArch64::ST3Threev8h_POST:
19247 case AArch64::ST3Threev16b_POST:
19248 case AArch64::ST4Fourv2d_POST:
19249 case AArch64::ST4Fourv2s_POST:
19250 case AArch64::ST4Fourv4h_POST:
19251 case AArch64::ST4Fourv4s_POST:
19252 case AArch64::ST4Fourv8b_POST:
19253 case AArch64::ST4Fourv8h_POST:
19254 case AArch64::ST4Fourv16b_POST: {
19255 // op: Vt
19256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19257 op &= UINT64_C(31);
19258 Value |= op;
19259 // op: Rn
19260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19261 op &= UINT64_C(31);
19262 op <<= 5;
19263 Value |= op;
19264 // op: Xm
19265 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19266 op &= UINT64_C(31);
19267 op <<= 16;
19268 Value |= op;
19269 break;
19270 }
19271 case AArch64::LDAP1: {
19272 // op: Vt
19273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19274 op &= UINT64_C(31);
19275 Value |= op;
19276 // op: Rn
19277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19278 op &= UINT64_C(31);
19279 op <<= 5;
19280 Value |= op;
19281 // op: Q
19282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19283 op &= UINT64_C(1);
19284 op <<= 30;
19285 Value |= op;
19286 break;
19287 }
19288 case AArch64::LD1i32:
19289 case AArch64::LD2i32:
19290 case AArch64::LD3i32:
19291 case AArch64::LD4i32: {
19292 // op: Vt
19293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19294 op &= UINT64_C(31);
19295 Value |= op;
19296 // op: Rn
19297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19298 op &= UINT64_C(31);
19299 op <<= 5;
19300 Value |= op;
19301 // op: idx
19302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19303 Value |= (op & UINT64_C(2)) << 29;
19304 Value |= (op & UINT64_C(1)) << 12;
19305 break;
19306 }
19307 case AArch64::ST1i32_POST:
19308 case AArch64::ST2i32_POST:
19309 case AArch64::ST3i32_POST:
19310 case AArch64::ST4i32_POST: {
19311 // op: Vt
19312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19313 op &= UINT64_C(31);
19314 Value |= op;
19315 // op: Rn
19316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19317 op &= UINT64_C(31);
19318 op <<= 5;
19319 Value |= op;
19320 // op: idx
19321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19322 Value |= (op & UINT64_C(2)) << 29;
19323 Value |= (op & UINT64_C(1)) << 12;
19324 // op: Xm
19325 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19326 op &= UINT64_C(31);
19327 op <<= 16;
19328 Value |= op;
19329 break;
19330 }
19331 case AArch64::LD1i16:
19332 case AArch64::LD2i16:
19333 case AArch64::LD3i16:
19334 case AArch64::LD4i16: {
19335 // op: Vt
19336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19337 op &= UINT64_C(31);
19338 Value |= op;
19339 // op: Rn
19340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19341 op &= UINT64_C(31);
19342 op <<= 5;
19343 Value |= op;
19344 // op: idx
19345 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19346 Value |= (op & UINT64_C(4)) << 28;
19347 Value |= (op & UINT64_C(3)) << 11;
19348 break;
19349 }
19350 case AArch64::ST1i16_POST:
19351 case AArch64::ST2i16_POST:
19352 case AArch64::ST3i16_POST:
19353 case AArch64::ST4i16_POST: {
19354 // op: Vt
19355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19356 op &= UINT64_C(31);
19357 Value |= op;
19358 // op: Rn
19359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19360 op &= UINT64_C(31);
19361 op <<= 5;
19362 Value |= op;
19363 // op: idx
19364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19365 Value |= (op & UINT64_C(4)) << 28;
19366 Value |= (op & UINT64_C(3)) << 11;
19367 // op: Xm
19368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19369 op &= UINT64_C(31);
19370 op <<= 16;
19371 Value |= op;
19372 break;
19373 }
19374 case AArch64::LD1i8:
19375 case AArch64::LD2i8:
19376 case AArch64::LD3i8:
19377 case AArch64::LD4i8: {
19378 // op: Vt
19379 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19380 op &= UINT64_C(31);
19381 Value |= op;
19382 // op: Rn
19383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19384 op &= UINT64_C(31);
19385 op <<= 5;
19386 Value |= op;
19387 // op: idx
19388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19389 Value |= (op & UINT64_C(8)) << 27;
19390 Value |= (op & UINT64_C(7)) << 10;
19391 break;
19392 }
19393 case AArch64::ST1i8_POST:
19394 case AArch64::ST2i8_POST:
19395 case AArch64::ST3i8_POST:
19396 case AArch64::ST4i8_POST: {
19397 // op: Vt
19398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19399 op &= UINT64_C(31);
19400 Value |= op;
19401 // op: Rn
19402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19403 op &= UINT64_C(31);
19404 op <<= 5;
19405 Value |= op;
19406 // op: idx
19407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19408 Value |= (op & UINT64_C(8)) << 27;
19409 Value |= (op & UINT64_C(7)) << 10;
19410 // op: Xm
19411 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19412 op &= UINT64_C(31);
19413 op <<= 16;
19414 Value |= op;
19415 break;
19416 }
19417 case AArch64::LD1i64:
19418 case AArch64::LD2i64:
19419 case AArch64::LD3i64:
19420 case AArch64::LD4i64: {
19421 // op: Vt
19422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19423 op &= UINT64_C(31);
19424 Value |= op;
19425 // op: Rn
19426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19427 op &= UINT64_C(31);
19428 op <<= 5;
19429 Value |= op;
19430 // op: idx
19431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19432 op &= UINT64_C(1);
19433 op <<= 30;
19434 Value |= op;
19435 break;
19436 }
19437 case AArch64::ST1i64_POST:
19438 case AArch64::ST2i64_POST:
19439 case AArch64::ST3i64_POST:
19440 case AArch64::ST4i64_POST: {
19441 // op: Vt
19442 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19443 op &= UINT64_C(31);
19444 Value |= op;
19445 // op: Rn
19446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19447 op &= UINT64_C(31);
19448 op <<= 5;
19449 Value |= op;
19450 // op: idx
19451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19452 op &= UINT64_C(1);
19453 op <<= 30;
19454 Value |= op;
19455 // op: Xm
19456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19457 op &= UINT64_C(31);
19458 op <<= 16;
19459 Value |= op;
19460 break;
19461 }
19462 case AArch64::LD1i32_POST:
19463 case AArch64::LD2i32_POST:
19464 case AArch64::LD3i32_POST:
19465 case AArch64::LD4i32_POST: {
19466 // op: Vt
19467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19468 op &= UINT64_C(31);
19469 Value |= op;
19470 // op: Rn
19471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19472 op &= UINT64_C(31);
19473 op <<= 5;
19474 Value |= op;
19475 // op: idx
19476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19477 Value |= (op & UINT64_C(2)) << 29;
19478 Value |= (op & UINT64_C(1)) << 12;
19479 // op: Xm
19480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
19481 op &= UINT64_C(31);
19482 op <<= 16;
19483 Value |= op;
19484 break;
19485 }
19486 case AArch64::LD1i16_POST:
19487 case AArch64::LD2i16_POST:
19488 case AArch64::LD3i16_POST:
19489 case AArch64::LD4i16_POST: {
19490 // op: Vt
19491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19492 op &= UINT64_C(31);
19493 Value |= op;
19494 // op: Rn
19495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19496 op &= UINT64_C(31);
19497 op <<= 5;
19498 Value |= op;
19499 // op: idx
19500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19501 Value |= (op & UINT64_C(4)) << 28;
19502 Value |= (op & UINT64_C(3)) << 11;
19503 // op: Xm
19504 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
19505 op &= UINT64_C(31);
19506 op <<= 16;
19507 Value |= op;
19508 break;
19509 }
19510 case AArch64::LD1i8_POST:
19511 case AArch64::LD2i8_POST:
19512 case AArch64::LD3i8_POST:
19513 case AArch64::LD4i8_POST: {
19514 // op: Vt
19515 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19516 op &= UINT64_C(31);
19517 Value |= op;
19518 // op: Rn
19519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19520 op &= UINT64_C(31);
19521 op <<= 5;
19522 Value |= op;
19523 // op: idx
19524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19525 Value |= (op & UINT64_C(8)) << 27;
19526 Value |= (op & UINT64_C(7)) << 10;
19527 // op: Xm
19528 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
19529 op &= UINT64_C(31);
19530 op <<= 16;
19531 Value |= op;
19532 break;
19533 }
19534 case AArch64::LD1i64_POST:
19535 case AArch64::LD2i64_POST:
19536 case AArch64::LD3i64_POST:
19537 case AArch64::LD4i64_POST: {
19538 // op: Vt
19539 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19540 op &= UINT64_C(31);
19541 Value |= op;
19542 // op: Rn
19543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19544 op &= UINT64_C(31);
19545 op <<= 5;
19546 Value |= op;
19547 // op: idx
19548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19549 op &= UINT64_C(1);
19550 op <<= 30;
19551 Value |= op;
19552 // op: Xm
19553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
19554 op &= UINT64_C(31);
19555 op <<= 16;
19556 Value |= op;
19557 break;
19558 }
19559 case AArch64::STLTXRW:
19560 case AArch64::STLTXRX:
19561 case AArch64::STLXRB:
19562 case AArch64::STLXRH:
19563 case AArch64::STLXRW:
19564 case AArch64::STLXRX:
19565 case AArch64::STXRB:
19566 case AArch64::STXRH:
19567 case AArch64::STXRW:
19568 case AArch64::STXRX: {
19569 // op: Ws
19570 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19571 op &= UINT64_C(31);
19572 op <<= 16;
19573 Value |= op;
19574 // op: Rt
19575 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19576 op &= UINT64_C(31);
19577 Value |= op;
19578 // op: Rn
19579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19580 op &= UINT64_C(31);
19581 op <<= 5;
19582 Value |= op;
19583 Value = fixLoadStoreExclusive<1,0>(MI, EncodedValue: Value, STI);
19584 break;
19585 }
19586 case AArch64::STLXPW:
19587 case AArch64::STLXPX:
19588 case AArch64::STXPW:
19589 case AArch64::STXPX: {
19590 // op: Ws
19591 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19592 op &= UINT64_C(31);
19593 op <<= 16;
19594 Value |= op;
19595 // op: Rt
19596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19597 op &= UINT64_C(31);
19598 Value |= op;
19599 // op: Rt2
19600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19601 op &= UINT64_C(31);
19602 op <<= 10;
19603 Value |= op;
19604 // op: Rn
19605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19606 op &= UINT64_C(31);
19607 op <<= 5;
19608 Value |= op;
19609 break;
19610 }
19611 case AArch64::ADR:
19612 case AArch64::ADRP: {
19613 // op: Xd
19614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19615 op &= UINT64_C(31);
19616 Value |= op;
19617 // op: label
19618 op = getAdrLabelOpValue(MI, OpIdx: 1, Fixups, STI);
19619 Value |= (op & UINT64_C(3)) << 29;
19620 Value |= (op & UINT64_C(2097148)) << 3;
19621 break;
19622 }
19623 case AArch64::APAS: {
19624 // op: Xt
19625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19626 op &= UINT64_C(31);
19627 Value |= op;
19628 break;
19629 }
19630 case AArch64::BFMOP4A_M2Z2Z_H:
19631 case AArch64::BFMOP4S_M2Z2Z_H:
19632 case AArch64::FMOP4A_M2Z2Z_BtoH:
19633 case AArch64::FMOP4A_M2Z2Z_H:
19634 case AArch64::FMOP4S_M2Z2Z_H: {
19635 // op: ZAda
19636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19637 op &= UINT64_C(1);
19638 Value |= op;
19639 // op: Zn
19640 op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI);
19641 op &= UINT64_C(7);
19642 op <<= 6;
19643 Value |= op;
19644 // op: Zm
19645 op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI);
19646 op &= UINT64_C(7);
19647 op <<= 17;
19648 Value |= op;
19649 break;
19650 }
19651 case AArch64::BFMOP4A_M2ZZ_H:
19652 case AArch64::BFMOP4S_M2ZZ_H:
19653 case AArch64::FMOP4A_M2ZZ_BtoH:
19654 case AArch64::FMOP4A_M2ZZ_H:
19655 case AArch64::FMOP4S_M2ZZ_H: {
19656 // op: ZAda
19657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19658 op &= UINT64_C(1);
19659 Value |= op;
19660 // op: Zn
19661 op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI);
19662 op &= UINT64_C(7);
19663 op <<= 6;
19664 Value |= op;
19665 // op: Zm
19666 op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI);
19667 op &= UINT64_C(7);
19668 op <<= 17;
19669 Value |= op;
19670 break;
19671 }
19672 case AArch64::BFTMOPA_M2ZZZI_HtoH:
19673 case AArch64::FTMOPA_M2ZZZI_BtoH:
19674 case AArch64::FTMOPA_M2ZZZI_HtoH: {
19675 // op: ZAda
19676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19677 op &= UINT64_C(1);
19678 Value |= op;
19679 // op: Zn
19680 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI);
19681 op &= UINT64_C(15);
19682 op <<= 6;
19683 Value |= op;
19684 // op: Zm
19685 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19686 op &= UINT64_C(31);
19687 op <<= 16;
19688 Value |= op;
19689 // op: Zk
19690 op = EncodeZK(MI, OpIdx: 4, Fixups, STI);
19691 op &= UINT64_C(7);
19692 op <<= 10;
19693 Value |= op;
19694 // op: imm
19695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
19696 op &= UINT64_C(3);
19697 op <<= 4;
19698 Value |= op;
19699 break;
19700 }
19701 case AArch64::BFMOP4A_MZ2Z_H:
19702 case AArch64::BFMOP4S_MZ2Z_H:
19703 case AArch64::FMOP4A_MZ2Z_BtoH:
19704 case AArch64::FMOP4A_MZ2Z_H:
19705 case AArch64::FMOP4S_MZ2Z_H: {
19706 // op: ZAda
19707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19708 op &= UINT64_C(1);
19709 Value |= op;
19710 // op: Zn
19711 op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI);
19712 op &= UINT64_C(7);
19713 op <<= 6;
19714 Value |= op;
19715 // op: Zm
19716 op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI);
19717 op &= UINT64_C(7);
19718 op <<= 17;
19719 Value |= op;
19720 break;
19721 }
19722 case AArch64::BFMOP4A_MZZ_H:
19723 case AArch64::BFMOP4S_MZZ_H:
19724 case AArch64::FMOP4A_MZZ_BtoH:
19725 case AArch64::FMOP4A_MZZ_H:
19726 case AArch64::FMOP4S_MZZ_H: {
19727 // op: ZAda
19728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19729 op &= UINT64_C(1);
19730 Value |= op;
19731 // op: Zn
19732 op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI);
19733 op &= UINT64_C(7);
19734 op <<= 6;
19735 Value |= op;
19736 // op: Zm
19737 op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI);
19738 op &= UINT64_C(7);
19739 op <<= 17;
19740 Value |= op;
19741 break;
19742 }
19743 case AArch64::BFMOP4A_M2Z2Z_S:
19744 case AArch64::BFMOP4S_M2Z2Z_S:
19745 case AArch64::FMOP4A_M2Z2Z_BtoS:
19746 case AArch64::FMOP4A_M2Z2Z_HtoS:
19747 case AArch64::FMOP4A_M2Z2Z_S:
19748 case AArch64::FMOP4S_M2Z2Z_HtoS:
19749 case AArch64::FMOP4S_M2Z2Z_S:
19750 case AArch64::SMOP4A_M2Z2Z_BToS:
19751 case AArch64::SMOP4A_M2Z2Z_HToS:
19752 case AArch64::SMOP4S_M2Z2Z_BToS:
19753 case AArch64::SMOP4S_M2Z2Z_HToS:
19754 case AArch64::SUMOP4A_M2Z2Z_BToS:
19755 case AArch64::SUMOP4S_M2Z2Z_BToS:
19756 case AArch64::UMOP4A_M2Z2Z_BToS:
19757 case AArch64::UMOP4A_M2Z2Z_HToS:
19758 case AArch64::UMOP4S_M2Z2Z_BToS:
19759 case AArch64::UMOP4S_M2Z2Z_HToS:
19760 case AArch64::USMOP4A_M2Z2Z_BToS:
19761 case AArch64::USMOP4S_M2Z2Z_BToS: {
19762 // op: ZAda
19763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19764 op &= UINT64_C(3);
19765 Value |= op;
19766 // op: Zn
19767 op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI);
19768 op &= UINT64_C(7);
19769 op <<= 6;
19770 Value |= op;
19771 // op: Zm
19772 op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI);
19773 op &= UINT64_C(7);
19774 op <<= 17;
19775 Value |= op;
19776 break;
19777 }
19778 case AArch64::BFMOP4A_M2ZZ_S:
19779 case AArch64::BFMOP4S_M2ZZ_S:
19780 case AArch64::FMOP4A_M2ZZ_BtoS:
19781 case AArch64::FMOP4A_M2ZZ_HtoS:
19782 case AArch64::FMOP4A_M2ZZ_S:
19783 case AArch64::FMOP4S_M2ZZ_HtoS:
19784 case AArch64::FMOP4S_M2ZZ_S:
19785 case AArch64::SMOP4A_M2ZZ_BToS:
19786 case AArch64::SMOP4A_M2ZZ_HToS:
19787 case AArch64::SMOP4S_M2ZZ_BToS:
19788 case AArch64::SMOP4S_M2ZZ_HToS:
19789 case AArch64::SUMOP4A_M2ZZ_BToS:
19790 case AArch64::SUMOP4S_M2ZZ_BToS:
19791 case AArch64::UMOP4A_M2ZZ_BToS:
19792 case AArch64::UMOP4A_M2ZZ_HToS:
19793 case AArch64::UMOP4S_M2ZZ_BToS:
19794 case AArch64::UMOP4S_M2ZZ_HToS:
19795 case AArch64::USMOP4A_M2ZZ_BToS:
19796 case AArch64::USMOP4S_M2ZZ_BToS: {
19797 // op: ZAda
19798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19799 op &= UINT64_C(3);
19800 Value |= op;
19801 // op: Zn
19802 op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI);
19803 op &= UINT64_C(7);
19804 op <<= 6;
19805 Value |= op;
19806 // op: Zm
19807 op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI);
19808 op &= UINT64_C(7);
19809 op <<= 17;
19810 Value |= op;
19811 break;
19812 }
19813 case AArch64::BFTMOPA_M2ZZZI_HtoS:
19814 case AArch64::FTMOPA_M2ZZZI_BtoS:
19815 case AArch64::FTMOPA_M2ZZZI_HtoS:
19816 case AArch64::FTMOPA_M2ZZZI_StoS:
19817 case AArch64::STMOPA_M2ZZZI_BtoS:
19818 case AArch64::STMOPA_M2ZZZI_HtoS:
19819 case AArch64::SUTMOPA_M2ZZZI_BtoS:
19820 case AArch64::USTMOPA_M2ZZZI_BtoS:
19821 case AArch64::UTMOPA_M2ZZZI_BtoS:
19822 case AArch64::UTMOPA_M2ZZZI_HtoS: {
19823 // op: ZAda
19824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19825 op &= UINT64_C(3);
19826 Value |= op;
19827 // op: Zn
19828 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI);
19829 op &= UINT64_C(15);
19830 op <<= 6;
19831 Value |= op;
19832 // op: Zm
19833 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19834 op &= UINT64_C(31);
19835 op <<= 16;
19836 Value |= op;
19837 // op: Zk
19838 op = EncodeZK(MI, OpIdx: 4, Fixups, STI);
19839 op &= UINT64_C(7);
19840 op <<= 10;
19841 Value |= op;
19842 // op: imm
19843 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
19844 op &= UINT64_C(3);
19845 op <<= 4;
19846 Value |= op;
19847 break;
19848 }
19849 case AArch64::BFMOP4A_MZ2Z_S:
19850 case AArch64::BFMOP4S_MZ2Z_S:
19851 case AArch64::FMOP4A_MZ2Z_BtoS:
19852 case AArch64::FMOP4A_MZ2Z_HtoS:
19853 case AArch64::FMOP4A_MZ2Z_S:
19854 case AArch64::FMOP4S_MZ2Z_HtoS:
19855 case AArch64::FMOP4S_MZ2Z_S:
19856 case AArch64::SMOP4A_MZ2Z_BToS:
19857 case AArch64::SMOP4A_MZ2Z_HToS:
19858 case AArch64::SMOP4S_MZ2Z_BToS:
19859 case AArch64::SMOP4S_MZ2Z_HToS:
19860 case AArch64::SUMOP4A_MZ2Z_BToS:
19861 case AArch64::SUMOP4S_MZ2Z_BToS:
19862 case AArch64::UMOP4A_MZ2Z_BToS:
19863 case AArch64::UMOP4A_MZ2Z_HToS:
19864 case AArch64::UMOP4S_MZ2Z_BToS:
19865 case AArch64::UMOP4S_MZ2Z_HToS:
19866 case AArch64::USMOP4A_MZ2Z_BToS:
19867 case AArch64::USMOP4S_MZ2Z_BToS: {
19868 // op: ZAda
19869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19870 op &= UINT64_C(3);
19871 Value |= op;
19872 // op: Zn
19873 op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI);
19874 op &= UINT64_C(7);
19875 op <<= 6;
19876 Value |= op;
19877 // op: Zm
19878 op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI);
19879 op &= UINT64_C(7);
19880 op <<= 17;
19881 Value |= op;
19882 break;
19883 }
19884 case AArch64::BFMOP4A_MZZ_S:
19885 case AArch64::BFMOP4S_MZZ_S:
19886 case AArch64::FMOP4A_MZZ_BtoS:
19887 case AArch64::FMOP4A_MZZ_HtoS:
19888 case AArch64::FMOP4A_MZZ_S:
19889 case AArch64::FMOP4S_MZZ_HtoS:
19890 case AArch64::FMOP4S_MZZ_S:
19891 case AArch64::SMOP4A_MZZ_BToS:
19892 case AArch64::SMOP4A_MZZ_HToS:
19893 case AArch64::SMOP4S_MZZ_BToS:
19894 case AArch64::SMOP4S_MZZ_HToS:
19895 case AArch64::SUMOP4A_MZZ_BToS:
19896 case AArch64::SUMOP4S_MZZ_BToS:
19897 case AArch64::UMOP4A_MZZ_BToS:
19898 case AArch64::UMOP4A_MZZ_HToS:
19899 case AArch64::UMOP4S_MZZ_BToS:
19900 case AArch64::UMOP4S_MZZ_HToS:
19901 case AArch64::USMOP4A_MZZ_BToS:
19902 case AArch64::USMOP4S_MZZ_BToS: {
19903 // op: ZAda
19904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19905 op &= UINT64_C(3);
19906 Value |= op;
19907 // op: Zn
19908 op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI);
19909 op &= UINT64_C(7);
19910 op <<= 6;
19911 Value |= op;
19912 // op: Zm
19913 op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI);
19914 op &= UINT64_C(7);
19915 op <<= 17;
19916 Value |= op;
19917 break;
19918 }
19919 case AArch64::FMOP4A_M2Z2Z_D:
19920 case AArch64::FMOP4S_M2Z2Z_D:
19921 case AArch64::SMOP4A_M2Z2Z_HtoD:
19922 case AArch64::SMOP4S_M2Z2Z_HtoD:
19923 case AArch64::SUMOP4A_M2Z2Z_HtoD:
19924 case AArch64::SUMOP4S_M2Z2Z_HtoD:
19925 case AArch64::UMOP4A_M2Z2Z_HtoD:
19926 case AArch64::UMOP4S_M2Z2Z_HtoD:
19927 case AArch64::USMOP4A_M2Z2Z_HtoD:
19928 case AArch64::USMOP4S_M2Z2Z_HtoD: {
19929 // op: ZAda
19930 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19931 op &= UINT64_C(7);
19932 Value |= op;
19933 // op: Zn
19934 op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI);
19935 op &= UINT64_C(7);
19936 op <<= 6;
19937 Value |= op;
19938 // op: Zm
19939 op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI);
19940 op &= UINT64_C(7);
19941 op <<= 17;
19942 Value |= op;
19943 break;
19944 }
19945 case AArch64::FMOP4A_M2ZZ_D:
19946 case AArch64::FMOP4S_M2ZZ_D:
19947 case AArch64::SMOP4A_M2ZZ_HtoD:
19948 case AArch64::SMOP4S_M2ZZ_HtoD:
19949 case AArch64::SUMOP4A_M2ZZ_HtoD:
19950 case AArch64::SUMOP4S_M2ZZ_HtoD:
19951 case AArch64::UMOP4A_M2ZZ_HtoD:
19952 case AArch64::UMOP4S_M2ZZ_HtoD:
19953 case AArch64::USMOP4A_M2ZZ_HtoD:
19954 case AArch64::USMOP4S_M2ZZ_HtoD: {
19955 // op: ZAda
19956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19957 op &= UINT64_C(7);
19958 Value |= op;
19959 // op: Zn
19960 op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI);
19961 op &= UINT64_C(7);
19962 op <<= 6;
19963 Value |= op;
19964 // op: Zm
19965 op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI);
19966 op &= UINT64_C(7);
19967 op <<= 17;
19968 Value |= op;
19969 break;
19970 }
19971 case AArch64::FMOP4A_MZ2Z_D:
19972 case AArch64::FMOP4S_MZ2Z_D:
19973 case AArch64::SMOP4A_MZ2Z_HtoD:
19974 case AArch64::SMOP4S_MZ2Z_HtoD:
19975 case AArch64::SUMOP4A_MZ2Z_HtoD:
19976 case AArch64::SUMOP4S_MZ2Z_HtoD:
19977 case AArch64::UMOP4A_MZ2Z_HtoD:
19978 case AArch64::UMOP4S_MZ2Z_HtoD:
19979 case AArch64::USMOP4A_MZ2Z_HtoD:
19980 case AArch64::USMOP4S_MZ2Z_HtoD: {
19981 // op: ZAda
19982 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19983 op &= UINT64_C(7);
19984 Value |= op;
19985 // op: Zn
19986 op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI);
19987 op &= UINT64_C(7);
19988 op <<= 6;
19989 Value |= op;
19990 // op: Zm
19991 op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI);
19992 op &= UINT64_C(7);
19993 op <<= 17;
19994 Value |= op;
19995 break;
19996 }
19997 case AArch64::FMOP4A_MZZ_D:
19998 case AArch64::FMOP4S_MZZ_D:
19999 case AArch64::SMOP4A_MZZ_HtoD:
20000 case AArch64::SMOP4S_MZZ_HtoD:
20001 case AArch64::SUMOP4A_MZZ_HtoD:
20002 case AArch64::SUMOP4S_MZZ_HtoD:
20003 case AArch64::UMOP4A_MZZ_HtoD:
20004 case AArch64::UMOP4S_MZZ_HtoD:
20005 case AArch64::USMOP4A_MZZ_HtoD:
20006 case AArch64::USMOP4S_MZZ_HtoD: {
20007 // op: ZAda
20008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20009 op &= UINT64_C(7);
20010 Value |= op;
20011 // op: Zn
20012 op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI);
20013 op &= UINT64_C(7);
20014 op <<= 6;
20015 Value |= op;
20016 // op: Zm
20017 op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI);
20018 op &= UINT64_C(7);
20019 op <<= 17;
20020 Value |= op;
20021 break;
20022 }
20023 case AArch64::MOVA_2ZMXI_H_H:
20024 case AArch64::MOVA_2ZMXI_V_H: {
20025 // op: Zd
20026 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20027 op &= UINT64_C(15);
20028 op <<= 1;
20029 Value |= op;
20030 // op: Rs
20031 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
20032 op &= UINT64_C(3);
20033 op <<= 13;
20034 Value |= op;
20035 // op: ZAn
20036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20037 op &= UINT64_C(1);
20038 op <<= 7;
20039 Value |= op;
20040 // op: imm
20041 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20042 op &= UINT64_C(3);
20043 op <<= 5;
20044 Value |= op;
20045 break;
20046 }
20047 case AArch64::MOVA_2ZMXI_H_S:
20048 case AArch64::MOVA_2ZMXI_V_S: {
20049 // op: Zd
20050 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20051 op &= UINT64_C(15);
20052 op <<= 1;
20053 Value |= op;
20054 // op: Rs
20055 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
20056 op &= UINT64_C(3);
20057 op <<= 13;
20058 Value |= op;
20059 // op: ZAn
20060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20061 op &= UINT64_C(3);
20062 op <<= 6;
20063 Value |= op;
20064 // op: imm
20065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20066 op &= UINT64_C(1);
20067 op <<= 5;
20068 Value |= op;
20069 break;
20070 }
20071 case AArch64::MOVA_2ZMXI_H_D:
20072 case AArch64::MOVA_2ZMXI_V_D: {
20073 // op: Zd
20074 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20075 op &= UINT64_C(15);
20076 op <<= 1;
20077 Value |= op;
20078 // op: Rs
20079 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
20080 op &= UINT64_C(3);
20081 op <<= 13;
20082 Value |= op;
20083 // op: ZAn
20084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20085 op &= UINT64_C(7);
20086 op <<= 5;
20087 Value |= op;
20088 break;
20089 }
20090 case AArch64::MOVA_2ZMXI_H_B:
20091 case AArch64::MOVA_2ZMXI_V_B: {
20092 // op: Zd
20093 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20094 op &= UINT64_C(15);
20095 op <<= 1;
20096 Value |= op;
20097 // op: Rs
20098 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
20099 op &= UINT64_C(3);
20100 op <<= 13;
20101 Value |= op;
20102 // op: imm
20103 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20104 op &= UINT64_C(7);
20105 op <<= 5;
20106 Value |= op;
20107 break;
20108 }
20109 case AArch64::MOVAZ_2ZMI_H_H:
20110 case AArch64::MOVAZ_2ZMI_V_H: {
20111 // op: Zd
20112 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20113 op &= UINT64_C(15);
20114 op <<= 1;
20115 Value |= op;
20116 // op: Rs
20117 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
20118 op &= UINT64_C(3);
20119 op <<= 13;
20120 Value |= op;
20121 // op: ZAn
20122 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20123 op &= UINT64_C(1);
20124 op <<= 7;
20125 Value |= op;
20126 // op: imm
20127 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20128 op &= UINT64_C(3);
20129 op <<= 5;
20130 Value |= op;
20131 break;
20132 }
20133 case AArch64::MOVAZ_2ZMI_H_S:
20134 case AArch64::MOVAZ_2ZMI_V_S: {
20135 // op: Zd
20136 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20137 op &= UINT64_C(15);
20138 op <<= 1;
20139 Value |= op;
20140 // op: Rs
20141 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
20142 op &= UINT64_C(3);
20143 op <<= 13;
20144 Value |= op;
20145 // op: ZAn
20146 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20147 op &= UINT64_C(3);
20148 op <<= 6;
20149 Value |= op;
20150 // op: imm
20151 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20152 op &= UINT64_C(1);
20153 op <<= 5;
20154 Value |= op;
20155 break;
20156 }
20157 case AArch64::MOVAZ_2ZMI_H_D:
20158 case AArch64::MOVAZ_2ZMI_V_D: {
20159 // op: Zd
20160 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20161 op &= UINT64_C(15);
20162 op <<= 1;
20163 Value |= op;
20164 // op: Rs
20165 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
20166 op &= UINT64_C(3);
20167 op <<= 13;
20168 Value |= op;
20169 // op: ZAn
20170 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20171 op &= UINT64_C(7);
20172 op <<= 5;
20173 Value |= op;
20174 break;
20175 }
20176 case AArch64::MOVAZ_2ZMI_H_B:
20177 case AArch64::MOVAZ_2ZMI_V_B: {
20178 // op: Zd
20179 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20180 op &= UINT64_C(15);
20181 op <<= 1;
20182 Value |= op;
20183 // op: Rs
20184 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
20185 op &= UINT64_C(3);
20186 op <<= 13;
20187 Value |= op;
20188 // op: imm
20189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20190 op &= UINT64_C(7);
20191 op <<= 5;
20192 Value |= op;
20193 break;
20194 }
20195 case AArch64::UZP_VG2_2ZZZ_B:
20196 case AArch64::UZP_VG2_2ZZZ_D:
20197 case AArch64::UZP_VG2_2ZZZ_H:
20198 case AArch64::UZP_VG2_2ZZZ_Q:
20199 case AArch64::UZP_VG2_2ZZZ_S:
20200 case AArch64::ZIP_VG2_2ZZZ_B:
20201 case AArch64::ZIP_VG2_2ZZZ_D:
20202 case AArch64::ZIP_VG2_2ZZZ_H:
20203 case AArch64::ZIP_VG2_2ZZZ_Q:
20204 case AArch64::ZIP_VG2_2ZZZ_S: {
20205 // op: Zd
20206 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20207 op &= UINT64_C(15);
20208 op <<= 1;
20209 Value |= op;
20210 // op: Zm
20211 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20212 op &= UINT64_C(31);
20213 op <<= 16;
20214 Value |= op;
20215 // op: Zn
20216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20217 op &= UINT64_C(31);
20218 op <<= 5;
20219 Value |= op;
20220 break;
20221 }
20222 case AArch64::BFMUL_2Z2Z:
20223 case AArch64::FMUL_2Z2Z_D:
20224 case AArch64::FMUL_2Z2Z_H:
20225 case AArch64::FMUL_2Z2Z_S: {
20226 // op: Zd
20227 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20228 op &= UINT64_C(15);
20229 op <<= 1;
20230 Value |= op;
20231 // op: Zn
20232 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI);
20233 op &= UINT64_C(15);
20234 op <<= 6;
20235 Value |= op;
20236 // op: Zm
20237 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI);
20238 op &= UINT64_C(15);
20239 op <<= 17;
20240 Value |= op;
20241 break;
20242 }
20243 case AArch64::BFMUL_2ZZ:
20244 case AArch64::FMUL_2ZZ_D:
20245 case AArch64::FMUL_2ZZ_H:
20246 case AArch64::FMUL_2ZZ_S: {
20247 // op: Zd
20248 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
20249 op &= UINT64_C(15);
20250 op <<= 1;
20251 Value |= op;
20252 // op: Zn
20253 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI);
20254 op &= UINT64_C(15);
20255 op <<= 6;
20256 Value |= op;
20257 // op: Zm
20258 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20259 op &= UINT64_C(15);
20260 op <<= 17;
20261 Value |= op;
20262 break;
20263 }
20264 case AArch64::MOVA_4ZMXI_H_H:
20265 case AArch64::MOVA_4ZMXI_V_H: {
20266 // op: Zd
20267 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20268 op &= UINT64_C(7);
20269 op <<= 2;
20270 Value |= op;
20271 // op: Rs
20272 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
20273 op &= UINT64_C(3);
20274 op <<= 13;
20275 Value |= op;
20276 // op: ZAn
20277 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20278 op &= UINT64_C(1);
20279 op <<= 6;
20280 Value |= op;
20281 // op: imm
20282 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20283 op &= UINT64_C(1);
20284 op <<= 5;
20285 Value |= op;
20286 break;
20287 }
20288 case AArch64::MOVA_4ZMXI_H_S:
20289 case AArch64::MOVA_4ZMXI_V_S: {
20290 // op: Zd
20291 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20292 op &= UINT64_C(7);
20293 op <<= 2;
20294 Value |= op;
20295 // op: Rs
20296 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
20297 op &= UINT64_C(3);
20298 op <<= 13;
20299 Value |= op;
20300 // op: ZAn
20301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20302 op &= UINT64_C(3);
20303 op <<= 5;
20304 Value |= op;
20305 break;
20306 }
20307 case AArch64::MOVA_4ZMXI_H_D:
20308 case AArch64::MOVA_4ZMXI_V_D: {
20309 // op: Zd
20310 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20311 op &= UINT64_C(7);
20312 op <<= 2;
20313 Value |= op;
20314 // op: Rs
20315 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
20316 op &= UINT64_C(3);
20317 op <<= 13;
20318 Value |= op;
20319 // op: ZAn
20320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20321 op &= UINT64_C(7);
20322 op <<= 5;
20323 Value |= op;
20324 break;
20325 }
20326 case AArch64::MOVA_4ZMXI_H_B:
20327 case AArch64::MOVA_4ZMXI_V_B: {
20328 // op: Zd
20329 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20330 op &= UINT64_C(7);
20331 op <<= 2;
20332 Value |= op;
20333 // op: Rs
20334 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
20335 op &= UINT64_C(3);
20336 op <<= 13;
20337 Value |= op;
20338 // op: imm
20339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20340 op &= UINT64_C(3);
20341 op <<= 5;
20342 Value |= op;
20343 break;
20344 }
20345 case AArch64::MOVAZ_4ZMI_H_H:
20346 case AArch64::MOVAZ_4ZMI_V_H: {
20347 // op: Zd
20348 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20349 op &= UINT64_C(7);
20350 op <<= 2;
20351 Value |= op;
20352 // op: Rs
20353 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
20354 op &= UINT64_C(3);
20355 op <<= 13;
20356 Value |= op;
20357 // op: ZAn
20358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20359 op &= UINT64_C(1);
20360 op <<= 6;
20361 Value |= op;
20362 // op: imm
20363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20364 op &= UINT64_C(1);
20365 op <<= 5;
20366 Value |= op;
20367 break;
20368 }
20369 case AArch64::MOVAZ_4ZMI_H_S:
20370 case AArch64::MOVAZ_4ZMI_V_S: {
20371 // op: Zd
20372 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20373 op &= UINT64_C(7);
20374 op <<= 2;
20375 Value |= op;
20376 // op: Rs
20377 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
20378 op &= UINT64_C(3);
20379 op <<= 13;
20380 Value |= op;
20381 // op: ZAn
20382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20383 op &= UINT64_C(3);
20384 op <<= 5;
20385 Value |= op;
20386 break;
20387 }
20388 case AArch64::MOVAZ_4ZMI_H_D:
20389 case AArch64::MOVAZ_4ZMI_V_D: {
20390 // op: Zd
20391 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20392 op &= UINT64_C(7);
20393 op <<= 2;
20394 Value |= op;
20395 // op: Rs
20396 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
20397 op &= UINT64_C(3);
20398 op <<= 13;
20399 Value |= op;
20400 // op: ZAn
20401 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20402 op &= UINT64_C(7);
20403 op <<= 5;
20404 Value |= op;
20405 break;
20406 }
20407 case AArch64::MOVAZ_4ZMI_H_B:
20408 case AArch64::MOVAZ_4ZMI_V_B: {
20409 // op: Zd
20410 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20411 op &= UINT64_C(7);
20412 op <<= 2;
20413 Value |= op;
20414 // op: Rs
20415 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
20416 op &= UINT64_C(3);
20417 op <<= 13;
20418 Value |= op;
20419 // op: imm
20420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20421 op &= UINT64_C(3);
20422 op <<= 5;
20423 Value |= op;
20424 break;
20425 }
20426 case AArch64::BFMUL_4Z4Z:
20427 case AArch64::FMUL_4Z4Z_D:
20428 case AArch64::FMUL_4Z4Z_H:
20429 case AArch64::FMUL_4Z4Z_S: {
20430 // op: Zd
20431 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20432 op &= UINT64_C(7);
20433 op <<= 2;
20434 Value |= op;
20435 // op: Zn
20436 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI);
20437 op &= UINT64_C(7);
20438 op <<= 7;
20439 Value |= op;
20440 // op: Zm
20441 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 2, Fixups, STI);
20442 op &= UINT64_C(7);
20443 op <<= 18;
20444 Value |= op;
20445 break;
20446 }
20447 case AArch64::BFMUL_4ZZ:
20448 case AArch64::FMUL_4ZZ_D:
20449 case AArch64::FMUL_4ZZ_H:
20450 case AArch64::FMUL_4ZZ_S: {
20451 // op: Zd
20452 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
20453 op &= UINT64_C(7);
20454 op <<= 2;
20455 Value |= op;
20456 // op: Zn
20457 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI);
20458 op &= UINT64_C(7);
20459 op <<= 7;
20460 Value |= op;
20461 // op: Zm
20462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20463 op &= UINT64_C(15);
20464 op <<= 17;
20465 Value |= op;
20466 break;
20467 }
20468 case AArch64::CPY_ZPzI_B:
20469 case AArch64::CPY_ZPzI_D:
20470 case AArch64::CPY_ZPzI_H:
20471 case AArch64::CPY_ZPzI_S: {
20472 // op: Zd
20473 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20474 op &= UINT64_C(31);
20475 Value |= op;
20476 // op: Pg
20477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20478 op &= UINT64_C(15);
20479 op <<= 16;
20480 Value |= op;
20481 // op: imm
20482 op = getImm8OptLsl(MI, OpIdx: 2, Fixups, STI);
20483 op &= UINT64_C(511);
20484 op <<= 5;
20485 Value |= op;
20486 break;
20487 }
20488 case AArch64::RBIT_ZPzZ_B:
20489 case AArch64::RBIT_ZPzZ_D:
20490 case AArch64::RBIT_ZPzZ_H:
20491 case AArch64::RBIT_ZPzZ_S:
20492 case AArch64::REVB_ZPzZ_D:
20493 case AArch64::REVB_ZPzZ_H:
20494 case AArch64::REVB_ZPzZ_S:
20495 case AArch64::REVD_ZPzZ:
20496 case AArch64::REVH_ZPzZ_D:
20497 case AArch64::REVH_ZPzZ_S:
20498 case AArch64::REVW_ZPzZ_D: {
20499 // op: Zd
20500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20501 op &= UINT64_C(31);
20502 Value |= op;
20503 // op: Pg
20504 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20505 op &= UINT64_C(7);
20506 op <<= 10;
20507 Value |= op;
20508 // op: Zn
20509 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20510 op &= UINT64_C(31);
20511 op <<= 5;
20512 Value |= op;
20513 break;
20514 }
20515 case AArch64::CPY_ZPmI_B:
20516 case AArch64::CPY_ZPmI_D:
20517 case AArch64::CPY_ZPmI_H:
20518 case AArch64::CPY_ZPmI_S: {
20519 // op: Zd
20520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20521 op &= UINT64_C(31);
20522 Value |= op;
20523 // op: Pg
20524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20525 op &= UINT64_C(15);
20526 op <<= 16;
20527 Value |= op;
20528 // op: imm
20529 op = getImm8OptLsl(MI, OpIdx: 3, Fixups, STI);
20530 op &= UINT64_C(511);
20531 op <<= 5;
20532 Value |= op;
20533 break;
20534 }
20535 case AArch64::RBIT_ZPmZ_B:
20536 case AArch64::RBIT_ZPmZ_D:
20537 case AArch64::RBIT_ZPmZ_H:
20538 case AArch64::RBIT_ZPmZ_S:
20539 case AArch64::REVB_ZPmZ_D:
20540 case AArch64::REVB_ZPmZ_H:
20541 case AArch64::REVB_ZPmZ_S:
20542 case AArch64::REVD_ZPmZ:
20543 case AArch64::REVH_ZPmZ_D:
20544 case AArch64::REVH_ZPmZ_S:
20545 case AArch64::REVW_ZPmZ_D: {
20546 // op: Zd
20547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20548 op &= UINT64_C(31);
20549 Value |= op;
20550 // op: Pg
20551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20552 op &= UINT64_C(7);
20553 op <<= 10;
20554 Value |= op;
20555 // op: Zn
20556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20557 op &= UINT64_C(31);
20558 op <<= 5;
20559 Value |= op;
20560 break;
20561 }
20562 case AArch64::PMOV_ZIP_B: {
20563 // op: Zd
20564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20565 op &= UINT64_C(31);
20566 Value |= op;
20567 // op: Pn
20568 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20569 op &= UINT64_C(15);
20570 op <<= 5;
20571 Value |= op;
20572 break;
20573 }
20574 case AArch64::PMOV_ZIP_D: {
20575 // op: Zd
20576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20577 op &= UINT64_C(31);
20578 Value |= op;
20579 // op: Pn
20580 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20581 op &= UINT64_C(15);
20582 op <<= 5;
20583 Value |= op;
20584 // op: index
20585 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20586 Value |= (op & UINT64_C(4)) << 20;
20587 Value |= (op & UINT64_C(3)) << 17;
20588 break;
20589 }
20590 case AArch64::PMOV_ZIP_H: {
20591 // op: Zd
20592 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20593 op &= UINT64_C(31);
20594 Value |= op;
20595 // op: Pn
20596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20597 op &= UINT64_C(15);
20598 op <<= 5;
20599 Value |= op;
20600 // op: index
20601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20602 op &= UINT64_C(1);
20603 op <<= 17;
20604 Value |= op;
20605 break;
20606 }
20607 case AArch64::PMOV_ZIP_S: {
20608 // op: Zd
20609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20610 op &= UINT64_C(31);
20611 Value |= op;
20612 // op: Pn
20613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20614 op &= UINT64_C(15);
20615 op <<= 5;
20616 Value |= op;
20617 // op: index
20618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20619 op &= UINT64_C(3);
20620 op <<= 17;
20621 Value |= op;
20622 break;
20623 }
20624 case AArch64::INDEX_RR_B:
20625 case AArch64::INDEX_RR_D:
20626 case AArch64::INDEX_RR_H:
20627 case AArch64::INDEX_RR_S: {
20628 // op: Zd
20629 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20630 op &= UINT64_C(31);
20631 Value |= op;
20632 // op: Rm
20633 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20634 op &= UINT64_C(31);
20635 op <<= 16;
20636 Value |= op;
20637 // op: Rn
20638 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20639 op &= UINT64_C(31);
20640 op <<= 5;
20641 Value |= op;
20642 break;
20643 }
20644 case AArch64::ADD_ZZZ_B:
20645 case AArch64::ADD_ZZZ_CPA:
20646 case AArch64::ADD_ZZZ_D:
20647 case AArch64::ADD_ZZZ_H:
20648 case AArch64::ADD_ZZZ_S:
20649 case AArch64::AND_ZZZ:
20650 case AArch64::ASR_WIDE_ZZZ_B:
20651 case AArch64::ASR_WIDE_ZZZ_H:
20652 case AArch64::ASR_WIDE_ZZZ_S:
20653 case AArch64::BFADD_ZZZ:
20654 case AArch64::BFMUL_ZZZ:
20655 case AArch64::BFSUB_ZZZ:
20656 case AArch64::BIC_ZZZ:
20657 case AArch64::EOR_ZZZ:
20658 case AArch64::FADD_ZZZ_D:
20659 case AArch64::FADD_ZZZ_H:
20660 case AArch64::FADD_ZZZ_S:
20661 case AArch64::FMUL_ZZZ_D:
20662 case AArch64::FMUL_ZZZ_H:
20663 case AArch64::FMUL_ZZZ_S:
20664 case AArch64::FRECPS_ZZZ_D:
20665 case AArch64::FRECPS_ZZZ_H:
20666 case AArch64::FRECPS_ZZZ_S:
20667 case AArch64::FRSQRTS_ZZZ_D:
20668 case AArch64::FRSQRTS_ZZZ_H:
20669 case AArch64::FRSQRTS_ZZZ_S:
20670 case AArch64::FSUB_ZZZ_D:
20671 case AArch64::FSUB_ZZZ_H:
20672 case AArch64::FSUB_ZZZ_S:
20673 case AArch64::FTSMUL_ZZZ_D:
20674 case AArch64::FTSMUL_ZZZ_H:
20675 case AArch64::FTSMUL_ZZZ_S:
20676 case AArch64::FTSSEL_ZZZ_D:
20677 case AArch64::FTSSEL_ZZZ_H:
20678 case AArch64::FTSSEL_ZZZ_S:
20679 case AArch64::LSL_WIDE_ZZZ_B:
20680 case AArch64::LSL_WIDE_ZZZ_H:
20681 case AArch64::LSL_WIDE_ZZZ_S:
20682 case AArch64::LSR_WIDE_ZZZ_B:
20683 case AArch64::LSR_WIDE_ZZZ_H:
20684 case AArch64::LSR_WIDE_ZZZ_S:
20685 case AArch64::MUL_ZZZ_B:
20686 case AArch64::MUL_ZZZ_D:
20687 case AArch64::MUL_ZZZ_H:
20688 case AArch64::MUL_ZZZ_S:
20689 case AArch64::ORR_ZZZ:
20690 case AArch64::PMUL_ZZZ_B:
20691 case AArch64::SMULH_ZZZ_B:
20692 case AArch64::SMULH_ZZZ_D:
20693 case AArch64::SMULH_ZZZ_H:
20694 case AArch64::SMULH_ZZZ_S:
20695 case AArch64::SQADD_ZZZ_B:
20696 case AArch64::SQADD_ZZZ_D:
20697 case AArch64::SQADD_ZZZ_H:
20698 case AArch64::SQADD_ZZZ_S:
20699 case AArch64::SQDMULH_ZZZ_B:
20700 case AArch64::SQDMULH_ZZZ_D:
20701 case AArch64::SQDMULH_ZZZ_H:
20702 case AArch64::SQDMULH_ZZZ_S:
20703 case AArch64::SQRDMULH_ZZZ_B:
20704 case AArch64::SQRDMULH_ZZZ_D:
20705 case AArch64::SQRDMULH_ZZZ_H:
20706 case AArch64::SQRDMULH_ZZZ_S:
20707 case AArch64::SQSUB_ZZZ_B:
20708 case AArch64::SQSUB_ZZZ_D:
20709 case AArch64::SQSUB_ZZZ_H:
20710 case AArch64::SQSUB_ZZZ_S:
20711 case AArch64::SUB_ZZZ_B:
20712 case AArch64::SUB_ZZZ_CPA:
20713 case AArch64::SUB_ZZZ_D:
20714 case AArch64::SUB_ZZZ_H:
20715 case AArch64::SUB_ZZZ_S:
20716 case AArch64::TBL_ZZZZ_B:
20717 case AArch64::TBL_ZZZZ_D:
20718 case AArch64::TBL_ZZZZ_H:
20719 case AArch64::TBL_ZZZZ_S:
20720 case AArch64::TBL_ZZZ_B:
20721 case AArch64::TBL_ZZZ_D:
20722 case AArch64::TBL_ZZZ_H:
20723 case AArch64::TBL_ZZZ_S:
20724 case AArch64::TRN1_ZZZ_B:
20725 case AArch64::TRN1_ZZZ_D:
20726 case AArch64::TRN1_ZZZ_H:
20727 case AArch64::TRN1_ZZZ_Q:
20728 case AArch64::TRN1_ZZZ_S:
20729 case AArch64::TRN2_ZZZ_B:
20730 case AArch64::TRN2_ZZZ_D:
20731 case AArch64::TRN2_ZZZ_H:
20732 case AArch64::TRN2_ZZZ_Q:
20733 case AArch64::TRN2_ZZZ_S:
20734 case AArch64::UMULH_ZZZ_B:
20735 case AArch64::UMULH_ZZZ_D:
20736 case AArch64::UMULH_ZZZ_H:
20737 case AArch64::UMULH_ZZZ_S:
20738 case AArch64::UQADD_ZZZ_B:
20739 case AArch64::UQADD_ZZZ_D:
20740 case AArch64::UQADD_ZZZ_H:
20741 case AArch64::UQADD_ZZZ_S:
20742 case AArch64::UQSUB_ZZZ_B:
20743 case AArch64::UQSUB_ZZZ_D:
20744 case AArch64::UQSUB_ZZZ_H:
20745 case AArch64::UQSUB_ZZZ_S:
20746 case AArch64::UZP1_ZZZ_B:
20747 case AArch64::UZP1_ZZZ_D:
20748 case AArch64::UZP1_ZZZ_H:
20749 case AArch64::UZP1_ZZZ_Q:
20750 case AArch64::UZP1_ZZZ_S:
20751 case AArch64::UZP2_ZZZ_B:
20752 case AArch64::UZP2_ZZZ_D:
20753 case AArch64::UZP2_ZZZ_H:
20754 case AArch64::UZP2_ZZZ_Q:
20755 case AArch64::UZP2_ZZZ_S:
20756 case AArch64::ZIP1_ZZZ_B:
20757 case AArch64::ZIP1_ZZZ_D:
20758 case AArch64::ZIP1_ZZZ_H:
20759 case AArch64::ZIP1_ZZZ_Q:
20760 case AArch64::ZIP1_ZZZ_S:
20761 case AArch64::ZIP2_ZZZ_B:
20762 case AArch64::ZIP2_ZZZ_D:
20763 case AArch64::ZIP2_ZZZ_H:
20764 case AArch64::ZIP2_ZZZ_Q:
20765 case AArch64::ZIP2_ZZZ_S: {
20766 // op: Zd
20767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20768 op &= UINT64_C(31);
20769 Value |= op;
20770 // op: Zm
20771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20772 op &= UINT64_C(31);
20773 op <<= 16;
20774 Value |= op;
20775 // op: Zn
20776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20777 op &= UINT64_C(31);
20778 op <<= 5;
20779 Value |= op;
20780 break;
20781 }
20782 case AArch64::TBXQ_ZZZ_B:
20783 case AArch64::TBXQ_ZZZ_D:
20784 case AArch64::TBXQ_ZZZ_H:
20785 case AArch64::TBXQ_ZZZ_S:
20786 case AArch64::TBX_ZZZ_B:
20787 case AArch64::TBX_ZZZ_D:
20788 case AArch64::TBX_ZZZ_H:
20789 case AArch64::TBX_ZZZ_S: {
20790 // op: Zd
20791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20792 op &= UINT64_C(31);
20793 Value |= op;
20794 // op: Zm
20795 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20796 op &= UINT64_C(31);
20797 op <<= 16;
20798 Value |= op;
20799 // op: Zn
20800 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20801 op &= UINT64_C(31);
20802 op <<= 5;
20803 Value |= op;
20804 break;
20805 }
20806 case AArch64::BFCVTN_Z2Z_HtoB:
20807 case AArch64::FCVTNB_Z2Z_StoB:
20808 case AArch64::FCVTN_Z2Z_HtoB:
20809 case AArch64::SQCVTN_Z2Z_StoH:
20810 case AArch64::SQCVTUN_Z2Z_StoH:
20811 case AArch64::UQCVTN_Z2Z_StoH: {
20812 // op: Zd
20813 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20814 op &= UINT64_C(31);
20815 Value |= op;
20816 // op: Zn
20817 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI);
20818 op &= UINT64_C(15);
20819 op <<= 6;
20820 Value |= op;
20821 break;
20822 }
20823 case AArch64::SQRSHRN_Z2ZI_StoH:
20824 case AArch64::SQRSHRUN_Z2ZI_StoH:
20825 case AArch64::UQRSHRN_Z2ZI_StoH: {
20826 // op: Zd
20827 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20828 op &= UINT64_C(31);
20829 Value |= op;
20830 // op: Zn
20831 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI);
20832 op &= UINT64_C(15);
20833 op <<= 6;
20834 Value |= op;
20835 // op: imm4
20836 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
20837 op &= UINT64_C(15);
20838 op <<= 16;
20839 Value |= op;
20840 break;
20841 }
20842 case AArch64::FCVTNT_Z2Z_StoB: {
20843 // op: Zd
20844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20845 op &= UINT64_C(31);
20846 Value |= op;
20847 // op: Zn
20848 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI);
20849 op &= UINT64_C(15);
20850 op <<= 6;
20851 Value |= op;
20852 break;
20853 }
20854 case AArch64::BF1CVTLT_ZZ_BtoH:
20855 case AArch64::BF1CVT_ZZ_BtoH:
20856 case AArch64::BF2CVTLT_ZZ_BtoH:
20857 case AArch64::BF2CVT_ZZ_BtoH:
20858 case AArch64::F1CVTLT_ZZ_BtoH:
20859 case AArch64::F1CVT_ZZ_BtoH:
20860 case AArch64::F2CVTLT_ZZ_BtoH:
20861 case AArch64::F2CVT_ZZ_BtoH:
20862 case AArch64::FEXPA_ZZ_D:
20863 case AArch64::FEXPA_ZZ_H:
20864 case AArch64::FEXPA_ZZ_S:
20865 case AArch64::FRECPE_ZZ_D:
20866 case AArch64::FRECPE_ZZ_H:
20867 case AArch64::FRECPE_ZZ_S:
20868 case AArch64::FRSQRTE_ZZ_D:
20869 case AArch64::FRSQRTE_ZZ_H:
20870 case AArch64::FRSQRTE_ZZ_S:
20871 case AArch64::MOVPRFX_ZZ:
20872 case AArch64::REV_ZZ_B:
20873 case AArch64::REV_ZZ_D:
20874 case AArch64::REV_ZZ_H:
20875 case AArch64::REV_ZZ_S:
20876 case AArch64::SQXTNB_ZZ_B:
20877 case AArch64::SQXTNB_ZZ_H:
20878 case AArch64::SQXTNB_ZZ_S:
20879 case AArch64::SQXTUNB_ZZ_B:
20880 case AArch64::SQXTUNB_ZZ_H:
20881 case AArch64::SQXTUNB_ZZ_S:
20882 case AArch64::SUNPKHI_ZZ_D:
20883 case AArch64::SUNPKHI_ZZ_H:
20884 case AArch64::SUNPKHI_ZZ_S:
20885 case AArch64::SUNPKLO_ZZ_D:
20886 case AArch64::SUNPKLO_ZZ_H:
20887 case AArch64::SUNPKLO_ZZ_S:
20888 case AArch64::UQXTNB_ZZ_B:
20889 case AArch64::UQXTNB_ZZ_H:
20890 case AArch64::UQXTNB_ZZ_S:
20891 case AArch64::UUNPKHI_ZZ_D:
20892 case AArch64::UUNPKHI_ZZ_H:
20893 case AArch64::UUNPKHI_ZZ_S:
20894 case AArch64::UUNPKLO_ZZ_D:
20895 case AArch64::UUNPKLO_ZZ_H:
20896 case AArch64::UUNPKLO_ZZ_S: {
20897 // op: Zd
20898 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20899 op &= UINT64_C(31);
20900 Value |= op;
20901 // op: Zn
20902 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20903 op &= UINT64_C(31);
20904 op <<= 5;
20905 Value |= op;
20906 break;
20907 }
20908 case AArch64::SMULLB_ZZZI_D:
20909 case AArch64::SMULLT_ZZZI_D:
20910 case AArch64::SQDMULLB_ZZZI_D:
20911 case AArch64::SQDMULLT_ZZZI_D:
20912 case AArch64::UMULLB_ZZZI_D:
20913 case AArch64::UMULLT_ZZZI_D: {
20914 // op: Zd
20915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20916 op &= UINT64_C(31);
20917 Value |= op;
20918 // op: Zn
20919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20920 op &= UINT64_C(31);
20921 op <<= 5;
20922 Value |= op;
20923 // op: Zm
20924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20925 op &= UINT64_C(15);
20926 op <<= 16;
20927 Value |= op;
20928 // op: iop
20929 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20930 Value |= (op & UINT64_C(2)) << 19;
20931 Value |= (op & UINT64_C(1)) << 11;
20932 break;
20933 }
20934 case AArch64::FMUL_ZZZI_D:
20935 case AArch64::MUL_ZZZI_D:
20936 case AArch64::SQDMULH_ZZZI_D:
20937 case AArch64::SQRDMULH_ZZZI_D: {
20938 // op: Zd
20939 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20940 op &= UINT64_C(31);
20941 Value |= op;
20942 // op: Zn
20943 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20944 op &= UINT64_C(31);
20945 op <<= 5;
20946 Value |= op;
20947 // op: Zm
20948 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20949 op &= UINT64_C(15);
20950 op <<= 16;
20951 Value |= op;
20952 // op: iop
20953 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20954 op &= UINT64_C(1);
20955 op <<= 20;
20956 Value |= op;
20957 break;
20958 }
20959 case AArch64::ADDHNB_ZZZ_B:
20960 case AArch64::ADDHNB_ZZZ_H:
20961 case AArch64::ADDHNB_ZZZ_S:
20962 case AArch64::ADR_LSL_ZZZ_D_0:
20963 case AArch64::ADR_LSL_ZZZ_D_1:
20964 case AArch64::ADR_LSL_ZZZ_D_2:
20965 case AArch64::ADR_LSL_ZZZ_D_3:
20966 case AArch64::ADR_LSL_ZZZ_S_0:
20967 case AArch64::ADR_LSL_ZZZ_S_1:
20968 case AArch64::ADR_LSL_ZZZ_S_2:
20969 case AArch64::ADR_LSL_ZZZ_S_3:
20970 case AArch64::ADR_SXTW_ZZZ_D_0:
20971 case AArch64::ADR_SXTW_ZZZ_D_1:
20972 case AArch64::ADR_SXTW_ZZZ_D_2:
20973 case AArch64::ADR_SXTW_ZZZ_D_3:
20974 case AArch64::ADR_UXTW_ZZZ_D_0:
20975 case AArch64::ADR_UXTW_ZZZ_D_1:
20976 case AArch64::ADR_UXTW_ZZZ_D_2:
20977 case AArch64::ADR_UXTW_ZZZ_D_3:
20978 case AArch64::BDEP_ZZZ_B:
20979 case AArch64::BDEP_ZZZ_D:
20980 case AArch64::BDEP_ZZZ_H:
20981 case AArch64::BDEP_ZZZ_S:
20982 case AArch64::BEXT_ZZZ_B:
20983 case AArch64::BEXT_ZZZ_D:
20984 case AArch64::BEXT_ZZZ_H:
20985 case AArch64::BEXT_ZZZ_S:
20986 case AArch64::BGRP_ZZZ_B:
20987 case AArch64::BGRP_ZZZ_D:
20988 case AArch64::BGRP_ZZZ_H:
20989 case AArch64::BGRP_ZZZ_S:
20990 case AArch64::HISTSEG_ZZZ:
20991 case AArch64::PMULLB_ZZZ_D:
20992 case AArch64::PMULLB_ZZZ_H:
20993 case AArch64::PMULLB_ZZZ_Q:
20994 case AArch64::PMULLT_ZZZ_D:
20995 case AArch64::PMULLT_ZZZ_H:
20996 case AArch64::PMULLT_ZZZ_Q:
20997 case AArch64::RADDHNB_ZZZ_B:
20998 case AArch64::RADDHNB_ZZZ_H:
20999 case AArch64::RADDHNB_ZZZ_S:
21000 case AArch64::RAX1_ZZZ_D:
21001 case AArch64::RSUBHNB_ZZZ_B:
21002 case AArch64::RSUBHNB_ZZZ_H:
21003 case AArch64::RSUBHNB_ZZZ_S:
21004 case AArch64::SABDLB_ZZZ_D:
21005 case AArch64::SABDLB_ZZZ_H:
21006 case AArch64::SABDLB_ZZZ_S:
21007 case AArch64::SABDLT_ZZZ_D:
21008 case AArch64::SABDLT_ZZZ_H:
21009 case AArch64::SABDLT_ZZZ_S:
21010 case AArch64::SADDLBT_ZZZ_D:
21011 case AArch64::SADDLBT_ZZZ_H:
21012 case AArch64::SADDLBT_ZZZ_S:
21013 case AArch64::SADDLB_ZZZ_D:
21014 case AArch64::SADDLB_ZZZ_H:
21015 case AArch64::SADDLB_ZZZ_S:
21016 case AArch64::SADDLT_ZZZ_D:
21017 case AArch64::SADDLT_ZZZ_H:
21018 case AArch64::SADDLT_ZZZ_S:
21019 case AArch64::SADDWB_ZZZ_D:
21020 case AArch64::SADDWB_ZZZ_H:
21021 case AArch64::SADDWB_ZZZ_S:
21022 case AArch64::SADDWT_ZZZ_D:
21023 case AArch64::SADDWT_ZZZ_H:
21024 case AArch64::SADDWT_ZZZ_S:
21025 case AArch64::SM4EKEY_ZZZ_S:
21026 case AArch64::SMULLB_ZZZ_D:
21027 case AArch64::SMULLB_ZZZ_H:
21028 case AArch64::SMULLB_ZZZ_S:
21029 case AArch64::SMULLT_ZZZ_D:
21030 case AArch64::SMULLT_ZZZ_H:
21031 case AArch64::SMULLT_ZZZ_S:
21032 case AArch64::SQDMULLB_ZZZ_D:
21033 case AArch64::SQDMULLB_ZZZ_H:
21034 case AArch64::SQDMULLB_ZZZ_S:
21035 case AArch64::SQDMULLT_ZZZ_D:
21036 case AArch64::SQDMULLT_ZZZ_H:
21037 case AArch64::SQDMULLT_ZZZ_S:
21038 case AArch64::SSUBLBT_ZZZ_D:
21039 case AArch64::SSUBLBT_ZZZ_H:
21040 case AArch64::SSUBLBT_ZZZ_S:
21041 case AArch64::SSUBLB_ZZZ_D:
21042 case AArch64::SSUBLB_ZZZ_H:
21043 case AArch64::SSUBLB_ZZZ_S:
21044 case AArch64::SSUBLTB_ZZZ_D:
21045 case AArch64::SSUBLTB_ZZZ_H:
21046 case AArch64::SSUBLTB_ZZZ_S:
21047 case AArch64::SSUBLT_ZZZ_D:
21048 case AArch64::SSUBLT_ZZZ_H:
21049 case AArch64::SSUBLT_ZZZ_S:
21050 case AArch64::SSUBWB_ZZZ_D:
21051 case AArch64::SSUBWB_ZZZ_H:
21052 case AArch64::SSUBWB_ZZZ_S:
21053 case AArch64::SSUBWT_ZZZ_D:
21054 case AArch64::SSUBWT_ZZZ_H:
21055 case AArch64::SSUBWT_ZZZ_S:
21056 case AArch64::SUBHNB_ZZZ_B:
21057 case AArch64::SUBHNB_ZZZ_H:
21058 case AArch64::SUBHNB_ZZZ_S:
21059 case AArch64::TBLQ_ZZZ_B:
21060 case AArch64::TBLQ_ZZZ_D:
21061 case AArch64::TBLQ_ZZZ_H:
21062 case AArch64::TBLQ_ZZZ_S:
21063 case AArch64::UABDLB_ZZZ_D:
21064 case AArch64::UABDLB_ZZZ_H:
21065 case AArch64::UABDLB_ZZZ_S:
21066 case AArch64::UABDLT_ZZZ_D:
21067 case AArch64::UABDLT_ZZZ_H:
21068 case AArch64::UABDLT_ZZZ_S:
21069 case AArch64::UADDLB_ZZZ_D:
21070 case AArch64::UADDLB_ZZZ_H:
21071 case AArch64::UADDLB_ZZZ_S:
21072 case AArch64::UADDLT_ZZZ_D:
21073 case AArch64::UADDLT_ZZZ_H:
21074 case AArch64::UADDLT_ZZZ_S:
21075 case AArch64::UADDWB_ZZZ_D:
21076 case AArch64::UADDWB_ZZZ_H:
21077 case AArch64::UADDWB_ZZZ_S:
21078 case AArch64::UADDWT_ZZZ_D:
21079 case AArch64::UADDWT_ZZZ_H:
21080 case AArch64::UADDWT_ZZZ_S:
21081 case AArch64::UMULLB_ZZZ_D:
21082 case AArch64::UMULLB_ZZZ_H:
21083 case AArch64::UMULLB_ZZZ_S:
21084 case AArch64::UMULLT_ZZZ_D:
21085 case AArch64::UMULLT_ZZZ_H:
21086 case AArch64::UMULLT_ZZZ_S:
21087 case AArch64::USUBLB_ZZZ_D:
21088 case AArch64::USUBLB_ZZZ_H:
21089 case AArch64::USUBLB_ZZZ_S:
21090 case AArch64::USUBLT_ZZZ_D:
21091 case AArch64::USUBLT_ZZZ_H:
21092 case AArch64::USUBLT_ZZZ_S:
21093 case AArch64::USUBWB_ZZZ_D:
21094 case AArch64::USUBWB_ZZZ_H:
21095 case AArch64::USUBWB_ZZZ_S:
21096 case AArch64::USUBWT_ZZZ_D:
21097 case AArch64::USUBWT_ZZZ_H:
21098 case AArch64::USUBWT_ZZZ_S:
21099 case AArch64::UZPQ1_ZZZ_B:
21100 case AArch64::UZPQ1_ZZZ_D:
21101 case AArch64::UZPQ1_ZZZ_H:
21102 case AArch64::UZPQ1_ZZZ_S:
21103 case AArch64::UZPQ2_ZZZ_B:
21104 case AArch64::UZPQ2_ZZZ_D:
21105 case AArch64::UZPQ2_ZZZ_H:
21106 case AArch64::UZPQ2_ZZZ_S:
21107 case AArch64::ZIPQ1_ZZZ_B:
21108 case AArch64::ZIPQ1_ZZZ_D:
21109 case AArch64::ZIPQ1_ZZZ_H:
21110 case AArch64::ZIPQ1_ZZZ_S:
21111 case AArch64::ZIPQ2_ZZZ_B:
21112 case AArch64::ZIPQ2_ZZZ_D:
21113 case AArch64::ZIPQ2_ZZZ_H:
21114 case AArch64::ZIPQ2_ZZZ_S: {
21115 // op: Zd
21116 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21117 op &= UINT64_C(31);
21118 Value |= op;
21119 // op: Zn
21120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21121 op &= UINT64_C(31);
21122 op <<= 5;
21123 Value |= op;
21124 // op: Zm
21125 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21126 op &= UINT64_C(31);
21127 op <<= 16;
21128 Value |= op;
21129 break;
21130 }
21131 case AArch64::LUTI2_ZZZI_H: {
21132 // op: Zd
21133 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21134 op &= UINT64_C(31);
21135 Value |= op;
21136 // op: Zn
21137 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21138 op &= UINT64_C(31);
21139 op <<= 5;
21140 Value |= op;
21141 // op: Zm
21142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21143 op &= UINT64_C(31);
21144 op <<= 16;
21145 Value |= op;
21146 // op: idx
21147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21148 Value |= (op & UINT64_C(6)) << 21;
21149 Value |= (op & UINT64_C(1)) << 12;
21150 break;
21151 }
21152 case AArch64::LUTI4_ZZZI_B: {
21153 // op: Zd
21154 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21155 op &= UINT64_C(31);
21156 Value |= op;
21157 // op: Zn
21158 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21159 op &= UINT64_C(31);
21160 op <<= 5;
21161 Value |= op;
21162 // op: Zm
21163 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21164 op &= UINT64_C(31);
21165 op <<= 16;
21166 Value |= op;
21167 // op: idx
21168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21169 op &= UINT64_C(1);
21170 op <<= 23;
21171 Value |= op;
21172 break;
21173 }
21174 case AArch64::LUTI2_ZZZI_B:
21175 case AArch64::LUTI4_Z2ZZI:
21176 case AArch64::LUTI4_ZZZI_H: {
21177 // op: Zd
21178 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21179 op &= UINT64_C(31);
21180 Value |= op;
21181 // op: Zn
21182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21183 op &= UINT64_C(31);
21184 op <<= 5;
21185 Value |= op;
21186 // op: Zm
21187 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21188 op &= UINT64_C(31);
21189 op <<= 16;
21190 Value |= op;
21191 // op: idx
21192 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21193 op &= UINT64_C(3);
21194 op <<= 22;
21195 Value |= op;
21196 break;
21197 }
21198 case AArch64::BFMUL_ZZZI:
21199 case AArch64::FMUL_ZZZI_H:
21200 case AArch64::MUL_ZZZI_H:
21201 case AArch64::SQDMULH_ZZZI_H:
21202 case AArch64::SQRDMULH_ZZZI_H: {
21203 // op: Zd
21204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21205 op &= UINT64_C(31);
21206 Value |= op;
21207 // op: Zn
21208 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21209 op &= UINT64_C(31);
21210 op <<= 5;
21211 Value |= op;
21212 // op: Zm
21213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21214 op &= UINT64_C(7);
21215 op <<= 16;
21216 Value |= op;
21217 // op: iop
21218 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21219 Value |= (op & UINT64_C(4)) << 20;
21220 Value |= (op & UINT64_C(3)) << 19;
21221 break;
21222 }
21223 case AArch64::SMULLB_ZZZI_S:
21224 case AArch64::SMULLT_ZZZI_S:
21225 case AArch64::SQDMULLB_ZZZI_S:
21226 case AArch64::SQDMULLT_ZZZI_S:
21227 case AArch64::UMULLB_ZZZI_S:
21228 case AArch64::UMULLT_ZZZI_S: {
21229 // op: Zd
21230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21231 op &= UINT64_C(31);
21232 Value |= op;
21233 // op: Zn
21234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21235 op &= UINT64_C(31);
21236 op <<= 5;
21237 Value |= op;
21238 // op: Zm
21239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21240 op &= UINT64_C(7);
21241 op <<= 16;
21242 Value |= op;
21243 // op: iop
21244 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21245 Value |= (op & UINT64_C(6)) << 18;
21246 Value |= (op & UINT64_C(1)) << 11;
21247 break;
21248 }
21249 case AArch64::FMUL_ZZZI_S:
21250 case AArch64::MUL_ZZZI_S:
21251 case AArch64::SQDMULH_ZZZI_S:
21252 case AArch64::SQRDMULH_ZZZI_S: {
21253 // op: Zd
21254 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21255 op &= UINT64_C(31);
21256 Value |= op;
21257 // op: Zn
21258 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21259 op &= UINT64_C(31);
21260 op <<= 5;
21261 Value |= op;
21262 // op: Zm
21263 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21264 op &= UINT64_C(7);
21265 op <<= 16;
21266 Value |= op;
21267 // op: iop
21268 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21269 op &= UINT64_C(3);
21270 op <<= 19;
21271 Value |= op;
21272 break;
21273 }
21274 case AArch64::DUP_ZZI_S: {
21275 // op: Zd
21276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21277 op &= UINT64_C(31);
21278 Value |= op;
21279 // op: Zn
21280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21281 op &= UINT64_C(31);
21282 op <<= 5;
21283 Value |= op;
21284 // op: idx
21285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21286 Value |= (op & UINT64_C(12)) << 20;
21287 Value |= (op & UINT64_C(3)) << 19;
21288 break;
21289 }
21290 case AArch64::DUP_ZZI_H: {
21291 // op: Zd
21292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21293 op &= UINT64_C(31);
21294 Value |= op;
21295 // op: Zn
21296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21297 op &= UINT64_C(31);
21298 op <<= 5;
21299 Value |= op;
21300 // op: idx
21301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21302 Value |= (op & UINT64_C(24)) << 19;
21303 Value |= (op & UINT64_C(7)) << 18;
21304 break;
21305 }
21306 case AArch64::DUP_ZZI_B: {
21307 // op: Zd
21308 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21309 op &= UINT64_C(31);
21310 Value |= op;
21311 // op: Zn
21312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21313 op &= UINT64_C(31);
21314 op <<= 5;
21315 Value |= op;
21316 // op: idx
21317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21318 Value |= (op & UINT64_C(48)) << 18;
21319 Value |= (op & UINT64_C(15)) << 17;
21320 break;
21321 }
21322 case AArch64::DUP_ZZI_D: {
21323 // op: Zd
21324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21325 op &= UINT64_C(31);
21326 Value |= op;
21327 // op: Zn
21328 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21329 op &= UINT64_C(31);
21330 op <<= 5;
21331 Value |= op;
21332 // op: idx
21333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21334 Value |= (op & UINT64_C(6)) << 21;
21335 Value |= (op & UINT64_C(1)) << 20;
21336 break;
21337 }
21338 case AArch64::DUP_ZZI_Q: {
21339 // op: Zd
21340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21341 op &= UINT64_C(31);
21342 Value |= op;
21343 // op: Zn
21344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21345 op &= UINT64_C(31);
21346 op <<= 5;
21347 Value |= op;
21348 // op: idx
21349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21350 op &= UINT64_C(3);
21351 op <<= 22;
21352 Value |= op;
21353 break;
21354 }
21355 case AArch64::LSL_ZZI_H:
21356 case AArch64::SSHLLB_ZZI_S:
21357 case AArch64::SSHLLT_ZZI_S:
21358 case AArch64::USHLLB_ZZI_S:
21359 case AArch64::USHLLT_ZZI_S: {
21360 // op: Zd
21361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21362 op &= UINT64_C(31);
21363 Value |= op;
21364 // op: Zn
21365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21366 op &= UINT64_C(31);
21367 op <<= 5;
21368 Value |= op;
21369 // op: imm
21370 op = getVecShiftL16OpValue(MI, OpIdx: 2, Fixups, STI);
21371 op &= UINT64_C(15);
21372 op <<= 16;
21373 Value |= op;
21374 break;
21375 }
21376 case AArch64::LSL_ZZI_S:
21377 case AArch64::SSHLLB_ZZI_D:
21378 case AArch64::SSHLLT_ZZI_D:
21379 case AArch64::USHLLB_ZZI_D:
21380 case AArch64::USHLLT_ZZI_D: {
21381 // op: Zd
21382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21383 op &= UINT64_C(31);
21384 Value |= op;
21385 // op: Zn
21386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21387 op &= UINT64_C(31);
21388 op <<= 5;
21389 Value |= op;
21390 // op: imm
21391 op = getVecShiftL32OpValue(MI, OpIdx: 2, Fixups, STI);
21392 op &= UINT64_C(31);
21393 op <<= 16;
21394 Value |= op;
21395 break;
21396 }
21397 case AArch64::LSL_ZZI_D: {
21398 // op: Zd
21399 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21400 op &= UINT64_C(31);
21401 Value |= op;
21402 // op: Zn
21403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21404 op &= UINT64_C(31);
21405 op <<= 5;
21406 Value |= op;
21407 // op: imm
21408 op = getVecShiftL64OpValue(MI, OpIdx: 2, Fixups, STI);
21409 Value |= (op & UINT64_C(32)) << 17;
21410 Value |= (op & UINT64_C(31)) << 16;
21411 break;
21412 }
21413 case AArch64::LSL_ZZI_B:
21414 case AArch64::SSHLLB_ZZI_H:
21415 case AArch64::SSHLLT_ZZI_H:
21416 case AArch64::USHLLB_ZZI_H:
21417 case AArch64::USHLLT_ZZI_H: {
21418 // op: Zd
21419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21420 op &= UINT64_C(31);
21421 Value |= op;
21422 // op: Zn
21423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21424 op &= UINT64_C(31);
21425 op <<= 5;
21426 Value |= op;
21427 // op: imm
21428 op = getVecShiftL8OpValue(MI, OpIdx: 2, Fixups, STI);
21429 op &= UINT64_C(7);
21430 op <<= 16;
21431 Value |= op;
21432 break;
21433 }
21434 case AArch64::ASR_ZZI_H:
21435 case AArch64::LSR_ZZI_H:
21436 case AArch64::RSHRNB_ZZI_H:
21437 case AArch64::SHRNB_ZZI_H:
21438 case AArch64::SQRSHRNB_ZZI_H:
21439 case AArch64::SQRSHRUNB_ZZI_H:
21440 case AArch64::SQSHRNB_ZZI_H:
21441 case AArch64::SQSHRUNB_ZZI_H:
21442 case AArch64::UQRSHRNB_ZZI_H:
21443 case AArch64::UQSHRNB_ZZI_H: {
21444 // op: Zd
21445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21446 op &= UINT64_C(31);
21447 Value |= op;
21448 // op: Zn
21449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21450 op &= UINT64_C(31);
21451 op <<= 5;
21452 Value |= op;
21453 // op: imm
21454 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
21455 op &= UINT64_C(15);
21456 op <<= 16;
21457 Value |= op;
21458 break;
21459 }
21460 case AArch64::ASR_ZZI_S:
21461 case AArch64::LSR_ZZI_S:
21462 case AArch64::RSHRNB_ZZI_S:
21463 case AArch64::SHRNB_ZZI_S:
21464 case AArch64::SQRSHRNB_ZZI_S:
21465 case AArch64::SQRSHRUNB_ZZI_S:
21466 case AArch64::SQSHRNB_ZZI_S:
21467 case AArch64::SQSHRUNB_ZZI_S:
21468 case AArch64::UQRSHRNB_ZZI_S:
21469 case AArch64::UQSHRNB_ZZI_S: {
21470 // op: Zd
21471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21472 op &= UINT64_C(31);
21473 Value |= op;
21474 // op: Zn
21475 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21476 op &= UINT64_C(31);
21477 op <<= 5;
21478 Value |= op;
21479 // op: imm
21480 op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI);
21481 op &= UINT64_C(31);
21482 op <<= 16;
21483 Value |= op;
21484 break;
21485 }
21486 case AArch64::ASR_ZZI_D:
21487 case AArch64::LSR_ZZI_D: {
21488 // op: Zd
21489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21490 op &= UINT64_C(31);
21491 Value |= op;
21492 // op: Zn
21493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21494 op &= UINT64_C(31);
21495 op <<= 5;
21496 Value |= op;
21497 // op: imm
21498 op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI);
21499 Value |= (op & UINT64_C(32)) << 17;
21500 Value |= (op & UINT64_C(31)) << 16;
21501 break;
21502 }
21503 case AArch64::ASR_ZZI_B:
21504 case AArch64::LSR_ZZI_B:
21505 case AArch64::RSHRNB_ZZI_B:
21506 case AArch64::SHRNB_ZZI_B:
21507 case AArch64::SQRSHRNB_ZZI_B:
21508 case AArch64::SQRSHRUNB_ZZI_B:
21509 case AArch64::SQSHRNB_ZZI_B:
21510 case AArch64::SQSHRUNB_ZZI_B:
21511 case AArch64::UQRSHRNB_ZZI_B:
21512 case AArch64::UQSHRNB_ZZI_B: {
21513 // op: Zd
21514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21515 op &= UINT64_C(31);
21516 Value |= op;
21517 // op: Zn
21518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21519 op &= UINT64_C(31);
21520 op <<= 5;
21521 Value |= op;
21522 // op: imm
21523 op = getVecShiftR8OpValue(MI, OpIdx: 2, Fixups, STI);
21524 op &= UINT64_C(7);
21525 op <<= 16;
21526 Value |= op;
21527 break;
21528 }
21529 case AArch64::EXT_ZZI_B: {
21530 // op: Zd
21531 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21532 op &= UINT64_C(31);
21533 Value |= op;
21534 // op: Zn
21535 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21536 op &= UINT64_C(31);
21537 op <<= 5;
21538 Value |= op;
21539 // op: imm8
21540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21541 Value |= (op & UINT64_C(248)) << 13;
21542 Value |= (op & UINT64_C(7)) << 10;
21543 break;
21544 }
21545 case AArch64::DUPQ_ZZI_D: {
21546 // op: Zd
21547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21548 op &= UINT64_C(31);
21549 Value |= op;
21550 // op: Zn
21551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21552 op &= UINT64_C(31);
21553 op <<= 5;
21554 Value |= op;
21555 // op: index
21556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21557 op &= UINT64_C(1);
21558 op <<= 20;
21559 Value |= op;
21560 break;
21561 }
21562 case AArch64::DUPQ_ZZI_B: {
21563 // op: Zd
21564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21565 op &= UINT64_C(31);
21566 Value |= op;
21567 // op: Zn
21568 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21569 op &= UINT64_C(31);
21570 op <<= 5;
21571 Value |= op;
21572 // op: index
21573 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21574 op &= UINT64_C(15);
21575 op <<= 17;
21576 Value |= op;
21577 break;
21578 }
21579 case AArch64::DUPQ_ZZI_S: {
21580 // op: Zd
21581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21582 op &= UINT64_C(31);
21583 Value |= op;
21584 // op: Zn
21585 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21586 op &= UINT64_C(31);
21587 op <<= 5;
21588 Value |= op;
21589 // op: index
21590 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21591 op &= UINT64_C(3);
21592 op <<= 19;
21593 Value |= op;
21594 break;
21595 }
21596 case AArch64::DUPQ_ZZI_H: {
21597 // op: Zd
21598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21599 op &= UINT64_C(31);
21600 Value |= op;
21601 // op: Zn
21602 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21603 op &= UINT64_C(31);
21604 op <<= 5;
21605 Value |= op;
21606 // op: index
21607 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21608 op &= UINT64_C(7);
21609 op <<= 18;
21610 Value |= op;
21611 break;
21612 }
21613 case AArch64::SQXTNT_ZZ_B:
21614 case AArch64::SQXTNT_ZZ_H:
21615 case AArch64::SQXTNT_ZZ_S:
21616 case AArch64::SQXTUNT_ZZ_B:
21617 case AArch64::SQXTUNT_ZZ_H:
21618 case AArch64::SQXTUNT_ZZ_S:
21619 case AArch64::UQXTNT_ZZ_B:
21620 case AArch64::UQXTNT_ZZ_H:
21621 case AArch64::UQXTNT_ZZ_S: {
21622 // op: Zd
21623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21624 op &= UINT64_C(31);
21625 Value |= op;
21626 // op: Zn
21627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21628 op &= UINT64_C(31);
21629 op <<= 5;
21630 Value |= op;
21631 break;
21632 }
21633 case AArch64::FCVTLT_ZPzZ_HtoS:
21634 case AArch64::FCVTLT_ZPzZ_StoD: {
21635 // op: Zd
21636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21637 op &= UINT64_C(31);
21638 Value |= op;
21639 // op: Zn
21640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21641 op &= UINT64_C(31);
21642 op <<= 5;
21643 Value |= op;
21644 // op: Pg
21645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21646 op &= UINT64_C(7);
21647 op <<= 10;
21648 Value |= op;
21649 break;
21650 }
21651 case AArch64::HISTCNT_ZPzZZ_D:
21652 case AArch64::HISTCNT_ZPzZZ_S: {
21653 // op: Zd
21654 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21655 op &= UINT64_C(31);
21656 Value |= op;
21657 // op: Zn
21658 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21659 op &= UINT64_C(31);
21660 op <<= 5;
21661 Value |= op;
21662 // op: Pg
21663 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21664 op &= UINT64_C(7);
21665 op <<= 10;
21666 Value |= op;
21667 // op: Zm
21668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21669 op &= UINT64_C(31);
21670 op <<= 16;
21671 Value |= op;
21672 break;
21673 }
21674 case AArch64::ADDHNT_ZZZ_B:
21675 case AArch64::ADDHNT_ZZZ_H:
21676 case AArch64::ADDHNT_ZZZ_S:
21677 case AArch64::EORBT_ZZZ_B:
21678 case AArch64::EORBT_ZZZ_D:
21679 case AArch64::EORBT_ZZZ_H:
21680 case AArch64::EORBT_ZZZ_S:
21681 case AArch64::EORTB_ZZZ_B:
21682 case AArch64::EORTB_ZZZ_D:
21683 case AArch64::EORTB_ZZZ_H:
21684 case AArch64::EORTB_ZZZ_S:
21685 case AArch64::RADDHNT_ZZZ_B:
21686 case AArch64::RADDHNT_ZZZ_H:
21687 case AArch64::RADDHNT_ZZZ_S:
21688 case AArch64::RSUBHNT_ZZZ_B:
21689 case AArch64::RSUBHNT_ZZZ_H:
21690 case AArch64::RSUBHNT_ZZZ_S:
21691 case AArch64::SUBHNT_ZZZ_B:
21692 case AArch64::SUBHNT_ZZZ_H:
21693 case AArch64::SUBHNT_ZZZ_S: {
21694 // op: Zd
21695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21696 op &= UINT64_C(31);
21697 Value |= op;
21698 // op: Zn
21699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21700 op &= UINT64_C(31);
21701 op <<= 5;
21702 Value |= op;
21703 // op: Zm
21704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21705 op &= UINT64_C(31);
21706 op <<= 16;
21707 Value |= op;
21708 break;
21709 }
21710 case AArch64::SLI_ZZI_H: {
21711 // op: Zd
21712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21713 op &= UINT64_C(31);
21714 Value |= op;
21715 // op: Zn
21716 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21717 op &= UINT64_C(31);
21718 op <<= 5;
21719 Value |= op;
21720 // op: imm
21721 op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI);
21722 op &= UINT64_C(15);
21723 op <<= 16;
21724 Value |= op;
21725 break;
21726 }
21727 case AArch64::SLI_ZZI_S: {
21728 // op: Zd
21729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21730 op &= UINT64_C(31);
21731 Value |= op;
21732 // op: Zn
21733 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21734 op &= UINT64_C(31);
21735 op <<= 5;
21736 Value |= op;
21737 // op: imm
21738 op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI);
21739 op &= UINT64_C(31);
21740 op <<= 16;
21741 Value |= op;
21742 break;
21743 }
21744 case AArch64::SLI_ZZI_D: {
21745 // op: Zd
21746 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21747 op &= UINT64_C(31);
21748 Value |= op;
21749 // op: Zn
21750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21751 op &= UINT64_C(31);
21752 op <<= 5;
21753 Value |= op;
21754 // op: imm
21755 op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI);
21756 Value |= (op & UINT64_C(32)) << 17;
21757 Value |= (op & UINT64_C(31)) << 16;
21758 break;
21759 }
21760 case AArch64::SLI_ZZI_B: {
21761 // op: Zd
21762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21763 op &= UINT64_C(31);
21764 Value |= op;
21765 // op: Zn
21766 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21767 op &= UINT64_C(31);
21768 op <<= 5;
21769 Value |= op;
21770 // op: imm
21771 op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI);
21772 op &= UINT64_C(7);
21773 op <<= 16;
21774 Value |= op;
21775 break;
21776 }
21777 case AArch64::RSHRNT_ZZI_H:
21778 case AArch64::SHRNT_ZZI_H:
21779 case AArch64::SQRSHRNT_ZZI_H:
21780 case AArch64::SQRSHRUNT_ZZI_H:
21781 case AArch64::SQSHRNT_ZZI_H:
21782 case AArch64::SQSHRUNT_ZZI_H:
21783 case AArch64::SRI_ZZI_H:
21784 case AArch64::UQRSHRNT_ZZI_H:
21785 case AArch64::UQSHRNT_ZZI_H: {
21786 // op: Zd
21787 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21788 op &= UINT64_C(31);
21789 Value |= op;
21790 // op: Zn
21791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21792 op &= UINT64_C(31);
21793 op <<= 5;
21794 Value |= op;
21795 // op: imm
21796 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
21797 op &= UINT64_C(15);
21798 op <<= 16;
21799 Value |= op;
21800 break;
21801 }
21802 case AArch64::RSHRNT_ZZI_S:
21803 case AArch64::SHRNT_ZZI_S:
21804 case AArch64::SQRSHRNT_ZZI_S:
21805 case AArch64::SQRSHRUNT_ZZI_S:
21806 case AArch64::SQSHRNT_ZZI_S:
21807 case AArch64::SQSHRUNT_ZZI_S:
21808 case AArch64::SRI_ZZI_S:
21809 case AArch64::UQRSHRNT_ZZI_S:
21810 case AArch64::UQSHRNT_ZZI_S: {
21811 // op: Zd
21812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21813 op &= UINT64_C(31);
21814 Value |= op;
21815 // op: Zn
21816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21817 op &= UINT64_C(31);
21818 op <<= 5;
21819 Value |= op;
21820 // op: imm
21821 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
21822 op &= UINT64_C(31);
21823 op <<= 16;
21824 Value |= op;
21825 break;
21826 }
21827 case AArch64::SRI_ZZI_D: {
21828 // op: Zd
21829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21830 op &= UINT64_C(31);
21831 Value |= op;
21832 // op: Zn
21833 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21834 op &= UINT64_C(31);
21835 op <<= 5;
21836 Value |= op;
21837 // op: imm
21838 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
21839 Value |= (op & UINT64_C(32)) << 17;
21840 Value |= (op & UINT64_C(31)) << 16;
21841 break;
21842 }
21843 case AArch64::RSHRNT_ZZI_B:
21844 case AArch64::SHRNT_ZZI_B:
21845 case AArch64::SQRSHRNT_ZZI_B:
21846 case AArch64::SQRSHRUNT_ZZI_B:
21847 case AArch64::SQSHRNT_ZZI_B:
21848 case AArch64::SQSHRUNT_ZZI_B:
21849 case AArch64::SRI_ZZI_B:
21850 case AArch64::UQRSHRNT_ZZI_B:
21851 case AArch64::UQSHRNT_ZZI_B: {
21852 // op: Zd
21853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21854 op &= UINT64_C(31);
21855 Value |= op;
21856 // op: Zn
21857 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21858 op &= UINT64_C(31);
21859 op <<= 5;
21860 Value |= op;
21861 // op: imm
21862 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
21863 op &= UINT64_C(7);
21864 op <<= 16;
21865 Value |= op;
21866 break;
21867 }
21868 case AArch64::BFCVTNT_ZPmZ:
21869 case AArch64::BFCVTNT_ZPzZ:
21870 case AArch64::FCVTLT_ZPmZ_HtoS:
21871 case AArch64::FCVTLT_ZPmZ_StoD:
21872 case AArch64::FCVTNT_ZPmZ_DtoS:
21873 case AArch64::FCVTNT_ZPmZ_StoH:
21874 case AArch64::FCVTNT_ZPzZ_DtoS:
21875 case AArch64::FCVTNT_ZPzZ_StoH:
21876 case AArch64::FCVTXNT_ZPmZ_DtoS:
21877 case AArch64::FCVTXNT_ZPzZ: {
21878 // op: Zd
21879 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21880 op &= UINT64_C(31);
21881 Value |= op;
21882 // op: Zn
21883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21884 op &= UINT64_C(31);
21885 op <<= 5;
21886 Value |= op;
21887 // op: Pg
21888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21889 op &= UINT64_C(7);
21890 op <<= 10;
21891 Value |= op;
21892 break;
21893 }
21894 case AArch64::DUP_ZI_B:
21895 case AArch64::DUP_ZI_D:
21896 case AArch64::DUP_ZI_H:
21897 case AArch64::DUP_ZI_S: {
21898 // op: Zd
21899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21900 op &= UINT64_C(31);
21901 Value |= op;
21902 // op: imm
21903 op = getImm8OptLsl(MI, OpIdx: 1, Fixups, STI);
21904 op &= UINT64_C(511);
21905 op <<= 5;
21906 Value |= op;
21907 break;
21908 }
21909 case AArch64::INDEX_II_B:
21910 case AArch64::INDEX_II_D:
21911 case AArch64::INDEX_II_H:
21912 case AArch64::INDEX_II_S: {
21913 // op: Zd
21914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21915 op &= UINT64_C(31);
21916 Value |= op;
21917 // op: imm5
21918 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21919 op &= UINT64_C(31);
21920 op <<= 5;
21921 Value |= op;
21922 // op: imm5b
21923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21924 op &= UINT64_C(31);
21925 op <<= 16;
21926 Value |= op;
21927 break;
21928 }
21929 case AArch64::FDUP_ZI_D:
21930 case AArch64::FDUP_ZI_H:
21931 case AArch64::FDUP_ZI_S: {
21932 // op: Zd
21933 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21934 op &= UINT64_C(31);
21935 Value |= op;
21936 // op: imm8
21937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21938 op &= UINT64_C(255);
21939 op <<= 5;
21940 Value |= op;
21941 break;
21942 }
21943 case AArch64::DUPM_ZI: {
21944 // op: Zd
21945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21946 op &= UINT64_C(31);
21947 Value |= op;
21948 // op: imms
21949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21950 op &= UINT64_C(8191);
21951 op <<= 5;
21952 Value |= op;
21953 break;
21954 }
21955 case AArch64::FCMLA_ZPmZZ_D:
21956 case AArch64::FCMLA_ZPmZZ_H:
21957 case AArch64::FCMLA_ZPmZZ_S: {
21958 // op: Zda
21959 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21960 op &= UINT64_C(31);
21961 Value |= op;
21962 // op: Pg
21963 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
21964 op &= UINT64_C(7);
21965 op <<= 10;
21966 Value |= op;
21967 // op: Zn
21968 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21969 op &= UINT64_C(31);
21970 op <<= 5;
21971 Value |= op;
21972 // op: Zm
21973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
21974 op &= UINT64_C(31);
21975 op <<= 16;
21976 Value |= op;
21977 // op: imm
21978 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21979 op &= UINT64_C(3);
21980 op <<= 13;
21981 Value |= op;
21982 break;
21983 }
21984 case AArch64::SMLALB_ZZZI_D:
21985 case AArch64::SMLALT_ZZZI_D:
21986 case AArch64::SMLSLB_ZZZI_D:
21987 case AArch64::SMLSLT_ZZZI_D:
21988 case AArch64::SQDMLALB_ZZZI_D:
21989 case AArch64::SQDMLALT_ZZZI_D:
21990 case AArch64::SQDMLSLB_ZZZI_D:
21991 case AArch64::SQDMLSLT_ZZZI_D:
21992 case AArch64::UMLALB_ZZZI_D:
21993 case AArch64::UMLALT_ZZZI_D:
21994 case AArch64::UMLSLB_ZZZI_D:
21995 case AArch64::UMLSLT_ZZZI_D: {
21996 // op: Zda
21997 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21998 op &= UINT64_C(31);
21999 Value |= op;
22000 // op: Zn
22001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22002 op &= UINT64_C(31);
22003 op <<= 5;
22004 Value |= op;
22005 // op: Zm
22006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22007 op &= UINT64_C(15);
22008 op <<= 16;
22009 Value |= op;
22010 // op: iop
22011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22012 Value |= (op & UINT64_C(2)) << 19;
22013 Value |= (op & UINT64_C(1)) << 11;
22014 break;
22015 }
22016 case AArch64::FMLA_ZZZI_D:
22017 case AArch64::FMLS_ZZZI_D:
22018 case AArch64::MLA_ZZZI_D:
22019 case AArch64::MLS_ZZZI_D:
22020 case AArch64::SQRDMLAH_ZZZI_D:
22021 case AArch64::SQRDMLSH_ZZZI_D: {
22022 // op: Zda
22023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22024 op &= UINT64_C(31);
22025 Value |= op;
22026 // op: Zn
22027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22028 op &= UINT64_C(31);
22029 op <<= 5;
22030 Value |= op;
22031 // op: Zm
22032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22033 op &= UINT64_C(15);
22034 op <<= 16;
22035 Value |= op;
22036 // op: iop
22037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22038 op &= UINT64_C(1);
22039 op <<= 20;
22040 Value |= op;
22041 break;
22042 }
22043 case AArch64::ADCLB_ZZZ_D:
22044 case AArch64::ADCLB_ZZZ_S:
22045 case AArch64::ADCLT_ZZZ_D:
22046 case AArch64::ADCLT_ZZZ_S:
22047 case AArch64::BFDOT_ZZZ:
22048 case AArch64::BFMLALB_ZZZ:
22049 case AArch64::BFMLALT_ZZZ:
22050 case AArch64::BFMLSLB_ZZZ_S:
22051 case AArch64::BFMLSLT_ZZZ_S:
22052 case AArch64::BFMMLA_ZZZ:
22053 case AArch64::FDOT_ZZZ_BtoH:
22054 case AArch64::FDOT_ZZZ_BtoS:
22055 case AArch64::FDOT_ZZZ_S:
22056 case AArch64::FMLALB_ZZZ:
22057 case AArch64::FMLALB_ZZZ_SHH:
22058 case AArch64::FMLALLBB_ZZZ:
22059 case AArch64::FMLALLBT_ZZZ:
22060 case AArch64::FMLALLTB_ZZZ:
22061 case AArch64::FMLALLTT_ZZZ:
22062 case AArch64::FMLALT_ZZZ:
22063 case AArch64::FMLALT_ZZZ_SHH:
22064 case AArch64::FMLLA_ZZZ_HtoS:
22065 case AArch64::FMLSLB_ZZZ_SHH:
22066 case AArch64::FMLSLT_ZZZ_SHH:
22067 case AArch64::FMMLA_ZZZ_BtoH:
22068 case AArch64::FMMLA_ZZZ_BtoS:
22069 case AArch64::FMMLA_ZZZ_D:
22070 case AArch64::FMMLA_ZZZ_S:
22071 case AArch64::MLA_CPA:
22072 case AArch64::SABALB_ZZZ_D:
22073 case AArch64::SABALB_ZZZ_H:
22074 case AArch64::SABALB_ZZZ_S:
22075 case AArch64::SABALT_ZZZ_D:
22076 case AArch64::SABALT_ZZZ_H:
22077 case AArch64::SABALT_ZZZ_S:
22078 case AArch64::SABA_ZZZ_B:
22079 case AArch64::SABA_ZZZ_D:
22080 case AArch64::SABA_ZZZ_H:
22081 case AArch64::SABA_ZZZ_S:
22082 case AArch64::SBCLB_ZZZ_D:
22083 case AArch64::SBCLB_ZZZ_S:
22084 case AArch64::SBCLT_ZZZ_D:
22085 case AArch64::SBCLT_ZZZ_S:
22086 case AArch64::SDOT_ZZZ_D:
22087 case AArch64::SDOT_ZZZ_HtoS:
22088 case AArch64::SDOT_ZZZ_S:
22089 case AArch64::SMLALB_ZZZ_D:
22090 case AArch64::SMLALB_ZZZ_H:
22091 case AArch64::SMLALB_ZZZ_S:
22092 case AArch64::SMLALT_ZZZ_D:
22093 case AArch64::SMLALT_ZZZ_H:
22094 case AArch64::SMLALT_ZZZ_S:
22095 case AArch64::SMLSLB_ZZZ_D:
22096 case AArch64::SMLSLB_ZZZ_H:
22097 case AArch64::SMLSLB_ZZZ_S:
22098 case AArch64::SMLSLT_ZZZ_D:
22099 case AArch64::SMLSLT_ZZZ_H:
22100 case AArch64::SMLSLT_ZZZ_S:
22101 case AArch64::SMMLA_ZZZ:
22102 case AArch64::SQDMLALBT_ZZZ_D:
22103 case AArch64::SQDMLALBT_ZZZ_H:
22104 case AArch64::SQDMLALBT_ZZZ_S:
22105 case AArch64::SQDMLALB_ZZZ_D:
22106 case AArch64::SQDMLALB_ZZZ_H:
22107 case AArch64::SQDMLALB_ZZZ_S:
22108 case AArch64::SQDMLALT_ZZZ_D:
22109 case AArch64::SQDMLALT_ZZZ_H:
22110 case AArch64::SQDMLALT_ZZZ_S:
22111 case AArch64::SQDMLSLBT_ZZZ_D:
22112 case AArch64::SQDMLSLBT_ZZZ_H:
22113 case AArch64::SQDMLSLBT_ZZZ_S:
22114 case AArch64::SQDMLSLB_ZZZ_D:
22115 case AArch64::SQDMLSLB_ZZZ_H:
22116 case AArch64::SQDMLSLB_ZZZ_S:
22117 case AArch64::SQDMLSLT_ZZZ_D:
22118 case AArch64::SQDMLSLT_ZZZ_H:
22119 case AArch64::SQDMLSLT_ZZZ_S:
22120 case AArch64::SQRDMLAH_ZZZ_B:
22121 case AArch64::SQRDMLAH_ZZZ_D:
22122 case AArch64::SQRDMLAH_ZZZ_H:
22123 case AArch64::SQRDMLAH_ZZZ_S:
22124 case AArch64::SQRDMLSH_ZZZ_B:
22125 case AArch64::SQRDMLSH_ZZZ_D:
22126 case AArch64::SQRDMLSH_ZZZ_H:
22127 case AArch64::SQRDMLSH_ZZZ_S:
22128 case AArch64::UABALB_ZZZ_D:
22129 case AArch64::UABALB_ZZZ_H:
22130 case AArch64::UABALB_ZZZ_S:
22131 case AArch64::UABALT_ZZZ_D:
22132 case AArch64::UABALT_ZZZ_H:
22133 case AArch64::UABALT_ZZZ_S:
22134 case AArch64::UABA_ZZZ_B:
22135 case AArch64::UABA_ZZZ_D:
22136 case AArch64::UABA_ZZZ_H:
22137 case AArch64::UABA_ZZZ_S:
22138 case AArch64::UDOT_ZZZ_D:
22139 case AArch64::UDOT_ZZZ_HtoS:
22140 case AArch64::UDOT_ZZZ_S:
22141 case AArch64::UMLALB_ZZZ_D:
22142 case AArch64::UMLALB_ZZZ_H:
22143 case AArch64::UMLALB_ZZZ_S:
22144 case AArch64::UMLALT_ZZZ_D:
22145 case AArch64::UMLALT_ZZZ_H:
22146 case AArch64::UMLALT_ZZZ_S:
22147 case AArch64::UMLSLB_ZZZ_D:
22148 case AArch64::UMLSLB_ZZZ_H:
22149 case AArch64::UMLSLB_ZZZ_S:
22150 case AArch64::UMLSLT_ZZZ_D:
22151 case AArch64::UMLSLT_ZZZ_H:
22152 case AArch64::UMLSLT_ZZZ_S:
22153 case AArch64::UMMLA_ZZZ:
22154 case AArch64::USDOT_ZZZ:
22155 case AArch64::USMMLA_ZZZ: {
22156 // op: Zda
22157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22158 op &= UINT64_C(31);
22159 Value |= op;
22160 // op: Zn
22161 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22162 op &= UINT64_C(31);
22163 op <<= 5;
22164 Value |= op;
22165 // op: Zm
22166 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22167 op &= UINT64_C(31);
22168 op <<= 16;
22169 Value |= op;
22170 break;
22171 }
22172 case AArch64::CDOT_ZZZ_D:
22173 case AArch64::CDOT_ZZZ_S:
22174 case AArch64::CMLA_ZZZ_B:
22175 case AArch64::CMLA_ZZZ_D:
22176 case AArch64::CMLA_ZZZ_H:
22177 case AArch64::CMLA_ZZZ_S:
22178 case AArch64::SQRDCMLAH_ZZZ_B:
22179 case AArch64::SQRDCMLAH_ZZZ_D:
22180 case AArch64::SQRDCMLAH_ZZZ_H:
22181 case AArch64::SQRDCMLAH_ZZZ_S: {
22182 // op: Zda
22183 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22184 op &= UINT64_C(31);
22185 Value |= op;
22186 // op: Zn
22187 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22188 op &= UINT64_C(31);
22189 op <<= 5;
22190 Value |= op;
22191 // op: Zm
22192 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22193 op &= UINT64_C(31);
22194 op <<= 16;
22195 Value |= op;
22196 // op: rot
22197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22198 op &= UINT64_C(3);
22199 op <<= 10;
22200 Value |= op;
22201 break;
22202 }
22203 case AArch64::SDOT_ZZZI_HtoS:
22204 case AArch64::UDOT_ZZZI_HtoS: {
22205 // op: Zda
22206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22207 op &= UINT64_C(31);
22208 Value |= op;
22209 // op: Zn
22210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22211 op &= UINT64_C(31);
22212 op <<= 5;
22213 Value |= op;
22214 // op: Zm
22215 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22216 op &= UINT64_C(7);
22217 op <<= 16;
22218 Value |= op;
22219 // op: i2
22220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22221 op &= UINT64_C(3);
22222 op <<= 19;
22223 Value |= op;
22224 break;
22225 }
22226 case AArch64::SUDOT_ZZZI:
22227 case AArch64::USDOT_ZZZI: {
22228 // op: Zda
22229 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22230 op &= UINT64_C(31);
22231 Value |= op;
22232 // op: Zn
22233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22234 op &= UINT64_C(31);
22235 op <<= 5;
22236 Value |= op;
22237 // op: Zm
22238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22239 op &= UINT64_C(7);
22240 op <<= 16;
22241 Value |= op;
22242 // op: idx
22243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22244 op &= UINT64_C(3);
22245 op <<= 19;
22246 Value |= op;
22247 break;
22248 }
22249 case AArch64::FMLALB_ZZZI:
22250 case AArch64::FMLALLBB_ZZZI:
22251 case AArch64::FMLALLBT_ZZZI:
22252 case AArch64::FMLALLTB_ZZZI:
22253 case AArch64::FMLALLTT_ZZZI:
22254 case AArch64::FMLALT_ZZZI: {
22255 // op: Zda
22256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22257 op &= UINT64_C(31);
22258 Value |= op;
22259 // op: Zn
22260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22261 op &= UINT64_C(31);
22262 op <<= 5;
22263 Value |= op;
22264 // op: Zm
22265 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22266 op &= UINT64_C(7);
22267 op <<= 16;
22268 Value |= op;
22269 // op: imm4
22270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22271 Value |= (op & UINT64_C(12)) << 17;
22272 Value |= (op & UINT64_C(3)) << 10;
22273 break;
22274 }
22275 case AArch64::BFMLA_ZZZI:
22276 case AArch64::BFMLS_ZZZI:
22277 case AArch64::FMLA_ZZZI_H:
22278 case AArch64::FMLS_ZZZI_H:
22279 case AArch64::MLA_ZZZI_H:
22280 case AArch64::MLS_ZZZI_H:
22281 case AArch64::SQRDMLAH_ZZZI_H:
22282 case AArch64::SQRDMLSH_ZZZI_H: {
22283 // op: Zda
22284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22285 op &= UINT64_C(31);
22286 Value |= op;
22287 // op: Zn
22288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22289 op &= UINT64_C(31);
22290 op <<= 5;
22291 Value |= op;
22292 // op: Zm
22293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22294 op &= UINT64_C(7);
22295 op <<= 16;
22296 Value |= op;
22297 // op: iop
22298 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22299 Value |= (op & UINT64_C(4)) << 20;
22300 Value |= (op & UINT64_C(3)) << 19;
22301 break;
22302 }
22303 case AArch64::BFMLALB_ZZZI:
22304 case AArch64::BFMLALT_ZZZI:
22305 case AArch64::BFMLSLB_ZZZI_S:
22306 case AArch64::BFMLSLT_ZZZI_S:
22307 case AArch64::FDOT_ZZZI_BtoH:
22308 case AArch64::FMLALB_ZZZI_SHH:
22309 case AArch64::FMLALT_ZZZI_SHH:
22310 case AArch64::FMLSLB_ZZZI_SHH:
22311 case AArch64::FMLSLT_ZZZI_SHH:
22312 case AArch64::SMLALB_ZZZI_S:
22313 case AArch64::SMLALT_ZZZI_S:
22314 case AArch64::SMLSLB_ZZZI_S:
22315 case AArch64::SMLSLT_ZZZI_S:
22316 case AArch64::SQDMLALB_ZZZI_S:
22317 case AArch64::SQDMLALT_ZZZI_S:
22318 case AArch64::SQDMLSLB_ZZZI_S:
22319 case AArch64::SQDMLSLT_ZZZI_S:
22320 case AArch64::UMLALB_ZZZI_S:
22321 case AArch64::UMLALT_ZZZI_S:
22322 case AArch64::UMLSLB_ZZZI_S:
22323 case AArch64::UMLSLT_ZZZI_S: {
22324 // op: Zda
22325 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22326 op &= UINT64_C(31);
22327 Value |= op;
22328 // op: Zn
22329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22330 op &= UINT64_C(31);
22331 op <<= 5;
22332 Value |= op;
22333 // op: Zm
22334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22335 op &= UINT64_C(7);
22336 op <<= 16;
22337 Value |= op;
22338 // op: iop
22339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22340 Value |= (op & UINT64_C(6)) << 18;
22341 Value |= (op & UINT64_C(1)) << 11;
22342 break;
22343 }
22344 case AArch64::BFDOT_ZZI:
22345 case AArch64::FDOT_ZZZI_BtoS:
22346 case AArch64::FDOT_ZZZI_S:
22347 case AArch64::FMLA_ZZZI_S:
22348 case AArch64::FMLS_ZZZI_S:
22349 case AArch64::MLA_ZZZI_S:
22350 case AArch64::MLS_ZZZI_S:
22351 case AArch64::SQRDMLAH_ZZZI_S:
22352 case AArch64::SQRDMLSH_ZZZI_S: {
22353 // op: Zda
22354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22355 op &= UINT64_C(31);
22356 Value |= op;
22357 // op: Zn
22358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22359 op &= UINT64_C(31);
22360 op <<= 5;
22361 Value |= op;
22362 // op: Zm
22363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22364 op &= UINT64_C(7);
22365 op <<= 16;
22366 Value |= op;
22367 // op: iop
22368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22369 op &= UINT64_C(3);
22370 op <<= 19;
22371 Value |= op;
22372 break;
22373 }
22374 case AArch64::FCMLA_ZZZI_S: {
22375 // op: Zda
22376 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22377 op &= UINT64_C(31);
22378 Value |= op;
22379 // op: Zn
22380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22381 op &= UINT64_C(31);
22382 op <<= 5;
22383 Value |= op;
22384 // op: imm
22385 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22386 op &= UINT64_C(3);
22387 op <<= 10;
22388 Value |= op;
22389 // op: Zm
22390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22391 op &= UINT64_C(15);
22392 op <<= 16;
22393 Value |= op;
22394 // op: iop
22395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22396 op &= UINT64_C(1);
22397 op <<= 20;
22398 Value |= op;
22399 break;
22400 }
22401 case AArch64::FCMLA_ZZZI_H: {
22402 // op: Zda
22403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22404 op &= UINT64_C(31);
22405 Value |= op;
22406 // op: Zn
22407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22408 op &= UINT64_C(31);
22409 op <<= 5;
22410 Value |= op;
22411 // op: imm
22412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22413 op &= UINT64_C(3);
22414 op <<= 10;
22415 Value |= op;
22416 // op: Zm
22417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22418 op &= UINT64_C(7);
22419 op <<= 16;
22420 Value |= op;
22421 // op: iop
22422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22423 op &= UINT64_C(3);
22424 op <<= 19;
22425 Value |= op;
22426 break;
22427 }
22428 case AArch64::SRSRA_ZZI_H:
22429 case AArch64::SSRA_ZZI_H:
22430 case AArch64::URSRA_ZZI_H:
22431 case AArch64::USRA_ZZI_H: {
22432 // op: Zda
22433 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22434 op &= UINT64_C(31);
22435 Value |= op;
22436 // op: Zn
22437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22438 op &= UINT64_C(31);
22439 op <<= 5;
22440 Value |= op;
22441 // op: imm
22442 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
22443 op &= UINT64_C(15);
22444 op <<= 16;
22445 Value |= op;
22446 break;
22447 }
22448 case AArch64::SRSRA_ZZI_S:
22449 case AArch64::SSRA_ZZI_S:
22450 case AArch64::URSRA_ZZI_S:
22451 case AArch64::USRA_ZZI_S: {
22452 // op: Zda
22453 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22454 op &= UINT64_C(31);
22455 Value |= op;
22456 // op: Zn
22457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22458 op &= UINT64_C(31);
22459 op <<= 5;
22460 Value |= op;
22461 // op: imm
22462 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
22463 op &= UINT64_C(31);
22464 op <<= 16;
22465 Value |= op;
22466 break;
22467 }
22468 case AArch64::SRSRA_ZZI_D:
22469 case AArch64::SSRA_ZZI_D:
22470 case AArch64::URSRA_ZZI_D:
22471 case AArch64::USRA_ZZI_D: {
22472 // op: Zda
22473 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22474 op &= UINT64_C(31);
22475 Value |= op;
22476 // op: Zn
22477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22478 op &= UINT64_C(31);
22479 op <<= 5;
22480 Value |= op;
22481 // op: imm
22482 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
22483 Value |= (op & UINT64_C(32)) << 17;
22484 Value |= (op & UINT64_C(31)) << 16;
22485 break;
22486 }
22487 case AArch64::SRSRA_ZZI_B:
22488 case AArch64::SSRA_ZZI_B:
22489 case AArch64::URSRA_ZZI_B:
22490 case AArch64::USRA_ZZI_B: {
22491 // op: Zda
22492 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22493 op &= UINT64_C(31);
22494 Value |= op;
22495 // op: Zn
22496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22497 op &= UINT64_C(31);
22498 op <<= 5;
22499 Value |= op;
22500 // op: imm
22501 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
22502 op &= UINT64_C(7);
22503 op <<= 16;
22504 Value |= op;
22505 break;
22506 }
22507 case AArch64::SDOT_ZZZI_D:
22508 case AArch64::UDOT_ZZZI_D: {
22509 // op: Zda
22510 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22511 op &= UINT64_C(31);
22512 Value |= op;
22513 // op: Zn
22514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22515 op &= UINT64_C(31);
22516 op <<= 5;
22517 Value |= op;
22518 // op: iop
22519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22520 op &= UINT64_C(1);
22521 op <<= 20;
22522 Value |= op;
22523 // op: Zm
22524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22525 op &= UINT64_C(15);
22526 op <<= 16;
22527 Value |= op;
22528 break;
22529 }
22530 case AArch64::SDOT_ZZZI_S:
22531 case AArch64::UDOT_ZZZI_S: {
22532 // op: Zda
22533 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22534 op &= UINT64_C(31);
22535 Value |= op;
22536 // op: Zn
22537 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22538 op &= UINT64_C(31);
22539 op <<= 5;
22540 Value |= op;
22541 // op: iop
22542 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22543 op &= UINT64_C(3);
22544 op <<= 19;
22545 Value |= op;
22546 // op: Zm
22547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22548 op &= UINT64_C(7);
22549 op <<= 16;
22550 Value |= op;
22551 break;
22552 }
22553 case AArch64::CDOT_ZZZI_D:
22554 case AArch64::CMLA_ZZZI_S:
22555 case AArch64::SQRDCMLAH_ZZZI_S: {
22556 // op: Zda
22557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22558 op &= UINT64_C(31);
22559 Value |= op;
22560 // op: Zn
22561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22562 op &= UINT64_C(31);
22563 op <<= 5;
22564 Value |= op;
22565 // op: rot
22566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22567 op &= UINT64_C(3);
22568 op <<= 10;
22569 Value |= op;
22570 // op: iop
22571 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22572 op &= UINT64_C(1);
22573 op <<= 20;
22574 Value |= op;
22575 // op: Zm
22576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22577 op &= UINT64_C(15);
22578 op <<= 16;
22579 Value |= op;
22580 break;
22581 }
22582 case AArch64::CDOT_ZZZI_S:
22583 case AArch64::CMLA_ZZZI_H:
22584 case AArch64::SQRDCMLAH_ZZZI_H: {
22585 // op: Zda
22586 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22587 op &= UINT64_C(31);
22588 Value |= op;
22589 // op: Zn
22590 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22591 op &= UINT64_C(31);
22592 op <<= 5;
22593 Value |= op;
22594 // op: rot
22595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22596 op &= UINT64_C(3);
22597 op <<= 10;
22598 Value |= op;
22599 // op: iop
22600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22601 op &= UINT64_C(3);
22602 op <<= 19;
22603 Value |= op;
22604 // op: Zm
22605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22606 op &= UINT64_C(7);
22607 op <<= 16;
22608 Value |= op;
22609 break;
22610 }
22611 case AArch64::AESIMC_ZZ_B:
22612 case AArch64::AESMC_ZZ_B: {
22613 // op: Zdn
22614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22615 op &= UINT64_C(31);
22616 Value |= op;
22617 break;
22618 }
22619 case AArch64::BCAX_ZZZZ:
22620 case AArch64::BSL1N_ZZZZ:
22621 case AArch64::BSL2N_ZZZZ:
22622 case AArch64::BSL_ZZZZ:
22623 case AArch64::EOR3_ZZZZ:
22624 case AArch64::NBSL_ZZZZ: {
22625 // op: Zdn
22626 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22627 op &= UINT64_C(31);
22628 Value |= op;
22629 // op: Zk
22630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22631 op &= UINT64_C(31);
22632 op <<= 5;
22633 Value |= op;
22634 // op: Zm
22635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22636 op &= UINT64_C(31);
22637 op <<= 16;
22638 Value |= op;
22639 break;
22640 }
22641 case AArch64::MAD_CPA: {
22642 // op: Zdn
22643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22644 op &= UINT64_C(31);
22645 Value |= op;
22646 // op: Zm
22647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22648 op &= UINT64_C(31);
22649 op <<= 16;
22650 Value |= op;
22651 // op: Za
22652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22653 op &= UINT64_C(31);
22654 op <<= 5;
22655 Value |= op;
22656 break;
22657 }
22658 case AArch64::AESD_ZZZ_B:
22659 case AArch64::AESE_ZZZ_B:
22660 case AArch64::SM4E_ZZZ_S: {
22661 // op: Zdn
22662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22663 op &= UINT64_C(31);
22664 Value |= op;
22665 // op: Zm
22666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22667 op &= UINT64_C(31);
22668 op <<= 5;
22669 Value |= op;
22670 break;
22671 }
22672 case AArch64::XAR_ZZZI_H: {
22673 // op: Zdn
22674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22675 op &= UINT64_C(31);
22676 Value |= op;
22677 // op: Zm
22678 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22679 op &= UINT64_C(31);
22680 op <<= 5;
22681 Value |= op;
22682 // op: imm
22683 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
22684 op &= UINT64_C(15);
22685 op <<= 16;
22686 Value |= op;
22687 break;
22688 }
22689 case AArch64::XAR_ZZZI_S: {
22690 // op: Zdn
22691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22692 op &= UINT64_C(31);
22693 Value |= op;
22694 // op: Zm
22695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22696 op &= UINT64_C(31);
22697 op <<= 5;
22698 Value |= op;
22699 // op: imm
22700 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
22701 op &= UINT64_C(31);
22702 op <<= 16;
22703 Value |= op;
22704 break;
22705 }
22706 case AArch64::XAR_ZZZI_D: {
22707 // op: Zdn
22708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22709 op &= UINT64_C(31);
22710 Value |= op;
22711 // op: Zm
22712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22713 op &= UINT64_C(31);
22714 op <<= 5;
22715 Value |= op;
22716 // op: imm
22717 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
22718 Value |= (op & UINT64_C(32)) << 17;
22719 Value |= (op & UINT64_C(31)) << 16;
22720 break;
22721 }
22722 case AArch64::XAR_ZZZI_B: {
22723 // op: Zdn
22724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22725 op &= UINT64_C(31);
22726 Value |= op;
22727 // op: Zm
22728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22729 op &= UINT64_C(31);
22730 op <<= 5;
22731 Value |= op;
22732 // op: imm
22733 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
22734 op &= UINT64_C(7);
22735 op <<= 16;
22736 Value |= op;
22737 break;
22738 }
22739 case AArch64::FTMAD_ZZI_D:
22740 case AArch64::FTMAD_ZZI_H:
22741 case AArch64::FTMAD_ZZI_S: {
22742 // op: Zdn
22743 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22744 op &= UINT64_C(31);
22745 Value |= op;
22746 // op: Zm
22747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22748 op &= UINT64_C(31);
22749 op <<= 5;
22750 Value |= op;
22751 // op: imm3
22752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22753 op &= UINT64_C(7);
22754 op <<= 16;
22755 Value |= op;
22756 break;
22757 }
22758 case AArch64::EXTQ_ZZI: {
22759 // op: Zdn
22760 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22761 op &= UINT64_C(31);
22762 Value |= op;
22763 // op: Zm
22764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22765 op &= UINT64_C(31);
22766 op <<= 5;
22767 Value |= op;
22768 // op: imm4
22769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22770 op &= UINT64_C(15);
22771 op <<= 16;
22772 Value |= op;
22773 break;
22774 }
22775 case AArch64::EXT_ZZI: {
22776 // op: Zdn
22777 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22778 op &= UINT64_C(31);
22779 Value |= op;
22780 // op: Zm
22781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22782 op &= UINT64_C(31);
22783 op <<= 5;
22784 Value |= op;
22785 // op: imm8
22786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22787 Value |= (op & UINT64_C(248)) << 13;
22788 Value |= (op & UINT64_C(7)) << 10;
22789 break;
22790 }
22791 case AArch64::CADD_ZZI_B:
22792 case AArch64::CADD_ZZI_D:
22793 case AArch64::CADD_ZZI_H:
22794 case AArch64::CADD_ZZI_S:
22795 case AArch64::SQCADD_ZZI_B:
22796 case AArch64::SQCADD_ZZI_D:
22797 case AArch64::SQCADD_ZZI_H:
22798 case AArch64::SQCADD_ZZI_S: {
22799 // op: Zdn
22800 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22801 op &= UINT64_C(31);
22802 Value |= op;
22803 // op: Zm
22804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22805 op &= UINT64_C(31);
22806 op <<= 5;
22807 Value |= op;
22808 // op: rot
22809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22810 op &= UINT64_C(1);
22811 op <<= 10;
22812 Value |= op;
22813 break;
22814 }
22815 case AArch64::FCADD_ZPmZ_D:
22816 case AArch64::FCADD_ZPmZ_H:
22817 case AArch64::FCADD_ZPmZ_S: {
22818 // op: Zdn
22819 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22820 op &= UINT64_C(31);
22821 Value |= op;
22822 // op: Zm
22823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22824 op &= UINT64_C(31);
22825 op <<= 5;
22826 Value |= op;
22827 // op: Pg
22828 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
22829 op &= UINT64_C(7);
22830 op <<= 10;
22831 Value |= op;
22832 // op: imm
22833 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22834 op &= UINT64_C(1);
22835 op <<= 16;
22836 Value |= op;
22837 break;
22838 }
22839 case AArch64::ADD_ZI_B:
22840 case AArch64::ADD_ZI_D:
22841 case AArch64::ADD_ZI_H:
22842 case AArch64::ADD_ZI_S:
22843 case AArch64::SQADD_ZI_B:
22844 case AArch64::SQADD_ZI_D:
22845 case AArch64::SQADD_ZI_H:
22846 case AArch64::SQADD_ZI_S:
22847 case AArch64::SQSUB_ZI_B:
22848 case AArch64::SQSUB_ZI_D:
22849 case AArch64::SQSUB_ZI_H:
22850 case AArch64::SQSUB_ZI_S:
22851 case AArch64::SUBR_ZI_B:
22852 case AArch64::SUBR_ZI_D:
22853 case AArch64::SUBR_ZI_H:
22854 case AArch64::SUBR_ZI_S:
22855 case AArch64::SUB_ZI_B:
22856 case AArch64::SUB_ZI_D:
22857 case AArch64::SUB_ZI_H:
22858 case AArch64::SUB_ZI_S:
22859 case AArch64::UQADD_ZI_B:
22860 case AArch64::UQADD_ZI_D:
22861 case AArch64::UQADD_ZI_H:
22862 case AArch64::UQADD_ZI_S:
22863 case AArch64::UQSUB_ZI_B:
22864 case AArch64::UQSUB_ZI_D:
22865 case AArch64::UQSUB_ZI_H:
22866 case AArch64::UQSUB_ZI_S: {
22867 // op: Zdn
22868 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22869 op &= UINT64_C(31);
22870 Value |= op;
22871 // op: imm
22872 op = getImm8OptLsl(MI, OpIdx: 2, Fixups, STI);
22873 op &= UINT64_C(511);
22874 op <<= 5;
22875 Value |= op;
22876 break;
22877 }
22878 case AArch64::MUL_ZI_B:
22879 case AArch64::MUL_ZI_D:
22880 case AArch64::MUL_ZI_H:
22881 case AArch64::MUL_ZI_S:
22882 case AArch64::SMAX_ZI_B:
22883 case AArch64::SMAX_ZI_D:
22884 case AArch64::SMAX_ZI_H:
22885 case AArch64::SMAX_ZI_S:
22886 case AArch64::SMIN_ZI_B:
22887 case AArch64::SMIN_ZI_D:
22888 case AArch64::SMIN_ZI_H:
22889 case AArch64::SMIN_ZI_S:
22890 case AArch64::UMAX_ZI_B:
22891 case AArch64::UMAX_ZI_D:
22892 case AArch64::UMAX_ZI_H:
22893 case AArch64::UMAX_ZI_S:
22894 case AArch64::UMIN_ZI_B:
22895 case AArch64::UMIN_ZI_D:
22896 case AArch64::UMIN_ZI_H:
22897 case AArch64::UMIN_ZI_S: {
22898 // op: Zdn
22899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22900 op &= UINT64_C(31);
22901 Value |= op;
22902 // op: imm
22903 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22904 op &= UINT64_C(255);
22905 op <<= 5;
22906 Value |= op;
22907 break;
22908 }
22909 case AArch64::AND_ZI:
22910 case AArch64::EOR_ZI:
22911 case AArch64::ORR_ZI: {
22912 // op: Zdn
22913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22914 op &= UINT64_C(31);
22915 Value |= op;
22916 // op: imms13
22917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22918 op &= UINT64_C(8191);
22919 op <<= 5;
22920 Value |= op;
22921 break;
22922 }
22923 case AArch64::DECD_ZPiI:
22924 case AArch64::DECH_ZPiI:
22925 case AArch64::DECW_ZPiI:
22926 case AArch64::INCD_ZPiI:
22927 case AArch64::INCH_ZPiI:
22928 case AArch64::INCW_ZPiI:
22929 case AArch64::SQDECD_ZPiI:
22930 case AArch64::SQDECH_ZPiI:
22931 case AArch64::SQDECW_ZPiI:
22932 case AArch64::SQINCD_ZPiI:
22933 case AArch64::SQINCH_ZPiI:
22934 case AArch64::SQINCW_ZPiI:
22935 case AArch64::UQDECD_ZPiI:
22936 case AArch64::UQDECH_ZPiI:
22937 case AArch64::UQDECW_ZPiI:
22938 case AArch64::UQINCD_ZPiI:
22939 case AArch64::UQINCH_ZPiI:
22940 case AArch64::UQINCW_ZPiI: {
22941 // op: Zdn
22942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22943 op &= UINT64_C(31);
22944 Value |= op;
22945 // op: pattern
22946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22947 op &= UINT64_C(31);
22948 op <<= 5;
22949 Value |= op;
22950 // op: imm4
22951 op = getSVEIncDecImm(MI, OpIdx: 3, Fixups, STI);
22952 op &= UINT64_C(15);
22953 op <<= 16;
22954 Value |= op;
22955 break;
22956 }
22957 case AArch64::BFMAXNM_VG2_2Z2Z_H:
22958 case AArch64::BFMAX_VG2_2Z2Z_H:
22959 case AArch64::BFMINNM_VG2_2Z2Z_H:
22960 case AArch64::BFMIN_VG2_2Z2Z_H:
22961 case AArch64::BFSCALE_2Z2Z:
22962 case AArch64::FAMAX_2Z2Z_D:
22963 case AArch64::FAMAX_2Z2Z_H:
22964 case AArch64::FAMAX_2Z2Z_S:
22965 case AArch64::FAMIN_2Z2Z_D:
22966 case AArch64::FAMIN_2Z2Z_H:
22967 case AArch64::FAMIN_2Z2Z_S:
22968 case AArch64::FMAXNM_VG2_2Z2Z_D:
22969 case AArch64::FMAXNM_VG2_2Z2Z_H:
22970 case AArch64::FMAXNM_VG2_2Z2Z_S:
22971 case AArch64::FMAX_VG2_2Z2Z_D:
22972 case AArch64::FMAX_VG2_2Z2Z_H:
22973 case AArch64::FMAX_VG2_2Z2Z_S:
22974 case AArch64::FMINNM_VG2_2Z2Z_D:
22975 case AArch64::FMINNM_VG2_2Z2Z_H:
22976 case AArch64::FMINNM_VG2_2Z2Z_S:
22977 case AArch64::FMIN_VG2_2Z2Z_D:
22978 case AArch64::FMIN_VG2_2Z2Z_H:
22979 case AArch64::FMIN_VG2_2Z2Z_S:
22980 case AArch64::FSCALE_2Z2Z_D:
22981 case AArch64::FSCALE_2Z2Z_H:
22982 case AArch64::FSCALE_2Z2Z_S:
22983 case AArch64::SMAX_VG2_2Z2Z_B:
22984 case AArch64::SMAX_VG2_2Z2Z_D:
22985 case AArch64::SMAX_VG2_2Z2Z_H:
22986 case AArch64::SMAX_VG2_2Z2Z_S:
22987 case AArch64::SMIN_VG2_2Z2Z_B:
22988 case AArch64::SMIN_VG2_2Z2Z_D:
22989 case AArch64::SMIN_VG2_2Z2Z_H:
22990 case AArch64::SMIN_VG2_2Z2Z_S:
22991 case AArch64::SQDMULH_VG2_2Z2Z_B:
22992 case AArch64::SQDMULH_VG2_2Z2Z_D:
22993 case AArch64::SQDMULH_VG2_2Z2Z_H:
22994 case AArch64::SQDMULH_VG2_2Z2Z_S:
22995 case AArch64::SRSHL_VG2_2Z2Z_B:
22996 case AArch64::SRSHL_VG2_2Z2Z_D:
22997 case AArch64::SRSHL_VG2_2Z2Z_H:
22998 case AArch64::SRSHL_VG2_2Z2Z_S:
22999 case AArch64::UMAX_VG2_2Z2Z_B:
23000 case AArch64::UMAX_VG2_2Z2Z_D:
23001 case AArch64::UMAX_VG2_2Z2Z_H:
23002 case AArch64::UMAX_VG2_2Z2Z_S:
23003 case AArch64::UMIN_VG2_2Z2Z_B:
23004 case AArch64::UMIN_VG2_2Z2Z_D:
23005 case AArch64::UMIN_VG2_2Z2Z_H:
23006 case AArch64::UMIN_VG2_2Z2Z_S:
23007 case AArch64::URSHL_VG2_2Z2Z_B:
23008 case AArch64::URSHL_VG2_2Z2Z_D:
23009 case AArch64::URSHL_VG2_2Z2Z_H:
23010 case AArch64::URSHL_VG2_2Z2Z_S: {
23011 // op: Zm
23012 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI);
23013 op &= UINT64_C(15);
23014 op <<= 17;
23015 Value |= op;
23016 // op: Zdn
23017 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
23018 op &= UINT64_C(15);
23019 op <<= 1;
23020 Value |= op;
23021 break;
23022 }
23023 case AArch64::FMLALL_VG2_M2Z2Z_BtoS:
23024 case AArch64::SMLALL_VG2_M2Z2Z_BtoS:
23025 case AArch64::SMLALL_VG2_M2Z2Z_HtoD:
23026 case AArch64::SMLSLL_VG2_M2Z2Z_BtoS:
23027 case AArch64::SMLSLL_VG2_M2Z2Z_HtoD:
23028 case AArch64::UMLALL_VG2_M2Z2Z_BtoS:
23029 case AArch64::UMLALL_VG2_M2Z2Z_HtoD:
23030 case AArch64::UMLSLL_VG2_M2Z2Z_BtoS:
23031 case AArch64::UMLSLL_VG2_M2Z2Z_HtoD:
23032 case AArch64::USMLALL_VG2_M2Z2Z_BtoS: {
23033 // op: Zm
23034 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 5, Fixups, STI);
23035 op &= UINT64_C(15);
23036 op <<= 17;
23037 Value |= op;
23038 // op: Rv
23039 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23040 op &= UINT64_C(3);
23041 op <<= 13;
23042 Value |= op;
23043 // op: Zn
23044 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
23045 op &= UINT64_C(15);
23046 op <<= 6;
23047 Value |= op;
23048 // op: imm
23049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23050 op &= UINT64_C(1);
23051 Value |= op;
23052 break;
23053 }
23054 case AArch64::ADD_VG2_M2Z2Z_D:
23055 case AArch64::ADD_VG2_M2Z2Z_S:
23056 case AArch64::BFDOT_VG2_M2Z2Z_HtoS:
23057 case AArch64::BFMLA_VG2_M2Z2Z:
23058 case AArch64::BFMLS_VG2_M2Z2Z:
23059 case AArch64::FDOT_VG2_M2Z2Z_BtoH:
23060 case AArch64::FDOT_VG2_M2Z2Z_BtoS:
23061 case AArch64::FDOT_VG2_M2Z2Z_HtoS:
23062 case AArch64::FMLA_VG2_M2Z2Z_D:
23063 case AArch64::FMLA_VG2_M2Z2Z_H:
23064 case AArch64::FMLA_VG2_M2Z2Z_S:
23065 case AArch64::FMLS_VG2_M2Z2Z_D:
23066 case AArch64::FMLS_VG2_M2Z2Z_H:
23067 case AArch64::FMLS_VG2_M2Z2Z_S:
23068 case AArch64::SDOT_VG2_M2Z2Z_BtoS:
23069 case AArch64::SDOT_VG2_M2Z2Z_HtoD:
23070 case AArch64::SDOT_VG2_M2Z2Z_HtoS:
23071 case AArch64::SUB_VG2_M2Z2Z_D:
23072 case AArch64::SUB_VG2_M2Z2Z_S:
23073 case AArch64::UDOT_VG2_M2Z2Z_BtoS:
23074 case AArch64::UDOT_VG2_M2Z2Z_HtoD:
23075 case AArch64::UDOT_VG2_M2Z2Z_HtoS:
23076 case AArch64::USDOT_VG2_M2Z2Z_BToS: {
23077 // op: Zm
23078 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 5, Fixups, STI);
23079 op &= UINT64_C(15);
23080 op <<= 17;
23081 Value |= op;
23082 // op: Zn
23083 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
23084 op &= UINT64_C(15);
23085 op <<= 6;
23086 Value |= op;
23087 // op: Rv
23088 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23089 op &= UINT64_C(3);
23090 op <<= 13;
23091 Value |= op;
23092 // op: imm3
23093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23094 op &= UINT64_C(7);
23095 Value |= op;
23096 break;
23097 }
23098 case AArch64::BFMAXNM_VG4_4Z2Z_H:
23099 case AArch64::BFMAX_VG4_4Z2Z_H:
23100 case AArch64::BFMINNM_VG4_4Z2Z_H:
23101 case AArch64::BFMIN_VG4_4Z2Z_H:
23102 case AArch64::BFSCALE_4Z4Z:
23103 case AArch64::FAMAX_4Z4Z_D:
23104 case AArch64::FAMAX_4Z4Z_H:
23105 case AArch64::FAMAX_4Z4Z_S:
23106 case AArch64::FAMIN_4Z4Z_D:
23107 case AArch64::FAMIN_4Z4Z_H:
23108 case AArch64::FAMIN_4Z4Z_S:
23109 case AArch64::FMAXNM_VG4_4Z4Z_D:
23110 case AArch64::FMAXNM_VG4_4Z4Z_H:
23111 case AArch64::FMAXNM_VG4_4Z4Z_S:
23112 case AArch64::FMAX_VG4_4Z4Z_D:
23113 case AArch64::FMAX_VG4_4Z4Z_H:
23114 case AArch64::FMAX_VG4_4Z4Z_S:
23115 case AArch64::FMINNM_VG4_4Z4Z_D:
23116 case AArch64::FMINNM_VG4_4Z4Z_H:
23117 case AArch64::FMINNM_VG4_4Z4Z_S:
23118 case AArch64::FMIN_VG4_4Z4Z_D:
23119 case AArch64::FMIN_VG4_4Z4Z_H:
23120 case AArch64::FMIN_VG4_4Z4Z_S:
23121 case AArch64::FSCALE_4Z4Z_D:
23122 case AArch64::FSCALE_4Z4Z_H:
23123 case AArch64::FSCALE_4Z4Z_S:
23124 case AArch64::SMAX_VG4_4Z4Z_B:
23125 case AArch64::SMAX_VG4_4Z4Z_D:
23126 case AArch64::SMAX_VG4_4Z4Z_H:
23127 case AArch64::SMAX_VG4_4Z4Z_S:
23128 case AArch64::SMIN_VG4_4Z4Z_B:
23129 case AArch64::SMIN_VG4_4Z4Z_D:
23130 case AArch64::SMIN_VG4_4Z4Z_H:
23131 case AArch64::SMIN_VG4_4Z4Z_S:
23132 case AArch64::SQDMULH_VG4_4Z4Z_B:
23133 case AArch64::SQDMULH_VG4_4Z4Z_D:
23134 case AArch64::SQDMULH_VG4_4Z4Z_H:
23135 case AArch64::SQDMULH_VG4_4Z4Z_S:
23136 case AArch64::SRSHL_VG4_4Z4Z_B:
23137 case AArch64::SRSHL_VG4_4Z4Z_D:
23138 case AArch64::SRSHL_VG4_4Z4Z_H:
23139 case AArch64::SRSHL_VG4_4Z4Z_S:
23140 case AArch64::UMAX_VG4_4Z4Z_B:
23141 case AArch64::UMAX_VG4_4Z4Z_D:
23142 case AArch64::UMAX_VG4_4Z4Z_H:
23143 case AArch64::UMAX_VG4_4Z4Z_S:
23144 case AArch64::UMIN_VG4_4Z4Z_B:
23145 case AArch64::UMIN_VG4_4Z4Z_D:
23146 case AArch64::UMIN_VG4_4Z4Z_H:
23147 case AArch64::UMIN_VG4_4Z4Z_S:
23148 case AArch64::URSHL_VG4_4Z4Z_B:
23149 case AArch64::URSHL_VG4_4Z4Z_D:
23150 case AArch64::URSHL_VG4_4Z4Z_H:
23151 case AArch64::URSHL_VG4_4Z4Z_S: {
23152 // op: Zm
23153 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 2, Fixups, STI);
23154 op &= UINT64_C(7);
23155 op <<= 18;
23156 Value |= op;
23157 // op: Zdn
23158 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
23159 op &= UINT64_C(7);
23160 op <<= 2;
23161 Value |= op;
23162 break;
23163 }
23164 case AArch64::FMLALL_VG4_M4Z4Z_BtoS:
23165 case AArch64::SMLALL_VG4_M4Z4Z_BtoS:
23166 case AArch64::SMLALL_VG4_M4Z4Z_HtoD:
23167 case AArch64::SMLSLL_VG4_M4Z4Z_BtoS:
23168 case AArch64::SMLSLL_VG4_M4Z4Z_HtoD:
23169 case AArch64::UMLALL_VG4_M4Z4Z_BtoS:
23170 case AArch64::UMLALL_VG4_M4Z4Z_HtoD:
23171 case AArch64::UMLSLL_VG4_M4Z4Z_BtoS:
23172 case AArch64::UMLSLL_VG4_M4Z4Z_HtoD:
23173 case AArch64::USMLALL_VG4_M4Z4Z_BtoS: {
23174 // op: Zm
23175 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 5, Fixups, STI);
23176 op &= UINT64_C(7);
23177 op <<= 18;
23178 Value |= op;
23179 // op: Rv
23180 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23181 op &= UINT64_C(3);
23182 op <<= 13;
23183 Value |= op;
23184 // op: Zn
23185 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
23186 op &= UINT64_C(7);
23187 op <<= 7;
23188 Value |= op;
23189 // op: imm
23190 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23191 op &= UINT64_C(1);
23192 Value |= op;
23193 break;
23194 }
23195 case AArch64::ADD_VG4_M4Z4Z_D:
23196 case AArch64::ADD_VG4_M4Z4Z_S:
23197 case AArch64::BFDOT_VG4_M4Z4Z_HtoS:
23198 case AArch64::BFMLA_VG4_M4Z4Z:
23199 case AArch64::BFMLS_VG4_M4Z4Z:
23200 case AArch64::FDOT_VG4_M4Z4Z_BtoH:
23201 case AArch64::FDOT_VG4_M4Z4Z_BtoS:
23202 case AArch64::FDOT_VG4_M4Z4Z_HtoS:
23203 case AArch64::FMLA_VG4_M4Z4Z_D:
23204 case AArch64::FMLA_VG4_M4Z4Z_H:
23205 case AArch64::FMLA_VG4_M4Z4Z_S:
23206 case AArch64::FMLS_VG4_M4Z4Z_D:
23207 case AArch64::FMLS_VG4_M4Z4Z_H:
23208 case AArch64::FMLS_VG4_M4Z4Z_S:
23209 case AArch64::SDOT_VG4_M4Z4Z_BtoS:
23210 case AArch64::SDOT_VG4_M4Z4Z_HtoD:
23211 case AArch64::SDOT_VG4_M4Z4Z_HtoS:
23212 case AArch64::SUB_VG4_M4Z4Z_D:
23213 case AArch64::SUB_VG4_M4Z4Z_S:
23214 case AArch64::UDOT_VG4_M4Z4Z_BtoS:
23215 case AArch64::UDOT_VG4_M4Z4Z_HtoD:
23216 case AArch64::UDOT_VG4_M4Z4Z_HtoS:
23217 case AArch64::USDOT_VG4_M4Z4Z_BToS: {
23218 // op: Zm
23219 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 5, Fixups, STI);
23220 op &= UINT64_C(7);
23221 op <<= 18;
23222 Value |= op;
23223 // op: Zn
23224 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
23225 op &= UINT64_C(7);
23226 op <<= 7;
23227 Value |= op;
23228 // op: Rv
23229 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23230 op &= UINT64_C(3);
23231 op <<= 13;
23232 Value |= op;
23233 // op: imm3
23234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23235 op &= UINT64_C(7);
23236 Value |= op;
23237 break;
23238 }
23239 case AArch64::ADD_VG2_2ZZ_B:
23240 case AArch64::ADD_VG2_2ZZ_D:
23241 case AArch64::ADD_VG2_2ZZ_H:
23242 case AArch64::ADD_VG2_2ZZ_S:
23243 case AArch64::BFMAXNM_VG2_2ZZ_H:
23244 case AArch64::BFMAX_VG2_2ZZ_H:
23245 case AArch64::BFMINNM_VG2_2ZZ_H:
23246 case AArch64::BFMIN_VG2_2ZZ_H:
23247 case AArch64::BFSCALE_2ZZ:
23248 case AArch64::FMAXNM_VG2_2ZZ_D:
23249 case AArch64::FMAXNM_VG2_2ZZ_H:
23250 case AArch64::FMAXNM_VG2_2ZZ_S:
23251 case AArch64::FMAX_VG2_2ZZ_D:
23252 case AArch64::FMAX_VG2_2ZZ_H:
23253 case AArch64::FMAX_VG2_2ZZ_S:
23254 case AArch64::FMINNM_VG2_2ZZ_D:
23255 case AArch64::FMINNM_VG2_2ZZ_H:
23256 case AArch64::FMINNM_VG2_2ZZ_S:
23257 case AArch64::FMIN_VG2_2ZZ_D:
23258 case AArch64::FMIN_VG2_2ZZ_H:
23259 case AArch64::FMIN_VG2_2ZZ_S:
23260 case AArch64::FSCALE_2ZZ_D:
23261 case AArch64::FSCALE_2ZZ_H:
23262 case AArch64::FSCALE_2ZZ_S:
23263 case AArch64::SMAX_VG2_2ZZ_B:
23264 case AArch64::SMAX_VG2_2ZZ_D:
23265 case AArch64::SMAX_VG2_2ZZ_H:
23266 case AArch64::SMAX_VG2_2ZZ_S:
23267 case AArch64::SMIN_VG2_2ZZ_B:
23268 case AArch64::SMIN_VG2_2ZZ_D:
23269 case AArch64::SMIN_VG2_2ZZ_H:
23270 case AArch64::SMIN_VG2_2ZZ_S:
23271 case AArch64::SQDMULH_VG2_2ZZ_B:
23272 case AArch64::SQDMULH_VG2_2ZZ_D:
23273 case AArch64::SQDMULH_VG2_2ZZ_H:
23274 case AArch64::SQDMULH_VG2_2ZZ_S:
23275 case AArch64::SRSHL_VG2_2ZZ_B:
23276 case AArch64::SRSHL_VG2_2ZZ_D:
23277 case AArch64::SRSHL_VG2_2ZZ_H:
23278 case AArch64::SRSHL_VG2_2ZZ_S:
23279 case AArch64::UMAX_VG2_2ZZ_B:
23280 case AArch64::UMAX_VG2_2ZZ_D:
23281 case AArch64::UMAX_VG2_2ZZ_H:
23282 case AArch64::UMAX_VG2_2ZZ_S:
23283 case AArch64::UMIN_VG2_2ZZ_B:
23284 case AArch64::UMIN_VG2_2ZZ_D:
23285 case AArch64::UMIN_VG2_2ZZ_H:
23286 case AArch64::UMIN_VG2_2ZZ_S:
23287 case AArch64::URSHL_VG2_2ZZ_B:
23288 case AArch64::URSHL_VG2_2ZZ_D:
23289 case AArch64::URSHL_VG2_2ZZ_H:
23290 case AArch64::URSHL_VG2_2ZZ_S: {
23291 // op: Zm
23292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23293 op &= UINT64_C(15);
23294 op <<= 16;
23295 Value |= op;
23296 // op: Zdn
23297 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
23298 op &= UINT64_C(15);
23299 op <<= 1;
23300 Value |= op;
23301 break;
23302 }
23303 case AArch64::ADD_VG4_4ZZ_B:
23304 case AArch64::ADD_VG4_4ZZ_D:
23305 case AArch64::ADD_VG4_4ZZ_H:
23306 case AArch64::ADD_VG4_4ZZ_S:
23307 case AArch64::BFMAXNM_VG4_4ZZ_H:
23308 case AArch64::BFMAX_VG4_4ZZ_H:
23309 case AArch64::BFMINNM_VG4_4ZZ_H:
23310 case AArch64::BFMIN_VG4_4ZZ_H:
23311 case AArch64::BFSCALE_4ZZ:
23312 case AArch64::FMAXNM_VG4_4ZZ_D:
23313 case AArch64::FMAXNM_VG4_4ZZ_H:
23314 case AArch64::FMAXNM_VG4_4ZZ_S:
23315 case AArch64::FMAX_VG4_4ZZ_D:
23316 case AArch64::FMAX_VG4_4ZZ_H:
23317 case AArch64::FMAX_VG4_4ZZ_S:
23318 case AArch64::FMINNM_VG4_4ZZ_D:
23319 case AArch64::FMINNM_VG4_4ZZ_H:
23320 case AArch64::FMINNM_VG4_4ZZ_S:
23321 case AArch64::FMIN_VG4_4ZZ_D:
23322 case AArch64::FMIN_VG4_4ZZ_H:
23323 case AArch64::FMIN_VG4_4ZZ_S:
23324 case AArch64::FSCALE_4ZZ_D:
23325 case AArch64::FSCALE_4ZZ_H:
23326 case AArch64::FSCALE_4ZZ_S:
23327 case AArch64::SMAX_VG4_4ZZ_B:
23328 case AArch64::SMAX_VG4_4ZZ_D:
23329 case AArch64::SMAX_VG4_4ZZ_H:
23330 case AArch64::SMAX_VG4_4ZZ_S:
23331 case AArch64::SMIN_VG4_4ZZ_B:
23332 case AArch64::SMIN_VG4_4ZZ_D:
23333 case AArch64::SMIN_VG4_4ZZ_H:
23334 case AArch64::SMIN_VG4_4ZZ_S:
23335 case AArch64::SQDMULH_VG4_4ZZ_B:
23336 case AArch64::SQDMULH_VG4_4ZZ_D:
23337 case AArch64::SQDMULH_VG4_4ZZ_H:
23338 case AArch64::SQDMULH_VG4_4ZZ_S:
23339 case AArch64::SRSHL_VG4_4ZZ_B:
23340 case AArch64::SRSHL_VG4_4ZZ_D:
23341 case AArch64::SRSHL_VG4_4ZZ_H:
23342 case AArch64::SRSHL_VG4_4ZZ_S:
23343 case AArch64::UMAX_VG4_4ZZ_B:
23344 case AArch64::UMAX_VG4_4ZZ_D:
23345 case AArch64::UMAX_VG4_4ZZ_H:
23346 case AArch64::UMAX_VG4_4ZZ_S:
23347 case AArch64::UMIN_VG4_4ZZ_B:
23348 case AArch64::UMIN_VG4_4ZZ_D:
23349 case AArch64::UMIN_VG4_4ZZ_H:
23350 case AArch64::UMIN_VG4_4ZZ_S:
23351 case AArch64::URSHL_VG4_4ZZ_B:
23352 case AArch64::URSHL_VG4_4ZZ_D:
23353 case AArch64::URSHL_VG4_4ZZ_H:
23354 case AArch64::URSHL_VG4_4ZZ_S: {
23355 // op: Zm
23356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23357 op &= UINT64_C(15);
23358 op <<= 16;
23359 Value |= op;
23360 // op: Zdn
23361 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
23362 op &= UINT64_C(7);
23363 op <<= 2;
23364 Value |= op;
23365 break;
23366 }
23367 case AArch64::PMULL_2ZZZ_Q: {
23368 // op: Zm
23369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23370 op &= UINT64_C(31);
23371 op <<= 16;
23372 Value |= op;
23373 // op: Zn
23374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23375 op &= UINT64_C(31);
23376 op <<= 5;
23377 Value |= op;
23378 // op: Zd
23379 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
23380 op &= UINT64_C(15);
23381 op <<= 1;
23382 Value |= op;
23383 break;
23384 }
23385 case AArch64::AESDMIC_2ZZI_B:
23386 case AArch64::AESD_2ZZI_B:
23387 case AArch64::AESEMC_2ZZI_B:
23388 case AArch64::AESE_2ZZI_B: {
23389 // op: Zm
23390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23391 op &= UINT64_C(31);
23392 op <<= 5;
23393 Value |= op;
23394 // op: Zdn
23395 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
23396 op &= UINT64_C(15);
23397 op <<= 1;
23398 Value |= op;
23399 // op: imm2
23400 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23401 op &= UINT64_C(3);
23402 op <<= 19;
23403 Value |= op;
23404 break;
23405 }
23406 case AArch64::AESDMIC_4ZZI_B:
23407 case AArch64::AESD_4ZZI_B:
23408 case AArch64::AESEMC_4ZZI_B:
23409 case AArch64::AESE_4ZZI_B: {
23410 // op: Zm
23411 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23412 op &= UINT64_C(31);
23413 op <<= 5;
23414 Value |= op;
23415 // op: Zdn
23416 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
23417 op &= UINT64_C(7);
23418 op <<= 2;
23419 Value |= op;
23420 // op: imm2
23421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23422 op &= UINT64_C(3);
23423 op <<= 19;
23424 Value |= op;
23425 break;
23426 }
23427 case AArch64::BFCLAMP_VG2_2ZZZ_H:
23428 case AArch64::FCLAMP_VG2_2Z2Z_D:
23429 case AArch64::FCLAMP_VG2_2Z2Z_H:
23430 case AArch64::FCLAMP_VG2_2Z2Z_S:
23431 case AArch64::SCLAMP_VG2_2Z2Z_B:
23432 case AArch64::SCLAMP_VG2_2Z2Z_D:
23433 case AArch64::SCLAMP_VG2_2Z2Z_H:
23434 case AArch64::SCLAMP_VG2_2Z2Z_S:
23435 case AArch64::UCLAMP_VG2_2Z2Z_B:
23436 case AArch64::UCLAMP_VG2_2Z2Z_D:
23437 case AArch64::UCLAMP_VG2_2Z2Z_H:
23438 case AArch64::UCLAMP_VG2_2Z2Z_S: {
23439 // op: Zm
23440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23441 op &= UINT64_C(31);
23442 op <<= 16;
23443 Value |= op;
23444 // op: Zn
23445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23446 op &= UINT64_C(31);
23447 op <<= 5;
23448 Value |= op;
23449 // op: Zd
23450 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
23451 op &= UINT64_C(15);
23452 op <<= 1;
23453 Value |= op;
23454 break;
23455 }
23456 case AArch64::BFCLAMP_VG4_4ZZZ_H:
23457 case AArch64::FCLAMP_VG4_4Z4Z_D:
23458 case AArch64::FCLAMP_VG4_4Z4Z_H:
23459 case AArch64::FCLAMP_VG4_4Z4Z_S:
23460 case AArch64::SCLAMP_VG4_4Z4Z_B:
23461 case AArch64::SCLAMP_VG4_4Z4Z_D:
23462 case AArch64::SCLAMP_VG4_4Z4Z_H:
23463 case AArch64::SCLAMP_VG4_4Z4Z_S:
23464 case AArch64::UCLAMP_VG4_4Z4Z_B:
23465 case AArch64::UCLAMP_VG4_4Z4Z_D:
23466 case AArch64::UCLAMP_VG4_4Z4Z_H:
23467 case AArch64::UCLAMP_VG4_4Z4Z_S: {
23468 // op: Zm
23469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23470 op &= UINT64_C(31);
23471 op <<= 16;
23472 Value |= op;
23473 // op: Zn
23474 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23475 op &= UINT64_C(31);
23476 op <<= 5;
23477 Value |= op;
23478 // op: Zd
23479 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
23480 op &= UINT64_C(7);
23481 op <<= 2;
23482 Value |= op;
23483 break;
23484 }
23485 case AArch64::BFCLAMP_ZZZ:
23486 case AArch64::FCLAMP_ZZZ_D:
23487 case AArch64::FCLAMP_ZZZ_H:
23488 case AArch64::FCLAMP_ZZZ_S:
23489 case AArch64::SCLAMP_ZZZ_B:
23490 case AArch64::SCLAMP_ZZZ_D:
23491 case AArch64::SCLAMP_ZZZ_H:
23492 case AArch64::SCLAMP_ZZZ_S:
23493 case AArch64::UCLAMP_ZZZ_B:
23494 case AArch64::UCLAMP_ZZZ_D:
23495 case AArch64::UCLAMP_ZZZ_H:
23496 case AArch64::UCLAMP_ZZZ_S: {
23497 // op: Zm
23498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23499 op &= UINT64_C(31);
23500 op <<= 16;
23501 Value |= op;
23502 // op: Zn
23503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23504 op &= UINT64_C(31);
23505 op <<= 5;
23506 Value |= op;
23507 // op: Zd
23508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23509 op &= UINT64_C(31);
23510 Value |= op;
23511 break;
23512 }
23513 case AArch64::PMLAL_2ZZZ_Q: {
23514 // op: Zm
23515 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23516 op &= UINT64_C(31);
23517 op <<= 16;
23518 Value |= op;
23519 // op: Zn
23520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23521 op &= UINT64_C(31);
23522 op <<= 5;
23523 Value |= op;
23524 // op: Zda
23525 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
23526 op &= UINT64_C(15);
23527 op <<= 1;
23528 Value |= op;
23529 break;
23530 }
23531 case AArch64::FVDOTB_VG4_M2ZZI_BtoS:
23532 case AArch64::FVDOTT_VG4_M2ZZI_BtoS: {
23533 // op: Zm
23534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23535 op &= UINT64_C(15);
23536 op <<= 16;
23537 Value |= op;
23538 // op: Rv
23539 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23540 op &= UINT64_C(3);
23541 op <<= 13;
23542 Value |= op;
23543 // op: Zn
23544 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
23545 op &= UINT64_C(15);
23546 op <<= 6;
23547 Value |= op;
23548 // op: imm3
23549 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23550 op &= UINT64_C(7);
23551 Value |= op;
23552 // op: i
23553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23554 Value |= (op & UINT64_C(2)) << 9;
23555 Value |= (op & UINT64_C(1)) << 3;
23556 break;
23557 }
23558 case AArch64::BFMLA_VG2_M2ZZI:
23559 case AArch64::BFMLS_VG2_M2ZZI:
23560 case AArch64::FDOT_VG2_M2ZZI_BtoH:
23561 case AArch64::FMLA_VG2_M2ZZI_H:
23562 case AArch64::FMLS_VG2_M2ZZI_H:
23563 case AArch64::FVDOT_VG2_M2ZZI_BtoH: {
23564 // op: Zm
23565 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23566 op &= UINT64_C(15);
23567 op <<= 16;
23568 Value |= op;
23569 // op: Rv
23570 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23571 op &= UINT64_C(3);
23572 op <<= 13;
23573 Value |= op;
23574 // op: Zn
23575 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
23576 op &= UINT64_C(15);
23577 op <<= 6;
23578 Value |= op;
23579 // op: imm3
23580 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23581 op &= UINT64_C(7);
23582 Value |= op;
23583 // op: i
23584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23585 Value |= (op & UINT64_C(6)) << 9;
23586 Value |= (op & UINT64_C(1)) << 3;
23587 break;
23588 }
23589 case AArch64::BFDOT_VG2_M2ZZI_HtoS:
23590 case AArch64::BFVDOT_VG2_M2ZZI_HtoS:
23591 case AArch64::FDOT_VG2_M2ZZI_BtoS:
23592 case AArch64::FDOT_VG2_M2ZZI_HtoS:
23593 case AArch64::FMLA_VG2_M2ZZI_S:
23594 case AArch64::FMLS_VG2_M2ZZI_S:
23595 case AArch64::FVDOT_VG2_M2ZZI_HtoS:
23596 case AArch64::SDOT_VG2_M2ZZI_BToS:
23597 case AArch64::SDOT_VG2_M2ZZI_HToS:
23598 case AArch64::SUDOT_VG2_M2ZZI_BToS:
23599 case AArch64::SVDOT_VG2_M2ZZI_HtoS:
23600 case AArch64::UDOT_VG2_M2ZZI_BToS:
23601 case AArch64::UDOT_VG2_M2ZZI_HToS:
23602 case AArch64::USDOT_VG2_M2ZZI_BToS:
23603 case AArch64::UVDOT_VG2_M2ZZI_HtoS: {
23604 // op: Zm
23605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23606 op &= UINT64_C(15);
23607 op <<= 16;
23608 Value |= op;
23609 // op: Rv
23610 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23611 op &= UINT64_C(3);
23612 op <<= 13;
23613 Value |= op;
23614 // op: Zn
23615 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
23616 op &= UINT64_C(15);
23617 op <<= 6;
23618 Value |= op;
23619 // op: imm3
23620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23621 op &= UINT64_C(7);
23622 Value |= op;
23623 // op: i
23624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23625 op &= UINT64_C(3);
23626 op <<= 10;
23627 Value |= op;
23628 break;
23629 }
23630 case AArch64::BFMLA_VG4_M4ZZI:
23631 case AArch64::BFMLS_VG4_M4ZZI:
23632 case AArch64::FDOT_VG4_M4ZZI_BtoH:
23633 case AArch64::FMLA_VG4_M4ZZI_H:
23634 case AArch64::FMLS_VG4_M4ZZI_H: {
23635 // op: Zm
23636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23637 op &= UINT64_C(15);
23638 op <<= 16;
23639 Value |= op;
23640 // op: Rv
23641 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23642 op &= UINT64_C(3);
23643 op <<= 13;
23644 Value |= op;
23645 // op: Zn
23646 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
23647 op &= UINT64_C(7);
23648 op <<= 7;
23649 Value |= op;
23650 // op: imm3
23651 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23652 op &= UINT64_C(7);
23653 Value |= op;
23654 // op: i
23655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23656 Value |= (op & UINT64_C(6)) << 9;
23657 Value |= (op & UINT64_C(1)) << 3;
23658 break;
23659 }
23660 case AArch64::BFDOT_VG4_M4ZZI_HtoS:
23661 case AArch64::FDOT_VG4_M4ZZI_BtoS:
23662 case AArch64::FDOT_VG4_M4ZZI_HtoS:
23663 case AArch64::FMLA_VG4_M4ZZI_S:
23664 case AArch64::FMLS_VG4_M4ZZI_S:
23665 case AArch64::SDOT_VG4_M4ZZI_BToS:
23666 case AArch64::SDOT_VG4_M4ZZI_HToS:
23667 case AArch64::SUDOT_VG4_M4ZZI_BToS:
23668 case AArch64::SUVDOT_VG4_M4ZZI_BToS:
23669 case AArch64::SVDOT_VG4_M4ZZI_BtoS:
23670 case AArch64::UDOT_VG4_M4ZZI_BtoS:
23671 case AArch64::UDOT_VG4_M4ZZI_HToS:
23672 case AArch64::USDOT_VG4_M4ZZI_BToS:
23673 case AArch64::USVDOT_VG4_M4ZZI_BToS:
23674 case AArch64::UVDOT_VG4_M4ZZI_BtoS: {
23675 // op: Zm
23676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23677 op &= UINT64_C(15);
23678 op <<= 16;
23679 Value |= op;
23680 // op: Rv
23681 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23682 op &= UINT64_C(3);
23683 op <<= 13;
23684 Value |= op;
23685 // op: Zn
23686 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
23687 op &= UINT64_C(7);
23688 op <<= 7;
23689 Value |= op;
23690 // op: imm3
23691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23692 op &= UINT64_C(7);
23693 Value |= op;
23694 // op: i
23695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23696 op &= UINT64_C(3);
23697 op <<= 10;
23698 Value |= op;
23699 break;
23700 }
23701 case AArch64::FMLALL_VG2_M2ZZ_BtoS:
23702 case AArch64::FMLALL_VG4_M4ZZ_BtoS:
23703 case AArch64::SMLALL_VG2_M2ZZ_BtoS:
23704 case AArch64::SMLALL_VG2_M2ZZ_HtoD:
23705 case AArch64::SMLALL_VG4_M4ZZ_BtoS:
23706 case AArch64::SMLALL_VG4_M4ZZ_HtoD:
23707 case AArch64::SMLSLL_VG2_M2ZZ_BtoS:
23708 case AArch64::SMLSLL_VG2_M2ZZ_HtoD:
23709 case AArch64::SMLSLL_VG4_M4ZZ_BtoS:
23710 case AArch64::SMLSLL_VG4_M4ZZ_HtoD:
23711 case AArch64::SUMLALL_VG2_M2ZZ_BtoS:
23712 case AArch64::SUMLALL_VG4_M4ZZ_BtoS:
23713 case AArch64::UMLALL_VG2_M2ZZ_BtoS:
23714 case AArch64::UMLALL_VG2_M2ZZ_HtoD:
23715 case AArch64::UMLALL_VG4_M4ZZ_BtoS:
23716 case AArch64::UMLALL_VG4_M4ZZ_HtoD:
23717 case AArch64::UMLSLL_VG2_M2ZZ_BtoS:
23718 case AArch64::UMLSLL_VG2_M2ZZ_HtoD:
23719 case AArch64::UMLSLL_VG4_M4ZZ_BtoS:
23720 case AArch64::UMLSLL_VG4_M4ZZ_HtoD:
23721 case AArch64::USMLALL_VG2_M2ZZ_BtoS:
23722 case AArch64::USMLALL_VG4_M4ZZ_BtoS: {
23723 // op: Zm
23724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23725 op &= UINT64_C(15);
23726 op <<= 16;
23727 Value |= op;
23728 // op: Rv
23729 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23730 op &= UINT64_C(3);
23731 op <<= 13;
23732 Value |= op;
23733 // op: Zn
23734 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
23735 op &= UINT64_C(31);
23736 op <<= 5;
23737 Value |= op;
23738 // op: imm
23739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23740 op &= UINT64_C(1);
23741 Value |= op;
23742 break;
23743 }
23744 case AArch64::FMLALL_MZZ_BtoS:
23745 case AArch64::SMLALL_MZZ_BtoS:
23746 case AArch64::SMLALL_MZZ_HtoD:
23747 case AArch64::SMLSLL_MZZ_BtoS:
23748 case AArch64::SMLSLL_MZZ_HtoD:
23749 case AArch64::UMLALL_MZZ_BtoS:
23750 case AArch64::UMLALL_MZZ_HtoD:
23751 case AArch64::UMLSLL_MZZ_BtoS:
23752 case AArch64::UMLSLL_MZZ_HtoD:
23753 case AArch64::USMLALL_MZZ_BtoS: {
23754 // op: Zm
23755 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23756 op &= UINT64_C(15);
23757 op <<= 16;
23758 Value |= op;
23759 // op: Rv
23760 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23761 op &= UINT64_C(3);
23762 op <<= 13;
23763 Value |= op;
23764 // op: Zn
23765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
23766 op &= UINT64_C(31);
23767 op <<= 5;
23768 Value |= op;
23769 // op: imm
23770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23771 op &= UINT64_C(3);
23772 Value |= op;
23773 break;
23774 }
23775 case AArch64::FMLALL_VG2_M2ZZI_BtoS:
23776 case AArch64::SMLALL_VG2_M2ZZI_BtoS:
23777 case AArch64::SMLSLL_VG2_M2ZZI_BtoS:
23778 case AArch64::SUMLALL_VG2_M2ZZI_BtoS:
23779 case AArch64::UMLALL_VG2_M2ZZI_BtoS:
23780 case AArch64::UMLSLL_VG2_M2ZZI_BtoS:
23781 case AArch64::USMLALL_VG2_M2ZZI_BtoS: {
23782 // op: Zm
23783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23784 op &= UINT64_C(15);
23785 op <<= 16;
23786 Value |= op;
23787 // op: Rv
23788 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23789 op &= UINT64_C(3);
23790 op <<= 13;
23791 Value |= op;
23792 // op: i
23793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23794 Value |= (op & UINT64_C(12)) << 8;
23795 Value |= (op & UINT64_C(3)) << 1;
23796 // op: imm
23797 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23798 op &= UINT64_C(1);
23799 Value |= op;
23800 // op: Zn
23801 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
23802 op &= UINT64_C(15);
23803 op <<= 6;
23804 Value |= op;
23805 break;
23806 }
23807 case AArch64::FMLALL_VG4_M4ZZI_BtoS:
23808 case AArch64::SMLALL_VG4_M4ZZI_BtoS:
23809 case AArch64::SMLSLL_VG4_M4ZZI_BtoS:
23810 case AArch64::SUMLALL_VG4_M4ZZI_BtoS:
23811 case AArch64::UMLALL_VG4_M4ZZI_BtoS:
23812 case AArch64::UMLSLL_VG4_M4ZZI_BtoS:
23813 case AArch64::USMLALL_VG4_M4ZZI_BtoS: {
23814 // op: Zm
23815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23816 op &= UINT64_C(15);
23817 op <<= 16;
23818 Value |= op;
23819 // op: Rv
23820 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23821 op &= UINT64_C(3);
23822 op <<= 13;
23823 Value |= op;
23824 // op: i
23825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23826 Value |= (op & UINT64_C(12)) << 8;
23827 Value |= (op & UINT64_C(3)) << 1;
23828 // op: imm
23829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23830 op &= UINT64_C(1);
23831 Value |= op;
23832 // op: Zn
23833 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
23834 op &= UINT64_C(7);
23835 op <<= 7;
23836 Value |= op;
23837 break;
23838 }
23839 case AArch64::FMLAL_VG2_M2ZZI_BtoH: {
23840 // op: Zm
23841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23842 op &= UINT64_C(15);
23843 op <<= 16;
23844 Value |= op;
23845 // op: Rv
23846 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23847 op &= UINT64_C(3);
23848 op <<= 13;
23849 Value |= op;
23850 // op: i
23851 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23852 Value |= (op & UINT64_C(12)) << 8;
23853 Value |= (op & UINT64_C(3)) << 2;
23854 // op: imm2
23855 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23856 op &= UINT64_C(3);
23857 Value |= op;
23858 // op: Zn
23859 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
23860 op &= UINT64_C(15);
23861 op <<= 6;
23862 Value |= op;
23863 break;
23864 }
23865 case AArch64::FMLAL_VG4_M4ZZI_BtoH: {
23866 // op: Zm
23867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23868 op &= UINT64_C(15);
23869 op <<= 16;
23870 Value |= op;
23871 // op: Rv
23872 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23873 op &= UINT64_C(3);
23874 op <<= 13;
23875 Value |= op;
23876 // op: i
23877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23878 Value |= (op & UINT64_C(12)) << 8;
23879 Value |= (op & UINT64_C(3)) << 2;
23880 // op: imm2
23881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23882 op &= UINT64_C(3);
23883 Value |= op;
23884 // op: Zn
23885 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
23886 op &= UINT64_C(7);
23887 op <<= 7;
23888 Value |= op;
23889 break;
23890 }
23891 case AArch64::SMLALL_MZZI_HtoD:
23892 case AArch64::SMLSLL_MZZI_HtoD:
23893 case AArch64::UMLALL_MZZI_HtoD:
23894 case AArch64::UMLSLL_MZZI_HtoD: {
23895 // op: Zm
23896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23897 op &= UINT64_C(15);
23898 op <<= 16;
23899 Value |= op;
23900 // op: Rv
23901 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23902 op &= UINT64_C(3);
23903 op <<= 13;
23904 Value |= op;
23905 // op: i
23906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23907 Value |= (op & UINT64_C(4)) << 13;
23908 Value |= (op & UINT64_C(3)) << 10;
23909 // op: Zn
23910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
23911 op &= UINT64_C(31);
23912 op <<= 5;
23913 Value |= op;
23914 // op: imm2
23915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23916 op &= UINT64_C(3);
23917 Value |= op;
23918 break;
23919 }
23920 case AArch64::SMLALL_VG2_M2ZZI_HtoD:
23921 case AArch64::SMLSLL_VG2_M2ZZI_HtoD:
23922 case AArch64::UMLALL_VG2_M2ZZI_HtoD:
23923 case AArch64::UMLSLL_VG2_M2ZZI_HtoD: {
23924 // op: Zm
23925 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23926 op &= UINT64_C(15);
23927 op <<= 16;
23928 Value |= op;
23929 // op: Rv
23930 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23931 op &= UINT64_C(3);
23932 op <<= 13;
23933 Value |= op;
23934 // op: i
23935 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23936 Value |= (op & UINT64_C(4)) << 8;
23937 Value |= (op & UINT64_C(3)) << 1;
23938 // op: imm
23939 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23940 op &= UINT64_C(1);
23941 Value |= op;
23942 // op: Zn
23943 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
23944 op &= UINT64_C(15);
23945 op <<= 6;
23946 Value |= op;
23947 break;
23948 }
23949 case AArch64::SMLALL_VG4_M4ZZI_HtoD:
23950 case AArch64::SMLSLL_VG4_M4ZZI_HtoD:
23951 case AArch64::UMLALL_VG4_M4ZZI_HtoD:
23952 case AArch64::UMLSLL_VG4_M4ZZI_HtoD: {
23953 // op: Zm
23954 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23955 op &= UINT64_C(15);
23956 op <<= 16;
23957 Value |= op;
23958 // op: Rv
23959 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23960 op &= UINT64_C(3);
23961 op <<= 13;
23962 Value |= op;
23963 // op: i
23964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23965 Value |= (op & UINT64_C(4)) << 8;
23966 Value |= (op & UINT64_C(3)) << 1;
23967 // op: imm
23968 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23969 op &= UINT64_C(1);
23970 Value |= op;
23971 // op: Zn
23972 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
23973 op &= UINT64_C(7);
23974 op <<= 7;
23975 Value |= op;
23976 break;
23977 }
23978 case AArch64::FMLAL_MZZI_BtoH: {
23979 // op: Zm
23980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
23981 op &= UINT64_C(15);
23982 op <<= 16;
23983 Value |= op;
23984 // op: Rv
23985 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
23986 op &= UINT64_C(3);
23987 op <<= 13;
23988 Value |= op;
23989 // op: i
23990 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
23991 Value |= (op & UINT64_C(8)) << 12;
23992 Value |= (op & UINT64_C(6)) << 9;
23993 Value |= (op & UINT64_C(1)) << 3;
23994 // op: Zn
23995 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
23996 op &= UINT64_C(31);
23997 op <<= 5;
23998 Value |= op;
23999 // op: imm3
24000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24001 op &= UINT64_C(7);
24002 Value |= op;
24003 break;
24004 }
24005 case AArch64::FMLALL_MZZI_BtoS:
24006 case AArch64::SMLALL_MZZI_BtoS:
24007 case AArch64::SMLSLL_MZZI_BtoS:
24008 case AArch64::SUMLALL_MZZI_BtoS:
24009 case AArch64::UMLALL_MZZI_BtoS:
24010 case AArch64::UMLSLL_MZZI_BtoS:
24011 case AArch64::USMLALL_MZZI_BtoS: {
24012 // op: Zm
24013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24014 op &= UINT64_C(15);
24015 op <<= 16;
24016 Value |= op;
24017 // op: Rv
24018 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
24019 op &= UINT64_C(3);
24020 op <<= 13;
24021 Value |= op;
24022 // op: i
24023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
24024 Value |= (op & UINT64_C(8)) << 12;
24025 Value |= (op & UINT64_C(7)) << 10;
24026 // op: Zn
24027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
24028 op &= UINT64_C(31);
24029 op <<= 5;
24030 Value |= op;
24031 // op: imm2
24032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24033 op &= UINT64_C(3);
24034 Value |= op;
24035 break;
24036 }
24037 case AArch64::FMLA_VG2_M2ZZI_D:
24038 case AArch64::FMLS_VG2_M2ZZI_D:
24039 case AArch64::SDOT_VG2_M2ZZI_HtoD:
24040 case AArch64::UDOT_VG2_M2ZZI_HtoD: {
24041 // op: Zm
24042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24043 op &= UINT64_C(15);
24044 op <<= 16;
24045 Value |= op;
24046 // op: Rv
24047 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
24048 op &= UINT64_C(3);
24049 op <<= 13;
24050 Value |= op;
24051 // op: i1
24052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
24053 op &= UINT64_C(1);
24054 op <<= 10;
24055 Value |= op;
24056 // op: Zn
24057 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
24058 op &= UINT64_C(15);
24059 op <<= 6;
24060 Value |= op;
24061 // op: imm3
24062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24063 op &= UINT64_C(7);
24064 Value |= op;
24065 break;
24066 }
24067 case AArch64::FMLA_VG4_M4ZZI_D:
24068 case AArch64::FMLS_VG4_M4ZZI_D:
24069 case AArch64::SDOT_VG4_M4ZZI_HtoD:
24070 case AArch64::SVDOT_VG4_M4ZZI_HtoD:
24071 case AArch64::UDOT_VG4_M4ZZI_HtoD:
24072 case AArch64::UVDOT_VG4_M4ZZI_HtoD: {
24073 // op: Zm
24074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24075 op &= UINT64_C(15);
24076 op <<= 16;
24077 Value |= op;
24078 // op: Rv
24079 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
24080 op &= UINT64_C(3);
24081 op <<= 13;
24082 Value |= op;
24083 // op: i1
24084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
24085 op &= UINT64_C(1);
24086 op <<= 10;
24087 Value |= op;
24088 // op: Zn
24089 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
24090 op &= UINT64_C(7);
24091 op <<= 7;
24092 Value |= op;
24093 // op: imm3
24094 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24095 op &= UINT64_C(7);
24096 Value |= op;
24097 break;
24098 }
24099 case AArch64::BFMLAL_MZZI_HtoS:
24100 case AArch64::BFMLSL_MZZI_HtoS:
24101 case AArch64::FMLAL_MZZI_HtoS:
24102 case AArch64::FMLSL_MZZI_HtoS:
24103 case AArch64::SMLAL_MZZI_HtoS:
24104 case AArch64::SMLSL_MZZI_HtoS:
24105 case AArch64::UMLAL_MZZI_HtoS:
24106 case AArch64::UMLSL_MZZI_HtoS: {
24107 // op: Zm
24108 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24109 op &= UINT64_C(15);
24110 op <<= 16;
24111 Value |= op;
24112 // op: Rv
24113 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
24114 op &= UINT64_C(3);
24115 op <<= 13;
24116 Value |= op;
24117 // op: i3
24118 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
24119 Value |= (op & UINT64_C(4)) << 13;
24120 Value |= (op & UINT64_C(3)) << 10;
24121 // op: Zn
24122 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
24123 op &= UINT64_C(31);
24124 op <<= 5;
24125 Value |= op;
24126 // op: imm
24127 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24128 op &= UINT64_C(7);
24129 Value |= op;
24130 break;
24131 }
24132 case AArch64::BFMLAL_VG2_M2ZZI_HtoS:
24133 case AArch64::BFMLSL_VG2_M2ZZI_HtoS:
24134 case AArch64::FMLAL_VG2_M2ZZI_HtoS:
24135 case AArch64::FMLSL_VG2_M2ZZI_HtoS:
24136 case AArch64::SMLAL_VG2_M2ZZI_S:
24137 case AArch64::SMLSL_VG2_M2ZZI_S:
24138 case AArch64::UMLAL_VG2_M2ZZI_S:
24139 case AArch64::UMLSL_VG2_M2ZZI_S: {
24140 // op: Zm
24141 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24142 op &= UINT64_C(15);
24143 op <<= 16;
24144 Value |= op;
24145 // op: Rv
24146 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
24147 op &= UINT64_C(3);
24148 op <<= 13;
24149 Value |= op;
24150 // op: i3
24151 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
24152 Value |= (op & UINT64_C(6)) << 9;
24153 Value |= (op & UINT64_C(1)) << 2;
24154 // op: Zn
24155 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI);
24156 op &= UINT64_C(15);
24157 op <<= 6;
24158 Value |= op;
24159 // op: imm
24160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24161 op &= UINT64_C(3);
24162 Value |= op;
24163 break;
24164 }
24165 case AArch64::BFMLAL_VG4_M4ZZI_HtoS:
24166 case AArch64::BFMLSL_VG4_M4ZZI_HtoS:
24167 case AArch64::FMLAL_VG4_M4ZZI_HtoS:
24168 case AArch64::FMLSL_VG4_M4ZZI_HtoS:
24169 case AArch64::SMLAL_VG4_M4ZZI_HtoS:
24170 case AArch64::SMLSL_VG4_M4ZZI_HtoS:
24171 case AArch64::UMLAL_VG4_M4ZZI_HtoS:
24172 case AArch64::UMLSL_VG4_M4ZZI_HtoS: {
24173 // op: Zm
24174 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24175 op &= UINT64_C(15);
24176 op <<= 16;
24177 Value |= op;
24178 // op: Rv
24179 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
24180 op &= UINT64_C(3);
24181 op <<= 13;
24182 Value |= op;
24183 // op: i3
24184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
24185 Value |= (op & UINT64_C(6)) << 9;
24186 Value |= (op & UINT64_C(1)) << 2;
24187 // op: Zn
24188 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI);
24189 op &= UINT64_C(7);
24190 op <<= 7;
24191 Value |= op;
24192 // op: imm
24193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24194 op &= UINT64_C(3);
24195 Value |= op;
24196 break;
24197 }
24198 case AArch64::ADD_VG2_M2ZZ_D:
24199 case AArch64::ADD_VG2_M2ZZ_S:
24200 case AArch64::ADD_VG4_M4ZZ_D:
24201 case AArch64::ADD_VG4_M4ZZ_S:
24202 case AArch64::BFDOT_VG2_M2ZZ_HtoS:
24203 case AArch64::BFDOT_VG4_M4ZZ_HtoS:
24204 case AArch64::BFMLA_VG2_M2ZZ:
24205 case AArch64::BFMLA_VG4_M4ZZ:
24206 case AArch64::BFMLS_VG2_M2ZZ:
24207 case AArch64::BFMLS_VG4_M4ZZ:
24208 case AArch64::FDOT_VG2_M2ZZ_BtoH:
24209 case AArch64::FDOT_VG2_M2ZZ_BtoS:
24210 case AArch64::FDOT_VG2_M2ZZ_HtoS:
24211 case AArch64::FDOT_VG4_M4ZZ_BtoH:
24212 case AArch64::FDOT_VG4_M4ZZ_BtoS:
24213 case AArch64::FDOT_VG4_M4ZZ_HtoS:
24214 case AArch64::FMLA_VG2_M2ZZ_D:
24215 case AArch64::FMLA_VG2_M2ZZ_H:
24216 case AArch64::FMLA_VG2_M2ZZ_S:
24217 case AArch64::FMLA_VG4_M4ZZ_D:
24218 case AArch64::FMLA_VG4_M4ZZ_H:
24219 case AArch64::FMLA_VG4_M4ZZ_S:
24220 case AArch64::FMLS_VG2_M2ZZ_D:
24221 case AArch64::FMLS_VG2_M2ZZ_H:
24222 case AArch64::FMLS_VG2_M2ZZ_S:
24223 case AArch64::FMLS_VG4_M4ZZ_D:
24224 case AArch64::FMLS_VG4_M4ZZ_H:
24225 case AArch64::FMLS_VG4_M4ZZ_S:
24226 case AArch64::SDOT_VG2_M2ZZ_BtoS:
24227 case AArch64::SDOT_VG2_M2ZZ_HtoD:
24228 case AArch64::SDOT_VG2_M2ZZ_HtoS:
24229 case AArch64::SDOT_VG4_M4ZZ_BtoS:
24230 case AArch64::SDOT_VG4_M4ZZ_HtoD:
24231 case AArch64::SDOT_VG4_M4ZZ_HtoS:
24232 case AArch64::SUB_VG2_M2ZZ_D:
24233 case AArch64::SUB_VG2_M2ZZ_S:
24234 case AArch64::SUB_VG4_M4ZZ_D:
24235 case AArch64::SUB_VG4_M4ZZ_S:
24236 case AArch64::SUDOT_VG2_M2ZZ_BToS:
24237 case AArch64::SUDOT_VG4_M4ZZ_BToS:
24238 case AArch64::UDOT_VG2_M2ZZ_BtoS:
24239 case AArch64::UDOT_VG2_M2ZZ_HtoD:
24240 case AArch64::UDOT_VG2_M2ZZ_HtoS:
24241 case AArch64::UDOT_VG4_M4ZZ_BtoS:
24242 case AArch64::UDOT_VG4_M4ZZ_HtoD:
24243 case AArch64::UDOT_VG4_M4ZZ_HtoS:
24244 case AArch64::USDOT_VG2_M2ZZ_BToS:
24245 case AArch64::USDOT_VG4_M4ZZ_BToS: {
24246 // op: Zm
24247 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24248 op &= UINT64_C(15);
24249 op <<= 16;
24250 Value |= op;
24251 // op: Zn
24252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
24253 op &= UINT64_C(31);
24254 op <<= 5;
24255 Value |= op;
24256 // op: Rv
24257 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
24258 op &= UINT64_C(3);
24259 op <<= 13;
24260 Value |= op;
24261 // op: imm3
24262 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24263 op &= UINT64_C(7);
24264 Value |= op;
24265 break;
24266 }
24267 case AArch64::BFMOPA_MPPZZ_H:
24268 case AArch64::BFMOPS_MPPZZ_H:
24269 case AArch64::FMOPA_MPPZZ_BtoH:
24270 case AArch64::FMOPA_MPPZZ_H:
24271 case AArch64::FMOPS_MPPZZ_H: {
24272 // op: Zm
24273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24274 op &= UINT64_C(31);
24275 op <<= 16;
24276 Value |= op;
24277 // op: Pm
24278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24279 op &= UINT64_C(7);
24280 op <<= 13;
24281 Value |= op;
24282 // op: Pn
24283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24284 op &= UINT64_C(7);
24285 op <<= 10;
24286 Value |= op;
24287 // op: Zn
24288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
24289 op &= UINT64_C(31);
24290 op <<= 5;
24291 Value |= op;
24292 // op: ZAda
24293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24294 op &= UINT64_C(1);
24295 Value |= op;
24296 break;
24297 }
24298 case AArch64::BFMOPA_MPPZZ:
24299 case AArch64::BFMOPS_MPPZZ:
24300 case AArch64::BMOPA_MPPZZ_S:
24301 case AArch64::BMOPS_MPPZZ_S:
24302 case AArch64::FMOPAL_MPPZZ:
24303 case AArch64::FMOPA_MPPZZ_BtoS:
24304 case AArch64::FMOPA_MPPZZ_S:
24305 case AArch64::FMOPSL_MPPZZ:
24306 case AArch64::FMOPS_MPPZZ_S:
24307 case AArch64::SMOPA_MPPZZ_HtoS:
24308 case AArch64::SMOPA_MPPZZ_S:
24309 case AArch64::SMOPS_MPPZZ_HtoS:
24310 case AArch64::SMOPS_MPPZZ_S:
24311 case AArch64::SUMOPA_MPPZZ_S:
24312 case AArch64::SUMOPS_MPPZZ_S:
24313 case AArch64::UMOPA_MPPZZ_HtoS:
24314 case AArch64::UMOPA_MPPZZ_S:
24315 case AArch64::UMOPS_MPPZZ_HtoS:
24316 case AArch64::UMOPS_MPPZZ_S:
24317 case AArch64::USMOPA_MPPZZ_S:
24318 case AArch64::USMOPS_MPPZZ_S: {
24319 // op: Zm
24320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24321 op &= UINT64_C(31);
24322 op <<= 16;
24323 Value |= op;
24324 // op: Pm
24325 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24326 op &= UINT64_C(7);
24327 op <<= 13;
24328 Value |= op;
24329 // op: Pn
24330 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24331 op &= UINT64_C(7);
24332 op <<= 10;
24333 Value |= op;
24334 // op: Zn
24335 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
24336 op &= UINT64_C(31);
24337 op <<= 5;
24338 Value |= op;
24339 // op: ZAda
24340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24341 op &= UINT64_C(3);
24342 Value |= op;
24343 break;
24344 }
24345 case AArch64::FMOPA_MPPZZ_D:
24346 case AArch64::FMOPS_MPPZZ_D:
24347 case AArch64::SMOPA_MPPZZ_D:
24348 case AArch64::SMOPS_MPPZZ_D:
24349 case AArch64::SUMOPA_MPPZZ_D:
24350 case AArch64::SUMOPS_MPPZZ_D:
24351 case AArch64::UMOPA_MPPZZ_D:
24352 case AArch64::UMOPS_MPPZZ_D:
24353 case AArch64::USMOPA_MPPZZ_D:
24354 case AArch64::USMOPS_MPPZZ_D: {
24355 // op: Zm
24356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
24357 op &= UINT64_C(31);
24358 op <<= 16;
24359 Value |= op;
24360 // op: Pm
24361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24362 op &= UINT64_C(7);
24363 op <<= 13;
24364 Value |= op;
24365 // op: Pn
24366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24367 op &= UINT64_C(7);
24368 op <<= 10;
24369 Value |= op;
24370 // op: Zn
24371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
24372 op &= UINT64_C(31);
24373 op <<= 5;
24374 Value |= op;
24375 // op: ZAda
24376 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24377 op &= UINT64_C(7);
24378 Value |= op;
24379 break;
24380 }
24381 case AArch64::FCVTZS_2Z2Z_StoS:
24382 case AArch64::FCVTZU_2Z2Z_StoS:
24383 case AArch64::FRINTA_2Z2Z_S:
24384 case AArch64::FRINTM_2Z2Z_S:
24385 case AArch64::FRINTN_2Z2Z_S:
24386 case AArch64::FRINTP_2Z2Z_S:
24387 case AArch64::SCVTF_2Z2Z_StoS:
24388 case AArch64::UCVTF_2Z2Z_StoS: {
24389 // op: Zn
24390 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI);
24391 op &= UINT64_C(15);
24392 op <<= 6;
24393 Value |= op;
24394 // op: Zd
24395 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
24396 op &= UINT64_C(15);
24397 op <<= 1;
24398 Value |= op;
24399 break;
24400 }
24401 case AArch64::SUNPK_VG4_4Z2Z_D:
24402 case AArch64::SUNPK_VG4_4Z2Z_H:
24403 case AArch64::SUNPK_VG4_4Z2Z_S:
24404 case AArch64::UUNPK_VG4_4Z2Z_D:
24405 case AArch64::UUNPK_VG4_4Z2Z_H:
24406 case AArch64::UUNPK_VG4_4Z2Z_S: {
24407 // op: Zn
24408 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI);
24409 op &= UINT64_C(15);
24410 op <<= 6;
24411 Value |= op;
24412 // op: Zd
24413 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
24414 op &= UINT64_C(7);
24415 op <<= 2;
24416 Value |= op;
24417 break;
24418 }
24419 case AArch64::BFCVTN_Z2Z_StoH:
24420 case AArch64::BFCVT_Z2Z_HtoB:
24421 case AArch64::BFCVT_Z2Z_StoH:
24422 case AArch64::FCVTN_Z2Z_StoH:
24423 case AArch64::FCVT_Z2Z_HtoB:
24424 case AArch64::FCVT_Z2Z_StoH:
24425 case AArch64::SQCVTU_Z2Z_StoH:
24426 case AArch64::SQCVT_Z2Z_StoH:
24427 case AArch64::UQCVT_Z2Z_StoH: {
24428 // op: Zn
24429 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI);
24430 op &= UINT64_C(15);
24431 op <<= 6;
24432 Value |= op;
24433 // op: Zd
24434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24435 op &= UINT64_C(31);
24436 Value |= op;
24437 break;
24438 }
24439 case AArch64::LUTI4_4ZZT2Z: {
24440 // op: Zn
24441 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI);
24442 op &= UINT64_C(15);
24443 op <<= 6;
24444 Value |= op;
24445 // op: Zd
24446 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
24447 op &= UINT64_C(7);
24448 op <<= 2;
24449 Value |= op;
24450 break;
24451 }
24452 case AArch64::LUTI4_S_4ZZT2Z: {
24453 // op: Zn
24454 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI);
24455 op &= UINT64_C(15);
24456 op <<= 6;
24457 Value |= op;
24458 // op: Zd
24459 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
24460 Value |= (op & UINT64_C(4)) << 2;
24461 Value |= (op & UINT64_C(3));
24462 break;
24463 }
24464 case AArch64::FCVTZS_4Z4Z_StoS:
24465 case AArch64::FCVTZU_4Z4Z_StoS:
24466 case AArch64::FRINTA_4Z4Z_S:
24467 case AArch64::FRINTM_4Z4Z_S:
24468 case AArch64::FRINTN_4Z4Z_S:
24469 case AArch64::FRINTP_4Z4Z_S:
24470 case AArch64::SCVTF_4Z4Z_StoS:
24471 case AArch64::UCVTF_4Z4Z_StoS:
24472 case AArch64::UZP_VG4_4Z4Z_B:
24473 case AArch64::UZP_VG4_4Z4Z_D:
24474 case AArch64::UZP_VG4_4Z4Z_H:
24475 case AArch64::UZP_VG4_4Z4Z_Q:
24476 case AArch64::UZP_VG4_4Z4Z_S:
24477 case AArch64::ZIP_VG4_4Z4Z_B:
24478 case AArch64::ZIP_VG4_4Z4Z_D:
24479 case AArch64::ZIP_VG4_4Z4Z_H:
24480 case AArch64::ZIP_VG4_4Z4Z_Q:
24481 case AArch64::ZIP_VG4_4Z4Z_S: {
24482 // op: Zn
24483 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI);
24484 op &= UINT64_C(7);
24485 op <<= 7;
24486 Value |= op;
24487 // op: Zd
24488 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
24489 op &= UINT64_C(7);
24490 op <<= 2;
24491 Value |= op;
24492 break;
24493 }
24494 case AArch64::FCVTN_Z4Z_StoB:
24495 case AArch64::FCVT_Z4Z_StoB:
24496 case AArch64::SQCVTN_Z4Z_DtoH:
24497 case AArch64::SQCVTN_Z4Z_StoB:
24498 case AArch64::SQCVTUN_Z4Z_DtoH:
24499 case AArch64::SQCVTUN_Z4Z_StoB:
24500 case AArch64::SQCVTU_Z4Z_DtoH:
24501 case AArch64::SQCVTU_Z4Z_StoB:
24502 case AArch64::SQCVT_Z4Z_DtoH:
24503 case AArch64::SQCVT_Z4Z_StoB:
24504 case AArch64::UQCVTN_Z4Z_DtoH:
24505 case AArch64::UQCVTN_Z4Z_StoB:
24506 case AArch64::UQCVT_Z4Z_DtoH:
24507 case AArch64::UQCVT_Z4Z_StoB: {
24508 // op: Zn
24509 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI);
24510 op &= UINT64_C(7);
24511 op <<= 7;
24512 Value |= op;
24513 // op: Zd
24514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24515 op &= UINT64_C(31);
24516 Value |= op;
24517 break;
24518 }
24519 case AArch64::SQRSHRN_VG4_Z4ZI_B:
24520 case AArch64::SQRSHRUN_VG4_Z4ZI_B:
24521 case AArch64::SQRSHRU_VG4_Z4ZI_B:
24522 case AArch64::SQRSHR_VG4_Z4ZI_B:
24523 case AArch64::UQRSHRN_VG4_Z4ZI_B:
24524 case AArch64::UQRSHR_VG4_Z4ZI_B: {
24525 // op: Zn
24526 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI);
24527 op &= UINT64_C(7);
24528 op <<= 7;
24529 Value |= op;
24530 // op: Zd
24531 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24532 op &= UINT64_C(31);
24533 Value |= op;
24534 // op: imm
24535 op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI);
24536 op &= UINT64_C(31);
24537 op <<= 16;
24538 Value |= op;
24539 break;
24540 }
24541 case AArch64::SQRSHRN_VG4_Z4ZI_H:
24542 case AArch64::SQRSHRUN_VG4_Z4ZI_H:
24543 case AArch64::SQRSHRU_VG4_Z4ZI_H:
24544 case AArch64::SQRSHR_VG4_Z4ZI_H:
24545 case AArch64::UQRSHRN_VG4_Z4ZI_H:
24546 case AArch64::UQRSHR_VG4_Z4ZI_H: {
24547 // op: Zn
24548 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI);
24549 op &= UINT64_C(7);
24550 op <<= 7;
24551 Value |= op;
24552 // op: Zd
24553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24554 op &= UINT64_C(31);
24555 Value |= op;
24556 // op: imm
24557 op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI);
24558 Value |= (op & UINT64_C(32)) << 17;
24559 Value |= (op & UINT64_C(31)) << 16;
24560 break;
24561 }
24562 case AArch64::BF1CVTL_2ZZ_BtoH:
24563 case AArch64::BF1CVT_2ZZ_BtoH:
24564 case AArch64::BF2CVTL_2ZZ_BtoH:
24565 case AArch64::BF2CVT_2ZZ_BtoH:
24566 case AArch64::F1CVTL_2ZZ_BtoH:
24567 case AArch64::F1CVT_2ZZ_BtoH:
24568 case AArch64::F2CVTL_2ZZ_BtoH:
24569 case AArch64::F2CVT_2ZZ_BtoH:
24570 case AArch64::FCVTL_2ZZ_H_S:
24571 case AArch64::FCVT_2ZZ_H_S:
24572 case AArch64::SUNPK_VG2_2ZZ_D:
24573 case AArch64::SUNPK_VG2_2ZZ_H:
24574 case AArch64::SUNPK_VG2_2ZZ_S:
24575 case AArch64::UUNPK_VG2_2ZZ_D:
24576 case AArch64::UUNPK_VG2_2ZZ_H:
24577 case AArch64::UUNPK_VG2_2ZZ_S: {
24578 // op: Zn
24579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
24580 op &= UINT64_C(31);
24581 op <<= 5;
24582 Value |= op;
24583 // op: Zd
24584 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
24585 op &= UINT64_C(15);
24586 op <<= 1;
24587 Value |= op;
24588 break;
24589 }
24590 case AArch64::FADDV_VPZ_D:
24591 case AArch64::FADDV_VPZ_H:
24592 case AArch64::FADDV_VPZ_S:
24593 case AArch64::FMAXNMV_VPZ_D:
24594 case AArch64::FMAXNMV_VPZ_H:
24595 case AArch64::FMAXNMV_VPZ_S:
24596 case AArch64::FMAXV_VPZ_D:
24597 case AArch64::FMAXV_VPZ_H:
24598 case AArch64::FMAXV_VPZ_S:
24599 case AArch64::FMINNMV_VPZ_D:
24600 case AArch64::FMINNMV_VPZ_H:
24601 case AArch64::FMINNMV_VPZ_S:
24602 case AArch64::FMINV_VPZ_D:
24603 case AArch64::FMINV_VPZ_H:
24604 case AArch64::FMINV_VPZ_S: {
24605 // op: Zn
24606 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24607 op &= UINT64_C(31);
24608 op <<= 5;
24609 Value |= op;
24610 // op: Vd
24611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24612 op &= UINT64_C(31);
24613 Value |= op;
24614 // op: Pg
24615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
24616 op &= UINT64_C(7);
24617 op <<= 10;
24618 Value |= op;
24619 break;
24620 }
24621 case AArch64::LUTI4_2ZTZI_B:
24622 case AArch64::LUTI4_2ZTZI_H:
24623 case AArch64::LUTI4_2ZTZI_S: {
24624 // op: Zn
24625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24626 op &= UINT64_C(31);
24627 op <<= 5;
24628 Value |= op;
24629 // op: Zd
24630 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
24631 op &= UINT64_C(15);
24632 op <<= 1;
24633 Value |= op;
24634 // op: i
24635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24636 op &= UINT64_C(3);
24637 op <<= 15;
24638 Value |= op;
24639 break;
24640 }
24641 case AArch64::LUTI2_2ZTZI_B:
24642 case AArch64::LUTI2_2ZTZI_H:
24643 case AArch64::LUTI2_2ZTZI_S: {
24644 // op: Zn
24645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24646 op &= UINT64_C(31);
24647 op <<= 5;
24648 Value |= op;
24649 // op: Zd
24650 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
24651 op &= UINT64_C(15);
24652 op <<= 1;
24653 Value |= op;
24654 // op: i
24655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24656 op &= UINT64_C(7);
24657 op <<= 15;
24658 Value |= op;
24659 break;
24660 }
24661 case AArch64::LUTI4_4ZTZI_H:
24662 case AArch64::LUTI4_4ZTZI_S: {
24663 // op: Zn
24664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24665 op &= UINT64_C(31);
24666 op <<= 5;
24667 Value |= op;
24668 // op: Zd
24669 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
24670 op &= UINT64_C(7);
24671 op <<= 2;
24672 Value |= op;
24673 // op: i
24674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24675 op &= UINT64_C(1);
24676 op <<= 16;
24677 Value |= op;
24678 break;
24679 }
24680 case AArch64::LUTI2_4ZTZI_B:
24681 case AArch64::LUTI2_4ZTZI_H:
24682 case AArch64::LUTI2_4ZTZI_S: {
24683 // op: Zn
24684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24685 op &= UINT64_C(31);
24686 op <<= 5;
24687 Value |= op;
24688 // op: Zd
24689 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
24690 op &= UINT64_C(7);
24691 op <<= 2;
24692 Value |= op;
24693 // op: i
24694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24695 op &= UINT64_C(3);
24696 op <<= 16;
24697 Value |= op;
24698 break;
24699 }
24700 case AArch64::LUTI4_S_2ZTZI_B:
24701 case AArch64::LUTI4_S_2ZTZI_H: {
24702 // op: Zn
24703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24704 op &= UINT64_C(31);
24705 op <<= 5;
24706 Value |= op;
24707 // op: Zd
24708 op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
24709 Value |= (op & UINT64_C(8)) << 1;
24710 Value |= (op & UINT64_C(7));
24711 // op: i
24712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24713 op &= UINT64_C(3);
24714 op <<= 15;
24715 Value |= op;
24716 break;
24717 }
24718 case AArch64::LUTI2_S_2ZTZI_B:
24719 case AArch64::LUTI2_S_2ZTZI_H: {
24720 // op: Zn
24721 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24722 op &= UINT64_C(31);
24723 op <<= 5;
24724 Value |= op;
24725 // op: Zd
24726 op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
24727 Value |= (op & UINT64_C(8)) << 1;
24728 Value |= (op & UINT64_C(7));
24729 // op: i
24730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24731 op &= UINT64_C(7);
24732 op <<= 15;
24733 Value |= op;
24734 break;
24735 }
24736 case AArch64::LUTI4_S_4ZTZI_H: {
24737 // op: Zn
24738 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24739 op &= UINT64_C(31);
24740 op <<= 5;
24741 Value |= op;
24742 // op: Zd
24743 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
24744 Value |= (op & UINT64_C(4)) << 2;
24745 Value |= (op & UINT64_C(3));
24746 // op: i
24747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24748 op &= UINT64_C(1);
24749 op <<= 16;
24750 Value |= op;
24751 break;
24752 }
24753 case AArch64::LUTI2_S_4ZTZI_B:
24754 case AArch64::LUTI2_S_4ZTZI_H: {
24755 // op: Zn
24756 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24757 op &= UINT64_C(31);
24758 op <<= 5;
24759 Value |= op;
24760 // op: Zd
24761 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
24762 Value |= (op & UINT64_C(4)) << 2;
24763 Value |= (op & UINT64_C(3));
24764 // op: i
24765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24766 op &= UINT64_C(3);
24767 op <<= 16;
24768 Value |= op;
24769 break;
24770 }
24771 case AArch64::LUTI2_ZTZI_B:
24772 case AArch64::LUTI2_ZTZI_H:
24773 case AArch64::LUTI2_ZTZI_S: {
24774 // op: Zn
24775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24776 op &= UINT64_C(31);
24777 op <<= 5;
24778 Value |= op;
24779 // op: Zd
24780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24781 op &= UINT64_C(31);
24782 Value |= op;
24783 // op: i
24784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24785 op &= UINT64_C(15);
24786 op <<= 14;
24787 Value |= op;
24788 break;
24789 }
24790 case AArch64::LUTI4_ZTZI_B:
24791 case AArch64::LUTI4_ZTZI_H:
24792 case AArch64::LUTI4_ZTZI_S: {
24793 // op: Zn
24794 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24795 op &= UINT64_C(31);
24796 op <<= 5;
24797 Value |= op;
24798 // op: Zd
24799 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24800 op &= UINT64_C(31);
24801 Value |= op;
24802 // op: i
24803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24804 op &= UINT64_C(7);
24805 op <<= 14;
24806 Value |= op;
24807 break;
24808 }
24809 case AArch64::LD1B_2Z:
24810 case AArch64::LD1D_2Z:
24811 case AArch64::LD1H_2Z:
24812 case AArch64::LD1W_2Z:
24813 case AArch64::LDNT1B_2Z:
24814 case AArch64::LDNT1D_2Z:
24815 case AArch64::LDNT1H_2Z:
24816 case AArch64::LDNT1W_2Z:
24817 case AArch64::ST1B_2Z:
24818 case AArch64::ST1D_2Z:
24819 case AArch64::ST1H_2Z:
24820 case AArch64::ST1W_2Z:
24821 case AArch64::STNT1B_2Z:
24822 case AArch64::STNT1D_2Z:
24823 case AArch64::STNT1H_2Z:
24824 case AArch64::STNT1W_2Z: {
24825 // op: Zt
24826 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
24827 op &= UINT64_C(15);
24828 op <<= 1;
24829 Value |= op;
24830 // op: Rm
24831 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24832 op &= UINT64_C(31);
24833 op <<= 16;
24834 Value |= op;
24835 // op: Rn
24836 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24837 op &= UINT64_C(31);
24838 op <<= 5;
24839 Value |= op;
24840 // op: PNg
24841 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
24842 op &= UINT64_C(7);
24843 op <<= 10;
24844 Value |= op;
24845 break;
24846 }
24847 case AArch64::LD1B_2Z_IMM:
24848 case AArch64::LD1D_2Z_IMM:
24849 case AArch64::LD1H_2Z_IMM:
24850 case AArch64::LD1W_2Z_IMM:
24851 case AArch64::LDNT1B_2Z_IMM:
24852 case AArch64::LDNT1D_2Z_IMM:
24853 case AArch64::LDNT1H_2Z_IMM:
24854 case AArch64::LDNT1W_2Z_IMM:
24855 case AArch64::ST1B_2Z_IMM:
24856 case AArch64::ST1D_2Z_IMM:
24857 case AArch64::ST1H_2Z_IMM:
24858 case AArch64::ST1W_2Z_IMM:
24859 case AArch64::STNT1B_2Z_IMM:
24860 case AArch64::STNT1D_2Z_IMM:
24861 case AArch64::STNT1H_2Z_IMM:
24862 case AArch64::STNT1W_2Z_IMM: {
24863 // op: Zt
24864 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI);
24865 op &= UINT64_C(15);
24866 op <<= 1;
24867 Value |= op;
24868 // op: Rn
24869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24870 op &= UINT64_C(31);
24871 op <<= 5;
24872 Value |= op;
24873 // op: PNg
24874 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
24875 op &= UINT64_C(7);
24876 op <<= 10;
24877 Value |= op;
24878 // op: imm4
24879 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24880 op &= UINT64_C(15);
24881 op <<= 16;
24882 Value |= op;
24883 break;
24884 }
24885 case AArch64::LD1B_4Z:
24886 case AArch64::LD1D_4Z:
24887 case AArch64::LD1H_4Z:
24888 case AArch64::LD1W_4Z:
24889 case AArch64::LDNT1B_4Z:
24890 case AArch64::LDNT1D_4Z:
24891 case AArch64::LDNT1H_4Z:
24892 case AArch64::LDNT1W_4Z:
24893 case AArch64::ST1B_4Z:
24894 case AArch64::ST1D_4Z:
24895 case AArch64::ST1H_4Z:
24896 case AArch64::ST1W_4Z:
24897 case AArch64::STNT1B_4Z:
24898 case AArch64::STNT1D_4Z:
24899 case AArch64::STNT1H_4Z:
24900 case AArch64::STNT1W_4Z: {
24901 // op: Zt
24902 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
24903 op &= UINT64_C(7);
24904 op <<= 2;
24905 Value |= op;
24906 // op: Rm
24907 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24908 op &= UINT64_C(31);
24909 op <<= 16;
24910 Value |= op;
24911 // op: Rn
24912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24913 op &= UINT64_C(31);
24914 op <<= 5;
24915 Value |= op;
24916 // op: PNg
24917 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
24918 op &= UINT64_C(7);
24919 op <<= 10;
24920 Value |= op;
24921 break;
24922 }
24923 case AArch64::LD1B_4Z_IMM:
24924 case AArch64::LD1D_4Z_IMM:
24925 case AArch64::LD1H_4Z_IMM:
24926 case AArch64::LD1W_4Z_IMM:
24927 case AArch64::LDNT1B_4Z_IMM:
24928 case AArch64::LDNT1D_4Z_IMM:
24929 case AArch64::LDNT1H_4Z_IMM:
24930 case AArch64::LDNT1W_4Z_IMM:
24931 case AArch64::ST1B_4Z_IMM:
24932 case AArch64::ST1D_4Z_IMM:
24933 case AArch64::ST1H_4Z_IMM:
24934 case AArch64::ST1W_4Z_IMM:
24935 case AArch64::STNT1B_4Z_IMM:
24936 case AArch64::STNT1D_4Z_IMM:
24937 case AArch64::STNT1H_4Z_IMM:
24938 case AArch64::STNT1W_4Z_IMM: {
24939 // op: Zt
24940 op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI);
24941 op &= UINT64_C(7);
24942 op <<= 2;
24943 Value |= op;
24944 // op: Rn
24945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
24946 op &= UINT64_C(31);
24947 op <<= 5;
24948 Value |= op;
24949 // op: PNg
24950 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
24951 op &= UINT64_C(7);
24952 op <<= 10;
24953 Value |= op;
24954 // op: imm4
24955 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
24956 op &= UINT64_C(15);
24957 op <<= 16;
24958 Value |= op;
24959 break;
24960 }
24961 case AArch64::LD1B:
24962 case AArch64::LD1B_D:
24963 case AArch64::LD1B_H:
24964 case AArch64::LD1B_S:
24965 case AArch64::LD1D:
24966 case AArch64::LD1H:
24967 case AArch64::LD1H_D:
24968 case AArch64::LD1H_S:
24969 case AArch64::LD1SB_D:
24970 case AArch64::LD1SB_H:
24971 case AArch64::LD1SB_S:
24972 case AArch64::LD1SH_D:
24973 case AArch64::LD1SH_S:
24974 case AArch64::LD1SW_D:
24975 case AArch64::LD1W:
24976 case AArch64::LD1W_D:
24977 case AArch64::LDFF1B:
24978 case AArch64::LDFF1B_D:
24979 case AArch64::LDFF1B_H:
24980 case AArch64::LDFF1B_S:
24981 case AArch64::LDFF1D:
24982 case AArch64::LDFF1H:
24983 case AArch64::LDFF1H_D:
24984 case AArch64::LDFF1H_S:
24985 case AArch64::LDFF1SB_D:
24986 case AArch64::LDFF1SB_H:
24987 case AArch64::LDFF1SB_S:
24988 case AArch64::LDFF1SH_D:
24989 case AArch64::LDFF1SH_S:
24990 case AArch64::LDFF1SW_D:
24991 case AArch64::LDFF1W:
24992 case AArch64::LDFF1W_D: {
24993 // op: Zt
24994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
24995 op &= UINT64_C(31);
24996 Value |= op;
24997 // op: Pg
24998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
24999 op &= UINT64_C(7);
25000 op <<= 10;
25001 Value |= op;
25002 // op: Rm
25003 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25004 op &= UINT64_C(31);
25005 op <<= 16;
25006 Value |= op;
25007 // op: Rn
25008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25009 op &= UINT64_C(31);
25010 op <<= 5;
25011 Value |= op;
25012 break;
25013 }
25014 case AArch64::LD1RO_B:
25015 case AArch64::LD1RO_D:
25016 case AArch64::LD1RO_H:
25017 case AArch64::LD1RO_W:
25018 case AArch64::LD1RQ_B:
25019 case AArch64::LD1RQ_D:
25020 case AArch64::LD1RQ_H:
25021 case AArch64::LD1RQ_W: {
25022 // op: Zt
25023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25024 op &= UINT64_C(31);
25025 Value |= op;
25026 // op: Pg
25027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25028 op &= UINT64_C(7);
25029 op <<= 10;
25030 Value |= op;
25031 // op: Rn
25032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25033 op &= UINT64_C(31);
25034 op <<= 5;
25035 Value |= op;
25036 // op: Rm
25037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25038 op &= UINT64_C(31);
25039 op <<= 16;
25040 Value |= op;
25041 break;
25042 }
25043 case AArch64::LD2B_IMM:
25044 case AArch64::LD2D_IMM:
25045 case AArch64::LD2H_IMM:
25046 case AArch64::LD2Q_IMM:
25047 case AArch64::LD2W_IMM:
25048 case AArch64::LD3B_IMM:
25049 case AArch64::LD3D_IMM:
25050 case AArch64::LD3H_IMM:
25051 case AArch64::LD3Q_IMM:
25052 case AArch64::LD3W_IMM:
25053 case AArch64::LD4B_IMM:
25054 case AArch64::LD4D_IMM:
25055 case AArch64::LD4H_IMM:
25056 case AArch64::LD4Q_IMM:
25057 case AArch64::LD4W_IMM:
25058 case AArch64::LDNT1B_ZRI:
25059 case AArch64::LDNT1D_ZRI:
25060 case AArch64::LDNT1H_ZRI:
25061 case AArch64::LDNT1W_ZRI: {
25062 // op: Zt
25063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25064 op &= UINT64_C(31);
25065 Value |= op;
25066 // op: Pg
25067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25068 op &= UINT64_C(7);
25069 op <<= 10;
25070 Value |= op;
25071 // op: Rn
25072 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25073 op &= UINT64_C(31);
25074 op <<= 5;
25075 Value |= op;
25076 // op: imm4
25077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25078 op &= UINT64_C(15);
25079 op <<= 16;
25080 Value |= op;
25081 break;
25082 }
25083 case AArch64::LD1D_Q:
25084 case AArch64::LD1W_Q:
25085 case AArch64::ST2Q:
25086 case AArch64::ST3Q:
25087 case AArch64::ST4Q: {
25088 // op: Zt
25089 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25090 op &= UINT64_C(31);
25091 Value |= op;
25092 // op: Rn
25093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25094 op &= UINT64_C(31);
25095 op <<= 5;
25096 Value |= op;
25097 // op: Pg
25098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25099 op &= UINT64_C(7);
25100 op <<= 10;
25101 Value |= op;
25102 // op: Rm
25103 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25104 op &= UINT64_C(31);
25105 op <<= 16;
25106 Value |= op;
25107 break;
25108 }
25109 case AArch64::LD1D_Q_IMM:
25110 case AArch64::LD1RO_B_IMM:
25111 case AArch64::LD1RO_D_IMM:
25112 case AArch64::LD1RO_H_IMM:
25113 case AArch64::LD1RO_W_IMM:
25114 case AArch64::LD1RQ_B_IMM:
25115 case AArch64::LD1RQ_D_IMM:
25116 case AArch64::LD1RQ_H_IMM:
25117 case AArch64::LD1RQ_W_IMM:
25118 case AArch64::LD1W_Q_IMM:
25119 case AArch64::ST2Q_IMM:
25120 case AArch64::ST3Q_IMM:
25121 case AArch64::ST4Q_IMM: {
25122 // op: Zt
25123 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25124 op &= UINT64_C(31);
25125 Value |= op;
25126 // op: Rn
25127 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25128 op &= UINT64_C(31);
25129 op <<= 5;
25130 Value |= op;
25131 // op: Pg
25132 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25133 op &= UINT64_C(7);
25134 op <<= 10;
25135 Value |= op;
25136 // op: imm4
25137 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25138 op &= UINT64_C(15);
25139 op <<= 16;
25140 Value |= op;
25141 break;
25142 }
25143 case AArch64::GLD1Q:
25144 case AArch64::SST1Q: {
25145 // op: Zt
25146 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25147 op &= UINT64_C(31);
25148 Value |= op;
25149 // op: Zn
25150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25151 op &= UINT64_C(31);
25152 op <<= 5;
25153 Value |= op;
25154 // op: Pg
25155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25156 op &= UINT64_C(7);
25157 op <<= 10;
25158 Value |= op;
25159 // op: Rm
25160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25161 op &= UINT64_C(31);
25162 op <<= 16;
25163 Value |= op;
25164 break;
25165 }
25166 case AArch64::MOVT_TIZ: {
25167 // op: Zt
25168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25169 op &= UINT64_C(31);
25170 Value |= op;
25171 // op: off2
25172 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25173 op &= UINT64_C(3);
25174 op <<= 12;
25175 Value |= op;
25176 break;
25177 }
25178 case AArch64::B:
25179 case AArch64::BL: {
25180 // op: addr
25181 op = getBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI);
25182 op &= UINT64_C(67108863);
25183 Value |= op;
25184 break;
25185 }
25186 case AArch64::BCcc:
25187 case AArch64::Bcc: {
25188 // op: cond
25189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25190 op &= UINT64_C(15);
25191 Value |= op;
25192 // op: target
25193 op = getCondBranchTargetOpValue(MI, OpIdx: 1, Fixups, STI);
25194 op &= UINT64_C(524287);
25195 op <<= 5;
25196 Value |= op;
25197 break;
25198 }
25199 case AArch64::DUPi64: {
25200 // op: dst
25201 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25202 op &= UINT64_C(31);
25203 Value |= op;
25204 // op: src
25205 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25206 op &= UINT64_C(31);
25207 op <<= 5;
25208 Value |= op;
25209 // op: idx
25210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25211 op &= UINT64_C(1);
25212 op <<= 20;
25213 Value |= op;
25214 break;
25215 }
25216 case AArch64::DUPi8: {
25217 // op: dst
25218 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25219 op &= UINT64_C(31);
25220 Value |= op;
25221 // op: src
25222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25223 op &= UINT64_C(31);
25224 op <<= 5;
25225 Value |= op;
25226 // op: idx
25227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25228 op &= UINT64_C(15);
25229 op <<= 17;
25230 Value |= op;
25231 break;
25232 }
25233 case AArch64::DUPi32: {
25234 // op: dst
25235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25236 op &= UINT64_C(31);
25237 Value |= op;
25238 // op: src
25239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25240 op &= UINT64_C(31);
25241 op <<= 5;
25242 Value |= op;
25243 // op: idx
25244 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25245 op &= UINT64_C(3);
25246 op <<= 19;
25247 Value |= op;
25248 break;
25249 }
25250 case AArch64::DUPi16: {
25251 // op: dst
25252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25253 op &= UINT64_C(31);
25254 Value |= op;
25255 // op: src
25256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25257 op &= UINT64_C(31);
25258 op <<= 5;
25259 Value |= op;
25260 // op: idx
25261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25262 op &= UINT64_C(7);
25263 op <<= 18;
25264 Value |= op;
25265 break;
25266 }
25267 case AArch64::ZERO_M: {
25268 // op: imm
25269 op = EncodeMatrixTileListRegisterClass(MI, OpIdx: 0, Fixups, STI);
25270 op &= UINT64_C(255);
25271 Value |= op;
25272 break;
25273 }
25274 case AArch64::HINT: {
25275 // op: imm
25276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25277 op &= UINT64_C(127);
25278 op <<= 5;
25279 Value |= op;
25280 break;
25281 }
25282 case AArch64::UDF: {
25283 // op: imm
25284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25285 op &= UINT64_C(65535);
25286 Value |= op;
25287 break;
25288 }
25289 case AArch64::BRK:
25290 case AArch64::DCPS1:
25291 case AArch64::DCPS2:
25292 case AArch64::DCPS3:
25293 case AArch64::HLT:
25294 case AArch64::HVC:
25295 case AArch64::SMC:
25296 case AArch64::SVC:
25297 case AArch64::TCANCEL: {
25298 // op: imm
25299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25300 op &= UINT64_C(65535);
25301 op <<= 5;
25302 Value |= op;
25303 break;
25304 }
25305 case AArch64::MOVT_TIX: {
25306 // op: imm3
25307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25308 op &= UINT64_C(7);
25309 op <<= 12;
25310 Value |= op;
25311 // op: Rt
25312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25313 op &= UINT64_C(31);
25314 Value |= op;
25315 break;
25316 }
25317 case AArch64::MOVT_XTI: {
25318 // op: imm3
25319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25320 op &= UINT64_C(7);
25321 op <<= 12;
25322 Value |= op;
25323 // op: Rt
25324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25325 op &= UINT64_C(31);
25326 Value |= op;
25327 break;
25328 }
25329 case AArch64::LD1B_2Z_STRIDED_IMM:
25330 case AArch64::LD1D_2Z_STRIDED_IMM:
25331 case AArch64::LD1H_2Z_STRIDED_IMM:
25332 case AArch64::LD1W_2Z_STRIDED_IMM:
25333 case AArch64::LDNT1B_2Z_STRIDED_IMM:
25334 case AArch64::LDNT1D_2Z_STRIDED_IMM:
25335 case AArch64::LDNT1H_2Z_STRIDED_IMM:
25336 case AArch64::LDNT1W_2Z_STRIDED_IMM:
25337 case AArch64::ST1B_2Z_STRIDED_IMM:
25338 case AArch64::ST1D_2Z_STRIDED_IMM:
25339 case AArch64::ST1H_2Z_STRIDED_IMM:
25340 case AArch64::ST1W_2Z_STRIDED_IMM:
25341 case AArch64::STNT1B_2Z_STRIDED_IMM:
25342 case AArch64::STNT1D_2Z_STRIDED_IMM:
25343 case AArch64::STNT1H_2Z_STRIDED_IMM:
25344 case AArch64::STNT1W_2Z_STRIDED_IMM: {
25345 // op: imm4
25346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25347 op &= UINT64_C(15);
25348 op <<= 16;
25349 Value |= op;
25350 // op: PNg
25351 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
25352 op &= UINT64_C(7);
25353 op <<= 10;
25354 Value |= op;
25355 // op: Rn
25356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25357 op &= UINT64_C(31);
25358 op <<= 5;
25359 Value |= op;
25360 // op: Zt
25361 op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
25362 Value |= (op & UINT64_C(8)) << 1;
25363 Value |= (op & UINT64_C(7));
25364 break;
25365 }
25366 case AArch64::LD1B_4Z_STRIDED_IMM:
25367 case AArch64::LD1D_4Z_STRIDED_IMM:
25368 case AArch64::LD1H_4Z_STRIDED_IMM:
25369 case AArch64::LD1W_4Z_STRIDED_IMM:
25370 case AArch64::LDNT1B_4Z_STRIDED_IMM:
25371 case AArch64::LDNT1D_4Z_STRIDED_IMM:
25372 case AArch64::LDNT1H_4Z_STRIDED_IMM:
25373 case AArch64::LDNT1W_4Z_STRIDED_IMM:
25374 case AArch64::ST1B_4Z_STRIDED_IMM:
25375 case AArch64::ST1D_4Z_STRIDED_IMM:
25376 case AArch64::ST1H_4Z_STRIDED_IMM:
25377 case AArch64::ST1W_4Z_STRIDED_IMM:
25378 case AArch64::STNT1B_4Z_STRIDED_IMM:
25379 case AArch64::STNT1D_4Z_STRIDED_IMM:
25380 case AArch64::STNT1H_4Z_STRIDED_IMM:
25381 case AArch64::STNT1W_4Z_STRIDED_IMM: {
25382 // op: imm4
25383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25384 op &= UINT64_C(15);
25385 op <<= 16;
25386 Value |= op;
25387 // op: PNg
25388 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
25389 op &= UINT64_C(7);
25390 op <<= 10;
25391 Value |= op;
25392 // op: Rn
25393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25394 op &= UINT64_C(31);
25395 op <<= 5;
25396 Value |= op;
25397 // op: Zt
25398 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
25399 Value |= (op & UINT64_C(4)) << 2;
25400 Value |= (op & UINT64_C(3));
25401 break;
25402 }
25403 case AArch64::SQRSHRU_VG2_Z2ZI_H:
25404 case AArch64::SQRSHR_VG2_Z2ZI_H:
25405 case AArch64::UQRSHR_VG2_Z2ZI_H: {
25406 // op: imm4
25407 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
25408 op &= UINT64_C(15);
25409 op <<= 16;
25410 Value |= op;
25411 // op: Zn
25412 op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI);
25413 op &= UINT64_C(15);
25414 op <<= 6;
25415 Value |= op;
25416 // op: Zd
25417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25418 op &= UINT64_C(31);
25419 Value |= op;
25420 break;
25421 }
25422 case AArch64::AUTIASPPCi:
25423 case AArch64::AUTIBSPPCi:
25424 case AArch64::RETAASPPCi:
25425 case AArch64::RETABSPPCi: {
25426 // op: label
25427 op = getPAuthPCRelOpValue(MI, OpIdx: 0, Fixups, STI);
25428 op &= UINT64_C(65535);
25429 op <<= 5;
25430 Value |= op;
25431 break;
25432 }
25433 case AArch64::LDRAAindexed:
25434 case AArch64::LDRABindexed: {
25435 // op: offset
25436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25437 Value |= (op & UINT64_C(512)) << 13;
25438 Value |= (op & UINT64_C(511)) << 12;
25439 // op: Rn
25440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25441 op &= UINT64_C(31);
25442 op <<= 5;
25443 Value |= op;
25444 // op: Rt
25445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25446 op &= UINT64_C(31);
25447 Value |= op;
25448 break;
25449 }
25450 case AArch64::LDRAAwriteback:
25451 case AArch64::LDRABwriteback: {
25452 // op: offset
25453 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25454 Value |= (op & UINT64_C(512)) << 13;
25455 Value |= (op & UINT64_C(511)) << 12;
25456 // op: Rn
25457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25458 op &= UINT64_C(31);
25459 op <<= 5;
25460 Value |= op;
25461 // op: Rt
25462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25463 op &= UINT64_C(31);
25464 Value |= op;
25465 break;
25466 }
25467 case AArch64::SYSPxt_XZR: {
25468 // op: op1
25469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25470 op &= UINT64_C(7);
25471 op <<= 16;
25472 Value |= op;
25473 // op: Cn
25474 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25475 op &= UINT64_C(15);
25476 op <<= 12;
25477 Value |= op;
25478 // op: Cm
25479 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
25480 op &= UINT64_C(15);
25481 op <<= 8;
25482 Value |= op;
25483 // op: op2
25484 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
25485 op &= UINT64_C(7);
25486 op <<= 5;
25487 Value |= op;
25488 break;
25489 }
25490 case AArch64::STSHH: {
25491 // op: policy
25492 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25493 op &= UINT64_C(7);
25494 op <<= 5;
25495 Value |= op;
25496 break;
25497 }
25498 case AArch64::MSRpstateImm1: {
25499 // op: pstatefield
25500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25501 Value |= (op & UINT64_C(56)) << 13;
25502 Value |= (op & UINT64_C(448)) << 3;
25503 Value |= (op & UINT64_C(7)) << 5;
25504 // op: imm
25505 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25506 op &= UINT64_C(1);
25507 op <<= 8;
25508 Value |= op;
25509 break;
25510 }
25511 case AArch64::MSRpstateImm4: {
25512 // op: pstatefield
25513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25514 Value |= (op & UINT64_C(56)) << 13;
25515 Value |= (op & UINT64_C(7)) << 5;
25516 // op: imm
25517 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25518 op &= UINT64_C(15);
25519 op <<= 8;
25520 Value |= op;
25521 break;
25522 }
25523 case AArch64::MSRpstatesvcrImm1: {
25524 // op: pstatefield
25525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
25526 op &= UINT64_C(7);
25527 op <<= 9;
25528 Value |= op;
25529 // op: imm
25530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
25531 op &= UINT64_C(1);
25532 op <<= 8;
25533 Value |= op;
25534 break;
25535 }
25536 default:
25537 std::string msg;
25538 raw_string_ostream Msg(msg);
25539 Msg << "Not supported instr: " << MI;
25540 report_fatal_error(reason: Msg.str().c_str());
25541 }
25542 return Value;
25543}
25544
25545#ifdef GET_OPERAND_BIT_OFFSET
25546#undef GET_OPERAND_BIT_OFFSET
25547
25548uint32_t AArch64MCCodeEmitter::getOperandBitOffset(const MCInst &MI,
25549 unsigned OpNum,
25550 const MCSubtargetInfo &STI) const {
25551 switch (MI.getOpcode()) {
25552 case AArch64::AUTIA1716:
25553 case AArch64::AUTIA171615:
25554 case AArch64::AUTIASP:
25555 case AArch64::AUTIAZ:
25556 case AArch64::AUTIB1716:
25557 case AArch64::AUTIB171615:
25558 case AArch64::AUTIBSP:
25559 case AArch64::AUTIBZ:
25560 case AArch64::AXFLAG:
25561 case AArch64::BRB_IALL:
25562 case AArch64::BRB_INJ:
25563 case AArch64::CFINV:
25564 case AArch64::CHKFEAT:
25565 case AArch64::DRPS:
25566 case AArch64::ERET:
25567 case AArch64::ERETAA:
25568 case AArch64::ERETAB:
25569 case AArch64::GCSPOPCX:
25570 case AArch64::GCSPOPX:
25571 case AArch64::GCSPUSHX:
25572 case AArch64::PACIA1716:
25573 case AArch64::PACIA171615:
25574 case AArch64::PACIASP:
25575 case AArch64::PACIASPPC:
25576 case AArch64::PACIAZ:
25577 case AArch64::PACIB1716:
25578 case AArch64::PACIB171615:
25579 case AArch64::PACIBSP:
25580 case AArch64::PACIBSPPC:
25581 case AArch64::PACIBZ:
25582 case AArch64::PACM:
25583 case AArch64::PACNBIASPPC:
25584 case AArch64::PACNBIBSPPC:
25585 case AArch64::RETAA:
25586 case AArch64::RETAB:
25587 case AArch64::SB:
25588 case AArch64::SETFFR:
25589 case AArch64::TCOMMIT:
25590 case AArch64::TSB:
25591 case AArch64::XAFLAG:
25592 case AArch64::XPACLRI:
25593 case AArch64::ZERO_T: {
25594 break;
25595 }
25596 case AArch64::DSBnXS: {
25597 switch (OpNum) {
25598 case 0:
25599 // op: CRm
25600 return 10;
25601 }
25602 break;
25603 }
25604 case AArch64::CLREX:
25605 case AArch64::DMB:
25606 case AArch64::DSB:
25607 case AArch64::ISB: {
25608 switch (OpNum) {
25609 case 0:
25610 // op: CRm
25611 return 8;
25612 }
25613 break;
25614 }
25615 case AArch64::WHILEGE_CXX_B:
25616 case AArch64::WHILEGE_CXX_D:
25617 case AArch64::WHILEGE_CXX_H:
25618 case AArch64::WHILEGE_CXX_S:
25619 case AArch64::WHILEGT_CXX_B:
25620 case AArch64::WHILEGT_CXX_D:
25621 case AArch64::WHILEGT_CXX_H:
25622 case AArch64::WHILEGT_CXX_S:
25623 case AArch64::WHILEHI_CXX_B:
25624 case AArch64::WHILEHI_CXX_D:
25625 case AArch64::WHILEHI_CXX_H:
25626 case AArch64::WHILEHI_CXX_S:
25627 case AArch64::WHILEHS_CXX_B:
25628 case AArch64::WHILEHS_CXX_D:
25629 case AArch64::WHILEHS_CXX_H:
25630 case AArch64::WHILEHS_CXX_S:
25631 case AArch64::WHILELE_CXX_B:
25632 case AArch64::WHILELE_CXX_D:
25633 case AArch64::WHILELE_CXX_H:
25634 case AArch64::WHILELE_CXX_S:
25635 case AArch64::WHILELO_CXX_B:
25636 case AArch64::WHILELO_CXX_D:
25637 case AArch64::WHILELO_CXX_H:
25638 case AArch64::WHILELO_CXX_S:
25639 case AArch64::WHILELS_CXX_B:
25640 case AArch64::WHILELS_CXX_D:
25641 case AArch64::WHILELS_CXX_H:
25642 case AArch64::WHILELS_CXX_S:
25643 case AArch64::WHILELT_CXX_B:
25644 case AArch64::WHILELT_CXX_D:
25645 case AArch64::WHILELT_CXX_H:
25646 case AArch64::WHILELT_CXX_S: {
25647 switch (OpNum) {
25648 case 0:
25649 // op: PNd
25650 return 0;
25651 case 1:
25652 // op: Rn
25653 return 5;
25654 case 3:
25655 // op: vl
25656 return 13;
25657 case 2:
25658 // op: Rm
25659 return 16;
25660 }
25661 break;
25662 }
25663 case AArch64::PTRUE_C_B:
25664 case AArch64::PTRUE_C_D:
25665 case AArch64::PTRUE_C_H:
25666 case AArch64::PTRUE_C_S: {
25667 switch (OpNum) {
25668 case 0:
25669 // op: PNd
25670 return 0;
25671 }
25672 break;
25673 }
25674 case AArch64::PEXT_2PCI_B:
25675 case AArch64::PEXT_2PCI_D:
25676 case AArch64::PEXT_2PCI_H:
25677 case AArch64::PEXT_2PCI_S:
25678 case AArch64::PEXT_PCI_B:
25679 case AArch64::PEXT_PCI_D:
25680 case AArch64::PEXT_PCI_H:
25681 case AArch64::PEXT_PCI_S: {
25682 switch (OpNum) {
25683 case 0:
25684 // op: Pd
25685 return 0;
25686 case 1:
25687 // op: PNn
25688 return 5;
25689 case 2:
25690 // op: index
25691 return 8;
25692 }
25693 break;
25694 }
25695 case AArch64::BRKAS_PPzP:
25696 case AArch64::BRKA_PPzP:
25697 case AArch64::BRKBS_PPzP:
25698 case AArch64::BRKB_PPzP: {
25699 switch (OpNum) {
25700 case 0:
25701 // op: Pd
25702 return 0;
25703 case 1:
25704 // op: Pg
25705 return 10;
25706 case 2:
25707 // op: Pn
25708 return 5;
25709 }
25710 break;
25711 }
25712 case AArch64::CMPEQ_PPzZI_B:
25713 case AArch64::CMPEQ_PPzZI_D:
25714 case AArch64::CMPEQ_PPzZI_H:
25715 case AArch64::CMPEQ_PPzZI_S:
25716 case AArch64::CMPGE_PPzZI_B:
25717 case AArch64::CMPGE_PPzZI_D:
25718 case AArch64::CMPGE_PPzZI_H:
25719 case AArch64::CMPGE_PPzZI_S:
25720 case AArch64::CMPGT_PPzZI_B:
25721 case AArch64::CMPGT_PPzZI_D:
25722 case AArch64::CMPGT_PPzZI_H:
25723 case AArch64::CMPGT_PPzZI_S:
25724 case AArch64::CMPLE_PPzZI_B:
25725 case AArch64::CMPLE_PPzZI_D:
25726 case AArch64::CMPLE_PPzZI_H:
25727 case AArch64::CMPLE_PPzZI_S:
25728 case AArch64::CMPLT_PPzZI_B:
25729 case AArch64::CMPLT_PPzZI_D:
25730 case AArch64::CMPLT_PPzZI_H:
25731 case AArch64::CMPLT_PPzZI_S:
25732 case AArch64::CMPNE_PPzZI_B:
25733 case AArch64::CMPNE_PPzZI_D:
25734 case AArch64::CMPNE_PPzZI_H:
25735 case AArch64::CMPNE_PPzZI_S: {
25736 switch (OpNum) {
25737 case 0:
25738 // op: Pd
25739 return 0;
25740 case 1:
25741 // op: Pg
25742 return 10;
25743 case 2:
25744 // op: Zn
25745 return 5;
25746 case 3:
25747 // op: imm5
25748 return 16;
25749 }
25750 break;
25751 }
25752 case AArch64::CMPHI_PPzZI_B:
25753 case AArch64::CMPHI_PPzZI_D:
25754 case AArch64::CMPHI_PPzZI_H:
25755 case AArch64::CMPHI_PPzZI_S:
25756 case AArch64::CMPHS_PPzZI_B:
25757 case AArch64::CMPHS_PPzZI_D:
25758 case AArch64::CMPHS_PPzZI_H:
25759 case AArch64::CMPHS_PPzZI_S:
25760 case AArch64::CMPLO_PPzZI_B:
25761 case AArch64::CMPLO_PPzZI_D:
25762 case AArch64::CMPLO_PPzZI_H:
25763 case AArch64::CMPLO_PPzZI_S:
25764 case AArch64::CMPLS_PPzZI_B:
25765 case AArch64::CMPLS_PPzZI_D:
25766 case AArch64::CMPLS_PPzZI_H:
25767 case AArch64::CMPLS_PPzZI_S: {
25768 switch (OpNum) {
25769 case 0:
25770 // op: Pd
25771 return 0;
25772 case 1:
25773 // op: Pg
25774 return 10;
25775 case 2:
25776 // op: Zn
25777 return 5;
25778 case 3:
25779 // op: imm7
25780 return 14;
25781 }
25782 break;
25783 }
25784 case AArch64::FCMEQ_PPzZ0_D:
25785 case AArch64::FCMEQ_PPzZ0_H:
25786 case AArch64::FCMEQ_PPzZ0_S:
25787 case AArch64::FCMGE_PPzZ0_D:
25788 case AArch64::FCMGE_PPzZ0_H:
25789 case AArch64::FCMGE_PPzZ0_S:
25790 case AArch64::FCMGT_PPzZ0_D:
25791 case AArch64::FCMGT_PPzZ0_H:
25792 case AArch64::FCMGT_PPzZ0_S:
25793 case AArch64::FCMLE_PPzZ0_D:
25794 case AArch64::FCMLE_PPzZ0_H:
25795 case AArch64::FCMLE_PPzZ0_S:
25796 case AArch64::FCMLT_PPzZ0_D:
25797 case AArch64::FCMLT_PPzZ0_H:
25798 case AArch64::FCMLT_PPzZ0_S:
25799 case AArch64::FCMNE_PPzZ0_D:
25800 case AArch64::FCMNE_PPzZ0_H:
25801 case AArch64::FCMNE_PPzZ0_S: {
25802 switch (OpNum) {
25803 case 0:
25804 // op: Pd
25805 return 0;
25806 case 1:
25807 // op: Pg
25808 return 10;
25809 case 2:
25810 // op: Zn
25811 return 5;
25812 }
25813 break;
25814 }
25815 case AArch64::ANDS_PPzPP:
25816 case AArch64::AND_PPzPP:
25817 case AArch64::BICS_PPzPP:
25818 case AArch64::BIC_PPzPP:
25819 case AArch64::BRKPAS_PPzPP:
25820 case AArch64::BRKPA_PPzPP:
25821 case AArch64::BRKPBS_PPzPP:
25822 case AArch64::BRKPB_PPzPP:
25823 case AArch64::EORS_PPzPP:
25824 case AArch64::EOR_PPzPP:
25825 case AArch64::NANDS_PPzPP:
25826 case AArch64::NAND_PPzPP:
25827 case AArch64::NORS_PPzPP:
25828 case AArch64::NOR_PPzPP:
25829 case AArch64::ORNS_PPzPP:
25830 case AArch64::ORN_PPzPP:
25831 case AArch64::ORRS_PPzPP:
25832 case AArch64::ORR_PPzPP:
25833 case AArch64::SEL_PPPP: {
25834 switch (OpNum) {
25835 case 0:
25836 // op: Pd
25837 return 0;
25838 case 1:
25839 // op: Pg
25840 return 10;
25841 case 3:
25842 // op: Pm
25843 return 16;
25844 case 2:
25845 // op: Pn
25846 return 5;
25847 }
25848 break;
25849 }
25850 case AArch64::CMPEQ_PPzZZ_B:
25851 case AArch64::CMPEQ_PPzZZ_D:
25852 case AArch64::CMPEQ_PPzZZ_H:
25853 case AArch64::CMPEQ_PPzZZ_S:
25854 case AArch64::CMPEQ_WIDE_PPzZZ_B:
25855 case AArch64::CMPEQ_WIDE_PPzZZ_H:
25856 case AArch64::CMPEQ_WIDE_PPzZZ_S:
25857 case AArch64::CMPGE_PPzZZ_B:
25858 case AArch64::CMPGE_PPzZZ_D:
25859 case AArch64::CMPGE_PPzZZ_H:
25860 case AArch64::CMPGE_PPzZZ_S:
25861 case AArch64::CMPGE_WIDE_PPzZZ_B:
25862 case AArch64::CMPGE_WIDE_PPzZZ_H:
25863 case AArch64::CMPGE_WIDE_PPzZZ_S:
25864 case AArch64::CMPGT_PPzZZ_B:
25865 case AArch64::CMPGT_PPzZZ_D:
25866 case AArch64::CMPGT_PPzZZ_H:
25867 case AArch64::CMPGT_PPzZZ_S:
25868 case AArch64::CMPGT_WIDE_PPzZZ_B:
25869 case AArch64::CMPGT_WIDE_PPzZZ_H:
25870 case AArch64::CMPGT_WIDE_PPzZZ_S:
25871 case AArch64::CMPHI_PPzZZ_B:
25872 case AArch64::CMPHI_PPzZZ_D:
25873 case AArch64::CMPHI_PPzZZ_H:
25874 case AArch64::CMPHI_PPzZZ_S:
25875 case AArch64::CMPHI_WIDE_PPzZZ_B:
25876 case AArch64::CMPHI_WIDE_PPzZZ_H:
25877 case AArch64::CMPHI_WIDE_PPzZZ_S:
25878 case AArch64::CMPHS_PPzZZ_B:
25879 case AArch64::CMPHS_PPzZZ_D:
25880 case AArch64::CMPHS_PPzZZ_H:
25881 case AArch64::CMPHS_PPzZZ_S:
25882 case AArch64::CMPHS_WIDE_PPzZZ_B:
25883 case AArch64::CMPHS_WIDE_PPzZZ_H:
25884 case AArch64::CMPHS_WIDE_PPzZZ_S:
25885 case AArch64::CMPLE_WIDE_PPzZZ_B:
25886 case AArch64::CMPLE_WIDE_PPzZZ_H:
25887 case AArch64::CMPLE_WIDE_PPzZZ_S:
25888 case AArch64::CMPLO_WIDE_PPzZZ_B:
25889 case AArch64::CMPLO_WIDE_PPzZZ_H:
25890 case AArch64::CMPLO_WIDE_PPzZZ_S:
25891 case AArch64::CMPLS_WIDE_PPzZZ_B:
25892 case AArch64::CMPLS_WIDE_PPzZZ_H:
25893 case AArch64::CMPLS_WIDE_PPzZZ_S:
25894 case AArch64::CMPLT_WIDE_PPzZZ_B:
25895 case AArch64::CMPLT_WIDE_PPzZZ_H:
25896 case AArch64::CMPLT_WIDE_PPzZZ_S:
25897 case AArch64::CMPNE_PPzZZ_B:
25898 case AArch64::CMPNE_PPzZZ_D:
25899 case AArch64::CMPNE_PPzZZ_H:
25900 case AArch64::CMPNE_PPzZZ_S:
25901 case AArch64::CMPNE_WIDE_PPzZZ_B:
25902 case AArch64::CMPNE_WIDE_PPzZZ_H:
25903 case AArch64::CMPNE_WIDE_PPzZZ_S:
25904 case AArch64::FACGE_PPzZZ_D:
25905 case AArch64::FACGE_PPzZZ_H:
25906 case AArch64::FACGE_PPzZZ_S:
25907 case AArch64::FACGT_PPzZZ_D:
25908 case AArch64::FACGT_PPzZZ_H:
25909 case AArch64::FACGT_PPzZZ_S:
25910 case AArch64::FCMEQ_PPzZZ_D:
25911 case AArch64::FCMEQ_PPzZZ_H:
25912 case AArch64::FCMEQ_PPzZZ_S:
25913 case AArch64::FCMGE_PPzZZ_D:
25914 case AArch64::FCMGE_PPzZZ_H:
25915 case AArch64::FCMGE_PPzZZ_S:
25916 case AArch64::FCMGT_PPzZZ_D:
25917 case AArch64::FCMGT_PPzZZ_H:
25918 case AArch64::FCMGT_PPzZZ_S:
25919 case AArch64::FCMNE_PPzZZ_D:
25920 case AArch64::FCMNE_PPzZZ_H:
25921 case AArch64::FCMNE_PPzZZ_S:
25922 case AArch64::FCMUO_PPzZZ_D:
25923 case AArch64::FCMUO_PPzZZ_H:
25924 case AArch64::FCMUO_PPzZZ_S:
25925 case AArch64::MATCH_PPzZZ_B:
25926 case AArch64::MATCH_PPzZZ_H:
25927 case AArch64::NMATCH_PPzZZ_B:
25928 case AArch64::NMATCH_PPzZZ_H: {
25929 switch (OpNum) {
25930 case 0:
25931 // op: Pd
25932 return 0;
25933 case 1:
25934 // op: Pg
25935 return 10;
25936 case 3:
25937 // op: Zm
25938 return 16;
25939 case 2:
25940 // op: Zn
25941 return 5;
25942 }
25943 break;
25944 }
25945 case AArch64::RDFFRS_PPz:
25946 case AArch64::RDFFR_PPz: {
25947 switch (OpNum) {
25948 case 0:
25949 // op: Pd
25950 return 0;
25951 case 1:
25952 // op: Pg
25953 return 5;
25954 }
25955 break;
25956 }
25957 case AArch64::PUNPKHI_PP:
25958 case AArch64::PUNPKLO_PP:
25959 case AArch64::REV_PP_B:
25960 case AArch64::REV_PP_D:
25961 case AArch64::REV_PP_H:
25962 case AArch64::REV_PP_S: {
25963 switch (OpNum) {
25964 case 0:
25965 // op: Pd
25966 return 0;
25967 case 1:
25968 // op: Pn
25969 return 5;
25970 }
25971 break;
25972 }
25973 case AArch64::PMOV_PZI_D:
25974 case AArch64::PMOV_PZI_H:
25975 case AArch64::PMOV_PZI_S: {
25976 switch (OpNum) {
25977 case 0:
25978 // op: Pd
25979 return 0;
25980 case 1:
25981 // op: Zn
25982 return 5;
25983 case 2:
25984 // op: index
25985 return 17;
25986 }
25987 break;
25988 }
25989 case AArch64::PMOV_PZI_B: {
25990 switch (OpNum) {
25991 case 0:
25992 // op: Pd
25993 return 0;
25994 case 1:
25995 // op: Zn
25996 return 5;
25997 }
25998 break;
25999 }
26000 case AArch64::PTRUES_B:
26001 case AArch64::PTRUES_D:
26002 case AArch64::PTRUES_H:
26003 case AArch64::PTRUES_S:
26004 case AArch64::PTRUE_B:
26005 case AArch64::PTRUE_D:
26006 case AArch64::PTRUE_H:
26007 case AArch64::PTRUE_S: {
26008 switch (OpNum) {
26009 case 0:
26010 // op: Pd
26011 return 0;
26012 case 1:
26013 // op: pattern
26014 return 5;
26015 }
26016 break;
26017 }
26018 case AArch64::BRKA_PPmP:
26019 case AArch64::BRKB_PPmP: {
26020 switch (OpNum) {
26021 case 0:
26022 // op: Pd
26023 return 0;
26024 case 2:
26025 // op: Pg
26026 return 10;
26027 case 3:
26028 // op: Pn
26029 return 5;
26030 }
26031 break;
26032 }
26033 case AArch64::TRN1_PPP_B:
26034 case AArch64::TRN1_PPP_D:
26035 case AArch64::TRN1_PPP_H:
26036 case AArch64::TRN1_PPP_S:
26037 case AArch64::TRN2_PPP_B:
26038 case AArch64::TRN2_PPP_D:
26039 case AArch64::TRN2_PPP_H:
26040 case AArch64::TRN2_PPP_S:
26041 case AArch64::UZP1_PPP_B:
26042 case AArch64::UZP1_PPP_D:
26043 case AArch64::UZP1_PPP_H:
26044 case AArch64::UZP1_PPP_S:
26045 case AArch64::UZP2_PPP_B:
26046 case AArch64::UZP2_PPP_D:
26047 case AArch64::UZP2_PPP_H:
26048 case AArch64::UZP2_PPP_S:
26049 case AArch64::ZIP1_PPP_B:
26050 case AArch64::ZIP1_PPP_D:
26051 case AArch64::ZIP1_PPP_H:
26052 case AArch64::ZIP1_PPP_S:
26053 case AArch64::ZIP2_PPP_B:
26054 case AArch64::ZIP2_PPP_D:
26055 case AArch64::ZIP2_PPP_H:
26056 case AArch64::ZIP2_PPP_S: {
26057 switch (OpNum) {
26058 case 0:
26059 // op: Pd
26060 return 0;
26061 case 2:
26062 // op: Pm
26063 return 16;
26064 case 1:
26065 // op: Pn
26066 return 5;
26067 }
26068 break;
26069 }
26070 case AArch64::WHILEGE_PWW_B:
26071 case AArch64::WHILEGE_PWW_D:
26072 case AArch64::WHILEGE_PWW_H:
26073 case AArch64::WHILEGE_PWW_S:
26074 case AArch64::WHILEGE_PXX_B:
26075 case AArch64::WHILEGE_PXX_D:
26076 case AArch64::WHILEGE_PXX_H:
26077 case AArch64::WHILEGE_PXX_S:
26078 case AArch64::WHILEGT_PWW_B:
26079 case AArch64::WHILEGT_PWW_D:
26080 case AArch64::WHILEGT_PWW_H:
26081 case AArch64::WHILEGT_PWW_S:
26082 case AArch64::WHILEGT_PXX_B:
26083 case AArch64::WHILEGT_PXX_D:
26084 case AArch64::WHILEGT_PXX_H:
26085 case AArch64::WHILEGT_PXX_S:
26086 case AArch64::WHILEHI_PWW_B:
26087 case AArch64::WHILEHI_PWW_D:
26088 case AArch64::WHILEHI_PWW_H:
26089 case AArch64::WHILEHI_PWW_S:
26090 case AArch64::WHILEHI_PXX_B:
26091 case AArch64::WHILEHI_PXX_D:
26092 case AArch64::WHILEHI_PXX_H:
26093 case AArch64::WHILEHI_PXX_S:
26094 case AArch64::WHILEHS_PWW_B:
26095 case AArch64::WHILEHS_PWW_D:
26096 case AArch64::WHILEHS_PWW_H:
26097 case AArch64::WHILEHS_PWW_S:
26098 case AArch64::WHILEHS_PXX_B:
26099 case AArch64::WHILEHS_PXX_D:
26100 case AArch64::WHILEHS_PXX_H:
26101 case AArch64::WHILEHS_PXX_S:
26102 case AArch64::WHILELE_PWW_B:
26103 case AArch64::WHILELE_PWW_D:
26104 case AArch64::WHILELE_PWW_H:
26105 case AArch64::WHILELE_PWW_S:
26106 case AArch64::WHILELE_PXX_B:
26107 case AArch64::WHILELE_PXX_D:
26108 case AArch64::WHILELE_PXX_H:
26109 case AArch64::WHILELE_PXX_S:
26110 case AArch64::WHILELO_PWW_B:
26111 case AArch64::WHILELO_PWW_D:
26112 case AArch64::WHILELO_PWW_H:
26113 case AArch64::WHILELO_PWW_S:
26114 case AArch64::WHILELO_PXX_B:
26115 case AArch64::WHILELO_PXX_D:
26116 case AArch64::WHILELO_PXX_H:
26117 case AArch64::WHILELO_PXX_S:
26118 case AArch64::WHILELS_PWW_B:
26119 case AArch64::WHILELS_PWW_D:
26120 case AArch64::WHILELS_PWW_H:
26121 case AArch64::WHILELS_PWW_S:
26122 case AArch64::WHILELS_PXX_B:
26123 case AArch64::WHILELS_PXX_D:
26124 case AArch64::WHILELS_PXX_H:
26125 case AArch64::WHILELS_PXX_S:
26126 case AArch64::WHILELT_PWW_B:
26127 case AArch64::WHILELT_PWW_D:
26128 case AArch64::WHILELT_PWW_H:
26129 case AArch64::WHILELT_PWW_S:
26130 case AArch64::WHILELT_PXX_B:
26131 case AArch64::WHILELT_PXX_D:
26132 case AArch64::WHILELT_PXX_H:
26133 case AArch64::WHILELT_PXX_S:
26134 case AArch64::WHILERW_PXX_B:
26135 case AArch64::WHILERW_PXX_D:
26136 case AArch64::WHILERW_PXX_H:
26137 case AArch64::WHILERW_PXX_S:
26138 case AArch64::WHILEWR_PXX_B:
26139 case AArch64::WHILEWR_PXX_D:
26140 case AArch64::WHILEWR_PXX_H:
26141 case AArch64::WHILEWR_PXX_S: {
26142 switch (OpNum) {
26143 case 0:
26144 // op: Pd
26145 return 0;
26146 case 2:
26147 // op: Rm
26148 return 16;
26149 case 1:
26150 // op: Rn
26151 return 5;
26152 }
26153 break;
26154 }
26155 case AArch64::PFALSE:
26156 case AArch64::RDFFR_P: {
26157 switch (OpNum) {
26158 case 0:
26159 // op: Pd
26160 return 0;
26161 }
26162 break;
26163 }
26164 case AArch64::WHILEGE_2PXX_B:
26165 case AArch64::WHILEGE_2PXX_D:
26166 case AArch64::WHILEGE_2PXX_H:
26167 case AArch64::WHILEGE_2PXX_S:
26168 case AArch64::WHILEGT_2PXX_B:
26169 case AArch64::WHILEGT_2PXX_D:
26170 case AArch64::WHILEGT_2PXX_H:
26171 case AArch64::WHILEGT_2PXX_S:
26172 case AArch64::WHILEHI_2PXX_B:
26173 case AArch64::WHILEHI_2PXX_D:
26174 case AArch64::WHILEHI_2PXX_H:
26175 case AArch64::WHILEHI_2PXX_S:
26176 case AArch64::WHILEHS_2PXX_B:
26177 case AArch64::WHILEHS_2PXX_D:
26178 case AArch64::WHILEHS_2PXX_H:
26179 case AArch64::WHILEHS_2PXX_S:
26180 case AArch64::WHILELE_2PXX_B:
26181 case AArch64::WHILELE_2PXX_D:
26182 case AArch64::WHILELE_2PXX_H:
26183 case AArch64::WHILELE_2PXX_S:
26184 case AArch64::WHILELO_2PXX_B:
26185 case AArch64::WHILELO_2PXX_D:
26186 case AArch64::WHILELO_2PXX_H:
26187 case AArch64::WHILELO_2PXX_S:
26188 case AArch64::WHILELS_2PXX_B:
26189 case AArch64::WHILELS_2PXX_D:
26190 case AArch64::WHILELS_2PXX_H:
26191 case AArch64::WHILELS_2PXX_S:
26192 case AArch64::WHILELT_2PXX_B:
26193 case AArch64::WHILELT_2PXX_D:
26194 case AArch64::WHILELT_2PXX_H:
26195 case AArch64::WHILELT_2PXX_S: {
26196 switch (OpNum) {
26197 case 0:
26198 // op: Pd
26199 return 1;
26200 case 1:
26201 // op: Rn
26202 return 5;
26203 case 2:
26204 // op: Rm
26205 return 16;
26206 }
26207 break;
26208 }
26209 case AArch64::BRKNS_PPzP:
26210 case AArch64::BRKN_PPzP: {
26211 switch (OpNum) {
26212 case 0:
26213 // op: Pdm
26214 return 0;
26215 case 1:
26216 // op: Pg
26217 return 10;
26218 case 2:
26219 // op: Pn
26220 return 5;
26221 }
26222 break;
26223 }
26224 case AArch64::PFIRST_B:
26225 case AArch64::PNEXT_B:
26226 case AArch64::PNEXT_D:
26227 case AArch64::PNEXT_H:
26228 case AArch64::PNEXT_S: {
26229 switch (OpNum) {
26230 case 0:
26231 // op: Pdn
26232 return 0;
26233 case 1:
26234 // op: Pg
26235 return 5;
26236 }
26237 break;
26238 }
26239 case AArch64::PTEST_PP: {
26240 switch (OpNum) {
26241 case 0:
26242 // op: Pg
26243 return 10;
26244 case 1:
26245 // op: Pn
26246 return 5;
26247 }
26248 break;
26249 }
26250 case AArch64::WRFFR: {
26251 switch (OpNum) {
26252 case 0:
26253 // op: Pn
26254 return 5;
26255 }
26256 break;
26257 }
26258 case AArch64::LDR_PXI:
26259 case AArch64::STR_PXI: {
26260 switch (OpNum) {
26261 case 0:
26262 // op: Pt
26263 return 0;
26264 case 1:
26265 // op: Rn
26266 return 5;
26267 case 2:
26268 // op: imm9
26269 return 10;
26270 }
26271 break;
26272 }
26273 case AArch64::CNTP_XCI_B:
26274 case AArch64::CNTP_XCI_D:
26275 case AArch64::CNTP_XCI_H:
26276 case AArch64::CNTP_XCI_S: {
26277 switch (OpNum) {
26278 case 0:
26279 // op: Rd
26280 return 0;
26281 case 1:
26282 // op: PNn
26283 return 5;
26284 case 2:
26285 // op: vl
26286 return 10;
26287 }
26288 break;
26289 }
26290 case AArch64::ADDPL_XXI:
26291 case AArch64::ADDSPL_XXI:
26292 case AArch64::ADDSVL_XXI:
26293 case AArch64::ADDVL_XXI: {
26294 switch (OpNum) {
26295 case 0:
26296 // op: Rd
26297 return 0;
26298 case 1:
26299 // op: Rn
26300 return 16;
26301 case 2:
26302 // op: imm6
26303 return 5;
26304 }
26305 break;
26306 }
26307 case AArch64::FMADDDrrr:
26308 case AArch64::FMADDHrrr:
26309 case AArch64::FMADDSrrr:
26310 case AArch64::FMSUBDrrr:
26311 case AArch64::FMSUBHrrr:
26312 case AArch64::FMSUBSrrr:
26313 case AArch64::FNMADDDrrr:
26314 case AArch64::FNMADDHrrr:
26315 case AArch64::FNMADDSrrr:
26316 case AArch64::FNMSUBDrrr:
26317 case AArch64::FNMSUBHrrr:
26318 case AArch64::FNMSUBSrrr:
26319 case AArch64::MADDPT:
26320 case AArch64::MADDWrrr:
26321 case AArch64::MADDXrrr:
26322 case AArch64::MSUBPT:
26323 case AArch64::MSUBWrrr:
26324 case AArch64::MSUBXrrr:
26325 case AArch64::SMADDLrrr:
26326 case AArch64::SMSUBLrrr:
26327 case AArch64::UMADDLrrr:
26328 case AArch64::UMSUBLrrr: {
26329 switch (OpNum) {
26330 case 0:
26331 // op: Rd
26332 return 0;
26333 case 1:
26334 // op: Rn
26335 return 5;
26336 case 2:
26337 // op: Rm
26338 return 16;
26339 case 3:
26340 // op: Ra
26341 return 10;
26342 }
26343 break;
26344 }
26345 case AArch64::CSELWr:
26346 case AArch64::CSELXr:
26347 case AArch64::CSINCWr:
26348 case AArch64::CSINCXr:
26349 case AArch64::CSINVWr:
26350 case AArch64::CSINVXr:
26351 case AArch64::CSNEGWr:
26352 case AArch64::CSNEGXr:
26353 case AArch64::FCSELDrrr:
26354 case AArch64::FCSELHrrr:
26355 case AArch64::FCSELSrrr: {
26356 switch (OpNum) {
26357 case 0:
26358 // op: Rd
26359 return 0;
26360 case 1:
26361 // op: Rn
26362 return 5;
26363 case 2:
26364 // op: Rm
26365 return 16;
26366 case 3:
26367 // op: cond
26368 return 12;
26369 }
26370 break;
26371 }
26372 case AArch64::ADDSXrx64:
26373 case AArch64::ADDXrx64:
26374 case AArch64::SUBSXrx64:
26375 case AArch64::SUBXrx64: {
26376 switch (OpNum) {
26377 case 0:
26378 // op: Rd
26379 return 0;
26380 case 1:
26381 // op: Rn
26382 return 5;
26383 case 2:
26384 // op: Rm
26385 return 16;
26386 case 3:
26387 // op: ext
26388 return 10;
26389 }
26390 break;
26391 }
26392 case AArch64::ADDSWrx:
26393 case AArch64::ADDSXrx:
26394 case AArch64::ADDWrx:
26395 case AArch64::ADDXrx:
26396 case AArch64::SUBSWrx:
26397 case AArch64::SUBSXrx:
26398 case AArch64::SUBWrx:
26399 case AArch64::SUBXrx: {
26400 switch (OpNum) {
26401 case 0:
26402 // op: Rd
26403 return 0;
26404 case 1:
26405 // op: Rn
26406 return 5;
26407 case 2:
26408 // op: Rm
26409 return 16;
26410 case 3:
26411 // op: extend
26412 return 10;
26413 }
26414 break;
26415 }
26416 case AArch64::FMULXv1i16_indexed:
26417 case AArch64::FMULXv1i32_indexed:
26418 case AArch64::FMULXv1i64_indexed:
26419 case AArch64::FMULXv2i32_indexed:
26420 case AArch64::FMULXv2i64_indexed:
26421 case AArch64::FMULXv4i16_indexed:
26422 case AArch64::FMULXv4i32_indexed:
26423 case AArch64::FMULXv8i16_indexed:
26424 case AArch64::FMULv1i16_indexed:
26425 case AArch64::FMULv1i32_indexed:
26426 case AArch64::FMULv1i64_indexed:
26427 case AArch64::FMULv2i32_indexed:
26428 case AArch64::FMULv2i64_indexed:
26429 case AArch64::FMULv4i16_indexed:
26430 case AArch64::FMULv4i32_indexed:
26431 case AArch64::FMULv8i16_indexed:
26432 case AArch64::MULv2i32_indexed:
26433 case AArch64::MULv4i16_indexed:
26434 case AArch64::MULv4i32_indexed:
26435 case AArch64::MULv8i16_indexed:
26436 case AArch64::SMULLv2i32_indexed:
26437 case AArch64::SMULLv4i16_indexed:
26438 case AArch64::SMULLv4i32_indexed:
26439 case AArch64::SMULLv8i16_indexed:
26440 case AArch64::SQDMULHv1i16_indexed:
26441 case AArch64::SQDMULHv1i32_indexed:
26442 case AArch64::SQDMULHv2i32_indexed:
26443 case AArch64::SQDMULHv4i16_indexed:
26444 case AArch64::SQDMULHv4i32_indexed:
26445 case AArch64::SQDMULHv8i16_indexed:
26446 case AArch64::SQDMULLv1i32_indexed:
26447 case AArch64::SQDMULLv1i64_indexed:
26448 case AArch64::SQDMULLv2i32_indexed:
26449 case AArch64::SQDMULLv4i16_indexed:
26450 case AArch64::SQDMULLv4i32_indexed:
26451 case AArch64::SQDMULLv8i16_indexed:
26452 case AArch64::SQRDMULHv1i16_indexed:
26453 case AArch64::SQRDMULHv1i32_indexed:
26454 case AArch64::SQRDMULHv2i32_indexed:
26455 case AArch64::SQRDMULHv4i16_indexed:
26456 case AArch64::SQRDMULHv4i32_indexed:
26457 case AArch64::SQRDMULHv8i16_indexed:
26458 case AArch64::UMULLv2i32_indexed:
26459 case AArch64::UMULLv4i16_indexed:
26460 case AArch64::UMULLv4i32_indexed:
26461 case AArch64::UMULLv8i16_indexed: {
26462 switch (OpNum) {
26463 case 0:
26464 // op: Rd
26465 return 0;
26466 case 1:
26467 // op: Rn
26468 return 5;
26469 case 2:
26470 // op: Rm
26471 return 16;
26472 case 3:
26473 // op: idx
26474 return 11;
26475 }
26476 break;
26477 }
26478 case AArch64::LUT2_H: {
26479 switch (OpNum) {
26480 case 0:
26481 // op: Rd
26482 return 0;
26483 case 1:
26484 // op: Rn
26485 return 5;
26486 case 2:
26487 // op: Rm
26488 return 16;
26489 case 3:
26490 // op: idx
26491 return 12;
26492 }
26493 break;
26494 }
26495 case AArch64::LUT2_B:
26496 case AArch64::LUT4_H: {
26497 switch (OpNum) {
26498 case 0:
26499 // op: Rd
26500 return 0;
26501 case 1:
26502 // op: Rn
26503 return 5;
26504 case 2:
26505 // op: Rm
26506 return 16;
26507 case 3:
26508 // op: idx
26509 return 13;
26510 }
26511 break;
26512 }
26513 case AArch64::LUT4_B: {
26514 switch (OpNum) {
26515 case 0:
26516 // op: Rd
26517 return 0;
26518 case 1:
26519 // op: Rn
26520 return 5;
26521 case 2:
26522 // op: Rm
26523 return 16;
26524 case 3:
26525 // op: idx
26526 return 14;
26527 }
26528 break;
26529 }
26530 case AArch64::EXTRWrri:
26531 case AArch64::EXTRXrri: {
26532 switch (OpNum) {
26533 case 0:
26534 // op: Rd
26535 return 0;
26536 case 1:
26537 // op: Rn
26538 return 5;
26539 case 2:
26540 // op: Rm
26541 return 16;
26542 case 3:
26543 // op: imm
26544 return 10;
26545 }
26546 break;
26547 }
26548 case AArch64::EXTv8i8:
26549 case AArch64::EXTv16i8: {
26550 switch (OpNum) {
26551 case 0:
26552 // op: Rd
26553 return 0;
26554 case 1:
26555 // op: Rn
26556 return 5;
26557 case 2:
26558 // op: Rm
26559 return 16;
26560 case 3:
26561 // op: imm
26562 return 11;
26563 }
26564 break;
26565 }
26566 case AArch64::FCADDv2f32:
26567 case AArch64::FCADDv2f64:
26568 case AArch64::FCADDv4f16:
26569 case AArch64::FCADDv4f32:
26570 case AArch64::FCADDv8f16: {
26571 switch (OpNum) {
26572 case 0:
26573 // op: Rd
26574 return 0;
26575 case 1:
26576 // op: Rn
26577 return 5;
26578 case 2:
26579 // op: Rm
26580 return 16;
26581 case 3:
26582 // op: rot
26583 return 12;
26584 }
26585 break;
26586 }
26587 case AArch64::ADDSWrs:
26588 case AArch64::ADDSXrs:
26589 case AArch64::ADDWrs:
26590 case AArch64::ADDXrs:
26591 case AArch64::ANDSWrs:
26592 case AArch64::ANDSXrs:
26593 case AArch64::ANDWrs:
26594 case AArch64::ANDXrs:
26595 case AArch64::BICSWrs:
26596 case AArch64::BICSXrs:
26597 case AArch64::BICWrs:
26598 case AArch64::BICXrs:
26599 case AArch64::EONWrs:
26600 case AArch64::EONXrs:
26601 case AArch64::EORWrs:
26602 case AArch64::EORXrs:
26603 case AArch64::ORNWrs:
26604 case AArch64::ORNXrs:
26605 case AArch64::ORRWrs:
26606 case AArch64::ORRXrs:
26607 case AArch64::SUBSWrs:
26608 case AArch64::SUBSXrs:
26609 case AArch64::SUBWrs:
26610 case AArch64::SUBXrs: {
26611 switch (OpNum) {
26612 case 0:
26613 // op: Rd
26614 return 0;
26615 case 1:
26616 // op: Rn
26617 return 5;
26618 case 2:
26619 // op: Rm
26620 return 16;
26621 case 3:
26622 // op: shift
26623 return 10;
26624 }
26625 break;
26626 }
26627 case AArch64::ADDPT_shift:
26628 case AArch64::SUBPT_shift: {
26629 switch (OpNum) {
26630 case 0:
26631 // op: Rd
26632 return 0;
26633 case 1:
26634 // op: Rn
26635 return 5;
26636 case 2:
26637 // op: Rm
26638 return 16;
26639 case 3:
26640 // op: shift_imm
26641 return 10;
26642 }
26643 break;
26644 }
26645 case AArch64::ADCSWr:
26646 case AArch64::ADCSXr:
26647 case AArch64::ADCWr:
26648 case AArch64::ADCXr:
26649 case AArch64::ADDHNv2i64_v2i32:
26650 case AArch64::ADDHNv4i32_v4i16:
26651 case AArch64::ADDHNv8i16_v8i8:
26652 case AArch64::ADDPv2i32:
26653 case AArch64::ADDPv2i64:
26654 case AArch64::ADDPv4i16:
26655 case AArch64::ADDPv4i32:
26656 case AArch64::ADDPv8i8:
26657 case AArch64::ADDPv8i16:
26658 case AArch64::ADDPv16i8:
26659 case AArch64::ADDv1i64:
26660 case AArch64::ADDv2i32:
26661 case AArch64::ADDv2i64:
26662 case AArch64::ADDv4i16:
26663 case AArch64::ADDv4i32:
26664 case AArch64::ADDv8i8:
26665 case AArch64::ADDv8i16:
26666 case AArch64::ADDv16i8:
26667 case AArch64::ANDv8i8:
26668 case AArch64::ANDv16i8:
26669 case AArch64::ASRVWr:
26670 case AArch64::ASRVXr:
26671 case AArch64::BICv8i8:
26672 case AArch64::BICv16i8:
26673 case AArch64::CMEQv1i64:
26674 case AArch64::CMEQv2i32:
26675 case AArch64::CMEQv2i64:
26676 case AArch64::CMEQv4i16:
26677 case AArch64::CMEQv4i32:
26678 case AArch64::CMEQv8i8:
26679 case AArch64::CMEQv8i16:
26680 case AArch64::CMEQv16i8:
26681 case AArch64::CMGEv1i64:
26682 case AArch64::CMGEv2i32:
26683 case AArch64::CMGEv2i64:
26684 case AArch64::CMGEv4i16:
26685 case AArch64::CMGEv4i32:
26686 case AArch64::CMGEv8i8:
26687 case AArch64::CMGEv8i16:
26688 case AArch64::CMGEv16i8:
26689 case AArch64::CMGTv1i64:
26690 case AArch64::CMGTv2i32:
26691 case AArch64::CMGTv2i64:
26692 case AArch64::CMGTv4i16:
26693 case AArch64::CMGTv4i32:
26694 case AArch64::CMGTv8i8:
26695 case AArch64::CMGTv8i16:
26696 case AArch64::CMGTv16i8:
26697 case AArch64::CMHIv1i64:
26698 case AArch64::CMHIv2i32:
26699 case AArch64::CMHIv2i64:
26700 case AArch64::CMHIv4i16:
26701 case AArch64::CMHIv4i32:
26702 case AArch64::CMHIv8i8:
26703 case AArch64::CMHIv8i16:
26704 case AArch64::CMHIv16i8:
26705 case AArch64::CMHSv1i64:
26706 case AArch64::CMHSv2i32:
26707 case AArch64::CMHSv2i64:
26708 case AArch64::CMHSv4i16:
26709 case AArch64::CMHSv4i32:
26710 case AArch64::CMHSv8i8:
26711 case AArch64::CMHSv8i16:
26712 case AArch64::CMHSv16i8:
26713 case AArch64::CMTSTv1i64:
26714 case AArch64::CMTSTv2i32:
26715 case AArch64::CMTSTv2i64:
26716 case AArch64::CMTSTv4i16:
26717 case AArch64::CMTSTv4i32:
26718 case AArch64::CMTSTv8i8:
26719 case AArch64::CMTSTv8i16:
26720 case AArch64::CMTSTv16i8:
26721 case AArch64::CRC32Brr:
26722 case AArch64::CRC32CBrr:
26723 case AArch64::CRC32CHrr:
26724 case AArch64::CRC32CWrr:
26725 case AArch64::CRC32CXrr:
26726 case AArch64::CRC32Hrr:
26727 case AArch64::CRC32Wrr:
26728 case AArch64::CRC32Xrr:
26729 case AArch64::EORv8i8:
26730 case AArch64::EORv16i8:
26731 case AArch64::FABD16:
26732 case AArch64::FABD32:
26733 case AArch64::FABD64:
26734 case AArch64::FABDv2f32:
26735 case AArch64::FABDv2f64:
26736 case AArch64::FABDv4f16:
26737 case AArch64::FABDv4f32:
26738 case AArch64::FABDv8f16:
26739 case AArch64::FACGE16:
26740 case AArch64::FACGE32:
26741 case AArch64::FACGE64:
26742 case AArch64::FACGEv2f32:
26743 case AArch64::FACGEv2f64:
26744 case AArch64::FACGEv4f16:
26745 case AArch64::FACGEv4f32:
26746 case AArch64::FACGEv8f16:
26747 case AArch64::FACGT16:
26748 case AArch64::FACGT32:
26749 case AArch64::FACGT64:
26750 case AArch64::FACGTv2f32:
26751 case AArch64::FACGTv2f64:
26752 case AArch64::FACGTv4f16:
26753 case AArch64::FACGTv4f32:
26754 case AArch64::FACGTv8f16:
26755 case AArch64::FADDDrr:
26756 case AArch64::FADDHrr:
26757 case AArch64::FADDPv2f32:
26758 case AArch64::FADDPv2f64:
26759 case AArch64::FADDPv4f16:
26760 case AArch64::FADDPv4f32:
26761 case AArch64::FADDPv8f16:
26762 case AArch64::FADDSrr:
26763 case AArch64::FADDv2f32:
26764 case AArch64::FADDv2f64:
26765 case AArch64::FADDv4f16:
26766 case AArch64::FADDv4f32:
26767 case AArch64::FADDv8f16:
26768 case AArch64::FAMAXv2f32:
26769 case AArch64::FAMAXv2f64:
26770 case AArch64::FAMAXv4f16:
26771 case AArch64::FAMAXv4f32:
26772 case AArch64::FAMAXv8f16:
26773 case AArch64::FAMINv2f32:
26774 case AArch64::FAMINv2f64:
26775 case AArch64::FAMINv4f16:
26776 case AArch64::FAMINv4f32:
26777 case AArch64::FAMINv8f16:
26778 case AArch64::FCMEQ16:
26779 case AArch64::FCMEQ32:
26780 case AArch64::FCMEQ64:
26781 case AArch64::FCMEQv2f32:
26782 case AArch64::FCMEQv2f64:
26783 case AArch64::FCMEQv4f16:
26784 case AArch64::FCMEQv4f32:
26785 case AArch64::FCMEQv8f16:
26786 case AArch64::FCMGE16:
26787 case AArch64::FCMGE32:
26788 case AArch64::FCMGE64:
26789 case AArch64::FCMGEv2f32:
26790 case AArch64::FCMGEv2f64:
26791 case AArch64::FCMGEv4f16:
26792 case AArch64::FCMGEv4f32:
26793 case AArch64::FCMGEv8f16:
26794 case AArch64::FCMGT16:
26795 case AArch64::FCMGT32:
26796 case AArch64::FCMGT64:
26797 case AArch64::FCMGTv2f32:
26798 case AArch64::FCMGTv2f64:
26799 case AArch64::FCMGTv4f16:
26800 case AArch64::FCMGTv4f32:
26801 case AArch64::FCMGTv8f16:
26802 case AArch64::FCVTN_F16v8f8:
26803 case AArch64::FCVTN_F16v16f8:
26804 case AArch64::FCVTN_F32v8f8:
26805 case AArch64::FDIVDrr:
26806 case AArch64::FDIVHrr:
26807 case AArch64::FDIVSrr:
26808 case AArch64::FDIVv2f32:
26809 case AArch64::FDIVv2f64:
26810 case AArch64::FDIVv4f16:
26811 case AArch64::FDIVv4f32:
26812 case AArch64::FDIVv8f16:
26813 case AArch64::FMAXDrr:
26814 case AArch64::FMAXHrr:
26815 case AArch64::FMAXNMDrr:
26816 case AArch64::FMAXNMHrr:
26817 case AArch64::FMAXNMPv2f32:
26818 case AArch64::FMAXNMPv2f64:
26819 case AArch64::FMAXNMPv4f16:
26820 case AArch64::FMAXNMPv4f32:
26821 case AArch64::FMAXNMPv8f16:
26822 case AArch64::FMAXNMSrr:
26823 case AArch64::FMAXNMv2f32:
26824 case AArch64::FMAXNMv2f64:
26825 case AArch64::FMAXNMv4f16:
26826 case AArch64::FMAXNMv4f32:
26827 case AArch64::FMAXNMv8f16:
26828 case AArch64::FMAXPv2f32:
26829 case AArch64::FMAXPv2f64:
26830 case AArch64::FMAXPv4f16:
26831 case AArch64::FMAXPv4f32:
26832 case AArch64::FMAXPv8f16:
26833 case AArch64::FMAXSrr:
26834 case AArch64::FMAXv2f32:
26835 case AArch64::FMAXv2f64:
26836 case AArch64::FMAXv4f16:
26837 case AArch64::FMAXv4f32:
26838 case AArch64::FMAXv8f16:
26839 case AArch64::FMINDrr:
26840 case AArch64::FMINHrr:
26841 case AArch64::FMINNMDrr:
26842 case AArch64::FMINNMHrr:
26843 case AArch64::FMINNMPv2f32:
26844 case AArch64::FMINNMPv2f64:
26845 case AArch64::FMINNMPv4f16:
26846 case AArch64::FMINNMPv4f32:
26847 case AArch64::FMINNMPv8f16:
26848 case AArch64::FMINNMSrr:
26849 case AArch64::FMINNMv2f32:
26850 case AArch64::FMINNMv2f64:
26851 case AArch64::FMINNMv4f16:
26852 case AArch64::FMINNMv4f32:
26853 case AArch64::FMINNMv8f16:
26854 case AArch64::FMINPv2f32:
26855 case AArch64::FMINPv2f64:
26856 case AArch64::FMINPv4f16:
26857 case AArch64::FMINPv4f32:
26858 case AArch64::FMINPv8f16:
26859 case AArch64::FMINSrr:
26860 case AArch64::FMINv2f32:
26861 case AArch64::FMINv2f64:
26862 case AArch64::FMINv4f16:
26863 case AArch64::FMINv4f32:
26864 case AArch64::FMINv8f16:
26865 case AArch64::FMULDrr:
26866 case AArch64::FMULHrr:
26867 case AArch64::FMULSrr:
26868 case AArch64::FMULX16:
26869 case AArch64::FMULX32:
26870 case AArch64::FMULX64:
26871 case AArch64::FMULXv2f32:
26872 case AArch64::FMULXv2f64:
26873 case AArch64::FMULXv4f16:
26874 case AArch64::FMULXv4f32:
26875 case AArch64::FMULXv8f16:
26876 case AArch64::FMULv2f32:
26877 case AArch64::FMULv2f64:
26878 case AArch64::FMULv4f16:
26879 case AArch64::FMULv4f32:
26880 case AArch64::FMULv8f16:
26881 case AArch64::FNMULDrr:
26882 case AArch64::FNMULHrr:
26883 case AArch64::FNMULSrr:
26884 case AArch64::FRECPS16:
26885 case AArch64::FRECPS32:
26886 case AArch64::FRECPS64:
26887 case AArch64::FRECPSv2f32:
26888 case AArch64::FRECPSv2f64:
26889 case AArch64::FRECPSv4f16:
26890 case AArch64::FRECPSv4f32:
26891 case AArch64::FRECPSv8f16:
26892 case AArch64::FRSQRTS16:
26893 case AArch64::FRSQRTS32:
26894 case AArch64::FRSQRTS64:
26895 case AArch64::FRSQRTSv2f32:
26896 case AArch64::FRSQRTSv2f64:
26897 case AArch64::FRSQRTSv4f16:
26898 case AArch64::FRSQRTSv4f32:
26899 case AArch64::FRSQRTSv8f16:
26900 case AArch64::FSCALEv2f32:
26901 case AArch64::FSCALEv2f64:
26902 case AArch64::FSCALEv4f16:
26903 case AArch64::FSCALEv4f32:
26904 case AArch64::FSCALEv8f16:
26905 case AArch64::FSUBDrr:
26906 case AArch64::FSUBHrr:
26907 case AArch64::FSUBSrr:
26908 case AArch64::FSUBv2f32:
26909 case AArch64::FSUBv2f64:
26910 case AArch64::FSUBv4f16:
26911 case AArch64::FSUBv4f32:
26912 case AArch64::FSUBv8f16:
26913 case AArch64::GMI:
26914 case AArch64::IRG:
26915 case AArch64::LSLVWr:
26916 case AArch64::LSLVXr:
26917 case AArch64::LSRVWr:
26918 case AArch64::LSRVXr:
26919 case AArch64::MULv2i32:
26920 case AArch64::MULv4i16:
26921 case AArch64::MULv4i32:
26922 case AArch64::MULv8i8:
26923 case AArch64::MULv8i16:
26924 case AArch64::MULv16i8:
26925 case AArch64::ORNv8i8:
26926 case AArch64::ORNv16i8:
26927 case AArch64::ORRv8i8:
26928 case AArch64::ORRv16i8:
26929 case AArch64::PACGA:
26930 case AArch64::PMULLv1i64:
26931 case AArch64::PMULLv2i64:
26932 case AArch64::PMULLv8i8:
26933 case AArch64::PMULLv16i8:
26934 case AArch64::PMULv8i8:
26935 case AArch64::PMULv16i8:
26936 case AArch64::RADDHNv2i64_v2i32:
26937 case AArch64::RADDHNv4i32_v4i16:
26938 case AArch64::RADDHNv8i16_v8i8:
26939 case AArch64::RORVWr:
26940 case AArch64::RORVXr:
26941 case AArch64::RSUBHNv2i64_v2i32:
26942 case AArch64::RSUBHNv4i32_v4i16:
26943 case AArch64::RSUBHNv8i16_v8i8:
26944 case AArch64::SABDLv2i32_v2i64:
26945 case AArch64::SABDLv4i16_v4i32:
26946 case AArch64::SABDLv4i32_v2i64:
26947 case AArch64::SABDLv8i8_v8i16:
26948 case AArch64::SABDLv8i16_v4i32:
26949 case AArch64::SABDLv16i8_v8i16:
26950 case AArch64::SABDv2i32:
26951 case AArch64::SABDv4i16:
26952 case AArch64::SABDv4i32:
26953 case AArch64::SABDv8i8:
26954 case AArch64::SABDv8i16:
26955 case AArch64::SABDv16i8:
26956 case AArch64::SADDLv2i32_v2i64:
26957 case AArch64::SADDLv4i16_v4i32:
26958 case AArch64::SADDLv4i32_v2i64:
26959 case AArch64::SADDLv8i8_v8i16:
26960 case AArch64::SADDLv8i16_v4i32:
26961 case AArch64::SADDLv16i8_v8i16:
26962 case AArch64::SADDWv2i32_v2i64:
26963 case AArch64::SADDWv4i16_v4i32:
26964 case AArch64::SADDWv4i32_v2i64:
26965 case AArch64::SADDWv8i8_v8i16:
26966 case AArch64::SADDWv8i16_v4i32:
26967 case AArch64::SADDWv16i8_v8i16:
26968 case AArch64::SBCSWr:
26969 case AArch64::SBCSXr:
26970 case AArch64::SBCWr:
26971 case AArch64::SBCXr:
26972 case AArch64::SDIVWr:
26973 case AArch64::SDIVXr:
26974 case AArch64::SHADDv2i32:
26975 case AArch64::SHADDv4i16:
26976 case AArch64::SHADDv4i32:
26977 case AArch64::SHADDv8i8:
26978 case AArch64::SHADDv8i16:
26979 case AArch64::SHADDv16i8:
26980 case AArch64::SHSUBv2i32:
26981 case AArch64::SHSUBv4i16:
26982 case AArch64::SHSUBv4i32:
26983 case AArch64::SHSUBv8i8:
26984 case AArch64::SHSUBv8i16:
26985 case AArch64::SHSUBv16i8:
26986 case AArch64::SMAXPv2i32:
26987 case AArch64::SMAXPv4i16:
26988 case AArch64::SMAXPv4i32:
26989 case AArch64::SMAXPv8i8:
26990 case AArch64::SMAXPv8i16:
26991 case AArch64::SMAXPv16i8:
26992 case AArch64::SMAXWrr:
26993 case AArch64::SMAXXrr:
26994 case AArch64::SMAXv2i32:
26995 case AArch64::SMAXv4i16:
26996 case AArch64::SMAXv4i32:
26997 case AArch64::SMAXv8i8:
26998 case AArch64::SMAXv8i16:
26999 case AArch64::SMAXv16i8:
27000 case AArch64::SMINPv2i32:
27001 case AArch64::SMINPv4i16:
27002 case AArch64::SMINPv4i32:
27003 case AArch64::SMINPv8i8:
27004 case AArch64::SMINPv8i16:
27005 case AArch64::SMINPv16i8:
27006 case AArch64::SMINWrr:
27007 case AArch64::SMINXrr:
27008 case AArch64::SMINv2i32:
27009 case AArch64::SMINv4i16:
27010 case AArch64::SMINv4i32:
27011 case AArch64::SMINv8i8:
27012 case AArch64::SMINv8i16:
27013 case AArch64::SMINv16i8:
27014 case AArch64::SMULHrr:
27015 case AArch64::SMULLv2i32_v2i64:
27016 case AArch64::SMULLv4i16_v4i32:
27017 case AArch64::SMULLv4i32_v2i64:
27018 case AArch64::SMULLv8i8_v8i16:
27019 case AArch64::SMULLv8i16_v4i32:
27020 case AArch64::SMULLv16i8_v8i16:
27021 case AArch64::SQADDv1i8:
27022 case AArch64::SQADDv1i16:
27023 case AArch64::SQADDv1i32:
27024 case AArch64::SQADDv1i64:
27025 case AArch64::SQADDv2i32:
27026 case AArch64::SQADDv2i64:
27027 case AArch64::SQADDv4i16:
27028 case AArch64::SQADDv4i32:
27029 case AArch64::SQADDv8i8:
27030 case AArch64::SQADDv8i16:
27031 case AArch64::SQADDv16i8:
27032 case AArch64::SQDMULHv1i16:
27033 case AArch64::SQDMULHv1i32:
27034 case AArch64::SQDMULHv2i32:
27035 case AArch64::SQDMULHv4i16:
27036 case AArch64::SQDMULHv4i32:
27037 case AArch64::SQDMULHv8i16:
27038 case AArch64::SQDMULLi16:
27039 case AArch64::SQDMULLi32:
27040 case AArch64::SQDMULLv2i32_v2i64:
27041 case AArch64::SQDMULLv4i16_v4i32:
27042 case AArch64::SQDMULLv4i32_v2i64:
27043 case AArch64::SQDMULLv8i16_v4i32:
27044 case AArch64::SQRDMULHv1i16:
27045 case AArch64::SQRDMULHv1i32:
27046 case AArch64::SQRDMULHv2i32:
27047 case AArch64::SQRDMULHv4i16:
27048 case AArch64::SQRDMULHv4i32:
27049 case AArch64::SQRDMULHv8i16:
27050 case AArch64::SQRSHLv1i8:
27051 case AArch64::SQRSHLv1i16:
27052 case AArch64::SQRSHLv1i32:
27053 case AArch64::SQRSHLv1i64:
27054 case AArch64::SQRSHLv2i32:
27055 case AArch64::SQRSHLv2i64:
27056 case AArch64::SQRSHLv4i16:
27057 case AArch64::SQRSHLv4i32:
27058 case AArch64::SQRSHLv8i8:
27059 case AArch64::SQRSHLv8i16:
27060 case AArch64::SQRSHLv16i8:
27061 case AArch64::SQSHLv1i8:
27062 case AArch64::SQSHLv1i16:
27063 case AArch64::SQSHLv1i32:
27064 case AArch64::SQSHLv1i64:
27065 case AArch64::SQSHLv2i32:
27066 case AArch64::SQSHLv2i64:
27067 case AArch64::SQSHLv4i16:
27068 case AArch64::SQSHLv4i32:
27069 case AArch64::SQSHLv8i8:
27070 case AArch64::SQSHLv8i16:
27071 case AArch64::SQSHLv16i8:
27072 case AArch64::SQSUBv1i8:
27073 case AArch64::SQSUBv1i16:
27074 case AArch64::SQSUBv1i32:
27075 case AArch64::SQSUBv1i64:
27076 case AArch64::SQSUBv2i32:
27077 case AArch64::SQSUBv2i64:
27078 case AArch64::SQSUBv4i16:
27079 case AArch64::SQSUBv4i32:
27080 case AArch64::SQSUBv8i8:
27081 case AArch64::SQSUBv8i16:
27082 case AArch64::SQSUBv16i8:
27083 case AArch64::SRHADDv2i32:
27084 case AArch64::SRHADDv4i16:
27085 case AArch64::SRHADDv4i32:
27086 case AArch64::SRHADDv8i8:
27087 case AArch64::SRHADDv8i16:
27088 case AArch64::SRHADDv16i8:
27089 case AArch64::SRSHLv1i64:
27090 case AArch64::SRSHLv2i32:
27091 case AArch64::SRSHLv2i64:
27092 case AArch64::SRSHLv4i16:
27093 case AArch64::SRSHLv4i32:
27094 case AArch64::SRSHLv8i8:
27095 case AArch64::SRSHLv8i16:
27096 case AArch64::SRSHLv16i8:
27097 case AArch64::SSHLv1i64:
27098 case AArch64::SSHLv2i32:
27099 case AArch64::SSHLv2i64:
27100 case AArch64::SSHLv4i16:
27101 case AArch64::SSHLv4i32:
27102 case AArch64::SSHLv8i8:
27103 case AArch64::SSHLv8i16:
27104 case AArch64::SSHLv16i8:
27105 case AArch64::SSUBLv2i32_v2i64:
27106 case AArch64::SSUBLv4i16_v4i32:
27107 case AArch64::SSUBLv4i32_v2i64:
27108 case AArch64::SSUBLv8i8_v8i16:
27109 case AArch64::SSUBLv8i16_v4i32:
27110 case AArch64::SSUBLv16i8_v8i16:
27111 case AArch64::SSUBWv2i32_v2i64:
27112 case AArch64::SSUBWv4i16_v4i32:
27113 case AArch64::SSUBWv4i32_v2i64:
27114 case AArch64::SSUBWv8i8_v8i16:
27115 case AArch64::SSUBWv8i16_v4i32:
27116 case AArch64::SSUBWv16i8_v8i16:
27117 case AArch64::SUBHNv2i64_v2i32:
27118 case AArch64::SUBHNv4i32_v4i16:
27119 case AArch64::SUBHNv8i16_v8i8:
27120 case AArch64::SUBP:
27121 case AArch64::SUBPS:
27122 case AArch64::SUBv1i64:
27123 case AArch64::SUBv2i32:
27124 case AArch64::SUBv2i64:
27125 case AArch64::SUBv4i16:
27126 case AArch64::SUBv4i32:
27127 case AArch64::SUBv8i8:
27128 case AArch64::SUBv8i16:
27129 case AArch64::SUBv16i8:
27130 case AArch64::TRN1v2i32:
27131 case AArch64::TRN1v2i64:
27132 case AArch64::TRN1v4i16:
27133 case AArch64::TRN1v4i32:
27134 case AArch64::TRN1v8i8:
27135 case AArch64::TRN1v8i16:
27136 case AArch64::TRN1v16i8:
27137 case AArch64::TRN2v2i32:
27138 case AArch64::TRN2v2i64:
27139 case AArch64::TRN2v4i16:
27140 case AArch64::TRN2v4i32:
27141 case AArch64::TRN2v8i8:
27142 case AArch64::TRN2v8i16:
27143 case AArch64::TRN2v16i8:
27144 case AArch64::UABDLv2i32_v2i64:
27145 case AArch64::UABDLv4i16_v4i32:
27146 case AArch64::UABDLv4i32_v2i64:
27147 case AArch64::UABDLv8i8_v8i16:
27148 case AArch64::UABDLv8i16_v4i32:
27149 case AArch64::UABDLv16i8_v8i16:
27150 case AArch64::UABDv2i32:
27151 case AArch64::UABDv4i16:
27152 case AArch64::UABDv4i32:
27153 case AArch64::UABDv8i8:
27154 case AArch64::UABDv8i16:
27155 case AArch64::UABDv16i8:
27156 case AArch64::UADDLv2i32_v2i64:
27157 case AArch64::UADDLv4i16_v4i32:
27158 case AArch64::UADDLv4i32_v2i64:
27159 case AArch64::UADDLv8i8_v8i16:
27160 case AArch64::UADDLv8i16_v4i32:
27161 case AArch64::UADDLv16i8_v8i16:
27162 case AArch64::UADDWv2i32_v2i64:
27163 case AArch64::UADDWv4i16_v4i32:
27164 case AArch64::UADDWv4i32_v2i64:
27165 case AArch64::UADDWv8i8_v8i16:
27166 case AArch64::UADDWv8i16_v4i32:
27167 case AArch64::UADDWv16i8_v8i16:
27168 case AArch64::UDIVWr:
27169 case AArch64::UDIVXr:
27170 case AArch64::UHADDv2i32:
27171 case AArch64::UHADDv4i16:
27172 case AArch64::UHADDv4i32:
27173 case AArch64::UHADDv8i8:
27174 case AArch64::UHADDv8i16:
27175 case AArch64::UHADDv16i8:
27176 case AArch64::UHSUBv2i32:
27177 case AArch64::UHSUBv4i16:
27178 case AArch64::UHSUBv4i32:
27179 case AArch64::UHSUBv8i8:
27180 case AArch64::UHSUBv8i16:
27181 case AArch64::UHSUBv16i8:
27182 case AArch64::UMAXPv2i32:
27183 case AArch64::UMAXPv4i16:
27184 case AArch64::UMAXPv4i32:
27185 case AArch64::UMAXPv8i8:
27186 case AArch64::UMAXPv8i16:
27187 case AArch64::UMAXPv16i8:
27188 case AArch64::UMAXWrr:
27189 case AArch64::UMAXXrr:
27190 case AArch64::UMAXv2i32:
27191 case AArch64::UMAXv4i16:
27192 case AArch64::UMAXv4i32:
27193 case AArch64::UMAXv8i8:
27194 case AArch64::UMAXv8i16:
27195 case AArch64::UMAXv16i8:
27196 case AArch64::UMINPv2i32:
27197 case AArch64::UMINPv4i16:
27198 case AArch64::UMINPv4i32:
27199 case AArch64::UMINPv8i8:
27200 case AArch64::UMINPv8i16:
27201 case AArch64::UMINPv16i8:
27202 case AArch64::UMINWrr:
27203 case AArch64::UMINXrr:
27204 case AArch64::UMINv2i32:
27205 case AArch64::UMINv4i16:
27206 case AArch64::UMINv4i32:
27207 case AArch64::UMINv8i8:
27208 case AArch64::UMINv8i16:
27209 case AArch64::UMINv16i8:
27210 case AArch64::UMULHrr:
27211 case AArch64::UMULLv2i32_v2i64:
27212 case AArch64::UMULLv4i16_v4i32:
27213 case AArch64::UMULLv4i32_v2i64:
27214 case AArch64::UMULLv8i8_v8i16:
27215 case AArch64::UMULLv8i16_v4i32:
27216 case AArch64::UMULLv16i8_v8i16:
27217 case AArch64::UQADDv1i8:
27218 case AArch64::UQADDv1i16:
27219 case AArch64::UQADDv1i32:
27220 case AArch64::UQADDv1i64:
27221 case AArch64::UQADDv2i32:
27222 case AArch64::UQADDv2i64:
27223 case AArch64::UQADDv4i16:
27224 case AArch64::UQADDv4i32:
27225 case AArch64::UQADDv8i8:
27226 case AArch64::UQADDv8i16:
27227 case AArch64::UQADDv16i8:
27228 case AArch64::UQRSHLv1i8:
27229 case AArch64::UQRSHLv1i16:
27230 case AArch64::UQRSHLv1i32:
27231 case AArch64::UQRSHLv1i64:
27232 case AArch64::UQRSHLv2i32:
27233 case AArch64::UQRSHLv2i64:
27234 case AArch64::UQRSHLv4i16:
27235 case AArch64::UQRSHLv4i32:
27236 case AArch64::UQRSHLv8i8:
27237 case AArch64::UQRSHLv8i16:
27238 case AArch64::UQRSHLv16i8:
27239 case AArch64::UQSHLv1i8:
27240 case AArch64::UQSHLv1i16:
27241 case AArch64::UQSHLv1i32:
27242 case AArch64::UQSHLv1i64:
27243 case AArch64::UQSHLv2i32:
27244 case AArch64::UQSHLv2i64:
27245 case AArch64::UQSHLv4i16:
27246 case AArch64::UQSHLv4i32:
27247 case AArch64::UQSHLv8i8:
27248 case AArch64::UQSHLv8i16:
27249 case AArch64::UQSHLv16i8:
27250 case AArch64::UQSUBv1i8:
27251 case AArch64::UQSUBv1i16:
27252 case AArch64::UQSUBv1i32:
27253 case AArch64::UQSUBv1i64:
27254 case AArch64::UQSUBv2i32:
27255 case AArch64::UQSUBv2i64:
27256 case AArch64::UQSUBv4i16:
27257 case AArch64::UQSUBv4i32:
27258 case AArch64::UQSUBv8i8:
27259 case AArch64::UQSUBv8i16:
27260 case AArch64::UQSUBv16i8:
27261 case AArch64::URHADDv2i32:
27262 case AArch64::URHADDv4i16:
27263 case AArch64::URHADDv4i32:
27264 case AArch64::URHADDv8i8:
27265 case AArch64::URHADDv8i16:
27266 case AArch64::URHADDv16i8:
27267 case AArch64::URSHLv1i64:
27268 case AArch64::URSHLv2i32:
27269 case AArch64::URSHLv2i64:
27270 case AArch64::URSHLv4i16:
27271 case AArch64::URSHLv4i32:
27272 case AArch64::URSHLv8i8:
27273 case AArch64::URSHLv8i16:
27274 case AArch64::URSHLv16i8:
27275 case AArch64::USHLv1i64:
27276 case AArch64::USHLv2i32:
27277 case AArch64::USHLv2i64:
27278 case AArch64::USHLv4i16:
27279 case AArch64::USHLv4i32:
27280 case AArch64::USHLv8i8:
27281 case AArch64::USHLv8i16:
27282 case AArch64::USHLv16i8:
27283 case AArch64::USUBLv2i32_v2i64:
27284 case AArch64::USUBLv4i16_v4i32:
27285 case AArch64::USUBLv4i32_v2i64:
27286 case AArch64::USUBLv8i8_v8i16:
27287 case AArch64::USUBLv8i16_v4i32:
27288 case AArch64::USUBLv16i8_v8i16:
27289 case AArch64::USUBWv2i32_v2i64:
27290 case AArch64::USUBWv4i16_v4i32:
27291 case AArch64::USUBWv4i32_v2i64:
27292 case AArch64::USUBWv8i8_v8i16:
27293 case AArch64::USUBWv8i16_v4i32:
27294 case AArch64::USUBWv16i8_v8i16:
27295 case AArch64::UZP1v2i32:
27296 case AArch64::UZP1v2i64:
27297 case AArch64::UZP1v4i16:
27298 case AArch64::UZP1v4i32:
27299 case AArch64::UZP1v8i8:
27300 case AArch64::UZP1v8i16:
27301 case AArch64::UZP1v16i8:
27302 case AArch64::UZP2v2i32:
27303 case AArch64::UZP2v2i64:
27304 case AArch64::UZP2v4i16:
27305 case AArch64::UZP2v4i32:
27306 case AArch64::UZP2v8i8:
27307 case AArch64::UZP2v8i16:
27308 case AArch64::UZP2v16i8:
27309 case AArch64::ZIP1v2i32:
27310 case AArch64::ZIP1v2i64:
27311 case AArch64::ZIP1v4i16:
27312 case AArch64::ZIP1v4i32:
27313 case AArch64::ZIP1v8i8:
27314 case AArch64::ZIP1v8i16:
27315 case AArch64::ZIP1v16i8:
27316 case AArch64::ZIP2v2i32:
27317 case AArch64::ZIP2v2i64:
27318 case AArch64::ZIP2v4i16:
27319 case AArch64::ZIP2v4i32:
27320 case AArch64::ZIP2v8i8:
27321 case AArch64::ZIP2v8i16:
27322 case AArch64::ZIP2v16i8: {
27323 switch (OpNum) {
27324 case 0:
27325 // op: Rd
27326 return 0;
27327 case 1:
27328 // op: Rn
27329 return 5;
27330 case 2:
27331 // op: Rm
27332 return 16;
27333 }
27334 break;
27335 }
27336 case AArch64::DUPv8i8lane:
27337 case AArch64::DUPv16i8lane:
27338 case AArch64::SMOVvi8to32:
27339 case AArch64::SMOVvi8to64:
27340 case AArch64::UMOVvi8: {
27341 switch (OpNum) {
27342 case 0:
27343 // op: Rd
27344 return 0;
27345 case 1:
27346 // op: Rn
27347 return 5;
27348 case 2:
27349 // op: idx
27350 return 17;
27351 }
27352 break;
27353 }
27354 case AArch64::DUPv4i16lane:
27355 case AArch64::DUPv8i16lane:
27356 case AArch64::SMOVvi16to32:
27357 case AArch64::SMOVvi16to64:
27358 case AArch64::UMOVvi16: {
27359 switch (OpNum) {
27360 case 0:
27361 // op: Rd
27362 return 0;
27363 case 1:
27364 // op: Rn
27365 return 5;
27366 case 2:
27367 // op: idx
27368 return 18;
27369 }
27370 break;
27371 }
27372 case AArch64::DUPv2i32lane:
27373 case AArch64::DUPv4i32lane:
27374 case AArch64::SMOVvi32to64:
27375 case AArch64::UMOVvi32: {
27376 switch (OpNum) {
27377 case 0:
27378 // op: Rd
27379 return 0;
27380 case 1:
27381 // op: Rn
27382 return 5;
27383 case 2:
27384 // op: idx
27385 return 19;
27386 }
27387 break;
27388 }
27389 case AArch64::DUPv2i64lane:
27390 case AArch64::UMOVvi64: {
27391 switch (OpNum) {
27392 case 0:
27393 // op: Rd
27394 return 0;
27395 case 1:
27396 // op: Rn
27397 return 5;
27398 case 2:
27399 // op: idx
27400 return 20;
27401 }
27402 break;
27403 }
27404 case AArch64::ADDSWri:
27405 case AArch64::ADDSXri:
27406 case AArch64::ADDWri:
27407 case AArch64::ADDXri:
27408 case AArch64::ANDSWri:
27409 case AArch64::ANDSXri:
27410 case AArch64::ANDWri:
27411 case AArch64::ANDXri:
27412 case AArch64::EORWri:
27413 case AArch64::EORXri:
27414 case AArch64::ORRWri:
27415 case AArch64::ORRXri:
27416 case AArch64::SMAXWri:
27417 case AArch64::SMAXXri:
27418 case AArch64::SMINWri:
27419 case AArch64::SMINXri:
27420 case AArch64::SUBSWri:
27421 case AArch64::SUBSXri:
27422 case AArch64::SUBWri:
27423 case AArch64::SUBXri:
27424 case AArch64::UMAXWri:
27425 case AArch64::UMAXXri:
27426 case AArch64::UMINWri:
27427 case AArch64::UMINXri: {
27428 switch (OpNum) {
27429 case 0:
27430 // op: Rd
27431 return 0;
27432 case 1:
27433 // op: Rn
27434 return 5;
27435 case 2:
27436 // op: imm
27437 return 10;
27438 }
27439 break;
27440 }
27441 case AArch64::FCVTZSd:
27442 case AArch64::FCVTZSh:
27443 case AArch64::FCVTZSs:
27444 case AArch64::FCVTZSv2i32_shift:
27445 case AArch64::FCVTZSv2i64_shift:
27446 case AArch64::FCVTZSv4i16_shift:
27447 case AArch64::FCVTZSv4i32_shift:
27448 case AArch64::FCVTZSv8i16_shift:
27449 case AArch64::FCVTZUd:
27450 case AArch64::FCVTZUh:
27451 case AArch64::FCVTZUs:
27452 case AArch64::FCVTZUv2i32_shift:
27453 case AArch64::FCVTZUv2i64_shift:
27454 case AArch64::FCVTZUv4i16_shift:
27455 case AArch64::FCVTZUv4i32_shift:
27456 case AArch64::FCVTZUv8i16_shift:
27457 case AArch64::RSHRNv2i32_shift:
27458 case AArch64::RSHRNv4i16_shift:
27459 case AArch64::RSHRNv8i8_shift:
27460 case AArch64::SCVTFd:
27461 case AArch64::SCVTFh:
27462 case AArch64::SCVTFs:
27463 case AArch64::SCVTFv2i32_shift:
27464 case AArch64::SCVTFv2i64_shift:
27465 case AArch64::SCVTFv4i16_shift:
27466 case AArch64::SCVTFv4i32_shift:
27467 case AArch64::SCVTFv8i16_shift:
27468 case AArch64::SHLd:
27469 case AArch64::SHLv2i32_shift:
27470 case AArch64::SHLv2i64_shift:
27471 case AArch64::SHLv4i16_shift:
27472 case AArch64::SHLv4i32_shift:
27473 case AArch64::SHLv8i8_shift:
27474 case AArch64::SHLv8i16_shift:
27475 case AArch64::SHLv16i8_shift:
27476 case AArch64::SHRNv2i32_shift:
27477 case AArch64::SHRNv4i16_shift:
27478 case AArch64::SHRNv8i8_shift:
27479 case AArch64::SQRSHRNb:
27480 case AArch64::SQRSHRNh:
27481 case AArch64::SQRSHRNs:
27482 case AArch64::SQRSHRNv2i32_shift:
27483 case AArch64::SQRSHRNv4i16_shift:
27484 case AArch64::SQRSHRNv8i8_shift:
27485 case AArch64::SQRSHRUNb:
27486 case AArch64::SQRSHRUNh:
27487 case AArch64::SQRSHRUNs:
27488 case AArch64::SQRSHRUNv2i32_shift:
27489 case AArch64::SQRSHRUNv4i16_shift:
27490 case AArch64::SQRSHRUNv8i8_shift:
27491 case AArch64::SQSHLUb:
27492 case AArch64::SQSHLUd:
27493 case AArch64::SQSHLUh:
27494 case AArch64::SQSHLUs:
27495 case AArch64::SQSHLUv2i32_shift:
27496 case AArch64::SQSHLUv2i64_shift:
27497 case AArch64::SQSHLUv4i16_shift:
27498 case AArch64::SQSHLUv4i32_shift:
27499 case AArch64::SQSHLUv8i8_shift:
27500 case AArch64::SQSHLUv8i16_shift:
27501 case AArch64::SQSHLUv16i8_shift:
27502 case AArch64::SQSHLb:
27503 case AArch64::SQSHLd:
27504 case AArch64::SQSHLh:
27505 case AArch64::SQSHLs:
27506 case AArch64::SQSHLv2i32_shift:
27507 case AArch64::SQSHLv2i64_shift:
27508 case AArch64::SQSHLv4i16_shift:
27509 case AArch64::SQSHLv4i32_shift:
27510 case AArch64::SQSHLv8i8_shift:
27511 case AArch64::SQSHLv8i16_shift:
27512 case AArch64::SQSHLv16i8_shift:
27513 case AArch64::SQSHRNb:
27514 case AArch64::SQSHRNh:
27515 case AArch64::SQSHRNs:
27516 case AArch64::SQSHRNv2i32_shift:
27517 case AArch64::SQSHRNv4i16_shift:
27518 case AArch64::SQSHRNv8i8_shift:
27519 case AArch64::SQSHRUNb:
27520 case AArch64::SQSHRUNh:
27521 case AArch64::SQSHRUNs:
27522 case AArch64::SQSHRUNv2i32_shift:
27523 case AArch64::SQSHRUNv4i16_shift:
27524 case AArch64::SQSHRUNv8i8_shift:
27525 case AArch64::SRSHRd:
27526 case AArch64::SRSHRv2i32_shift:
27527 case AArch64::SRSHRv2i64_shift:
27528 case AArch64::SRSHRv4i16_shift:
27529 case AArch64::SRSHRv4i32_shift:
27530 case AArch64::SRSHRv8i8_shift:
27531 case AArch64::SRSHRv8i16_shift:
27532 case AArch64::SRSHRv16i8_shift:
27533 case AArch64::SSHLLv2i32_shift:
27534 case AArch64::SSHLLv4i16_shift:
27535 case AArch64::SSHLLv4i32_shift:
27536 case AArch64::SSHLLv8i8_shift:
27537 case AArch64::SSHLLv8i16_shift:
27538 case AArch64::SSHLLv16i8_shift:
27539 case AArch64::SSHRd:
27540 case AArch64::SSHRv2i32_shift:
27541 case AArch64::SSHRv2i64_shift:
27542 case AArch64::SSHRv4i16_shift:
27543 case AArch64::SSHRv4i32_shift:
27544 case AArch64::SSHRv8i8_shift:
27545 case AArch64::SSHRv8i16_shift:
27546 case AArch64::SSHRv16i8_shift:
27547 case AArch64::UCVTFd:
27548 case AArch64::UCVTFh:
27549 case AArch64::UCVTFs:
27550 case AArch64::UCVTFv2i32_shift:
27551 case AArch64::UCVTFv2i64_shift:
27552 case AArch64::UCVTFv4i16_shift:
27553 case AArch64::UCVTFv4i32_shift:
27554 case AArch64::UCVTFv8i16_shift:
27555 case AArch64::UQRSHRNb:
27556 case AArch64::UQRSHRNh:
27557 case AArch64::UQRSHRNs:
27558 case AArch64::UQRSHRNv2i32_shift:
27559 case AArch64::UQRSHRNv4i16_shift:
27560 case AArch64::UQRSHRNv8i8_shift:
27561 case AArch64::UQSHLb:
27562 case AArch64::UQSHLd:
27563 case AArch64::UQSHLh:
27564 case AArch64::UQSHLs:
27565 case AArch64::UQSHLv2i32_shift:
27566 case AArch64::UQSHLv2i64_shift:
27567 case AArch64::UQSHLv4i16_shift:
27568 case AArch64::UQSHLv4i32_shift:
27569 case AArch64::UQSHLv8i8_shift:
27570 case AArch64::UQSHLv8i16_shift:
27571 case AArch64::UQSHLv16i8_shift:
27572 case AArch64::UQSHRNb:
27573 case AArch64::UQSHRNh:
27574 case AArch64::UQSHRNs:
27575 case AArch64::UQSHRNv2i32_shift:
27576 case AArch64::UQSHRNv4i16_shift:
27577 case AArch64::UQSHRNv8i8_shift:
27578 case AArch64::URSHRd:
27579 case AArch64::URSHRv2i32_shift:
27580 case AArch64::URSHRv2i64_shift:
27581 case AArch64::URSHRv4i16_shift:
27582 case AArch64::URSHRv4i32_shift:
27583 case AArch64::URSHRv8i8_shift:
27584 case AArch64::URSHRv8i16_shift:
27585 case AArch64::URSHRv16i8_shift:
27586 case AArch64::USHLLv2i32_shift:
27587 case AArch64::USHLLv4i16_shift:
27588 case AArch64::USHLLv4i32_shift:
27589 case AArch64::USHLLv8i8_shift:
27590 case AArch64::USHLLv8i16_shift:
27591 case AArch64::USHLLv16i8_shift:
27592 case AArch64::USHRd:
27593 case AArch64::USHRv2i32_shift:
27594 case AArch64::USHRv2i64_shift:
27595 case AArch64::USHRv4i16_shift:
27596 case AArch64::USHRv4i32_shift:
27597 case AArch64::USHRv8i8_shift:
27598 case AArch64::USHRv8i16_shift:
27599 case AArch64::USHRv16i8_shift: {
27600 switch (OpNum) {
27601 case 0:
27602 // op: Rd
27603 return 0;
27604 case 1:
27605 // op: Rn
27606 return 5;
27607 case 2:
27608 // op: imm
27609 return 16;
27610 }
27611 break;
27612 }
27613 case AArch64::ADDG:
27614 case AArch64::SUBG: {
27615 switch (OpNum) {
27616 case 0:
27617 // op: Rd
27618 return 0;
27619 case 1:
27620 // op: Rn
27621 return 5;
27622 case 2:
27623 // op: imm6
27624 return 16;
27625 case 3:
27626 // op: imm4
27627 return 10;
27628 }
27629 break;
27630 }
27631 case AArch64::SBFMWri:
27632 case AArch64::SBFMXri:
27633 case AArch64::UBFMWri:
27634 case AArch64::UBFMXri: {
27635 switch (OpNum) {
27636 case 0:
27637 // op: Rd
27638 return 0;
27639 case 1:
27640 // op: Rn
27641 return 5;
27642 case 2:
27643 // op: immr
27644 return 16;
27645 case 3:
27646 // op: imms
27647 return 10;
27648 }
27649 break;
27650 }
27651 case AArch64::FCVTZSSWDri:
27652 case AArch64::FCVTZSSWHri:
27653 case AArch64::FCVTZSSWSri:
27654 case AArch64::FCVTZSSXDri:
27655 case AArch64::FCVTZSSXHri:
27656 case AArch64::FCVTZSSXSri:
27657 case AArch64::FCVTZUSWDri:
27658 case AArch64::FCVTZUSWHri:
27659 case AArch64::FCVTZUSWSri:
27660 case AArch64::FCVTZUSXDri:
27661 case AArch64::FCVTZUSXHri:
27662 case AArch64::FCVTZUSXSri:
27663 case AArch64::SCVTFSWDri:
27664 case AArch64::SCVTFSWHri:
27665 case AArch64::SCVTFSWSri:
27666 case AArch64::SCVTFSXDri:
27667 case AArch64::SCVTFSXHri:
27668 case AArch64::SCVTFSXSri:
27669 case AArch64::UCVTFSWDri:
27670 case AArch64::UCVTFSWHri:
27671 case AArch64::UCVTFSWSri:
27672 case AArch64::UCVTFSXDri:
27673 case AArch64::UCVTFSXHri:
27674 case AArch64::UCVTFSXSri: {
27675 switch (OpNum) {
27676 case 0:
27677 // op: Rd
27678 return 0;
27679 case 1:
27680 // op: Rn
27681 return 5;
27682 case 2:
27683 // op: scale
27684 return 10;
27685 }
27686 break;
27687 }
27688 case AArch64::ABSWr:
27689 case AArch64::ABSXr:
27690 case AArch64::ABSv1i64:
27691 case AArch64::ABSv2i32:
27692 case AArch64::ABSv2i64:
27693 case AArch64::ABSv4i16:
27694 case AArch64::ABSv4i32:
27695 case AArch64::ABSv8i8:
27696 case AArch64::ABSv8i16:
27697 case AArch64::ABSv16i8:
27698 case AArch64::ADDPv2i64p:
27699 case AArch64::ADDVv4i16v:
27700 case AArch64::ADDVv4i32v:
27701 case AArch64::ADDVv8i8v:
27702 case AArch64::ADDVv8i16v:
27703 case AArch64::ADDVv16i8v:
27704 case AArch64::AESIMCrr:
27705 case AArch64::AESMCrr:
27706 case AArch64::BF1CVTL:
27707 case AArch64::BF1CVTL2:
27708 case AArch64::BF2CVTL:
27709 case AArch64::BF2CVTL2:
27710 case AArch64::BFCVT:
27711 case AArch64::BFCVTN:
27712 case AArch64::CLSWr:
27713 case AArch64::CLSXr:
27714 case AArch64::CLSv2i32:
27715 case AArch64::CLSv4i16:
27716 case AArch64::CLSv4i32:
27717 case AArch64::CLSv8i8:
27718 case AArch64::CLSv8i16:
27719 case AArch64::CLSv16i8:
27720 case AArch64::CLZWr:
27721 case AArch64::CLZXr:
27722 case AArch64::CLZv2i32:
27723 case AArch64::CLZv4i16:
27724 case AArch64::CLZv4i32:
27725 case AArch64::CLZv8i8:
27726 case AArch64::CLZv8i16:
27727 case AArch64::CLZv16i8:
27728 case AArch64::CMEQv1i64rz:
27729 case AArch64::CMEQv2i32rz:
27730 case AArch64::CMEQv2i64rz:
27731 case AArch64::CMEQv4i16rz:
27732 case AArch64::CMEQv4i32rz:
27733 case AArch64::CMEQv8i8rz:
27734 case AArch64::CMEQv8i16rz:
27735 case AArch64::CMEQv16i8rz:
27736 case AArch64::CMGEv1i64rz:
27737 case AArch64::CMGEv2i32rz:
27738 case AArch64::CMGEv2i64rz:
27739 case AArch64::CMGEv4i16rz:
27740 case AArch64::CMGEv4i32rz:
27741 case AArch64::CMGEv8i8rz:
27742 case AArch64::CMGEv8i16rz:
27743 case AArch64::CMGEv16i8rz:
27744 case AArch64::CMGTv1i64rz:
27745 case AArch64::CMGTv2i32rz:
27746 case AArch64::CMGTv2i64rz:
27747 case AArch64::CMGTv4i16rz:
27748 case AArch64::CMGTv4i32rz:
27749 case AArch64::CMGTv8i8rz:
27750 case AArch64::CMGTv8i16rz:
27751 case AArch64::CMGTv16i8rz:
27752 case AArch64::CMLEv1i64rz:
27753 case AArch64::CMLEv2i32rz:
27754 case AArch64::CMLEv2i64rz:
27755 case AArch64::CMLEv4i16rz:
27756 case AArch64::CMLEv4i32rz:
27757 case AArch64::CMLEv8i8rz:
27758 case AArch64::CMLEv8i16rz:
27759 case AArch64::CMLEv16i8rz:
27760 case AArch64::CMLTv1i64rz:
27761 case AArch64::CMLTv2i32rz:
27762 case AArch64::CMLTv2i64rz:
27763 case AArch64::CMLTv4i16rz:
27764 case AArch64::CMLTv4i32rz:
27765 case AArch64::CMLTv8i8rz:
27766 case AArch64::CMLTv8i16rz:
27767 case AArch64::CMLTv16i8rz:
27768 case AArch64::CNTWr:
27769 case AArch64::CNTXr:
27770 case AArch64::CNTv8i8:
27771 case AArch64::CNTv16i8:
27772 case AArch64::CTZWr:
27773 case AArch64::CTZXr:
27774 case AArch64::DUPv2i32gpr:
27775 case AArch64::DUPv2i64gpr:
27776 case AArch64::DUPv4i16gpr:
27777 case AArch64::DUPv4i32gpr:
27778 case AArch64::DUPv8i8gpr:
27779 case AArch64::DUPv8i16gpr:
27780 case AArch64::DUPv16i8gpr:
27781 case AArch64::F1CVTL:
27782 case AArch64::F1CVTL2:
27783 case AArch64::F2CVTL:
27784 case AArch64::F2CVTL2:
27785 case AArch64::FABSDr:
27786 case AArch64::FABSHr:
27787 case AArch64::FABSSr:
27788 case AArch64::FABSv2f32:
27789 case AArch64::FABSv2f64:
27790 case AArch64::FABSv4f16:
27791 case AArch64::FABSv4f32:
27792 case AArch64::FABSv8f16:
27793 case AArch64::FADDPv2i16p:
27794 case AArch64::FADDPv2i32p:
27795 case AArch64::FADDPv2i64p:
27796 case AArch64::FCMEQv1i16rz:
27797 case AArch64::FCMEQv1i32rz:
27798 case AArch64::FCMEQv1i64rz:
27799 case AArch64::FCMEQv2i32rz:
27800 case AArch64::FCMEQv2i64rz:
27801 case AArch64::FCMEQv4i16rz:
27802 case AArch64::FCMEQv4i32rz:
27803 case AArch64::FCMEQv8i16rz:
27804 case AArch64::FCMGEv1i16rz:
27805 case AArch64::FCMGEv1i32rz:
27806 case AArch64::FCMGEv1i64rz:
27807 case AArch64::FCMGEv2i32rz:
27808 case AArch64::FCMGEv2i64rz:
27809 case AArch64::FCMGEv4i16rz:
27810 case AArch64::FCMGEv4i32rz:
27811 case AArch64::FCMGEv8i16rz:
27812 case AArch64::FCMGTv1i16rz:
27813 case AArch64::FCMGTv1i32rz:
27814 case AArch64::FCMGTv1i64rz:
27815 case AArch64::FCMGTv2i32rz:
27816 case AArch64::FCMGTv2i64rz:
27817 case AArch64::FCMGTv4i16rz:
27818 case AArch64::FCMGTv4i32rz:
27819 case AArch64::FCMGTv8i16rz:
27820 case AArch64::FCMLEv1i16rz:
27821 case AArch64::FCMLEv1i32rz:
27822 case AArch64::FCMLEv1i64rz:
27823 case AArch64::FCMLEv2i32rz:
27824 case AArch64::FCMLEv2i64rz:
27825 case AArch64::FCMLEv4i16rz:
27826 case AArch64::FCMLEv4i32rz:
27827 case AArch64::FCMLEv8i16rz:
27828 case AArch64::FCMLTv1i16rz:
27829 case AArch64::FCMLTv1i32rz:
27830 case AArch64::FCMLTv1i64rz:
27831 case AArch64::FCMLTv2i32rz:
27832 case AArch64::FCMLTv2i64rz:
27833 case AArch64::FCMLTv4i16rz:
27834 case AArch64::FCMLTv4i32rz:
27835 case AArch64::FCMLTv8i16rz:
27836 case AArch64::FCVTASDHr:
27837 case AArch64::FCVTASDSr:
27838 case AArch64::FCVTASSDr:
27839 case AArch64::FCVTASSHr:
27840 case AArch64::FCVTASUWDr:
27841 case AArch64::FCVTASUWHr:
27842 case AArch64::FCVTASUWSr:
27843 case AArch64::FCVTASUXDr:
27844 case AArch64::FCVTASUXHr:
27845 case AArch64::FCVTASUXSr:
27846 case AArch64::FCVTASv1f16:
27847 case AArch64::FCVTASv1i32:
27848 case AArch64::FCVTASv1i64:
27849 case AArch64::FCVTASv2f32:
27850 case AArch64::FCVTASv2f64:
27851 case AArch64::FCVTASv4f16:
27852 case AArch64::FCVTASv4f32:
27853 case AArch64::FCVTASv8f16:
27854 case AArch64::FCVTAUDHr:
27855 case AArch64::FCVTAUDSr:
27856 case AArch64::FCVTAUSDr:
27857 case AArch64::FCVTAUSHr:
27858 case AArch64::FCVTAUUWDr:
27859 case AArch64::FCVTAUUWHr:
27860 case AArch64::FCVTAUUWSr:
27861 case AArch64::FCVTAUUXDr:
27862 case AArch64::FCVTAUUXHr:
27863 case AArch64::FCVTAUUXSr:
27864 case AArch64::FCVTAUv1f16:
27865 case AArch64::FCVTAUv1i32:
27866 case AArch64::FCVTAUv1i64:
27867 case AArch64::FCVTAUv2f32:
27868 case AArch64::FCVTAUv2f64:
27869 case AArch64::FCVTAUv4f16:
27870 case AArch64::FCVTAUv4f32:
27871 case AArch64::FCVTAUv8f16:
27872 case AArch64::FCVTDHr:
27873 case AArch64::FCVTDSr:
27874 case AArch64::FCVTHDr:
27875 case AArch64::FCVTHSr:
27876 case AArch64::FCVTLv2i32:
27877 case AArch64::FCVTLv4i16:
27878 case AArch64::FCVTLv4i32:
27879 case AArch64::FCVTLv8i16:
27880 case AArch64::FCVTMSDHr:
27881 case AArch64::FCVTMSDSr:
27882 case AArch64::FCVTMSSDr:
27883 case AArch64::FCVTMSSHr:
27884 case AArch64::FCVTMSUWDr:
27885 case AArch64::FCVTMSUWHr:
27886 case AArch64::FCVTMSUWSr:
27887 case AArch64::FCVTMSUXDr:
27888 case AArch64::FCVTMSUXHr:
27889 case AArch64::FCVTMSUXSr:
27890 case AArch64::FCVTMSv1f16:
27891 case AArch64::FCVTMSv1i32:
27892 case AArch64::FCVTMSv1i64:
27893 case AArch64::FCVTMSv2f32:
27894 case AArch64::FCVTMSv2f64:
27895 case AArch64::FCVTMSv4f16:
27896 case AArch64::FCVTMSv4f32:
27897 case AArch64::FCVTMSv8f16:
27898 case AArch64::FCVTMUDHr:
27899 case AArch64::FCVTMUDSr:
27900 case AArch64::FCVTMUSDr:
27901 case AArch64::FCVTMUSHr:
27902 case AArch64::FCVTMUUWDr:
27903 case AArch64::FCVTMUUWHr:
27904 case AArch64::FCVTMUUWSr:
27905 case AArch64::FCVTMUUXDr:
27906 case AArch64::FCVTMUUXHr:
27907 case AArch64::FCVTMUUXSr:
27908 case AArch64::FCVTMUv1f16:
27909 case AArch64::FCVTMUv1i32:
27910 case AArch64::FCVTMUv1i64:
27911 case AArch64::FCVTMUv2f32:
27912 case AArch64::FCVTMUv2f64:
27913 case AArch64::FCVTMUv4f16:
27914 case AArch64::FCVTMUv4f32:
27915 case AArch64::FCVTMUv8f16:
27916 case AArch64::FCVTNSDHr:
27917 case AArch64::FCVTNSDSr:
27918 case AArch64::FCVTNSSDr:
27919 case AArch64::FCVTNSSHr:
27920 case AArch64::FCVTNSUWDr:
27921 case AArch64::FCVTNSUWHr:
27922 case AArch64::FCVTNSUWSr:
27923 case AArch64::FCVTNSUXDr:
27924 case AArch64::FCVTNSUXHr:
27925 case AArch64::FCVTNSUXSr:
27926 case AArch64::FCVTNSv1f16:
27927 case AArch64::FCVTNSv1i32:
27928 case AArch64::FCVTNSv1i64:
27929 case AArch64::FCVTNSv2f32:
27930 case AArch64::FCVTNSv2f64:
27931 case AArch64::FCVTNSv4f16:
27932 case AArch64::FCVTNSv4f32:
27933 case AArch64::FCVTNSv8f16:
27934 case AArch64::FCVTNUDHr:
27935 case AArch64::FCVTNUDSr:
27936 case AArch64::FCVTNUSDr:
27937 case AArch64::FCVTNUSHr:
27938 case AArch64::FCVTNUUWDr:
27939 case AArch64::FCVTNUUWHr:
27940 case AArch64::FCVTNUUWSr:
27941 case AArch64::FCVTNUUXDr:
27942 case AArch64::FCVTNUUXHr:
27943 case AArch64::FCVTNUUXSr:
27944 case AArch64::FCVTNUv1f16:
27945 case AArch64::FCVTNUv1i32:
27946 case AArch64::FCVTNUv1i64:
27947 case AArch64::FCVTNUv2f32:
27948 case AArch64::FCVTNUv2f64:
27949 case AArch64::FCVTNUv4f16:
27950 case AArch64::FCVTNUv4f32:
27951 case AArch64::FCVTNUv8f16:
27952 case AArch64::FCVTNv2i32:
27953 case AArch64::FCVTNv4i16:
27954 case AArch64::FCVTPSDHr:
27955 case AArch64::FCVTPSDSr:
27956 case AArch64::FCVTPSSDr:
27957 case AArch64::FCVTPSSHr:
27958 case AArch64::FCVTPSUWDr:
27959 case AArch64::FCVTPSUWHr:
27960 case AArch64::FCVTPSUWSr:
27961 case AArch64::FCVTPSUXDr:
27962 case AArch64::FCVTPSUXHr:
27963 case AArch64::FCVTPSUXSr:
27964 case AArch64::FCVTPSv1f16:
27965 case AArch64::FCVTPSv1i32:
27966 case AArch64::FCVTPSv1i64:
27967 case AArch64::FCVTPSv2f32:
27968 case AArch64::FCVTPSv2f64:
27969 case AArch64::FCVTPSv4f16:
27970 case AArch64::FCVTPSv4f32:
27971 case AArch64::FCVTPSv8f16:
27972 case AArch64::FCVTPUDHr:
27973 case AArch64::FCVTPUDSr:
27974 case AArch64::FCVTPUSDr:
27975 case AArch64::FCVTPUSHr:
27976 case AArch64::FCVTPUUWDr:
27977 case AArch64::FCVTPUUWHr:
27978 case AArch64::FCVTPUUWSr:
27979 case AArch64::FCVTPUUXDr:
27980 case AArch64::FCVTPUUXHr:
27981 case AArch64::FCVTPUUXSr:
27982 case AArch64::FCVTPUv1f16:
27983 case AArch64::FCVTPUv1i32:
27984 case AArch64::FCVTPUv1i64:
27985 case AArch64::FCVTPUv2f32:
27986 case AArch64::FCVTPUv2f64:
27987 case AArch64::FCVTPUv4f16:
27988 case AArch64::FCVTPUv4f32:
27989 case AArch64::FCVTPUv8f16:
27990 case AArch64::FCVTSDr:
27991 case AArch64::FCVTSHr:
27992 case AArch64::FCVTXNv1i64:
27993 case AArch64::FCVTXNv2f32:
27994 case AArch64::FCVTZSDHr:
27995 case AArch64::FCVTZSDSr:
27996 case AArch64::FCVTZSSDr:
27997 case AArch64::FCVTZSSHr:
27998 case AArch64::FCVTZSUWDr:
27999 case AArch64::FCVTZSUWHr:
28000 case AArch64::FCVTZSUWSr:
28001 case AArch64::FCVTZSUXDr:
28002 case AArch64::FCVTZSUXHr:
28003 case AArch64::FCVTZSUXSr:
28004 case AArch64::FCVTZSv1f16:
28005 case AArch64::FCVTZSv1i32:
28006 case AArch64::FCVTZSv1i64:
28007 case AArch64::FCVTZSv2f32:
28008 case AArch64::FCVTZSv2f64:
28009 case AArch64::FCVTZSv4f16:
28010 case AArch64::FCVTZSv4f32:
28011 case AArch64::FCVTZSv8f16:
28012 case AArch64::FCVTZUDHr:
28013 case AArch64::FCVTZUDSr:
28014 case AArch64::FCVTZUSDr:
28015 case AArch64::FCVTZUSHr:
28016 case AArch64::FCVTZUUWDr:
28017 case AArch64::FCVTZUUWHr:
28018 case AArch64::FCVTZUUWSr:
28019 case AArch64::FCVTZUUXDr:
28020 case AArch64::FCVTZUUXHr:
28021 case AArch64::FCVTZUUXSr:
28022 case AArch64::FCVTZUv1f16:
28023 case AArch64::FCVTZUv1i32:
28024 case AArch64::FCVTZUv1i64:
28025 case AArch64::FCVTZUv2f32:
28026 case AArch64::FCVTZUv2f64:
28027 case AArch64::FCVTZUv4f16:
28028 case AArch64::FCVTZUv4f32:
28029 case AArch64::FCVTZUv8f16:
28030 case AArch64::FJCVTZS:
28031 case AArch64::FMAXNMPv2i16p:
28032 case AArch64::FMAXNMPv2i32p:
28033 case AArch64::FMAXNMPv2i64p:
28034 case AArch64::FMAXNMVv4i16v:
28035 case AArch64::FMAXNMVv4i32v:
28036 case AArch64::FMAXNMVv8i16v:
28037 case AArch64::FMAXPv2i16p:
28038 case AArch64::FMAXPv2i32p:
28039 case AArch64::FMAXPv2i64p:
28040 case AArch64::FMAXVv4i16v:
28041 case AArch64::FMAXVv4i32v:
28042 case AArch64::FMAXVv8i16v:
28043 case AArch64::FMINNMPv2i16p:
28044 case AArch64::FMINNMPv2i32p:
28045 case AArch64::FMINNMPv2i64p:
28046 case AArch64::FMINNMVv4i16v:
28047 case AArch64::FMINNMVv4i32v:
28048 case AArch64::FMINNMVv8i16v:
28049 case AArch64::FMINPv2i16p:
28050 case AArch64::FMINPv2i32p:
28051 case AArch64::FMINPv2i64p:
28052 case AArch64::FMINVv4i16v:
28053 case AArch64::FMINVv4i32v:
28054 case AArch64::FMINVv8i16v:
28055 case AArch64::FMOVDXHighr:
28056 case AArch64::FMOVDXr:
28057 case AArch64::FMOVDr:
28058 case AArch64::FMOVHWr:
28059 case AArch64::FMOVHXr:
28060 case AArch64::FMOVHr:
28061 case AArch64::FMOVSWr:
28062 case AArch64::FMOVSr:
28063 case AArch64::FMOVWHr:
28064 case AArch64::FMOVWSr:
28065 case AArch64::FMOVXDHighr:
28066 case AArch64::FMOVXDr:
28067 case AArch64::FMOVXHr:
28068 case AArch64::FNEGDr:
28069 case AArch64::FNEGHr:
28070 case AArch64::FNEGSr:
28071 case AArch64::FNEGv2f32:
28072 case AArch64::FNEGv2f64:
28073 case AArch64::FNEGv4f16:
28074 case AArch64::FNEGv4f32:
28075 case AArch64::FNEGv8f16:
28076 case AArch64::FRECPEv1f16:
28077 case AArch64::FRECPEv1i32:
28078 case AArch64::FRECPEv1i64:
28079 case AArch64::FRECPEv2f32:
28080 case AArch64::FRECPEv2f64:
28081 case AArch64::FRECPEv4f16:
28082 case AArch64::FRECPEv4f32:
28083 case AArch64::FRECPEv8f16:
28084 case AArch64::FRECPXv1f16:
28085 case AArch64::FRECPXv1i32:
28086 case AArch64::FRECPXv1i64:
28087 case AArch64::FRINT32XDr:
28088 case AArch64::FRINT32XSr:
28089 case AArch64::FRINT32Xv2f32:
28090 case AArch64::FRINT32Xv2f64:
28091 case AArch64::FRINT32Xv4f32:
28092 case AArch64::FRINT32ZDr:
28093 case AArch64::FRINT32ZSr:
28094 case AArch64::FRINT32Zv2f32:
28095 case AArch64::FRINT32Zv2f64:
28096 case AArch64::FRINT32Zv4f32:
28097 case AArch64::FRINT64XDr:
28098 case AArch64::FRINT64XSr:
28099 case AArch64::FRINT64Xv2f32:
28100 case AArch64::FRINT64Xv2f64:
28101 case AArch64::FRINT64Xv4f32:
28102 case AArch64::FRINT64ZDr:
28103 case AArch64::FRINT64ZSr:
28104 case AArch64::FRINT64Zv2f32:
28105 case AArch64::FRINT64Zv2f64:
28106 case AArch64::FRINT64Zv4f32:
28107 case AArch64::FRINTADr:
28108 case AArch64::FRINTAHr:
28109 case AArch64::FRINTASr:
28110 case AArch64::FRINTAv2f32:
28111 case AArch64::FRINTAv2f64:
28112 case AArch64::FRINTAv4f16:
28113 case AArch64::FRINTAv4f32:
28114 case AArch64::FRINTAv8f16:
28115 case AArch64::FRINTIDr:
28116 case AArch64::FRINTIHr:
28117 case AArch64::FRINTISr:
28118 case AArch64::FRINTIv2f32:
28119 case AArch64::FRINTIv2f64:
28120 case AArch64::FRINTIv4f16:
28121 case AArch64::FRINTIv4f32:
28122 case AArch64::FRINTIv8f16:
28123 case AArch64::FRINTMDr:
28124 case AArch64::FRINTMHr:
28125 case AArch64::FRINTMSr:
28126 case AArch64::FRINTMv2f32:
28127 case AArch64::FRINTMv2f64:
28128 case AArch64::FRINTMv4f16:
28129 case AArch64::FRINTMv4f32:
28130 case AArch64::FRINTMv8f16:
28131 case AArch64::FRINTNDr:
28132 case AArch64::FRINTNHr:
28133 case AArch64::FRINTNSr:
28134 case AArch64::FRINTNv2f32:
28135 case AArch64::FRINTNv2f64:
28136 case AArch64::FRINTNv4f16:
28137 case AArch64::FRINTNv4f32:
28138 case AArch64::FRINTNv8f16:
28139 case AArch64::FRINTPDr:
28140 case AArch64::FRINTPHr:
28141 case AArch64::FRINTPSr:
28142 case AArch64::FRINTPv2f32:
28143 case AArch64::FRINTPv2f64:
28144 case AArch64::FRINTPv4f16:
28145 case AArch64::FRINTPv4f32:
28146 case AArch64::FRINTPv8f16:
28147 case AArch64::FRINTXDr:
28148 case AArch64::FRINTXHr:
28149 case AArch64::FRINTXSr:
28150 case AArch64::FRINTXv2f32:
28151 case AArch64::FRINTXv2f64:
28152 case AArch64::FRINTXv4f16:
28153 case AArch64::FRINTXv4f32:
28154 case AArch64::FRINTXv8f16:
28155 case AArch64::FRINTZDr:
28156 case AArch64::FRINTZHr:
28157 case AArch64::FRINTZSr:
28158 case AArch64::FRINTZv2f32:
28159 case AArch64::FRINTZv2f64:
28160 case AArch64::FRINTZv4f16:
28161 case AArch64::FRINTZv4f32:
28162 case AArch64::FRINTZv8f16:
28163 case AArch64::FRSQRTEv1f16:
28164 case AArch64::FRSQRTEv1i32:
28165 case AArch64::FRSQRTEv1i64:
28166 case AArch64::FRSQRTEv2f32:
28167 case AArch64::FRSQRTEv2f64:
28168 case AArch64::FRSQRTEv4f16:
28169 case AArch64::FRSQRTEv4f32:
28170 case AArch64::FRSQRTEv8f16:
28171 case AArch64::FSQRTDr:
28172 case AArch64::FSQRTHr:
28173 case AArch64::FSQRTSr:
28174 case AArch64::FSQRTv2f32:
28175 case AArch64::FSQRTv2f64:
28176 case AArch64::FSQRTv4f16:
28177 case AArch64::FSQRTv4f32:
28178 case AArch64::FSQRTv8f16:
28179 case AArch64::NEGv1i64:
28180 case AArch64::NEGv2i32:
28181 case AArch64::NEGv2i64:
28182 case AArch64::NEGv4i16:
28183 case AArch64::NEGv4i32:
28184 case AArch64::NEGv8i8:
28185 case AArch64::NEGv8i16:
28186 case AArch64::NEGv16i8:
28187 case AArch64::NOTv8i8:
28188 case AArch64::NOTv16i8:
28189 case AArch64::RBITWr:
28190 case AArch64::RBITXr:
28191 case AArch64::RBITv8i8:
28192 case AArch64::RBITv16i8:
28193 case AArch64::REV16Wr:
28194 case AArch64::REV16Xr:
28195 case AArch64::REV16v8i8:
28196 case AArch64::REV16v16i8:
28197 case AArch64::REV32Xr:
28198 case AArch64::REV32v4i16:
28199 case AArch64::REV32v8i8:
28200 case AArch64::REV32v8i16:
28201 case AArch64::REV32v16i8:
28202 case AArch64::REV64v2i32:
28203 case AArch64::REV64v4i16:
28204 case AArch64::REV64v4i32:
28205 case AArch64::REV64v8i8:
28206 case AArch64::REV64v8i16:
28207 case AArch64::REV64v16i8:
28208 case AArch64::REVWr:
28209 case AArch64::REVXr:
28210 case AArch64::SADDLPv2i32_v1i64:
28211 case AArch64::SADDLPv4i16_v2i32:
28212 case AArch64::SADDLPv4i32_v2i64:
28213 case AArch64::SADDLPv8i8_v4i16:
28214 case AArch64::SADDLPv8i16_v4i32:
28215 case AArch64::SADDLPv16i8_v8i16:
28216 case AArch64::SADDLVv4i16v:
28217 case AArch64::SADDLVv4i32v:
28218 case AArch64::SADDLVv8i8v:
28219 case AArch64::SADDLVv8i16v:
28220 case AArch64::SADDLVv16i8v:
28221 case AArch64::SCVTFDSr:
28222 case AArch64::SCVTFHDr:
28223 case AArch64::SCVTFHSr:
28224 case AArch64::SCVTFSDr:
28225 case AArch64::SCVTFUWDri:
28226 case AArch64::SCVTFUWHri:
28227 case AArch64::SCVTFUWSri:
28228 case AArch64::SCVTFUXDri:
28229 case AArch64::SCVTFUXHri:
28230 case AArch64::SCVTFUXSri:
28231 case AArch64::SCVTFv1i16:
28232 case AArch64::SCVTFv1i32:
28233 case AArch64::SCVTFv1i64:
28234 case AArch64::SCVTFv2f32:
28235 case AArch64::SCVTFv2f64:
28236 case AArch64::SCVTFv4f16:
28237 case AArch64::SCVTFv4f32:
28238 case AArch64::SCVTFv8f16:
28239 case AArch64::SHA1Hrr:
28240 case AArch64::SHLLv2i32:
28241 case AArch64::SHLLv4i16:
28242 case AArch64::SHLLv4i32:
28243 case AArch64::SHLLv8i8:
28244 case AArch64::SHLLv8i16:
28245 case AArch64::SHLLv16i8:
28246 case AArch64::SMAXVv4i16v:
28247 case AArch64::SMAXVv4i32v:
28248 case AArch64::SMAXVv8i8v:
28249 case AArch64::SMAXVv8i16v:
28250 case AArch64::SMAXVv16i8v:
28251 case AArch64::SMINVv4i16v:
28252 case AArch64::SMINVv4i32v:
28253 case AArch64::SMINVv8i8v:
28254 case AArch64::SMINVv8i16v:
28255 case AArch64::SMINVv16i8v:
28256 case AArch64::SMOVvi8to32_idx0:
28257 case AArch64::SMOVvi8to64_idx0:
28258 case AArch64::SMOVvi16to32_idx0:
28259 case AArch64::SMOVvi16to64_idx0:
28260 case AArch64::SMOVvi32to64_idx0:
28261 case AArch64::SQABSv1i8:
28262 case AArch64::SQABSv1i16:
28263 case AArch64::SQABSv1i32:
28264 case AArch64::SQABSv1i64:
28265 case AArch64::SQABSv2i32:
28266 case AArch64::SQABSv2i64:
28267 case AArch64::SQABSv4i16:
28268 case AArch64::SQABSv4i32:
28269 case AArch64::SQABSv8i8:
28270 case AArch64::SQABSv8i16:
28271 case AArch64::SQABSv16i8:
28272 case AArch64::SQNEGv1i8:
28273 case AArch64::SQNEGv1i16:
28274 case AArch64::SQNEGv1i32:
28275 case AArch64::SQNEGv1i64:
28276 case AArch64::SQNEGv2i32:
28277 case AArch64::SQNEGv2i64:
28278 case AArch64::SQNEGv4i16:
28279 case AArch64::SQNEGv4i32:
28280 case AArch64::SQNEGv8i8:
28281 case AArch64::SQNEGv8i16:
28282 case AArch64::SQNEGv16i8:
28283 case AArch64::SQXTNv1i8:
28284 case AArch64::SQXTNv1i16:
28285 case AArch64::SQXTNv1i32:
28286 case AArch64::SQXTNv2i32:
28287 case AArch64::SQXTNv4i16:
28288 case AArch64::SQXTNv8i8:
28289 case AArch64::SQXTUNv1i8:
28290 case AArch64::SQXTUNv1i16:
28291 case AArch64::SQXTUNv1i32:
28292 case AArch64::SQXTUNv2i32:
28293 case AArch64::SQXTUNv4i16:
28294 case AArch64::SQXTUNv8i8:
28295 case AArch64::UADDLPv2i32_v1i64:
28296 case AArch64::UADDLPv4i16_v2i32:
28297 case AArch64::UADDLPv4i32_v2i64:
28298 case AArch64::UADDLPv8i8_v4i16:
28299 case AArch64::UADDLPv8i16_v4i32:
28300 case AArch64::UADDLPv16i8_v8i16:
28301 case AArch64::UADDLVv4i16v:
28302 case AArch64::UADDLVv4i32v:
28303 case AArch64::UADDLVv8i8v:
28304 case AArch64::UADDLVv8i16v:
28305 case AArch64::UADDLVv16i8v:
28306 case AArch64::UCVTFDSr:
28307 case AArch64::UCVTFHDr:
28308 case AArch64::UCVTFHSr:
28309 case AArch64::UCVTFSDr:
28310 case AArch64::UCVTFUWDri:
28311 case AArch64::UCVTFUWHri:
28312 case AArch64::UCVTFUWSri:
28313 case AArch64::UCVTFUXDri:
28314 case AArch64::UCVTFUXHri:
28315 case AArch64::UCVTFUXSri:
28316 case AArch64::UCVTFv1i16:
28317 case AArch64::UCVTFv1i32:
28318 case AArch64::UCVTFv1i64:
28319 case AArch64::UCVTFv2f32:
28320 case AArch64::UCVTFv2f64:
28321 case AArch64::UCVTFv4f16:
28322 case AArch64::UCVTFv4f32:
28323 case AArch64::UCVTFv8f16:
28324 case AArch64::UMAXVv4i16v:
28325 case AArch64::UMAXVv4i32v:
28326 case AArch64::UMAXVv8i8v:
28327 case AArch64::UMAXVv8i16v:
28328 case AArch64::UMAXVv16i8v:
28329 case AArch64::UMINVv4i16v:
28330 case AArch64::UMINVv4i32v:
28331 case AArch64::UMINVv8i8v:
28332 case AArch64::UMINVv8i16v:
28333 case AArch64::UMINVv16i8v:
28334 case AArch64::UMOVvi8_idx0:
28335 case AArch64::UMOVvi16_idx0:
28336 case AArch64::UMOVvi32_idx0:
28337 case AArch64::UMOVvi64_idx0:
28338 case AArch64::UQXTNv1i8:
28339 case AArch64::UQXTNv1i16:
28340 case AArch64::UQXTNv1i32:
28341 case AArch64::UQXTNv2i32:
28342 case AArch64::UQXTNv4i16:
28343 case AArch64::UQXTNv8i8:
28344 case AArch64::URECPEv2i32:
28345 case AArch64::URECPEv4i32:
28346 case AArch64::URSQRTEv2i32:
28347 case AArch64::URSQRTEv4i32:
28348 case AArch64::XTNv2i32:
28349 case AArch64::XTNv4i16:
28350 case AArch64::XTNv8i8: {
28351 switch (OpNum) {
28352 case 0:
28353 // op: Rd
28354 return 0;
28355 case 1:
28356 // op: Rn
28357 return 5;
28358 }
28359 break;
28360 }
28361 case AArch64::FMOVDi:
28362 case AArch64::FMOVHi:
28363 case AArch64::FMOVSi: {
28364 switch (OpNum) {
28365 case 0:
28366 // op: Rd
28367 return 0;
28368 case 1:
28369 // op: imm
28370 return 13;
28371 }
28372 break;
28373 }
28374 case AArch64::MOVNWi:
28375 case AArch64::MOVNXi:
28376 case AArch64::MOVZWi:
28377 case AArch64::MOVZXi: {
28378 switch (OpNum) {
28379 case 0:
28380 // op: Rd
28381 return 0;
28382 case 1:
28383 // op: imm
28384 return 5;
28385 case 2:
28386 // op: shift
28387 return 21;
28388 }
28389 break;
28390 }
28391 case AArch64::RDSVLI_XI:
28392 case AArch64::RDVLI_XI: {
28393 switch (OpNum) {
28394 case 0:
28395 // op: Rd
28396 return 0;
28397 case 1:
28398 // op: imm6
28399 return 5;
28400 }
28401 break;
28402 }
28403 case AArch64::MOVIv2s_msl:
28404 case AArch64::MOVIv4s_msl:
28405 case AArch64::MVNIv2s_msl:
28406 case AArch64::MVNIv4s_msl: {
28407 switch (OpNum) {
28408 case 0:
28409 // op: Rd
28410 return 0;
28411 case 1:
28412 // op: imm8
28413 return 5;
28414 case 2:
28415 // op: shift
28416 return 12;
28417 }
28418 break;
28419 }
28420 case AArch64::MOVIv2i32:
28421 case AArch64::MOVIv4i16:
28422 case AArch64::MOVIv4i32:
28423 case AArch64::MOVIv8i16:
28424 case AArch64::MVNIv2i32:
28425 case AArch64::MVNIv4i16:
28426 case AArch64::MVNIv4i32:
28427 case AArch64::MVNIv8i16: {
28428 switch (OpNum) {
28429 case 0:
28430 // op: Rd
28431 return 0;
28432 case 1:
28433 // op: imm8
28434 return 5;
28435 case 2:
28436 // op: shift
28437 return 13;
28438 }
28439 break;
28440 }
28441 case AArch64::FMOVv2f32_ns:
28442 case AArch64::FMOVv2f64_ns:
28443 case AArch64::FMOVv4f16_ns:
28444 case AArch64::FMOVv4f32_ns:
28445 case AArch64::FMOVv8f16_ns:
28446 case AArch64::MOVID:
28447 case AArch64::MOVIv2d_ns:
28448 case AArch64::MOVIv8b_ns:
28449 case AArch64::MOVIv16b_ns: {
28450 switch (OpNum) {
28451 case 0:
28452 // op: Rd
28453 return 0;
28454 case 1:
28455 // op: imm8
28456 return 5;
28457 }
28458 break;
28459 }
28460 case AArch64::BFMWri:
28461 case AArch64::BFMXri: {
28462 switch (OpNum) {
28463 case 0:
28464 // op: Rd
28465 return 0;
28466 case 2:
28467 // op: Rn
28468 return 5;
28469 case 3:
28470 // op: immr
28471 return 16;
28472 case 4:
28473 // op: imms
28474 return 10;
28475 }
28476 break;
28477 }
28478 case AArch64::MOVKWi:
28479 case AArch64::MOVKXi: {
28480 switch (OpNum) {
28481 case 0:
28482 // op: Rd
28483 return 0;
28484 case 2:
28485 // op: imm
28486 return 5;
28487 case 3:
28488 // op: shift
28489 return 21;
28490 }
28491 break;
28492 }
28493 case AArch64::CNTB_XPiI:
28494 case AArch64::CNTD_XPiI:
28495 case AArch64::CNTH_XPiI:
28496 case AArch64::CNTW_XPiI: {
28497 switch (OpNum) {
28498 case 0:
28499 // op: Rd
28500 return 0;
28501 case 2:
28502 // op: imm4
28503 return 16;
28504 case 1:
28505 // op: pattern
28506 return 5;
28507 }
28508 break;
28509 }
28510 case AArch64::XPACD:
28511 case AArch64::XPACI: {
28512 switch (OpNum) {
28513 case 0:
28514 // op: Rd
28515 return 0;
28516 }
28517 break;
28518 }
28519 case AArch64::DECP_XP_B:
28520 case AArch64::DECP_XP_D:
28521 case AArch64::DECP_XP_H:
28522 case AArch64::DECP_XP_S:
28523 case AArch64::INCP_XP_B:
28524 case AArch64::INCP_XP_D:
28525 case AArch64::INCP_XP_H:
28526 case AArch64::INCP_XP_S:
28527 case AArch64::SQDECP_XPWd_B:
28528 case AArch64::SQDECP_XPWd_D:
28529 case AArch64::SQDECP_XPWd_H:
28530 case AArch64::SQDECP_XPWd_S:
28531 case AArch64::SQDECP_XP_B:
28532 case AArch64::SQDECP_XP_D:
28533 case AArch64::SQDECP_XP_H:
28534 case AArch64::SQDECP_XP_S:
28535 case AArch64::SQINCP_XPWd_B:
28536 case AArch64::SQINCP_XPWd_D:
28537 case AArch64::SQINCP_XPWd_H:
28538 case AArch64::SQINCP_XPWd_S:
28539 case AArch64::SQINCP_XP_B:
28540 case AArch64::SQINCP_XP_D:
28541 case AArch64::SQINCP_XP_H:
28542 case AArch64::SQINCP_XP_S:
28543 case AArch64::UQDECP_WP_B:
28544 case AArch64::UQDECP_WP_D:
28545 case AArch64::UQDECP_WP_H:
28546 case AArch64::UQDECP_WP_S:
28547 case AArch64::UQDECP_XP_B:
28548 case AArch64::UQDECP_XP_D:
28549 case AArch64::UQDECP_XP_H:
28550 case AArch64::UQDECP_XP_S:
28551 case AArch64::UQINCP_WP_B:
28552 case AArch64::UQINCP_WP_D:
28553 case AArch64::UQINCP_WP_H:
28554 case AArch64::UQINCP_WP_S:
28555 case AArch64::UQINCP_XP_B:
28556 case AArch64::UQINCP_XP_D:
28557 case AArch64::UQINCP_XP_H:
28558 case AArch64::UQINCP_XP_S: {
28559 switch (OpNum) {
28560 case 0:
28561 // op: Rdn
28562 return 0;
28563 case 1:
28564 // op: Pg
28565 return 5;
28566 }
28567 break;
28568 }
28569 case AArch64::DECB_XPiI:
28570 case AArch64::DECD_XPiI:
28571 case AArch64::DECH_XPiI:
28572 case AArch64::DECW_XPiI:
28573 case AArch64::INCB_XPiI:
28574 case AArch64::INCD_XPiI:
28575 case AArch64::INCH_XPiI:
28576 case AArch64::INCW_XPiI:
28577 case AArch64::SQDECB_XPiI:
28578 case AArch64::SQDECB_XPiWdI:
28579 case AArch64::SQDECD_XPiI:
28580 case AArch64::SQDECD_XPiWdI:
28581 case AArch64::SQDECH_XPiI:
28582 case AArch64::SQDECH_XPiWdI:
28583 case AArch64::SQDECW_XPiI:
28584 case AArch64::SQDECW_XPiWdI:
28585 case AArch64::SQINCB_XPiI:
28586 case AArch64::SQINCB_XPiWdI:
28587 case AArch64::SQINCD_XPiI:
28588 case AArch64::SQINCD_XPiWdI:
28589 case AArch64::SQINCH_XPiI:
28590 case AArch64::SQINCH_XPiWdI:
28591 case AArch64::SQINCW_XPiI:
28592 case AArch64::SQINCW_XPiWdI:
28593 case AArch64::UQDECB_WPiI:
28594 case AArch64::UQDECB_XPiI:
28595 case AArch64::UQDECD_WPiI:
28596 case AArch64::UQDECD_XPiI:
28597 case AArch64::UQDECH_WPiI:
28598 case AArch64::UQDECH_XPiI:
28599 case AArch64::UQDECW_WPiI:
28600 case AArch64::UQDECW_XPiI:
28601 case AArch64::UQINCB_WPiI:
28602 case AArch64::UQINCB_XPiI:
28603 case AArch64::UQINCD_WPiI:
28604 case AArch64::UQINCD_XPiI:
28605 case AArch64::UQINCH_WPiI:
28606 case AArch64::UQINCH_XPiI:
28607 case AArch64::UQINCW_WPiI:
28608 case AArch64::UQINCW_XPiI: {
28609 switch (OpNum) {
28610 case 0:
28611 // op: Rdn
28612 return 0;
28613 case 2:
28614 // op: pattern
28615 return 5;
28616 case 3:
28617 // op: imm4
28618 return 16;
28619 }
28620 break;
28621 }
28622 case AArch64::RETAASPPCr:
28623 case AArch64::RETABSPPCr: {
28624 switch (OpNum) {
28625 case 0:
28626 // op: Rm
28627 return 0;
28628 }
28629 break;
28630 }
28631 case AArch64::BLRAA:
28632 case AArch64::BLRAB:
28633 case AArch64::BRAA:
28634 case AArch64::BRAB: {
28635 switch (OpNum) {
28636 case 0:
28637 // op: Rn
28638 return 5;
28639 case 1:
28640 // op: Rm
28641 return 0;
28642 }
28643 break;
28644 }
28645 case AArch64::CCMNWr:
28646 case AArch64::CCMNXr:
28647 case AArch64::CCMPWr:
28648 case AArch64::CCMPXr:
28649 case AArch64::FCCMPDrr:
28650 case AArch64::FCCMPEDrr:
28651 case AArch64::FCCMPEHrr:
28652 case AArch64::FCCMPESrr:
28653 case AArch64::FCCMPHrr:
28654 case AArch64::FCCMPSrr: {
28655 switch (OpNum) {
28656 case 0:
28657 // op: Rn
28658 return 5;
28659 case 1:
28660 // op: Rm
28661 return 16;
28662 case 2:
28663 // op: nzcv
28664 return 0;
28665 case 3:
28666 // op: cond
28667 return 12;
28668 }
28669 break;
28670 }
28671 case AArch64::RMIF: {
28672 switch (OpNum) {
28673 case 0:
28674 // op: Rn
28675 return 5;
28676 case 1:
28677 // op: imm
28678 return 15;
28679 case 2:
28680 // op: mask
28681 return 0;
28682 }
28683 break;
28684 }
28685 case AArch64::CCMNWi:
28686 case AArch64::CCMNXi:
28687 case AArch64::CCMPWi:
28688 case AArch64::CCMPXi: {
28689 switch (OpNum) {
28690 case 0:
28691 // op: Rn
28692 return 5;
28693 case 1:
28694 // op: imm
28695 return 16;
28696 case 2:
28697 // op: nzcv
28698 return 0;
28699 case 3:
28700 // op: cond
28701 return 12;
28702 }
28703 break;
28704 }
28705 case AArch64::AUTIASPPCr:
28706 case AArch64::AUTIBSPPCr:
28707 case AArch64::BLR:
28708 case AArch64::BLRAAZ:
28709 case AArch64::BLRABZ:
28710 case AArch64::BR:
28711 case AArch64::BRAAZ:
28712 case AArch64::BRABZ:
28713 case AArch64::FCMPDri:
28714 case AArch64::FCMPEDri:
28715 case AArch64::FCMPEHri:
28716 case AArch64::FCMPESri:
28717 case AArch64::FCMPHri:
28718 case AArch64::FCMPSri:
28719 case AArch64::RET:
28720 case AArch64::SETF8:
28721 case AArch64::SETF16: {
28722 switch (OpNum) {
28723 case 0:
28724 // op: Rn
28725 return 5;
28726 }
28727 break;
28728 }
28729 case AArch64::STBFADD:
28730 case AArch64::STBFADDL:
28731 case AArch64::STBFMAX:
28732 case AArch64::STBFMAXL:
28733 case AArch64::STBFMAXNM:
28734 case AArch64::STBFMAXNML:
28735 case AArch64::STBFMIN:
28736 case AArch64::STBFMINL:
28737 case AArch64::STBFMINNM:
28738 case AArch64::STBFMINNML:
28739 case AArch64::STFADDD:
28740 case AArch64::STFADDH:
28741 case AArch64::STFADDLD:
28742 case AArch64::STFADDLH:
28743 case AArch64::STFADDLS:
28744 case AArch64::STFADDS:
28745 case AArch64::STFMAXD:
28746 case AArch64::STFMAXH:
28747 case AArch64::STFMAXLD:
28748 case AArch64::STFMAXLH:
28749 case AArch64::STFMAXLS:
28750 case AArch64::STFMAXNMD:
28751 case AArch64::STFMAXNMH:
28752 case AArch64::STFMAXNMLD:
28753 case AArch64::STFMAXNMLH:
28754 case AArch64::STFMAXNMLS:
28755 case AArch64::STFMAXNMS:
28756 case AArch64::STFMAXS:
28757 case AArch64::STFMIND:
28758 case AArch64::STFMINH:
28759 case AArch64::STFMINLD:
28760 case AArch64::STFMINLH:
28761 case AArch64::STFMINLS:
28762 case AArch64::STFMINNMD:
28763 case AArch64::STFMINNMH:
28764 case AArch64::STFMINNMLD:
28765 case AArch64::STFMINNMLH:
28766 case AArch64::STFMINNMLS:
28767 case AArch64::STFMINNMS:
28768 case AArch64::STFMINS: {
28769 switch (OpNum) {
28770 case 0:
28771 // op: Rs
28772 return 16;
28773 case 1:
28774 // op: Rn
28775 return 5;
28776 }
28777 break;
28778 }
28779 case AArch64::LDRBBroW:
28780 case AArch64::LDRBBroX:
28781 case AArch64::LDRBroW:
28782 case AArch64::LDRBroX:
28783 case AArch64::LDRDroW:
28784 case AArch64::LDRDroX:
28785 case AArch64::LDRHHroW:
28786 case AArch64::LDRHHroX:
28787 case AArch64::LDRHroW:
28788 case AArch64::LDRHroX:
28789 case AArch64::LDRQroW:
28790 case AArch64::LDRQroX:
28791 case AArch64::LDRSBWroW:
28792 case AArch64::LDRSBWroX:
28793 case AArch64::LDRSBXroW:
28794 case AArch64::LDRSBXroX:
28795 case AArch64::LDRSHWroW:
28796 case AArch64::LDRSHWroX:
28797 case AArch64::LDRSHXroW:
28798 case AArch64::LDRSHXroX:
28799 case AArch64::LDRSWroW:
28800 case AArch64::LDRSWroX:
28801 case AArch64::LDRSroW:
28802 case AArch64::LDRSroX:
28803 case AArch64::LDRWroW:
28804 case AArch64::LDRWroX:
28805 case AArch64::LDRXroW:
28806 case AArch64::LDRXroX:
28807 case AArch64::PRFMroW:
28808 case AArch64::PRFMroX:
28809 case AArch64::STRBBroW:
28810 case AArch64::STRBBroX:
28811 case AArch64::STRBroW:
28812 case AArch64::STRBroX:
28813 case AArch64::STRDroW:
28814 case AArch64::STRDroX:
28815 case AArch64::STRHHroW:
28816 case AArch64::STRHHroX:
28817 case AArch64::STRHroW:
28818 case AArch64::STRHroX:
28819 case AArch64::STRQroW:
28820 case AArch64::STRQroX:
28821 case AArch64::STRSroW:
28822 case AArch64::STRSroX:
28823 case AArch64::STRWroW:
28824 case AArch64::STRWroX:
28825 case AArch64::STRXroW:
28826 case AArch64::STRXroX: {
28827 switch (OpNum) {
28828 case 0:
28829 // op: Rt
28830 return 0;
28831 case 1:
28832 // op: Rn
28833 return 5;
28834 case 2:
28835 // op: Rm
28836 return 16;
28837 case 3:
28838 // op: extend
28839 return 12;
28840 }
28841 break;
28842 }
28843 case AArch64::LDRBBui:
28844 case AArch64::LDRBui:
28845 case AArch64::LDRDui:
28846 case AArch64::LDRHHui:
28847 case AArch64::LDRHui:
28848 case AArch64::LDRQui:
28849 case AArch64::LDRSBWui:
28850 case AArch64::LDRSBXui:
28851 case AArch64::LDRSHWui:
28852 case AArch64::LDRSHXui:
28853 case AArch64::LDRSWui:
28854 case AArch64::LDRSui:
28855 case AArch64::LDRWui:
28856 case AArch64::LDRXui:
28857 case AArch64::PRFMui:
28858 case AArch64::STRBBui:
28859 case AArch64::STRBui:
28860 case AArch64::STRDui:
28861 case AArch64::STRHHui:
28862 case AArch64::STRHui:
28863 case AArch64::STRQui:
28864 case AArch64::STRSui:
28865 case AArch64::STRWui:
28866 case AArch64::STRXui: {
28867 switch (OpNum) {
28868 case 0:
28869 // op: Rt
28870 return 0;
28871 case 1:
28872 // op: Rn
28873 return 5;
28874 case 2:
28875 // op: offset
28876 return 10;
28877 }
28878 break;
28879 }
28880 case AArch64::LDAPURBi:
28881 case AArch64::LDAPURHi:
28882 case AArch64::LDAPURSBWi:
28883 case AArch64::LDAPURSBXi:
28884 case AArch64::LDAPURSHWi:
28885 case AArch64::LDAPURSHXi:
28886 case AArch64::LDAPURSWi:
28887 case AArch64::LDAPURXi:
28888 case AArch64::LDAPURi:
28889 case AArch64::LDTRBi:
28890 case AArch64::LDTRHi:
28891 case AArch64::LDTRSBWi:
28892 case AArch64::LDTRSBXi:
28893 case AArch64::LDTRSHWi:
28894 case AArch64::LDTRSHXi:
28895 case AArch64::LDTRSWi:
28896 case AArch64::LDTRWi:
28897 case AArch64::LDTRXi:
28898 case AArch64::LDURBBi:
28899 case AArch64::LDURBi:
28900 case AArch64::LDURDi:
28901 case AArch64::LDURHHi:
28902 case AArch64::LDURHi:
28903 case AArch64::LDURQi:
28904 case AArch64::LDURSBWi:
28905 case AArch64::LDURSBXi:
28906 case AArch64::LDURSHWi:
28907 case AArch64::LDURSHXi:
28908 case AArch64::LDURSWi:
28909 case AArch64::LDURSi:
28910 case AArch64::LDURWi:
28911 case AArch64::LDURXi:
28912 case AArch64::PRFUMi:
28913 case AArch64::STLURBi:
28914 case AArch64::STLURHi:
28915 case AArch64::STLURWi:
28916 case AArch64::STLURXi:
28917 case AArch64::STTRBi:
28918 case AArch64::STTRHi:
28919 case AArch64::STTRWi:
28920 case AArch64::STTRXi:
28921 case AArch64::STURBBi:
28922 case AArch64::STURBi:
28923 case AArch64::STURDi:
28924 case AArch64::STURHHi:
28925 case AArch64::STURHi:
28926 case AArch64::STURQi:
28927 case AArch64::STURSi:
28928 case AArch64::STURWi:
28929 case AArch64::STURXi: {
28930 switch (OpNum) {
28931 case 0:
28932 // op: Rt
28933 return 0;
28934 case 1:
28935 // op: Rn
28936 return 5;
28937 case 2:
28938 // op: offset
28939 return 12;
28940 }
28941 break;
28942 }
28943 case AArch64::LDAPURbi:
28944 case AArch64::LDAPURdi:
28945 case AArch64::LDAPURhi:
28946 case AArch64::LDAPURqi:
28947 case AArch64::LDAPURsi:
28948 case AArch64::STLURbi:
28949 case AArch64::STLURdi:
28950 case AArch64::STLURhi:
28951 case AArch64::STLURqi:
28952 case AArch64::STLURsi: {
28953 switch (OpNum) {
28954 case 0:
28955 // op: Rt
28956 return 0;
28957 case 1:
28958 // op: Rn
28959 return 5;
28960 case 2:
28961 // op: simm
28962 return 12;
28963 }
28964 break;
28965 }
28966 case AArch64::GCSSTR:
28967 case AArch64::GCSSTTR:
28968 case AArch64::LD64B:
28969 case AArch64::LDARB:
28970 case AArch64::LDARH:
28971 case AArch64::LDARW:
28972 case AArch64::LDARX:
28973 case AArch64::LDATXRW:
28974 case AArch64::LDATXRX:
28975 case AArch64::LDAXRB:
28976 case AArch64::LDAXRH:
28977 case AArch64::LDAXRW:
28978 case AArch64::LDAXRX:
28979 case AArch64::LDLARB:
28980 case AArch64::LDLARH:
28981 case AArch64::LDLARW:
28982 case AArch64::LDLARX:
28983 case AArch64::LDTXRWr:
28984 case AArch64::LDTXRXr:
28985 case AArch64::LDXRB:
28986 case AArch64::LDXRH:
28987 case AArch64::LDXRW:
28988 case AArch64::LDXRX:
28989 case AArch64::ST64B:
28990 case AArch64::STLLRB:
28991 case AArch64::STLLRH:
28992 case AArch64::STLLRW:
28993 case AArch64::STLLRX:
28994 case AArch64::STLRB:
28995 case AArch64::STLRH:
28996 case AArch64::STLRW:
28997 case AArch64::STLRX: {
28998 switch (OpNum) {
28999 case 0:
29000 // op: Rt
29001 return 0;
29002 case 1:
29003 // op: Rn
29004 return 5;
29005 }
29006 break;
29007 }
29008 case AArch64::LDBFADD:
29009 case AArch64::LDBFADDA:
29010 case AArch64::LDBFADDAL:
29011 case AArch64::LDBFADDL:
29012 case AArch64::LDBFMAX:
29013 case AArch64::LDBFMAXA:
29014 case AArch64::LDBFMAXAL:
29015 case AArch64::LDBFMAXL:
29016 case AArch64::LDBFMAXNM:
29017 case AArch64::LDBFMAXNMA:
29018 case AArch64::LDBFMAXNMAL:
29019 case AArch64::LDBFMAXNML:
29020 case AArch64::LDBFMIN:
29021 case AArch64::LDBFMINA:
29022 case AArch64::LDBFMINAL:
29023 case AArch64::LDBFMINL:
29024 case AArch64::LDBFMINNM:
29025 case AArch64::LDBFMINNMA:
29026 case AArch64::LDBFMINNMAL:
29027 case AArch64::LDBFMINNML:
29028 case AArch64::LDFADDAD:
29029 case AArch64::LDFADDAH:
29030 case AArch64::LDFADDALD:
29031 case AArch64::LDFADDALH:
29032 case AArch64::LDFADDALS:
29033 case AArch64::LDFADDAS:
29034 case AArch64::LDFADDD:
29035 case AArch64::LDFADDH:
29036 case AArch64::LDFADDLD:
29037 case AArch64::LDFADDLH:
29038 case AArch64::LDFADDLS:
29039 case AArch64::LDFADDS:
29040 case AArch64::LDFMAXAD:
29041 case AArch64::LDFMAXAH:
29042 case AArch64::LDFMAXALD:
29043 case AArch64::LDFMAXALH:
29044 case AArch64::LDFMAXALS:
29045 case AArch64::LDFMAXAS:
29046 case AArch64::LDFMAXD:
29047 case AArch64::LDFMAXH:
29048 case AArch64::LDFMAXLD:
29049 case AArch64::LDFMAXLH:
29050 case AArch64::LDFMAXLS:
29051 case AArch64::LDFMAXNMAD:
29052 case AArch64::LDFMAXNMAH:
29053 case AArch64::LDFMAXNMALD:
29054 case AArch64::LDFMAXNMALH:
29055 case AArch64::LDFMAXNMALS:
29056 case AArch64::LDFMAXNMAS:
29057 case AArch64::LDFMAXNMD:
29058 case AArch64::LDFMAXNMH:
29059 case AArch64::LDFMAXNMLD:
29060 case AArch64::LDFMAXNMLH:
29061 case AArch64::LDFMAXNMLS:
29062 case AArch64::LDFMAXNMS:
29063 case AArch64::LDFMAXS:
29064 case AArch64::LDFMINAD:
29065 case AArch64::LDFMINAH:
29066 case AArch64::LDFMINALD:
29067 case AArch64::LDFMINALH:
29068 case AArch64::LDFMINALS:
29069 case AArch64::LDFMINAS:
29070 case AArch64::LDFMIND:
29071 case AArch64::LDFMINH:
29072 case AArch64::LDFMINLD:
29073 case AArch64::LDFMINLH:
29074 case AArch64::LDFMINLS:
29075 case AArch64::LDFMINNMAD:
29076 case AArch64::LDFMINNMAH:
29077 case AArch64::LDFMINNMALD:
29078 case AArch64::LDFMINNMALH:
29079 case AArch64::LDFMINNMALS:
29080 case AArch64::LDFMINNMAS:
29081 case AArch64::LDFMINNMD:
29082 case AArch64::LDFMINNMH:
29083 case AArch64::LDFMINNMLD:
29084 case AArch64::LDFMINNMLH:
29085 case AArch64::LDFMINNMLS:
29086 case AArch64::LDFMINNMS:
29087 case AArch64::LDFMINS: {
29088 switch (OpNum) {
29089 case 0:
29090 // op: Rt
29091 return 0;
29092 case 1:
29093 // op: Rs
29094 return 16;
29095 case 2:
29096 // op: Rn
29097 return 5;
29098 }
29099 break;
29100 }
29101 case AArch64::LDNPDi:
29102 case AArch64::LDNPQi:
29103 case AArch64::LDNPSi:
29104 case AArch64::LDNPWi:
29105 case AArch64::LDNPXi:
29106 case AArch64::LDPDi:
29107 case AArch64::LDPQi:
29108 case AArch64::LDPSWi:
29109 case AArch64::LDPSi:
29110 case AArch64::LDPWi:
29111 case AArch64::LDPXi:
29112 case AArch64::LDTNPQi:
29113 case AArch64::LDTNPXi:
29114 case AArch64::LDTPQi:
29115 case AArch64::LDTPi:
29116 case AArch64::STGPi:
29117 case AArch64::STNPDi:
29118 case AArch64::STNPQi:
29119 case AArch64::STNPSi:
29120 case AArch64::STNPWi:
29121 case AArch64::STNPXi:
29122 case AArch64::STPDi:
29123 case AArch64::STPQi:
29124 case AArch64::STPSi:
29125 case AArch64::STPWi:
29126 case AArch64::STPXi:
29127 case AArch64::STTNPQi:
29128 case AArch64::STTNPXi:
29129 case AArch64::STTPQi:
29130 case AArch64::STTPi: {
29131 switch (OpNum) {
29132 case 0:
29133 // op: Rt
29134 return 0;
29135 case 1:
29136 // op: Rt2
29137 return 10;
29138 case 2:
29139 // op: Rn
29140 return 5;
29141 case 3:
29142 // op: offset
29143 return 15;
29144 }
29145 break;
29146 }
29147 case AArch64::LDAXPW:
29148 case AArch64::LDAXPX:
29149 case AArch64::LDXPW:
29150 case AArch64::LDXPX: {
29151 switch (OpNum) {
29152 case 0:
29153 // op: Rt
29154 return 0;
29155 case 1:
29156 // op: Rt2
29157 return 10;
29158 case 2:
29159 // op: Rn
29160 return 5;
29161 }
29162 break;
29163 }
29164 case AArch64::TBNZW:
29165 case AArch64::TBNZX:
29166 case AArch64::TBZW:
29167 case AArch64::TBZX: {
29168 switch (OpNum) {
29169 case 0:
29170 // op: Rt
29171 return 0;
29172 case 1:
29173 // op: bit_off
29174 return 19;
29175 case 2:
29176 // op: target
29177 return 5;
29178 }
29179 break;
29180 }
29181 case AArch64::CBEQWri:
29182 case AArch64::CBEQXri:
29183 case AArch64::CBGTWri:
29184 case AArch64::CBGTXri:
29185 case AArch64::CBHIWri:
29186 case AArch64::CBHIXri:
29187 case AArch64::CBLOWri:
29188 case AArch64::CBLOXri:
29189 case AArch64::CBLTWri:
29190 case AArch64::CBLTXri:
29191 case AArch64::CBNEWri:
29192 case AArch64::CBNEXri: {
29193 switch (OpNum) {
29194 case 0:
29195 // op: Rt
29196 return 0;
29197 case 1:
29198 // op: imm
29199 return 15;
29200 case 2:
29201 // op: target
29202 return 5;
29203 }
29204 break;
29205 }
29206 case AArch64::LDRDl:
29207 case AArch64::LDRQl:
29208 case AArch64::LDRSWl:
29209 case AArch64::LDRSl:
29210 case AArch64::LDRWl:
29211 case AArch64::LDRXl:
29212 case AArch64::PRFMl: {
29213 switch (OpNum) {
29214 case 0:
29215 // op: Rt
29216 return 0;
29217 case 1:
29218 // op: label
29219 return 5;
29220 }
29221 break;
29222 }
29223 case AArch64::SYSLxt: {
29224 switch (OpNum) {
29225 case 0:
29226 // op: Rt
29227 return 0;
29228 case 1:
29229 // op: op1
29230 return 16;
29231 case 2:
29232 // op: Cn
29233 return 12;
29234 case 3:
29235 // op: Cm
29236 return 8;
29237 case 4:
29238 // op: op2
29239 return 5;
29240 }
29241 break;
29242 }
29243 case AArch64::MRRS:
29244 case AArch64::MRS: {
29245 switch (OpNum) {
29246 case 0:
29247 // op: Rt
29248 return 0;
29249 case 1:
29250 // op: systemreg
29251 return 5;
29252 }
29253 break;
29254 }
29255 case AArch64::CBNZW:
29256 case AArch64::CBNZX:
29257 case AArch64::CBZW:
29258 case AArch64::CBZX: {
29259 switch (OpNum) {
29260 case 0:
29261 // op: Rt
29262 return 0;
29263 case 1:
29264 // op: target
29265 return 5;
29266 }
29267 break;
29268 }
29269 case AArch64::RPRFM: {
29270 switch (OpNum) {
29271 case 0:
29272 // op: Rt
29273 return 0;
29274 case 2:
29275 // op: Rn
29276 return 5;
29277 case 1:
29278 // op: Rm
29279 return 16;
29280 }
29281 break;
29282 }
29283 case AArch64::LDIAPPW:
29284 case AArch64::LDIAPPX:
29285 case AArch64::STILPW:
29286 case AArch64::STILPX: {
29287 switch (OpNum) {
29288 case 0:
29289 // op: Rt
29290 return 0;
29291 case 2:
29292 // op: Rn
29293 return 5;
29294 case 1:
29295 // op: Rt2
29296 return 16;
29297 }
29298 break;
29299 }
29300 case AArch64::GCSPOPM:
29301 case AArch64::GCSPUSHM:
29302 case AArch64::GCSSS1:
29303 case AArch64::GCSSS2:
29304 case AArch64::TRCIT:
29305 case AArch64::TSTART:
29306 case AArch64::TTEST:
29307 case AArch64::WFET:
29308 case AArch64::WFIT: {
29309 switch (OpNum) {
29310 case 0:
29311 // op: Rt
29312 return 0;
29313 }
29314 break;
29315 }
29316 case AArch64::BCAX:
29317 case AArch64::EOR3:
29318 case AArch64::SM3SS1: {
29319 switch (OpNum) {
29320 case 0:
29321 // op: Vd
29322 return 0;
29323 case 1:
29324 // op: Vn
29325 return 5;
29326 case 2:
29327 // op: Vm
29328 return 16;
29329 case 3:
29330 // op: Va
29331 return 10;
29332 }
29333 break;
29334 }
29335 case AArch64::RAX1:
29336 case AArch64::SM4ENCKEY:
29337 case AArch64::TBLv8i8Four:
29338 case AArch64::TBLv8i8One:
29339 case AArch64::TBLv8i8Three:
29340 case AArch64::TBLv8i8Two:
29341 case AArch64::TBLv16i8Four:
29342 case AArch64::TBLv16i8One:
29343 case AArch64::TBLv16i8Three:
29344 case AArch64::TBLv16i8Two: {
29345 switch (OpNum) {
29346 case 0:
29347 // op: Vd
29348 return 0;
29349 case 1:
29350 // op: Vn
29351 return 5;
29352 case 2:
29353 // op: Vm
29354 return 16;
29355 }
29356 break;
29357 }
29358 case AArch64::XAR: {
29359 switch (OpNum) {
29360 case 0:
29361 // op: Vd
29362 return 0;
29363 case 1:
29364 // op: Vn
29365 return 5;
29366 case 3:
29367 // op: imm
29368 return 10;
29369 case 2:
29370 // op: Vm
29371 return 16;
29372 }
29373 break;
29374 }
29375 case AArch64::ADDQV_VPZ_B:
29376 case AArch64::ADDQV_VPZ_D:
29377 case AArch64::ADDQV_VPZ_H:
29378 case AArch64::ADDQV_VPZ_S:
29379 case AArch64::ANDQV_VPZ_B:
29380 case AArch64::ANDQV_VPZ_D:
29381 case AArch64::ANDQV_VPZ_H:
29382 case AArch64::ANDQV_VPZ_S:
29383 case AArch64::EORQV_VPZ_B:
29384 case AArch64::EORQV_VPZ_D:
29385 case AArch64::EORQV_VPZ_H:
29386 case AArch64::EORQV_VPZ_S:
29387 case AArch64::FADDQV_D:
29388 case AArch64::FADDQV_H:
29389 case AArch64::FADDQV_S:
29390 case AArch64::FMAXNMQV_D:
29391 case AArch64::FMAXNMQV_H:
29392 case AArch64::FMAXNMQV_S:
29393 case AArch64::FMAXQV_D:
29394 case AArch64::FMAXQV_H:
29395 case AArch64::FMAXQV_S:
29396 case AArch64::FMINNMQV_D:
29397 case AArch64::FMINNMQV_H:
29398 case AArch64::FMINNMQV_S:
29399 case AArch64::FMINQV_D:
29400 case AArch64::FMINQV_H:
29401 case AArch64::FMINQV_S:
29402 case AArch64::ORQV_VPZ_B:
29403 case AArch64::ORQV_VPZ_D:
29404 case AArch64::ORQV_VPZ_H:
29405 case AArch64::ORQV_VPZ_S:
29406 case AArch64::SMAXQV_VPZ_B:
29407 case AArch64::SMAXQV_VPZ_D:
29408 case AArch64::SMAXQV_VPZ_H:
29409 case AArch64::SMAXQV_VPZ_S:
29410 case AArch64::SMINQV_VPZ_B:
29411 case AArch64::SMINQV_VPZ_D:
29412 case AArch64::SMINQV_VPZ_H:
29413 case AArch64::SMINQV_VPZ_S:
29414 case AArch64::UMAXQV_VPZ_B:
29415 case AArch64::UMAXQV_VPZ_D:
29416 case AArch64::UMAXQV_VPZ_H:
29417 case AArch64::UMAXQV_VPZ_S:
29418 case AArch64::UMINQV_VPZ_B:
29419 case AArch64::UMINQV_VPZ_D:
29420 case AArch64::UMINQV_VPZ_H:
29421 case AArch64::UMINQV_VPZ_S: {
29422 switch (OpNum) {
29423 case 0:
29424 // op: Vd
29425 return 0;
29426 case 2:
29427 // op: Zn
29428 return 5;
29429 case 1:
29430 // op: Pg
29431 return 10;
29432 }
29433 break;
29434 }
29435 case AArch64::LD1Fourv1d:
29436 case AArch64::LD1Fourv2d:
29437 case AArch64::LD1Fourv2s:
29438 case AArch64::LD1Fourv4h:
29439 case AArch64::LD1Fourv4s:
29440 case AArch64::LD1Fourv8b:
29441 case AArch64::LD1Fourv8h:
29442 case AArch64::LD1Fourv16b:
29443 case AArch64::LD1Onev1d:
29444 case AArch64::LD1Onev2d:
29445 case AArch64::LD1Onev2s:
29446 case AArch64::LD1Onev4h:
29447 case AArch64::LD1Onev4s:
29448 case AArch64::LD1Onev8b:
29449 case AArch64::LD1Onev8h:
29450 case AArch64::LD1Onev16b:
29451 case AArch64::LD1Rv1d:
29452 case AArch64::LD1Rv2d:
29453 case AArch64::LD1Rv2s:
29454 case AArch64::LD1Rv4h:
29455 case AArch64::LD1Rv4s:
29456 case AArch64::LD1Rv8b:
29457 case AArch64::LD1Rv8h:
29458 case AArch64::LD1Rv16b:
29459 case AArch64::LD1Threev1d:
29460 case AArch64::LD1Threev2d:
29461 case AArch64::LD1Threev2s:
29462 case AArch64::LD1Threev4h:
29463 case AArch64::LD1Threev4s:
29464 case AArch64::LD1Threev8b:
29465 case AArch64::LD1Threev8h:
29466 case AArch64::LD1Threev16b:
29467 case AArch64::LD1Twov1d:
29468 case AArch64::LD1Twov2d:
29469 case AArch64::LD1Twov2s:
29470 case AArch64::LD1Twov4h:
29471 case AArch64::LD1Twov4s:
29472 case AArch64::LD1Twov8b:
29473 case AArch64::LD1Twov8h:
29474 case AArch64::LD1Twov16b:
29475 case AArch64::LD2Rv1d:
29476 case AArch64::LD2Rv2d:
29477 case AArch64::LD2Rv2s:
29478 case AArch64::LD2Rv4h:
29479 case AArch64::LD2Rv4s:
29480 case AArch64::LD2Rv8b:
29481 case AArch64::LD2Rv8h:
29482 case AArch64::LD2Rv16b:
29483 case AArch64::LD2Twov2d:
29484 case AArch64::LD2Twov2s:
29485 case AArch64::LD2Twov4h:
29486 case AArch64::LD2Twov4s:
29487 case AArch64::LD2Twov8b:
29488 case AArch64::LD2Twov8h:
29489 case AArch64::LD2Twov16b:
29490 case AArch64::LD3Rv1d:
29491 case AArch64::LD3Rv2d:
29492 case AArch64::LD3Rv2s:
29493 case AArch64::LD3Rv4h:
29494 case AArch64::LD3Rv4s:
29495 case AArch64::LD3Rv8b:
29496 case AArch64::LD3Rv8h:
29497 case AArch64::LD3Rv16b:
29498 case AArch64::LD3Threev2d:
29499 case AArch64::LD3Threev2s:
29500 case AArch64::LD3Threev4h:
29501 case AArch64::LD3Threev4s:
29502 case AArch64::LD3Threev8b:
29503 case AArch64::LD3Threev8h:
29504 case AArch64::LD3Threev16b:
29505 case AArch64::LD4Fourv2d:
29506 case AArch64::LD4Fourv2s:
29507 case AArch64::LD4Fourv4h:
29508 case AArch64::LD4Fourv4s:
29509 case AArch64::LD4Fourv8b:
29510 case AArch64::LD4Fourv8h:
29511 case AArch64::LD4Fourv16b:
29512 case AArch64::LD4Rv1d:
29513 case AArch64::LD4Rv2d:
29514 case AArch64::LD4Rv2s:
29515 case AArch64::LD4Rv4h:
29516 case AArch64::LD4Rv4s:
29517 case AArch64::LD4Rv8b:
29518 case AArch64::LD4Rv8h:
29519 case AArch64::LD4Rv16b:
29520 case AArch64::ST1Fourv1d:
29521 case AArch64::ST1Fourv2d:
29522 case AArch64::ST1Fourv2s:
29523 case AArch64::ST1Fourv4h:
29524 case AArch64::ST1Fourv4s:
29525 case AArch64::ST1Fourv8b:
29526 case AArch64::ST1Fourv8h:
29527 case AArch64::ST1Fourv16b:
29528 case AArch64::ST1Onev1d:
29529 case AArch64::ST1Onev2d:
29530 case AArch64::ST1Onev2s:
29531 case AArch64::ST1Onev4h:
29532 case AArch64::ST1Onev4s:
29533 case AArch64::ST1Onev8b:
29534 case AArch64::ST1Onev8h:
29535 case AArch64::ST1Onev16b:
29536 case AArch64::ST1Threev1d:
29537 case AArch64::ST1Threev2d:
29538 case AArch64::ST1Threev2s:
29539 case AArch64::ST1Threev4h:
29540 case AArch64::ST1Threev4s:
29541 case AArch64::ST1Threev8b:
29542 case AArch64::ST1Threev8h:
29543 case AArch64::ST1Threev16b:
29544 case AArch64::ST1Twov1d:
29545 case AArch64::ST1Twov2d:
29546 case AArch64::ST1Twov2s:
29547 case AArch64::ST1Twov4h:
29548 case AArch64::ST1Twov4s:
29549 case AArch64::ST1Twov8b:
29550 case AArch64::ST1Twov8h:
29551 case AArch64::ST1Twov16b:
29552 case AArch64::ST2Twov2d:
29553 case AArch64::ST2Twov2s:
29554 case AArch64::ST2Twov4h:
29555 case AArch64::ST2Twov4s:
29556 case AArch64::ST2Twov8b:
29557 case AArch64::ST2Twov8h:
29558 case AArch64::ST2Twov16b:
29559 case AArch64::ST3Threev2d:
29560 case AArch64::ST3Threev2s:
29561 case AArch64::ST3Threev4h:
29562 case AArch64::ST3Threev4s:
29563 case AArch64::ST3Threev8b:
29564 case AArch64::ST3Threev8h:
29565 case AArch64::ST3Threev16b:
29566 case AArch64::ST4Fourv2d:
29567 case AArch64::ST4Fourv2s:
29568 case AArch64::ST4Fourv4h:
29569 case AArch64::ST4Fourv4s:
29570 case AArch64::ST4Fourv8b:
29571 case AArch64::ST4Fourv8h:
29572 case AArch64::ST4Fourv16b: {
29573 switch (OpNum) {
29574 case 0:
29575 // op: Vt
29576 return 0;
29577 case 1:
29578 // op: Rn
29579 return 5;
29580 }
29581 break;
29582 }
29583 case AArch64::STL1: {
29584 switch (OpNum) {
29585 case 0:
29586 // op: Vt
29587 return 0;
29588 case 2:
29589 // op: Rn
29590 return 5;
29591 case 1:
29592 // op: Q
29593 return 30;
29594 }
29595 break;
29596 }
29597 case AArch64::ST1i8:
29598 case AArch64::ST2i8:
29599 case AArch64::ST3i8:
29600 case AArch64::ST4i8: {
29601 switch (OpNum) {
29602 case 0:
29603 // op: Vt
29604 return 0;
29605 case 2:
29606 // op: Rn
29607 return 5;
29608 case 1:
29609 // op: idx
29610 return 10;
29611 }
29612 break;
29613 }
29614 case AArch64::ST1i16:
29615 case AArch64::ST2i16:
29616 case AArch64::ST3i16:
29617 case AArch64::ST4i16: {
29618 switch (OpNum) {
29619 case 0:
29620 // op: Vt
29621 return 0;
29622 case 2:
29623 // op: Rn
29624 return 5;
29625 case 1:
29626 // op: idx
29627 return 11;
29628 }
29629 break;
29630 }
29631 case AArch64::ST1i32:
29632 case AArch64::ST2i32:
29633 case AArch64::ST3i32:
29634 case AArch64::ST4i32: {
29635 switch (OpNum) {
29636 case 0:
29637 // op: Vt
29638 return 0;
29639 case 2:
29640 // op: Rn
29641 return 5;
29642 case 1:
29643 // op: idx
29644 return 12;
29645 }
29646 break;
29647 }
29648 case AArch64::ST1i64:
29649 case AArch64::ST2i64:
29650 case AArch64::ST3i64:
29651 case AArch64::ST4i64: {
29652 switch (OpNum) {
29653 case 0:
29654 // op: Vt
29655 return 0;
29656 case 2:
29657 // op: Rn
29658 return 5;
29659 case 1:
29660 // op: idx
29661 return 30;
29662 }
29663 break;
29664 }
29665 case AArch64::STLTXRW:
29666 case AArch64::STLTXRX:
29667 case AArch64::STLXRB:
29668 case AArch64::STLXRH:
29669 case AArch64::STLXRW:
29670 case AArch64::STLXRX:
29671 case AArch64::STXRB:
29672 case AArch64::STXRH:
29673 case AArch64::STXRW:
29674 case AArch64::STXRX: {
29675 switch (OpNum) {
29676 case 0:
29677 // op: Ws
29678 return 16;
29679 case 1:
29680 // op: Rt
29681 return 0;
29682 case 2:
29683 // op: Rn
29684 return 5;
29685 }
29686 break;
29687 }
29688 case AArch64::STLXPW:
29689 case AArch64::STLXPX:
29690 case AArch64::STXPW:
29691 case AArch64::STXPX: {
29692 switch (OpNum) {
29693 case 0:
29694 // op: Ws
29695 return 16;
29696 case 1:
29697 // op: Rt
29698 return 0;
29699 case 2:
29700 // op: Rt2
29701 return 10;
29702 case 3:
29703 // op: Rn
29704 return 5;
29705 }
29706 break;
29707 }
29708 case AArch64::ADR:
29709 case AArch64::ADRP: {
29710 switch (OpNum) {
29711 case 0:
29712 // op: Xd
29713 return 0;
29714 case 1:
29715 // op: label
29716 return 5;
29717 }
29718 break;
29719 }
29720 case AArch64::APAS: {
29721 switch (OpNum) {
29722 case 0:
29723 // op: Xt
29724 return 0;
29725 }
29726 break;
29727 }
29728 case AArch64::BFTMOPA_M2ZZZI_HtoH:
29729 case AArch64::BFTMOPA_M2ZZZI_HtoS:
29730 case AArch64::FTMOPA_M2ZZZI_BtoH:
29731 case AArch64::FTMOPA_M2ZZZI_BtoS:
29732 case AArch64::FTMOPA_M2ZZZI_HtoH:
29733 case AArch64::FTMOPA_M2ZZZI_HtoS:
29734 case AArch64::FTMOPA_M2ZZZI_StoS:
29735 case AArch64::STMOPA_M2ZZZI_BtoS:
29736 case AArch64::STMOPA_M2ZZZI_HtoS:
29737 case AArch64::SUTMOPA_M2ZZZI_BtoS:
29738 case AArch64::USTMOPA_M2ZZZI_BtoS:
29739 case AArch64::UTMOPA_M2ZZZI_BtoS:
29740 case AArch64::UTMOPA_M2ZZZI_HtoS: {
29741 switch (OpNum) {
29742 case 0:
29743 // op: ZAda
29744 return 0;
29745 case 2:
29746 // op: Zn
29747 return 6;
29748 case 3:
29749 // op: Zm
29750 return 16;
29751 case 4:
29752 // op: Zk
29753 return 10;
29754 case 5:
29755 // op: imm
29756 return 4;
29757 }
29758 break;
29759 }
29760 case AArch64::BFMOP4A_M2Z2Z_H:
29761 case AArch64::BFMOP4A_M2Z2Z_S:
29762 case AArch64::BFMOP4A_M2ZZ_H:
29763 case AArch64::BFMOP4A_M2ZZ_S:
29764 case AArch64::BFMOP4A_MZ2Z_H:
29765 case AArch64::BFMOP4A_MZ2Z_S:
29766 case AArch64::BFMOP4A_MZZ_H:
29767 case AArch64::BFMOP4A_MZZ_S:
29768 case AArch64::BFMOP4S_M2Z2Z_H:
29769 case AArch64::BFMOP4S_M2Z2Z_S:
29770 case AArch64::BFMOP4S_M2ZZ_H:
29771 case AArch64::BFMOP4S_M2ZZ_S:
29772 case AArch64::BFMOP4S_MZ2Z_H:
29773 case AArch64::BFMOP4S_MZ2Z_S:
29774 case AArch64::BFMOP4S_MZZ_H:
29775 case AArch64::BFMOP4S_MZZ_S:
29776 case AArch64::FMOP4A_M2Z2Z_BtoH:
29777 case AArch64::FMOP4A_M2Z2Z_BtoS:
29778 case AArch64::FMOP4A_M2Z2Z_D:
29779 case AArch64::FMOP4A_M2Z2Z_H:
29780 case AArch64::FMOP4A_M2Z2Z_HtoS:
29781 case AArch64::FMOP4A_M2Z2Z_S:
29782 case AArch64::FMOP4A_M2ZZ_BtoH:
29783 case AArch64::FMOP4A_M2ZZ_BtoS:
29784 case AArch64::FMOP4A_M2ZZ_D:
29785 case AArch64::FMOP4A_M2ZZ_H:
29786 case AArch64::FMOP4A_M2ZZ_HtoS:
29787 case AArch64::FMOP4A_M2ZZ_S:
29788 case AArch64::FMOP4A_MZ2Z_BtoH:
29789 case AArch64::FMOP4A_MZ2Z_BtoS:
29790 case AArch64::FMOP4A_MZ2Z_D:
29791 case AArch64::FMOP4A_MZ2Z_H:
29792 case AArch64::FMOP4A_MZ2Z_HtoS:
29793 case AArch64::FMOP4A_MZ2Z_S:
29794 case AArch64::FMOP4A_MZZ_BtoH:
29795 case AArch64::FMOP4A_MZZ_BtoS:
29796 case AArch64::FMOP4A_MZZ_D:
29797 case AArch64::FMOP4A_MZZ_H:
29798 case AArch64::FMOP4A_MZZ_HtoS:
29799 case AArch64::FMOP4A_MZZ_S:
29800 case AArch64::FMOP4S_M2Z2Z_D:
29801 case AArch64::FMOP4S_M2Z2Z_H:
29802 case AArch64::FMOP4S_M2Z2Z_HtoS:
29803 case AArch64::FMOP4S_M2Z2Z_S:
29804 case AArch64::FMOP4S_M2ZZ_D:
29805 case AArch64::FMOP4S_M2ZZ_H:
29806 case AArch64::FMOP4S_M2ZZ_HtoS:
29807 case AArch64::FMOP4S_M2ZZ_S:
29808 case AArch64::FMOP4S_MZ2Z_D:
29809 case AArch64::FMOP4S_MZ2Z_H:
29810 case AArch64::FMOP4S_MZ2Z_HtoS:
29811 case AArch64::FMOP4S_MZ2Z_S:
29812 case AArch64::FMOP4S_MZZ_D:
29813 case AArch64::FMOP4S_MZZ_H:
29814 case AArch64::FMOP4S_MZZ_HtoS:
29815 case AArch64::FMOP4S_MZZ_S:
29816 case AArch64::SMOP4A_M2Z2Z_BToS:
29817 case AArch64::SMOP4A_M2Z2Z_HToS:
29818 case AArch64::SMOP4A_M2Z2Z_HtoD:
29819 case AArch64::SMOP4A_M2ZZ_BToS:
29820 case AArch64::SMOP4A_M2ZZ_HToS:
29821 case AArch64::SMOP4A_M2ZZ_HtoD:
29822 case AArch64::SMOP4A_MZ2Z_BToS:
29823 case AArch64::SMOP4A_MZ2Z_HToS:
29824 case AArch64::SMOP4A_MZ2Z_HtoD:
29825 case AArch64::SMOP4A_MZZ_BToS:
29826 case AArch64::SMOP4A_MZZ_HToS:
29827 case AArch64::SMOP4A_MZZ_HtoD:
29828 case AArch64::SMOP4S_M2Z2Z_BToS:
29829 case AArch64::SMOP4S_M2Z2Z_HToS:
29830 case AArch64::SMOP4S_M2Z2Z_HtoD:
29831 case AArch64::SMOP4S_M2ZZ_BToS:
29832 case AArch64::SMOP4S_M2ZZ_HToS:
29833 case AArch64::SMOP4S_M2ZZ_HtoD:
29834 case AArch64::SMOP4S_MZ2Z_BToS:
29835 case AArch64::SMOP4S_MZ2Z_HToS:
29836 case AArch64::SMOP4S_MZ2Z_HtoD:
29837 case AArch64::SMOP4S_MZZ_BToS:
29838 case AArch64::SMOP4S_MZZ_HToS:
29839 case AArch64::SMOP4S_MZZ_HtoD:
29840 case AArch64::SUMOP4A_M2Z2Z_BToS:
29841 case AArch64::SUMOP4A_M2Z2Z_HtoD:
29842 case AArch64::SUMOP4A_M2ZZ_BToS:
29843 case AArch64::SUMOP4A_M2ZZ_HtoD:
29844 case AArch64::SUMOP4A_MZ2Z_BToS:
29845 case AArch64::SUMOP4A_MZ2Z_HtoD:
29846 case AArch64::SUMOP4A_MZZ_BToS:
29847 case AArch64::SUMOP4A_MZZ_HtoD:
29848 case AArch64::SUMOP4S_M2Z2Z_BToS:
29849 case AArch64::SUMOP4S_M2Z2Z_HtoD:
29850 case AArch64::SUMOP4S_M2ZZ_BToS:
29851 case AArch64::SUMOP4S_M2ZZ_HtoD:
29852 case AArch64::SUMOP4S_MZ2Z_BToS:
29853 case AArch64::SUMOP4S_MZ2Z_HtoD:
29854 case AArch64::SUMOP4S_MZZ_BToS:
29855 case AArch64::SUMOP4S_MZZ_HtoD:
29856 case AArch64::UMOP4A_M2Z2Z_BToS:
29857 case AArch64::UMOP4A_M2Z2Z_HToS:
29858 case AArch64::UMOP4A_M2Z2Z_HtoD:
29859 case AArch64::UMOP4A_M2ZZ_BToS:
29860 case AArch64::UMOP4A_M2ZZ_HToS:
29861 case AArch64::UMOP4A_M2ZZ_HtoD:
29862 case AArch64::UMOP4A_MZ2Z_BToS:
29863 case AArch64::UMOP4A_MZ2Z_HToS:
29864 case AArch64::UMOP4A_MZ2Z_HtoD:
29865 case AArch64::UMOP4A_MZZ_BToS:
29866 case AArch64::UMOP4A_MZZ_HToS:
29867 case AArch64::UMOP4A_MZZ_HtoD:
29868 case AArch64::UMOP4S_M2Z2Z_BToS:
29869 case AArch64::UMOP4S_M2Z2Z_HToS:
29870 case AArch64::UMOP4S_M2Z2Z_HtoD:
29871 case AArch64::UMOP4S_M2ZZ_BToS:
29872 case AArch64::UMOP4S_M2ZZ_HToS:
29873 case AArch64::UMOP4S_M2ZZ_HtoD:
29874 case AArch64::UMOP4S_MZ2Z_BToS:
29875 case AArch64::UMOP4S_MZ2Z_HToS:
29876 case AArch64::UMOP4S_MZ2Z_HtoD:
29877 case AArch64::UMOP4S_MZZ_BToS:
29878 case AArch64::UMOP4S_MZZ_HToS:
29879 case AArch64::UMOP4S_MZZ_HtoD:
29880 case AArch64::USMOP4A_M2Z2Z_BToS:
29881 case AArch64::USMOP4A_M2Z2Z_HtoD:
29882 case AArch64::USMOP4A_M2ZZ_BToS:
29883 case AArch64::USMOP4A_M2ZZ_HtoD:
29884 case AArch64::USMOP4A_MZ2Z_BToS:
29885 case AArch64::USMOP4A_MZ2Z_HtoD:
29886 case AArch64::USMOP4A_MZZ_BToS:
29887 case AArch64::USMOP4A_MZZ_HtoD:
29888 case AArch64::USMOP4S_M2Z2Z_BToS:
29889 case AArch64::USMOP4S_M2Z2Z_HtoD:
29890 case AArch64::USMOP4S_M2ZZ_BToS:
29891 case AArch64::USMOP4S_M2ZZ_HtoD:
29892 case AArch64::USMOP4S_MZ2Z_BToS:
29893 case AArch64::USMOP4S_MZ2Z_HtoD:
29894 case AArch64::USMOP4S_MZZ_BToS:
29895 case AArch64::USMOP4S_MZZ_HtoD: {
29896 switch (OpNum) {
29897 case 0:
29898 // op: ZAda
29899 return 0;
29900 case 2:
29901 // op: Zn
29902 return 6;
29903 case 3:
29904 // op: Zm
29905 return 17;
29906 }
29907 break;
29908 }
29909 case AArch64::RBIT_ZPzZ_B:
29910 case AArch64::RBIT_ZPzZ_D:
29911 case AArch64::RBIT_ZPzZ_H:
29912 case AArch64::RBIT_ZPzZ_S:
29913 case AArch64::REVB_ZPzZ_D:
29914 case AArch64::REVB_ZPzZ_H:
29915 case AArch64::REVB_ZPzZ_S:
29916 case AArch64::REVD_ZPzZ:
29917 case AArch64::REVH_ZPzZ_D:
29918 case AArch64::REVH_ZPzZ_S:
29919 case AArch64::REVW_ZPzZ_D: {
29920 switch (OpNum) {
29921 case 0:
29922 // op: Zd
29923 return 0;
29924 case 1:
29925 // op: Pg
29926 return 10;
29927 case 2:
29928 // op: Zn
29929 return 5;
29930 }
29931 break;
29932 }
29933 case AArch64::CPY_ZPzI_B:
29934 case AArch64::CPY_ZPzI_D:
29935 case AArch64::CPY_ZPzI_H:
29936 case AArch64::CPY_ZPzI_S: {
29937 switch (OpNum) {
29938 case 0:
29939 // op: Zd
29940 return 0;
29941 case 1:
29942 // op: Pg
29943 return 16;
29944 case 2:
29945 // op: imm
29946 return 5;
29947 }
29948 break;
29949 }
29950 case AArch64::LUTI2_ZZZI_H: {
29951 switch (OpNum) {
29952 case 0:
29953 // op: Zd
29954 return 0;
29955 case 1:
29956 // op: Zn
29957 return 5;
29958 case 2:
29959 // op: Zm
29960 return 16;
29961 case 3:
29962 // op: idx
29963 return 12;
29964 }
29965 break;
29966 }
29967 case AArch64::LUTI2_ZZZI_B:
29968 case AArch64::LUTI4_Z2ZZI:
29969 case AArch64::LUTI4_ZZZI_H: {
29970 switch (OpNum) {
29971 case 0:
29972 // op: Zd
29973 return 0;
29974 case 1:
29975 // op: Zn
29976 return 5;
29977 case 2:
29978 // op: Zm
29979 return 16;
29980 case 3:
29981 // op: idx
29982 return 22;
29983 }
29984 break;
29985 }
29986 case AArch64::LUTI4_ZZZI_B: {
29987 switch (OpNum) {
29988 case 0:
29989 // op: Zd
29990 return 0;
29991 case 1:
29992 // op: Zn
29993 return 5;
29994 case 2:
29995 // op: Zm
29996 return 16;
29997 case 3:
29998 // op: idx
29999 return 23;
30000 }
30001 break;
30002 }
30003 case AArch64::SMULLB_ZZZI_D:
30004 case AArch64::SMULLB_ZZZI_S:
30005 case AArch64::SMULLT_ZZZI_D:
30006 case AArch64::SMULLT_ZZZI_S:
30007 case AArch64::SQDMULLB_ZZZI_D:
30008 case AArch64::SQDMULLB_ZZZI_S:
30009 case AArch64::SQDMULLT_ZZZI_D:
30010 case AArch64::SQDMULLT_ZZZI_S:
30011 case AArch64::UMULLB_ZZZI_D:
30012 case AArch64::UMULLB_ZZZI_S:
30013 case AArch64::UMULLT_ZZZI_D:
30014 case AArch64::UMULLT_ZZZI_S: {
30015 switch (OpNum) {
30016 case 0:
30017 // op: Zd
30018 return 0;
30019 case 1:
30020 // op: Zn
30021 return 5;
30022 case 2:
30023 // op: Zm
30024 return 16;
30025 case 3:
30026 // op: iop
30027 return 11;
30028 }
30029 break;
30030 }
30031 case AArch64::BFMUL_ZZZI:
30032 case AArch64::FMUL_ZZZI_H:
30033 case AArch64::FMUL_ZZZI_S:
30034 case AArch64::MUL_ZZZI_H:
30035 case AArch64::MUL_ZZZI_S:
30036 case AArch64::SQDMULH_ZZZI_H:
30037 case AArch64::SQDMULH_ZZZI_S:
30038 case AArch64::SQRDMULH_ZZZI_H:
30039 case AArch64::SQRDMULH_ZZZI_S: {
30040 switch (OpNum) {
30041 case 0:
30042 // op: Zd
30043 return 0;
30044 case 1:
30045 // op: Zn
30046 return 5;
30047 case 2:
30048 // op: Zm
30049 return 16;
30050 case 3:
30051 // op: iop
30052 return 19;
30053 }
30054 break;
30055 }
30056 case AArch64::FMUL_ZZZI_D:
30057 case AArch64::MUL_ZZZI_D:
30058 case AArch64::SQDMULH_ZZZI_D:
30059 case AArch64::SQRDMULH_ZZZI_D: {
30060 switch (OpNum) {
30061 case 0:
30062 // op: Zd
30063 return 0;
30064 case 1:
30065 // op: Zn
30066 return 5;
30067 case 2:
30068 // op: Zm
30069 return 16;
30070 case 3:
30071 // op: iop
30072 return 20;
30073 }
30074 break;
30075 }
30076 case AArch64::ADDHNB_ZZZ_B:
30077 case AArch64::ADDHNB_ZZZ_H:
30078 case AArch64::ADDHNB_ZZZ_S:
30079 case AArch64::ADR_LSL_ZZZ_D_0:
30080 case AArch64::ADR_LSL_ZZZ_D_1:
30081 case AArch64::ADR_LSL_ZZZ_D_2:
30082 case AArch64::ADR_LSL_ZZZ_D_3:
30083 case AArch64::ADR_LSL_ZZZ_S_0:
30084 case AArch64::ADR_LSL_ZZZ_S_1:
30085 case AArch64::ADR_LSL_ZZZ_S_2:
30086 case AArch64::ADR_LSL_ZZZ_S_3:
30087 case AArch64::ADR_SXTW_ZZZ_D_0:
30088 case AArch64::ADR_SXTW_ZZZ_D_1:
30089 case AArch64::ADR_SXTW_ZZZ_D_2:
30090 case AArch64::ADR_SXTW_ZZZ_D_3:
30091 case AArch64::ADR_UXTW_ZZZ_D_0:
30092 case AArch64::ADR_UXTW_ZZZ_D_1:
30093 case AArch64::ADR_UXTW_ZZZ_D_2:
30094 case AArch64::ADR_UXTW_ZZZ_D_3:
30095 case AArch64::BDEP_ZZZ_B:
30096 case AArch64::BDEP_ZZZ_D:
30097 case AArch64::BDEP_ZZZ_H:
30098 case AArch64::BDEP_ZZZ_S:
30099 case AArch64::BEXT_ZZZ_B:
30100 case AArch64::BEXT_ZZZ_D:
30101 case AArch64::BEXT_ZZZ_H:
30102 case AArch64::BEXT_ZZZ_S:
30103 case AArch64::BGRP_ZZZ_B:
30104 case AArch64::BGRP_ZZZ_D:
30105 case AArch64::BGRP_ZZZ_H:
30106 case AArch64::BGRP_ZZZ_S:
30107 case AArch64::HISTSEG_ZZZ:
30108 case AArch64::PMULLB_ZZZ_D:
30109 case AArch64::PMULLB_ZZZ_H:
30110 case AArch64::PMULLB_ZZZ_Q:
30111 case AArch64::PMULLT_ZZZ_D:
30112 case AArch64::PMULLT_ZZZ_H:
30113 case AArch64::PMULLT_ZZZ_Q:
30114 case AArch64::RADDHNB_ZZZ_B:
30115 case AArch64::RADDHNB_ZZZ_H:
30116 case AArch64::RADDHNB_ZZZ_S:
30117 case AArch64::RAX1_ZZZ_D:
30118 case AArch64::RSUBHNB_ZZZ_B:
30119 case AArch64::RSUBHNB_ZZZ_H:
30120 case AArch64::RSUBHNB_ZZZ_S:
30121 case AArch64::SABDLB_ZZZ_D:
30122 case AArch64::SABDLB_ZZZ_H:
30123 case AArch64::SABDLB_ZZZ_S:
30124 case AArch64::SABDLT_ZZZ_D:
30125 case AArch64::SABDLT_ZZZ_H:
30126 case AArch64::SABDLT_ZZZ_S:
30127 case AArch64::SADDLBT_ZZZ_D:
30128 case AArch64::SADDLBT_ZZZ_H:
30129 case AArch64::SADDLBT_ZZZ_S:
30130 case AArch64::SADDLB_ZZZ_D:
30131 case AArch64::SADDLB_ZZZ_H:
30132 case AArch64::SADDLB_ZZZ_S:
30133 case AArch64::SADDLT_ZZZ_D:
30134 case AArch64::SADDLT_ZZZ_H:
30135 case AArch64::SADDLT_ZZZ_S:
30136 case AArch64::SADDWB_ZZZ_D:
30137 case AArch64::SADDWB_ZZZ_H:
30138 case AArch64::SADDWB_ZZZ_S:
30139 case AArch64::SADDWT_ZZZ_D:
30140 case AArch64::SADDWT_ZZZ_H:
30141 case AArch64::SADDWT_ZZZ_S:
30142 case AArch64::SM4EKEY_ZZZ_S:
30143 case AArch64::SMULLB_ZZZ_D:
30144 case AArch64::SMULLB_ZZZ_H:
30145 case AArch64::SMULLB_ZZZ_S:
30146 case AArch64::SMULLT_ZZZ_D:
30147 case AArch64::SMULLT_ZZZ_H:
30148 case AArch64::SMULLT_ZZZ_S:
30149 case AArch64::SQDMULLB_ZZZ_D:
30150 case AArch64::SQDMULLB_ZZZ_H:
30151 case AArch64::SQDMULLB_ZZZ_S:
30152 case AArch64::SQDMULLT_ZZZ_D:
30153 case AArch64::SQDMULLT_ZZZ_H:
30154 case AArch64::SQDMULLT_ZZZ_S:
30155 case AArch64::SSUBLBT_ZZZ_D:
30156 case AArch64::SSUBLBT_ZZZ_H:
30157 case AArch64::SSUBLBT_ZZZ_S:
30158 case AArch64::SSUBLB_ZZZ_D:
30159 case AArch64::SSUBLB_ZZZ_H:
30160 case AArch64::SSUBLB_ZZZ_S:
30161 case AArch64::SSUBLTB_ZZZ_D:
30162 case AArch64::SSUBLTB_ZZZ_H:
30163 case AArch64::SSUBLTB_ZZZ_S:
30164 case AArch64::SSUBLT_ZZZ_D:
30165 case AArch64::SSUBLT_ZZZ_H:
30166 case AArch64::SSUBLT_ZZZ_S:
30167 case AArch64::SSUBWB_ZZZ_D:
30168 case AArch64::SSUBWB_ZZZ_H:
30169 case AArch64::SSUBWB_ZZZ_S:
30170 case AArch64::SSUBWT_ZZZ_D:
30171 case AArch64::SSUBWT_ZZZ_H:
30172 case AArch64::SSUBWT_ZZZ_S:
30173 case AArch64::SUBHNB_ZZZ_B:
30174 case AArch64::SUBHNB_ZZZ_H:
30175 case AArch64::SUBHNB_ZZZ_S:
30176 case AArch64::TBLQ_ZZZ_B:
30177 case AArch64::TBLQ_ZZZ_D:
30178 case AArch64::TBLQ_ZZZ_H:
30179 case AArch64::TBLQ_ZZZ_S:
30180 case AArch64::UABDLB_ZZZ_D:
30181 case AArch64::UABDLB_ZZZ_H:
30182 case AArch64::UABDLB_ZZZ_S:
30183 case AArch64::UABDLT_ZZZ_D:
30184 case AArch64::UABDLT_ZZZ_H:
30185 case AArch64::UABDLT_ZZZ_S:
30186 case AArch64::UADDLB_ZZZ_D:
30187 case AArch64::UADDLB_ZZZ_H:
30188 case AArch64::UADDLB_ZZZ_S:
30189 case AArch64::UADDLT_ZZZ_D:
30190 case AArch64::UADDLT_ZZZ_H:
30191 case AArch64::UADDLT_ZZZ_S:
30192 case AArch64::UADDWB_ZZZ_D:
30193 case AArch64::UADDWB_ZZZ_H:
30194 case AArch64::UADDWB_ZZZ_S:
30195 case AArch64::UADDWT_ZZZ_D:
30196 case AArch64::UADDWT_ZZZ_H:
30197 case AArch64::UADDWT_ZZZ_S:
30198 case AArch64::UMULLB_ZZZ_D:
30199 case AArch64::UMULLB_ZZZ_H:
30200 case AArch64::UMULLB_ZZZ_S:
30201 case AArch64::UMULLT_ZZZ_D:
30202 case AArch64::UMULLT_ZZZ_H:
30203 case AArch64::UMULLT_ZZZ_S:
30204 case AArch64::USUBLB_ZZZ_D:
30205 case AArch64::USUBLB_ZZZ_H:
30206 case AArch64::USUBLB_ZZZ_S:
30207 case AArch64::USUBLT_ZZZ_D:
30208 case AArch64::USUBLT_ZZZ_H:
30209 case AArch64::USUBLT_ZZZ_S:
30210 case AArch64::USUBWB_ZZZ_D:
30211 case AArch64::USUBWB_ZZZ_H:
30212 case AArch64::USUBWB_ZZZ_S:
30213 case AArch64::USUBWT_ZZZ_D:
30214 case AArch64::USUBWT_ZZZ_H:
30215 case AArch64::USUBWT_ZZZ_S:
30216 case AArch64::UZPQ1_ZZZ_B:
30217 case AArch64::UZPQ1_ZZZ_D:
30218 case AArch64::UZPQ1_ZZZ_H:
30219 case AArch64::UZPQ1_ZZZ_S:
30220 case AArch64::UZPQ2_ZZZ_B:
30221 case AArch64::UZPQ2_ZZZ_D:
30222 case AArch64::UZPQ2_ZZZ_H:
30223 case AArch64::UZPQ2_ZZZ_S:
30224 case AArch64::ZIPQ1_ZZZ_B:
30225 case AArch64::ZIPQ1_ZZZ_D:
30226 case AArch64::ZIPQ1_ZZZ_H:
30227 case AArch64::ZIPQ1_ZZZ_S:
30228 case AArch64::ZIPQ2_ZZZ_B:
30229 case AArch64::ZIPQ2_ZZZ_D:
30230 case AArch64::ZIPQ2_ZZZ_H:
30231 case AArch64::ZIPQ2_ZZZ_S: {
30232 switch (OpNum) {
30233 case 0:
30234 // op: Zd
30235 return 0;
30236 case 1:
30237 // op: Zn
30238 return 5;
30239 case 2:
30240 // op: Zm
30241 return 16;
30242 }
30243 break;
30244 }
30245 case AArch64::DUP_ZZI_B: {
30246 switch (OpNum) {
30247 case 0:
30248 // op: Zd
30249 return 0;
30250 case 1:
30251 // op: Zn
30252 return 5;
30253 case 2:
30254 // op: idx
30255 return 17;
30256 }
30257 break;
30258 }
30259 case AArch64::DUP_ZZI_H: {
30260 switch (OpNum) {
30261 case 0:
30262 // op: Zd
30263 return 0;
30264 case 1:
30265 // op: Zn
30266 return 5;
30267 case 2:
30268 // op: idx
30269 return 18;
30270 }
30271 break;
30272 }
30273 case AArch64::DUP_ZZI_S: {
30274 switch (OpNum) {
30275 case 0:
30276 // op: Zd
30277 return 0;
30278 case 1:
30279 // op: Zn
30280 return 5;
30281 case 2:
30282 // op: idx
30283 return 19;
30284 }
30285 break;
30286 }
30287 case AArch64::DUP_ZZI_D: {
30288 switch (OpNum) {
30289 case 0:
30290 // op: Zd
30291 return 0;
30292 case 1:
30293 // op: Zn
30294 return 5;
30295 case 2:
30296 // op: idx
30297 return 20;
30298 }
30299 break;
30300 }
30301 case AArch64::DUP_ZZI_Q: {
30302 switch (OpNum) {
30303 case 0:
30304 // op: Zd
30305 return 0;
30306 case 1:
30307 // op: Zn
30308 return 5;
30309 case 2:
30310 // op: idx
30311 return 22;
30312 }
30313 break;
30314 }
30315 case AArch64::ASR_ZZI_B:
30316 case AArch64::ASR_ZZI_D:
30317 case AArch64::ASR_ZZI_H:
30318 case AArch64::ASR_ZZI_S:
30319 case AArch64::LSL_ZZI_B:
30320 case AArch64::LSL_ZZI_D:
30321 case AArch64::LSL_ZZI_H:
30322 case AArch64::LSL_ZZI_S:
30323 case AArch64::LSR_ZZI_B:
30324 case AArch64::LSR_ZZI_D:
30325 case AArch64::LSR_ZZI_H:
30326 case AArch64::LSR_ZZI_S:
30327 case AArch64::RSHRNB_ZZI_B:
30328 case AArch64::RSHRNB_ZZI_H:
30329 case AArch64::RSHRNB_ZZI_S:
30330 case AArch64::SHRNB_ZZI_B:
30331 case AArch64::SHRNB_ZZI_H:
30332 case AArch64::SHRNB_ZZI_S:
30333 case AArch64::SQRSHRNB_ZZI_B:
30334 case AArch64::SQRSHRNB_ZZI_H:
30335 case AArch64::SQRSHRNB_ZZI_S:
30336 case AArch64::SQRSHRUNB_ZZI_B:
30337 case AArch64::SQRSHRUNB_ZZI_H:
30338 case AArch64::SQRSHRUNB_ZZI_S:
30339 case AArch64::SQSHRNB_ZZI_B:
30340 case AArch64::SQSHRNB_ZZI_H:
30341 case AArch64::SQSHRNB_ZZI_S:
30342 case AArch64::SQSHRUNB_ZZI_B:
30343 case AArch64::SQSHRUNB_ZZI_H:
30344 case AArch64::SQSHRUNB_ZZI_S:
30345 case AArch64::SSHLLB_ZZI_D:
30346 case AArch64::SSHLLB_ZZI_H:
30347 case AArch64::SSHLLB_ZZI_S:
30348 case AArch64::SSHLLT_ZZI_D:
30349 case AArch64::SSHLLT_ZZI_H:
30350 case AArch64::SSHLLT_ZZI_S:
30351 case AArch64::UQRSHRNB_ZZI_B:
30352 case AArch64::UQRSHRNB_ZZI_H:
30353 case AArch64::UQRSHRNB_ZZI_S:
30354 case AArch64::UQSHRNB_ZZI_B:
30355 case AArch64::UQSHRNB_ZZI_H:
30356 case AArch64::UQSHRNB_ZZI_S:
30357 case AArch64::USHLLB_ZZI_D:
30358 case AArch64::USHLLB_ZZI_H:
30359 case AArch64::USHLLB_ZZI_S:
30360 case AArch64::USHLLT_ZZI_D:
30361 case AArch64::USHLLT_ZZI_H:
30362 case AArch64::USHLLT_ZZI_S: {
30363 switch (OpNum) {
30364 case 0:
30365 // op: Zd
30366 return 0;
30367 case 1:
30368 // op: Zn
30369 return 5;
30370 case 2:
30371 // op: imm
30372 return 16;
30373 }
30374 break;
30375 }
30376 case AArch64::EXT_ZZI_B: {
30377 switch (OpNum) {
30378 case 0:
30379 // op: Zd
30380 return 0;
30381 case 1:
30382 // op: Zn
30383 return 5;
30384 case 2:
30385 // op: imm8
30386 return 10;
30387 }
30388 break;
30389 }
30390 case AArch64::DUPQ_ZZI_B: {
30391 switch (OpNum) {
30392 case 0:
30393 // op: Zd
30394 return 0;
30395 case 1:
30396 // op: Zn
30397 return 5;
30398 case 2:
30399 // op: index
30400 return 17;
30401 }
30402 break;
30403 }
30404 case AArch64::DUPQ_ZZI_H: {
30405 switch (OpNum) {
30406 case 0:
30407 // op: Zd
30408 return 0;
30409 case 1:
30410 // op: Zn
30411 return 5;
30412 case 2:
30413 // op: index
30414 return 18;
30415 }
30416 break;
30417 }
30418 case AArch64::DUPQ_ZZI_S: {
30419 switch (OpNum) {
30420 case 0:
30421 // op: Zd
30422 return 0;
30423 case 1:
30424 // op: Zn
30425 return 5;
30426 case 2:
30427 // op: index
30428 return 19;
30429 }
30430 break;
30431 }
30432 case AArch64::DUPQ_ZZI_D: {
30433 switch (OpNum) {
30434 case 0:
30435 // op: Zd
30436 return 0;
30437 case 1:
30438 // op: Zn
30439 return 5;
30440 case 2:
30441 // op: index
30442 return 20;
30443 }
30444 break;
30445 }
30446 case AArch64::BF1CVTLT_ZZ_BtoH:
30447 case AArch64::BF1CVT_ZZ_BtoH:
30448 case AArch64::BF2CVTLT_ZZ_BtoH:
30449 case AArch64::BF2CVT_ZZ_BtoH:
30450 case AArch64::F1CVTLT_ZZ_BtoH:
30451 case AArch64::F1CVT_ZZ_BtoH:
30452 case AArch64::F2CVTLT_ZZ_BtoH:
30453 case AArch64::F2CVT_ZZ_BtoH:
30454 case AArch64::FEXPA_ZZ_D:
30455 case AArch64::FEXPA_ZZ_H:
30456 case AArch64::FEXPA_ZZ_S:
30457 case AArch64::FRECPE_ZZ_D:
30458 case AArch64::FRECPE_ZZ_H:
30459 case AArch64::FRECPE_ZZ_S:
30460 case AArch64::FRSQRTE_ZZ_D:
30461 case AArch64::FRSQRTE_ZZ_H:
30462 case AArch64::FRSQRTE_ZZ_S:
30463 case AArch64::MOVPRFX_ZZ:
30464 case AArch64::REV_ZZ_B:
30465 case AArch64::REV_ZZ_D:
30466 case AArch64::REV_ZZ_H:
30467 case AArch64::REV_ZZ_S:
30468 case AArch64::SQXTNB_ZZ_B:
30469 case AArch64::SQXTNB_ZZ_H:
30470 case AArch64::SQXTNB_ZZ_S:
30471 case AArch64::SQXTUNB_ZZ_B:
30472 case AArch64::SQXTUNB_ZZ_H:
30473 case AArch64::SQXTUNB_ZZ_S:
30474 case AArch64::SUNPKHI_ZZ_D:
30475 case AArch64::SUNPKHI_ZZ_H:
30476 case AArch64::SUNPKHI_ZZ_S:
30477 case AArch64::SUNPKLO_ZZ_D:
30478 case AArch64::SUNPKLO_ZZ_H:
30479 case AArch64::SUNPKLO_ZZ_S:
30480 case AArch64::UQXTNB_ZZ_B:
30481 case AArch64::UQXTNB_ZZ_H:
30482 case AArch64::UQXTNB_ZZ_S:
30483 case AArch64::UUNPKHI_ZZ_D:
30484 case AArch64::UUNPKHI_ZZ_H:
30485 case AArch64::UUNPKHI_ZZ_S:
30486 case AArch64::UUNPKLO_ZZ_D:
30487 case AArch64::UUNPKLO_ZZ_H:
30488 case AArch64::UUNPKLO_ZZ_S: {
30489 switch (OpNum) {
30490 case 0:
30491 // op: Zd
30492 return 0;
30493 case 1:
30494 // op: Zn
30495 return 5;
30496 }
30497 break;
30498 }
30499 case AArch64::SQRSHRN_Z2ZI_StoH:
30500 case AArch64::SQRSHRUN_Z2ZI_StoH:
30501 case AArch64::UQRSHRN_Z2ZI_StoH: {
30502 switch (OpNum) {
30503 case 0:
30504 // op: Zd
30505 return 0;
30506 case 1:
30507 // op: Zn
30508 return 6;
30509 case 2:
30510 // op: imm4
30511 return 16;
30512 }
30513 break;
30514 }
30515 case AArch64::BFCVTN_Z2Z_HtoB:
30516 case AArch64::FCVTNB_Z2Z_StoB:
30517 case AArch64::FCVTN_Z2Z_HtoB:
30518 case AArch64::SQCVTN_Z2Z_StoH:
30519 case AArch64::SQCVTUN_Z2Z_StoH:
30520 case AArch64::UQCVTN_Z2Z_StoH: {
30521 switch (OpNum) {
30522 case 0:
30523 // op: Zd
30524 return 0;
30525 case 1:
30526 // op: Zn
30527 return 6;
30528 }
30529 break;
30530 }
30531 case AArch64::DUP_ZI_B:
30532 case AArch64::DUP_ZI_D:
30533 case AArch64::DUP_ZI_H:
30534 case AArch64::DUP_ZI_S: {
30535 switch (OpNum) {
30536 case 0:
30537 // op: Zd
30538 return 0;
30539 case 1:
30540 // op: imm
30541 return 5;
30542 }
30543 break;
30544 }
30545 case AArch64::INDEX_II_B:
30546 case AArch64::INDEX_II_D:
30547 case AArch64::INDEX_II_H:
30548 case AArch64::INDEX_II_S: {
30549 switch (OpNum) {
30550 case 0:
30551 // op: Zd
30552 return 0;
30553 case 1:
30554 // op: imm5
30555 return 5;
30556 case 2:
30557 // op: imm5b
30558 return 16;
30559 }
30560 break;
30561 }
30562 case AArch64::FDUP_ZI_D:
30563 case AArch64::FDUP_ZI_H:
30564 case AArch64::FDUP_ZI_S: {
30565 switch (OpNum) {
30566 case 0:
30567 // op: Zd
30568 return 0;
30569 case 1:
30570 // op: imm8
30571 return 5;
30572 }
30573 break;
30574 }
30575 case AArch64::DUPM_ZI: {
30576 switch (OpNum) {
30577 case 0:
30578 // op: Zd
30579 return 0;
30580 case 1:
30581 // op: imms
30582 return 5;
30583 }
30584 break;
30585 }
30586 case AArch64::RBIT_ZPmZ_B:
30587 case AArch64::RBIT_ZPmZ_D:
30588 case AArch64::RBIT_ZPmZ_H:
30589 case AArch64::RBIT_ZPmZ_S:
30590 case AArch64::REVB_ZPmZ_D:
30591 case AArch64::REVB_ZPmZ_H:
30592 case AArch64::REVB_ZPmZ_S:
30593 case AArch64::REVD_ZPmZ:
30594 case AArch64::REVH_ZPmZ_D:
30595 case AArch64::REVH_ZPmZ_S:
30596 case AArch64::REVW_ZPmZ_D: {
30597 switch (OpNum) {
30598 case 0:
30599 // op: Zd
30600 return 0;
30601 case 2:
30602 // op: Pg
30603 return 10;
30604 case 3:
30605 // op: Zn
30606 return 5;
30607 }
30608 break;
30609 }
30610 case AArch64::CPY_ZPmI_B:
30611 case AArch64::CPY_ZPmI_D:
30612 case AArch64::CPY_ZPmI_H:
30613 case AArch64::CPY_ZPmI_S: {
30614 switch (OpNum) {
30615 case 0:
30616 // op: Zd
30617 return 0;
30618 case 2:
30619 // op: Pg
30620 return 16;
30621 case 3:
30622 // op: imm
30623 return 5;
30624 }
30625 break;
30626 }
30627 case AArch64::INDEX_RR_B:
30628 case AArch64::INDEX_RR_D:
30629 case AArch64::INDEX_RR_H:
30630 case AArch64::INDEX_RR_S: {
30631 switch (OpNum) {
30632 case 0:
30633 // op: Zd
30634 return 0;
30635 case 2:
30636 // op: Rm
30637 return 16;
30638 case 1:
30639 // op: Rn
30640 return 5;
30641 }
30642 break;
30643 }
30644 case AArch64::ADD_ZZZ_B:
30645 case AArch64::ADD_ZZZ_CPA:
30646 case AArch64::ADD_ZZZ_D:
30647 case AArch64::ADD_ZZZ_H:
30648 case AArch64::ADD_ZZZ_S:
30649 case AArch64::AND_ZZZ:
30650 case AArch64::ASR_WIDE_ZZZ_B:
30651 case AArch64::ASR_WIDE_ZZZ_H:
30652 case AArch64::ASR_WIDE_ZZZ_S:
30653 case AArch64::BFADD_ZZZ:
30654 case AArch64::BFMUL_ZZZ:
30655 case AArch64::BFSUB_ZZZ:
30656 case AArch64::BIC_ZZZ:
30657 case AArch64::EOR_ZZZ:
30658 case AArch64::FADD_ZZZ_D:
30659 case AArch64::FADD_ZZZ_H:
30660 case AArch64::FADD_ZZZ_S:
30661 case AArch64::FMUL_ZZZ_D:
30662 case AArch64::FMUL_ZZZ_H:
30663 case AArch64::FMUL_ZZZ_S:
30664 case AArch64::FRECPS_ZZZ_D:
30665 case AArch64::FRECPS_ZZZ_H:
30666 case AArch64::FRECPS_ZZZ_S:
30667 case AArch64::FRSQRTS_ZZZ_D:
30668 case AArch64::FRSQRTS_ZZZ_H:
30669 case AArch64::FRSQRTS_ZZZ_S:
30670 case AArch64::FSUB_ZZZ_D:
30671 case AArch64::FSUB_ZZZ_H:
30672 case AArch64::FSUB_ZZZ_S:
30673 case AArch64::FTSMUL_ZZZ_D:
30674 case AArch64::FTSMUL_ZZZ_H:
30675 case AArch64::FTSMUL_ZZZ_S:
30676 case AArch64::FTSSEL_ZZZ_D:
30677 case AArch64::FTSSEL_ZZZ_H:
30678 case AArch64::FTSSEL_ZZZ_S:
30679 case AArch64::LSL_WIDE_ZZZ_B:
30680 case AArch64::LSL_WIDE_ZZZ_H:
30681 case AArch64::LSL_WIDE_ZZZ_S:
30682 case AArch64::LSR_WIDE_ZZZ_B:
30683 case AArch64::LSR_WIDE_ZZZ_H:
30684 case AArch64::LSR_WIDE_ZZZ_S:
30685 case AArch64::MUL_ZZZ_B:
30686 case AArch64::MUL_ZZZ_D:
30687 case AArch64::MUL_ZZZ_H:
30688 case AArch64::MUL_ZZZ_S:
30689 case AArch64::ORR_ZZZ:
30690 case AArch64::PMUL_ZZZ_B:
30691 case AArch64::SMULH_ZZZ_B:
30692 case AArch64::SMULH_ZZZ_D:
30693 case AArch64::SMULH_ZZZ_H:
30694 case AArch64::SMULH_ZZZ_S:
30695 case AArch64::SQADD_ZZZ_B:
30696 case AArch64::SQADD_ZZZ_D:
30697 case AArch64::SQADD_ZZZ_H:
30698 case AArch64::SQADD_ZZZ_S:
30699 case AArch64::SQDMULH_ZZZ_B:
30700 case AArch64::SQDMULH_ZZZ_D:
30701 case AArch64::SQDMULH_ZZZ_H:
30702 case AArch64::SQDMULH_ZZZ_S:
30703 case AArch64::SQRDMULH_ZZZ_B:
30704 case AArch64::SQRDMULH_ZZZ_D:
30705 case AArch64::SQRDMULH_ZZZ_H:
30706 case AArch64::SQRDMULH_ZZZ_S:
30707 case AArch64::SQSUB_ZZZ_B:
30708 case AArch64::SQSUB_ZZZ_D:
30709 case AArch64::SQSUB_ZZZ_H:
30710 case AArch64::SQSUB_ZZZ_S:
30711 case AArch64::SUB_ZZZ_B:
30712 case AArch64::SUB_ZZZ_CPA:
30713 case AArch64::SUB_ZZZ_D:
30714 case AArch64::SUB_ZZZ_H:
30715 case AArch64::SUB_ZZZ_S:
30716 case AArch64::TBL_ZZZZ_B:
30717 case AArch64::TBL_ZZZZ_D:
30718 case AArch64::TBL_ZZZZ_H:
30719 case AArch64::TBL_ZZZZ_S:
30720 case AArch64::TBL_ZZZ_B:
30721 case AArch64::TBL_ZZZ_D:
30722 case AArch64::TBL_ZZZ_H:
30723 case AArch64::TBL_ZZZ_S:
30724 case AArch64::TRN1_ZZZ_B:
30725 case AArch64::TRN1_ZZZ_D:
30726 case AArch64::TRN1_ZZZ_H:
30727 case AArch64::TRN1_ZZZ_Q:
30728 case AArch64::TRN1_ZZZ_S:
30729 case AArch64::TRN2_ZZZ_B:
30730 case AArch64::TRN2_ZZZ_D:
30731 case AArch64::TRN2_ZZZ_H:
30732 case AArch64::TRN2_ZZZ_Q:
30733 case AArch64::TRN2_ZZZ_S:
30734 case AArch64::UMULH_ZZZ_B:
30735 case AArch64::UMULH_ZZZ_D:
30736 case AArch64::UMULH_ZZZ_H:
30737 case AArch64::UMULH_ZZZ_S:
30738 case AArch64::UQADD_ZZZ_B:
30739 case AArch64::UQADD_ZZZ_D:
30740 case AArch64::UQADD_ZZZ_H:
30741 case AArch64::UQADD_ZZZ_S:
30742 case AArch64::UQSUB_ZZZ_B:
30743 case AArch64::UQSUB_ZZZ_D:
30744 case AArch64::UQSUB_ZZZ_H:
30745 case AArch64::UQSUB_ZZZ_S:
30746 case AArch64::UZP1_ZZZ_B:
30747 case AArch64::UZP1_ZZZ_D:
30748 case AArch64::UZP1_ZZZ_H:
30749 case AArch64::UZP1_ZZZ_Q:
30750 case AArch64::UZP1_ZZZ_S:
30751 case AArch64::UZP2_ZZZ_B:
30752 case AArch64::UZP2_ZZZ_D:
30753 case AArch64::UZP2_ZZZ_H:
30754 case AArch64::UZP2_ZZZ_Q:
30755 case AArch64::UZP2_ZZZ_S:
30756 case AArch64::ZIP1_ZZZ_B:
30757 case AArch64::ZIP1_ZZZ_D:
30758 case AArch64::ZIP1_ZZZ_H:
30759 case AArch64::ZIP1_ZZZ_Q:
30760 case AArch64::ZIP1_ZZZ_S:
30761 case AArch64::ZIP2_ZZZ_B:
30762 case AArch64::ZIP2_ZZZ_D:
30763 case AArch64::ZIP2_ZZZ_H:
30764 case AArch64::ZIP2_ZZZ_Q:
30765 case AArch64::ZIP2_ZZZ_S: {
30766 switch (OpNum) {
30767 case 0:
30768 // op: Zd
30769 return 0;
30770 case 2:
30771 // op: Zm
30772 return 16;
30773 case 1:
30774 // op: Zn
30775 return 5;
30776 }
30777 break;
30778 }
30779 case AArch64::HISTCNT_ZPzZZ_D:
30780 case AArch64::HISTCNT_ZPzZZ_S: {
30781 switch (OpNum) {
30782 case 0:
30783 // op: Zd
30784 return 0;
30785 case 2:
30786 // op: Zn
30787 return 5;
30788 case 1:
30789 // op: Pg
30790 return 10;
30791 case 3:
30792 // op: Zm
30793 return 16;
30794 }
30795 break;
30796 }
30797 case AArch64::FCVTLT_ZPzZ_HtoS:
30798 case AArch64::FCVTLT_ZPzZ_StoD: {
30799 switch (OpNum) {
30800 case 0:
30801 // op: Zd
30802 return 0;
30803 case 2:
30804 // op: Zn
30805 return 5;
30806 case 1:
30807 // op: Pg
30808 return 10;
30809 }
30810 break;
30811 }
30812 case AArch64::ADDHNT_ZZZ_B:
30813 case AArch64::ADDHNT_ZZZ_H:
30814 case AArch64::ADDHNT_ZZZ_S:
30815 case AArch64::EORBT_ZZZ_B:
30816 case AArch64::EORBT_ZZZ_D:
30817 case AArch64::EORBT_ZZZ_H:
30818 case AArch64::EORBT_ZZZ_S:
30819 case AArch64::EORTB_ZZZ_B:
30820 case AArch64::EORTB_ZZZ_D:
30821 case AArch64::EORTB_ZZZ_H:
30822 case AArch64::EORTB_ZZZ_S:
30823 case AArch64::RADDHNT_ZZZ_B:
30824 case AArch64::RADDHNT_ZZZ_H:
30825 case AArch64::RADDHNT_ZZZ_S:
30826 case AArch64::RSUBHNT_ZZZ_B:
30827 case AArch64::RSUBHNT_ZZZ_H:
30828 case AArch64::RSUBHNT_ZZZ_S:
30829 case AArch64::SUBHNT_ZZZ_B:
30830 case AArch64::SUBHNT_ZZZ_H:
30831 case AArch64::SUBHNT_ZZZ_S: {
30832 switch (OpNum) {
30833 case 0:
30834 // op: Zd
30835 return 0;
30836 case 2:
30837 // op: Zn
30838 return 5;
30839 case 3:
30840 // op: Zm
30841 return 16;
30842 }
30843 break;
30844 }
30845 case AArch64::RSHRNT_ZZI_B:
30846 case AArch64::RSHRNT_ZZI_H:
30847 case AArch64::RSHRNT_ZZI_S:
30848 case AArch64::SHRNT_ZZI_B:
30849 case AArch64::SHRNT_ZZI_H:
30850 case AArch64::SHRNT_ZZI_S:
30851 case AArch64::SLI_ZZI_B:
30852 case AArch64::SLI_ZZI_D:
30853 case AArch64::SLI_ZZI_H:
30854 case AArch64::SLI_ZZI_S:
30855 case AArch64::SQRSHRNT_ZZI_B:
30856 case AArch64::SQRSHRNT_ZZI_H:
30857 case AArch64::SQRSHRNT_ZZI_S:
30858 case AArch64::SQRSHRUNT_ZZI_B:
30859 case AArch64::SQRSHRUNT_ZZI_H:
30860 case AArch64::SQRSHRUNT_ZZI_S:
30861 case AArch64::SQSHRNT_ZZI_B:
30862 case AArch64::SQSHRNT_ZZI_H:
30863 case AArch64::SQSHRNT_ZZI_S:
30864 case AArch64::SQSHRUNT_ZZI_B:
30865 case AArch64::SQSHRUNT_ZZI_H:
30866 case AArch64::SQSHRUNT_ZZI_S:
30867 case AArch64::SRI_ZZI_B:
30868 case AArch64::SRI_ZZI_D:
30869 case AArch64::SRI_ZZI_H:
30870 case AArch64::SRI_ZZI_S:
30871 case AArch64::UQRSHRNT_ZZI_B:
30872 case AArch64::UQRSHRNT_ZZI_H:
30873 case AArch64::UQRSHRNT_ZZI_S:
30874 case AArch64::UQSHRNT_ZZI_B:
30875 case AArch64::UQSHRNT_ZZI_H:
30876 case AArch64::UQSHRNT_ZZI_S: {
30877 switch (OpNum) {
30878 case 0:
30879 // op: Zd
30880 return 0;
30881 case 2:
30882 // op: Zn
30883 return 5;
30884 case 3:
30885 // op: imm
30886 return 16;
30887 }
30888 break;
30889 }
30890 case AArch64::SQXTNT_ZZ_B:
30891 case AArch64::SQXTNT_ZZ_H:
30892 case AArch64::SQXTNT_ZZ_S:
30893 case AArch64::SQXTUNT_ZZ_B:
30894 case AArch64::SQXTUNT_ZZ_H:
30895 case AArch64::SQXTUNT_ZZ_S:
30896 case AArch64::UQXTNT_ZZ_B:
30897 case AArch64::UQXTNT_ZZ_H:
30898 case AArch64::UQXTNT_ZZ_S: {
30899 switch (OpNum) {
30900 case 0:
30901 // op: Zd
30902 return 0;
30903 case 2:
30904 // op: Zn
30905 return 5;
30906 }
30907 break;
30908 }
30909 case AArch64::FCVTNT_Z2Z_StoB: {
30910 switch (OpNum) {
30911 case 0:
30912 // op: Zd
30913 return 0;
30914 case 2:
30915 // op: Zn
30916 return 6;
30917 }
30918 break;
30919 }
30920 case AArch64::PMOV_ZIP_D:
30921 case AArch64::PMOV_ZIP_H:
30922 case AArch64::PMOV_ZIP_S: {
30923 switch (OpNum) {
30924 case 0:
30925 // op: Zd
30926 return 0;
30927 case 3:
30928 // op: Pn
30929 return 5;
30930 case 2:
30931 // op: index
30932 return 17;
30933 }
30934 break;
30935 }
30936 case AArch64::PMOV_ZIP_B: {
30937 switch (OpNum) {
30938 case 0:
30939 // op: Zd
30940 return 0;
30941 case 3:
30942 // op: Pn
30943 return 5;
30944 }
30945 break;
30946 }
30947 case AArch64::TBXQ_ZZZ_B:
30948 case AArch64::TBXQ_ZZZ_D:
30949 case AArch64::TBXQ_ZZZ_H:
30950 case AArch64::TBXQ_ZZZ_S:
30951 case AArch64::TBX_ZZZ_B:
30952 case AArch64::TBX_ZZZ_D:
30953 case AArch64::TBX_ZZZ_H:
30954 case AArch64::TBX_ZZZ_S: {
30955 switch (OpNum) {
30956 case 0:
30957 // op: Zd
30958 return 0;
30959 case 3:
30960 // op: Zm
30961 return 16;
30962 case 2:
30963 // op: Zn
30964 return 5;
30965 }
30966 break;
30967 }
30968 case AArch64::BFCVTNT_ZPmZ:
30969 case AArch64::BFCVTNT_ZPzZ:
30970 case AArch64::FCVTLT_ZPmZ_HtoS:
30971 case AArch64::FCVTLT_ZPmZ_StoD:
30972 case AArch64::FCVTNT_ZPmZ_DtoS:
30973 case AArch64::FCVTNT_ZPmZ_StoH:
30974 case AArch64::FCVTNT_ZPzZ_DtoS:
30975 case AArch64::FCVTNT_ZPzZ_StoH:
30976 case AArch64::FCVTXNT_ZPmZ_DtoS:
30977 case AArch64::FCVTXNT_ZPzZ: {
30978 switch (OpNum) {
30979 case 0:
30980 // op: Zd
30981 return 0;
30982 case 3:
30983 // op: Zn
30984 return 5;
30985 case 2:
30986 // op: Pg
30987 return 10;
30988 }
30989 break;
30990 }
30991 case AArch64::BFMUL_2Z2Z:
30992 case AArch64::BFMUL_2ZZ:
30993 case AArch64::FMUL_2Z2Z_D:
30994 case AArch64::FMUL_2Z2Z_H:
30995 case AArch64::FMUL_2Z2Z_S:
30996 case AArch64::FMUL_2ZZ_D:
30997 case AArch64::FMUL_2ZZ_H:
30998 case AArch64::FMUL_2ZZ_S: {
30999 switch (OpNum) {
31000 case 0:
31001 // op: Zd
31002 return 1;
31003 case 1:
31004 // op: Zn
31005 return 6;
31006 case 2:
31007 // op: Zm
31008 return 17;
31009 }
31010 break;
31011 }
31012 case AArch64::MOVA_2ZMXI_H_D:
31013 case AArch64::MOVA_2ZMXI_V_D: {
31014 switch (OpNum) {
31015 case 0:
31016 // op: Zd
31017 return 1;
31018 case 2:
31019 // op: Rs
31020 return 13;
31021 case 1:
31022 // op: ZAn
31023 return 5;
31024 }
31025 break;
31026 }
31027 case AArch64::MOVA_2ZMXI_H_S:
31028 case AArch64::MOVA_2ZMXI_V_S: {
31029 switch (OpNum) {
31030 case 0:
31031 // op: Zd
31032 return 1;
31033 case 2:
31034 // op: Rs
31035 return 13;
31036 case 1:
31037 // op: ZAn
31038 return 6;
31039 case 3:
31040 // op: imm
31041 return 5;
31042 }
31043 break;
31044 }
31045 case AArch64::MOVA_2ZMXI_H_H:
31046 case AArch64::MOVA_2ZMXI_V_H: {
31047 switch (OpNum) {
31048 case 0:
31049 // op: Zd
31050 return 1;
31051 case 2:
31052 // op: Rs
31053 return 13;
31054 case 1:
31055 // op: ZAn
31056 return 7;
31057 case 3:
31058 // op: imm
31059 return 5;
31060 }
31061 break;
31062 }
31063 case AArch64::MOVA_2ZMXI_H_B:
31064 case AArch64::MOVA_2ZMXI_V_B: {
31065 switch (OpNum) {
31066 case 0:
31067 // op: Zd
31068 return 1;
31069 case 2:
31070 // op: Rs
31071 return 13;
31072 case 3:
31073 // op: imm
31074 return 5;
31075 }
31076 break;
31077 }
31078 case AArch64::UZP_VG2_2ZZZ_B:
31079 case AArch64::UZP_VG2_2ZZZ_D:
31080 case AArch64::UZP_VG2_2ZZZ_H:
31081 case AArch64::UZP_VG2_2ZZZ_Q:
31082 case AArch64::UZP_VG2_2ZZZ_S:
31083 case AArch64::ZIP_VG2_2ZZZ_B:
31084 case AArch64::ZIP_VG2_2ZZZ_D:
31085 case AArch64::ZIP_VG2_2ZZZ_H:
31086 case AArch64::ZIP_VG2_2ZZZ_Q:
31087 case AArch64::ZIP_VG2_2ZZZ_S: {
31088 switch (OpNum) {
31089 case 0:
31090 // op: Zd
31091 return 1;
31092 case 2:
31093 // op: Zm
31094 return 16;
31095 case 1:
31096 // op: Zn
31097 return 5;
31098 }
31099 break;
31100 }
31101 case AArch64::MOVAZ_2ZMI_H_D:
31102 case AArch64::MOVAZ_2ZMI_V_D: {
31103 switch (OpNum) {
31104 case 0:
31105 // op: Zd
31106 return 1;
31107 case 3:
31108 // op: Rs
31109 return 13;
31110 case 2:
31111 // op: ZAn
31112 return 5;
31113 }
31114 break;
31115 }
31116 case AArch64::MOVAZ_2ZMI_H_S:
31117 case AArch64::MOVAZ_2ZMI_V_S: {
31118 switch (OpNum) {
31119 case 0:
31120 // op: Zd
31121 return 1;
31122 case 3:
31123 // op: Rs
31124 return 13;
31125 case 2:
31126 // op: ZAn
31127 return 6;
31128 case 4:
31129 // op: imm
31130 return 5;
31131 }
31132 break;
31133 }
31134 case AArch64::MOVAZ_2ZMI_H_H:
31135 case AArch64::MOVAZ_2ZMI_V_H: {
31136 switch (OpNum) {
31137 case 0:
31138 // op: Zd
31139 return 1;
31140 case 3:
31141 // op: Rs
31142 return 13;
31143 case 2:
31144 // op: ZAn
31145 return 7;
31146 case 4:
31147 // op: imm
31148 return 5;
31149 }
31150 break;
31151 }
31152 case AArch64::MOVAZ_2ZMI_H_B:
31153 case AArch64::MOVAZ_2ZMI_V_B: {
31154 switch (OpNum) {
31155 case 0:
31156 // op: Zd
31157 return 1;
31158 case 3:
31159 // op: Rs
31160 return 13;
31161 case 4:
31162 // op: imm
31163 return 5;
31164 }
31165 break;
31166 }
31167 case AArch64::BFMUL_4ZZ:
31168 case AArch64::FMUL_4ZZ_D:
31169 case AArch64::FMUL_4ZZ_H:
31170 case AArch64::FMUL_4ZZ_S: {
31171 switch (OpNum) {
31172 case 0:
31173 // op: Zd
31174 return 2;
31175 case 1:
31176 // op: Zn
31177 return 7;
31178 case 2:
31179 // op: Zm
31180 return 17;
31181 }
31182 break;
31183 }
31184 case AArch64::BFMUL_4Z4Z:
31185 case AArch64::FMUL_4Z4Z_D:
31186 case AArch64::FMUL_4Z4Z_H:
31187 case AArch64::FMUL_4Z4Z_S: {
31188 switch (OpNum) {
31189 case 0:
31190 // op: Zd
31191 return 2;
31192 case 1:
31193 // op: Zn
31194 return 7;
31195 case 2:
31196 // op: Zm
31197 return 18;
31198 }
31199 break;
31200 }
31201 case AArch64::MOVA_4ZMXI_H_D:
31202 case AArch64::MOVA_4ZMXI_H_S:
31203 case AArch64::MOVA_4ZMXI_V_D:
31204 case AArch64::MOVA_4ZMXI_V_S: {
31205 switch (OpNum) {
31206 case 0:
31207 // op: Zd
31208 return 2;
31209 case 2:
31210 // op: Rs
31211 return 13;
31212 case 1:
31213 // op: ZAn
31214 return 5;
31215 }
31216 break;
31217 }
31218 case AArch64::MOVA_4ZMXI_H_H:
31219 case AArch64::MOVA_4ZMXI_V_H: {
31220 switch (OpNum) {
31221 case 0:
31222 // op: Zd
31223 return 2;
31224 case 2:
31225 // op: Rs
31226 return 13;
31227 case 1:
31228 // op: ZAn
31229 return 6;
31230 case 3:
31231 // op: imm
31232 return 5;
31233 }
31234 break;
31235 }
31236 case AArch64::MOVA_4ZMXI_H_B:
31237 case AArch64::MOVA_4ZMXI_V_B: {
31238 switch (OpNum) {
31239 case 0:
31240 // op: Zd
31241 return 2;
31242 case 2:
31243 // op: Rs
31244 return 13;
31245 case 3:
31246 // op: imm
31247 return 5;
31248 }
31249 break;
31250 }
31251 case AArch64::MOVAZ_4ZMI_H_D:
31252 case AArch64::MOVAZ_4ZMI_H_S:
31253 case AArch64::MOVAZ_4ZMI_V_D:
31254 case AArch64::MOVAZ_4ZMI_V_S: {
31255 switch (OpNum) {
31256 case 0:
31257 // op: Zd
31258 return 2;
31259 case 3:
31260 // op: Rs
31261 return 13;
31262 case 2:
31263 // op: ZAn
31264 return 5;
31265 }
31266 break;
31267 }
31268 case AArch64::MOVAZ_4ZMI_H_H:
31269 case AArch64::MOVAZ_4ZMI_V_H: {
31270 switch (OpNum) {
31271 case 0:
31272 // op: Zd
31273 return 2;
31274 case 3:
31275 // op: Rs
31276 return 13;
31277 case 2:
31278 // op: ZAn
31279 return 6;
31280 case 4:
31281 // op: imm
31282 return 5;
31283 }
31284 break;
31285 }
31286 case AArch64::MOVAZ_4ZMI_H_B:
31287 case AArch64::MOVAZ_4ZMI_V_B: {
31288 switch (OpNum) {
31289 case 0:
31290 // op: Zd
31291 return 2;
31292 case 3:
31293 // op: Rs
31294 return 13;
31295 case 4:
31296 // op: imm
31297 return 5;
31298 }
31299 break;
31300 }
31301 case AArch64::FCMLA_ZPmZZ_D:
31302 case AArch64::FCMLA_ZPmZZ_H:
31303 case AArch64::FCMLA_ZPmZZ_S: {
31304 switch (OpNum) {
31305 case 0:
31306 // op: Zda
31307 return 0;
31308 case 1:
31309 // op: Pg
31310 return 10;
31311 case 3:
31312 // op: Zn
31313 return 5;
31314 case 4:
31315 // op: Zm
31316 return 16;
31317 case 5:
31318 // op: imm
31319 return 13;
31320 }
31321 break;
31322 }
31323 case AArch64::SDOT_ZZZI_HtoS:
31324 case AArch64::UDOT_ZZZI_HtoS: {
31325 switch (OpNum) {
31326 case 0:
31327 // op: Zda
31328 return 0;
31329 case 2:
31330 // op: Zn
31331 return 5;
31332 case 3:
31333 // op: Zm
31334 return 16;
31335 case 4:
31336 // op: i2
31337 return 19;
31338 }
31339 break;
31340 }
31341 case AArch64::SUDOT_ZZZI:
31342 case AArch64::USDOT_ZZZI: {
31343 switch (OpNum) {
31344 case 0:
31345 // op: Zda
31346 return 0;
31347 case 2:
31348 // op: Zn
31349 return 5;
31350 case 3:
31351 // op: Zm
31352 return 16;
31353 case 4:
31354 // op: idx
31355 return 19;
31356 }
31357 break;
31358 }
31359 case AArch64::FMLALB_ZZZI:
31360 case AArch64::FMLALLBB_ZZZI:
31361 case AArch64::FMLALLBT_ZZZI:
31362 case AArch64::FMLALLTB_ZZZI:
31363 case AArch64::FMLALLTT_ZZZI:
31364 case AArch64::FMLALT_ZZZI: {
31365 switch (OpNum) {
31366 case 0:
31367 // op: Zda
31368 return 0;
31369 case 2:
31370 // op: Zn
31371 return 5;
31372 case 3:
31373 // op: Zm
31374 return 16;
31375 case 4:
31376 // op: imm4
31377 return 10;
31378 }
31379 break;
31380 }
31381 case AArch64::BFMLALB_ZZZI:
31382 case AArch64::BFMLALT_ZZZI:
31383 case AArch64::BFMLSLB_ZZZI_S:
31384 case AArch64::BFMLSLT_ZZZI_S:
31385 case AArch64::FDOT_ZZZI_BtoH:
31386 case AArch64::FMLALB_ZZZI_SHH:
31387 case AArch64::FMLALT_ZZZI_SHH:
31388 case AArch64::FMLSLB_ZZZI_SHH:
31389 case AArch64::FMLSLT_ZZZI_SHH:
31390 case AArch64::SMLALB_ZZZI_D:
31391 case AArch64::SMLALB_ZZZI_S:
31392 case AArch64::SMLALT_ZZZI_D:
31393 case AArch64::SMLALT_ZZZI_S:
31394 case AArch64::SMLSLB_ZZZI_D:
31395 case AArch64::SMLSLB_ZZZI_S:
31396 case AArch64::SMLSLT_ZZZI_D:
31397 case AArch64::SMLSLT_ZZZI_S:
31398 case AArch64::SQDMLALB_ZZZI_D:
31399 case AArch64::SQDMLALB_ZZZI_S:
31400 case AArch64::SQDMLALT_ZZZI_D:
31401 case AArch64::SQDMLALT_ZZZI_S:
31402 case AArch64::SQDMLSLB_ZZZI_D:
31403 case AArch64::SQDMLSLB_ZZZI_S:
31404 case AArch64::SQDMLSLT_ZZZI_D:
31405 case AArch64::SQDMLSLT_ZZZI_S:
31406 case AArch64::UMLALB_ZZZI_D:
31407 case AArch64::UMLALB_ZZZI_S:
31408 case AArch64::UMLALT_ZZZI_D:
31409 case AArch64::UMLALT_ZZZI_S:
31410 case AArch64::UMLSLB_ZZZI_D:
31411 case AArch64::UMLSLB_ZZZI_S:
31412 case AArch64::UMLSLT_ZZZI_D:
31413 case AArch64::UMLSLT_ZZZI_S: {
31414 switch (OpNum) {
31415 case 0:
31416 // op: Zda
31417 return 0;
31418 case 2:
31419 // op: Zn
31420 return 5;
31421 case 3:
31422 // op: Zm
31423 return 16;
31424 case 4:
31425 // op: iop
31426 return 11;
31427 }
31428 break;
31429 }
31430 case AArch64::BFDOT_ZZI:
31431 case AArch64::BFMLA_ZZZI:
31432 case AArch64::BFMLS_ZZZI:
31433 case AArch64::FDOT_ZZZI_BtoS:
31434 case AArch64::FDOT_ZZZI_S:
31435 case AArch64::FMLA_ZZZI_H:
31436 case AArch64::FMLA_ZZZI_S:
31437 case AArch64::FMLS_ZZZI_H:
31438 case AArch64::FMLS_ZZZI_S:
31439 case AArch64::MLA_ZZZI_H:
31440 case AArch64::MLA_ZZZI_S:
31441 case AArch64::MLS_ZZZI_H:
31442 case AArch64::MLS_ZZZI_S:
31443 case AArch64::SQRDMLAH_ZZZI_H:
31444 case AArch64::SQRDMLAH_ZZZI_S:
31445 case AArch64::SQRDMLSH_ZZZI_H:
31446 case AArch64::SQRDMLSH_ZZZI_S: {
31447 switch (OpNum) {
31448 case 0:
31449 // op: Zda
31450 return 0;
31451 case 2:
31452 // op: Zn
31453 return 5;
31454 case 3:
31455 // op: Zm
31456 return 16;
31457 case 4:
31458 // op: iop
31459 return 19;
31460 }
31461 break;
31462 }
31463 case AArch64::FMLA_ZZZI_D:
31464 case AArch64::FMLS_ZZZI_D:
31465 case AArch64::MLA_ZZZI_D:
31466 case AArch64::MLS_ZZZI_D:
31467 case AArch64::SQRDMLAH_ZZZI_D:
31468 case AArch64::SQRDMLSH_ZZZI_D: {
31469 switch (OpNum) {
31470 case 0:
31471 // op: Zda
31472 return 0;
31473 case 2:
31474 // op: Zn
31475 return 5;
31476 case 3:
31477 // op: Zm
31478 return 16;
31479 case 4:
31480 // op: iop
31481 return 20;
31482 }
31483 break;
31484 }
31485 case AArch64::CDOT_ZZZ_D:
31486 case AArch64::CDOT_ZZZ_S:
31487 case AArch64::CMLA_ZZZ_B:
31488 case AArch64::CMLA_ZZZ_D:
31489 case AArch64::CMLA_ZZZ_H:
31490 case AArch64::CMLA_ZZZ_S:
31491 case AArch64::SQRDCMLAH_ZZZ_B:
31492 case AArch64::SQRDCMLAH_ZZZ_D:
31493 case AArch64::SQRDCMLAH_ZZZ_H:
31494 case AArch64::SQRDCMLAH_ZZZ_S: {
31495 switch (OpNum) {
31496 case 0:
31497 // op: Zda
31498 return 0;
31499 case 2:
31500 // op: Zn
31501 return 5;
31502 case 3:
31503 // op: Zm
31504 return 16;
31505 case 4:
31506 // op: rot
31507 return 10;
31508 }
31509 break;
31510 }
31511 case AArch64::ADCLB_ZZZ_D:
31512 case AArch64::ADCLB_ZZZ_S:
31513 case AArch64::ADCLT_ZZZ_D:
31514 case AArch64::ADCLT_ZZZ_S:
31515 case AArch64::BFDOT_ZZZ:
31516 case AArch64::BFMLALB_ZZZ:
31517 case AArch64::BFMLALT_ZZZ:
31518 case AArch64::BFMLSLB_ZZZ_S:
31519 case AArch64::BFMLSLT_ZZZ_S:
31520 case AArch64::BFMMLA_ZZZ:
31521 case AArch64::FDOT_ZZZ_BtoH:
31522 case AArch64::FDOT_ZZZ_BtoS:
31523 case AArch64::FDOT_ZZZ_S:
31524 case AArch64::FMLALB_ZZZ:
31525 case AArch64::FMLALB_ZZZ_SHH:
31526 case AArch64::FMLALLBB_ZZZ:
31527 case AArch64::FMLALLBT_ZZZ:
31528 case AArch64::FMLALLTB_ZZZ:
31529 case AArch64::FMLALLTT_ZZZ:
31530 case AArch64::FMLALT_ZZZ:
31531 case AArch64::FMLALT_ZZZ_SHH:
31532 case AArch64::FMLLA_ZZZ_HtoS:
31533 case AArch64::FMLSLB_ZZZ_SHH:
31534 case AArch64::FMLSLT_ZZZ_SHH:
31535 case AArch64::FMMLA_ZZZ_BtoH:
31536 case AArch64::FMMLA_ZZZ_BtoS:
31537 case AArch64::FMMLA_ZZZ_D:
31538 case AArch64::FMMLA_ZZZ_S:
31539 case AArch64::MLA_CPA:
31540 case AArch64::SABALB_ZZZ_D:
31541 case AArch64::SABALB_ZZZ_H:
31542 case AArch64::SABALB_ZZZ_S:
31543 case AArch64::SABALT_ZZZ_D:
31544 case AArch64::SABALT_ZZZ_H:
31545 case AArch64::SABALT_ZZZ_S:
31546 case AArch64::SABA_ZZZ_B:
31547 case AArch64::SABA_ZZZ_D:
31548 case AArch64::SABA_ZZZ_H:
31549 case AArch64::SABA_ZZZ_S:
31550 case AArch64::SBCLB_ZZZ_D:
31551 case AArch64::SBCLB_ZZZ_S:
31552 case AArch64::SBCLT_ZZZ_D:
31553 case AArch64::SBCLT_ZZZ_S:
31554 case AArch64::SDOT_ZZZ_D:
31555 case AArch64::SDOT_ZZZ_HtoS:
31556 case AArch64::SDOT_ZZZ_S:
31557 case AArch64::SMLALB_ZZZ_D:
31558 case AArch64::SMLALB_ZZZ_H:
31559 case AArch64::SMLALB_ZZZ_S:
31560 case AArch64::SMLALT_ZZZ_D:
31561 case AArch64::SMLALT_ZZZ_H:
31562 case AArch64::SMLALT_ZZZ_S:
31563 case AArch64::SMLSLB_ZZZ_D:
31564 case AArch64::SMLSLB_ZZZ_H:
31565 case AArch64::SMLSLB_ZZZ_S:
31566 case AArch64::SMLSLT_ZZZ_D:
31567 case AArch64::SMLSLT_ZZZ_H:
31568 case AArch64::SMLSLT_ZZZ_S:
31569 case AArch64::SMMLA_ZZZ:
31570 case AArch64::SQDMLALBT_ZZZ_D:
31571 case AArch64::SQDMLALBT_ZZZ_H:
31572 case AArch64::SQDMLALBT_ZZZ_S:
31573 case AArch64::SQDMLALB_ZZZ_D:
31574 case AArch64::SQDMLALB_ZZZ_H:
31575 case AArch64::SQDMLALB_ZZZ_S:
31576 case AArch64::SQDMLALT_ZZZ_D:
31577 case AArch64::SQDMLALT_ZZZ_H:
31578 case AArch64::SQDMLALT_ZZZ_S:
31579 case AArch64::SQDMLSLBT_ZZZ_D:
31580 case AArch64::SQDMLSLBT_ZZZ_H:
31581 case AArch64::SQDMLSLBT_ZZZ_S:
31582 case AArch64::SQDMLSLB_ZZZ_D:
31583 case AArch64::SQDMLSLB_ZZZ_H:
31584 case AArch64::SQDMLSLB_ZZZ_S:
31585 case AArch64::SQDMLSLT_ZZZ_D:
31586 case AArch64::SQDMLSLT_ZZZ_H:
31587 case AArch64::SQDMLSLT_ZZZ_S:
31588 case AArch64::SQRDMLAH_ZZZ_B:
31589 case AArch64::SQRDMLAH_ZZZ_D:
31590 case AArch64::SQRDMLAH_ZZZ_H:
31591 case AArch64::SQRDMLAH_ZZZ_S:
31592 case AArch64::SQRDMLSH_ZZZ_B:
31593 case AArch64::SQRDMLSH_ZZZ_D:
31594 case AArch64::SQRDMLSH_ZZZ_H:
31595 case AArch64::SQRDMLSH_ZZZ_S:
31596 case AArch64::UABALB_ZZZ_D:
31597 case AArch64::UABALB_ZZZ_H:
31598 case AArch64::UABALB_ZZZ_S:
31599 case AArch64::UABALT_ZZZ_D:
31600 case AArch64::UABALT_ZZZ_H:
31601 case AArch64::UABALT_ZZZ_S:
31602 case AArch64::UABA_ZZZ_B:
31603 case AArch64::UABA_ZZZ_D:
31604 case AArch64::UABA_ZZZ_H:
31605 case AArch64::UABA_ZZZ_S:
31606 case AArch64::UDOT_ZZZ_D:
31607 case AArch64::UDOT_ZZZ_HtoS:
31608 case AArch64::UDOT_ZZZ_S:
31609 case AArch64::UMLALB_ZZZ_D:
31610 case AArch64::UMLALB_ZZZ_H:
31611 case AArch64::UMLALB_ZZZ_S:
31612 case AArch64::UMLALT_ZZZ_D:
31613 case AArch64::UMLALT_ZZZ_H:
31614 case AArch64::UMLALT_ZZZ_S:
31615 case AArch64::UMLSLB_ZZZ_D:
31616 case AArch64::UMLSLB_ZZZ_H:
31617 case AArch64::UMLSLB_ZZZ_S:
31618 case AArch64::UMLSLT_ZZZ_D:
31619 case AArch64::UMLSLT_ZZZ_H:
31620 case AArch64::UMLSLT_ZZZ_S:
31621 case AArch64::UMMLA_ZZZ:
31622 case AArch64::USDOT_ZZZ:
31623 case AArch64::USMMLA_ZZZ: {
31624 switch (OpNum) {
31625 case 0:
31626 // op: Zda
31627 return 0;
31628 case 2:
31629 // op: Zn
31630 return 5;
31631 case 3:
31632 // op: Zm
31633 return 16;
31634 }
31635 break;
31636 }
31637 case AArch64::SRSRA_ZZI_B:
31638 case AArch64::SRSRA_ZZI_D:
31639 case AArch64::SRSRA_ZZI_H:
31640 case AArch64::SRSRA_ZZI_S:
31641 case AArch64::SSRA_ZZI_B:
31642 case AArch64::SSRA_ZZI_D:
31643 case AArch64::SSRA_ZZI_H:
31644 case AArch64::SSRA_ZZI_S:
31645 case AArch64::URSRA_ZZI_B:
31646 case AArch64::URSRA_ZZI_D:
31647 case AArch64::URSRA_ZZI_H:
31648 case AArch64::URSRA_ZZI_S:
31649 case AArch64::USRA_ZZI_B:
31650 case AArch64::USRA_ZZI_D:
31651 case AArch64::USRA_ZZI_H:
31652 case AArch64::USRA_ZZI_S: {
31653 switch (OpNum) {
31654 case 0:
31655 // op: Zda
31656 return 0;
31657 case 2:
31658 // op: Zn
31659 return 5;
31660 case 3:
31661 // op: imm
31662 return 16;
31663 }
31664 break;
31665 }
31666 case AArch64::SDOT_ZZZI_S:
31667 case AArch64::UDOT_ZZZI_S: {
31668 switch (OpNum) {
31669 case 0:
31670 // op: Zda
31671 return 0;
31672 case 2:
31673 // op: Zn
31674 return 5;
31675 case 4:
31676 // op: iop
31677 return 19;
31678 case 3:
31679 // op: Zm
31680 return 16;
31681 }
31682 break;
31683 }
31684 case AArch64::SDOT_ZZZI_D:
31685 case AArch64::UDOT_ZZZI_D: {
31686 switch (OpNum) {
31687 case 0:
31688 // op: Zda
31689 return 0;
31690 case 2:
31691 // op: Zn
31692 return 5;
31693 case 4:
31694 // op: iop
31695 return 20;
31696 case 3:
31697 // op: Zm
31698 return 16;
31699 }
31700 break;
31701 }
31702 case AArch64::FCMLA_ZZZI_H: {
31703 switch (OpNum) {
31704 case 0:
31705 // op: Zda
31706 return 0;
31707 case 2:
31708 // op: Zn
31709 return 5;
31710 case 5:
31711 // op: imm
31712 return 10;
31713 case 3:
31714 // op: Zm
31715 return 16;
31716 case 4:
31717 // op: iop
31718 return 19;
31719 }
31720 break;
31721 }
31722 case AArch64::FCMLA_ZZZI_S: {
31723 switch (OpNum) {
31724 case 0:
31725 // op: Zda
31726 return 0;
31727 case 2:
31728 // op: Zn
31729 return 5;
31730 case 5:
31731 // op: imm
31732 return 10;
31733 case 3:
31734 // op: Zm
31735 return 16;
31736 case 4:
31737 // op: iop
31738 return 20;
31739 }
31740 break;
31741 }
31742 case AArch64::CDOT_ZZZI_S:
31743 case AArch64::CMLA_ZZZI_H:
31744 case AArch64::SQRDCMLAH_ZZZI_H: {
31745 switch (OpNum) {
31746 case 0:
31747 // op: Zda
31748 return 0;
31749 case 2:
31750 // op: Zn
31751 return 5;
31752 case 5:
31753 // op: rot
31754 return 10;
31755 case 4:
31756 // op: iop
31757 return 19;
31758 case 3:
31759 // op: Zm
31760 return 16;
31761 }
31762 break;
31763 }
31764 case AArch64::CDOT_ZZZI_D:
31765 case AArch64::CMLA_ZZZI_S:
31766 case AArch64::SQRDCMLAH_ZZZI_S: {
31767 switch (OpNum) {
31768 case 0:
31769 // op: Zda
31770 return 0;
31771 case 2:
31772 // op: Zn
31773 return 5;
31774 case 5:
31775 // op: rot
31776 return 10;
31777 case 4:
31778 // op: iop
31779 return 20;
31780 case 3:
31781 // op: Zm
31782 return 16;
31783 }
31784 break;
31785 }
31786 case AArch64::MAD_CPA: {
31787 switch (OpNum) {
31788 case 0:
31789 // op: Zdn
31790 return 0;
31791 case 2:
31792 // op: Zm
31793 return 16;
31794 case 3:
31795 // op: Za
31796 return 5;
31797 }
31798 break;
31799 }
31800 case AArch64::XAR_ZZZI_B:
31801 case AArch64::XAR_ZZZI_D:
31802 case AArch64::XAR_ZZZI_H:
31803 case AArch64::XAR_ZZZI_S: {
31804 switch (OpNum) {
31805 case 0:
31806 // op: Zdn
31807 return 0;
31808 case 2:
31809 // op: Zm
31810 return 5;
31811 case 3:
31812 // op: imm
31813 return 16;
31814 }
31815 break;
31816 }
31817 case AArch64::FTMAD_ZZI_D:
31818 case AArch64::FTMAD_ZZI_H:
31819 case AArch64::FTMAD_ZZI_S: {
31820 switch (OpNum) {
31821 case 0:
31822 // op: Zdn
31823 return 0;
31824 case 2:
31825 // op: Zm
31826 return 5;
31827 case 3:
31828 // op: imm3
31829 return 16;
31830 }
31831 break;
31832 }
31833 case AArch64::EXTQ_ZZI: {
31834 switch (OpNum) {
31835 case 0:
31836 // op: Zdn
31837 return 0;
31838 case 2:
31839 // op: Zm
31840 return 5;
31841 case 3:
31842 // op: imm4
31843 return 16;
31844 }
31845 break;
31846 }
31847 case AArch64::EXT_ZZI: {
31848 switch (OpNum) {
31849 case 0:
31850 // op: Zdn
31851 return 0;
31852 case 2:
31853 // op: Zm
31854 return 5;
31855 case 3:
31856 // op: imm8
31857 return 10;
31858 }
31859 break;
31860 }
31861 case AArch64::CADD_ZZI_B:
31862 case AArch64::CADD_ZZI_D:
31863 case AArch64::CADD_ZZI_H:
31864 case AArch64::CADD_ZZI_S:
31865 case AArch64::SQCADD_ZZI_B:
31866 case AArch64::SQCADD_ZZI_D:
31867 case AArch64::SQCADD_ZZI_H:
31868 case AArch64::SQCADD_ZZI_S: {
31869 switch (OpNum) {
31870 case 0:
31871 // op: Zdn
31872 return 0;
31873 case 2:
31874 // op: Zm
31875 return 5;
31876 case 3:
31877 // op: rot
31878 return 10;
31879 }
31880 break;
31881 }
31882 case AArch64::AESD_ZZZ_B:
31883 case AArch64::AESE_ZZZ_B:
31884 case AArch64::SM4E_ZZZ_S: {
31885 switch (OpNum) {
31886 case 0:
31887 // op: Zdn
31888 return 0;
31889 case 2:
31890 // op: Zm
31891 return 5;
31892 }
31893 break;
31894 }
31895 case AArch64::ADD_ZI_B:
31896 case AArch64::ADD_ZI_D:
31897 case AArch64::ADD_ZI_H:
31898 case AArch64::ADD_ZI_S:
31899 case AArch64::MUL_ZI_B:
31900 case AArch64::MUL_ZI_D:
31901 case AArch64::MUL_ZI_H:
31902 case AArch64::MUL_ZI_S:
31903 case AArch64::SMAX_ZI_B:
31904 case AArch64::SMAX_ZI_D:
31905 case AArch64::SMAX_ZI_H:
31906 case AArch64::SMAX_ZI_S:
31907 case AArch64::SMIN_ZI_B:
31908 case AArch64::SMIN_ZI_D:
31909 case AArch64::SMIN_ZI_H:
31910 case AArch64::SMIN_ZI_S:
31911 case AArch64::SQADD_ZI_B:
31912 case AArch64::SQADD_ZI_D:
31913 case AArch64::SQADD_ZI_H:
31914 case AArch64::SQADD_ZI_S:
31915 case AArch64::SQSUB_ZI_B:
31916 case AArch64::SQSUB_ZI_D:
31917 case AArch64::SQSUB_ZI_H:
31918 case AArch64::SQSUB_ZI_S:
31919 case AArch64::SUBR_ZI_B:
31920 case AArch64::SUBR_ZI_D:
31921 case AArch64::SUBR_ZI_H:
31922 case AArch64::SUBR_ZI_S:
31923 case AArch64::SUB_ZI_B:
31924 case AArch64::SUB_ZI_D:
31925 case AArch64::SUB_ZI_H:
31926 case AArch64::SUB_ZI_S:
31927 case AArch64::UMAX_ZI_B:
31928 case AArch64::UMAX_ZI_D:
31929 case AArch64::UMAX_ZI_H:
31930 case AArch64::UMAX_ZI_S:
31931 case AArch64::UMIN_ZI_B:
31932 case AArch64::UMIN_ZI_D:
31933 case AArch64::UMIN_ZI_H:
31934 case AArch64::UMIN_ZI_S:
31935 case AArch64::UQADD_ZI_B:
31936 case AArch64::UQADD_ZI_D:
31937 case AArch64::UQADD_ZI_H:
31938 case AArch64::UQADD_ZI_S:
31939 case AArch64::UQSUB_ZI_B:
31940 case AArch64::UQSUB_ZI_D:
31941 case AArch64::UQSUB_ZI_H:
31942 case AArch64::UQSUB_ZI_S: {
31943 switch (OpNum) {
31944 case 0:
31945 // op: Zdn
31946 return 0;
31947 case 2:
31948 // op: imm
31949 return 5;
31950 }
31951 break;
31952 }
31953 case AArch64::AND_ZI:
31954 case AArch64::EOR_ZI:
31955 case AArch64::ORR_ZI: {
31956 switch (OpNum) {
31957 case 0:
31958 // op: Zdn
31959 return 0;
31960 case 2:
31961 // op: imms13
31962 return 5;
31963 }
31964 break;
31965 }
31966 case AArch64::DECD_ZPiI:
31967 case AArch64::DECH_ZPiI:
31968 case AArch64::DECW_ZPiI:
31969 case AArch64::INCD_ZPiI:
31970 case AArch64::INCH_ZPiI:
31971 case AArch64::INCW_ZPiI:
31972 case AArch64::SQDECD_ZPiI:
31973 case AArch64::SQDECH_ZPiI:
31974 case AArch64::SQDECW_ZPiI:
31975 case AArch64::SQINCD_ZPiI:
31976 case AArch64::SQINCH_ZPiI:
31977 case AArch64::SQINCW_ZPiI:
31978 case AArch64::UQDECD_ZPiI:
31979 case AArch64::UQDECH_ZPiI:
31980 case AArch64::UQDECW_ZPiI:
31981 case AArch64::UQINCD_ZPiI:
31982 case AArch64::UQINCH_ZPiI:
31983 case AArch64::UQINCW_ZPiI: {
31984 switch (OpNum) {
31985 case 0:
31986 // op: Zdn
31987 return 0;
31988 case 2:
31989 // op: pattern
31990 return 5;
31991 case 3:
31992 // op: imm4
31993 return 16;
31994 }
31995 break;
31996 }
31997 case AArch64::BCAX_ZZZZ:
31998 case AArch64::BSL1N_ZZZZ:
31999 case AArch64::BSL2N_ZZZZ:
32000 case AArch64::BSL_ZZZZ:
32001 case AArch64::EOR3_ZZZZ:
32002 case AArch64::NBSL_ZZZZ: {
32003 switch (OpNum) {
32004 case 0:
32005 // op: Zdn
32006 return 0;
32007 case 3:
32008 // op: Zk
32009 return 5;
32010 case 2:
32011 // op: Zm
32012 return 16;
32013 }
32014 break;
32015 }
32016 case AArch64::FCADD_ZPmZ_D:
32017 case AArch64::FCADD_ZPmZ_H:
32018 case AArch64::FCADD_ZPmZ_S: {
32019 switch (OpNum) {
32020 case 0:
32021 // op: Zdn
32022 return 0;
32023 case 3:
32024 // op: Zm
32025 return 5;
32026 case 1:
32027 // op: Pg
32028 return 10;
32029 case 4:
32030 // op: imm
32031 return 16;
32032 }
32033 break;
32034 }
32035 case AArch64::AESIMC_ZZ_B:
32036 case AArch64::AESMC_ZZ_B: {
32037 switch (OpNum) {
32038 case 0:
32039 // op: Zdn
32040 return 0;
32041 }
32042 break;
32043 }
32044 case AArch64::LD1RO_B:
32045 case AArch64::LD1RO_D:
32046 case AArch64::LD1RO_H:
32047 case AArch64::LD1RO_W:
32048 case AArch64::LD1RQ_B:
32049 case AArch64::LD1RQ_D:
32050 case AArch64::LD1RQ_H:
32051 case AArch64::LD1RQ_W: {
32052 switch (OpNum) {
32053 case 0:
32054 // op: Zt
32055 return 0;
32056 case 1:
32057 // op: Pg
32058 return 10;
32059 case 2:
32060 // op: Rn
32061 return 5;
32062 case 3:
32063 // op: Rm
32064 return 16;
32065 }
32066 break;
32067 }
32068 case AArch64::LD2B_IMM:
32069 case AArch64::LD2D_IMM:
32070 case AArch64::LD2H_IMM:
32071 case AArch64::LD2Q_IMM:
32072 case AArch64::LD2W_IMM:
32073 case AArch64::LD3B_IMM:
32074 case AArch64::LD3D_IMM:
32075 case AArch64::LD3H_IMM:
32076 case AArch64::LD3Q_IMM:
32077 case AArch64::LD3W_IMM:
32078 case AArch64::LD4B_IMM:
32079 case AArch64::LD4D_IMM:
32080 case AArch64::LD4H_IMM:
32081 case AArch64::LD4Q_IMM:
32082 case AArch64::LD4W_IMM:
32083 case AArch64::LDNT1B_ZRI:
32084 case AArch64::LDNT1D_ZRI:
32085 case AArch64::LDNT1H_ZRI:
32086 case AArch64::LDNT1W_ZRI: {
32087 switch (OpNum) {
32088 case 0:
32089 // op: Zt
32090 return 0;
32091 case 1:
32092 // op: Pg
32093 return 10;
32094 case 2:
32095 // op: Rn
32096 return 5;
32097 case 3:
32098 // op: imm4
32099 return 16;
32100 }
32101 break;
32102 }
32103 case AArch64::LD1B:
32104 case AArch64::LD1B_D:
32105 case AArch64::LD1B_H:
32106 case AArch64::LD1B_S:
32107 case AArch64::LD1D:
32108 case AArch64::LD1H:
32109 case AArch64::LD1H_D:
32110 case AArch64::LD1H_S:
32111 case AArch64::LD1SB_D:
32112 case AArch64::LD1SB_H:
32113 case AArch64::LD1SB_S:
32114 case AArch64::LD1SH_D:
32115 case AArch64::LD1SH_S:
32116 case AArch64::LD1SW_D:
32117 case AArch64::LD1W:
32118 case AArch64::LD1W_D:
32119 case AArch64::LDFF1B:
32120 case AArch64::LDFF1B_D:
32121 case AArch64::LDFF1B_H:
32122 case AArch64::LDFF1B_S:
32123 case AArch64::LDFF1D:
32124 case AArch64::LDFF1H:
32125 case AArch64::LDFF1H_D:
32126 case AArch64::LDFF1H_S:
32127 case AArch64::LDFF1SB_D:
32128 case AArch64::LDFF1SB_H:
32129 case AArch64::LDFF1SB_S:
32130 case AArch64::LDFF1SH_D:
32131 case AArch64::LDFF1SH_S:
32132 case AArch64::LDFF1SW_D:
32133 case AArch64::LDFF1W:
32134 case AArch64::LDFF1W_D: {
32135 switch (OpNum) {
32136 case 0:
32137 // op: Zt
32138 return 0;
32139 case 1:
32140 // op: Pg
32141 return 10;
32142 case 3:
32143 // op: Rm
32144 return 16;
32145 case 2:
32146 // op: Rn
32147 return 5;
32148 }
32149 break;
32150 }
32151 case AArch64::LD1D_Q:
32152 case AArch64::LD1W_Q:
32153 case AArch64::ST2Q:
32154 case AArch64::ST3Q:
32155 case AArch64::ST4Q: {
32156 switch (OpNum) {
32157 case 0:
32158 // op: Zt
32159 return 0;
32160 case 2:
32161 // op: Rn
32162 return 5;
32163 case 1:
32164 // op: Pg
32165 return 10;
32166 case 3:
32167 // op: Rm
32168 return 16;
32169 }
32170 break;
32171 }
32172 case AArch64::LD1D_Q_IMM:
32173 case AArch64::LD1RO_B_IMM:
32174 case AArch64::LD1RO_D_IMM:
32175 case AArch64::LD1RO_H_IMM:
32176 case AArch64::LD1RO_W_IMM:
32177 case AArch64::LD1RQ_B_IMM:
32178 case AArch64::LD1RQ_D_IMM:
32179 case AArch64::LD1RQ_H_IMM:
32180 case AArch64::LD1RQ_W_IMM:
32181 case AArch64::LD1W_Q_IMM:
32182 case AArch64::ST2Q_IMM:
32183 case AArch64::ST3Q_IMM:
32184 case AArch64::ST4Q_IMM: {
32185 switch (OpNum) {
32186 case 0:
32187 // op: Zt
32188 return 0;
32189 case 2:
32190 // op: Rn
32191 return 5;
32192 case 1:
32193 // op: Pg
32194 return 10;
32195 case 3:
32196 // op: imm4
32197 return 16;
32198 }
32199 break;
32200 }
32201 case AArch64::GLD1Q:
32202 case AArch64::SST1Q: {
32203 switch (OpNum) {
32204 case 0:
32205 // op: Zt
32206 return 0;
32207 case 2:
32208 // op: Zn
32209 return 5;
32210 case 1:
32211 // op: Pg
32212 return 10;
32213 case 3:
32214 // op: Rm
32215 return 16;
32216 }
32217 break;
32218 }
32219 case AArch64::LD1B_2Z_IMM:
32220 case AArch64::LD1D_2Z_IMM:
32221 case AArch64::LD1H_2Z_IMM:
32222 case AArch64::LD1W_2Z_IMM:
32223 case AArch64::LDNT1B_2Z_IMM:
32224 case AArch64::LDNT1D_2Z_IMM:
32225 case AArch64::LDNT1H_2Z_IMM:
32226 case AArch64::LDNT1W_2Z_IMM:
32227 case AArch64::ST1B_2Z_IMM:
32228 case AArch64::ST1D_2Z_IMM:
32229 case AArch64::ST1H_2Z_IMM:
32230 case AArch64::ST1W_2Z_IMM:
32231 case AArch64::STNT1B_2Z_IMM:
32232 case AArch64::STNT1D_2Z_IMM:
32233 case AArch64::STNT1H_2Z_IMM:
32234 case AArch64::STNT1W_2Z_IMM: {
32235 switch (OpNum) {
32236 case 0:
32237 // op: Zt
32238 return 1;
32239 case 2:
32240 // op: Rn
32241 return 5;
32242 case 1:
32243 // op: PNg
32244 return 10;
32245 case 3:
32246 // op: imm4
32247 return 16;
32248 }
32249 break;
32250 }
32251 case AArch64::LD1B_2Z:
32252 case AArch64::LD1D_2Z:
32253 case AArch64::LD1H_2Z:
32254 case AArch64::LD1W_2Z:
32255 case AArch64::LDNT1B_2Z:
32256 case AArch64::LDNT1D_2Z:
32257 case AArch64::LDNT1H_2Z:
32258 case AArch64::LDNT1W_2Z:
32259 case AArch64::ST1B_2Z:
32260 case AArch64::ST1D_2Z:
32261 case AArch64::ST1H_2Z:
32262 case AArch64::ST1W_2Z:
32263 case AArch64::STNT1B_2Z:
32264 case AArch64::STNT1D_2Z:
32265 case AArch64::STNT1H_2Z:
32266 case AArch64::STNT1W_2Z: {
32267 switch (OpNum) {
32268 case 0:
32269 // op: Zt
32270 return 1;
32271 case 3:
32272 // op: Rm
32273 return 16;
32274 case 2:
32275 // op: Rn
32276 return 5;
32277 case 1:
32278 // op: PNg
32279 return 10;
32280 }
32281 break;
32282 }
32283 case AArch64::LD1B_4Z_IMM:
32284 case AArch64::LD1D_4Z_IMM:
32285 case AArch64::LD1H_4Z_IMM:
32286 case AArch64::LD1W_4Z_IMM:
32287 case AArch64::LDNT1B_4Z_IMM:
32288 case AArch64::LDNT1D_4Z_IMM:
32289 case AArch64::LDNT1H_4Z_IMM:
32290 case AArch64::LDNT1W_4Z_IMM:
32291 case AArch64::ST1B_4Z_IMM:
32292 case AArch64::ST1D_4Z_IMM:
32293 case AArch64::ST1H_4Z_IMM:
32294 case AArch64::ST1W_4Z_IMM:
32295 case AArch64::STNT1B_4Z_IMM:
32296 case AArch64::STNT1D_4Z_IMM:
32297 case AArch64::STNT1H_4Z_IMM:
32298 case AArch64::STNT1W_4Z_IMM: {
32299 switch (OpNum) {
32300 case 0:
32301 // op: Zt
32302 return 2;
32303 case 2:
32304 // op: Rn
32305 return 5;
32306 case 1:
32307 // op: PNg
32308 return 10;
32309 case 3:
32310 // op: imm4
32311 return 16;
32312 }
32313 break;
32314 }
32315 case AArch64::LD1B_4Z:
32316 case AArch64::LD1D_4Z:
32317 case AArch64::LD1H_4Z:
32318 case AArch64::LD1W_4Z:
32319 case AArch64::LDNT1B_4Z:
32320 case AArch64::LDNT1D_4Z:
32321 case AArch64::LDNT1H_4Z:
32322 case AArch64::LDNT1W_4Z:
32323 case AArch64::ST1B_4Z:
32324 case AArch64::ST1D_4Z:
32325 case AArch64::ST1H_4Z:
32326 case AArch64::ST1W_4Z:
32327 case AArch64::STNT1B_4Z:
32328 case AArch64::STNT1D_4Z:
32329 case AArch64::STNT1H_4Z:
32330 case AArch64::STNT1W_4Z: {
32331 switch (OpNum) {
32332 case 0:
32333 // op: Zt
32334 return 2;
32335 case 3:
32336 // op: Rm
32337 return 16;
32338 case 2:
32339 // op: Rn
32340 return 5;
32341 case 1:
32342 // op: PNg
32343 return 10;
32344 }
32345 break;
32346 }
32347 case AArch64::B:
32348 case AArch64::BL: {
32349 switch (OpNum) {
32350 case 0:
32351 // op: addr
32352 return 0;
32353 }
32354 break;
32355 }
32356 case AArch64::BCcc:
32357 case AArch64::Bcc: {
32358 switch (OpNum) {
32359 case 0:
32360 // op: cond
32361 return 0;
32362 case 1:
32363 // op: target
32364 return 5;
32365 }
32366 break;
32367 }
32368 case AArch64::DUPi8: {
32369 switch (OpNum) {
32370 case 0:
32371 // op: dst
32372 return 0;
32373 case 1:
32374 // op: src
32375 return 5;
32376 case 2:
32377 // op: idx
32378 return 17;
32379 }
32380 break;
32381 }
32382 case AArch64::DUPi16: {
32383 switch (OpNum) {
32384 case 0:
32385 // op: dst
32386 return 0;
32387 case 1:
32388 // op: src
32389 return 5;
32390 case 2:
32391 // op: idx
32392 return 18;
32393 }
32394 break;
32395 }
32396 case AArch64::DUPi32: {
32397 switch (OpNum) {
32398 case 0:
32399 // op: dst
32400 return 0;
32401 case 1:
32402 // op: src
32403 return 5;
32404 case 2:
32405 // op: idx
32406 return 19;
32407 }
32408 break;
32409 }
32410 case AArch64::DUPi64: {
32411 switch (OpNum) {
32412 case 0:
32413 // op: dst
32414 return 0;
32415 case 1:
32416 // op: src
32417 return 5;
32418 case 2:
32419 // op: idx
32420 return 20;
32421 }
32422 break;
32423 }
32424 case AArch64::UDF:
32425 case AArch64::ZERO_M: {
32426 switch (OpNum) {
32427 case 0:
32428 // op: imm
32429 return 0;
32430 }
32431 break;
32432 }
32433 case AArch64::BRK:
32434 case AArch64::DCPS1:
32435 case AArch64::DCPS2:
32436 case AArch64::DCPS3:
32437 case AArch64::HINT:
32438 case AArch64::HLT:
32439 case AArch64::HVC:
32440 case AArch64::SMC:
32441 case AArch64::SVC:
32442 case AArch64::TCANCEL: {
32443 switch (OpNum) {
32444 case 0:
32445 // op: imm
32446 return 5;
32447 }
32448 break;
32449 }
32450 case AArch64::AUTIASPPCi:
32451 case AArch64::AUTIBSPPCi:
32452 case AArch64::RETAASPPCi:
32453 case AArch64::RETABSPPCi: {
32454 switch (OpNum) {
32455 case 0:
32456 // op: label
32457 return 5;
32458 }
32459 break;
32460 }
32461 case AArch64::SYSPxt_XZR: {
32462 switch (OpNum) {
32463 case 0:
32464 // op: op1
32465 return 16;
32466 case 1:
32467 // op: Cn
32468 return 12;
32469 case 2:
32470 // op: Cm
32471 return 8;
32472 case 3:
32473 // op: op2
32474 return 5;
32475 }
32476 break;
32477 }
32478 case AArch64::STSHH: {
32479 switch (OpNum) {
32480 case 0:
32481 // op: policy
32482 return 5;
32483 }
32484 break;
32485 }
32486 case AArch64::MSRpstateImm1:
32487 case AArch64::MSRpstateImm4: {
32488 switch (OpNum) {
32489 case 0:
32490 // op: pstatefield
32491 return 5;
32492 case 1:
32493 // op: imm
32494 return 8;
32495 }
32496 break;
32497 }
32498 case AArch64::MSRpstatesvcrImm1: {
32499 switch (OpNum) {
32500 case 0:
32501 // op: pstatefield
32502 return 9;
32503 case 1:
32504 // op: imm
32505 return 8;
32506 }
32507 break;
32508 }
32509 case AArch64::SEL_VG2_2ZC2Z2Z_B:
32510 case AArch64::SEL_VG2_2ZC2Z2Z_D:
32511 case AArch64::SEL_VG2_2ZC2Z2Z_H:
32512 case AArch64::SEL_VG2_2ZC2Z2Z_S: {
32513 switch (OpNum) {
32514 case 1:
32515 // op: PNg
32516 return 10;
32517 case 3:
32518 // op: Zm
32519 return 17;
32520 case 2:
32521 // op: Zn
32522 return 6;
32523 case 0:
32524 // op: Zd
32525 return 1;
32526 }
32527 break;
32528 }
32529 case AArch64::SEL_VG4_4ZC4Z4Z_B:
32530 case AArch64::SEL_VG4_4ZC4Z4Z_D:
32531 case AArch64::SEL_VG4_4ZC4Z4Z_H:
32532 case AArch64::SEL_VG4_4ZC4Z4Z_S: {
32533 switch (OpNum) {
32534 case 1:
32535 // op: PNg
32536 return 10;
32537 case 3:
32538 // op: Zm
32539 return 18;
32540 case 2:
32541 // op: Zn
32542 return 7;
32543 case 0:
32544 // op: Zd
32545 return 2;
32546 }
32547 break;
32548 }
32549 case AArch64::LASTA_RPZ_B:
32550 case AArch64::LASTA_RPZ_D:
32551 case AArch64::LASTA_RPZ_H:
32552 case AArch64::LASTA_RPZ_S:
32553 case AArch64::LASTB_RPZ_B:
32554 case AArch64::LASTB_RPZ_D:
32555 case AArch64::LASTB_RPZ_H:
32556 case AArch64::LASTB_RPZ_S: {
32557 switch (OpNum) {
32558 case 1:
32559 // op: Pg
32560 return 10;
32561 case 0:
32562 // op: Rd
32563 return 0;
32564 case 2:
32565 // op: Zn
32566 return 5;
32567 }
32568 break;
32569 }
32570 case AArch64::CLASTA_RPZ_B:
32571 case AArch64::CLASTA_RPZ_D:
32572 case AArch64::CLASTA_RPZ_H:
32573 case AArch64::CLASTA_RPZ_S:
32574 case AArch64::CLASTB_RPZ_B:
32575 case AArch64::CLASTB_RPZ_D:
32576 case AArch64::CLASTB_RPZ_H:
32577 case AArch64::CLASTB_RPZ_S: {
32578 switch (OpNum) {
32579 case 1:
32580 // op: Pg
32581 return 10;
32582 case 0:
32583 // op: Rdn
32584 return 0;
32585 case 3:
32586 // op: Zm
32587 return 5;
32588 }
32589 break;
32590 }
32591 case AArch64::ANDV_VPZ_B:
32592 case AArch64::ANDV_VPZ_D:
32593 case AArch64::ANDV_VPZ_H:
32594 case AArch64::ANDV_VPZ_S:
32595 case AArch64::EORV_VPZ_B:
32596 case AArch64::EORV_VPZ_D:
32597 case AArch64::EORV_VPZ_H:
32598 case AArch64::EORV_VPZ_S:
32599 case AArch64::LASTA_VPZ_B:
32600 case AArch64::LASTA_VPZ_D:
32601 case AArch64::LASTA_VPZ_H:
32602 case AArch64::LASTA_VPZ_S:
32603 case AArch64::LASTB_VPZ_B:
32604 case AArch64::LASTB_VPZ_D:
32605 case AArch64::LASTB_VPZ_H:
32606 case AArch64::LASTB_VPZ_S:
32607 case AArch64::ORV_VPZ_B:
32608 case AArch64::ORV_VPZ_D:
32609 case AArch64::ORV_VPZ_H:
32610 case AArch64::ORV_VPZ_S:
32611 case AArch64::SADDV_VPZ_B:
32612 case AArch64::SADDV_VPZ_H:
32613 case AArch64::SADDV_VPZ_S:
32614 case AArch64::SMAXV_VPZ_B:
32615 case AArch64::SMAXV_VPZ_D:
32616 case AArch64::SMAXV_VPZ_H:
32617 case AArch64::SMAXV_VPZ_S:
32618 case AArch64::SMINV_VPZ_B:
32619 case AArch64::SMINV_VPZ_D:
32620 case AArch64::SMINV_VPZ_H:
32621 case AArch64::SMINV_VPZ_S:
32622 case AArch64::UADDV_VPZ_B:
32623 case AArch64::UADDV_VPZ_D:
32624 case AArch64::UADDV_VPZ_H:
32625 case AArch64::UADDV_VPZ_S:
32626 case AArch64::UMAXV_VPZ_B:
32627 case AArch64::UMAXV_VPZ_D:
32628 case AArch64::UMAXV_VPZ_H:
32629 case AArch64::UMAXV_VPZ_S:
32630 case AArch64::UMINV_VPZ_B:
32631 case AArch64::UMINV_VPZ_D:
32632 case AArch64::UMINV_VPZ_H:
32633 case AArch64::UMINV_VPZ_S: {
32634 switch (OpNum) {
32635 case 1:
32636 // op: Pg
32637 return 10;
32638 case 0:
32639 // op: Vd
32640 return 0;
32641 case 2:
32642 // op: Zn
32643 return 5;
32644 }
32645 break;
32646 }
32647 case AArch64::CLASTA_VPZ_B:
32648 case AArch64::CLASTA_VPZ_D:
32649 case AArch64::CLASTA_VPZ_H:
32650 case AArch64::CLASTA_VPZ_S:
32651 case AArch64::CLASTB_VPZ_B:
32652 case AArch64::CLASTB_VPZ_D:
32653 case AArch64::CLASTB_VPZ_H:
32654 case AArch64::CLASTB_VPZ_S:
32655 case AArch64::FADDA_VPZ_D:
32656 case AArch64::FADDA_VPZ_H:
32657 case AArch64::FADDA_VPZ_S: {
32658 switch (OpNum) {
32659 case 1:
32660 // op: Pg
32661 return 10;
32662 case 0:
32663 // op: Vdn
32664 return 0;
32665 case 3:
32666 // op: Zm
32667 return 5;
32668 }
32669 break;
32670 }
32671 case AArch64::ABS_ZPzZ_B:
32672 case AArch64::ABS_ZPzZ_D:
32673 case AArch64::ABS_ZPzZ_H:
32674 case AArch64::ABS_ZPzZ_S:
32675 case AArch64::BFCVT_ZPzZ_StoH:
32676 case AArch64::CLS_ZPzZ_B:
32677 case AArch64::CLS_ZPzZ_D:
32678 case AArch64::CLS_ZPzZ_H:
32679 case AArch64::CLS_ZPzZ_S:
32680 case AArch64::CLZ_ZPzZ_B:
32681 case AArch64::CLZ_ZPzZ_D:
32682 case AArch64::CLZ_ZPzZ_H:
32683 case AArch64::CLZ_ZPzZ_S:
32684 case AArch64::CNOT_ZPzZ_B:
32685 case AArch64::CNOT_ZPzZ_D:
32686 case AArch64::CNOT_ZPzZ_H:
32687 case AArch64::CNOT_ZPzZ_S:
32688 case AArch64::CNT_ZPzZ_B:
32689 case AArch64::CNT_ZPzZ_D:
32690 case AArch64::CNT_ZPzZ_H:
32691 case AArch64::CNT_ZPzZ_S:
32692 case AArch64::COMPACT_ZPZ_B:
32693 case AArch64::COMPACT_ZPZ_D:
32694 case AArch64::COMPACT_ZPZ_H:
32695 case AArch64::COMPACT_ZPZ_S:
32696 case AArch64::FABS_ZPzZ_D:
32697 case AArch64::FABS_ZPzZ_H:
32698 case AArch64::FABS_ZPzZ_S:
32699 case AArch64::FCVTX_ZPzZ_DtoS:
32700 case AArch64::FCVTZS_ZPzZ_DtoD:
32701 case AArch64::FCVTZS_ZPzZ_DtoS:
32702 case AArch64::FCVTZS_ZPzZ_HtoD:
32703 case AArch64::FCVTZS_ZPzZ_HtoH:
32704 case AArch64::FCVTZS_ZPzZ_HtoS:
32705 case AArch64::FCVTZS_ZPzZ_StoD:
32706 case AArch64::FCVTZS_ZPzZ_StoS:
32707 case AArch64::FCVTZU_ZPzZ_DtoD:
32708 case AArch64::FCVTZU_ZPzZ_DtoS:
32709 case AArch64::FCVTZU_ZPzZ_HtoD:
32710 case AArch64::FCVTZU_ZPzZ_HtoH:
32711 case AArch64::FCVTZU_ZPzZ_HtoS:
32712 case AArch64::FCVTZU_ZPzZ_StoD:
32713 case AArch64::FCVTZU_ZPzZ_StoS:
32714 case AArch64::FCVT_ZPzZ_DtoH:
32715 case AArch64::FCVT_ZPzZ_DtoS:
32716 case AArch64::FCVT_ZPzZ_HtoD:
32717 case AArch64::FCVT_ZPzZ_HtoS:
32718 case AArch64::FCVT_ZPzZ_StoD:
32719 case AArch64::FCVT_ZPzZ_StoH:
32720 case AArch64::FLOGB_ZPzZ_D:
32721 case AArch64::FLOGB_ZPzZ_H:
32722 case AArch64::FLOGB_ZPzZ_S:
32723 case AArch64::FNEG_ZPzZ_D:
32724 case AArch64::FNEG_ZPzZ_H:
32725 case AArch64::FNEG_ZPzZ_S:
32726 case AArch64::FRECPX_ZPzZ_D:
32727 case AArch64::FRECPX_ZPzZ_H:
32728 case AArch64::FRECPX_ZPzZ_S:
32729 case AArch64::FRINT32X_ZPzZ_D:
32730 case AArch64::FRINT32X_ZPzZ_S:
32731 case AArch64::FRINT32Z_ZPzZ_D:
32732 case AArch64::FRINT32Z_ZPzZ_S:
32733 case AArch64::FRINT64X_ZPzZ_D:
32734 case AArch64::FRINT64X_ZPzZ_S:
32735 case AArch64::FRINT64Z_ZPzZ_D:
32736 case AArch64::FRINT64Z_ZPzZ_S:
32737 case AArch64::FRINTA_ZPzZ_D:
32738 case AArch64::FRINTA_ZPzZ_H:
32739 case AArch64::FRINTA_ZPzZ_S:
32740 case AArch64::FRINTI_ZPzZ_D:
32741 case AArch64::FRINTI_ZPzZ_H:
32742 case AArch64::FRINTI_ZPzZ_S:
32743 case AArch64::FRINTM_ZPzZ_D:
32744 case AArch64::FRINTM_ZPzZ_H:
32745 case AArch64::FRINTM_ZPzZ_S:
32746 case AArch64::FRINTN_ZPzZ_D:
32747 case AArch64::FRINTN_ZPzZ_H:
32748 case AArch64::FRINTN_ZPzZ_S:
32749 case AArch64::FRINTP_ZPzZ_D:
32750 case AArch64::FRINTP_ZPzZ_H:
32751 case AArch64::FRINTP_ZPzZ_S:
32752 case AArch64::FRINTX_ZPzZ_D:
32753 case AArch64::FRINTX_ZPzZ_H:
32754 case AArch64::FRINTX_ZPzZ_S:
32755 case AArch64::FRINTZ_ZPzZ_D:
32756 case AArch64::FRINTZ_ZPzZ_H:
32757 case AArch64::FRINTZ_ZPzZ_S:
32758 case AArch64::FSQRT_ZPZz_D:
32759 case AArch64::FSQRT_ZPZz_H:
32760 case AArch64::FSQRT_ZPZz_S:
32761 case AArch64::MOVPRFX_ZPzZ_B:
32762 case AArch64::MOVPRFX_ZPzZ_D:
32763 case AArch64::MOVPRFX_ZPzZ_H:
32764 case AArch64::MOVPRFX_ZPzZ_S:
32765 case AArch64::NEG_ZPzZ_B:
32766 case AArch64::NEG_ZPzZ_D:
32767 case AArch64::NEG_ZPzZ_H:
32768 case AArch64::NEG_ZPzZ_S:
32769 case AArch64::NOT_ZPzZ_B:
32770 case AArch64::NOT_ZPzZ_D:
32771 case AArch64::NOT_ZPzZ_H:
32772 case AArch64::NOT_ZPzZ_S:
32773 case AArch64::SCVTF_ZPzZ_DtoD:
32774 case AArch64::SCVTF_ZPzZ_DtoH:
32775 case AArch64::SCVTF_ZPzZ_DtoS:
32776 case AArch64::SCVTF_ZPzZ_HtoH:
32777 case AArch64::SCVTF_ZPzZ_StoD:
32778 case AArch64::SCVTF_ZPzZ_StoH:
32779 case AArch64::SCVTF_ZPzZ_StoS:
32780 case AArch64::SQABS_ZPzZ_B:
32781 case AArch64::SQABS_ZPzZ_D:
32782 case AArch64::SQABS_ZPzZ_H:
32783 case AArch64::SQABS_ZPzZ_S:
32784 case AArch64::SQNEG_ZPzZ_B:
32785 case AArch64::SQNEG_ZPzZ_D:
32786 case AArch64::SQNEG_ZPzZ_H:
32787 case AArch64::SQNEG_ZPzZ_S:
32788 case AArch64::SXTB_ZPzZ_D:
32789 case AArch64::SXTB_ZPzZ_H:
32790 case AArch64::SXTB_ZPzZ_S:
32791 case AArch64::SXTH_ZPzZ_D:
32792 case AArch64::SXTH_ZPzZ_S:
32793 case AArch64::SXTW_ZPzZ_D:
32794 case AArch64::UCVTF_ZPzZ_DtoD:
32795 case AArch64::UCVTF_ZPzZ_DtoH:
32796 case AArch64::UCVTF_ZPzZ_DtoS:
32797 case AArch64::UCVTF_ZPzZ_HtoH:
32798 case AArch64::UCVTF_ZPzZ_StoD:
32799 case AArch64::UCVTF_ZPzZ_StoH:
32800 case AArch64::UCVTF_ZPzZ_StoS:
32801 case AArch64::URECPE_ZPzZ_S:
32802 case AArch64::URSQRTE_ZPzZ_S:
32803 case AArch64::UXTB_ZPzZ_D:
32804 case AArch64::UXTB_ZPzZ_H:
32805 case AArch64::UXTB_ZPzZ_S:
32806 case AArch64::UXTH_ZPzZ_D:
32807 case AArch64::UXTH_ZPzZ_S:
32808 case AArch64::UXTW_ZPzZ_D: {
32809 switch (OpNum) {
32810 case 1:
32811 // op: Pg
32812 return 10;
32813 case 0:
32814 // op: Zd
32815 return 0;
32816 case 2:
32817 // op: Zn
32818 return 5;
32819 }
32820 break;
32821 }
32822 case AArch64::SEL_ZPZZ_B:
32823 case AArch64::SEL_ZPZZ_D:
32824 case AArch64::SEL_ZPZZ_H:
32825 case AArch64::SEL_ZPZZ_S: {
32826 switch (OpNum) {
32827 case 1:
32828 // op: Pg
32829 return 10;
32830 case 0:
32831 // op: Zd
32832 return 0;
32833 case 3:
32834 // op: Zm
32835 return 16;
32836 case 2:
32837 // op: Zn
32838 return 5;
32839 }
32840 break;
32841 }
32842 case AArch64::BFMLA_ZPmZZ:
32843 case AArch64::BFMLS_ZPmZZ:
32844 case AArch64::FMLA_ZPmZZ_D:
32845 case AArch64::FMLA_ZPmZZ_H:
32846 case AArch64::FMLA_ZPmZZ_S:
32847 case AArch64::FMLS_ZPmZZ_D:
32848 case AArch64::FMLS_ZPmZZ_H:
32849 case AArch64::FMLS_ZPmZZ_S:
32850 case AArch64::FNMLA_ZPmZZ_D:
32851 case AArch64::FNMLA_ZPmZZ_H:
32852 case AArch64::FNMLA_ZPmZZ_S:
32853 case AArch64::FNMLS_ZPmZZ_D:
32854 case AArch64::FNMLS_ZPmZZ_H:
32855 case AArch64::FNMLS_ZPmZZ_S:
32856 case AArch64::MLA_ZPmZZ_B:
32857 case AArch64::MLA_ZPmZZ_D:
32858 case AArch64::MLA_ZPmZZ_H:
32859 case AArch64::MLA_ZPmZZ_S:
32860 case AArch64::MLS_ZPmZZ_B:
32861 case AArch64::MLS_ZPmZZ_D:
32862 case AArch64::MLS_ZPmZZ_H:
32863 case AArch64::MLS_ZPmZZ_S: {
32864 switch (OpNum) {
32865 case 1:
32866 // op: Pg
32867 return 10;
32868 case 0:
32869 // op: Zda
32870 return 0;
32871 case 4:
32872 // op: Zm
32873 return 16;
32874 case 3:
32875 // op: Zn
32876 return 5;
32877 }
32878 break;
32879 }
32880 case AArch64::ADD_ZPmZ_B:
32881 case AArch64::ADD_ZPmZ_CPA:
32882 case AArch64::ADD_ZPmZ_D:
32883 case AArch64::ADD_ZPmZ_H:
32884 case AArch64::ADD_ZPmZ_S:
32885 case AArch64::AND_ZPmZ_B:
32886 case AArch64::AND_ZPmZ_D:
32887 case AArch64::AND_ZPmZ_H:
32888 case AArch64::AND_ZPmZ_S:
32889 case AArch64::ASRR_ZPmZ_B:
32890 case AArch64::ASRR_ZPmZ_D:
32891 case AArch64::ASRR_ZPmZ_H:
32892 case AArch64::ASRR_ZPmZ_S:
32893 case AArch64::ASR_WIDE_ZPmZ_B:
32894 case AArch64::ASR_WIDE_ZPmZ_H:
32895 case AArch64::ASR_WIDE_ZPmZ_S:
32896 case AArch64::ASR_ZPmZ_B:
32897 case AArch64::ASR_ZPmZ_D:
32898 case AArch64::ASR_ZPmZ_H:
32899 case AArch64::ASR_ZPmZ_S:
32900 case AArch64::BFADD_ZPmZZ:
32901 case AArch64::BFMAXNM_ZPmZZ:
32902 case AArch64::BFMAX_ZPmZZ:
32903 case AArch64::BFMINNM_ZPmZZ:
32904 case AArch64::BFMIN_ZPmZZ:
32905 case AArch64::BFMUL_ZPmZZ:
32906 case AArch64::BFSCALE_ZPZZ:
32907 case AArch64::BFSUB_ZPmZZ:
32908 case AArch64::BIC_ZPmZ_B:
32909 case AArch64::BIC_ZPmZ_D:
32910 case AArch64::BIC_ZPmZ_H:
32911 case AArch64::BIC_ZPmZ_S:
32912 case AArch64::CLASTA_ZPZ_B:
32913 case AArch64::CLASTA_ZPZ_D:
32914 case AArch64::CLASTA_ZPZ_H:
32915 case AArch64::CLASTA_ZPZ_S:
32916 case AArch64::CLASTB_ZPZ_B:
32917 case AArch64::CLASTB_ZPZ_D:
32918 case AArch64::CLASTB_ZPZ_H:
32919 case AArch64::CLASTB_ZPZ_S:
32920 case AArch64::EOR_ZPmZ_B:
32921 case AArch64::EOR_ZPmZ_D:
32922 case AArch64::EOR_ZPmZ_H:
32923 case AArch64::EOR_ZPmZ_S:
32924 case AArch64::FABD_ZPmZ_D:
32925 case AArch64::FABD_ZPmZ_H:
32926 case AArch64::FABD_ZPmZ_S:
32927 case AArch64::FADD_ZPmZ_D:
32928 case AArch64::FADD_ZPmZ_H:
32929 case AArch64::FADD_ZPmZ_S:
32930 case AArch64::FAMAX_ZPmZ_D:
32931 case AArch64::FAMAX_ZPmZ_H:
32932 case AArch64::FAMAX_ZPmZ_S:
32933 case AArch64::FAMIN_ZPmZ_D:
32934 case AArch64::FAMIN_ZPmZ_H:
32935 case AArch64::FAMIN_ZPmZ_S:
32936 case AArch64::FDIVR_ZPmZ_D:
32937 case AArch64::FDIVR_ZPmZ_H:
32938 case AArch64::FDIVR_ZPmZ_S:
32939 case AArch64::FDIV_ZPmZ_D:
32940 case AArch64::FDIV_ZPmZ_H:
32941 case AArch64::FDIV_ZPmZ_S:
32942 case AArch64::FMAXNM_ZPmZ_D:
32943 case AArch64::FMAXNM_ZPmZ_H:
32944 case AArch64::FMAXNM_ZPmZ_S:
32945 case AArch64::FMAX_ZPmZ_D:
32946 case AArch64::FMAX_ZPmZ_H:
32947 case AArch64::FMAX_ZPmZ_S:
32948 case AArch64::FMINNM_ZPmZ_D:
32949 case AArch64::FMINNM_ZPmZ_H:
32950 case AArch64::FMINNM_ZPmZ_S:
32951 case AArch64::FMIN_ZPmZ_D:
32952 case AArch64::FMIN_ZPmZ_H:
32953 case AArch64::FMIN_ZPmZ_S:
32954 case AArch64::FMULX_ZPmZ_D:
32955 case AArch64::FMULX_ZPmZ_H:
32956 case AArch64::FMULX_ZPmZ_S:
32957 case AArch64::FMUL_ZPmZ_D:
32958 case AArch64::FMUL_ZPmZ_H:
32959 case AArch64::FMUL_ZPmZ_S:
32960 case AArch64::FSCALE_ZPmZ_D:
32961 case AArch64::FSCALE_ZPmZ_H:
32962 case AArch64::FSCALE_ZPmZ_S:
32963 case AArch64::FSUBR_ZPmZ_D:
32964 case AArch64::FSUBR_ZPmZ_H:
32965 case AArch64::FSUBR_ZPmZ_S:
32966 case AArch64::FSUB_ZPmZ_D:
32967 case AArch64::FSUB_ZPmZ_H:
32968 case AArch64::FSUB_ZPmZ_S:
32969 case AArch64::LSLR_ZPmZ_B:
32970 case AArch64::LSLR_ZPmZ_D:
32971 case AArch64::LSLR_ZPmZ_H:
32972 case AArch64::LSLR_ZPmZ_S:
32973 case AArch64::LSL_WIDE_ZPmZ_B:
32974 case AArch64::LSL_WIDE_ZPmZ_H:
32975 case AArch64::LSL_WIDE_ZPmZ_S:
32976 case AArch64::LSL_ZPmZ_B:
32977 case AArch64::LSL_ZPmZ_D:
32978 case AArch64::LSL_ZPmZ_H:
32979 case AArch64::LSL_ZPmZ_S:
32980 case AArch64::LSRR_ZPmZ_B:
32981 case AArch64::LSRR_ZPmZ_D:
32982 case AArch64::LSRR_ZPmZ_H:
32983 case AArch64::LSRR_ZPmZ_S:
32984 case AArch64::LSR_WIDE_ZPmZ_B:
32985 case AArch64::LSR_WIDE_ZPmZ_H:
32986 case AArch64::LSR_WIDE_ZPmZ_S:
32987 case AArch64::LSR_ZPmZ_B:
32988 case AArch64::LSR_ZPmZ_D:
32989 case AArch64::LSR_ZPmZ_H:
32990 case AArch64::LSR_ZPmZ_S:
32991 case AArch64::MUL_ZPmZ_B:
32992 case AArch64::MUL_ZPmZ_D:
32993 case AArch64::MUL_ZPmZ_H:
32994 case AArch64::MUL_ZPmZ_S:
32995 case AArch64::ORR_ZPmZ_B:
32996 case AArch64::ORR_ZPmZ_D:
32997 case AArch64::ORR_ZPmZ_H:
32998 case AArch64::ORR_ZPmZ_S:
32999 case AArch64::SABD_ZPmZ_B:
33000 case AArch64::SABD_ZPmZ_D:
33001 case AArch64::SABD_ZPmZ_H:
33002 case AArch64::SABD_ZPmZ_S:
33003 case AArch64::SDIVR_ZPmZ_D:
33004 case AArch64::SDIVR_ZPmZ_S:
33005 case AArch64::SDIV_ZPmZ_D:
33006 case AArch64::SDIV_ZPmZ_S:
33007 case AArch64::SMAX_ZPmZ_B:
33008 case AArch64::SMAX_ZPmZ_D:
33009 case AArch64::SMAX_ZPmZ_H:
33010 case AArch64::SMAX_ZPmZ_S:
33011 case AArch64::SMIN_ZPmZ_B:
33012 case AArch64::SMIN_ZPmZ_D:
33013 case AArch64::SMIN_ZPmZ_H:
33014 case AArch64::SMIN_ZPmZ_S:
33015 case AArch64::SMULH_ZPmZ_B:
33016 case AArch64::SMULH_ZPmZ_D:
33017 case AArch64::SMULH_ZPmZ_H:
33018 case AArch64::SMULH_ZPmZ_S:
33019 case AArch64::SPLICE_ZPZ_B:
33020 case AArch64::SPLICE_ZPZ_D:
33021 case AArch64::SPLICE_ZPZ_H:
33022 case AArch64::SPLICE_ZPZ_S:
33023 case AArch64::SUBR_ZPmZ_B:
33024 case AArch64::SUBR_ZPmZ_D:
33025 case AArch64::SUBR_ZPmZ_H:
33026 case AArch64::SUBR_ZPmZ_S:
33027 case AArch64::SUB_ZPmZ_B:
33028 case AArch64::SUB_ZPmZ_CPA:
33029 case AArch64::SUB_ZPmZ_D:
33030 case AArch64::SUB_ZPmZ_H:
33031 case AArch64::SUB_ZPmZ_S:
33032 case AArch64::UABD_ZPmZ_B:
33033 case AArch64::UABD_ZPmZ_D:
33034 case AArch64::UABD_ZPmZ_H:
33035 case AArch64::UABD_ZPmZ_S:
33036 case AArch64::UDIVR_ZPmZ_D:
33037 case AArch64::UDIVR_ZPmZ_S:
33038 case AArch64::UDIV_ZPmZ_D:
33039 case AArch64::UDIV_ZPmZ_S:
33040 case AArch64::UMAX_ZPmZ_B:
33041 case AArch64::UMAX_ZPmZ_D:
33042 case AArch64::UMAX_ZPmZ_H:
33043 case AArch64::UMAX_ZPmZ_S:
33044 case AArch64::UMIN_ZPmZ_B:
33045 case AArch64::UMIN_ZPmZ_D:
33046 case AArch64::UMIN_ZPmZ_H:
33047 case AArch64::UMIN_ZPmZ_S:
33048 case AArch64::UMULH_ZPmZ_B:
33049 case AArch64::UMULH_ZPmZ_D:
33050 case AArch64::UMULH_ZPmZ_H:
33051 case AArch64::UMULH_ZPmZ_S: {
33052 switch (OpNum) {
33053 case 1:
33054 // op: Pg
33055 return 10;
33056 case 0:
33057 // op: Zdn
33058 return 0;
33059 case 3:
33060 // op: Zm
33061 return 5;
33062 }
33063 break;
33064 }
33065 case AArch64::FADD_ZPmI_D:
33066 case AArch64::FADD_ZPmI_H:
33067 case AArch64::FADD_ZPmI_S:
33068 case AArch64::FMAXNM_ZPmI_D:
33069 case AArch64::FMAXNM_ZPmI_H:
33070 case AArch64::FMAXNM_ZPmI_S:
33071 case AArch64::FMAX_ZPmI_D:
33072 case AArch64::FMAX_ZPmI_H:
33073 case AArch64::FMAX_ZPmI_S:
33074 case AArch64::FMINNM_ZPmI_D:
33075 case AArch64::FMINNM_ZPmI_H:
33076 case AArch64::FMINNM_ZPmI_S:
33077 case AArch64::FMIN_ZPmI_D:
33078 case AArch64::FMIN_ZPmI_H:
33079 case AArch64::FMIN_ZPmI_S:
33080 case AArch64::FMUL_ZPmI_D:
33081 case AArch64::FMUL_ZPmI_H:
33082 case AArch64::FMUL_ZPmI_S:
33083 case AArch64::FSUBR_ZPmI_D:
33084 case AArch64::FSUBR_ZPmI_H:
33085 case AArch64::FSUBR_ZPmI_S:
33086 case AArch64::FSUB_ZPmI_D:
33087 case AArch64::FSUB_ZPmI_H:
33088 case AArch64::FSUB_ZPmI_S: {
33089 switch (OpNum) {
33090 case 1:
33091 // op: Pg
33092 return 10;
33093 case 0:
33094 // op: Zdn
33095 return 0;
33096 case 3:
33097 // op: i1
33098 return 5;
33099 }
33100 break;
33101 }
33102 case AArch64::ASRD_ZPmI_B:
33103 case AArch64::ASRD_ZPmI_D:
33104 case AArch64::ASRD_ZPmI_H:
33105 case AArch64::ASRD_ZPmI_S:
33106 case AArch64::ASR_ZPmI_B:
33107 case AArch64::ASR_ZPmI_D:
33108 case AArch64::ASR_ZPmI_H:
33109 case AArch64::ASR_ZPmI_S:
33110 case AArch64::LSL_ZPmI_B:
33111 case AArch64::LSL_ZPmI_D:
33112 case AArch64::LSL_ZPmI_H:
33113 case AArch64::LSL_ZPmI_S:
33114 case AArch64::LSR_ZPmI_B:
33115 case AArch64::LSR_ZPmI_D:
33116 case AArch64::LSR_ZPmI_H:
33117 case AArch64::LSR_ZPmI_S:
33118 case AArch64::SQSHLU_ZPmI_B:
33119 case AArch64::SQSHLU_ZPmI_D:
33120 case AArch64::SQSHLU_ZPmI_H:
33121 case AArch64::SQSHLU_ZPmI_S:
33122 case AArch64::SQSHL_ZPmI_B:
33123 case AArch64::SQSHL_ZPmI_D:
33124 case AArch64::SQSHL_ZPmI_H:
33125 case AArch64::SQSHL_ZPmI_S:
33126 case AArch64::SRSHR_ZPmI_B:
33127 case AArch64::SRSHR_ZPmI_D:
33128 case AArch64::SRSHR_ZPmI_H:
33129 case AArch64::SRSHR_ZPmI_S:
33130 case AArch64::UQSHL_ZPmI_B:
33131 case AArch64::UQSHL_ZPmI_D:
33132 case AArch64::UQSHL_ZPmI_H:
33133 case AArch64::UQSHL_ZPmI_S:
33134 case AArch64::URSHR_ZPmI_B:
33135 case AArch64::URSHR_ZPmI_D:
33136 case AArch64::URSHR_ZPmI_H:
33137 case AArch64::URSHR_ZPmI_S: {
33138 switch (OpNum) {
33139 case 1:
33140 // op: Pg
33141 return 10;
33142 case 0:
33143 // op: Zdn
33144 return 0;
33145 case 3:
33146 // op: imm
33147 return 5;
33148 }
33149 break;
33150 }
33151 case AArch64::MAD_ZPmZZ_B:
33152 case AArch64::MAD_ZPmZZ_D:
33153 case AArch64::MAD_ZPmZZ_H:
33154 case AArch64::MAD_ZPmZZ_S:
33155 case AArch64::MSB_ZPmZZ_B:
33156 case AArch64::MSB_ZPmZZ_D:
33157 case AArch64::MSB_ZPmZZ_H:
33158 case AArch64::MSB_ZPmZZ_S: {
33159 switch (OpNum) {
33160 case 1:
33161 // op: Pg
33162 return 10;
33163 case 0:
33164 // op: Zdn
33165 return 0;
33166 case 4:
33167 // op: Za
33168 return 5;
33169 case 3:
33170 // op: Zm
33171 return 16;
33172 }
33173 break;
33174 }
33175 case AArch64::CNTP_XPP_B:
33176 case AArch64::CNTP_XPP_D:
33177 case AArch64::CNTP_XPP_H:
33178 case AArch64::CNTP_XPP_S:
33179 case AArch64::FIRSTP_XPP_B:
33180 case AArch64::FIRSTP_XPP_D:
33181 case AArch64::FIRSTP_XPP_H:
33182 case AArch64::FIRSTP_XPP_S:
33183 case AArch64::LASTP_XPP_B:
33184 case AArch64::LASTP_XPP_D:
33185 case AArch64::LASTP_XPP_H:
33186 case AArch64::LASTP_XPP_S: {
33187 switch (OpNum) {
33188 case 1:
33189 // op: Pg
33190 return 10;
33191 case 2:
33192 // op: Pn
33193 return 5;
33194 case 0:
33195 // op: Rd
33196 return 0;
33197 }
33198 break;
33199 }
33200 case AArch64::LD1B_D_IMM:
33201 case AArch64::LD1B_H_IMM:
33202 case AArch64::LD1B_IMM:
33203 case AArch64::LD1B_S_IMM:
33204 case AArch64::LD1D_IMM:
33205 case AArch64::LD1H_D_IMM:
33206 case AArch64::LD1H_IMM:
33207 case AArch64::LD1H_S_IMM:
33208 case AArch64::LD1SB_D_IMM:
33209 case AArch64::LD1SB_H_IMM:
33210 case AArch64::LD1SB_S_IMM:
33211 case AArch64::LD1SH_D_IMM:
33212 case AArch64::LD1SH_S_IMM:
33213 case AArch64::LD1SW_D_IMM:
33214 case AArch64::LD1W_D_IMM:
33215 case AArch64::LD1W_IMM:
33216 case AArch64::LDNF1B_D_IMM:
33217 case AArch64::LDNF1B_H_IMM:
33218 case AArch64::LDNF1B_IMM:
33219 case AArch64::LDNF1B_S_IMM:
33220 case AArch64::LDNF1D_IMM:
33221 case AArch64::LDNF1H_D_IMM:
33222 case AArch64::LDNF1H_IMM:
33223 case AArch64::LDNF1H_S_IMM:
33224 case AArch64::LDNF1SB_D_IMM:
33225 case AArch64::LDNF1SB_H_IMM:
33226 case AArch64::LDNF1SB_S_IMM:
33227 case AArch64::LDNF1SH_D_IMM:
33228 case AArch64::LDNF1SH_S_IMM:
33229 case AArch64::LDNF1SW_D_IMM:
33230 case AArch64::LDNF1W_D_IMM:
33231 case AArch64::LDNF1W_IMM:
33232 case AArch64::ST1B_D_IMM:
33233 case AArch64::ST1B_H_IMM:
33234 case AArch64::ST1B_IMM:
33235 case AArch64::ST1B_S_IMM:
33236 case AArch64::ST1D_IMM:
33237 case AArch64::ST1D_Q_IMM:
33238 case AArch64::ST1H_D_IMM:
33239 case AArch64::ST1H_IMM:
33240 case AArch64::ST1H_S_IMM:
33241 case AArch64::ST1W_D_IMM:
33242 case AArch64::ST1W_IMM:
33243 case AArch64::ST1W_Q_IMM:
33244 case AArch64::ST2B_IMM:
33245 case AArch64::ST2D_IMM:
33246 case AArch64::ST2H_IMM:
33247 case AArch64::ST2W_IMM:
33248 case AArch64::ST3B_IMM:
33249 case AArch64::ST3D_IMM:
33250 case AArch64::ST3H_IMM:
33251 case AArch64::ST3W_IMM:
33252 case AArch64::ST4B_IMM:
33253 case AArch64::ST4D_IMM:
33254 case AArch64::ST4H_IMM:
33255 case AArch64::ST4W_IMM:
33256 case AArch64::STNT1B_ZRI:
33257 case AArch64::STNT1D_ZRI:
33258 case AArch64::STNT1H_ZRI:
33259 case AArch64::STNT1W_ZRI: {
33260 switch (OpNum) {
33261 case 1:
33262 // op: Pg
33263 return 10;
33264 case 2:
33265 // op: Rn
33266 return 5;
33267 case 0:
33268 // op: Zt
33269 return 0;
33270 case 3:
33271 // op: imm4
33272 return 16;
33273 }
33274 break;
33275 }
33276 case AArch64::LD1RB_D_IMM:
33277 case AArch64::LD1RB_H_IMM:
33278 case AArch64::LD1RB_IMM:
33279 case AArch64::LD1RB_S_IMM:
33280 case AArch64::LD1RD_IMM:
33281 case AArch64::LD1RH_D_IMM:
33282 case AArch64::LD1RH_IMM:
33283 case AArch64::LD1RH_S_IMM:
33284 case AArch64::LD1RSB_D_IMM:
33285 case AArch64::LD1RSB_H_IMM:
33286 case AArch64::LD1RSB_S_IMM:
33287 case AArch64::LD1RSH_D_IMM:
33288 case AArch64::LD1RSH_S_IMM:
33289 case AArch64::LD1RSW_IMM:
33290 case AArch64::LD1RW_D_IMM:
33291 case AArch64::LD1RW_IMM: {
33292 switch (OpNum) {
33293 case 1:
33294 // op: Pg
33295 return 10;
33296 case 2:
33297 // op: Rn
33298 return 5;
33299 case 0:
33300 // op: Zt
33301 return 0;
33302 case 3:
33303 // op: imm6
33304 return 16;
33305 }
33306 break;
33307 }
33308 case AArch64::GLD1B_D:
33309 case AArch64::GLD1B_D_SXTW:
33310 case AArch64::GLD1B_D_UXTW:
33311 case AArch64::GLD1B_S_SXTW:
33312 case AArch64::GLD1B_S_UXTW:
33313 case AArch64::GLD1D:
33314 case AArch64::GLD1D_SCALED:
33315 case AArch64::GLD1D_SXTW:
33316 case AArch64::GLD1D_SXTW_SCALED:
33317 case AArch64::GLD1D_UXTW:
33318 case AArch64::GLD1D_UXTW_SCALED:
33319 case AArch64::GLD1H_D:
33320 case AArch64::GLD1H_D_SCALED:
33321 case AArch64::GLD1H_D_SXTW:
33322 case AArch64::GLD1H_D_SXTW_SCALED:
33323 case AArch64::GLD1H_D_UXTW:
33324 case AArch64::GLD1H_D_UXTW_SCALED:
33325 case AArch64::GLD1H_S_SXTW:
33326 case AArch64::GLD1H_S_SXTW_SCALED:
33327 case AArch64::GLD1H_S_UXTW:
33328 case AArch64::GLD1H_S_UXTW_SCALED:
33329 case AArch64::GLD1SB_D:
33330 case AArch64::GLD1SB_D_SXTW:
33331 case AArch64::GLD1SB_D_UXTW:
33332 case AArch64::GLD1SB_S_SXTW:
33333 case AArch64::GLD1SB_S_UXTW:
33334 case AArch64::GLD1SH_D:
33335 case AArch64::GLD1SH_D_SCALED:
33336 case AArch64::GLD1SH_D_SXTW:
33337 case AArch64::GLD1SH_D_SXTW_SCALED:
33338 case AArch64::GLD1SH_D_UXTW:
33339 case AArch64::GLD1SH_D_UXTW_SCALED:
33340 case AArch64::GLD1SH_S_SXTW:
33341 case AArch64::GLD1SH_S_SXTW_SCALED:
33342 case AArch64::GLD1SH_S_UXTW:
33343 case AArch64::GLD1SH_S_UXTW_SCALED:
33344 case AArch64::GLD1SW_D:
33345 case AArch64::GLD1SW_D_SCALED:
33346 case AArch64::GLD1SW_D_SXTW:
33347 case AArch64::GLD1SW_D_SXTW_SCALED:
33348 case AArch64::GLD1SW_D_UXTW:
33349 case AArch64::GLD1SW_D_UXTW_SCALED:
33350 case AArch64::GLD1W_D:
33351 case AArch64::GLD1W_D_SCALED:
33352 case AArch64::GLD1W_D_SXTW:
33353 case AArch64::GLD1W_D_SXTW_SCALED:
33354 case AArch64::GLD1W_D_UXTW:
33355 case AArch64::GLD1W_D_UXTW_SCALED:
33356 case AArch64::GLD1W_SXTW:
33357 case AArch64::GLD1W_SXTW_SCALED:
33358 case AArch64::GLD1W_UXTW:
33359 case AArch64::GLD1W_UXTW_SCALED:
33360 case AArch64::GLDFF1B_D:
33361 case AArch64::GLDFF1B_D_SXTW:
33362 case AArch64::GLDFF1B_D_UXTW:
33363 case AArch64::GLDFF1B_S_SXTW:
33364 case AArch64::GLDFF1B_S_UXTW:
33365 case AArch64::GLDFF1D:
33366 case AArch64::GLDFF1D_SCALED:
33367 case AArch64::GLDFF1D_SXTW:
33368 case AArch64::GLDFF1D_SXTW_SCALED:
33369 case AArch64::GLDFF1D_UXTW:
33370 case AArch64::GLDFF1D_UXTW_SCALED:
33371 case AArch64::GLDFF1H_D:
33372 case AArch64::GLDFF1H_D_SCALED:
33373 case AArch64::GLDFF1H_D_SXTW:
33374 case AArch64::GLDFF1H_D_SXTW_SCALED:
33375 case AArch64::GLDFF1H_D_UXTW:
33376 case AArch64::GLDFF1H_D_UXTW_SCALED:
33377 case AArch64::GLDFF1H_S_SXTW:
33378 case AArch64::GLDFF1H_S_SXTW_SCALED:
33379 case AArch64::GLDFF1H_S_UXTW:
33380 case AArch64::GLDFF1H_S_UXTW_SCALED:
33381 case AArch64::GLDFF1SB_D:
33382 case AArch64::GLDFF1SB_D_SXTW:
33383 case AArch64::GLDFF1SB_D_UXTW:
33384 case AArch64::GLDFF1SB_S_SXTW:
33385 case AArch64::GLDFF1SB_S_UXTW:
33386 case AArch64::GLDFF1SH_D:
33387 case AArch64::GLDFF1SH_D_SCALED:
33388 case AArch64::GLDFF1SH_D_SXTW:
33389 case AArch64::GLDFF1SH_D_SXTW_SCALED:
33390 case AArch64::GLDFF1SH_D_UXTW:
33391 case AArch64::GLDFF1SH_D_UXTW_SCALED:
33392 case AArch64::GLDFF1SH_S_SXTW:
33393 case AArch64::GLDFF1SH_S_SXTW_SCALED:
33394 case AArch64::GLDFF1SH_S_UXTW:
33395 case AArch64::GLDFF1SH_S_UXTW_SCALED:
33396 case AArch64::GLDFF1SW_D:
33397 case AArch64::GLDFF1SW_D_SCALED:
33398 case AArch64::GLDFF1SW_D_SXTW:
33399 case AArch64::GLDFF1SW_D_SXTW_SCALED:
33400 case AArch64::GLDFF1SW_D_UXTW:
33401 case AArch64::GLDFF1SW_D_UXTW_SCALED:
33402 case AArch64::GLDFF1W_D:
33403 case AArch64::GLDFF1W_D_SCALED:
33404 case AArch64::GLDFF1W_D_SXTW:
33405 case AArch64::GLDFF1W_D_SXTW_SCALED:
33406 case AArch64::GLDFF1W_D_UXTW:
33407 case AArch64::GLDFF1W_D_UXTW_SCALED:
33408 case AArch64::GLDFF1W_SXTW:
33409 case AArch64::GLDFF1W_SXTW_SCALED:
33410 case AArch64::GLDFF1W_UXTW:
33411 case AArch64::GLDFF1W_UXTW_SCALED:
33412 case AArch64::SST1B_D:
33413 case AArch64::SST1B_D_SXTW:
33414 case AArch64::SST1B_D_UXTW:
33415 case AArch64::SST1B_S_SXTW:
33416 case AArch64::SST1B_S_UXTW:
33417 case AArch64::SST1D:
33418 case AArch64::SST1D_SCALED:
33419 case AArch64::SST1D_SXTW:
33420 case AArch64::SST1D_SXTW_SCALED:
33421 case AArch64::SST1D_UXTW:
33422 case AArch64::SST1D_UXTW_SCALED:
33423 case AArch64::SST1H_D:
33424 case AArch64::SST1H_D_SCALED:
33425 case AArch64::SST1H_D_SXTW:
33426 case AArch64::SST1H_D_SXTW_SCALED:
33427 case AArch64::SST1H_D_UXTW:
33428 case AArch64::SST1H_D_UXTW_SCALED:
33429 case AArch64::SST1H_S_SXTW:
33430 case AArch64::SST1H_S_SXTW_SCALED:
33431 case AArch64::SST1H_S_UXTW:
33432 case AArch64::SST1H_S_UXTW_SCALED:
33433 case AArch64::SST1W_D:
33434 case AArch64::SST1W_D_SCALED:
33435 case AArch64::SST1W_D_SXTW:
33436 case AArch64::SST1W_D_SXTW_SCALED:
33437 case AArch64::SST1W_D_UXTW:
33438 case AArch64::SST1W_D_UXTW_SCALED:
33439 case AArch64::SST1W_SXTW:
33440 case AArch64::SST1W_SXTW_SCALED:
33441 case AArch64::SST1W_UXTW:
33442 case AArch64::SST1W_UXTW_SCALED: {
33443 switch (OpNum) {
33444 case 1:
33445 // op: Pg
33446 return 10;
33447 case 2:
33448 // op: Rn
33449 return 5;
33450 case 3:
33451 // op: Zm
33452 return 16;
33453 case 0:
33454 // op: Zt
33455 return 0;
33456 }
33457 break;
33458 }
33459 case AArch64::PRFB_D_SCALED:
33460 case AArch64::PRFB_D_SXTW_SCALED:
33461 case AArch64::PRFB_D_UXTW_SCALED:
33462 case AArch64::PRFB_S_SXTW_SCALED:
33463 case AArch64::PRFB_S_UXTW_SCALED:
33464 case AArch64::PRFD_D_SCALED:
33465 case AArch64::PRFD_D_SXTW_SCALED:
33466 case AArch64::PRFD_D_UXTW_SCALED:
33467 case AArch64::PRFD_S_SXTW_SCALED:
33468 case AArch64::PRFD_S_UXTW_SCALED:
33469 case AArch64::PRFH_D_SCALED:
33470 case AArch64::PRFH_D_SXTW_SCALED:
33471 case AArch64::PRFH_D_UXTW_SCALED:
33472 case AArch64::PRFH_S_SXTW_SCALED:
33473 case AArch64::PRFH_S_UXTW_SCALED:
33474 case AArch64::PRFW_D_SCALED:
33475 case AArch64::PRFW_D_SXTW_SCALED:
33476 case AArch64::PRFW_D_UXTW_SCALED:
33477 case AArch64::PRFW_S_SXTW_SCALED:
33478 case AArch64::PRFW_S_UXTW_SCALED: {
33479 switch (OpNum) {
33480 case 1:
33481 // op: Pg
33482 return 10;
33483 case 2:
33484 // op: Rn
33485 return 5;
33486 case 3:
33487 // op: Zm
33488 return 16;
33489 case 0:
33490 // op: prfop
33491 return 0;
33492 }
33493 break;
33494 }
33495 case AArch64::EXPAND_ZPZ_B:
33496 case AArch64::EXPAND_ZPZ_D:
33497 case AArch64::EXPAND_ZPZ_H:
33498 case AArch64::EXPAND_ZPZ_S:
33499 case AArch64::SPLICE_ZPZZ_B:
33500 case AArch64::SPLICE_ZPZZ_D:
33501 case AArch64::SPLICE_ZPZZ_H:
33502 case AArch64::SPLICE_ZPZZ_S: {
33503 switch (OpNum) {
33504 case 1:
33505 // op: Pg
33506 return 10;
33507 case 2:
33508 // op: Zn
33509 return 5;
33510 case 0:
33511 // op: Zd
33512 return 0;
33513 }
33514 break;
33515 }
33516 case AArch64::GLD1B_D_IMM:
33517 case AArch64::GLD1B_S_IMM:
33518 case AArch64::GLD1D_IMM:
33519 case AArch64::GLD1H_D_IMM:
33520 case AArch64::GLD1H_S_IMM:
33521 case AArch64::GLD1SB_D_IMM:
33522 case AArch64::GLD1SB_S_IMM:
33523 case AArch64::GLD1SH_D_IMM:
33524 case AArch64::GLD1SH_S_IMM:
33525 case AArch64::GLD1SW_D_IMM:
33526 case AArch64::GLD1W_D_IMM:
33527 case AArch64::GLD1W_IMM:
33528 case AArch64::GLDFF1B_D_IMM:
33529 case AArch64::GLDFF1B_S_IMM:
33530 case AArch64::GLDFF1D_IMM:
33531 case AArch64::GLDFF1H_D_IMM:
33532 case AArch64::GLDFF1H_S_IMM:
33533 case AArch64::GLDFF1SB_D_IMM:
33534 case AArch64::GLDFF1SB_S_IMM:
33535 case AArch64::GLDFF1SH_D_IMM:
33536 case AArch64::GLDFF1SH_S_IMM:
33537 case AArch64::GLDFF1SW_D_IMM:
33538 case AArch64::GLDFF1W_D_IMM:
33539 case AArch64::GLDFF1W_IMM: {
33540 switch (OpNum) {
33541 case 1:
33542 // op: Pg
33543 return 10;
33544 case 2:
33545 // op: Zn
33546 return 5;
33547 case 0:
33548 // op: Zt
33549 return 0;
33550 case 3:
33551 // op: imm5
33552 return 16;
33553 }
33554 break;
33555 }
33556 case AArch64::PRFB_D_PZI:
33557 case AArch64::PRFB_S_PZI:
33558 case AArch64::PRFD_D_PZI:
33559 case AArch64::PRFD_S_PZI:
33560 case AArch64::PRFH_D_PZI:
33561 case AArch64::PRFH_S_PZI:
33562 case AArch64::PRFW_D_PZI:
33563 case AArch64::PRFW_S_PZI: {
33564 switch (OpNum) {
33565 case 1:
33566 // op: Pg
33567 return 10;
33568 case 2:
33569 // op: Zn
33570 return 5;
33571 case 3:
33572 // op: imm5
33573 return 16;
33574 case 0:
33575 // op: prfop
33576 return 0;
33577 }
33578 break;
33579 }
33580 case AArch64::LD2B:
33581 case AArch64::LD2D:
33582 case AArch64::LD2H:
33583 case AArch64::LD2Q:
33584 case AArch64::LD2W:
33585 case AArch64::LD3B:
33586 case AArch64::LD3D:
33587 case AArch64::LD3H:
33588 case AArch64::LD3Q:
33589 case AArch64::LD3W:
33590 case AArch64::LD4B:
33591 case AArch64::LD4D:
33592 case AArch64::LD4H:
33593 case AArch64::LD4Q:
33594 case AArch64::LD4W:
33595 case AArch64::LDNT1B_ZRR:
33596 case AArch64::LDNT1D_ZRR:
33597 case AArch64::LDNT1H_ZRR:
33598 case AArch64::LDNT1W_ZRR:
33599 case AArch64::ST1B:
33600 case AArch64::ST1B_D:
33601 case AArch64::ST1B_H:
33602 case AArch64::ST1B_S:
33603 case AArch64::ST1D:
33604 case AArch64::ST1D_Q:
33605 case AArch64::ST1H:
33606 case AArch64::ST1H_D:
33607 case AArch64::ST1H_S:
33608 case AArch64::ST1W:
33609 case AArch64::ST1W_D:
33610 case AArch64::ST1W_Q:
33611 case AArch64::ST2B:
33612 case AArch64::ST2D:
33613 case AArch64::ST2H:
33614 case AArch64::ST2W:
33615 case AArch64::ST3B:
33616 case AArch64::ST3D:
33617 case AArch64::ST3H:
33618 case AArch64::ST3W:
33619 case AArch64::ST4B:
33620 case AArch64::ST4D:
33621 case AArch64::ST4H:
33622 case AArch64::ST4W:
33623 case AArch64::STNT1B_ZRR:
33624 case AArch64::STNT1D_ZRR:
33625 case AArch64::STNT1H_ZRR:
33626 case AArch64::STNT1W_ZRR: {
33627 switch (OpNum) {
33628 case 1:
33629 // op: Pg
33630 return 10;
33631 case 3:
33632 // op: Rm
33633 return 16;
33634 case 2:
33635 // op: Rn
33636 return 5;
33637 case 0:
33638 // op: Zt
33639 return 0;
33640 }
33641 break;
33642 }
33643 case AArch64::LDNT1B_ZZR_D:
33644 case AArch64::LDNT1B_ZZR_S:
33645 case AArch64::LDNT1D_ZZR_D:
33646 case AArch64::LDNT1H_ZZR_D:
33647 case AArch64::LDNT1H_ZZR_S:
33648 case AArch64::LDNT1SB_ZZR_D:
33649 case AArch64::LDNT1SB_ZZR_S:
33650 case AArch64::LDNT1SH_ZZR_D:
33651 case AArch64::LDNT1SH_ZZR_S:
33652 case AArch64::LDNT1SW_ZZR_D:
33653 case AArch64::LDNT1W_ZZR_D:
33654 case AArch64::LDNT1W_ZZR_S:
33655 case AArch64::STNT1B_ZZR_D:
33656 case AArch64::STNT1B_ZZR_S:
33657 case AArch64::STNT1D_ZZR_D:
33658 case AArch64::STNT1H_ZZR_D:
33659 case AArch64::STNT1H_ZZR_S:
33660 case AArch64::STNT1W_ZZR_D:
33661 case AArch64::STNT1W_ZZR_S: {
33662 switch (OpNum) {
33663 case 1:
33664 // op: Pg
33665 return 10;
33666 case 3:
33667 // op: Rm
33668 return 16;
33669 case 2:
33670 // op: Zn
33671 return 5;
33672 case 0:
33673 // op: Zt
33674 return 0;
33675 }
33676 break;
33677 }
33678 case AArch64::ADDP_ZPmZ_B:
33679 case AArch64::ADDP_ZPmZ_D:
33680 case AArch64::ADDP_ZPmZ_H:
33681 case AArch64::ADDP_ZPmZ_S:
33682 case AArch64::FADDP_ZPmZZ_D:
33683 case AArch64::FADDP_ZPmZZ_H:
33684 case AArch64::FADDP_ZPmZZ_S:
33685 case AArch64::FMAXNMP_ZPmZZ_D:
33686 case AArch64::FMAXNMP_ZPmZZ_H:
33687 case AArch64::FMAXNMP_ZPmZZ_S:
33688 case AArch64::FMAXP_ZPmZZ_D:
33689 case AArch64::FMAXP_ZPmZZ_H:
33690 case AArch64::FMAXP_ZPmZZ_S:
33691 case AArch64::FMINNMP_ZPmZZ_D:
33692 case AArch64::FMINNMP_ZPmZZ_H:
33693 case AArch64::FMINNMP_ZPmZZ_S:
33694 case AArch64::FMINP_ZPmZZ_D:
33695 case AArch64::FMINP_ZPmZZ_H:
33696 case AArch64::FMINP_ZPmZZ_S:
33697 case AArch64::SHADD_ZPmZ_B:
33698 case AArch64::SHADD_ZPmZ_D:
33699 case AArch64::SHADD_ZPmZ_H:
33700 case AArch64::SHADD_ZPmZ_S:
33701 case AArch64::SHSUBR_ZPmZ_B:
33702 case AArch64::SHSUBR_ZPmZ_D:
33703 case AArch64::SHSUBR_ZPmZ_H:
33704 case AArch64::SHSUBR_ZPmZ_S:
33705 case AArch64::SHSUB_ZPmZ_B:
33706 case AArch64::SHSUB_ZPmZ_D:
33707 case AArch64::SHSUB_ZPmZ_H:
33708 case AArch64::SHSUB_ZPmZ_S:
33709 case AArch64::SMAXP_ZPmZ_B:
33710 case AArch64::SMAXP_ZPmZ_D:
33711 case AArch64::SMAXP_ZPmZ_H:
33712 case AArch64::SMAXP_ZPmZ_S:
33713 case AArch64::SMINP_ZPmZ_B:
33714 case AArch64::SMINP_ZPmZ_D:
33715 case AArch64::SMINP_ZPmZ_H:
33716 case AArch64::SMINP_ZPmZ_S:
33717 case AArch64::SQADD_ZPmZ_B:
33718 case AArch64::SQADD_ZPmZ_D:
33719 case AArch64::SQADD_ZPmZ_H:
33720 case AArch64::SQADD_ZPmZ_S:
33721 case AArch64::SQRSHLR_ZPmZ_B:
33722 case AArch64::SQRSHLR_ZPmZ_D:
33723 case AArch64::SQRSHLR_ZPmZ_H:
33724 case AArch64::SQRSHLR_ZPmZ_S:
33725 case AArch64::SQRSHL_ZPmZ_B:
33726 case AArch64::SQRSHL_ZPmZ_D:
33727 case AArch64::SQRSHL_ZPmZ_H:
33728 case AArch64::SQRSHL_ZPmZ_S:
33729 case AArch64::SQSHLR_ZPmZ_B:
33730 case AArch64::SQSHLR_ZPmZ_D:
33731 case AArch64::SQSHLR_ZPmZ_H:
33732 case AArch64::SQSHLR_ZPmZ_S:
33733 case AArch64::SQSHL_ZPmZ_B:
33734 case AArch64::SQSHL_ZPmZ_D:
33735 case AArch64::SQSHL_ZPmZ_H:
33736 case AArch64::SQSHL_ZPmZ_S:
33737 case AArch64::SQSUBR_ZPmZ_B:
33738 case AArch64::SQSUBR_ZPmZ_D:
33739 case AArch64::SQSUBR_ZPmZ_H:
33740 case AArch64::SQSUBR_ZPmZ_S:
33741 case AArch64::SQSUB_ZPmZ_B:
33742 case AArch64::SQSUB_ZPmZ_D:
33743 case AArch64::SQSUB_ZPmZ_H:
33744 case AArch64::SQSUB_ZPmZ_S:
33745 case AArch64::SRHADD_ZPmZ_B:
33746 case AArch64::SRHADD_ZPmZ_D:
33747 case AArch64::SRHADD_ZPmZ_H:
33748 case AArch64::SRHADD_ZPmZ_S:
33749 case AArch64::SRSHLR_ZPmZ_B:
33750 case AArch64::SRSHLR_ZPmZ_D:
33751 case AArch64::SRSHLR_ZPmZ_H:
33752 case AArch64::SRSHLR_ZPmZ_S:
33753 case AArch64::SRSHL_ZPmZ_B:
33754 case AArch64::SRSHL_ZPmZ_D:
33755 case AArch64::SRSHL_ZPmZ_H:
33756 case AArch64::SRSHL_ZPmZ_S:
33757 case AArch64::SUQADD_ZPmZ_B:
33758 case AArch64::SUQADD_ZPmZ_D:
33759 case AArch64::SUQADD_ZPmZ_H:
33760 case AArch64::SUQADD_ZPmZ_S:
33761 case AArch64::UHADD_ZPmZ_B:
33762 case AArch64::UHADD_ZPmZ_D:
33763 case AArch64::UHADD_ZPmZ_H:
33764 case AArch64::UHADD_ZPmZ_S:
33765 case AArch64::UHSUBR_ZPmZ_B:
33766 case AArch64::UHSUBR_ZPmZ_D:
33767 case AArch64::UHSUBR_ZPmZ_H:
33768 case AArch64::UHSUBR_ZPmZ_S:
33769 case AArch64::UHSUB_ZPmZ_B:
33770 case AArch64::UHSUB_ZPmZ_D:
33771 case AArch64::UHSUB_ZPmZ_H:
33772 case AArch64::UHSUB_ZPmZ_S:
33773 case AArch64::UMAXP_ZPmZ_B:
33774 case AArch64::UMAXP_ZPmZ_D:
33775 case AArch64::UMAXP_ZPmZ_H:
33776 case AArch64::UMAXP_ZPmZ_S:
33777 case AArch64::UMINP_ZPmZ_B:
33778 case AArch64::UMINP_ZPmZ_D:
33779 case AArch64::UMINP_ZPmZ_H:
33780 case AArch64::UMINP_ZPmZ_S:
33781 case AArch64::UQADD_ZPmZ_B:
33782 case AArch64::UQADD_ZPmZ_D:
33783 case AArch64::UQADD_ZPmZ_H:
33784 case AArch64::UQADD_ZPmZ_S:
33785 case AArch64::UQRSHLR_ZPmZ_B:
33786 case AArch64::UQRSHLR_ZPmZ_D:
33787 case AArch64::UQRSHLR_ZPmZ_H:
33788 case AArch64::UQRSHLR_ZPmZ_S:
33789 case AArch64::UQRSHL_ZPmZ_B:
33790 case AArch64::UQRSHL_ZPmZ_D:
33791 case AArch64::UQRSHL_ZPmZ_H:
33792 case AArch64::UQRSHL_ZPmZ_S:
33793 case AArch64::UQSHLR_ZPmZ_B:
33794 case AArch64::UQSHLR_ZPmZ_D:
33795 case AArch64::UQSHLR_ZPmZ_H:
33796 case AArch64::UQSHLR_ZPmZ_S:
33797 case AArch64::UQSHL_ZPmZ_B:
33798 case AArch64::UQSHL_ZPmZ_D:
33799 case AArch64::UQSHL_ZPmZ_H:
33800 case AArch64::UQSHL_ZPmZ_S:
33801 case AArch64::UQSUBR_ZPmZ_B:
33802 case AArch64::UQSUBR_ZPmZ_D:
33803 case AArch64::UQSUBR_ZPmZ_H:
33804 case AArch64::UQSUBR_ZPmZ_S:
33805 case AArch64::UQSUB_ZPmZ_B:
33806 case AArch64::UQSUB_ZPmZ_D:
33807 case AArch64::UQSUB_ZPmZ_H:
33808 case AArch64::UQSUB_ZPmZ_S:
33809 case AArch64::URHADD_ZPmZ_B:
33810 case AArch64::URHADD_ZPmZ_D:
33811 case AArch64::URHADD_ZPmZ_H:
33812 case AArch64::URHADD_ZPmZ_S:
33813 case AArch64::URSHLR_ZPmZ_B:
33814 case AArch64::URSHLR_ZPmZ_D:
33815 case AArch64::URSHLR_ZPmZ_H:
33816 case AArch64::URSHLR_ZPmZ_S:
33817 case AArch64::URSHL_ZPmZ_B:
33818 case AArch64::URSHL_ZPmZ_D:
33819 case AArch64::URSHL_ZPmZ_H:
33820 case AArch64::URSHL_ZPmZ_S:
33821 case AArch64::USQADD_ZPmZ_B:
33822 case AArch64::USQADD_ZPmZ_D:
33823 case AArch64::USQADD_ZPmZ_H:
33824 case AArch64::USQADD_ZPmZ_S: {
33825 switch (OpNum) {
33826 case 1:
33827 // op: Pg
33828 return 10;
33829 case 3:
33830 // op: Zm
33831 return 5;
33832 case 0:
33833 // op: Zdn
33834 return 0;
33835 }
33836 break;
33837 }
33838 case AArch64::SADALP_ZPmZ_D:
33839 case AArch64::SADALP_ZPmZ_H:
33840 case AArch64::SADALP_ZPmZ_S:
33841 case AArch64::UADALP_ZPmZ_D:
33842 case AArch64::UADALP_ZPmZ_H:
33843 case AArch64::UADALP_ZPmZ_S: {
33844 switch (OpNum) {
33845 case 1:
33846 // op: Pg
33847 return 10;
33848 case 3:
33849 // op: Zn
33850 return 5;
33851 case 0:
33852 // op: Zda
33853 return 0;
33854 }
33855 break;
33856 }
33857 case AArch64::SST1B_D_IMM:
33858 case AArch64::SST1B_S_IMM:
33859 case AArch64::SST1D_IMM:
33860 case AArch64::SST1H_D_IMM:
33861 case AArch64::SST1H_S_IMM:
33862 case AArch64::SST1W_D_IMM:
33863 case AArch64::SST1W_IMM: {
33864 switch (OpNum) {
33865 case 1:
33866 // op: Pg
33867 return 10;
33868 case 3:
33869 // op: imm5
33870 return 16;
33871 case 2:
33872 // op: Zn
33873 return 5;
33874 case 0:
33875 // op: Zt
33876 return 0;
33877 }
33878 break;
33879 }
33880 case AArch64::FMAD_ZPmZZ_D:
33881 case AArch64::FMAD_ZPmZZ_H:
33882 case AArch64::FMAD_ZPmZZ_S:
33883 case AArch64::FMSB_ZPmZZ_D:
33884 case AArch64::FMSB_ZPmZZ_H:
33885 case AArch64::FMSB_ZPmZZ_S:
33886 case AArch64::FNMAD_ZPmZZ_D:
33887 case AArch64::FNMAD_ZPmZZ_H:
33888 case AArch64::FNMAD_ZPmZZ_S:
33889 case AArch64::FNMSB_ZPmZZ_D:
33890 case AArch64::FNMSB_ZPmZZ_H:
33891 case AArch64::FNMSB_ZPmZZ_S: {
33892 switch (OpNum) {
33893 case 1:
33894 // op: Pg
33895 return 10;
33896 case 4:
33897 // op: Za
33898 return 16;
33899 case 0:
33900 // op: Zdn
33901 return 0;
33902 case 3:
33903 // op: Zm
33904 return 5;
33905 }
33906 break;
33907 }
33908 case AArch64::BF16DOTlanev4bf16:
33909 case AArch64::BF16DOTlanev8bf16:
33910 case AArch64::BFMLALBIdx:
33911 case AArch64::BFMLALTIdx:
33912 case AArch64::FDOTlanev2f32:
33913 case AArch64::FDOTlanev4f16:
33914 case AArch64::FDOTlanev4f32:
33915 case AArch64::FDOTlanev8f16:
33916 case AArch64::FMLAL2lanev4f16:
33917 case AArch64::FMLAL2lanev8f16:
33918 case AArch64::FMLALBlanev8f16:
33919 case AArch64::FMLALLBBlanev4f32:
33920 case AArch64::FMLALLBTlanev4f32:
33921 case AArch64::FMLALLTBlanev4f32:
33922 case AArch64::FMLALLTTlanev4f32:
33923 case AArch64::FMLALTlanev8f16:
33924 case AArch64::FMLALlanev4f16:
33925 case AArch64::FMLALlanev8f16:
33926 case AArch64::FMLAv1i16_indexed:
33927 case AArch64::FMLAv1i32_indexed:
33928 case AArch64::FMLAv1i64_indexed:
33929 case AArch64::FMLAv2i32_indexed:
33930 case AArch64::FMLAv2i64_indexed:
33931 case AArch64::FMLAv4i16_indexed:
33932 case AArch64::FMLAv4i32_indexed:
33933 case AArch64::FMLAv8i16_indexed:
33934 case AArch64::FMLSL2lanev4f16:
33935 case AArch64::FMLSL2lanev8f16:
33936 case AArch64::FMLSLlanev4f16:
33937 case AArch64::FMLSLlanev8f16:
33938 case AArch64::FMLSv1i16_indexed:
33939 case AArch64::FMLSv1i32_indexed:
33940 case AArch64::FMLSv1i64_indexed:
33941 case AArch64::FMLSv2i32_indexed:
33942 case AArch64::FMLSv2i64_indexed:
33943 case AArch64::FMLSv4i16_indexed:
33944 case AArch64::FMLSv4i32_indexed:
33945 case AArch64::FMLSv8i16_indexed:
33946 case AArch64::MLAv2i32_indexed:
33947 case AArch64::MLAv4i16_indexed:
33948 case AArch64::MLAv4i32_indexed:
33949 case AArch64::MLAv8i16_indexed:
33950 case AArch64::MLSv2i32_indexed:
33951 case AArch64::MLSv4i16_indexed:
33952 case AArch64::MLSv4i32_indexed:
33953 case AArch64::MLSv8i16_indexed:
33954 case AArch64::SDOTlanev8i8:
33955 case AArch64::SDOTlanev16i8:
33956 case AArch64::SMLALv2i32_indexed:
33957 case AArch64::SMLALv4i16_indexed:
33958 case AArch64::SMLALv4i32_indexed:
33959 case AArch64::SMLALv8i16_indexed:
33960 case AArch64::SMLSLv2i32_indexed:
33961 case AArch64::SMLSLv4i16_indexed:
33962 case AArch64::SMLSLv4i32_indexed:
33963 case AArch64::SMLSLv8i16_indexed:
33964 case AArch64::SQDMLALv1i32_indexed:
33965 case AArch64::SQDMLALv1i64_indexed:
33966 case AArch64::SQDMLALv2i32_indexed:
33967 case AArch64::SQDMLALv4i16_indexed:
33968 case AArch64::SQDMLALv4i32_indexed:
33969 case AArch64::SQDMLALv8i16_indexed:
33970 case AArch64::SQDMLSLv1i32_indexed:
33971 case AArch64::SQDMLSLv1i64_indexed:
33972 case AArch64::SQDMLSLv2i32_indexed:
33973 case AArch64::SQDMLSLv4i16_indexed:
33974 case AArch64::SQDMLSLv4i32_indexed:
33975 case AArch64::SQDMLSLv8i16_indexed:
33976 case AArch64::SQRDMLAHv1i16_indexed:
33977 case AArch64::SQRDMLAHv1i32_indexed:
33978 case AArch64::SQRDMLAHv2i32_indexed:
33979 case AArch64::SQRDMLAHv4i16_indexed:
33980 case AArch64::SQRDMLAHv4i32_indexed:
33981 case AArch64::SQRDMLAHv8i16_indexed:
33982 case AArch64::SQRDMLSHv1i16_indexed:
33983 case AArch64::SQRDMLSHv1i32_indexed:
33984 case AArch64::SQRDMLSHv2i32_indexed:
33985 case AArch64::SQRDMLSHv4i16_indexed:
33986 case AArch64::SQRDMLSHv4i32_indexed:
33987 case AArch64::SQRDMLSHv8i16_indexed:
33988 case AArch64::SUDOTlanev8i8:
33989 case AArch64::SUDOTlanev16i8:
33990 case AArch64::UDOTlanev8i8:
33991 case AArch64::UDOTlanev16i8:
33992 case AArch64::UMLALv2i32_indexed:
33993 case AArch64::UMLALv4i16_indexed:
33994 case AArch64::UMLALv4i32_indexed:
33995 case AArch64::UMLALv8i16_indexed:
33996 case AArch64::UMLSLv2i32_indexed:
33997 case AArch64::UMLSLv4i16_indexed:
33998 case AArch64::UMLSLv4i32_indexed:
33999 case AArch64::UMLSLv8i16_indexed:
34000 case AArch64::USDOTlanev8i8:
34001 case AArch64::USDOTlanev16i8: {
34002 switch (OpNum) {
34003 case 1:
34004 // op: Rd
34005 return 0;
34006 case 2:
34007 // op: Rn
34008 return 5;
34009 case 3:
34010 // op: Rm
34011 return 16;
34012 case 4:
34013 // op: idx
34014 return 11;
34015 }
34016 break;
34017 }
34018 case AArch64::FCMLAv2f32:
34019 case AArch64::FCMLAv2f64:
34020 case AArch64::FCMLAv4f16:
34021 case AArch64::FCMLAv4f32:
34022 case AArch64::FCMLAv8f16: {
34023 switch (OpNum) {
34024 case 1:
34025 // op: Rd
34026 return 0;
34027 case 2:
34028 // op: Rn
34029 return 5;
34030 case 3:
34031 // op: Rm
34032 return 16;
34033 case 4:
34034 // op: rot
34035 return 11;
34036 }
34037 break;
34038 }
34039 case AArch64::FCMLAv4f32_indexed:
34040 case AArch64::FCMLAv8f16_indexed: {
34041 switch (OpNum) {
34042 case 1:
34043 // op: Rd
34044 return 0;
34045 case 2:
34046 // op: Rn
34047 return 5;
34048 case 3:
34049 // op: Rm
34050 return 16;
34051 case 5:
34052 // op: rot
34053 return 13;
34054 case 4:
34055 // op: idx
34056 return 11;
34057 }
34058 break;
34059 }
34060 case AArch64::FCMLAv4f16_indexed: {
34061 switch (OpNum) {
34062 case 1:
34063 // op: Rd
34064 return 0;
34065 case 2:
34066 // op: Rn
34067 return 5;
34068 case 3:
34069 // op: Rm
34070 return 16;
34071 case 5:
34072 // op: rot
34073 return 13;
34074 case 4:
34075 // op: idx
34076 return 21;
34077 }
34078 break;
34079 }
34080 case AArch64::ADDHNv2i64_v4i32:
34081 case AArch64::ADDHNv4i32_v8i16:
34082 case AArch64::ADDHNv8i16_v16i8:
34083 case AArch64::BFDOTv4bf16:
34084 case AArch64::BFDOTv8bf16:
34085 case AArch64::BFMLALB:
34086 case AArch64::BFMLALT:
34087 case AArch64::BFMMLA:
34088 case AArch64::BIFv8i8:
34089 case AArch64::BIFv16i8:
34090 case AArch64::BITv8i8:
34091 case AArch64::BITv16i8:
34092 case AArch64::BSLv8i8:
34093 case AArch64::BSLv16i8:
34094 case AArch64::FCVTN_F322v16f8:
34095 case AArch64::FDOTv2f32:
34096 case AArch64::FDOTv4f16:
34097 case AArch64::FDOTv4f32:
34098 case AArch64::FDOTv8f16:
34099 case AArch64::FMLAL2v4f16:
34100 case AArch64::FMLAL2v8f16:
34101 case AArch64::FMLALBv8f16:
34102 case AArch64::FMLALLBBv4f32:
34103 case AArch64::FMLALLBTv4f32:
34104 case AArch64::FMLALLTBv4f32:
34105 case AArch64::FMLALLTTv4f32:
34106 case AArch64::FMLALTv8f16:
34107 case AArch64::FMLALv4f16:
34108 case AArch64::FMLALv8f16:
34109 case AArch64::FMLAv2f32:
34110 case AArch64::FMLAv2f64:
34111 case AArch64::FMLAv4f16:
34112 case AArch64::FMLAv4f32:
34113 case AArch64::FMLAv8f16:
34114 case AArch64::FMLSL2v4f16:
34115 case AArch64::FMLSL2v8f16:
34116 case AArch64::FMLSLv4f16:
34117 case AArch64::FMLSLv8f16:
34118 case AArch64::FMLSv2f32:
34119 case AArch64::FMLSv2f64:
34120 case AArch64::FMLSv4f16:
34121 case AArch64::FMLSv4f32:
34122 case AArch64::FMLSv8f16:
34123 case AArch64::FMMLAv4f32:
34124 case AArch64::FMMLAv8f16:
34125 case AArch64::MLAv2i32:
34126 case AArch64::MLAv4i16:
34127 case AArch64::MLAv4i32:
34128 case AArch64::MLAv8i8:
34129 case AArch64::MLAv8i16:
34130 case AArch64::MLAv16i8:
34131 case AArch64::MLSv2i32:
34132 case AArch64::MLSv4i16:
34133 case AArch64::MLSv4i32:
34134 case AArch64::MLSv8i8:
34135 case AArch64::MLSv8i16:
34136 case AArch64::MLSv16i8:
34137 case AArch64::RADDHNv2i64_v4i32:
34138 case AArch64::RADDHNv4i32_v8i16:
34139 case AArch64::RADDHNv8i16_v16i8:
34140 case AArch64::RSUBHNv2i64_v4i32:
34141 case AArch64::RSUBHNv4i32_v8i16:
34142 case AArch64::RSUBHNv8i16_v16i8:
34143 case AArch64::SABALv2i32_v2i64:
34144 case AArch64::SABALv4i16_v4i32:
34145 case AArch64::SABALv4i32_v2i64:
34146 case AArch64::SABALv8i8_v8i16:
34147 case AArch64::SABALv8i16_v4i32:
34148 case AArch64::SABALv16i8_v8i16:
34149 case AArch64::SABAv2i32:
34150 case AArch64::SABAv4i16:
34151 case AArch64::SABAv4i32:
34152 case AArch64::SABAv8i8:
34153 case AArch64::SABAv8i16:
34154 case AArch64::SABAv16i8:
34155 case AArch64::SDOTv8i8:
34156 case AArch64::SDOTv16i8:
34157 case AArch64::SHA1Crrr:
34158 case AArch64::SHA1Mrrr:
34159 case AArch64::SHA1Prrr:
34160 case AArch64::SHA1SU0rrr:
34161 case AArch64::SHA256H2rrr:
34162 case AArch64::SHA256Hrrr:
34163 case AArch64::SHA256SU1rrr:
34164 case AArch64::SMLALv2i32_v2i64:
34165 case AArch64::SMLALv4i16_v4i32:
34166 case AArch64::SMLALv4i32_v2i64:
34167 case AArch64::SMLALv8i8_v8i16:
34168 case AArch64::SMLALv8i16_v4i32:
34169 case AArch64::SMLALv16i8_v8i16:
34170 case AArch64::SMLSLv2i32_v2i64:
34171 case AArch64::SMLSLv4i16_v4i32:
34172 case AArch64::SMLSLv4i32_v2i64:
34173 case AArch64::SMLSLv8i8_v8i16:
34174 case AArch64::SMLSLv8i16_v4i32:
34175 case AArch64::SMLSLv16i8_v8i16:
34176 case AArch64::SMMLA:
34177 case AArch64::SQDMLALi16:
34178 case AArch64::SQDMLALi32:
34179 case AArch64::SQDMLALv2i32_v2i64:
34180 case AArch64::SQDMLALv4i16_v4i32:
34181 case AArch64::SQDMLALv4i32_v2i64:
34182 case AArch64::SQDMLALv8i16_v4i32:
34183 case AArch64::SQDMLSLi16:
34184 case AArch64::SQDMLSLi32:
34185 case AArch64::SQDMLSLv2i32_v2i64:
34186 case AArch64::SQDMLSLv4i16_v4i32:
34187 case AArch64::SQDMLSLv4i32_v2i64:
34188 case AArch64::SQDMLSLv8i16_v4i32:
34189 case AArch64::SQRDMLAHv1i16:
34190 case AArch64::SQRDMLAHv1i32:
34191 case AArch64::SQRDMLAHv2i32:
34192 case AArch64::SQRDMLAHv4i16:
34193 case AArch64::SQRDMLAHv4i32:
34194 case AArch64::SQRDMLAHv8i16:
34195 case AArch64::SQRDMLSHv1i16:
34196 case AArch64::SQRDMLSHv1i32:
34197 case AArch64::SQRDMLSHv2i32:
34198 case AArch64::SQRDMLSHv4i16:
34199 case AArch64::SQRDMLSHv4i32:
34200 case AArch64::SQRDMLSHv8i16:
34201 case AArch64::SUBHNv2i64_v4i32:
34202 case AArch64::SUBHNv4i32_v8i16:
34203 case AArch64::SUBHNv8i16_v16i8:
34204 case AArch64::UABALv2i32_v2i64:
34205 case AArch64::UABALv4i16_v4i32:
34206 case AArch64::UABALv4i32_v2i64:
34207 case AArch64::UABALv8i8_v8i16:
34208 case AArch64::UABALv8i16_v4i32:
34209 case AArch64::UABALv16i8_v8i16:
34210 case AArch64::UABAv2i32:
34211 case AArch64::UABAv4i16:
34212 case AArch64::UABAv4i32:
34213 case AArch64::UABAv8i8:
34214 case AArch64::UABAv8i16:
34215 case AArch64::UABAv16i8:
34216 case AArch64::UDOTv8i8:
34217 case AArch64::UDOTv16i8:
34218 case AArch64::UMLALv2i32_v2i64:
34219 case AArch64::UMLALv4i16_v4i32:
34220 case AArch64::UMLALv4i32_v2i64:
34221 case AArch64::UMLALv8i8_v8i16:
34222 case AArch64::UMLALv8i16_v4i32:
34223 case AArch64::UMLALv16i8_v8i16:
34224 case AArch64::UMLSLv2i32_v2i64:
34225 case AArch64::UMLSLv4i16_v4i32:
34226 case AArch64::UMLSLv4i32_v2i64:
34227 case AArch64::UMLSLv8i8_v8i16:
34228 case AArch64::UMLSLv8i16_v4i32:
34229 case AArch64::UMLSLv16i8_v8i16:
34230 case AArch64::UMMLA:
34231 case AArch64::USDOTv8i8:
34232 case AArch64::USDOTv16i8:
34233 case AArch64::USMMLA: {
34234 switch (OpNum) {
34235 case 1:
34236 // op: Rd
34237 return 0;
34238 case 2:
34239 // op: Rn
34240 return 5;
34241 case 3:
34242 // op: Rm
34243 return 16;
34244 }
34245 break;
34246 }
34247 case AArch64::RSHRNv4i32_shift:
34248 case AArch64::RSHRNv8i16_shift:
34249 case AArch64::RSHRNv16i8_shift:
34250 case AArch64::SHRNv4i32_shift:
34251 case AArch64::SHRNv8i16_shift:
34252 case AArch64::SHRNv16i8_shift:
34253 case AArch64::SLId:
34254 case AArch64::SLIv2i32_shift:
34255 case AArch64::SLIv2i64_shift:
34256 case AArch64::SLIv4i16_shift:
34257 case AArch64::SLIv4i32_shift:
34258 case AArch64::SLIv8i8_shift:
34259 case AArch64::SLIv8i16_shift:
34260 case AArch64::SLIv16i8_shift:
34261 case AArch64::SQRSHRNv4i32_shift:
34262 case AArch64::SQRSHRNv8i16_shift:
34263 case AArch64::SQRSHRNv16i8_shift:
34264 case AArch64::SQRSHRUNv4i32_shift:
34265 case AArch64::SQRSHRUNv8i16_shift:
34266 case AArch64::SQRSHRUNv16i8_shift:
34267 case AArch64::SQSHRNv4i32_shift:
34268 case AArch64::SQSHRNv8i16_shift:
34269 case AArch64::SQSHRNv16i8_shift:
34270 case AArch64::SQSHRUNv4i32_shift:
34271 case AArch64::SQSHRUNv8i16_shift:
34272 case AArch64::SQSHRUNv16i8_shift:
34273 case AArch64::SRId:
34274 case AArch64::SRIv2i32_shift:
34275 case AArch64::SRIv2i64_shift:
34276 case AArch64::SRIv4i16_shift:
34277 case AArch64::SRIv4i32_shift:
34278 case AArch64::SRIv8i8_shift:
34279 case AArch64::SRIv8i16_shift:
34280 case AArch64::SRIv16i8_shift:
34281 case AArch64::SRSRAd:
34282 case AArch64::SRSRAv2i32_shift:
34283 case AArch64::SRSRAv2i64_shift:
34284 case AArch64::SRSRAv4i16_shift:
34285 case AArch64::SRSRAv4i32_shift:
34286 case AArch64::SRSRAv8i8_shift:
34287 case AArch64::SRSRAv8i16_shift:
34288 case AArch64::SRSRAv16i8_shift:
34289 case AArch64::SSRAd:
34290 case AArch64::SSRAv2i32_shift:
34291 case AArch64::SSRAv2i64_shift:
34292 case AArch64::SSRAv4i16_shift:
34293 case AArch64::SSRAv4i32_shift:
34294 case AArch64::SSRAv8i8_shift:
34295 case AArch64::SSRAv8i16_shift:
34296 case AArch64::SSRAv16i8_shift:
34297 case AArch64::UQRSHRNv4i32_shift:
34298 case AArch64::UQRSHRNv8i16_shift:
34299 case AArch64::UQRSHRNv16i8_shift:
34300 case AArch64::UQSHRNv4i32_shift:
34301 case AArch64::UQSHRNv8i16_shift:
34302 case AArch64::UQSHRNv16i8_shift:
34303 case AArch64::URSRAd:
34304 case AArch64::URSRAv2i32_shift:
34305 case AArch64::URSRAv2i64_shift:
34306 case AArch64::URSRAv4i16_shift:
34307 case AArch64::URSRAv4i32_shift:
34308 case AArch64::URSRAv8i8_shift:
34309 case AArch64::URSRAv8i16_shift:
34310 case AArch64::URSRAv16i8_shift:
34311 case AArch64::USRAd:
34312 case AArch64::USRAv2i32_shift:
34313 case AArch64::USRAv2i64_shift:
34314 case AArch64::USRAv4i16_shift:
34315 case AArch64::USRAv4i32_shift:
34316 case AArch64::USRAv8i8_shift:
34317 case AArch64::USRAv8i16_shift:
34318 case AArch64::USRAv16i8_shift: {
34319 switch (OpNum) {
34320 case 1:
34321 // op: Rd
34322 return 0;
34323 case 2:
34324 // op: Rn
34325 return 5;
34326 case 3:
34327 // op: imm
34328 return 16;
34329 }
34330 break;
34331 }
34332 case AArch64::AESDrr:
34333 case AArch64::AESErr:
34334 case AArch64::AUTDA:
34335 case AArch64::AUTDB:
34336 case AArch64::AUTIA:
34337 case AArch64::AUTIB:
34338 case AArch64::BFCVTN2:
34339 case AArch64::FCVTNv4i32:
34340 case AArch64::FCVTNv8i16:
34341 case AArch64::FCVTXNv4f32:
34342 case AArch64::PACDA:
34343 case AArch64::PACDB:
34344 case AArch64::PACIA:
34345 case AArch64::PACIB:
34346 case AArch64::SADALPv2i32_v1i64:
34347 case AArch64::SADALPv4i16_v2i32:
34348 case AArch64::SADALPv4i32_v2i64:
34349 case AArch64::SADALPv8i8_v4i16:
34350 case AArch64::SADALPv8i16_v4i32:
34351 case AArch64::SADALPv16i8_v8i16:
34352 case AArch64::SHA1SU1rr:
34353 case AArch64::SHA256SU0rr:
34354 case AArch64::SQXTNv4i32:
34355 case AArch64::SQXTNv8i16:
34356 case AArch64::SQXTNv16i8:
34357 case AArch64::SQXTUNv4i32:
34358 case AArch64::SQXTUNv8i16:
34359 case AArch64::SQXTUNv16i8:
34360 case AArch64::SUQADDv1i8:
34361 case AArch64::SUQADDv1i16:
34362 case AArch64::SUQADDv1i32:
34363 case AArch64::SUQADDv1i64:
34364 case AArch64::SUQADDv2i32:
34365 case AArch64::SUQADDv2i64:
34366 case AArch64::SUQADDv4i16:
34367 case AArch64::SUQADDv4i32:
34368 case AArch64::SUQADDv8i8:
34369 case AArch64::SUQADDv8i16:
34370 case AArch64::SUQADDv16i8:
34371 case AArch64::UADALPv2i32_v1i64:
34372 case AArch64::UADALPv4i16_v2i32:
34373 case AArch64::UADALPv4i32_v2i64:
34374 case AArch64::UADALPv8i8_v4i16:
34375 case AArch64::UADALPv8i16_v4i32:
34376 case AArch64::UADALPv16i8_v8i16:
34377 case AArch64::UQXTNv4i32:
34378 case AArch64::UQXTNv8i16:
34379 case AArch64::UQXTNv16i8:
34380 case AArch64::USQADDv1i8:
34381 case AArch64::USQADDv1i16:
34382 case AArch64::USQADDv1i32:
34383 case AArch64::USQADDv1i64:
34384 case AArch64::USQADDv2i32:
34385 case AArch64::USQADDv2i64:
34386 case AArch64::USQADDv4i16:
34387 case AArch64::USQADDv4i32:
34388 case AArch64::USQADDv8i8:
34389 case AArch64::USQADDv8i16:
34390 case AArch64::USQADDv16i8:
34391 case AArch64::XTNv4i32:
34392 case AArch64::XTNv8i16:
34393 case AArch64::XTNv16i8: {
34394 switch (OpNum) {
34395 case 1:
34396 // op: Rd
34397 return 0;
34398 case 2:
34399 // op: Rn
34400 return 5;
34401 }
34402 break;
34403 }
34404 case AArch64::BICv2i32:
34405 case AArch64::BICv4i16:
34406 case AArch64::BICv4i32:
34407 case AArch64::BICv8i16:
34408 case AArch64::ORRv2i32:
34409 case AArch64::ORRv4i16:
34410 case AArch64::ORRv4i32:
34411 case AArch64::ORRv8i16: {
34412 switch (OpNum) {
34413 case 1:
34414 // op: Rd
34415 return 0;
34416 case 2:
34417 // op: imm8
34418 return 5;
34419 case 3:
34420 // op: shift
34421 return 13;
34422 }
34423 break;
34424 }
34425 case AArch64::INSvi8lane: {
34426 switch (OpNum) {
34427 case 1:
34428 // op: Rd
34429 return 0;
34430 case 3:
34431 // op: Rn
34432 return 5;
34433 case 2:
34434 // op: idx
34435 return 17;
34436 case 4:
34437 // op: idx2
34438 return 11;
34439 }
34440 break;
34441 }
34442 case AArch64::INSvi8gpr: {
34443 switch (OpNum) {
34444 case 1:
34445 // op: Rd
34446 return 0;
34447 case 3:
34448 // op: Rn
34449 return 5;
34450 case 2:
34451 // op: idx
34452 return 17;
34453 }
34454 break;
34455 }
34456 case AArch64::INSvi16lane: {
34457 switch (OpNum) {
34458 case 1:
34459 // op: Rd
34460 return 0;
34461 case 3:
34462 // op: Rn
34463 return 5;
34464 case 2:
34465 // op: idx
34466 return 18;
34467 case 4:
34468 // op: idx2
34469 return 12;
34470 }
34471 break;
34472 }
34473 case AArch64::INSvi16gpr: {
34474 switch (OpNum) {
34475 case 1:
34476 // op: Rd
34477 return 0;
34478 case 3:
34479 // op: Rn
34480 return 5;
34481 case 2:
34482 // op: idx
34483 return 18;
34484 }
34485 break;
34486 }
34487 case AArch64::INSvi32lane: {
34488 switch (OpNum) {
34489 case 1:
34490 // op: Rd
34491 return 0;
34492 case 3:
34493 // op: Rn
34494 return 5;
34495 case 2:
34496 // op: idx
34497 return 19;
34498 case 4:
34499 // op: idx2
34500 return 13;
34501 }
34502 break;
34503 }
34504 case AArch64::INSvi32gpr: {
34505 switch (OpNum) {
34506 case 1:
34507 // op: Rd
34508 return 0;
34509 case 3:
34510 // op: Rn
34511 return 5;
34512 case 2:
34513 // op: idx
34514 return 19;
34515 }
34516 break;
34517 }
34518 case AArch64::INSvi64lane: {
34519 switch (OpNum) {
34520 case 1:
34521 // op: Rd
34522 return 0;
34523 case 3:
34524 // op: Rn
34525 return 5;
34526 case 2:
34527 // op: idx
34528 return 20;
34529 case 4:
34530 // op: idx2
34531 return 14;
34532 }
34533 break;
34534 }
34535 case AArch64::INSvi64gpr: {
34536 switch (OpNum) {
34537 case 1:
34538 // op: Rd
34539 return 0;
34540 case 3:
34541 // op: Rn
34542 return 5;
34543 case 2:
34544 // op: idx
34545 return 20;
34546 }
34547 break;
34548 }
34549 case AArch64::AUTDZA:
34550 case AArch64::AUTDZB:
34551 case AArch64::AUTIZA:
34552 case AArch64::AUTIZB:
34553 case AArch64::PACDZA:
34554 case AArch64::PACDZB:
34555 case AArch64::PACIZA:
34556 case AArch64::PACIZB: {
34557 switch (OpNum) {
34558 case 1:
34559 // op: Rd
34560 return 0;
34561 }
34562 break;
34563 }
34564 case AArch64::CTERMEQ_WW:
34565 case AArch64::CTERMEQ_XX:
34566 case AArch64::CTERMNE_WW:
34567 case AArch64::CTERMNE_XX:
34568 case AArch64::FCMPDrr:
34569 case AArch64::FCMPEDrr:
34570 case AArch64::FCMPEHrr:
34571 case AArch64::FCMPESrr:
34572 case AArch64::FCMPHrr:
34573 case AArch64::FCMPSrr: {
34574 switch (OpNum) {
34575 case 1:
34576 // op: Rm
34577 return 16;
34578 case 0:
34579 // op: Rn
34580 return 5;
34581 }
34582 break;
34583 }
34584 case AArch64::CBBEQWrr:
34585 case AArch64::CBBGEWrr:
34586 case AArch64::CBBGTWrr:
34587 case AArch64::CBBHIWrr:
34588 case AArch64::CBBHSWrr:
34589 case AArch64::CBBNEWrr:
34590 case AArch64::CBEQWrr:
34591 case AArch64::CBEQXrr:
34592 case AArch64::CBGEWrr:
34593 case AArch64::CBGEXrr:
34594 case AArch64::CBGTWrr:
34595 case AArch64::CBGTXrr:
34596 case AArch64::CBHEQWrr:
34597 case AArch64::CBHGEWrr:
34598 case AArch64::CBHGTWrr:
34599 case AArch64::CBHHIWrr:
34600 case AArch64::CBHHSWrr:
34601 case AArch64::CBHIWrr:
34602 case AArch64::CBHIXrr:
34603 case AArch64::CBHNEWrr:
34604 case AArch64::CBHSWrr:
34605 case AArch64::CBHSXrr:
34606 case AArch64::CBNEWrr:
34607 case AArch64::CBNEXrr: {
34608 switch (OpNum) {
34609 case 1:
34610 // op: Rm
34611 return 16;
34612 case 0:
34613 // op: Rt
34614 return 0;
34615 case 2:
34616 // op: target
34617 return 5;
34618 }
34619 break;
34620 }
34621 case AArch64::ST2Gi:
34622 case AArch64::STGi:
34623 case AArch64::STZ2Gi:
34624 case AArch64::STZGi: {
34625 switch (OpNum) {
34626 case 1:
34627 // op: Rn
34628 return 5;
34629 case 0:
34630 // op: Rt
34631 return 0;
34632 case 2:
34633 // op: offset
34634 return 12;
34635 }
34636 break;
34637 }
34638 case AArch64::LDAPRB:
34639 case AArch64::LDAPRH:
34640 case AArch64::LDAPRW:
34641 case AArch64::LDAPRX:
34642 case AArch64::LDGM:
34643 case AArch64::STGM:
34644 case AArch64::STZGM: {
34645 switch (OpNum) {
34646 case 1:
34647 // op: Rn
34648 return 5;
34649 case 0:
34650 // op: Rt
34651 return 0;
34652 }
34653 break;
34654 }
34655 case AArch64::INDEX_RI_B:
34656 case AArch64::INDEX_RI_D:
34657 case AArch64::INDEX_RI_H:
34658 case AArch64::INDEX_RI_S: {
34659 switch (OpNum) {
34660 case 1:
34661 // op: Rn
34662 return 5;
34663 case 0:
34664 // op: Zd
34665 return 0;
34666 case 2:
34667 // op: imm5
34668 return 16;
34669 }
34670 break;
34671 }
34672 case AArch64::DUP_ZR_B:
34673 case AArch64::DUP_ZR_D:
34674 case AArch64::DUP_ZR_H:
34675 case AArch64::DUP_ZR_S: {
34676 switch (OpNum) {
34677 case 1:
34678 // op: Rn
34679 return 5;
34680 case 0:
34681 // op: Zd
34682 return 0;
34683 }
34684 break;
34685 }
34686 case AArch64::LDR_ZXI:
34687 case AArch64::STR_ZXI: {
34688 switch (OpNum) {
34689 case 1:
34690 // op: Rn
34691 return 5;
34692 case 0:
34693 // op: Zt
34694 return 0;
34695 case 2:
34696 // op: imm9
34697 return 10;
34698 }
34699 break;
34700 }
34701 case AArch64::LDR_TX:
34702 case AArch64::STR_TX: {
34703 switch (OpNum) {
34704 case 1:
34705 // op: Rn
34706 return 5;
34707 }
34708 break;
34709 }
34710 case AArch64::LDADDAB:
34711 case AArch64::LDADDAH:
34712 case AArch64::LDADDALB:
34713 case AArch64::LDADDALH:
34714 case AArch64::LDADDALW:
34715 case AArch64::LDADDALX:
34716 case AArch64::LDADDAW:
34717 case AArch64::LDADDAX:
34718 case AArch64::LDADDB:
34719 case AArch64::LDADDH:
34720 case AArch64::LDADDLB:
34721 case AArch64::LDADDLH:
34722 case AArch64::LDADDLW:
34723 case AArch64::LDADDLX:
34724 case AArch64::LDADDW:
34725 case AArch64::LDADDX:
34726 case AArch64::LDCLRAB:
34727 case AArch64::LDCLRAH:
34728 case AArch64::LDCLRALB:
34729 case AArch64::LDCLRALH:
34730 case AArch64::LDCLRALW:
34731 case AArch64::LDCLRALX:
34732 case AArch64::LDCLRAW:
34733 case AArch64::LDCLRAX:
34734 case AArch64::LDCLRB:
34735 case AArch64::LDCLRH:
34736 case AArch64::LDCLRLB:
34737 case AArch64::LDCLRLH:
34738 case AArch64::LDCLRLW:
34739 case AArch64::LDCLRLX:
34740 case AArch64::LDCLRW:
34741 case AArch64::LDCLRX:
34742 case AArch64::LDEORAB:
34743 case AArch64::LDEORAH:
34744 case AArch64::LDEORALB:
34745 case AArch64::LDEORALH:
34746 case AArch64::LDEORALW:
34747 case AArch64::LDEORALX:
34748 case AArch64::LDEORAW:
34749 case AArch64::LDEORAX:
34750 case AArch64::LDEORB:
34751 case AArch64::LDEORH:
34752 case AArch64::LDEORLB:
34753 case AArch64::LDEORLH:
34754 case AArch64::LDEORLW:
34755 case AArch64::LDEORLX:
34756 case AArch64::LDEORW:
34757 case AArch64::LDEORX:
34758 case AArch64::LDSETAB:
34759 case AArch64::LDSETAH:
34760 case AArch64::LDSETALB:
34761 case AArch64::LDSETALH:
34762 case AArch64::LDSETALW:
34763 case AArch64::LDSETALX:
34764 case AArch64::LDSETAW:
34765 case AArch64::LDSETAX:
34766 case AArch64::LDSETB:
34767 case AArch64::LDSETH:
34768 case AArch64::LDSETLB:
34769 case AArch64::LDSETLH:
34770 case AArch64::LDSETLW:
34771 case AArch64::LDSETLX:
34772 case AArch64::LDSETW:
34773 case AArch64::LDSETX:
34774 case AArch64::LDSMAXAB:
34775 case AArch64::LDSMAXAH:
34776 case AArch64::LDSMAXALB:
34777 case AArch64::LDSMAXALH:
34778 case AArch64::LDSMAXALW:
34779 case AArch64::LDSMAXALX:
34780 case AArch64::LDSMAXAW:
34781 case AArch64::LDSMAXAX:
34782 case AArch64::LDSMAXB:
34783 case AArch64::LDSMAXH:
34784 case AArch64::LDSMAXLB:
34785 case AArch64::LDSMAXLH:
34786 case AArch64::LDSMAXLW:
34787 case AArch64::LDSMAXLX:
34788 case AArch64::LDSMAXW:
34789 case AArch64::LDSMAXX:
34790 case AArch64::LDSMINAB:
34791 case AArch64::LDSMINAH:
34792 case AArch64::LDSMINALB:
34793 case AArch64::LDSMINALH:
34794 case AArch64::LDSMINALW:
34795 case AArch64::LDSMINALX:
34796 case AArch64::LDSMINAW:
34797 case AArch64::LDSMINAX:
34798 case AArch64::LDSMINB:
34799 case AArch64::LDSMINH:
34800 case AArch64::LDSMINLB:
34801 case AArch64::LDSMINLH:
34802 case AArch64::LDSMINLW:
34803 case AArch64::LDSMINLX:
34804 case AArch64::LDSMINW:
34805 case AArch64::LDSMINX:
34806 case AArch64::LDTADDALW:
34807 case AArch64::LDTADDALX:
34808 case AArch64::LDTADDAW:
34809 case AArch64::LDTADDAX:
34810 case AArch64::LDTADDLW:
34811 case AArch64::LDTADDLX:
34812 case AArch64::LDTADDW:
34813 case AArch64::LDTADDX:
34814 case AArch64::LDTCLRALW:
34815 case AArch64::LDTCLRALX:
34816 case AArch64::LDTCLRAW:
34817 case AArch64::LDTCLRAX:
34818 case AArch64::LDTCLRLW:
34819 case AArch64::LDTCLRLX:
34820 case AArch64::LDTCLRW:
34821 case AArch64::LDTCLRX:
34822 case AArch64::LDTSETALW:
34823 case AArch64::LDTSETALX:
34824 case AArch64::LDTSETAW:
34825 case AArch64::LDTSETAX:
34826 case AArch64::LDTSETLW:
34827 case AArch64::LDTSETLX:
34828 case AArch64::LDTSETW:
34829 case AArch64::LDTSETX:
34830 case AArch64::LDUMAXAB:
34831 case AArch64::LDUMAXAH:
34832 case AArch64::LDUMAXALB:
34833 case AArch64::LDUMAXALH:
34834 case AArch64::LDUMAXALW:
34835 case AArch64::LDUMAXALX:
34836 case AArch64::LDUMAXAW:
34837 case AArch64::LDUMAXAX:
34838 case AArch64::LDUMAXB:
34839 case AArch64::LDUMAXH:
34840 case AArch64::LDUMAXLB:
34841 case AArch64::LDUMAXLH:
34842 case AArch64::LDUMAXLW:
34843 case AArch64::LDUMAXLX:
34844 case AArch64::LDUMAXW:
34845 case AArch64::LDUMAXX:
34846 case AArch64::LDUMINAB:
34847 case AArch64::LDUMINAH:
34848 case AArch64::LDUMINALB:
34849 case AArch64::LDUMINALH:
34850 case AArch64::LDUMINALW:
34851 case AArch64::LDUMINALX:
34852 case AArch64::LDUMINAW:
34853 case AArch64::LDUMINAX:
34854 case AArch64::LDUMINB:
34855 case AArch64::LDUMINH:
34856 case AArch64::LDUMINLB:
34857 case AArch64::LDUMINLH:
34858 case AArch64::LDUMINLW:
34859 case AArch64::LDUMINLX:
34860 case AArch64::LDUMINW:
34861 case AArch64::LDUMINX:
34862 case AArch64::RCWCLR:
34863 case AArch64::RCWCLRA:
34864 case AArch64::RCWCLRAL:
34865 case AArch64::RCWCLRL:
34866 case AArch64::RCWCLRS:
34867 case AArch64::RCWCLRSA:
34868 case AArch64::RCWCLRSAL:
34869 case AArch64::RCWCLRSL:
34870 case AArch64::RCWSET:
34871 case AArch64::RCWSETA:
34872 case AArch64::RCWSETAL:
34873 case AArch64::RCWSETL:
34874 case AArch64::RCWSETS:
34875 case AArch64::RCWSETSA:
34876 case AArch64::RCWSETSAL:
34877 case AArch64::RCWSETSL:
34878 case AArch64::RCWSWP:
34879 case AArch64::RCWSWPA:
34880 case AArch64::RCWSWPAL:
34881 case AArch64::RCWSWPL:
34882 case AArch64::RCWSWPS:
34883 case AArch64::RCWSWPSA:
34884 case AArch64::RCWSWPSAL:
34885 case AArch64::RCWSWPSL:
34886 case AArch64::SWPAB:
34887 case AArch64::SWPAH:
34888 case AArch64::SWPALB:
34889 case AArch64::SWPALH:
34890 case AArch64::SWPALW:
34891 case AArch64::SWPALX:
34892 case AArch64::SWPAW:
34893 case AArch64::SWPAX:
34894 case AArch64::SWPB:
34895 case AArch64::SWPH:
34896 case AArch64::SWPLB:
34897 case AArch64::SWPLH:
34898 case AArch64::SWPLW:
34899 case AArch64::SWPLX:
34900 case AArch64::SWPTALW:
34901 case AArch64::SWPTALX:
34902 case AArch64::SWPTAW:
34903 case AArch64::SWPTAX:
34904 case AArch64::SWPTLW:
34905 case AArch64::SWPTLX:
34906 case AArch64::SWPTW:
34907 case AArch64::SWPTX:
34908 case AArch64::SWPW:
34909 case AArch64::SWPX: {
34910 switch (OpNum) {
34911 case 1:
34912 // op: Rs
34913 return 16;
34914 case 2:
34915 // op: Rn
34916 return 5;
34917 case 0:
34918 // op: Rt
34919 return 0;
34920 }
34921 break;
34922 }
34923 case AArch64::CASAB:
34924 case AArch64::CASAH:
34925 case AArch64::CASALB:
34926 case AArch64::CASALH:
34927 case AArch64::CASALTX:
34928 case AArch64::CASALW:
34929 case AArch64::CASALX:
34930 case AArch64::CASATX:
34931 case AArch64::CASAW:
34932 case AArch64::CASAX:
34933 case AArch64::CASB:
34934 case AArch64::CASH:
34935 case AArch64::CASLB:
34936 case AArch64::CASLH:
34937 case AArch64::CASLTX:
34938 case AArch64::CASLW:
34939 case AArch64::CASLX:
34940 case AArch64::CASPALTX:
34941 case AArch64::CASPALW:
34942 case AArch64::CASPALX:
34943 case AArch64::CASPATX:
34944 case AArch64::CASPAW:
34945 case AArch64::CASPAX:
34946 case AArch64::CASPLTX:
34947 case AArch64::CASPLW:
34948 case AArch64::CASPLX:
34949 case AArch64::CASPTX:
34950 case AArch64::CASPW:
34951 case AArch64::CASPX:
34952 case AArch64::CASTX:
34953 case AArch64::CASW:
34954 case AArch64::CASX:
34955 case AArch64::RCWCAS:
34956 case AArch64::RCWCASA:
34957 case AArch64::RCWCASAL:
34958 case AArch64::RCWCASL:
34959 case AArch64::RCWCASP:
34960 case AArch64::RCWCASPA:
34961 case AArch64::RCWCASPAL:
34962 case AArch64::RCWCASPL:
34963 case AArch64::RCWSCAS:
34964 case AArch64::RCWSCASA:
34965 case AArch64::RCWSCASAL:
34966 case AArch64::RCWSCASL:
34967 case AArch64::RCWSCASP:
34968 case AArch64::RCWSCASPA:
34969 case AArch64::RCWSCASPAL:
34970 case AArch64::RCWSCASPL: {
34971 switch (OpNum) {
34972 case 1:
34973 // op: Rs
34974 return 16;
34975 case 3:
34976 // op: Rn
34977 return 5;
34978 case 2:
34979 // op: Rt
34980 return 0;
34981 }
34982 break;
34983 }
34984 case AArch64::MSR:
34985 case AArch64::MSRR: {
34986 switch (OpNum) {
34987 case 1:
34988 // op: Rt
34989 return 0;
34990 case 0:
34991 // op: systemreg
34992 return 5;
34993 }
34994 break;
34995 }
34996 case AArch64::ST64BV:
34997 case AArch64::ST64BV0: {
34998 switch (OpNum) {
34999 case 1:
35000 // op: Rt
35001 return 0;
35002 case 2:
35003 // op: Rn
35004 return 5;
35005 case 0:
35006 // op: Rs
35007 return 16;
35008 }
35009 break;
35010 }
35011 case AArch64::STTXRWr:
35012 case AArch64::STTXRXr: {
35013 switch (OpNum) {
35014 case 1:
35015 // op: Rt
35016 return 0;
35017 case 2:
35018 // op: Rn
35019 return 5;
35020 case 0:
35021 // op: Ws
35022 return 16;
35023 }
35024 break;
35025 }
35026 case AArch64::LDRBBpost:
35027 case AArch64::LDRBBpre:
35028 case AArch64::LDRBpost:
35029 case AArch64::LDRBpre:
35030 case AArch64::LDRDpost:
35031 case AArch64::LDRDpre:
35032 case AArch64::LDRHHpost:
35033 case AArch64::LDRHHpre:
35034 case AArch64::LDRHpost:
35035 case AArch64::LDRHpre:
35036 case AArch64::LDRQpost:
35037 case AArch64::LDRQpre:
35038 case AArch64::LDRSBWpost:
35039 case AArch64::LDRSBWpre:
35040 case AArch64::LDRSBXpost:
35041 case AArch64::LDRSBXpre:
35042 case AArch64::LDRSHWpost:
35043 case AArch64::LDRSHWpre:
35044 case AArch64::LDRSHXpost:
35045 case AArch64::LDRSHXpre:
35046 case AArch64::LDRSWpost:
35047 case AArch64::LDRSWpre:
35048 case AArch64::LDRSpost:
35049 case AArch64::LDRSpre:
35050 case AArch64::LDRWpost:
35051 case AArch64::LDRWpre:
35052 case AArch64::LDRXpost:
35053 case AArch64::LDRXpre:
35054 case AArch64::STRBBpost:
35055 case AArch64::STRBBpre:
35056 case AArch64::STRBpost:
35057 case AArch64::STRBpre:
35058 case AArch64::STRDpost:
35059 case AArch64::STRDpre:
35060 case AArch64::STRHHpost:
35061 case AArch64::STRHHpre:
35062 case AArch64::STRHpost:
35063 case AArch64::STRHpre:
35064 case AArch64::STRQpost:
35065 case AArch64::STRQpre:
35066 case AArch64::STRSpost:
35067 case AArch64::STRSpre:
35068 case AArch64::STRWpost:
35069 case AArch64::STRWpre:
35070 case AArch64::STRXpost:
35071 case AArch64::STRXpre: {
35072 switch (OpNum) {
35073 case 1:
35074 // op: Rt
35075 return 0;
35076 case 2:
35077 // op: Rn
35078 return 5;
35079 case 3:
35080 // op: offset
35081 return 12;
35082 }
35083 break;
35084 }
35085 case AArch64::LDAPRWpost:
35086 case AArch64::LDAPRXpost:
35087 case AArch64::STLRWpre:
35088 case AArch64::STLRXpre: {
35089 switch (OpNum) {
35090 case 1:
35091 // op: Rt
35092 return 0;
35093 case 2:
35094 // op: Rn
35095 return 5;
35096 }
35097 break;
35098 }
35099 case AArch64::LDPDpost:
35100 case AArch64::LDPDpre:
35101 case AArch64::LDPQpost:
35102 case AArch64::LDPQpre:
35103 case AArch64::LDPSWpost:
35104 case AArch64::LDPSWpre:
35105 case AArch64::LDPSpost:
35106 case AArch64::LDPSpre:
35107 case AArch64::LDPWpost:
35108 case AArch64::LDPWpre:
35109 case AArch64::LDPXpost:
35110 case AArch64::LDPXpre:
35111 case AArch64::LDTPQpost:
35112 case AArch64::LDTPQpre:
35113 case AArch64::LDTPpost:
35114 case AArch64::LDTPpre:
35115 case AArch64::STGPpost:
35116 case AArch64::STGPpre:
35117 case AArch64::STPDpost:
35118 case AArch64::STPDpre:
35119 case AArch64::STPQpost:
35120 case AArch64::STPQpre:
35121 case AArch64::STPSpost:
35122 case AArch64::STPSpre:
35123 case AArch64::STPWpost:
35124 case AArch64::STPWpre:
35125 case AArch64::STPXpost:
35126 case AArch64::STPXpre:
35127 case AArch64::STTPQpost:
35128 case AArch64::STTPQpre:
35129 case AArch64::STTPpost:
35130 case AArch64::STTPpre: {
35131 switch (OpNum) {
35132 case 1:
35133 // op: Rt
35134 return 0;
35135 case 2:
35136 // op: Rt2
35137 return 10;
35138 case 3:
35139 // op: Rn
35140 return 5;
35141 case 4:
35142 // op: offset
35143 return 15;
35144 }
35145 break;
35146 }
35147 case AArch64::LDIAPPWpost:
35148 case AArch64::LDIAPPXpost:
35149 case AArch64::STILPWpre:
35150 case AArch64::STILPXpre: {
35151 switch (OpNum) {
35152 case 1:
35153 // op: Rt
35154 return 0;
35155 case 3:
35156 // op: Rn
35157 return 5;
35158 case 2:
35159 // op: Rt2
35160 return 16;
35161 }
35162 break;
35163 }
35164 case AArch64::LDR_ZA:
35165 case AArch64::STR_ZA: {
35166 switch (OpNum) {
35167 case 1:
35168 // op: Rv
35169 return 13;
35170 case 3:
35171 // op: Rn
35172 return 5;
35173 case 2:
35174 // op: imm4
35175 return 0;
35176 }
35177 break;
35178 }
35179 case AArch64::SHA512H:
35180 case AArch64::SHA512H2:
35181 case AArch64::SHA512SU1:
35182 case AArch64::SM3PARTW1:
35183 case AArch64::SM3PARTW2:
35184 case AArch64::TBXv8i8Four:
35185 case AArch64::TBXv8i8One:
35186 case AArch64::TBXv8i8Three:
35187 case AArch64::TBXv8i8Two:
35188 case AArch64::TBXv16i8Four:
35189 case AArch64::TBXv16i8One:
35190 case AArch64::TBXv16i8Three:
35191 case AArch64::TBXv16i8Two: {
35192 switch (OpNum) {
35193 case 1:
35194 // op: Vd
35195 return 0;
35196 case 2:
35197 // op: Vn
35198 return 5;
35199 case 3:
35200 // op: Vm
35201 return 16;
35202 }
35203 break;
35204 }
35205 case AArch64::SM3TT1A:
35206 case AArch64::SM3TT1B:
35207 case AArch64::SM3TT2A:
35208 case AArch64::SM3TT2B: {
35209 switch (OpNum) {
35210 case 1:
35211 // op: Vd
35212 return 0;
35213 case 2:
35214 // op: Vn
35215 return 5;
35216 case 4:
35217 // op: imm
35218 return 12;
35219 case 3:
35220 // op: Vm
35221 return 16;
35222 }
35223 break;
35224 }
35225 case AArch64::SHA512SU0:
35226 case AArch64::SM4E: {
35227 switch (OpNum) {
35228 case 1:
35229 // op: Vd
35230 return 0;
35231 case 2:
35232 // op: Vn
35233 return 5;
35234 }
35235 break;
35236 }
35237 case AArch64::LD1Fourv1d_POST:
35238 case AArch64::LD1Fourv2d_POST:
35239 case AArch64::LD1Fourv2s_POST:
35240 case AArch64::LD1Fourv4h_POST:
35241 case AArch64::LD1Fourv4s_POST:
35242 case AArch64::LD1Fourv8b_POST:
35243 case AArch64::LD1Fourv8h_POST:
35244 case AArch64::LD1Fourv16b_POST:
35245 case AArch64::LD1Onev1d_POST:
35246 case AArch64::LD1Onev2d_POST:
35247 case AArch64::LD1Onev2s_POST:
35248 case AArch64::LD1Onev4h_POST:
35249 case AArch64::LD1Onev4s_POST:
35250 case AArch64::LD1Onev8b_POST:
35251 case AArch64::LD1Onev8h_POST:
35252 case AArch64::LD1Onev16b_POST:
35253 case AArch64::LD1Rv1d_POST:
35254 case AArch64::LD1Rv2d_POST:
35255 case AArch64::LD1Rv2s_POST:
35256 case AArch64::LD1Rv4h_POST:
35257 case AArch64::LD1Rv4s_POST:
35258 case AArch64::LD1Rv8b_POST:
35259 case AArch64::LD1Rv8h_POST:
35260 case AArch64::LD1Rv16b_POST:
35261 case AArch64::LD1Threev1d_POST:
35262 case AArch64::LD1Threev2d_POST:
35263 case AArch64::LD1Threev2s_POST:
35264 case AArch64::LD1Threev4h_POST:
35265 case AArch64::LD1Threev4s_POST:
35266 case AArch64::LD1Threev8b_POST:
35267 case AArch64::LD1Threev8h_POST:
35268 case AArch64::LD1Threev16b_POST:
35269 case AArch64::LD1Twov1d_POST:
35270 case AArch64::LD1Twov2d_POST:
35271 case AArch64::LD1Twov2s_POST:
35272 case AArch64::LD1Twov4h_POST:
35273 case AArch64::LD1Twov4s_POST:
35274 case AArch64::LD1Twov8b_POST:
35275 case AArch64::LD1Twov8h_POST:
35276 case AArch64::LD1Twov16b_POST:
35277 case AArch64::LD2Rv1d_POST:
35278 case AArch64::LD2Rv2d_POST:
35279 case AArch64::LD2Rv2s_POST:
35280 case AArch64::LD2Rv4h_POST:
35281 case AArch64::LD2Rv4s_POST:
35282 case AArch64::LD2Rv8b_POST:
35283 case AArch64::LD2Rv8h_POST:
35284 case AArch64::LD2Rv16b_POST:
35285 case AArch64::LD2Twov2d_POST:
35286 case AArch64::LD2Twov2s_POST:
35287 case AArch64::LD2Twov4h_POST:
35288 case AArch64::LD2Twov4s_POST:
35289 case AArch64::LD2Twov8b_POST:
35290 case AArch64::LD2Twov8h_POST:
35291 case AArch64::LD2Twov16b_POST:
35292 case AArch64::LD3Rv1d_POST:
35293 case AArch64::LD3Rv2d_POST:
35294 case AArch64::LD3Rv2s_POST:
35295 case AArch64::LD3Rv4h_POST:
35296 case AArch64::LD3Rv4s_POST:
35297 case AArch64::LD3Rv8b_POST:
35298 case AArch64::LD3Rv8h_POST:
35299 case AArch64::LD3Rv16b_POST:
35300 case AArch64::LD3Threev2d_POST:
35301 case AArch64::LD3Threev2s_POST:
35302 case AArch64::LD3Threev4h_POST:
35303 case AArch64::LD3Threev4s_POST:
35304 case AArch64::LD3Threev8b_POST:
35305 case AArch64::LD3Threev8h_POST:
35306 case AArch64::LD3Threev16b_POST:
35307 case AArch64::LD4Fourv2d_POST:
35308 case AArch64::LD4Fourv2s_POST:
35309 case AArch64::LD4Fourv4h_POST:
35310 case AArch64::LD4Fourv4s_POST:
35311 case AArch64::LD4Fourv8b_POST:
35312 case AArch64::LD4Fourv8h_POST:
35313 case AArch64::LD4Fourv16b_POST:
35314 case AArch64::LD4Rv1d_POST:
35315 case AArch64::LD4Rv2d_POST:
35316 case AArch64::LD4Rv2s_POST:
35317 case AArch64::LD4Rv4h_POST:
35318 case AArch64::LD4Rv4s_POST:
35319 case AArch64::LD4Rv8b_POST:
35320 case AArch64::LD4Rv8h_POST:
35321 case AArch64::LD4Rv16b_POST:
35322 case AArch64::ST1Fourv1d_POST:
35323 case AArch64::ST1Fourv2d_POST:
35324 case AArch64::ST1Fourv2s_POST:
35325 case AArch64::ST1Fourv4h_POST:
35326 case AArch64::ST1Fourv4s_POST:
35327 case AArch64::ST1Fourv8b_POST:
35328 case AArch64::ST1Fourv8h_POST:
35329 case AArch64::ST1Fourv16b_POST:
35330 case AArch64::ST1Onev1d_POST:
35331 case AArch64::ST1Onev2d_POST:
35332 case AArch64::ST1Onev2s_POST:
35333 case AArch64::ST1Onev4h_POST:
35334 case AArch64::ST1Onev4s_POST:
35335 case AArch64::ST1Onev8b_POST:
35336 case AArch64::ST1Onev8h_POST:
35337 case AArch64::ST1Onev16b_POST:
35338 case AArch64::ST1Threev1d_POST:
35339 case AArch64::ST1Threev2d_POST:
35340 case AArch64::ST1Threev2s_POST:
35341 case AArch64::ST1Threev4h_POST:
35342 case AArch64::ST1Threev4s_POST:
35343 case AArch64::ST1Threev8b_POST:
35344 case AArch64::ST1Threev8h_POST:
35345 case AArch64::ST1Threev16b_POST:
35346 case AArch64::ST1Twov1d_POST:
35347 case AArch64::ST1Twov2d_POST:
35348 case AArch64::ST1Twov2s_POST:
35349 case AArch64::ST1Twov4h_POST:
35350 case AArch64::ST1Twov4s_POST:
35351 case AArch64::ST1Twov8b_POST:
35352 case AArch64::ST1Twov8h_POST:
35353 case AArch64::ST1Twov16b_POST:
35354 case AArch64::ST2Twov2d_POST:
35355 case AArch64::ST2Twov2s_POST:
35356 case AArch64::ST2Twov4h_POST:
35357 case AArch64::ST2Twov4s_POST:
35358 case AArch64::ST2Twov8b_POST:
35359 case AArch64::ST2Twov8h_POST:
35360 case AArch64::ST2Twov16b_POST:
35361 case AArch64::ST3Threev2d_POST:
35362 case AArch64::ST3Threev2s_POST:
35363 case AArch64::ST3Threev4h_POST:
35364 case AArch64::ST3Threev4s_POST:
35365 case AArch64::ST3Threev8b_POST:
35366 case AArch64::ST3Threev8h_POST:
35367 case AArch64::ST3Threev16b_POST:
35368 case AArch64::ST4Fourv2d_POST:
35369 case AArch64::ST4Fourv2s_POST:
35370 case AArch64::ST4Fourv4h_POST:
35371 case AArch64::ST4Fourv4s_POST:
35372 case AArch64::ST4Fourv8b_POST:
35373 case AArch64::ST4Fourv8h_POST:
35374 case AArch64::ST4Fourv16b_POST: {
35375 switch (OpNum) {
35376 case 1:
35377 // op: Vt
35378 return 0;
35379 case 2:
35380 // op: Rn
35381 return 5;
35382 case 3:
35383 // op: Xm
35384 return 16;
35385 }
35386 break;
35387 }
35388 case AArch64::LDAP1: {
35389 switch (OpNum) {
35390 case 1:
35391 // op: Vt
35392 return 0;
35393 case 3:
35394 // op: Rn
35395 return 5;
35396 case 2:
35397 // op: Q
35398 return 30;
35399 }
35400 break;
35401 }
35402 case AArch64::ST1i8_POST:
35403 case AArch64::ST2i8_POST:
35404 case AArch64::ST3i8_POST:
35405 case AArch64::ST4i8_POST: {
35406 switch (OpNum) {
35407 case 1:
35408 // op: Vt
35409 return 0;
35410 case 3:
35411 // op: Rn
35412 return 5;
35413 case 2:
35414 // op: idx
35415 return 10;
35416 case 4:
35417 // op: Xm
35418 return 16;
35419 }
35420 break;
35421 }
35422 case AArch64::LD1i8:
35423 case AArch64::LD2i8:
35424 case AArch64::LD3i8:
35425 case AArch64::LD4i8: {
35426 switch (OpNum) {
35427 case 1:
35428 // op: Vt
35429 return 0;
35430 case 3:
35431 // op: Rn
35432 return 5;
35433 case 2:
35434 // op: idx
35435 return 10;
35436 }
35437 break;
35438 }
35439 case AArch64::ST1i16_POST:
35440 case AArch64::ST2i16_POST:
35441 case AArch64::ST3i16_POST:
35442 case AArch64::ST4i16_POST: {
35443 switch (OpNum) {
35444 case 1:
35445 // op: Vt
35446 return 0;
35447 case 3:
35448 // op: Rn
35449 return 5;
35450 case 2:
35451 // op: idx
35452 return 11;
35453 case 4:
35454 // op: Xm
35455 return 16;
35456 }
35457 break;
35458 }
35459 case AArch64::LD1i16:
35460 case AArch64::LD2i16:
35461 case AArch64::LD3i16:
35462 case AArch64::LD4i16: {
35463 switch (OpNum) {
35464 case 1:
35465 // op: Vt
35466 return 0;
35467 case 3:
35468 // op: Rn
35469 return 5;
35470 case 2:
35471 // op: idx
35472 return 11;
35473 }
35474 break;
35475 }
35476 case AArch64::ST1i32_POST:
35477 case AArch64::ST2i32_POST:
35478 case AArch64::ST3i32_POST:
35479 case AArch64::ST4i32_POST: {
35480 switch (OpNum) {
35481 case 1:
35482 // op: Vt
35483 return 0;
35484 case 3:
35485 // op: Rn
35486 return 5;
35487 case 2:
35488 // op: idx
35489 return 12;
35490 case 4:
35491 // op: Xm
35492 return 16;
35493 }
35494 break;
35495 }
35496 case AArch64::LD1i32:
35497 case AArch64::LD2i32:
35498 case AArch64::LD3i32:
35499 case AArch64::LD4i32: {
35500 switch (OpNum) {
35501 case 1:
35502 // op: Vt
35503 return 0;
35504 case 3:
35505 // op: Rn
35506 return 5;
35507 case 2:
35508 // op: idx
35509 return 12;
35510 }
35511 break;
35512 }
35513 case AArch64::ST1i64_POST:
35514 case AArch64::ST2i64_POST:
35515 case AArch64::ST3i64_POST:
35516 case AArch64::ST4i64_POST: {
35517 switch (OpNum) {
35518 case 1:
35519 // op: Vt
35520 return 0;
35521 case 3:
35522 // op: Rn
35523 return 5;
35524 case 2:
35525 // op: idx
35526 return 30;
35527 case 4:
35528 // op: Xm
35529 return 16;
35530 }
35531 break;
35532 }
35533 case AArch64::LD1i64:
35534 case AArch64::LD2i64:
35535 case AArch64::LD3i64:
35536 case AArch64::LD4i64: {
35537 switch (OpNum) {
35538 case 1:
35539 // op: Vt
35540 return 0;
35541 case 3:
35542 // op: Rn
35543 return 5;
35544 case 2:
35545 // op: idx
35546 return 30;
35547 }
35548 break;
35549 }
35550 case AArch64::BF1CVTL_2ZZ_BtoH:
35551 case AArch64::BF1CVT_2ZZ_BtoH:
35552 case AArch64::BF2CVTL_2ZZ_BtoH:
35553 case AArch64::BF2CVT_2ZZ_BtoH:
35554 case AArch64::F1CVTL_2ZZ_BtoH:
35555 case AArch64::F1CVT_2ZZ_BtoH:
35556 case AArch64::F2CVTL_2ZZ_BtoH:
35557 case AArch64::F2CVT_2ZZ_BtoH:
35558 case AArch64::FCVTL_2ZZ_H_S:
35559 case AArch64::FCVT_2ZZ_H_S:
35560 case AArch64::SUNPK_VG2_2ZZ_D:
35561 case AArch64::SUNPK_VG2_2ZZ_H:
35562 case AArch64::SUNPK_VG2_2ZZ_S:
35563 case AArch64::UUNPK_VG2_2ZZ_D:
35564 case AArch64::UUNPK_VG2_2ZZ_H:
35565 case AArch64::UUNPK_VG2_2ZZ_S: {
35566 switch (OpNum) {
35567 case 1:
35568 // op: Zn
35569 return 5;
35570 case 0:
35571 // op: Zd
35572 return 1;
35573 }
35574 break;
35575 }
35576 case AArch64::BFCVTN_Z2Z_StoH:
35577 case AArch64::BFCVT_Z2Z_HtoB:
35578 case AArch64::BFCVT_Z2Z_StoH:
35579 case AArch64::FCVTN_Z2Z_StoH:
35580 case AArch64::FCVT_Z2Z_HtoB:
35581 case AArch64::FCVT_Z2Z_StoH:
35582 case AArch64::SQCVTU_Z2Z_StoH:
35583 case AArch64::SQCVT_Z2Z_StoH:
35584 case AArch64::UQCVT_Z2Z_StoH: {
35585 switch (OpNum) {
35586 case 1:
35587 // op: Zn
35588 return 6;
35589 case 0:
35590 // op: Zd
35591 return 0;
35592 }
35593 break;
35594 }
35595 case AArch64::FCVTZS_2Z2Z_StoS:
35596 case AArch64::FCVTZU_2Z2Z_StoS:
35597 case AArch64::FRINTA_2Z2Z_S:
35598 case AArch64::FRINTM_2Z2Z_S:
35599 case AArch64::FRINTN_2Z2Z_S:
35600 case AArch64::FRINTP_2Z2Z_S:
35601 case AArch64::SCVTF_2Z2Z_StoS:
35602 case AArch64::UCVTF_2Z2Z_StoS: {
35603 switch (OpNum) {
35604 case 1:
35605 // op: Zn
35606 return 6;
35607 case 0:
35608 // op: Zd
35609 return 1;
35610 }
35611 break;
35612 }
35613 case AArch64::SUNPK_VG4_4Z2Z_D:
35614 case AArch64::SUNPK_VG4_4Z2Z_H:
35615 case AArch64::SUNPK_VG4_4Z2Z_S:
35616 case AArch64::UUNPK_VG4_4Z2Z_D:
35617 case AArch64::UUNPK_VG4_4Z2Z_H:
35618 case AArch64::UUNPK_VG4_4Z2Z_S: {
35619 switch (OpNum) {
35620 case 1:
35621 // op: Zn
35622 return 6;
35623 case 0:
35624 // op: Zd
35625 return 2;
35626 }
35627 break;
35628 }
35629 case AArch64::SQRSHRN_VG4_Z4ZI_B:
35630 case AArch64::SQRSHRN_VG4_Z4ZI_H:
35631 case AArch64::SQRSHRUN_VG4_Z4ZI_B:
35632 case AArch64::SQRSHRUN_VG4_Z4ZI_H:
35633 case AArch64::SQRSHRU_VG4_Z4ZI_B:
35634 case AArch64::SQRSHRU_VG4_Z4ZI_H:
35635 case AArch64::SQRSHR_VG4_Z4ZI_B:
35636 case AArch64::SQRSHR_VG4_Z4ZI_H:
35637 case AArch64::UQRSHRN_VG4_Z4ZI_B:
35638 case AArch64::UQRSHRN_VG4_Z4ZI_H:
35639 case AArch64::UQRSHR_VG4_Z4ZI_B:
35640 case AArch64::UQRSHR_VG4_Z4ZI_H: {
35641 switch (OpNum) {
35642 case 1:
35643 // op: Zn
35644 return 7;
35645 case 0:
35646 // op: Zd
35647 return 0;
35648 case 2:
35649 // op: imm
35650 return 16;
35651 }
35652 break;
35653 }
35654 case AArch64::FCVTN_Z4Z_StoB:
35655 case AArch64::FCVT_Z4Z_StoB:
35656 case AArch64::SQCVTN_Z4Z_DtoH:
35657 case AArch64::SQCVTN_Z4Z_StoB:
35658 case AArch64::SQCVTUN_Z4Z_DtoH:
35659 case AArch64::SQCVTUN_Z4Z_StoB:
35660 case AArch64::SQCVTU_Z4Z_DtoH:
35661 case AArch64::SQCVTU_Z4Z_StoB:
35662 case AArch64::SQCVT_Z4Z_DtoH:
35663 case AArch64::SQCVT_Z4Z_StoB:
35664 case AArch64::UQCVTN_Z4Z_DtoH:
35665 case AArch64::UQCVTN_Z4Z_StoB:
35666 case AArch64::UQCVT_Z4Z_DtoH:
35667 case AArch64::UQCVT_Z4Z_StoB: {
35668 switch (OpNum) {
35669 case 1:
35670 // op: Zn
35671 return 7;
35672 case 0:
35673 // op: Zd
35674 return 0;
35675 }
35676 break;
35677 }
35678 case AArch64::FCVTZS_4Z4Z_StoS:
35679 case AArch64::FCVTZU_4Z4Z_StoS:
35680 case AArch64::FRINTA_4Z4Z_S:
35681 case AArch64::FRINTM_4Z4Z_S:
35682 case AArch64::FRINTN_4Z4Z_S:
35683 case AArch64::FRINTP_4Z4Z_S:
35684 case AArch64::SCVTF_4Z4Z_StoS:
35685 case AArch64::UCVTF_4Z4Z_StoS:
35686 case AArch64::UZP_VG4_4Z4Z_B:
35687 case AArch64::UZP_VG4_4Z4Z_D:
35688 case AArch64::UZP_VG4_4Z4Z_H:
35689 case AArch64::UZP_VG4_4Z4Z_Q:
35690 case AArch64::UZP_VG4_4Z4Z_S:
35691 case AArch64::ZIP_VG4_4Z4Z_B:
35692 case AArch64::ZIP_VG4_4Z4Z_D:
35693 case AArch64::ZIP_VG4_4Z4Z_H:
35694 case AArch64::ZIP_VG4_4Z4Z_Q:
35695 case AArch64::ZIP_VG4_4Z4Z_S: {
35696 switch (OpNum) {
35697 case 1:
35698 // op: Zn
35699 return 7;
35700 case 0:
35701 // op: Zd
35702 return 2;
35703 }
35704 break;
35705 }
35706 case AArch64::MOVT_TIX: {
35707 switch (OpNum) {
35708 case 1:
35709 // op: imm3
35710 return 12;
35711 case 2:
35712 // op: Rt
35713 return 0;
35714 }
35715 break;
35716 }
35717 case AArch64::ABS_ZPmZ_B:
35718 case AArch64::ABS_ZPmZ_D:
35719 case AArch64::ABS_ZPmZ_H:
35720 case AArch64::ABS_ZPmZ_S:
35721 case AArch64::BFCVT_ZPmZ:
35722 case AArch64::CLS_ZPmZ_B:
35723 case AArch64::CLS_ZPmZ_D:
35724 case AArch64::CLS_ZPmZ_H:
35725 case AArch64::CLS_ZPmZ_S:
35726 case AArch64::CLZ_ZPmZ_B:
35727 case AArch64::CLZ_ZPmZ_D:
35728 case AArch64::CLZ_ZPmZ_H:
35729 case AArch64::CLZ_ZPmZ_S:
35730 case AArch64::CNOT_ZPmZ_B:
35731 case AArch64::CNOT_ZPmZ_D:
35732 case AArch64::CNOT_ZPmZ_H:
35733 case AArch64::CNOT_ZPmZ_S:
35734 case AArch64::CNT_ZPmZ_B:
35735 case AArch64::CNT_ZPmZ_D:
35736 case AArch64::CNT_ZPmZ_H:
35737 case AArch64::CNT_ZPmZ_S:
35738 case AArch64::FABS_ZPmZ_D:
35739 case AArch64::FABS_ZPmZ_H:
35740 case AArch64::FABS_ZPmZ_S:
35741 case AArch64::FCVTX_ZPmZ_DtoS:
35742 case AArch64::FCVTZS_ZPmZ_DtoD:
35743 case AArch64::FCVTZS_ZPmZ_DtoS:
35744 case AArch64::FCVTZS_ZPmZ_HtoD:
35745 case AArch64::FCVTZS_ZPmZ_HtoH:
35746 case AArch64::FCVTZS_ZPmZ_HtoS:
35747 case AArch64::FCVTZS_ZPmZ_StoD:
35748 case AArch64::FCVTZS_ZPmZ_StoS:
35749 case AArch64::FCVTZU_ZPmZ_DtoD:
35750 case AArch64::FCVTZU_ZPmZ_DtoS:
35751 case AArch64::FCVTZU_ZPmZ_HtoD:
35752 case AArch64::FCVTZU_ZPmZ_HtoH:
35753 case AArch64::FCVTZU_ZPmZ_HtoS:
35754 case AArch64::FCVTZU_ZPmZ_StoD:
35755 case AArch64::FCVTZU_ZPmZ_StoS:
35756 case AArch64::FCVT_ZPmZ_DtoH:
35757 case AArch64::FCVT_ZPmZ_DtoS:
35758 case AArch64::FCVT_ZPmZ_HtoD:
35759 case AArch64::FCVT_ZPmZ_HtoS:
35760 case AArch64::FCVT_ZPmZ_StoD:
35761 case AArch64::FCVT_ZPmZ_StoH:
35762 case AArch64::FLOGB_ZPmZ_D:
35763 case AArch64::FLOGB_ZPmZ_H:
35764 case AArch64::FLOGB_ZPmZ_S:
35765 case AArch64::FNEG_ZPmZ_D:
35766 case AArch64::FNEG_ZPmZ_H:
35767 case AArch64::FNEG_ZPmZ_S:
35768 case AArch64::FRECPX_ZPmZ_D:
35769 case AArch64::FRECPX_ZPmZ_H:
35770 case AArch64::FRECPX_ZPmZ_S:
35771 case AArch64::FRINT32X_ZPmZ_D:
35772 case AArch64::FRINT32X_ZPmZ_S:
35773 case AArch64::FRINT32Z_ZPmZ_D:
35774 case AArch64::FRINT32Z_ZPmZ_S:
35775 case AArch64::FRINT64X_ZPmZ_D:
35776 case AArch64::FRINT64X_ZPmZ_S:
35777 case AArch64::FRINT64Z_ZPmZ_D:
35778 case AArch64::FRINT64Z_ZPmZ_S:
35779 case AArch64::FRINTA_ZPmZ_D:
35780 case AArch64::FRINTA_ZPmZ_H:
35781 case AArch64::FRINTA_ZPmZ_S:
35782 case AArch64::FRINTI_ZPmZ_D:
35783 case AArch64::FRINTI_ZPmZ_H:
35784 case AArch64::FRINTI_ZPmZ_S:
35785 case AArch64::FRINTM_ZPmZ_D:
35786 case AArch64::FRINTM_ZPmZ_H:
35787 case AArch64::FRINTM_ZPmZ_S:
35788 case AArch64::FRINTN_ZPmZ_D:
35789 case AArch64::FRINTN_ZPmZ_H:
35790 case AArch64::FRINTN_ZPmZ_S:
35791 case AArch64::FRINTP_ZPmZ_D:
35792 case AArch64::FRINTP_ZPmZ_H:
35793 case AArch64::FRINTP_ZPmZ_S:
35794 case AArch64::FRINTX_ZPmZ_D:
35795 case AArch64::FRINTX_ZPmZ_H:
35796 case AArch64::FRINTX_ZPmZ_S:
35797 case AArch64::FRINTZ_ZPmZ_D:
35798 case AArch64::FRINTZ_ZPmZ_H:
35799 case AArch64::FRINTZ_ZPmZ_S:
35800 case AArch64::FSQRT_ZPmZ_D:
35801 case AArch64::FSQRT_ZPmZ_H:
35802 case AArch64::FSQRT_ZPmZ_S:
35803 case AArch64::MOVPRFX_ZPmZ_B:
35804 case AArch64::MOVPRFX_ZPmZ_D:
35805 case AArch64::MOVPRFX_ZPmZ_H:
35806 case AArch64::MOVPRFX_ZPmZ_S:
35807 case AArch64::NEG_ZPmZ_B:
35808 case AArch64::NEG_ZPmZ_D:
35809 case AArch64::NEG_ZPmZ_H:
35810 case AArch64::NEG_ZPmZ_S:
35811 case AArch64::NOT_ZPmZ_B:
35812 case AArch64::NOT_ZPmZ_D:
35813 case AArch64::NOT_ZPmZ_H:
35814 case AArch64::NOT_ZPmZ_S:
35815 case AArch64::SCVTF_ZPmZ_DtoD:
35816 case AArch64::SCVTF_ZPmZ_DtoH:
35817 case AArch64::SCVTF_ZPmZ_DtoS:
35818 case AArch64::SCVTF_ZPmZ_HtoH:
35819 case AArch64::SCVTF_ZPmZ_StoD:
35820 case AArch64::SCVTF_ZPmZ_StoH:
35821 case AArch64::SCVTF_ZPmZ_StoS:
35822 case AArch64::SQABS_ZPmZ_B:
35823 case AArch64::SQABS_ZPmZ_D:
35824 case AArch64::SQABS_ZPmZ_H:
35825 case AArch64::SQABS_ZPmZ_S:
35826 case AArch64::SQNEG_ZPmZ_B:
35827 case AArch64::SQNEG_ZPmZ_D:
35828 case AArch64::SQNEG_ZPmZ_H:
35829 case AArch64::SQNEG_ZPmZ_S:
35830 case AArch64::SXTB_ZPmZ_D:
35831 case AArch64::SXTB_ZPmZ_H:
35832 case AArch64::SXTB_ZPmZ_S:
35833 case AArch64::SXTH_ZPmZ_D:
35834 case AArch64::SXTH_ZPmZ_S:
35835 case AArch64::SXTW_ZPmZ_D:
35836 case AArch64::UCVTF_ZPmZ_DtoD:
35837 case AArch64::UCVTF_ZPmZ_DtoH:
35838 case AArch64::UCVTF_ZPmZ_DtoS:
35839 case AArch64::UCVTF_ZPmZ_HtoH:
35840 case AArch64::UCVTF_ZPmZ_StoD:
35841 case AArch64::UCVTF_ZPmZ_StoH:
35842 case AArch64::UCVTF_ZPmZ_StoS:
35843 case AArch64::URECPE_ZPmZ_S:
35844 case AArch64::URSQRTE_ZPmZ_S:
35845 case AArch64::UXTB_ZPmZ_D:
35846 case AArch64::UXTB_ZPmZ_H:
35847 case AArch64::UXTB_ZPmZ_S:
35848 case AArch64::UXTH_ZPmZ_D:
35849 case AArch64::UXTH_ZPmZ_S:
35850 case AArch64::UXTW_ZPmZ_D: {
35851 switch (OpNum) {
35852 case 2:
35853 // op: Pg
35854 return 10;
35855 case 0:
35856 // op: Zd
35857 return 0;
35858 case 3:
35859 // op: Zn
35860 return 5;
35861 }
35862 break;
35863 }
35864 case AArch64::CPY_ZPmR_B:
35865 case AArch64::CPY_ZPmR_D:
35866 case AArch64::CPY_ZPmR_H:
35867 case AArch64::CPY_ZPmR_S: {
35868 switch (OpNum) {
35869 case 2:
35870 // op: Pg
35871 return 10;
35872 case 3:
35873 // op: Rn
35874 return 5;
35875 case 0:
35876 // op: Zd
35877 return 0;
35878 }
35879 break;
35880 }
35881 case AArch64::CPY_ZPmV_B:
35882 case AArch64::CPY_ZPmV_D:
35883 case AArch64::CPY_ZPmV_H:
35884 case AArch64::CPY_ZPmV_S: {
35885 switch (OpNum) {
35886 case 2:
35887 // op: Pg
35888 return 10;
35889 case 3:
35890 // op: Vn
35891 return 5;
35892 case 0:
35893 // op: Zd
35894 return 0;
35895 }
35896 break;
35897 }
35898 case AArch64::FCPY_ZPmI_D:
35899 case AArch64::FCPY_ZPmI_H:
35900 case AArch64::FCPY_ZPmI_S: {
35901 switch (OpNum) {
35902 case 2:
35903 // op: Pg
35904 return 16;
35905 case 0:
35906 // op: Zd
35907 return 0;
35908 case 3:
35909 // op: imm8
35910 return 5;
35911 }
35912 break;
35913 }
35914 case AArch64::DECP_ZP_D:
35915 case AArch64::DECP_ZP_H:
35916 case AArch64::DECP_ZP_S:
35917 case AArch64::INCP_ZP_D:
35918 case AArch64::INCP_ZP_H:
35919 case AArch64::INCP_ZP_S:
35920 case AArch64::SQDECP_ZP_D:
35921 case AArch64::SQDECP_ZP_H:
35922 case AArch64::SQDECP_ZP_S:
35923 case AArch64::SQINCP_ZP_D:
35924 case AArch64::SQINCP_ZP_H:
35925 case AArch64::SQINCP_ZP_S:
35926 case AArch64::UQDECP_ZP_D:
35927 case AArch64::UQDECP_ZP_H:
35928 case AArch64::UQDECP_ZP_S:
35929 case AArch64::UQINCP_ZP_D:
35930 case AArch64::UQINCP_ZP_H:
35931 case AArch64::UQINCP_ZP_S: {
35932 switch (OpNum) {
35933 case 2:
35934 // op: Pm
35935 return 5;
35936 case 0:
35937 // op: Zdn
35938 return 0;
35939 }
35940 break;
35941 }
35942 case AArch64::MOPSSETGE:
35943 case AArch64::MOPSSETGEN:
35944 case AArch64::MOPSSETGET:
35945 case AArch64::MOPSSETGETN:
35946 case AArch64::SETE:
35947 case AArch64::SETEN:
35948 case AArch64::SETET:
35949 case AArch64::SETETN:
35950 case AArch64::SETGM:
35951 case AArch64::SETGMN:
35952 case AArch64::SETGMT:
35953 case AArch64::SETGMTN:
35954 case AArch64::SETGP:
35955 case AArch64::SETGPN:
35956 case AArch64::SETGPT:
35957 case AArch64::SETGPTN:
35958 case AArch64::SETM:
35959 case AArch64::SETMN:
35960 case AArch64::SETMT:
35961 case AArch64::SETMTN:
35962 case AArch64::SETP:
35963 case AArch64::SETPN:
35964 case AArch64::SETPT:
35965 case AArch64::SETPTN: {
35966 switch (OpNum) {
35967 case 2:
35968 // op: Rd
35969 return 0;
35970 case 3:
35971 // op: Rn
35972 return 5;
35973 case 4:
35974 // op: Rm
35975 return 16;
35976 }
35977 break;
35978 }
35979 case AArch64::INDEX_IR_B:
35980 case AArch64::INDEX_IR_D:
35981 case AArch64::INDEX_IR_H:
35982 case AArch64::INDEX_IR_S: {
35983 switch (OpNum) {
35984 case 2:
35985 // op: Rm
35986 return 16;
35987 case 0:
35988 // op: Zd
35989 return 0;
35990 case 1:
35991 // op: imm5
35992 return 5;
35993 }
35994 break;
35995 }
35996 case AArch64::INSR_ZR_B:
35997 case AArch64::INSR_ZR_D:
35998 case AArch64::INSR_ZR_H:
35999 case AArch64::INSR_ZR_S: {
36000 switch (OpNum) {
36001 case 2:
36002 // op: Rm
36003 return 5;
36004 case 0:
36005 // op: Zdn
36006 return 0;
36007 }
36008 break;
36009 }
36010 case AArch64::PRFB_PRI:
36011 case AArch64::PRFD_PRI:
36012 case AArch64::PRFH_PRI:
36013 case AArch64::PRFW_PRI: {
36014 switch (OpNum) {
36015 case 2:
36016 // op: Rn
36017 return 5;
36018 case 1:
36019 // op: Pg
36020 return 10;
36021 case 3:
36022 // op: imm6
36023 return 16;
36024 case 0:
36025 // op: prfop
36026 return 0;
36027 }
36028 break;
36029 }
36030 case AArch64::LDG:
36031 case AArch64::ST2GPostIndex:
36032 case AArch64::ST2GPreIndex:
36033 case AArch64::STGPostIndex:
36034 case AArch64::STGPreIndex:
36035 case AArch64::STZ2GPostIndex:
36036 case AArch64::STZ2GPreIndex:
36037 case AArch64::STZGPostIndex:
36038 case AArch64::STZGPreIndex: {
36039 switch (OpNum) {
36040 case 2:
36041 // op: Rn
36042 return 5;
36043 case 1:
36044 // op: Rt
36045 return 0;
36046 case 3:
36047 // op: offset
36048 return 12;
36049 }
36050 break;
36051 }
36052 case AArch64::MOVA_VG2_MXI2Z: {
36053 switch (OpNum) {
36054 case 2:
36055 // op: Rs
36056 return 13;
36057 case 3:
36058 // op: imm
36059 return 0;
36060 case 4:
36061 // op: Zn
36062 return 6;
36063 }
36064 break;
36065 }
36066 case AArch64::MOVA_VG4_MXI4Z: {
36067 switch (OpNum) {
36068 case 2:
36069 // op: Rs
36070 return 13;
36071 case 3:
36072 // op: imm
36073 return 0;
36074 case 4:
36075 // op: Zn
36076 return 7;
36077 }
36078 break;
36079 }
36080 case AArch64::MOVA_VG2_2ZMXI: {
36081 switch (OpNum) {
36082 case 2:
36083 // op: Rs
36084 return 13;
36085 case 3:
36086 // op: imm
36087 return 5;
36088 case 0:
36089 // op: Zd
36090 return 1;
36091 }
36092 break;
36093 }
36094 case AArch64::MOVA_VG4_4ZMXI: {
36095 switch (OpNum) {
36096 case 2:
36097 // op: Rs
36098 return 13;
36099 case 3:
36100 // op: imm
36101 return 5;
36102 case 0:
36103 // op: Zd
36104 return 2;
36105 }
36106 break;
36107 }
36108 case AArch64::MOVA_MXI2Z_H_D:
36109 case AArch64::MOVA_MXI2Z_V_D: {
36110 switch (OpNum) {
36111 case 2:
36112 // op: Rs
36113 return 13;
36114 case 4:
36115 // op: Zn
36116 return 6;
36117 case 0:
36118 // op: ZAd
36119 return 0;
36120 }
36121 break;
36122 }
36123 case AArch64::MOVA_MXI2Z_H_S:
36124 case AArch64::MOVA_MXI2Z_V_S: {
36125 switch (OpNum) {
36126 case 2:
36127 // op: Rs
36128 return 13;
36129 case 4:
36130 // op: Zn
36131 return 6;
36132 case 0:
36133 // op: ZAd
36134 return 1;
36135 case 3:
36136 // op: imm
36137 return 0;
36138 }
36139 break;
36140 }
36141 case AArch64::MOVA_MXI2Z_H_H:
36142 case AArch64::MOVA_MXI2Z_V_H: {
36143 switch (OpNum) {
36144 case 2:
36145 // op: Rs
36146 return 13;
36147 case 4:
36148 // op: Zn
36149 return 6;
36150 case 0:
36151 // op: ZAd
36152 return 2;
36153 case 3:
36154 // op: imm
36155 return 0;
36156 }
36157 break;
36158 }
36159 case AArch64::MOVA_MXI2Z_H_B:
36160 case AArch64::MOVA_MXI2Z_V_B: {
36161 switch (OpNum) {
36162 case 2:
36163 // op: Rs
36164 return 13;
36165 case 4:
36166 // op: Zn
36167 return 6;
36168 case 3:
36169 // op: imm
36170 return 0;
36171 }
36172 break;
36173 }
36174 case AArch64::MOVA_MXI4Z_H_D:
36175 case AArch64::MOVA_MXI4Z_H_S:
36176 case AArch64::MOVA_MXI4Z_V_D:
36177 case AArch64::MOVA_MXI4Z_V_S: {
36178 switch (OpNum) {
36179 case 2:
36180 // op: Rs
36181 return 13;
36182 case 4:
36183 // op: Zn
36184 return 7;
36185 case 0:
36186 // op: ZAd
36187 return 0;
36188 }
36189 break;
36190 }
36191 case AArch64::MOVA_MXI4Z_H_H:
36192 case AArch64::MOVA_MXI4Z_V_H: {
36193 switch (OpNum) {
36194 case 2:
36195 // op: Rs
36196 return 13;
36197 case 4:
36198 // op: Zn
36199 return 7;
36200 case 0:
36201 // op: ZAd
36202 return 1;
36203 case 3:
36204 // op: imm
36205 return 0;
36206 }
36207 break;
36208 }
36209 case AArch64::MOVA_MXI4Z_H_B:
36210 case AArch64::MOVA_MXI4Z_V_B: {
36211 switch (OpNum) {
36212 case 2:
36213 // op: Rs
36214 return 13;
36215 case 4:
36216 // op: Zn
36217 return 7;
36218 case 3:
36219 // op: imm
36220 return 0;
36221 }
36222 break;
36223 }
36224 case AArch64::LDCLRP:
36225 case AArch64::LDCLRPA:
36226 case AArch64::LDCLRPAL:
36227 case AArch64::LDCLRPL:
36228 case AArch64::LDSETP:
36229 case AArch64::LDSETPA:
36230 case AArch64::LDSETPAL:
36231 case AArch64::LDSETPL:
36232 case AArch64::SWPP:
36233 case AArch64::SWPPA:
36234 case AArch64::SWPPAL:
36235 case AArch64::SWPPL: {
36236 switch (OpNum) {
36237 case 2:
36238 // op: Rt
36239 return 0;
36240 case 3:
36241 // op: Rt2
36242 return 16;
36243 case 4:
36244 // op: Rn
36245 return 5;
36246 }
36247 break;
36248 }
36249 case AArch64::ZERO_MXI_2Z:
36250 case AArch64::ZERO_MXI_4Z:
36251 case AArch64::ZERO_MXI_VG2_2Z:
36252 case AArch64::ZERO_MXI_VG2_4Z:
36253 case AArch64::ZERO_MXI_VG2_Z:
36254 case AArch64::ZERO_MXI_VG4_2Z:
36255 case AArch64::ZERO_MXI_VG4_4Z:
36256 case AArch64::ZERO_MXI_VG4_Z: {
36257 switch (OpNum) {
36258 case 2:
36259 // op: Rv
36260 return 13;
36261 case 3:
36262 // op: imm
36263 return 0;
36264 }
36265 break;
36266 }
36267 case AArch64::ADD_VG2_M2Z_D:
36268 case AArch64::ADD_VG2_M2Z_S:
36269 case AArch64::BFADD_VG2_M2Z_H:
36270 case AArch64::BFSUB_VG2_M2Z_H:
36271 case AArch64::FADD_VG2_M2Z_D:
36272 case AArch64::FADD_VG2_M2Z_H:
36273 case AArch64::FADD_VG2_M2Z_S:
36274 case AArch64::FSUB_VG2_M2Z_D:
36275 case AArch64::FSUB_VG2_M2Z_H:
36276 case AArch64::FSUB_VG2_M2Z_S:
36277 case AArch64::SUB_VG2_M2Z_D:
36278 case AArch64::SUB_VG2_M2Z_S: {
36279 switch (OpNum) {
36280 case 2:
36281 // op: Rv
36282 return 13;
36283 case 3:
36284 // op: imm3
36285 return 0;
36286 case 4:
36287 // op: Zm
36288 return 6;
36289 }
36290 break;
36291 }
36292 case AArch64::ADD_VG4_M4Z_D:
36293 case AArch64::ADD_VG4_M4Z_S:
36294 case AArch64::BFADD_VG4_M4Z_H:
36295 case AArch64::BFSUB_VG4_M4Z_H:
36296 case AArch64::FADD_VG4_M4Z_D:
36297 case AArch64::FADD_VG4_M4Z_H:
36298 case AArch64::FADD_VG4_M4Z_S:
36299 case AArch64::FSUB_VG4_M4Z_D:
36300 case AArch64::FSUB_VG4_M4Z_H:
36301 case AArch64::FSUB_VG4_M4Z_S:
36302 case AArch64::SUB_VG4_M4Z_D:
36303 case AArch64::SUB_VG4_M4Z_S: {
36304 switch (OpNum) {
36305 case 2:
36306 // op: Rv
36307 return 13;
36308 case 3:
36309 // op: imm3
36310 return 0;
36311 case 4:
36312 // op: Zm
36313 return 7;
36314 }
36315 break;
36316 }
36317 case AArch64::INSERT_MXIPZ_H_Q:
36318 case AArch64::INSERT_MXIPZ_V_Q: {
36319 switch (OpNum) {
36320 case 2:
36321 // op: Rv
36322 return 13;
36323 case 4:
36324 // op: Pg
36325 return 10;
36326 case 5:
36327 // op: Zn
36328 return 5;
36329 case 0:
36330 // op: ZAd
36331 return 0;
36332 }
36333 break;
36334 }
36335 case AArch64::INSERT_MXIPZ_H_D:
36336 case AArch64::INSERT_MXIPZ_V_D: {
36337 switch (OpNum) {
36338 case 2:
36339 // op: Rv
36340 return 13;
36341 case 4:
36342 // op: Pg
36343 return 10;
36344 case 5:
36345 // op: Zn
36346 return 5;
36347 case 0:
36348 // op: ZAd
36349 return 1;
36350 case 3:
36351 // op: imm
36352 return 0;
36353 }
36354 break;
36355 }
36356 case AArch64::INSERT_MXIPZ_H_S:
36357 case AArch64::INSERT_MXIPZ_V_S: {
36358 switch (OpNum) {
36359 case 2:
36360 // op: Rv
36361 return 13;
36362 case 4:
36363 // op: Pg
36364 return 10;
36365 case 5:
36366 // op: Zn
36367 return 5;
36368 case 0:
36369 // op: ZAd
36370 return 2;
36371 case 3:
36372 // op: imm
36373 return 0;
36374 }
36375 break;
36376 }
36377 case AArch64::INSERT_MXIPZ_H_H:
36378 case AArch64::INSERT_MXIPZ_V_H: {
36379 switch (OpNum) {
36380 case 2:
36381 // op: Rv
36382 return 13;
36383 case 4:
36384 // op: Pg
36385 return 10;
36386 case 5:
36387 // op: Zn
36388 return 5;
36389 case 0:
36390 // op: ZAd
36391 return 3;
36392 case 3:
36393 // op: imm
36394 return 0;
36395 }
36396 break;
36397 }
36398 case AArch64::INSERT_MXIPZ_H_B:
36399 case AArch64::INSERT_MXIPZ_V_B: {
36400 switch (OpNum) {
36401 case 2:
36402 // op: Rv
36403 return 13;
36404 case 4:
36405 // op: Pg
36406 return 10;
36407 case 5:
36408 // op: Zn
36409 return 5;
36410 case 3:
36411 // op: imm
36412 return 0;
36413 }
36414 break;
36415 }
36416 case AArch64::BFMLAL_MZZ_HtoS:
36417 case AArch64::BFMLAL_VG2_M2ZZ_HtoS:
36418 case AArch64::BFMLAL_VG4_M4ZZ_HtoS:
36419 case AArch64::BFMLSL_MZZ_HtoS:
36420 case AArch64::BFMLSL_VG2_M2ZZ_HtoS:
36421 case AArch64::BFMLSL_VG4_M4ZZ_HtoS:
36422 case AArch64::FMLAL_MZZ_HtoS:
36423 case AArch64::FMLAL_VG2_M2ZZ_BtoH:
36424 case AArch64::FMLAL_VG2_M2ZZ_HtoS:
36425 case AArch64::FMLAL_VG2_MZZ_BtoH:
36426 case AArch64::FMLAL_VG4_M4ZZ_BtoH:
36427 case AArch64::FMLAL_VG4_M4ZZ_HtoS:
36428 case AArch64::FMLSL_MZZ_HtoS:
36429 case AArch64::FMLSL_VG2_M2ZZ_HtoS:
36430 case AArch64::FMLSL_VG4_M4ZZ_HtoS:
36431 case AArch64::SMLAL_MZZ_HtoS:
36432 case AArch64::SMLAL_VG2_M2ZZ_HtoS:
36433 case AArch64::SMLAL_VG4_M4ZZ_HtoS:
36434 case AArch64::SMLSL_MZZ_HtoS:
36435 case AArch64::SMLSL_VG2_M2ZZ_HtoS:
36436 case AArch64::SMLSL_VG4_M4ZZ_HtoS:
36437 case AArch64::UMLAL_MZZ_HtoS:
36438 case AArch64::UMLAL_VG2_M2ZZ_HtoS:
36439 case AArch64::UMLAL_VG4_M4ZZ_HtoS:
36440 case AArch64::UMLSL_MZZ_HtoS:
36441 case AArch64::UMLSL_VG2_M2ZZ_HtoS:
36442 case AArch64::UMLSL_VG4_M4ZZ_HtoS: {
36443 switch (OpNum) {
36444 case 2:
36445 // op: Rv
36446 return 13;
36447 case 5:
36448 // op: Zm
36449 return 16;
36450 case 4:
36451 // op: Zn
36452 return 5;
36453 case 3:
36454 // op: imm
36455 return 0;
36456 }
36457 break;
36458 }
36459 case AArch64::BFMLAL_VG2_M2Z2Z_HtoS:
36460 case AArch64::BFMLSL_VG2_M2Z2Z_HtoS:
36461 case AArch64::FMLAL_VG2_M2Z2Z_BtoH:
36462 case AArch64::FMLAL_VG2_M2Z2Z_HtoS:
36463 case AArch64::FMLSL_VG2_M2Z2Z_HtoS:
36464 case AArch64::SMLAL_VG2_M2Z2Z_HtoS:
36465 case AArch64::SMLSL_VG2_M2Z2Z_HtoS:
36466 case AArch64::UMLAL_VG2_M2Z2Z_HtoS:
36467 case AArch64::UMLSL_VG2_M2Z2Z_HtoS: {
36468 switch (OpNum) {
36469 case 2:
36470 // op: Rv
36471 return 13;
36472 case 5:
36473 // op: Zm
36474 return 17;
36475 case 4:
36476 // op: Zn
36477 return 6;
36478 case 3:
36479 // op: imm
36480 return 0;
36481 }
36482 break;
36483 }
36484 case AArch64::BFMLAL_VG4_M4Z4Z_HtoS:
36485 case AArch64::BFMLSL_VG4_M4Z4Z_HtoS:
36486 case AArch64::FMLAL_VG4_M4Z4Z_BtoH:
36487 case AArch64::FMLAL_VG4_M4Z4Z_HtoS:
36488 case AArch64::FMLSL_VG4_M4Z4Z_HtoS:
36489 case AArch64::SMLAL_VG4_M4Z4Z_HtoS:
36490 case AArch64::SMLSL_VG4_M4Z4Z_HtoS:
36491 case AArch64::UMLAL_VG4_M4Z4Z_HtoS:
36492 case AArch64::UMLSL_VG4_M4Z4Z_HtoS: {
36493 switch (OpNum) {
36494 case 2:
36495 // op: Rv
36496 return 13;
36497 case 5:
36498 // op: Zm
36499 return 18;
36500 case 4:
36501 // op: Zn
36502 return 7;
36503 case 3:
36504 // op: imm
36505 return 0;
36506 }
36507 break;
36508 }
36509 case AArch64::INSR_ZV_B:
36510 case AArch64::INSR_ZV_D:
36511 case AArch64::INSR_ZV_H:
36512 case AArch64::INSR_ZV_S: {
36513 switch (OpNum) {
36514 case 2:
36515 // op: Vm
36516 return 5;
36517 case 0:
36518 // op: Zdn
36519 return 0;
36520 }
36521 break;
36522 }
36523 case AArch64::LD1i8_POST:
36524 case AArch64::LD2i8_POST:
36525 case AArch64::LD3i8_POST:
36526 case AArch64::LD4i8_POST: {
36527 switch (OpNum) {
36528 case 2:
36529 // op: Vt
36530 return 0;
36531 case 4:
36532 // op: Rn
36533 return 5;
36534 case 3:
36535 // op: idx
36536 return 10;
36537 case 5:
36538 // op: Xm
36539 return 16;
36540 }
36541 break;
36542 }
36543 case AArch64::LD1i16_POST:
36544 case AArch64::LD2i16_POST:
36545 case AArch64::LD3i16_POST:
36546 case AArch64::LD4i16_POST: {
36547 switch (OpNum) {
36548 case 2:
36549 // op: Vt
36550 return 0;
36551 case 4:
36552 // op: Rn
36553 return 5;
36554 case 3:
36555 // op: idx
36556 return 11;
36557 case 5:
36558 // op: Xm
36559 return 16;
36560 }
36561 break;
36562 }
36563 case AArch64::LD1i32_POST:
36564 case AArch64::LD2i32_POST:
36565 case AArch64::LD3i32_POST:
36566 case AArch64::LD4i32_POST: {
36567 switch (OpNum) {
36568 case 2:
36569 // op: Vt
36570 return 0;
36571 case 4:
36572 // op: Rn
36573 return 5;
36574 case 3:
36575 // op: idx
36576 return 12;
36577 case 5:
36578 // op: Xm
36579 return 16;
36580 }
36581 break;
36582 }
36583 case AArch64::LD1i64_POST:
36584 case AArch64::LD2i64_POST:
36585 case AArch64::LD3i64_POST:
36586 case AArch64::LD4i64_POST: {
36587 switch (OpNum) {
36588 case 2:
36589 // op: Vt
36590 return 0;
36591 case 4:
36592 // op: Rn
36593 return 5;
36594 case 3:
36595 // op: idx
36596 return 30;
36597 case 5:
36598 // op: Xm
36599 return 16;
36600 }
36601 break;
36602 }
36603 case AArch64::ADD_VG2_2ZZ_B:
36604 case AArch64::ADD_VG2_2ZZ_D:
36605 case AArch64::ADD_VG2_2ZZ_H:
36606 case AArch64::ADD_VG2_2ZZ_S:
36607 case AArch64::BFMAXNM_VG2_2ZZ_H:
36608 case AArch64::BFMAX_VG2_2ZZ_H:
36609 case AArch64::BFMINNM_VG2_2ZZ_H:
36610 case AArch64::BFMIN_VG2_2ZZ_H:
36611 case AArch64::BFSCALE_2ZZ:
36612 case AArch64::FMAXNM_VG2_2ZZ_D:
36613 case AArch64::FMAXNM_VG2_2ZZ_H:
36614 case AArch64::FMAXNM_VG2_2ZZ_S:
36615 case AArch64::FMAX_VG2_2ZZ_D:
36616 case AArch64::FMAX_VG2_2ZZ_H:
36617 case AArch64::FMAX_VG2_2ZZ_S:
36618 case AArch64::FMINNM_VG2_2ZZ_D:
36619 case AArch64::FMINNM_VG2_2ZZ_H:
36620 case AArch64::FMINNM_VG2_2ZZ_S:
36621 case AArch64::FMIN_VG2_2ZZ_D:
36622 case AArch64::FMIN_VG2_2ZZ_H:
36623 case AArch64::FMIN_VG2_2ZZ_S:
36624 case AArch64::FSCALE_2ZZ_D:
36625 case AArch64::FSCALE_2ZZ_H:
36626 case AArch64::FSCALE_2ZZ_S:
36627 case AArch64::SMAX_VG2_2ZZ_B:
36628 case AArch64::SMAX_VG2_2ZZ_D:
36629 case AArch64::SMAX_VG2_2ZZ_H:
36630 case AArch64::SMAX_VG2_2ZZ_S:
36631 case AArch64::SMIN_VG2_2ZZ_B:
36632 case AArch64::SMIN_VG2_2ZZ_D:
36633 case AArch64::SMIN_VG2_2ZZ_H:
36634 case AArch64::SMIN_VG2_2ZZ_S:
36635 case AArch64::SQDMULH_VG2_2ZZ_B:
36636 case AArch64::SQDMULH_VG2_2ZZ_D:
36637 case AArch64::SQDMULH_VG2_2ZZ_H:
36638 case AArch64::SQDMULH_VG2_2ZZ_S:
36639 case AArch64::SRSHL_VG2_2ZZ_B:
36640 case AArch64::SRSHL_VG2_2ZZ_D:
36641 case AArch64::SRSHL_VG2_2ZZ_H:
36642 case AArch64::SRSHL_VG2_2ZZ_S:
36643 case AArch64::UMAX_VG2_2ZZ_B:
36644 case AArch64::UMAX_VG2_2ZZ_D:
36645 case AArch64::UMAX_VG2_2ZZ_H:
36646 case AArch64::UMAX_VG2_2ZZ_S:
36647 case AArch64::UMIN_VG2_2ZZ_B:
36648 case AArch64::UMIN_VG2_2ZZ_D:
36649 case AArch64::UMIN_VG2_2ZZ_H:
36650 case AArch64::UMIN_VG2_2ZZ_S:
36651 case AArch64::URSHL_VG2_2ZZ_B:
36652 case AArch64::URSHL_VG2_2ZZ_D:
36653 case AArch64::URSHL_VG2_2ZZ_H:
36654 case AArch64::URSHL_VG2_2ZZ_S: {
36655 switch (OpNum) {
36656 case 2:
36657 // op: Zm
36658 return 16;
36659 case 0:
36660 // op: Zdn
36661 return 1;
36662 }
36663 break;
36664 }
36665 case AArch64::ADD_VG4_4ZZ_B:
36666 case AArch64::ADD_VG4_4ZZ_D:
36667 case AArch64::ADD_VG4_4ZZ_H:
36668 case AArch64::ADD_VG4_4ZZ_S:
36669 case AArch64::BFMAXNM_VG4_4ZZ_H:
36670 case AArch64::BFMAX_VG4_4ZZ_H:
36671 case AArch64::BFMINNM_VG4_4ZZ_H:
36672 case AArch64::BFMIN_VG4_4ZZ_H:
36673 case AArch64::BFSCALE_4ZZ:
36674 case AArch64::FMAXNM_VG4_4ZZ_D:
36675 case AArch64::FMAXNM_VG4_4ZZ_H:
36676 case AArch64::FMAXNM_VG4_4ZZ_S:
36677 case AArch64::FMAX_VG4_4ZZ_D:
36678 case AArch64::FMAX_VG4_4ZZ_H:
36679 case AArch64::FMAX_VG4_4ZZ_S:
36680 case AArch64::FMINNM_VG4_4ZZ_D:
36681 case AArch64::FMINNM_VG4_4ZZ_H:
36682 case AArch64::FMINNM_VG4_4ZZ_S:
36683 case AArch64::FMIN_VG4_4ZZ_D:
36684 case AArch64::FMIN_VG4_4ZZ_H:
36685 case AArch64::FMIN_VG4_4ZZ_S:
36686 case AArch64::FSCALE_4ZZ_D:
36687 case AArch64::FSCALE_4ZZ_H:
36688 case AArch64::FSCALE_4ZZ_S:
36689 case AArch64::SMAX_VG4_4ZZ_B:
36690 case AArch64::SMAX_VG4_4ZZ_D:
36691 case AArch64::SMAX_VG4_4ZZ_H:
36692 case AArch64::SMAX_VG4_4ZZ_S:
36693 case AArch64::SMIN_VG4_4ZZ_B:
36694 case AArch64::SMIN_VG4_4ZZ_D:
36695 case AArch64::SMIN_VG4_4ZZ_H:
36696 case AArch64::SMIN_VG4_4ZZ_S:
36697 case AArch64::SQDMULH_VG4_4ZZ_B:
36698 case AArch64::SQDMULH_VG4_4ZZ_D:
36699 case AArch64::SQDMULH_VG4_4ZZ_H:
36700 case AArch64::SQDMULH_VG4_4ZZ_S:
36701 case AArch64::SRSHL_VG4_4ZZ_B:
36702 case AArch64::SRSHL_VG4_4ZZ_D:
36703 case AArch64::SRSHL_VG4_4ZZ_H:
36704 case AArch64::SRSHL_VG4_4ZZ_S:
36705 case AArch64::UMAX_VG4_4ZZ_B:
36706 case AArch64::UMAX_VG4_4ZZ_D:
36707 case AArch64::UMAX_VG4_4ZZ_H:
36708 case AArch64::UMAX_VG4_4ZZ_S:
36709 case AArch64::UMIN_VG4_4ZZ_B:
36710 case AArch64::UMIN_VG4_4ZZ_D:
36711 case AArch64::UMIN_VG4_4ZZ_H:
36712 case AArch64::UMIN_VG4_4ZZ_S:
36713 case AArch64::URSHL_VG4_4ZZ_B:
36714 case AArch64::URSHL_VG4_4ZZ_D:
36715 case AArch64::URSHL_VG4_4ZZ_H:
36716 case AArch64::URSHL_VG4_4ZZ_S: {
36717 switch (OpNum) {
36718 case 2:
36719 // op: Zm
36720 return 16;
36721 case 0:
36722 // op: Zdn
36723 return 2;
36724 }
36725 break;
36726 }
36727 case AArch64::PMULL_2ZZZ_Q: {
36728 switch (OpNum) {
36729 case 2:
36730 // op: Zm
36731 return 16;
36732 case 1:
36733 // op: Zn
36734 return 5;
36735 case 0:
36736 // op: Zd
36737 return 1;
36738 }
36739 break;
36740 }
36741 case AArch64::BFMAXNM_VG2_2Z2Z_H:
36742 case AArch64::BFMAX_VG2_2Z2Z_H:
36743 case AArch64::BFMINNM_VG2_2Z2Z_H:
36744 case AArch64::BFMIN_VG2_2Z2Z_H:
36745 case AArch64::BFSCALE_2Z2Z:
36746 case AArch64::FAMAX_2Z2Z_D:
36747 case AArch64::FAMAX_2Z2Z_H:
36748 case AArch64::FAMAX_2Z2Z_S:
36749 case AArch64::FAMIN_2Z2Z_D:
36750 case AArch64::FAMIN_2Z2Z_H:
36751 case AArch64::FAMIN_2Z2Z_S:
36752 case AArch64::FMAXNM_VG2_2Z2Z_D:
36753 case AArch64::FMAXNM_VG2_2Z2Z_H:
36754 case AArch64::FMAXNM_VG2_2Z2Z_S:
36755 case AArch64::FMAX_VG2_2Z2Z_D:
36756 case AArch64::FMAX_VG2_2Z2Z_H:
36757 case AArch64::FMAX_VG2_2Z2Z_S:
36758 case AArch64::FMINNM_VG2_2Z2Z_D:
36759 case AArch64::FMINNM_VG2_2Z2Z_H:
36760 case AArch64::FMINNM_VG2_2Z2Z_S:
36761 case AArch64::FMIN_VG2_2Z2Z_D:
36762 case AArch64::FMIN_VG2_2Z2Z_H:
36763 case AArch64::FMIN_VG2_2Z2Z_S:
36764 case AArch64::FSCALE_2Z2Z_D:
36765 case AArch64::FSCALE_2Z2Z_H:
36766 case AArch64::FSCALE_2Z2Z_S:
36767 case AArch64::SMAX_VG2_2Z2Z_B:
36768 case AArch64::SMAX_VG2_2Z2Z_D:
36769 case AArch64::SMAX_VG2_2Z2Z_H:
36770 case AArch64::SMAX_VG2_2Z2Z_S:
36771 case AArch64::SMIN_VG2_2Z2Z_B:
36772 case AArch64::SMIN_VG2_2Z2Z_D:
36773 case AArch64::SMIN_VG2_2Z2Z_H:
36774 case AArch64::SMIN_VG2_2Z2Z_S:
36775 case AArch64::SQDMULH_VG2_2Z2Z_B:
36776 case AArch64::SQDMULH_VG2_2Z2Z_D:
36777 case AArch64::SQDMULH_VG2_2Z2Z_H:
36778 case AArch64::SQDMULH_VG2_2Z2Z_S:
36779 case AArch64::SRSHL_VG2_2Z2Z_B:
36780 case AArch64::SRSHL_VG2_2Z2Z_D:
36781 case AArch64::SRSHL_VG2_2Z2Z_H:
36782 case AArch64::SRSHL_VG2_2Z2Z_S:
36783 case AArch64::UMAX_VG2_2Z2Z_B:
36784 case AArch64::UMAX_VG2_2Z2Z_D:
36785 case AArch64::UMAX_VG2_2Z2Z_H:
36786 case AArch64::UMAX_VG2_2Z2Z_S:
36787 case AArch64::UMIN_VG2_2Z2Z_B:
36788 case AArch64::UMIN_VG2_2Z2Z_D:
36789 case AArch64::UMIN_VG2_2Z2Z_H:
36790 case AArch64::UMIN_VG2_2Z2Z_S:
36791 case AArch64::URSHL_VG2_2Z2Z_B:
36792 case AArch64::URSHL_VG2_2Z2Z_D:
36793 case AArch64::URSHL_VG2_2Z2Z_H:
36794 case AArch64::URSHL_VG2_2Z2Z_S: {
36795 switch (OpNum) {
36796 case 2:
36797 // op: Zm
36798 return 17;
36799 case 0:
36800 // op: Zdn
36801 return 1;
36802 }
36803 break;
36804 }
36805 case AArch64::BFMAXNM_VG4_4Z2Z_H:
36806 case AArch64::BFMAX_VG4_4Z2Z_H:
36807 case AArch64::BFMINNM_VG4_4Z2Z_H:
36808 case AArch64::BFMIN_VG4_4Z2Z_H:
36809 case AArch64::BFSCALE_4Z4Z:
36810 case AArch64::FAMAX_4Z4Z_D:
36811 case AArch64::FAMAX_4Z4Z_H:
36812 case AArch64::FAMAX_4Z4Z_S:
36813 case AArch64::FAMIN_4Z4Z_D:
36814 case AArch64::FAMIN_4Z4Z_H:
36815 case AArch64::FAMIN_4Z4Z_S:
36816 case AArch64::FMAXNM_VG4_4Z4Z_D:
36817 case AArch64::FMAXNM_VG4_4Z4Z_H:
36818 case AArch64::FMAXNM_VG4_4Z4Z_S:
36819 case AArch64::FMAX_VG4_4Z4Z_D:
36820 case AArch64::FMAX_VG4_4Z4Z_H:
36821 case AArch64::FMAX_VG4_4Z4Z_S:
36822 case AArch64::FMINNM_VG4_4Z4Z_D:
36823 case AArch64::FMINNM_VG4_4Z4Z_H:
36824 case AArch64::FMINNM_VG4_4Z4Z_S:
36825 case AArch64::FMIN_VG4_4Z4Z_D:
36826 case AArch64::FMIN_VG4_4Z4Z_H:
36827 case AArch64::FMIN_VG4_4Z4Z_S:
36828 case AArch64::FSCALE_4Z4Z_D:
36829 case AArch64::FSCALE_4Z4Z_H:
36830 case AArch64::FSCALE_4Z4Z_S:
36831 case AArch64::SMAX_VG4_4Z4Z_B:
36832 case AArch64::SMAX_VG4_4Z4Z_D:
36833 case AArch64::SMAX_VG4_4Z4Z_H:
36834 case AArch64::SMAX_VG4_4Z4Z_S:
36835 case AArch64::SMIN_VG4_4Z4Z_B:
36836 case AArch64::SMIN_VG4_4Z4Z_D:
36837 case AArch64::SMIN_VG4_4Z4Z_H:
36838 case AArch64::SMIN_VG4_4Z4Z_S:
36839 case AArch64::SQDMULH_VG4_4Z4Z_B:
36840 case AArch64::SQDMULH_VG4_4Z4Z_D:
36841 case AArch64::SQDMULH_VG4_4Z4Z_H:
36842 case AArch64::SQDMULH_VG4_4Z4Z_S:
36843 case AArch64::SRSHL_VG4_4Z4Z_B:
36844 case AArch64::SRSHL_VG4_4Z4Z_D:
36845 case AArch64::SRSHL_VG4_4Z4Z_H:
36846 case AArch64::SRSHL_VG4_4Z4Z_S:
36847 case AArch64::UMAX_VG4_4Z4Z_B:
36848 case AArch64::UMAX_VG4_4Z4Z_D:
36849 case AArch64::UMAX_VG4_4Z4Z_H:
36850 case AArch64::UMAX_VG4_4Z4Z_S:
36851 case AArch64::UMIN_VG4_4Z4Z_B:
36852 case AArch64::UMIN_VG4_4Z4Z_D:
36853 case AArch64::UMIN_VG4_4Z4Z_H:
36854 case AArch64::UMIN_VG4_4Z4Z_S:
36855 case AArch64::URSHL_VG4_4Z4Z_B:
36856 case AArch64::URSHL_VG4_4Z4Z_D:
36857 case AArch64::URSHL_VG4_4Z4Z_H:
36858 case AArch64::URSHL_VG4_4Z4Z_S: {
36859 switch (OpNum) {
36860 case 2:
36861 // op: Zm
36862 return 18;
36863 case 0:
36864 // op: Zdn
36865 return 2;
36866 }
36867 break;
36868 }
36869 case AArch64::AESDMIC_2ZZI_B:
36870 case AArch64::AESD_2ZZI_B:
36871 case AArch64::AESEMC_2ZZI_B:
36872 case AArch64::AESE_2ZZI_B: {
36873 switch (OpNum) {
36874 case 2:
36875 // op: Zm
36876 return 5;
36877 case 0:
36878 // op: Zdn
36879 return 1;
36880 case 3:
36881 // op: imm2
36882 return 19;
36883 }
36884 break;
36885 }
36886 case AArch64::AESDMIC_4ZZI_B:
36887 case AArch64::AESD_4ZZI_B:
36888 case AArch64::AESEMC_4ZZI_B:
36889 case AArch64::AESE_4ZZI_B: {
36890 switch (OpNum) {
36891 case 2:
36892 // op: Zm
36893 return 5;
36894 case 0:
36895 // op: Zdn
36896 return 2;
36897 case 3:
36898 // op: imm2
36899 return 19;
36900 }
36901 break;
36902 }
36903 case AArch64::FADDV_VPZ_D:
36904 case AArch64::FADDV_VPZ_H:
36905 case AArch64::FADDV_VPZ_S:
36906 case AArch64::FMAXNMV_VPZ_D:
36907 case AArch64::FMAXNMV_VPZ_H:
36908 case AArch64::FMAXNMV_VPZ_S:
36909 case AArch64::FMAXV_VPZ_D:
36910 case AArch64::FMAXV_VPZ_H:
36911 case AArch64::FMAXV_VPZ_S:
36912 case AArch64::FMINNMV_VPZ_D:
36913 case AArch64::FMINNMV_VPZ_H:
36914 case AArch64::FMINNMV_VPZ_S:
36915 case AArch64::FMINV_VPZ_D:
36916 case AArch64::FMINV_VPZ_H:
36917 case AArch64::FMINV_VPZ_S: {
36918 switch (OpNum) {
36919 case 2:
36920 // op: Zn
36921 return 5;
36922 case 0:
36923 // op: Vd
36924 return 0;
36925 case 1:
36926 // op: Pg
36927 return 10;
36928 }
36929 break;
36930 }
36931 case AArch64::LUTI2_ZTZI_B:
36932 case AArch64::LUTI2_ZTZI_H:
36933 case AArch64::LUTI2_ZTZI_S:
36934 case AArch64::LUTI4_ZTZI_B:
36935 case AArch64::LUTI4_ZTZI_H:
36936 case AArch64::LUTI4_ZTZI_S: {
36937 switch (OpNum) {
36938 case 2:
36939 // op: Zn
36940 return 5;
36941 case 0:
36942 // op: Zd
36943 return 0;
36944 case 3:
36945 // op: i
36946 return 14;
36947 }
36948 break;
36949 }
36950 case AArch64::LUTI2_S_2ZTZI_B:
36951 case AArch64::LUTI2_S_2ZTZI_H:
36952 case AArch64::LUTI4_S_2ZTZI_B:
36953 case AArch64::LUTI4_S_2ZTZI_H: {
36954 switch (OpNum) {
36955 case 2:
36956 // op: Zn
36957 return 5;
36958 case 0:
36959 // op: Zd
36960 return 0;
36961 case 3:
36962 // op: i
36963 return 15;
36964 }
36965 break;
36966 }
36967 case AArch64::LUTI2_S_4ZTZI_B:
36968 case AArch64::LUTI2_S_4ZTZI_H:
36969 case AArch64::LUTI4_S_4ZTZI_H: {
36970 switch (OpNum) {
36971 case 2:
36972 // op: Zn
36973 return 5;
36974 case 0:
36975 // op: Zd
36976 return 0;
36977 case 3:
36978 // op: i
36979 return 16;
36980 }
36981 break;
36982 }
36983 case AArch64::LUTI2_2ZTZI_B:
36984 case AArch64::LUTI2_2ZTZI_H:
36985 case AArch64::LUTI2_2ZTZI_S:
36986 case AArch64::LUTI4_2ZTZI_B:
36987 case AArch64::LUTI4_2ZTZI_H:
36988 case AArch64::LUTI4_2ZTZI_S: {
36989 switch (OpNum) {
36990 case 2:
36991 // op: Zn
36992 return 5;
36993 case 0:
36994 // op: Zd
36995 return 1;
36996 case 3:
36997 // op: i
36998 return 15;
36999 }
37000 break;
37001 }
37002 case AArch64::LUTI2_4ZTZI_B:
37003 case AArch64::LUTI2_4ZTZI_H:
37004 case AArch64::LUTI2_4ZTZI_S:
37005 case AArch64::LUTI4_4ZTZI_H:
37006 case AArch64::LUTI4_4ZTZI_S: {
37007 switch (OpNum) {
37008 case 2:
37009 // op: Zn
37010 return 5;
37011 case 0:
37012 // op: Zd
37013 return 2;
37014 case 3:
37015 // op: i
37016 return 16;
37017 }
37018 break;
37019 }
37020 case AArch64::LUTI4_S_4ZZT2Z: {
37021 switch (OpNum) {
37022 case 2:
37023 // op: Zn
37024 return 6;
37025 case 0:
37026 // op: Zd
37027 return 0;
37028 }
37029 break;
37030 }
37031 case AArch64::LUTI4_4ZZT2Z: {
37032 switch (OpNum) {
37033 case 2:
37034 // op: Zn
37035 return 6;
37036 case 0:
37037 // op: Zd
37038 return 2;
37039 }
37040 break;
37041 }
37042 case AArch64::MOVT_TIZ: {
37043 switch (OpNum) {
37044 case 2:
37045 // op: Zt
37046 return 0;
37047 case 1:
37048 // op: off2
37049 return 12;
37050 }
37051 break;
37052 }
37053 case AArch64::MOVT_XTI: {
37054 switch (OpNum) {
37055 case 2:
37056 // op: imm3
37057 return 12;
37058 case 0:
37059 // op: Rt
37060 return 0;
37061 }
37062 break;
37063 }
37064 case AArch64::SQRSHRU_VG2_Z2ZI_H:
37065 case AArch64::SQRSHR_VG2_Z2ZI_H:
37066 case AArch64::UQRSHR_VG2_Z2ZI_H: {
37067 switch (OpNum) {
37068 case 2:
37069 // op: imm4
37070 return 16;
37071 case 1:
37072 // op: Zn
37073 return 6;
37074 case 0:
37075 // op: Zd
37076 return 0;
37077 }
37078 break;
37079 }
37080 case AArch64::LDRAAindexed:
37081 case AArch64::LDRABindexed: {
37082 switch (OpNum) {
37083 case 2:
37084 // op: offset
37085 return 12;
37086 case 1:
37087 // op: Rn
37088 return 5;
37089 case 0:
37090 // op: Rt
37091 return 0;
37092 }
37093 break;
37094 }
37095 case AArch64::ADDHA_MPPZ_D:
37096 case AArch64::ADDHA_MPPZ_S:
37097 case AArch64::ADDVA_MPPZ_D:
37098 case AArch64::ADDVA_MPPZ_S: {
37099 switch (OpNum) {
37100 case 3:
37101 // op: Pm
37102 return 13;
37103 case 2:
37104 // op: Pn
37105 return 10;
37106 case 4:
37107 // op: Zn
37108 return 5;
37109 case 0:
37110 // op: ZAda
37111 return 0;
37112 }
37113 break;
37114 }
37115 case AArch64::CPYE:
37116 case AArch64::CPYEN:
37117 case AArch64::CPYERN:
37118 case AArch64::CPYERT:
37119 case AArch64::CPYERTN:
37120 case AArch64::CPYERTRN:
37121 case AArch64::CPYERTWN:
37122 case AArch64::CPYET:
37123 case AArch64::CPYETN:
37124 case AArch64::CPYETRN:
37125 case AArch64::CPYETWN:
37126 case AArch64::CPYEWN:
37127 case AArch64::CPYEWT:
37128 case AArch64::CPYEWTN:
37129 case AArch64::CPYEWTRN:
37130 case AArch64::CPYEWTWN:
37131 case AArch64::CPYFE:
37132 case AArch64::CPYFEN:
37133 case AArch64::CPYFERN:
37134 case AArch64::CPYFERT:
37135 case AArch64::CPYFERTN:
37136 case AArch64::CPYFERTRN:
37137 case AArch64::CPYFERTWN:
37138 case AArch64::CPYFET:
37139 case AArch64::CPYFETN:
37140 case AArch64::CPYFETRN:
37141 case AArch64::CPYFETWN:
37142 case AArch64::CPYFEWN:
37143 case AArch64::CPYFEWT:
37144 case AArch64::CPYFEWTN:
37145 case AArch64::CPYFEWTRN:
37146 case AArch64::CPYFEWTWN:
37147 case AArch64::CPYFM:
37148 case AArch64::CPYFMN:
37149 case AArch64::CPYFMRN:
37150 case AArch64::CPYFMRT:
37151 case AArch64::CPYFMRTN:
37152 case AArch64::CPYFMRTRN:
37153 case AArch64::CPYFMRTWN:
37154 case AArch64::CPYFMT:
37155 case AArch64::CPYFMTN:
37156 case AArch64::CPYFMTRN:
37157 case AArch64::CPYFMTWN:
37158 case AArch64::CPYFMWN:
37159 case AArch64::CPYFMWT:
37160 case AArch64::CPYFMWTN:
37161 case AArch64::CPYFMWTRN:
37162 case AArch64::CPYFMWTWN:
37163 case AArch64::CPYFP:
37164 case AArch64::CPYFPN:
37165 case AArch64::CPYFPRN:
37166 case AArch64::CPYFPRT:
37167 case AArch64::CPYFPRTN:
37168 case AArch64::CPYFPRTRN:
37169 case AArch64::CPYFPRTWN:
37170 case AArch64::CPYFPT:
37171 case AArch64::CPYFPTN:
37172 case AArch64::CPYFPTRN:
37173 case AArch64::CPYFPTWN:
37174 case AArch64::CPYFPWN:
37175 case AArch64::CPYFPWT:
37176 case AArch64::CPYFPWTN:
37177 case AArch64::CPYFPWTRN:
37178 case AArch64::CPYFPWTWN:
37179 case AArch64::CPYM:
37180 case AArch64::CPYMN:
37181 case AArch64::CPYMRN:
37182 case AArch64::CPYMRT:
37183 case AArch64::CPYMRTN:
37184 case AArch64::CPYMRTRN:
37185 case AArch64::CPYMRTWN:
37186 case AArch64::CPYMT:
37187 case AArch64::CPYMTN:
37188 case AArch64::CPYMTRN:
37189 case AArch64::CPYMTWN:
37190 case AArch64::CPYMWN:
37191 case AArch64::CPYMWT:
37192 case AArch64::CPYMWTN:
37193 case AArch64::CPYMWTRN:
37194 case AArch64::CPYMWTWN:
37195 case AArch64::CPYP:
37196 case AArch64::CPYPN:
37197 case AArch64::CPYPRN:
37198 case AArch64::CPYPRT:
37199 case AArch64::CPYPRTN:
37200 case AArch64::CPYPRTRN:
37201 case AArch64::CPYPRTWN:
37202 case AArch64::CPYPT:
37203 case AArch64::CPYPTN:
37204 case AArch64::CPYPTRN:
37205 case AArch64::CPYPTWN:
37206 case AArch64::CPYPWN:
37207 case AArch64::CPYPWT:
37208 case AArch64::CPYPWTN:
37209 case AArch64::CPYPWTRN:
37210 case AArch64::CPYPWTWN: {
37211 switch (OpNum) {
37212 case 3:
37213 // op: Rd
37214 return 0;
37215 case 4:
37216 // op: Rs
37217 return 16;
37218 case 5:
37219 // op: Rn
37220 return 5;
37221 }
37222 break;
37223 }
37224 case AArch64::LD1B_2Z_STRIDED:
37225 case AArch64::LD1B_4Z_STRIDED:
37226 case AArch64::LD1D_2Z_STRIDED:
37227 case AArch64::LD1D_4Z_STRIDED:
37228 case AArch64::LD1H_2Z_STRIDED:
37229 case AArch64::LD1H_4Z_STRIDED:
37230 case AArch64::LD1W_2Z_STRIDED:
37231 case AArch64::LD1W_4Z_STRIDED:
37232 case AArch64::LDNT1B_2Z_STRIDED:
37233 case AArch64::LDNT1B_4Z_STRIDED:
37234 case AArch64::LDNT1D_2Z_STRIDED:
37235 case AArch64::LDNT1D_4Z_STRIDED:
37236 case AArch64::LDNT1H_2Z_STRIDED:
37237 case AArch64::LDNT1H_4Z_STRIDED:
37238 case AArch64::LDNT1W_2Z_STRIDED:
37239 case AArch64::LDNT1W_4Z_STRIDED:
37240 case AArch64::ST1B_2Z_STRIDED:
37241 case AArch64::ST1B_4Z_STRIDED:
37242 case AArch64::ST1D_2Z_STRIDED:
37243 case AArch64::ST1D_4Z_STRIDED:
37244 case AArch64::ST1H_2Z_STRIDED:
37245 case AArch64::ST1H_4Z_STRIDED:
37246 case AArch64::ST1W_2Z_STRIDED:
37247 case AArch64::ST1W_4Z_STRIDED:
37248 case AArch64::STNT1B_2Z_STRIDED:
37249 case AArch64::STNT1B_4Z_STRIDED:
37250 case AArch64::STNT1D_2Z_STRIDED:
37251 case AArch64::STNT1D_4Z_STRIDED:
37252 case AArch64::STNT1H_2Z_STRIDED:
37253 case AArch64::STNT1H_4Z_STRIDED:
37254 case AArch64::STNT1W_2Z_STRIDED:
37255 case AArch64::STNT1W_4Z_STRIDED: {
37256 switch (OpNum) {
37257 case 3:
37258 // op: Rm
37259 return 16;
37260 case 1:
37261 // op: PNg
37262 return 10;
37263 case 2:
37264 // op: Rn
37265 return 5;
37266 case 0:
37267 // op: Zt
37268 return 0;
37269 }
37270 break;
37271 }
37272 case AArch64::PRFB_PRR:
37273 case AArch64::PRFD_PRR:
37274 case AArch64::PRFH_PRR:
37275 case AArch64::PRFW_PRR: {
37276 switch (OpNum) {
37277 case 3:
37278 // op: Rm
37279 return 16;
37280 case 2:
37281 // op: Rn
37282 return 5;
37283 case 1:
37284 // op: Pg
37285 return 10;
37286 case 0:
37287 // op: prfop
37288 return 0;
37289 }
37290 break;
37291 }
37292 case AArch64::MOVAZ_ZMI_H_Q:
37293 case AArch64::MOVAZ_ZMI_V_Q: {
37294 switch (OpNum) {
37295 case 3:
37296 // op: Rs
37297 return 13;
37298 case 0:
37299 // op: Zd
37300 return 0;
37301 case 1:
37302 // op: ZAn
37303 return 5;
37304 }
37305 break;
37306 }
37307 case AArch64::MOVAZ_ZMI_H_D:
37308 case AArch64::MOVAZ_ZMI_V_D: {
37309 switch (OpNum) {
37310 case 3:
37311 // op: Rs
37312 return 13;
37313 case 0:
37314 // op: Zd
37315 return 0;
37316 case 1:
37317 // op: ZAn
37318 return 6;
37319 case 4:
37320 // op: imm
37321 return 5;
37322 }
37323 break;
37324 }
37325 case AArch64::MOVAZ_ZMI_H_S:
37326 case AArch64::MOVAZ_ZMI_V_S: {
37327 switch (OpNum) {
37328 case 3:
37329 // op: Rs
37330 return 13;
37331 case 0:
37332 // op: Zd
37333 return 0;
37334 case 1:
37335 // op: ZAn
37336 return 7;
37337 case 4:
37338 // op: imm
37339 return 5;
37340 }
37341 break;
37342 }
37343 case AArch64::MOVAZ_ZMI_H_H:
37344 case AArch64::MOVAZ_ZMI_V_H: {
37345 switch (OpNum) {
37346 case 3:
37347 // op: Rs
37348 return 13;
37349 case 0:
37350 // op: Zd
37351 return 0;
37352 case 1:
37353 // op: ZAn
37354 return 8;
37355 case 4:
37356 // op: imm
37357 return 5;
37358 }
37359 break;
37360 }
37361 case AArch64::MOVAZ_ZMI_H_B:
37362 case AArch64::MOVAZ_ZMI_V_B: {
37363 switch (OpNum) {
37364 case 3:
37365 // op: Rs
37366 return 13;
37367 case 0:
37368 // op: Zd
37369 return 0;
37370 case 4:
37371 // op: imm
37372 return 5;
37373 }
37374 break;
37375 }
37376 case AArch64::MOVAZ_VG2_2ZMXI: {
37377 switch (OpNum) {
37378 case 3:
37379 // op: Rs
37380 return 13;
37381 case 4:
37382 // op: imm
37383 return 5;
37384 case 0:
37385 // op: Zd
37386 return 1;
37387 }
37388 break;
37389 }
37390 case AArch64::MOVAZ_VG4_4ZMXI: {
37391 switch (OpNum) {
37392 case 3:
37393 // op: Rs
37394 return 13;
37395 case 4:
37396 // op: imm
37397 return 5;
37398 case 0:
37399 // op: Zd
37400 return 2;
37401 }
37402 break;
37403 }
37404 case AArch64::RCWCLRP:
37405 case AArch64::RCWCLRPA:
37406 case AArch64::RCWCLRPAL:
37407 case AArch64::RCWCLRPL:
37408 case AArch64::RCWCLRSP:
37409 case AArch64::RCWCLRSPA:
37410 case AArch64::RCWCLRSPAL:
37411 case AArch64::RCWCLRSPL:
37412 case AArch64::RCWSETP:
37413 case AArch64::RCWSETPA:
37414 case AArch64::RCWSETPAL:
37415 case AArch64::RCWSETPL:
37416 case AArch64::RCWSETSP:
37417 case AArch64::RCWSETSPA:
37418 case AArch64::RCWSETSPAL:
37419 case AArch64::RCWSETSPL:
37420 case AArch64::RCWSWPP:
37421 case AArch64::RCWSWPPA:
37422 case AArch64::RCWSWPPAL:
37423 case AArch64::RCWSWPPL:
37424 case AArch64::RCWSWPSP:
37425 case AArch64::RCWSWPSPA:
37426 case AArch64::RCWSWPSPAL:
37427 case AArch64::RCWSWPSPL: {
37428 switch (OpNum) {
37429 case 3:
37430 // op: Rt2
37431 return 16;
37432 case 4:
37433 // op: Rn
37434 return 5;
37435 case 2:
37436 // op: Rt
37437 return 0;
37438 }
37439 break;
37440 }
37441 case AArch64::PSEL_PPPRI_B: {
37442 switch (OpNum) {
37443 case 3:
37444 // op: Rv
37445 return 16;
37446 case 1:
37447 // op: Pn
37448 return 10;
37449 case 2:
37450 // op: Pm
37451 return 5;
37452 case 0:
37453 // op: Pd
37454 return 0;
37455 case 4:
37456 // op: imm
37457 return 19;
37458 }
37459 break;
37460 }
37461 case AArch64::PSEL_PPPRI_H: {
37462 switch (OpNum) {
37463 case 3:
37464 // op: Rv
37465 return 16;
37466 case 1:
37467 // op: Pn
37468 return 10;
37469 case 2:
37470 // op: Pm
37471 return 5;
37472 case 0:
37473 // op: Pd
37474 return 0;
37475 case 4:
37476 // op: imm
37477 return 20;
37478 }
37479 break;
37480 }
37481 case AArch64::PSEL_PPPRI_S: {
37482 switch (OpNum) {
37483 case 3:
37484 // op: Rv
37485 return 16;
37486 case 1:
37487 // op: Pn
37488 return 10;
37489 case 2:
37490 // op: Pm
37491 return 5;
37492 case 0:
37493 // op: Pd
37494 return 0;
37495 case 4:
37496 // op: imm
37497 return 22;
37498 }
37499 break;
37500 }
37501 case AArch64::PSEL_PPPRI_D: {
37502 switch (OpNum) {
37503 case 3:
37504 // op: Rv
37505 return 16;
37506 case 1:
37507 // op: Pn
37508 return 10;
37509 case 2:
37510 // op: Pm
37511 return 5;
37512 case 0:
37513 // op: Pd
37514 return 0;
37515 case 4:
37516 // op: imm
37517 return 23;
37518 }
37519 break;
37520 }
37521 case AArch64::BFCLAMP_ZZZ:
37522 case AArch64::FCLAMP_ZZZ_D:
37523 case AArch64::FCLAMP_ZZZ_H:
37524 case AArch64::FCLAMP_ZZZ_S:
37525 case AArch64::SCLAMP_ZZZ_B:
37526 case AArch64::SCLAMP_ZZZ_D:
37527 case AArch64::SCLAMP_ZZZ_H:
37528 case AArch64::SCLAMP_ZZZ_S:
37529 case AArch64::UCLAMP_ZZZ_B:
37530 case AArch64::UCLAMP_ZZZ_D:
37531 case AArch64::UCLAMP_ZZZ_H:
37532 case AArch64::UCLAMP_ZZZ_S: {
37533 switch (OpNum) {
37534 case 3:
37535 // op: Zm
37536 return 16;
37537 case 2:
37538 // op: Zn
37539 return 5;
37540 case 0:
37541 // op: Zd
37542 return 0;
37543 }
37544 break;
37545 }
37546 case AArch64::BFCLAMP_VG2_2ZZZ_H:
37547 case AArch64::FCLAMP_VG2_2Z2Z_D:
37548 case AArch64::FCLAMP_VG2_2Z2Z_H:
37549 case AArch64::FCLAMP_VG2_2Z2Z_S:
37550 case AArch64::SCLAMP_VG2_2Z2Z_B:
37551 case AArch64::SCLAMP_VG2_2Z2Z_D:
37552 case AArch64::SCLAMP_VG2_2Z2Z_H:
37553 case AArch64::SCLAMP_VG2_2Z2Z_S:
37554 case AArch64::UCLAMP_VG2_2Z2Z_B:
37555 case AArch64::UCLAMP_VG2_2Z2Z_D:
37556 case AArch64::UCLAMP_VG2_2Z2Z_H:
37557 case AArch64::UCLAMP_VG2_2Z2Z_S: {
37558 switch (OpNum) {
37559 case 3:
37560 // op: Zm
37561 return 16;
37562 case 2:
37563 // op: Zn
37564 return 5;
37565 case 0:
37566 // op: Zd
37567 return 1;
37568 }
37569 break;
37570 }
37571 case AArch64::BFCLAMP_VG4_4ZZZ_H:
37572 case AArch64::FCLAMP_VG4_4Z4Z_D:
37573 case AArch64::FCLAMP_VG4_4Z4Z_H:
37574 case AArch64::FCLAMP_VG4_4Z4Z_S:
37575 case AArch64::SCLAMP_VG4_4Z4Z_B:
37576 case AArch64::SCLAMP_VG4_4Z4Z_D:
37577 case AArch64::SCLAMP_VG4_4Z4Z_H:
37578 case AArch64::SCLAMP_VG4_4Z4Z_S:
37579 case AArch64::UCLAMP_VG4_4Z4Z_B:
37580 case AArch64::UCLAMP_VG4_4Z4Z_D:
37581 case AArch64::UCLAMP_VG4_4Z4Z_H:
37582 case AArch64::UCLAMP_VG4_4Z4Z_S: {
37583 switch (OpNum) {
37584 case 3:
37585 // op: Zm
37586 return 16;
37587 case 2:
37588 // op: Zn
37589 return 5;
37590 case 0:
37591 // op: Zd
37592 return 2;
37593 }
37594 break;
37595 }
37596 case AArch64::PMLAL_2ZZZ_Q: {
37597 switch (OpNum) {
37598 case 3:
37599 // op: Zm
37600 return 16;
37601 case 2:
37602 // op: Zn
37603 return 5;
37604 case 0:
37605 // op: Zda
37606 return 1;
37607 }
37608 break;
37609 }
37610 case AArch64::LD1B_2Z_STRIDED_IMM:
37611 case AArch64::LD1B_4Z_STRIDED_IMM:
37612 case AArch64::LD1D_2Z_STRIDED_IMM:
37613 case AArch64::LD1D_4Z_STRIDED_IMM:
37614 case AArch64::LD1H_2Z_STRIDED_IMM:
37615 case AArch64::LD1H_4Z_STRIDED_IMM:
37616 case AArch64::LD1W_2Z_STRIDED_IMM:
37617 case AArch64::LD1W_4Z_STRIDED_IMM:
37618 case AArch64::LDNT1B_2Z_STRIDED_IMM:
37619 case AArch64::LDNT1B_4Z_STRIDED_IMM:
37620 case AArch64::LDNT1D_2Z_STRIDED_IMM:
37621 case AArch64::LDNT1D_4Z_STRIDED_IMM:
37622 case AArch64::LDNT1H_2Z_STRIDED_IMM:
37623 case AArch64::LDNT1H_4Z_STRIDED_IMM:
37624 case AArch64::LDNT1W_2Z_STRIDED_IMM:
37625 case AArch64::LDNT1W_4Z_STRIDED_IMM:
37626 case AArch64::ST1B_2Z_STRIDED_IMM:
37627 case AArch64::ST1B_4Z_STRIDED_IMM:
37628 case AArch64::ST1D_2Z_STRIDED_IMM:
37629 case AArch64::ST1D_4Z_STRIDED_IMM:
37630 case AArch64::ST1H_2Z_STRIDED_IMM:
37631 case AArch64::ST1H_4Z_STRIDED_IMM:
37632 case AArch64::ST1W_2Z_STRIDED_IMM:
37633 case AArch64::ST1W_4Z_STRIDED_IMM:
37634 case AArch64::STNT1B_2Z_STRIDED_IMM:
37635 case AArch64::STNT1B_4Z_STRIDED_IMM:
37636 case AArch64::STNT1D_2Z_STRIDED_IMM:
37637 case AArch64::STNT1D_4Z_STRIDED_IMM:
37638 case AArch64::STNT1H_2Z_STRIDED_IMM:
37639 case AArch64::STNT1H_4Z_STRIDED_IMM:
37640 case AArch64::STNT1W_2Z_STRIDED_IMM:
37641 case AArch64::STNT1W_4Z_STRIDED_IMM: {
37642 switch (OpNum) {
37643 case 3:
37644 // op: imm4
37645 return 16;
37646 case 1:
37647 // op: PNg
37648 return 10;
37649 case 2:
37650 // op: Rn
37651 return 5;
37652 case 0:
37653 // op: Zt
37654 return 0;
37655 }
37656 break;
37657 }
37658 case AArch64::LDRAAwriteback:
37659 case AArch64::LDRABwriteback: {
37660 switch (OpNum) {
37661 case 3:
37662 // op: offset
37663 return 12;
37664 case 2:
37665 // op: Rn
37666 return 5;
37667 case 1:
37668 // op: Rt
37669 return 0;
37670 }
37671 break;
37672 }
37673 case AArch64::SYSPxt:
37674 case AArch64::SYSxt: {
37675 switch (OpNum) {
37676 case 4:
37677 // op: Rt
37678 return 0;
37679 case 0:
37680 // op: op1
37681 return 16;
37682 case 1:
37683 // op: Cn
37684 return 12;
37685 case 2:
37686 // op: Cm
37687 return 8;
37688 case 3:
37689 // op: op2
37690 return 5;
37691 }
37692 break;
37693 }
37694 case AArch64::EXTRACT_ZPMXI_H_Q:
37695 case AArch64::EXTRACT_ZPMXI_V_Q: {
37696 switch (OpNum) {
37697 case 4:
37698 // op: Rv
37699 return 13;
37700 case 2:
37701 // op: Pg
37702 return 10;
37703 case 0:
37704 // op: Zd
37705 return 0;
37706 case 3:
37707 // op: ZAn
37708 return 5;
37709 }
37710 break;
37711 }
37712 case AArch64::EXTRACT_ZPMXI_H_D:
37713 case AArch64::EXTRACT_ZPMXI_V_D: {
37714 switch (OpNum) {
37715 case 4:
37716 // op: Rv
37717 return 13;
37718 case 2:
37719 // op: Pg
37720 return 10;
37721 case 0:
37722 // op: Zd
37723 return 0;
37724 case 3:
37725 // op: ZAn
37726 return 6;
37727 case 5:
37728 // op: imm
37729 return 5;
37730 }
37731 break;
37732 }
37733 case AArch64::EXTRACT_ZPMXI_H_S:
37734 case AArch64::EXTRACT_ZPMXI_V_S: {
37735 switch (OpNum) {
37736 case 4:
37737 // op: Rv
37738 return 13;
37739 case 2:
37740 // op: Pg
37741 return 10;
37742 case 0:
37743 // op: Zd
37744 return 0;
37745 case 3:
37746 // op: ZAn
37747 return 7;
37748 case 5:
37749 // op: imm
37750 return 5;
37751 }
37752 break;
37753 }
37754 case AArch64::EXTRACT_ZPMXI_H_H:
37755 case AArch64::EXTRACT_ZPMXI_V_H: {
37756 switch (OpNum) {
37757 case 4:
37758 // op: Rv
37759 return 13;
37760 case 2:
37761 // op: Pg
37762 return 10;
37763 case 0:
37764 // op: Zd
37765 return 0;
37766 case 3:
37767 // op: ZAn
37768 return 8;
37769 case 5:
37770 // op: imm
37771 return 5;
37772 }
37773 break;
37774 }
37775 case AArch64::EXTRACT_ZPMXI_H_B:
37776 case AArch64::EXTRACT_ZPMXI_V_B: {
37777 switch (OpNum) {
37778 case 4:
37779 // op: Rv
37780 return 13;
37781 case 2:
37782 // op: Pg
37783 return 10;
37784 case 0:
37785 // op: Zd
37786 return 0;
37787 case 5:
37788 // op: imm
37789 return 5;
37790 }
37791 break;
37792 }
37793 case AArch64::LD1_MXIPXX_H_Q:
37794 case AArch64::LD1_MXIPXX_V_Q:
37795 case AArch64::ST1_MXIPXX_H_Q:
37796 case AArch64::ST1_MXIPXX_V_Q: {
37797 switch (OpNum) {
37798 case 5:
37799 // op: Rm
37800 return 16;
37801 case 1:
37802 // op: Rv
37803 return 13;
37804 case 3:
37805 // op: Pg
37806 return 10;
37807 case 4:
37808 // op: Rn
37809 return 5;
37810 case 0:
37811 // op: ZAt
37812 return 0;
37813 }
37814 break;
37815 }
37816 case AArch64::LD1_MXIPXX_H_D:
37817 case AArch64::LD1_MXIPXX_V_D:
37818 case AArch64::ST1_MXIPXX_H_D:
37819 case AArch64::ST1_MXIPXX_V_D: {
37820 switch (OpNum) {
37821 case 5:
37822 // op: Rm
37823 return 16;
37824 case 1:
37825 // op: Rv
37826 return 13;
37827 case 3:
37828 // op: Pg
37829 return 10;
37830 case 4:
37831 // op: Rn
37832 return 5;
37833 case 0:
37834 // op: ZAt
37835 return 1;
37836 case 2:
37837 // op: imm
37838 return 0;
37839 }
37840 break;
37841 }
37842 case AArch64::LD1_MXIPXX_H_S:
37843 case AArch64::LD1_MXIPXX_V_S:
37844 case AArch64::ST1_MXIPXX_H_S:
37845 case AArch64::ST1_MXIPXX_V_S: {
37846 switch (OpNum) {
37847 case 5:
37848 // op: Rm
37849 return 16;
37850 case 1:
37851 // op: Rv
37852 return 13;
37853 case 3:
37854 // op: Pg
37855 return 10;
37856 case 4:
37857 // op: Rn
37858 return 5;
37859 case 0:
37860 // op: ZAt
37861 return 2;
37862 case 2:
37863 // op: imm
37864 return 0;
37865 }
37866 break;
37867 }
37868 case AArch64::LD1_MXIPXX_H_H:
37869 case AArch64::LD1_MXIPXX_V_H:
37870 case AArch64::ST1_MXIPXX_H_H:
37871 case AArch64::ST1_MXIPXX_V_H: {
37872 switch (OpNum) {
37873 case 5:
37874 // op: Rm
37875 return 16;
37876 case 1:
37877 // op: Rv
37878 return 13;
37879 case 3:
37880 // op: Pg
37881 return 10;
37882 case 4:
37883 // op: Rn
37884 return 5;
37885 case 0:
37886 // op: ZAt
37887 return 3;
37888 case 2:
37889 // op: imm
37890 return 0;
37891 }
37892 break;
37893 }
37894 case AArch64::LD1_MXIPXX_H_B:
37895 case AArch64::LD1_MXIPXX_V_B:
37896 case AArch64::ST1_MXIPXX_H_B:
37897 case AArch64::ST1_MXIPXX_V_B: {
37898 switch (OpNum) {
37899 case 5:
37900 // op: Rm
37901 return 16;
37902 case 1:
37903 // op: Rv
37904 return 13;
37905 case 3:
37906 // op: Pg
37907 return 10;
37908 case 4:
37909 // op: Rn
37910 return 5;
37911 case 2:
37912 // op: imm
37913 return 0;
37914 }
37915 break;
37916 }
37917 case AArch64::FMLALL_MZZ_BtoS:
37918 case AArch64::FMLALL_VG2_M2ZZ_BtoS:
37919 case AArch64::FMLALL_VG4_M4ZZ_BtoS:
37920 case AArch64::SMLALL_MZZ_BtoS:
37921 case AArch64::SMLALL_MZZ_HtoD:
37922 case AArch64::SMLALL_VG2_M2ZZ_BtoS:
37923 case AArch64::SMLALL_VG2_M2ZZ_HtoD:
37924 case AArch64::SMLALL_VG4_M4ZZ_BtoS:
37925 case AArch64::SMLALL_VG4_M4ZZ_HtoD:
37926 case AArch64::SMLSLL_MZZ_BtoS:
37927 case AArch64::SMLSLL_MZZ_HtoD:
37928 case AArch64::SMLSLL_VG2_M2ZZ_BtoS:
37929 case AArch64::SMLSLL_VG2_M2ZZ_HtoD:
37930 case AArch64::SMLSLL_VG4_M4ZZ_BtoS:
37931 case AArch64::SMLSLL_VG4_M4ZZ_HtoD:
37932 case AArch64::SUMLALL_VG2_M2ZZ_BtoS:
37933 case AArch64::SUMLALL_VG4_M4ZZ_BtoS:
37934 case AArch64::UMLALL_MZZ_BtoS:
37935 case AArch64::UMLALL_MZZ_HtoD:
37936 case AArch64::UMLALL_VG2_M2ZZ_BtoS:
37937 case AArch64::UMLALL_VG2_M2ZZ_HtoD:
37938 case AArch64::UMLALL_VG4_M4ZZ_BtoS:
37939 case AArch64::UMLALL_VG4_M4ZZ_HtoD:
37940 case AArch64::UMLSLL_MZZ_BtoS:
37941 case AArch64::UMLSLL_MZZ_HtoD:
37942 case AArch64::UMLSLL_VG2_M2ZZ_BtoS:
37943 case AArch64::UMLSLL_VG2_M2ZZ_HtoD:
37944 case AArch64::UMLSLL_VG4_M4ZZ_BtoS:
37945 case AArch64::UMLSLL_VG4_M4ZZ_HtoD:
37946 case AArch64::USMLALL_MZZ_BtoS:
37947 case AArch64::USMLALL_VG2_M2ZZ_BtoS:
37948 case AArch64::USMLALL_VG4_M4ZZ_BtoS: {
37949 switch (OpNum) {
37950 case 5:
37951 // op: Zm
37952 return 16;
37953 case 2:
37954 // op: Rv
37955 return 13;
37956 case 4:
37957 // op: Zn
37958 return 5;
37959 case 3:
37960 // op: imm
37961 return 0;
37962 }
37963 break;
37964 }
37965 case AArch64::BFDOT_VG2_M2ZZI_HtoS:
37966 case AArch64::BFVDOT_VG2_M2ZZI_HtoS:
37967 case AArch64::FDOT_VG2_M2ZZI_BtoS:
37968 case AArch64::FDOT_VG2_M2ZZI_HtoS:
37969 case AArch64::FMLA_VG2_M2ZZI_S:
37970 case AArch64::FMLS_VG2_M2ZZI_S:
37971 case AArch64::FVDOT_VG2_M2ZZI_HtoS:
37972 case AArch64::SDOT_VG2_M2ZZI_BToS:
37973 case AArch64::SDOT_VG2_M2ZZI_HToS:
37974 case AArch64::SUDOT_VG2_M2ZZI_BToS:
37975 case AArch64::SVDOT_VG2_M2ZZI_HtoS:
37976 case AArch64::UDOT_VG2_M2ZZI_BToS:
37977 case AArch64::UDOT_VG2_M2ZZI_HToS:
37978 case AArch64::USDOT_VG2_M2ZZI_BToS:
37979 case AArch64::UVDOT_VG2_M2ZZI_HtoS: {
37980 switch (OpNum) {
37981 case 5:
37982 // op: Zm
37983 return 16;
37984 case 2:
37985 // op: Rv
37986 return 13;
37987 case 4:
37988 // op: Zn
37989 return 6;
37990 case 3:
37991 // op: imm3
37992 return 0;
37993 case 6:
37994 // op: i
37995 return 10;
37996 }
37997 break;
37998 }
37999 case AArch64::BFMLA_VG2_M2ZZI:
38000 case AArch64::BFMLS_VG2_M2ZZI:
38001 case AArch64::FDOT_VG2_M2ZZI_BtoH:
38002 case AArch64::FMLA_VG2_M2ZZI_H:
38003 case AArch64::FMLS_VG2_M2ZZI_H:
38004 case AArch64::FVDOTB_VG4_M2ZZI_BtoS:
38005 case AArch64::FVDOTT_VG4_M2ZZI_BtoS:
38006 case AArch64::FVDOT_VG2_M2ZZI_BtoH: {
38007 switch (OpNum) {
38008 case 5:
38009 // op: Zm
38010 return 16;
38011 case 2:
38012 // op: Rv
38013 return 13;
38014 case 4:
38015 // op: Zn
38016 return 6;
38017 case 3:
38018 // op: imm3
38019 return 0;
38020 case 6:
38021 // op: i
38022 return 3;
38023 }
38024 break;
38025 }
38026 case AArch64::BFDOT_VG4_M4ZZI_HtoS:
38027 case AArch64::FDOT_VG4_M4ZZI_BtoS:
38028 case AArch64::FDOT_VG4_M4ZZI_HtoS:
38029 case AArch64::FMLA_VG4_M4ZZI_S:
38030 case AArch64::FMLS_VG4_M4ZZI_S:
38031 case AArch64::SDOT_VG4_M4ZZI_BToS:
38032 case AArch64::SDOT_VG4_M4ZZI_HToS:
38033 case AArch64::SUDOT_VG4_M4ZZI_BToS:
38034 case AArch64::SUVDOT_VG4_M4ZZI_BToS:
38035 case AArch64::SVDOT_VG4_M4ZZI_BtoS:
38036 case AArch64::UDOT_VG4_M4ZZI_BtoS:
38037 case AArch64::UDOT_VG4_M4ZZI_HToS:
38038 case AArch64::USDOT_VG4_M4ZZI_BToS:
38039 case AArch64::USVDOT_VG4_M4ZZI_BToS:
38040 case AArch64::UVDOT_VG4_M4ZZI_BtoS: {
38041 switch (OpNum) {
38042 case 5:
38043 // op: Zm
38044 return 16;
38045 case 2:
38046 // op: Rv
38047 return 13;
38048 case 4:
38049 // op: Zn
38050 return 7;
38051 case 3:
38052 // op: imm3
38053 return 0;
38054 case 6:
38055 // op: i
38056 return 10;
38057 }
38058 break;
38059 }
38060 case AArch64::BFMLA_VG4_M4ZZI:
38061 case AArch64::BFMLS_VG4_M4ZZI:
38062 case AArch64::FDOT_VG4_M4ZZI_BtoH:
38063 case AArch64::FMLA_VG4_M4ZZI_H:
38064 case AArch64::FMLS_VG4_M4ZZI_H: {
38065 switch (OpNum) {
38066 case 5:
38067 // op: Zm
38068 return 16;
38069 case 2:
38070 // op: Rv
38071 return 13;
38072 case 4:
38073 // op: Zn
38074 return 7;
38075 case 3:
38076 // op: imm3
38077 return 0;
38078 case 6:
38079 // op: i
38080 return 3;
38081 }
38082 break;
38083 }
38084 case AArch64::FMLALL_MZZI_BtoS:
38085 case AArch64::SMLALL_MZZI_BtoS:
38086 case AArch64::SMLALL_MZZI_HtoD:
38087 case AArch64::SMLSLL_MZZI_BtoS:
38088 case AArch64::SMLSLL_MZZI_HtoD:
38089 case AArch64::SUMLALL_MZZI_BtoS:
38090 case AArch64::UMLALL_MZZI_BtoS:
38091 case AArch64::UMLALL_MZZI_HtoD:
38092 case AArch64::UMLSLL_MZZI_BtoS:
38093 case AArch64::UMLSLL_MZZI_HtoD:
38094 case AArch64::USMLALL_MZZI_BtoS: {
38095 switch (OpNum) {
38096 case 5:
38097 // op: Zm
38098 return 16;
38099 case 2:
38100 // op: Rv
38101 return 13;
38102 case 6:
38103 // op: i
38104 return 10;
38105 case 4:
38106 // op: Zn
38107 return 5;
38108 case 3:
38109 // op: imm2
38110 return 0;
38111 }
38112 break;
38113 }
38114 case AArch64::FMLALL_VG2_M2ZZI_BtoS:
38115 case AArch64::SMLALL_VG2_M2ZZI_BtoS:
38116 case AArch64::SMLALL_VG2_M2ZZI_HtoD:
38117 case AArch64::SMLSLL_VG2_M2ZZI_BtoS:
38118 case AArch64::SMLSLL_VG2_M2ZZI_HtoD:
38119 case AArch64::SUMLALL_VG2_M2ZZI_BtoS:
38120 case AArch64::UMLALL_VG2_M2ZZI_BtoS:
38121 case AArch64::UMLALL_VG2_M2ZZI_HtoD:
38122 case AArch64::UMLSLL_VG2_M2ZZI_BtoS:
38123 case AArch64::UMLSLL_VG2_M2ZZI_HtoD:
38124 case AArch64::USMLALL_VG2_M2ZZI_BtoS: {
38125 switch (OpNum) {
38126 case 5:
38127 // op: Zm
38128 return 16;
38129 case 2:
38130 // op: Rv
38131 return 13;
38132 case 6:
38133 // op: i
38134 return 1;
38135 case 3:
38136 // op: imm
38137 return 0;
38138 case 4:
38139 // op: Zn
38140 return 6;
38141 }
38142 break;
38143 }
38144 case AArch64::FMLALL_VG4_M4ZZI_BtoS:
38145 case AArch64::SMLALL_VG4_M4ZZI_BtoS:
38146 case AArch64::SMLALL_VG4_M4ZZI_HtoD:
38147 case AArch64::SMLSLL_VG4_M4ZZI_BtoS:
38148 case AArch64::SMLSLL_VG4_M4ZZI_HtoD:
38149 case AArch64::SUMLALL_VG4_M4ZZI_BtoS:
38150 case AArch64::UMLALL_VG4_M4ZZI_BtoS:
38151 case AArch64::UMLALL_VG4_M4ZZI_HtoD:
38152 case AArch64::UMLSLL_VG4_M4ZZI_BtoS:
38153 case AArch64::UMLSLL_VG4_M4ZZI_HtoD:
38154 case AArch64::USMLALL_VG4_M4ZZI_BtoS: {
38155 switch (OpNum) {
38156 case 5:
38157 // op: Zm
38158 return 16;
38159 case 2:
38160 // op: Rv
38161 return 13;
38162 case 6:
38163 // op: i
38164 return 1;
38165 case 3:
38166 // op: imm
38167 return 0;
38168 case 4:
38169 // op: Zn
38170 return 7;
38171 }
38172 break;
38173 }
38174 case AArch64::FMLAL_VG2_M2ZZI_BtoH: {
38175 switch (OpNum) {
38176 case 5:
38177 // op: Zm
38178 return 16;
38179 case 2:
38180 // op: Rv
38181 return 13;
38182 case 6:
38183 // op: i
38184 return 2;
38185 case 3:
38186 // op: imm2
38187 return 0;
38188 case 4:
38189 // op: Zn
38190 return 6;
38191 }
38192 break;
38193 }
38194 case AArch64::FMLAL_VG4_M4ZZI_BtoH: {
38195 switch (OpNum) {
38196 case 5:
38197 // op: Zm
38198 return 16;
38199 case 2:
38200 // op: Rv
38201 return 13;
38202 case 6:
38203 // op: i
38204 return 2;
38205 case 3:
38206 // op: imm2
38207 return 0;
38208 case 4:
38209 // op: Zn
38210 return 7;
38211 }
38212 break;
38213 }
38214 case AArch64::FMLAL_MZZI_BtoH: {
38215 switch (OpNum) {
38216 case 5:
38217 // op: Zm
38218 return 16;
38219 case 2:
38220 // op: Rv
38221 return 13;
38222 case 6:
38223 // op: i
38224 return 3;
38225 case 4:
38226 // op: Zn
38227 return 5;
38228 case 3:
38229 // op: imm3
38230 return 0;
38231 }
38232 break;
38233 }
38234 case AArch64::FMLA_VG2_M2ZZI_D:
38235 case AArch64::FMLS_VG2_M2ZZI_D:
38236 case AArch64::SDOT_VG2_M2ZZI_HtoD:
38237 case AArch64::UDOT_VG2_M2ZZI_HtoD: {
38238 switch (OpNum) {
38239 case 5:
38240 // op: Zm
38241 return 16;
38242 case 2:
38243 // op: Rv
38244 return 13;
38245 case 6:
38246 // op: i1
38247 return 10;
38248 case 4:
38249 // op: Zn
38250 return 6;
38251 case 3:
38252 // op: imm3
38253 return 0;
38254 }
38255 break;
38256 }
38257 case AArch64::FMLA_VG4_M4ZZI_D:
38258 case AArch64::FMLS_VG4_M4ZZI_D:
38259 case AArch64::SDOT_VG4_M4ZZI_HtoD:
38260 case AArch64::SVDOT_VG4_M4ZZI_HtoD:
38261 case AArch64::UDOT_VG4_M4ZZI_HtoD:
38262 case AArch64::UVDOT_VG4_M4ZZI_HtoD: {
38263 switch (OpNum) {
38264 case 5:
38265 // op: Zm
38266 return 16;
38267 case 2:
38268 // op: Rv
38269 return 13;
38270 case 6:
38271 // op: i1
38272 return 10;
38273 case 4:
38274 // op: Zn
38275 return 7;
38276 case 3:
38277 // op: imm3
38278 return 0;
38279 }
38280 break;
38281 }
38282 case AArch64::BFMLAL_MZZI_HtoS:
38283 case AArch64::BFMLSL_MZZI_HtoS:
38284 case AArch64::FMLAL_MZZI_HtoS:
38285 case AArch64::FMLSL_MZZI_HtoS:
38286 case AArch64::SMLAL_MZZI_HtoS:
38287 case AArch64::SMLSL_MZZI_HtoS:
38288 case AArch64::UMLAL_MZZI_HtoS:
38289 case AArch64::UMLSL_MZZI_HtoS: {
38290 switch (OpNum) {
38291 case 5:
38292 // op: Zm
38293 return 16;
38294 case 2:
38295 // op: Rv
38296 return 13;
38297 case 6:
38298 // op: i3
38299 return 10;
38300 case 4:
38301 // op: Zn
38302 return 5;
38303 case 3:
38304 // op: imm
38305 return 0;
38306 }
38307 break;
38308 }
38309 case AArch64::BFMLAL_VG2_M2ZZI_HtoS:
38310 case AArch64::BFMLSL_VG2_M2ZZI_HtoS:
38311 case AArch64::FMLAL_VG2_M2ZZI_HtoS:
38312 case AArch64::FMLSL_VG2_M2ZZI_HtoS:
38313 case AArch64::SMLAL_VG2_M2ZZI_S:
38314 case AArch64::SMLSL_VG2_M2ZZI_S:
38315 case AArch64::UMLAL_VG2_M2ZZI_S:
38316 case AArch64::UMLSL_VG2_M2ZZI_S: {
38317 switch (OpNum) {
38318 case 5:
38319 // op: Zm
38320 return 16;
38321 case 2:
38322 // op: Rv
38323 return 13;
38324 case 6:
38325 // op: i3
38326 return 2;
38327 case 4:
38328 // op: Zn
38329 return 6;
38330 case 3:
38331 // op: imm
38332 return 0;
38333 }
38334 break;
38335 }
38336 case AArch64::BFMLAL_VG4_M4ZZI_HtoS:
38337 case AArch64::BFMLSL_VG4_M4ZZI_HtoS:
38338 case AArch64::FMLAL_VG4_M4ZZI_HtoS:
38339 case AArch64::FMLSL_VG4_M4ZZI_HtoS:
38340 case AArch64::SMLAL_VG4_M4ZZI_HtoS:
38341 case AArch64::SMLSL_VG4_M4ZZI_HtoS:
38342 case AArch64::UMLAL_VG4_M4ZZI_HtoS:
38343 case AArch64::UMLSL_VG4_M4ZZI_HtoS: {
38344 switch (OpNum) {
38345 case 5:
38346 // op: Zm
38347 return 16;
38348 case 2:
38349 // op: Rv
38350 return 13;
38351 case 6:
38352 // op: i3
38353 return 2;
38354 case 4:
38355 // op: Zn
38356 return 7;
38357 case 3:
38358 // op: imm
38359 return 0;
38360 }
38361 break;
38362 }
38363 case AArch64::BFMOPA_MPPZZ:
38364 case AArch64::BFMOPA_MPPZZ_H:
38365 case AArch64::BFMOPS_MPPZZ:
38366 case AArch64::BFMOPS_MPPZZ_H:
38367 case AArch64::BMOPA_MPPZZ_S:
38368 case AArch64::BMOPS_MPPZZ_S:
38369 case AArch64::FMOPAL_MPPZZ:
38370 case AArch64::FMOPA_MPPZZ_BtoH:
38371 case AArch64::FMOPA_MPPZZ_BtoS:
38372 case AArch64::FMOPA_MPPZZ_D:
38373 case AArch64::FMOPA_MPPZZ_H:
38374 case AArch64::FMOPA_MPPZZ_S:
38375 case AArch64::FMOPSL_MPPZZ:
38376 case AArch64::FMOPS_MPPZZ_D:
38377 case AArch64::FMOPS_MPPZZ_H:
38378 case AArch64::FMOPS_MPPZZ_S:
38379 case AArch64::SMOPA_MPPZZ_D:
38380 case AArch64::SMOPA_MPPZZ_HtoS:
38381 case AArch64::SMOPA_MPPZZ_S:
38382 case AArch64::SMOPS_MPPZZ_D:
38383 case AArch64::SMOPS_MPPZZ_HtoS:
38384 case AArch64::SMOPS_MPPZZ_S:
38385 case AArch64::SUMOPA_MPPZZ_D:
38386 case AArch64::SUMOPA_MPPZZ_S:
38387 case AArch64::SUMOPS_MPPZZ_D:
38388 case AArch64::SUMOPS_MPPZZ_S:
38389 case AArch64::UMOPA_MPPZZ_D:
38390 case AArch64::UMOPA_MPPZZ_HtoS:
38391 case AArch64::UMOPA_MPPZZ_S:
38392 case AArch64::UMOPS_MPPZZ_D:
38393 case AArch64::UMOPS_MPPZZ_HtoS:
38394 case AArch64::UMOPS_MPPZZ_S:
38395 case AArch64::USMOPA_MPPZZ_D:
38396 case AArch64::USMOPA_MPPZZ_S:
38397 case AArch64::USMOPS_MPPZZ_D:
38398 case AArch64::USMOPS_MPPZZ_S: {
38399 switch (OpNum) {
38400 case 5:
38401 // op: Zm
38402 return 16;
38403 case 3:
38404 // op: Pm
38405 return 13;
38406 case 2:
38407 // op: Pn
38408 return 10;
38409 case 4:
38410 // op: Zn
38411 return 5;
38412 case 0:
38413 // op: ZAda
38414 return 0;
38415 }
38416 break;
38417 }
38418 case AArch64::ADD_VG2_M2ZZ_D:
38419 case AArch64::ADD_VG2_M2ZZ_S:
38420 case AArch64::ADD_VG4_M4ZZ_D:
38421 case AArch64::ADD_VG4_M4ZZ_S:
38422 case AArch64::BFDOT_VG2_M2ZZ_HtoS:
38423 case AArch64::BFDOT_VG4_M4ZZ_HtoS:
38424 case AArch64::BFMLA_VG2_M2ZZ:
38425 case AArch64::BFMLA_VG4_M4ZZ:
38426 case AArch64::BFMLS_VG2_M2ZZ:
38427 case AArch64::BFMLS_VG4_M4ZZ:
38428 case AArch64::FDOT_VG2_M2ZZ_BtoH:
38429 case AArch64::FDOT_VG2_M2ZZ_BtoS:
38430 case AArch64::FDOT_VG2_M2ZZ_HtoS:
38431 case AArch64::FDOT_VG4_M4ZZ_BtoH:
38432 case AArch64::FDOT_VG4_M4ZZ_BtoS:
38433 case AArch64::FDOT_VG4_M4ZZ_HtoS:
38434 case AArch64::FMLA_VG2_M2ZZ_D:
38435 case AArch64::FMLA_VG2_M2ZZ_H:
38436 case AArch64::FMLA_VG2_M2ZZ_S:
38437 case AArch64::FMLA_VG4_M4ZZ_D:
38438 case AArch64::FMLA_VG4_M4ZZ_H:
38439 case AArch64::FMLA_VG4_M4ZZ_S:
38440 case AArch64::FMLS_VG2_M2ZZ_D:
38441 case AArch64::FMLS_VG2_M2ZZ_H:
38442 case AArch64::FMLS_VG2_M2ZZ_S:
38443 case AArch64::FMLS_VG4_M4ZZ_D:
38444 case AArch64::FMLS_VG4_M4ZZ_H:
38445 case AArch64::FMLS_VG4_M4ZZ_S:
38446 case AArch64::SDOT_VG2_M2ZZ_BtoS:
38447 case AArch64::SDOT_VG2_M2ZZ_HtoD:
38448 case AArch64::SDOT_VG2_M2ZZ_HtoS:
38449 case AArch64::SDOT_VG4_M4ZZ_BtoS:
38450 case AArch64::SDOT_VG4_M4ZZ_HtoD:
38451 case AArch64::SDOT_VG4_M4ZZ_HtoS:
38452 case AArch64::SUB_VG2_M2ZZ_D:
38453 case AArch64::SUB_VG2_M2ZZ_S:
38454 case AArch64::SUB_VG4_M4ZZ_D:
38455 case AArch64::SUB_VG4_M4ZZ_S:
38456 case AArch64::SUDOT_VG2_M2ZZ_BToS:
38457 case AArch64::SUDOT_VG4_M4ZZ_BToS:
38458 case AArch64::UDOT_VG2_M2ZZ_BtoS:
38459 case AArch64::UDOT_VG2_M2ZZ_HtoD:
38460 case AArch64::UDOT_VG2_M2ZZ_HtoS:
38461 case AArch64::UDOT_VG4_M4ZZ_BtoS:
38462 case AArch64::UDOT_VG4_M4ZZ_HtoD:
38463 case AArch64::UDOT_VG4_M4ZZ_HtoS:
38464 case AArch64::USDOT_VG2_M2ZZ_BToS:
38465 case AArch64::USDOT_VG4_M4ZZ_BToS: {
38466 switch (OpNum) {
38467 case 5:
38468 // op: Zm
38469 return 16;
38470 case 4:
38471 // op: Zn
38472 return 5;
38473 case 2:
38474 // op: Rv
38475 return 13;
38476 case 3:
38477 // op: imm3
38478 return 0;
38479 }
38480 break;
38481 }
38482 case AArch64::FMLALL_VG2_M2Z2Z_BtoS:
38483 case AArch64::SMLALL_VG2_M2Z2Z_BtoS:
38484 case AArch64::SMLALL_VG2_M2Z2Z_HtoD:
38485 case AArch64::SMLSLL_VG2_M2Z2Z_BtoS:
38486 case AArch64::SMLSLL_VG2_M2Z2Z_HtoD:
38487 case AArch64::UMLALL_VG2_M2Z2Z_BtoS:
38488 case AArch64::UMLALL_VG2_M2Z2Z_HtoD:
38489 case AArch64::UMLSLL_VG2_M2Z2Z_BtoS:
38490 case AArch64::UMLSLL_VG2_M2Z2Z_HtoD:
38491 case AArch64::USMLALL_VG2_M2Z2Z_BtoS: {
38492 switch (OpNum) {
38493 case 5:
38494 // op: Zm
38495 return 17;
38496 case 2:
38497 // op: Rv
38498 return 13;
38499 case 4:
38500 // op: Zn
38501 return 6;
38502 case 3:
38503 // op: imm
38504 return 0;
38505 }
38506 break;
38507 }
38508 case AArch64::ADD_VG2_M2Z2Z_D:
38509 case AArch64::ADD_VG2_M2Z2Z_S:
38510 case AArch64::BFDOT_VG2_M2Z2Z_HtoS:
38511 case AArch64::BFMLA_VG2_M2Z2Z:
38512 case AArch64::BFMLS_VG2_M2Z2Z:
38513 case AArch64::FDOT_VG2_M2Z2Z_BtoH:
38514 case AArch64::FDOT_VG2_M2Z2Z_BtoS:
38515 case AArch64::FDOT_VG2_M2Z2Z_HtoS:
38516 case AArch64::FMLA_VG2_M2Z2Z_D:
38517 case AArch64::FMLA_VG2_M2Z2Z_H:
38518 case AArch64::FMLA_VG2_M2Z2Z_S:
38519 case AArch64::FMLS_VG2_M2Z2Z_D:
38520 case AArch64::FMLS_VG2_M2Z2Z_H:
38521 case AArch64::FMLS_VG2_M2Z2Z_S:
38522 case AArch64::SDOT_VG2_M2Z2Z_BtoS:
38523 case AArch64::SDOT_VG2_M2Z2Z_HtoD:
38524 case AArch64::SDOT_VG2_M2Z2Z_HtoS:
38525 case AArch64::SUB_VG2_M2Z2Z_D:
38526 case AArch64::SUB_VG2_M2Z2Z_S:
38527 case AArch64::UDOT_VG2_M2Z2Z_BtoS:
38528 case AArch64::UDOT_VG2_M2Z2Z_HtoD:
38529 case AArch64::UDOT_VG2_M2Z2Z_HtoS:
38530 case AArch64::USDOT_VG2_M2Z2Z_BToS: {
38531 switch (OpNum) {
38532 case 5:
38533 // op: Zm
38534 return 17;
38535 case 4:
38536 // op: Zn
38537 return 6;
38538 case 2:
38539 // op: Rv
38540 return 13;
38541 case 3:
38542 // op: imm3
38543 return 0;
38544 }
38545 break;
38546 }
38547 case AArch64::FMLALL_VG4_M4Z4Z_BtoS:
38548 case AArch64::SMLALL_VG4_M4Z4Z_BtoS:
38549 case AArch64::SMLALL_VG4_M4Z4Z_HtoD:
38550 case AArch64::SMLSLL_VG4_M4Z4Z_BtoS:
38551 case AArch64::SMLSLL_VG4_M4Z4Z_HtoD:
38552 case AArch64::UMLALL_VG4_M4Z4Z_BtoS:
38553 case AArch64::UMLALL_VG4_M4Z4Z_HtoD:
38554 case AArch64::UMLSLL_VG4_M4Z4Z_BtoS:
38555 case AArch64::UMLSLL_VG4_M4Z4Z_HtoD:
38556 case AArch64::USMLALL_VG4_M4Z4Z_BtoS: {
38557 switch (OpNum) {
38558 case 5:
38559 // op: Zm
38560 return 18;
38561 case 2:
38562 // op: Rv
38563 return 13;
38564 case 4:
38565 // op: Zn
38566 return 7;
38567 case 3:
38568 // op: imm
38569 return 0;
38570 }
38571 break;
38572 }
38573 case AArch64::ADD_VG4_M4Z4Z_D:
38574 case AArch64::ADD_VG4_M4Z4Z_S:
38575 case AArch64::BFDOT_VG4_M4Z4Z_HtoS:
38576 case AArch64::BFMLA_VG4_M4Z4Z:
38577 case AArch64::BFMLS_VG4_M4Z4Z:
38578 case AArch64::FDOT_VG4_M4Z4Z_BtoH:
38579 case AArch64::FDOT_VG4_M4Z4Z_BtoS:
38580 case AArch64::FDOT_VG4_M4Z4Z_HtoS:
38581 case AArch64::FMLA_VG4_M4Z4Z_D:
38582 case AArch64::FMLA_VG4_M4Z4Z_H:
38583 case AArch64::FMLA_VG4_M4Z4Z_S:
38584 case AArch64::FMLS_VG4_M4Z4Z_D:
38585 case AArch64::FMLS_VG4_M4Z4Z_H:
38586 case AArch64::FMLS_VG4_M4Z4Z_S:
38587 case AArch64::SDOT_VG4_M4Z4Z_BtoS:
38588 case AArch64::SDOT_VG4_M4Z4Z_HtoD:
38589 case AArch64::SDOT_VG4_M4Z4Z_HtoS:
38590 case AArch64::SUB_VG4_M4Z4Z_D:
38591 case AArch64::SUB_VG4_M4Z4Z_S:
38592 case AArch64::UDOT_VG4_M4Z4Z_BtoS:
38593 case AArch64::UDOT_VG4_M4Z4Z_HtoD:
38594 case AArch64::UDOT_VG4_M4Z4Z_HtoS:
38595 case AArch64::USDOT_VG4_M4Z4Z_BToS: {
38596 switch (OpNum) {
38597 case 5:
38598 // op: Zm
38599 return 18;
38600 case 4:
38601 // op: Zn
38602 return 7;
38603 case 2:
38604 // op: Rv
38605 return 13;
38606 case 3:
38607 // op: imm3
38608 return 0;
38609 }
38610 break;
38611 }
38612 }
38613 std::string msg;
38614 raw_string_ostream Msg(msg);
38615 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
38616 report_fatal_error(Msg.str().c_str());
38617}
38618
38619#endif // GET_OPERAND_BIT_OFFSET
38620
38621