1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: ARM.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands,
18 const SmallBitVector &OptionalOperandsMask,
19 ArrayRef<unsigned> DefaultsOffset);
20 void convertToMapAndConstraints(unsigned Kind,
21 const OperandVector &Operands) override;
22 unsigned MatchInstructionImpl(const OperandVector &Operands,
23 MCInst &Inst,
24 SmallVectorImpl<NearMissInfo> *NearMisses,
25 bool matchingInlineAsm,
26 unsigned VariantID = 0);
27 ParseStatus MatchOperandParserImpl(
28 OperandVector &Operands,
29 StringRef Mnemonic,
30 bool ParseForAllFeatures = false);
31 ParseStatus tryCustomParseOperand(
32 OperandVector &Operands,
33 unsigned MCK);
34
35#endif // GET_ASSEMBLER_HEADER
36
37
38#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
39#undef GET_OPERAND_DIAGNOSTIC_TYPES
40
41 Match_AlignedMemory16,
42 Match_AlignedMemory32,
43 Match_AlignedMemory64,
44 Match_AlignedMemory64or128,
45 Match_AlignedMemory64or128or256,
46 Match_AlignedMemoryNone,
47 Match_ComplexRotationEven,
48 Match_ComplexRotationOdd,
49 Match_CondCodeRestrictedFP,
50 Match_CondCodeRestrictedI,
51 Match_CondCodeRestrictedS,
52 Match_CondCodeRestrictedU,
53 Match_DPR,
54 Match_DPR_8,
55 Match_DPR_RegList,
56 Match_DPR_VFP2,
57 Match_DupAlignedMemory16,
58 Match_DupAlignedMemory32,
59 Match_DupAlignedMemory64,
60 Match_DupAlignedMemory64or128,
61 Match_DupAlignedMemoryNone,
62 Match_GPR,
63 Match_GPRnoip,
64 Match_GPRnopc,
65 Match_GPRnosp,
66 Match_GPRsp,
67 Match_GPRwithAPSR,
68 Match_GPRwithAPSR_NZCVnosp,
69 Match_GPRwithZR,
70 Match_GPRwithZRnosp,
71 Match_Imm0_1,
72 Match_Imm0_15,
73 Match_Imm0_239,
74 Match_Imm0_255,
75 Match_Imm0_255Expr,
76 Match_Imm0_3,
77 Match_Imm0_31,
78 Match_Imm0_32,
79 Match_Imm0_4095,
80 Match_Imm0_63,
81 Match_Imm0_65535,
82 Match_Imm0_65535Expr,
83 Match_Imm0_7,
84 Match_Imm11b,
85 Match_Imm12b,
86 Match_Imm13b,
87 Match_Imm16,
88 Match_Imm1_15,
89 Match_Imm1_31,
90 Match_Imm1_7,
91 Match_Imm24bit,
92 Match_Imm256_65535Expr,
93 Match_Imm32,
94 Match_Imm3b,
95 Match_Imm4b,
96 Match_Imm6b,
97 Match_Imm7b,
98 Match_Imm8,
99 Match_Imm8_255,
100 Match_Imm9b,
101 Match_ImmRange1_16,
102 Match_ImmRange1_32,
103 Match_ImmThumbSR,
104 Match_LELabel,
105 Match_MVELongShift,
106 Match_MVEShiftImm1_15,
107 Match_MVEShiftImm1_7,
108 Match_MVEVcvtImm16,
109 Match_MVEVcvtImm32,
110 Match_MveSaturate,
111 Match_PKHLSLImm,
112 Match_QPR,
113 Match_QPR_8,
114 Match_QPR_VFP2,
115 Match_SPR,
116 Match_SPRRegList,
117 Match_SPR_8,
118 Match_SetEndImm,
119 Match_ShrImm16,
120 Match_ShrImm32,
121 Match_ShrImm64,
122 Match_ShrImm8,
123 Match_VIDUP_imm,
124 Match_VecListFourMQ,
125 Match_VecListTwoMQ,
126 Match_WLSLabel,
127 Match_hGPR,
128 Match_rGPR,
129 Match_tGPR,
130 Match_tGPREven,
131 Match_tGPROdd,
132 END_OPERAND_DIAGNOSTIC_TYPES
133#endif // GET_OPERAND_DIAGNOSTIC_TYPES
134
135
136#ifdef GET_REGISTER_MATCHER
137#undef GET_REGISTER_MATCHER
138
139// Bits for subtarget features that participate in instruction matching.
140enum SubtargetFeatureBits : uint8_t {
141 Feature_HasV4TBit = 35,
142 Feature_HasV5TBit = 36,
143 Feature_HasV5TEBit = 37,
144 Feature_HasV6Bit = 38,
145 Feature_HasV6MBit = 40,
146 Feature_HasV8MBaselineBit = 45,
147 Feature_HasV8MMainlineBit = 46,
148 Feature_HasV8_1MMainlineBit = 47,
149 Feature_HasMVEIntBit = 26,
150 Feature_HasMVEFloatBit = 25,
151 Feature_HasCDEBit = 4,
152 Feature_HasFPRegsBit = 18,
153 Feature_HasFPRegs16Bit = 19,
154 Feature_HasNoFPRegs16Bit = 29,
155 Feature_HasFPRegs64Bit = 20,
156 Feature_HasFPRegsV8_1MBit = 21,
157 Feature_HasV6T2Bit = 41,
158 Feature_HasV6KBit = 39,
159 Feature_HasV7Bit = 42,
160 Feature_HasV8Bit = 44,
161 Feature_PreV8Bit = 64,
162 Feature_HasV8_1aBit = 48,
163 Feature_HasV8_2aBit = 49,
164 Feature_HasV8_3aBit = 50,
165 Feature_HasV8_4aBit = 51,
166 Feature_HasV8_5aBit = 52,
167 Feature_HasV8_6aBit = 53,
168 Feature_HasV8_7aBit = 54,
169 Feature_HasVFP2Bit = 55,
170 Feature_HasVFP3Bit = 56,
171 Feature_HasVFP4Bit = 57,
172 Feature_HasDPVFPBit = 10,
173 Feature_HasFPARMv8Bit = 17,
174 Feature_HasNEONBit = 28,
175 Feature_HasSHA2Bit = 33,
176 Feature_HasAESBit = 1,
177 Feature_HasCryptoBit = 7,
178 Feature_HasDotProdBit = 14,
179 Feature_HasCRCBit = 6,
180 Feature_HasRASBit = 31,
181 Feature_HasLOBBit = 23,
182 Feature_HasPACBTIBit = 30,
183 Feature_HasFP16Bit = 15,
184 Feature_HasFullFP16Bit = 22,
185 Feature_HasFP16FMLBit = 16,
186 Feature_HasBF16Bit = 3,
187 Feature_HasMatMulInt8Bit = 27,
188 Feature_HasDivideInThumbBit = 13,
189 Feature_HasDivideInARMBit = 12,
190 Feature_HasDSPBit = 11,
191 Feature_HasDBBit = 8,
192 Feature_HasDFBBit = 9,
193 Feature_HasV7ClrexBit = 43,
194 Feature_HasAcquireReleaseBit = 2,
195 Feature_HasMPBit = 24,
196 Feature_HasVirtualizationBit = 58,
197 Feature_HasTrustZoneBit = 34,
198 Feature_Has8MSecExtBit = 0,
199 Feature_IsThumbBit = 62,
200 Feature_IsThumb2Bit = 63,
201 Feature_IsMClassBit = 60,
202 Feature_IsNotMClassBit = 61,
203 Feature_IsARMBit = 59,
204 Feature_UseNaClTrapBit = 65,
205 Feature_UseNegativeImmediatesBit = 66,
206 Feature_HasSBBit = 32,
207 Feature_HasCLRBHBBit = 5,
208};
209
210static MCRegister MatchRegisterName(StringRef Name) {
211 switch (Name.size()) {
212 default: break;
213 case 2: // 45 strings to match.
214 switch (Name[0]) {
215 default: break;
216 case 'd': // 10 strings to match.
217 switch (Name[1]) {
218 default: break;
219 case '0': // 1 string to match.
220 return ARM::D0; // "d0"
221 case '1': // 1 string to match.
222 return ARM::D1; // "d1"
223 case '2': // 1 string to match.
224 return ARM::D2; // "d2"
225 case '3': // 1 string to match.
226 return ARM::D3; // "d3"
227 case '4': // 1 string to match.
228 return ARM::D4; // "d4"
229 case '5': // 1 string to match.
230 return ARM::D5; // "d5"
231 case '6': // 1 string to match.
232 return ARM::D6; // "d6"
233 case '7': // 1 string to match.
234 return ARM::D7; // "d7"
235 case '8': // 1 string to match.
236 return ARM::D8; // "d8"
237 case '9': // 1 string to match.
238 return ARM::D9; // "d9"
239 }
240 break;
241 case 'l': // 1 string to match.
242 if (Name[1] != 'r')
243 break;
244 return ARM::LR; // "lr"
245 case 'p': // 2 strings to match.
246 switch (Name[1]) {
247 default: break;
248 case '0': // 1 string to match.
249 return ARM::P0; // "p0"
250 case 'c': // 1 string to match.
251 return ARM::PC; // "pc"
252 }
253 break;
254 case 'q': // 10 strings to match.
255 switch (Name[1]) {
256 default: break;
257 case '0': // 1 string to match.
258 return ARM::Q0; // "q0"
259 case '1': // 1 string to match.
260 return ARM::Q1; // "q1"
261 case '2': // 1 string to match.
262 return ARM::Q2; // "q2"
263 case '3': // 1 string to match.
264 return ARM::Q3; // "q3"
265 case '4': // 1 string to match.
266 return ARM::Q4; // "q4"
267 case '5': // 1 string to match.
268 return ARM::Q5; // "q5"
269 case '6': // 1 string to match.
270 return ARM::Q6; // "q6"
271 case '7': // 1 string to match.
272 return ARM::Q7; // "q7"
273 case '8': // 1 string to match.
274 return ARM::Q8; // "q8"
275 case '9': // 1 string to match.
276 return ARM::Q9; // "q9"
277 }
278 break;
279 case 'r': // 10 strings to match.
280 switch (Name[1]) {
281 default: break;
282 case '0': // 1 string to match.
283 return ARM::R0; // "r0"
284 case '1': // 1 string to match.
285 return ARM::R1; // "r1"
286 case '2': // 1 string to match.
287 return ARM::R2; // "r2"
288 case '3': // 1 string to match.
289 return ARM::R3; // "r3"
290 case '4': // 1 string to match.
291 return ARM::R4; // "r4"
292 case '5': // 1 string to match.
293 return ARM::R5; // "r5"
294 case '6': // 1 string to match.
295 return ARM::R6; // "r6"
296 case '7': // 1 string to match.
297 return ARM::R7; // "r7"
298 case '8': // 1 string to match.
299 return ARM::R8; // "r8"
300 case '9': // 1 string to match.
301 return ARM::R9; // "r9"
302 }
303 break;
304 case 's': // 11 strings to match.
305 switch (Name[1]) {
306 default: break;
307 case '0': // 1 string to match.
308 return ARM::S0; // "s0"
309 case '1': // 1 string to match.
310 return ARM::S1; // "s1"
311 case '2': // 1 string to match.
312 return ARM::S2; // "s2"
313 case '3': // 1 string to match.
314 return ARM::S3; // "s3"
315 case '4': // 1 string to match.
316 return ARM::S4; // "s4"
317 case '5': // 1 string to match.
318 return ARM::S5; // "s5"
319 case '6': // 1 string to match.
320 return ARM::S6; // "s6"
321 case '7': // 1 string to match.
322 return ARM::S7; // "s7"
323 case '8': // 1 string to match.
324 return ARM::S8; // "s8"
325 case '9': // 1 string to match.
326 return ARM::S9; // "s9"
327 case 'p': // 1 string to match.
328 return ARM::SP; // "sp"
329 }
330 break;
331 case 'z': // 1 string to match.
332 if (Name[1] != 'r')
333 break;
334 return ARM::ZR; // "zr"
335 }
336 break;
337 case 3: // 54 strings to match.
338 switch (Name[0]) {
339 default: break;
340 case 'd': // 22 strings to match.
341 switch (Name[1]) {
342 default: break;
343 case '1': // 10 strings to match.
344 switch (Name[2]) {
345 default: break;
346 case '0': // 1 string to match.
347 return ARM::D10; // "d10"
348 case '1': // 1 string to match.
349 return ARM::D11; // "d11"
350 case '2': // 1 string to match.
351 return ARM::D12; // "d12"
352 case '3': // 1 string to match.
353 return ARM::D13; // "d13"
354 case '4': // 1 string to match.
355 return ARM::D14; // "d14"
356 case '5': // 1 string to match.
357 return ARM::D15; // "d15"
358 case '6': // 1 string to match.
359 return ARM::D16; // "d16"
360 case '7': // 1 string to match.
361 return ARM::D17; // "d17"
362 case '8': // 1 string to match.
363 return ARM::D18; // "d18"
364 case '9': // 1 string to match.
365 return ARM::D19; // "d19"
366 }
367 break;
368 case '2': // 10 strings to match.
369 switch (Name[2]) {
370 default: break;
371 case '0': // 1 string to match.
372 return ARM::D20; // "d20"
373 case '1': // 1 string to match.
374 return ARM::D21; // "d21"
375 case '2': // 1 string to match.
376 return ARM::D22; // "d22"
377 case '3': // 1 string to match.
378 return ARM::D23; // "d23"
379 case '4': // 1 string to match.
380 return ARM::D24; // "d24"
381 case '5': // 1 string to match.
382 return ARM::D25; // "d25"
383 case '6': // 1 string to match.
384 return ARM::D26; // "d26"
385 case '7': // 1 string to match.
386 return ARM::D27; // "d27"
387 case '8': // 1 string to match.
388 return ARM::D28; // "d28"
389 case '9': // 1 string to match.
390 return ARM::D29; // "d29"
391 }
392 break;
393 case '3': // 2 strings to match.
394 switch (Name[2]) {
395 default: break;
396 case '0': // 1 string to match.
397 return ARM::D30; // "d30"
398 case '1': // 1 string to match.
399 return ARM::D31; // "d31"
400 }
401 break;
402 }
403 break;
404 case 'q': // 6 strings to match.
405 if (Name[1] != '1')
406 break;
407 switch (Name[2]) {
408 default: break;
409 case '0': // 1 string to match.
410 return ARM::Q10; // "q10"
411 case '1': // 1 string to match.
412 return ARM::Q11; // "q11"
413 case '2': // 1 string to match.
414 return ARM::Q12; // "q12"
415 case '3': // 1 string to match.
416 return ARM::Q13; // "q13"
417 case '4': // 1 string to match.
418 return ARM::Q14; // "q14"
419 case '5': // 1 string to match.
420 return ARM::Q15; // "q15"
421 }
422 break;
423 case 'r': // 3 strings to match.
424 if (Name[1] != '1')
425 break;
426 switch (Name[2]) {
427 default: break;
428 case '0': // 1 string to match.
429 return ARM::R10; // "r10"
430 case '1': // 1 string to match.
431 return ARM::R11; // "r11"
432 case '2': // 1 string to match.
433 return ARM::R12; // "r12"
434 }
435 break;
436 case 's': // 22 strings to match.
437 switch (Name[1]) {
438 default: break;
439 case '1': // 10 strings to match.
440 switch (Name[2]) {
441 default: break;
442 case '0': // 1 string to match.
443 return ARM::S10; // "s10"
444 case '1': // 1 string to match.
445 return ARM::S11; // "s11"
446 case '2': // 1 string to match.
447 return ARM::S12; // "s12"
448 case '3': // 1 string to match.
449 return ARM::S13; // "s13"
450 case '4': // 1 string to match.
451 return ARM::S14; // "s14"
452 case '5': // 1 string to match.
453 return ARM::S15; // "s15"
454 case '6': // 1 string to match.
455 return ARM::S16; // "s16"
456 case '7': // 1 string to match.
457 return ARM::S17; // "s17"
458 case '8': // 1 string to match.
459 return ARM::S18; // "s18"
460 case '9': // 1 string to match.
461 return ARM::S19; // "s19"
462 }
463 break;
464 case '2': // 10 strings to match.
465 switch (Name[2]) {
466 default: break;
467 case '0': // 1 string to match.
468 return ARM::S20; // "s20"
469 case '1': // 1 string to match.
470 return ARM::S21; // "s21"
471 case '2': // 1 string to match.
472 return ARM::S22; // "s22"
473 case '3': // 1 string to match.
474 return ARM::S23; // "s23"
475 case '4': // 1 string to match.
476 return ARM::S24; // "s24"
477 case '5': // 1 string to match.
478 return ARM::S25; // "s25"
479 case '6': // 1 string to match.
480 return ARM::S26; // "s26"
481 case '7': // 1 string to match.
482 return ARM::S27; // "s27"
483 case '8': // 1 string to match.
484 return ARM::S28; // "s28"
485 case '9': // 1 string to match.
486 return ARM::S29; // "s29"
487 }
488 break;
489 case '3': // 2 strings to match.
490 switch (Name[2]) {
491 default: break;
492 case '0': // 1 string to match.
493 return ARM::S30; // "s30"
494 case '1': // 1 string to match.
495 return ARM::S31; // "s31"
496 }
497 break;
498 }
499 break;
500 case 'v': // 1 string to match.
501 if (memcmp(Name.data()+1, "pr", 2) != 0)
502 break;
503 return ARM::VPR; // "vpr"
504 }
505 break;
506 case 4: // 3 strings to match.
507 switch (Name[0]) {
508 default: break;
509 case 'a': // 1 string to match.
510 if (memcmp(Name.data()+1, "psr", 3) != 0)
511 break;
512 return ARM::APSR; // "apsr"
513 case 'c': // 1 string to match.
514 if (memcmp(Name.data()+1, "psr", 3) != 0)
515 break;
516 return ARM::CPSR; // "cpsr"
517 case 's': // 1 string to match.
518 if (memcmp(Name.data()+1, "psr", 3) != 0)
519 break;
520 return ARM::SPSR; // "spsr"
521 }
522 break;
523 case 5: // 6 strings to match.
524 switch (Name[0]) {
525 default: break;
526 case 'f': // 3 strings to match.
527 if (Name[1] != 'p')
528 break;
529 switch (Name[2]) {
530 default: break;
531 case 'e': // 1 string to match.
532 if (memcmp(Name.data()+3, "xc", 2) != 0)
533 break;
534 return ARM::FPEXC; // "fpexc"
535 case 's': // 2 strings to match.
536 switch (Name[3]) {
537 default: break;
538 case 'c': // 1 string to match.
539 if (Name[4] != 'r')
540 break;
541 return ARM::FPSCR; // "fpscr"
542 case 'i': // 1 string to match.
543 if (Name[4] != 'd')
544 break;
545 return ARM::FPSID; // "fpsid"
546 }
547 break;
548 }
549 break;
550 case 'm': // 3 strings to match.
551 if (memcmp(Name.data()+1, "vfr", 3) != 0)
552 break;
553 switch (Name[4]) {
554 default: break;
555 case '0': // 1 string to match.
556 return ARM::MVFR0; // "mvfr0"
557 case '1': // 1 string to match.
558 return ARM::MVFR1; // "mvfr1"
559 case '2': // 1 string to match.
560 return ARM::MVFR2; // "mvfr2"
561 }
562 break;
563 }
564 break;
565 case 6: // 2 strings to match.
566 if (memcmp(Name.data()+0, "fp", 2) != 0)
567 break;
568 switch (Name[2]) {
569 default: break;
570 case 'c': // 1 string to match.
571 if (memcmp(Name.data()+3, "xts", 3) != 0)
572 break;
573 return ARM::FPCXTS; // "fpcxts"
574 case 'i': // 1 string to match.
575 if (memcmp(Name.data()+3, "nst", 3) != 0)
576 break;
577 return ARM::FPINST; // "fpinst"
578 }
579 break;
580 case 7: // 3 strings to match.
581 switch (Name[0]) {
582 default: break;
583 case 'f': // 2 strings to match.
584 if (Name[1] != 'p')
585 break;
586 switch (Name[2]) {
587 default: break;
588 case 'c': // 1 string to match.
589 if (memcmp(Name.data()+3, "xtns", 4) != 0)
590 break;
591 return ARM::FPCXTNS; // "fpcxtns"
592 case 'i': // 1 string to match.
593 if (memcmp(Name.data()+3, "nst2", 4) != 0)
594 break;
595 return ARM::FPINST2; // "fpinst2"
596 }
597 break;
598 case 'i': // 1 string to match.
599 if (memcmp(Name.data()+1, "tstate", 6) != 0)
600 break;
601 return ARM::ITSTATE; // "itstate"
602 }
603 break;
604 case 9: // 1 string to match.
605 if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0)
606 break;
607 return ARM::APSR_NZCV; // "apsr_nzcv"
608 case 10: // 1 string to match.
609 if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0)
610 break;
611 return ARM::FPSCR_NZCV; // "fpscr_nzcv"
612 case 12: // 2 strings to match.
613 switch (Name[0]) {
614 default: break;
615 case 'f': // 1 string to match.
616 if (memcmp(Name.data()+1, "pscr_nzcvqc", 11) != 0)
617 break;
618 return ARM::FPSCR_NZCVQC; // "fpscr_nzcvqc"
619 case 'r': // 1 string to match.
620 if (memcmp(Name.data()+1, "a_auth_code", 11) != 0)
621 break;
622 return ARM::RA_AUTH_CODE; // "ra_auth_code"
623 }
624 break;
625 }
626 return ARM::NoRegister;
627}
628
629#endif // GET_REGISTER_MATCHER
630
631
632#ifdef GET_SUBTARGET_FEATURE_NAME
633#undef GET_SUBTARGET_FEATURE_NAME
634
635// User-level names for subtarget features that participate in
636// instruction matching.
637static const char *getSubtargetFeatureName(uint64_t Val) {
638 switch(Val) {
639 case Feature_HasV4TBit: return "armv4t";
640 case Feature_HasV5TBit: return "armv5t";
641 case Feature_HasV5TEBit: return "armv5te";
642 case Feature_HasV6Bit: return "armv6";
643 case Feature_HasV6MBit: return "armv6m or armv6t2";
644 case Feature_HasV8MBaselineBit: return "armv8m.base";
645 case Feature_HasV8MMainlineBit: return "armv8m.main";
646 case Feature_HasV8_1MMainlineBit: return "armv8.1m.main";
647 case Feature_HasMVEIntBit: return "mve";
648 case Feature_HasMVEFloatBit: return "mve.fp";
649 case Feature_HasCDEBit: return "cde";
650 case Feature_HasFPRegsBit: return "fp registers";
651 case Feature_HasFPRegs16Bit: return "16-bit fp registers";
652 case Feature_HasNoFPRegs16Bit: return "16-bit fp registers";
653 case Feature_HasFPRegs64Bit: return "64-bit fp registers";
654 case Feature_HasFPRegsV8_1MBit: return "armv8.1m.main with FP or MVE";
655 case Feature_HasV6T2Bit: return "armv6t2";
656 case Feature_HasV6KBit: return "armv6k";
657 case Feature_HasV7Bit: return "armv7";
658 case Feature_HasV8Bit: return "armv8";
659 case Feature_PreV8Bit: return "armv7 or earlier";
660 case Feature_HasV8_1aBit: return "armv8.1a";
661 case Feature_HasV8_2aBit: return "armv8.2a";
662 case Feature_HasV8_3aBit: return "armv8.3a";
663 case Feature_HasV8_4aBit: return "armv8.4a";
664 case Feature_HasV8_5aBit: return "armv8.5a";
665 case Feature_HasV8_6aBit: return "armv8.6a";
666 case Feature_HasV8_7aBit: return "armv8.7a";
667 case Feature_HasVFP2Bit: return "VFP2";
668 case Feature_HasVFP3Bit: return "VFP3";
669 case Feature_HasVFP4Bit: return "VFP4";
670 case Feature_HasDPVFPBit: return "double precision VFP";
671 case Feature_HasFPARMv8Bit: return "FPARMv8";
672 case Feature_HasNEONBit: return "NEON";
673 case Feature_HasSHA2Bit: return "sha2";
674 case Feature_HasAESBit: return "aes";
675 case Feature_HasCryptoBit: return "crypto";
676 case Feature_HasDotProdBit: return "dotprod";
677 case Feature_HasCRCBit: return "crc";
678 case Feature_HasRASBit: return "ras";
679 case Feature_HasLOBBit: return "lob";
680 case Feature_HasPACBTIBit: return "pacbti";
681 case Feature_HasFP16Bit: return "half-float conversions";
682 case Feature_HasFullFP16Bit: return "full half-float";
683 case Feature_HasFP16FMLBit: return "full half-float fml";
684 case Feature_HasBF16Bit: return "BFloat16 floating point extension";
685 case Feature_HasMatMulInt8Bit: return "8-bit integer matrix multiply";
686 case Feature_HasDivideInThumbBit: return "divide in THUMB";
687 case Feature_HasDivideInARMBit: return "divide in ARM";
688 case Feature_HasDSPBit: return "dsp";
689 case Feature_HasDBBit: return "data-barriers";
690 case Feature_HasDFBBit: return "full-data-barrier";
691 case Feature_HasV7ClrexBit: return "v7 clrex";
692 case Feature_HasAcquireReleaseBit: return "acquire/release";
693 case Feature_HasMPBit: return "mp-extensions";
694 case Feature_HasVirtualizationBit: return "virtualization-extensions";
695 case Feature_HasTrustZoneBit: return "TrustZone";
696 case Feature_Has8MSecExtBit: return "ARMv8-M Security Extensions";
697 case Feature_IsThumbBit: return "thumb";
698 case Feature_IsThumb2Bit: return "thumb2";
699 case Feature_IsMClassBit: return "armv*m";
700 case Feature_IsNotMClassBit: return "!armv*m";
701 case Feature_IsARMBit: return "arm-mode";
702 case Feature_UseNaClTrapBit: return "NaCl";
703 case Feature_UseNegativeImmediatesBit: return "NegativeImmediates";
704 case Feature_HasSBBit: return "sb";
705 case Feature_HasCLRBHBBit: return "clrbhb";
706 default: return "(unknown)";
707 }
708}
709
710#endif // GET_SUBTARGET_FEATURE_NAME
711
712
713#ifdef GET_MATCHER_IMPLEMENTATION
714#undef GET_MATCHER_IMPLEMENTATION
715
716static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
717 switch (VariantID) {
718 case 0:
719 break;
720 }
721 switch (Mnemonic.size()) {
722 default: break;
723 case 3: // 4 strings to match.
724 switch (Mnemonic[0]) {
725 default: break;
726 case 'r': // 1 string to match.
727 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
728 break;
729 Mnemonic = "rfeia"; // "rfe"
730 return;
731 case 's': // 3 strings to match.
732 switch (Mnemonic[1]) {
733 default: break;
734 case 'm': // 1 string to match.
735 if (Mnemonic[2] != 'i')
736 break;
737 Mnemonic = "smc"; // "smi"
738 return;
739 case 'r': // 1 string to match.
740 if (Mnemonic[2] != 's')
741 break;
742 Mnemonic = "srsia"; // "srs"
743 return;
744 case 'w': // 1 string to match.
745 if (Mnemonic[2] != 'i')
746 break;
747 Mnemonic = "svc"; // "swi"
748 return;
749 }
750 break;
751 }
752 break;
753 case 4: // 10 strings to match.
754 switch (Mnemonic[0]) {
755 default: break;
756 case 'f': // 8 strings to match.
757 switch (Mnemonic[1]) {
758 default: break;
759 case 'l': // 2 strings to match.
760 if (Mnemonic[2] != 'd')
761 break;
762 switch (Mnemonic[3]) {
763 default: break;
764 case 'd': // 1 string to match.
765 if (Features.test(Feature_HasVFP2Bit)) // "fldd"
766 Mnemonic = "vldr";
767 return;
768 case 's': // 1 string to match.
769 if (Features.test(Feature_HasVFP2Bit)) // "flds"
770 Mnemonic = "vldr";
771 return;
772 }
773 break;
774 case 'm': // 4 strings to match.
775 switch (Mnemonic[2]) {
776 default: break;
777 case 'r': // 2 strings to match.
778 switch (Mnemonic[3]) {
779 default: break;
780 case 's': // 1 string to match.
781 if (Features.test(Feature_HasVFP2Bit)) // "fmrs"
782 Mnemonic = "vmov";
783 return;
784 case 'x': // 1 string to match.
785 if (Features.test(Feature_HasVFP2Bit)) // "fmrx"
786 Mnemonic = "vmrs";
787 return;
788 }
789 break;
790 case 's': // 1 string to match.
791 if (Mnemonic[3] != 'r')
792 break;
793 if (Features.test(Feature_HasVFP2Bit)) // "fmsr"
794 Mnemonic = "vmov";
795 return;
796 case 'x': // 1 string to match.
797 if (Mnemonic[3] != 'r')
798 break;
799 if (Features.test(Feature_HasVFP2Bit)) // "fmxr"
800 Mnemonic = "vmsr";
801 return;
802 }
803 break;
804 case 's': // 2 strings to match.
805 if (Mnemonic[2] != 't')
806 break;
807 switch (Mnemonic[3]) {
808 default: break;
809 case 'd': // 1 string to match.
810 if (Features.test(Feature_HasVFP2Bit)) // "fstd"
811 Mnemonic = "vstr";
812 return;
813 case 's': // 1 string to match.
814 if (Features.test(Feature_HasVFP2Bit)) // "fsts"
815 Mnemonic = "vstr";
816 return;
817 }
818 break;
819 }
820 break;
821 case 'v': // 2 strings to match.
822 switch (Mnemonic[1]) {
823 default: break;
824 case 'l': // 1 string to match.
825 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
826 break;
827 Mnemonic = "vldmia"; // "vldm"
828 return;
829 case 's': // 1 string to match.
830 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
831 break;
832 Mnemonic = "vstmia"; // "vstm"
833 return;
834 }
835 break;
836 }
837 break;
838 case 5: // 51 strings to match.
839 switch (Mnemonic[0]) {
840 default: break;
841 case 'f': // 18 strings to match.
842 switch (Mnemonic[1]) {
843 default: break;
844 case 'a': // 2 strings to match.
845 if (memcmp(Mnemonic.data()+2, "dd", 2) != 0)
846 break;
847 switch (Mnemonic[4]) {
848 default: break;
849 case 'd': // 1 string to match.
850 if (Features.test(Feature_HasVFP2Bit)) // "faddd"
851 Mnemonic = "vadd.f64";
852 return;
853 case 's': // 1 string to match.
854 if (Features.test(Feature_HasVFP2Bit)) // "fadds"
855 Mnemonic = "vadd.f32";
856 return;
857 }
858 break;
859 case 'c': // 4 strings to match.
860 switch (Mnemonic[2]) {
861 default: break;
862 case 'm': // 2 strings to match.
863 if (Mnemonic[3] != 'p')
864 break;
865 switch (Mnemonic[4]) {
866 default: break;
867 case 'd': // 1 string to match.
868 if (Features.test(Feature_HasVFP2Bit)) // "fcmpd"
869 Mnemonic = "vcmp.f64";
870 return;
871 case 's': // 1 string to match.
872 if (Features.test(Feature_HasVFP2Bit)) // "fcmps"
873 Mnemonic = "vcmp.f32";
874 return;
875 }
876 break;
877 case 'p': // 2 strings to match.
878 if (Mnemonic[3] != 'y')
879 break;
880 switch (Mnemonic[4]) {
881 default: break;
882 case 'd': // 1 string to match.
883 if (Features.test(Feature_HasVFP2Bit)) // "fcpyd"
884 Mnemonic = "vmov.f64";
885 return;
886 case 's': // 1 string to match.
887 if (Features.test(Feature_HasVFP2Bit)) // "fcpys"
888 Mnemonic = "vmov.f32";
889 return;
890 }
891 break;
892 }
893 break;
894 case 'd': // 2 strings to match.
895 if (memcmp(Mnemonic.data()+2, "iv", 2) != 0)
896 break;
897 switch (Mnemonic[4]) {
898 default: break;
899 case 'd': // 1 string to match.
900 if (Features.test(Feature_HasVFP2Bit)) // "fdivd"
901 Mnemonic = "vdiv.f64";
902 return;
903 case 's': // 1 string to match.
904 if (Features.test(Feature_HasVFP2Bit)) // "fdivs"
905 Mnemonic = "vdiv.f32";
906 return;
907 }
908 break;
909 case 'm': // 8 strings to match.
910 switch (Mnemonic[2]) {
911 default: break;
912 case 'a': // 2 strings to match.
913 if (Mnemonic[3] != 'c')
914 break;
915 switch (Mnemonic[4]) {
916 default: break;
917 case 'd': // 1 string to match.
918 if (Features.test(Feature_HasVFP2Bit)) // "fmacd"
919 Mnemonic = "vmla.f64";
920 return;
921 case 's': // 1 string to match.
922 if (Features.test(Feature_HasVFP2Bit)) // "fmacs"
923 Mnemonic = "vmla.f32";
924 return;
925 }
926 break;
927 case 'd': // 1 string to match.
928 if (memcmp(Mnemonic.data()+3, "rr", 2) != 0)
929 break;
930 if (Features.test(Feature_HasVFP2Bit)) // "fmdrr"
931 Mnemonic = "vmov";
932 return;
933 case 'r': // 3 strings to match.
934 switch (Mnemonic[3]) {
935 default: break;
936 case 'd': // 2 strings to match.
937 switch (Mnemonic[4]) {
938 default: break;
939 case 'd': // 1 string to match.
940 if (Features.test(Feature_HasVFP2Bit)) // "fmrdd"
941 Mnemonic = "vmov";
942 return;
943 case 's': // 1 string to match.
944 if (Features.test(Feature_HasVFP2Bit)) // "fmrds"
945 Mnemonic = "vmov";
946 return;
947 }
948 break;
949 case 'r': // 1 string to match.
950 if (Mnemonic[4] != 'd')
951 break;
952 if (Features.test(Feature_HasVFP2Bit)) // "fmrrd"
953 Mnemonic = "vmov";
954 return;
955 }
956 break;
957 case 'u': // 2 strings to match.
958 if (Mnemonic[3] != 'l')
959 break;
960 switch (Mnemonic[4]) {
961 default: break;
962 case 'd': // 1 string to match.
963 if (Features.test(Feature_HasVFP2Bit)) // "fmuld"
964 Mnemonic = "vmul.f64";
965 return;
966 case 's': // 1 string to match.
967 if (Features.test(Feature_HasVFP2Bit)) // "fmuls"
968 Mnemonic = "vmul.f32";
969 return;
970 }
971 break;
972 }
973 break;
974 case 'n': // 2 strings to match.
975 if (memcmp(Mnemonic.data()+2, "eg", 2) != 0)
976 break;
977 switch (Mnemonic[4]) {
978 default: break;
979 case 'd': // 1 string to match.
980 if (Features.test(Feature_HasVFP2Bit)) // "fnegd"
981 Mnemonic = "vneg.f64";
982 return;
983 case 's': // 1 string to match.
984 if (Features.test(Feature_HasVFP2Bit)) // "fnegs"
985 Mnemonic = "vneg.f32";
986 return;
987 }
988 break;
989 }
990 break;
991 case 'l': // 3 strings to match.
992 if (memcmp(Mnemonic.data()+1, "dm", 2) != 0)
993 break;
994 switch (Mnemonic[3]) {
995 default: break;
996 case 'e': // 1 string to match.
997 if (Mnemonic[4] != 'a')
998 break;
999 Mnemonic = "ldmdb"; // "ldmea"
1000 return;
1001 case 'f': // 1 string to match.
1002 if (Mnemonic[4] != 'd')
1003 break;
1004 Mnemonic = "ldm"; // "ldmfd"
1005 return;
1006 case 'i': // 1 string to match.
1007 if (Mnemonic[4] != 'a')
1008 break;
1009 Mnemonic = "ldm"; // "ldmia"
1010 return;
1011 }
1012 break;
1013 case 'r': // 4 strings to match.
1014 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
1015 break;
1016 switch (Mnemonic[3]) {
1017 default: break;
1018 case 'e': // 2 strings to match.
1019 switch (Mnemonic[4]) {
1020 default: break;
1021 case 'a': // 1 string to match.
1022 Mnemonic = "rfedb"; // "rfeea"
1023 return;
1024 case 'd': // 1 string to match.
1025 Mnemonic = "rfeib"; // "rfeed"
1026 return;
1027 }
1028 break;
1029 case 'f': // 2 strings to match.
1030 switch (Mnemonic[4]) {
1031 default: break;
1032 case 'a': // 1 string to match.
1033 Mnemonic = "rfeda"; // "rfefa"
1034 return;
1035 case 'd': // 1 string to match.
1036 Mnemonic = "rfeia"; // "rfefd"
1037 return;
1038 }
1039 break;
1040 }
1041 break;
1042 case 's': // 7 strings to match.
1043 switch (Mnemonic[1]) {
1044 default: break;
1045 case 'r': // 4 strings to match.
1046 if (Mnemonic[2] != 's')
1047 break;
1048 switch (Mnemonic[3]) {
1049 default: break;
1050 case 'e': // 2 strings to match.
1051 switch (Mnemonic[4]) {
1052 default: break;
1053 case 'a': // 1 string to match.
1054 Mnemonic = "srsia"; // "srsea"
1055 return;
1056 case 'd': // 1 string to match.
1057 Mnemonic = "srsda"; // "srsed"
1058 return;
1059 }
1060 break;
1061 case 'f': // 2 strings to match.
1062 switch (Mnemonic[4]) {
1063 default: break;
1064 case 'a': // 1 string to match.
1065 Mnemonic = "srsib"; // "srsfa"
1066 return;
1067 case 'd': // 1 string to match.
1068 Mnemonic = "srsdb"; // "srsfd"
1069 return;
1070 }
1071 break;
1072 }
1073 break;
1074 case 't': // 3 strings to match.
1075 if (Mnemonic[2] != 'm')
1076 break;
1077 switch (Mnemonic[3]) {
1078 default: break;
1079 case 'e': // 1 string to match.
1080 if (Mnemonic[4] != 'a')
1081 break;
1082 Mnemonic = "stm"; // "stmea"
1083 return;
1084 case 'f': // 1 string to match.
1085 if (Mnemonic[4] != 'd')
1086 break;
1087 Mnemonic = "stmdb"; // "stmfd"
1088 return;
1089 case 'i': // 1 string to match.
1090 if (Mnemonic[4] != 'a')
1091 break;
1092 Mnemonic = "stm"; // "stmia"
1093 return;
1094 }
1095 break;
1096 }
1097 break;
1098 case 'v': // 19 strings to match.
1099 switch (Mnemonic[1]) {
1100 default: break;
1101 case 'a': // 3 strings to match.
1102 switch (Mnemonic[2]) {
1103 default: break;
1104 case 'b': // 1 string to match.
1105 if (memcmp(Mnemonic.data()+3, "sq", 2) != 0)
1106 break;
1107 if (Features.test(Feature_HasNEONBit)) // "vabsq"
1108 Mnemonic = "vabs";
1109 return;
1110 case 'd': // 1 string to match.
1111 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1112 break;
1113 if (Features.test(Feature_HasNEONBit)) // "vaddq"
1114 Mnemonic = "vadd";
1115 return;
1116 case 'n': // 1 string to match.
1117 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1118 break;
1119 if (Features.test(Feature_HasNEONBit)) // "vandq"
1120 Mnemonic = "vand";
1121 return;
1122 }
1123 break;
1124 case 'b': // 1 string to match.
1125 if (memcmp(Mnemonic.data()+2, "icq", 3) != 0)
1126 break;
1127 if (Features.test(Feature_HasNEONBit)) // "vbicq"
1128 Mnemonic = "vbic";
1129 return;
1130 case 'c': // 3 strings to match.
1131 switch (Mnemonic[2]) {
1132 default: break;
1133 case 'e': // 1 string to match.
1134 if (memcmp(Mnemonic.data()+3, "qq", 2) != 0)
1135 break;
1136 if (Features.test(Feature_HasNEONBit)) // "vceqq"
1137 Mnemonic = "vceq";
1138 return;
1139 case 'l': // 1 string to match.
1140 if (memcmp(Mnemonic.data()+3, "eq", 2) != 0)
1141 break;
1142 if (Features.test(Feature_HasNEONBit)) // "vcleq"
1143 Mnemonic = "vcle";
1144 return;
1145 case 'v': // 1 string to match.
1146 if (memcmp(Mnemonic.data()+3, "tq", 2) != 0)
1147 break;
1148 if (Features.test(Feature_HasNEONBit)) // "vcvtq"
1149 Mnemonic = "vcvt";
1150 return;
1151 }
1152 break;
1153 case 'e': // 1 string to match.
1154 if (memcmp(Mnemonic.data()+2, "orq", 3) != 0)
1155 break;
1156 if (Features.test(Feature_HasNEONBit)) // "veorq"
1157 Mnemonic = "veor";
1158 return;
1159 case 'm': // 5 strings to match.
1160 switch (Mnemonic[2]) {
1161 default: break;
1162 case 'a': // 1 string to match.
1163 if (memcmp(Mnemonic.data()+3, "xq", 2) != 0)
1164 break;
1165 if (Features.test(Feature_HasNEONBit)) // "vmaxq"
1166 Mnemonic = "vmax";
1167 return;
1168 case 'i': // 1 string to match.
1169 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1170 break;
1171 if (Features.test(Feature_HasNEONBit)) // "vminq"
1172 Mnemonic = "vmin";
1173 return;
1174 case 'o': // 1 string to match.
1175 if (memcmp(Mnemonic.data()+3, "vq", 2) != 0)
1176 break;
1177 if (Features.test(Feature_HasNEONBit)) // "vmovq"
1178 Mnemonic = "vmov";
1179 return;
1180 case 'u': // 1 string to match.
1181 if (memcmp(Mnemonic.data()+3, "lq", 2) != 0)
1182 break;
1183 if (Features.test(Feature_HasNEONBit)) // "vmulq"
1184 Mnemonic = "vmul";
1185 return;
1186 case 'v': // 1 string to match.
1187 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1188 break;
1189 if (Features.test(Feature_HasNEONBit)) // "vmvnq"
1190 Mnemonic = "vmvn";
1191 return;
1192 }
1193 break;
1194 case 'o': // 1 string to match.
1195 if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0)
1196 break;
1197 if (Features.test(Feature_HasNEONBit)) // "vorrq"
1198 Mnemonic = "vorr";
1199 return;
1200 case 's': // 4 strings to match.
1201 switch (Mnemonic[2]) {
1202 default: break;
1203 case 'h': // 2 strings to match.
1204 switch (Mnemonic[3]) {
1205 default: break;
1206 case 'l': // 1 string to match.
1207 if (Mnemonic[4] != 'q')
1208 break;
1209 if (Features.test(Feature_HasNEONBit)) // "vshlq"
1210 Mnemonic = "vshl";
1211 return;
1212 case 'r': // 1 string to match.
1213 if (Mnemonic[4] != 'q')
1214 break;
1215 if (Features.test(Feature_HasNEONBit)) // "vshrq"
1216 Mnemonic = "vshr";
1217 return;
1218 }
1219 break;
1220 case 'u': // 1 string to match.
1221 if (memcmp(Mnemonic.data()+3, "bq", 2) != 0)
1222 break;
1223 if (Features.test(Feature_HasNEONBit)) // "vsubq"
1224 Mnemonic = "vsub";
1225 return;
1226 case 'w': // 1 string to match.
1227 if (memcmp(Mnemonic.data()+3, "pq", 2) != 0)
1228 break;
1229 if (Features.test(Feature_HasNEONBit)) // "vswpq"
1230 Mnemonic = "vswp";
1231 return;
1232 }
1233 break;
1234 case 'z': // 1 string to match.
1235 if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0)
1236 break;
1237 if (Features.test(Feature_HasNEONBit)) // "vzipq"
1238 Mnemonic = "vzip";
1239 return;
1240 }
1241 break;
1242 }
1243 break;
1244 case 6: // 10 strings to match.
1245 if (Mnemonic[0] != 'f')
1246 break;
1247 switch (Mnemonic[1]) {
1248 default: break;
1249 case 's': // 4 strings to match.
1250 switch (Mnemonic[2]) {
1251 default: break;
1252 case 'i': // 2 strings to match.
1253 if (memcmp(Mnemonic.data()+3, "to", 2) != 0)
1254 break;
1255 switch (Mnemonic[5]) {
1256 default: break;
1257 case 'd': // 1 string to match.
1258 if (Features.test(Feature_HasVFP2Bit)) // "fsitod"
1259 Mnemonic = "vcvt.f64.s32";
1260 return;
1261 case 's': // 1 string to match.
1262 if (Features.test(Feature_HasVFP2Bit)) // "fsitos"
1263 Mnemonic = "vcvt.f32.s32";
1264 return;
1265 }
1266 break;
1267 case 'q': // 2 strings to match.
1268 if (memcmp(Mnemonic.data()+3, "rt", 2) != 0)
1269 break;
1270 switch (Mnemonic[5]) {
1271 default: break;
1272 case 'd': // 1 string to match.
1273 if (Features.test(Feature_HasVFP2Bit)) // "fsqrtd"
1274 Mnemonic = "vsqrt";
1275 return;
1276 case 's': // 1 string to match.
1277 if (Features.test(Feature_HasVFP2Bit)) // "fsqrts"
1278 Mnemonic = "vsqrt";
1279 return;
1280 }
1281 break;
1282 }
1283 break;
1284 case 't': // 4 strings to match.
1285 if (Mnemonic[2] != 'o')
1286 break;
1287 switch (Mnemonic[3]) {
1288 default: break;
1289 case 's': // 2 strings to match.
1290 if (Mnemonic[4] != 'i')
1291 break;
1292 switch (Mnemonic[5]) {
1293 default: break;
1294 case 'd': // 1 string to match.
1295 if (Features.test(Feature_HasVFP2Bit)) // "ftosid"
1296 Mnemonic = "vcvtr.s32.f64";
1297 return;
1298 case 's': // 1 string to match.
1299 if (Features.test(Feature_HasVFP2Bit)) // "ftosis"
1300 Mnemonic = "vcvtr.s32.f32";
1301 return;
1302 }
1303 break;
1304 case 'u': // 2 strings to match.
1305 if (Mnemonic[4] != 'i')
1306 break;
1307 switch (Mnemonic[5]) {
1308 default: break;
1309 case 'd': // 1 string to match.
1310 if (Features.test(Feature_HasVFP2Bit)) // "ftouid"
1311 Mnemonic = "vcvtr.u32.f64";
1312 return;
1313 case 's': // 1 string to match.
1314 if (Features.test(Feature_HasVFP2Bit)) // "ftouis"
1315 Mnemonic = "vcvtr.u32.f32";
1316 return;
1317 }
1318 break;
1319 }
1320 break;
1321 case 'u': // 2 strings to match.
1322 if (memcmp(Mnemonic.data()+2, "ito", 3) != 0)
1323 break;
1324 switch (Mnemonic[5]) {
1325 default: break;
1326 case 'd': // 1 string to match.
1327 if (Features.test(Feature_HasVFP2Bit)) // "fuitod"
1328 Mnemonic = "vcvt.f64.u32";
1329 return;
1330 case 's': // 1 string to match.
1331 if (Features.test(Feature_HasVFP2Bit)) // "fuitos"
1332 Mnemonic = "vcvt.f32.u32";
1333 return;
1334 }
1335 break;
1336 }
1337 break;
1338 case 7: // 9 strings to match.
1339 switch (Mnemonic[0]) {
1340 default: break;
1341 case 'f': // 8 strings to match.
1342 switch (Mnemonic[1]) {
1343 default: break;
1344 case 'l': // 2 strings to match.
1345 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
1346 break;
1347 switch (Mnemonic[4]) {
1348 default: break;
1349 case 'e': // 1 string to match.
1350 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1351 break;
1352 if (Features.test(Feature_HasVFP2Bit)) // "fldmeax"
1353 Mnemonic = "fldmdbx";
1354 return;
1355 case 'f': // 1 string to match.
1356 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1357 break;
1358 if (Features.test(Feature_HasVFP2Bit)) // "fldmfdx"
1359 Mnemonic = "fldmiax";
1360 return;
1361 }
1362 break;
1363 case 's': // 2 strings to match.
1364 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
1365 break;
1366 switch (Mnemonic[4]) {
1367 default: break;
1368 case 'e': // 1 string to match.
1369 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1370 break;
1371 if (Features.test(Feature_HasVFP2Bit)) // "fstmeax"
1372 Mnemonic = "fstmiax";
1373 return;
1374 case 'f': // 1 string to match.
1375 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1376 break;
1377 if (Features.test(Feature_HasVFP2Bit)) // "fstmfdx"
1378 Mnemonic = "fstmdbx";
1379 return;
1380 }
1381 break;
1382 case 't': // 4 strings to match.
1383 if (Mnemonic[2] != 'o')
1384 break;
1385 switch (Mnemonic[3]) {
1386 default: break;
1387 case 's': // 2 strings to match.
1388 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1389 break;
1390 switch (Mnemonic[6]) {
1391 default: break;
1392 case 'd': // 1 string to match.
1393 if (Features.test(Feature_HasVFP2Bit)) // "ftosizd"
1394 Mnemonic = "vcvt.s32.f64";
1395 return;
1396 case 's': // 1 string to match.
1397 if (Features.test(Feature_HasVFP2Bit)) // "ftosizs"
1398 Mnemonic = "vcvt.s32.f32";
1399 return;
1400 }
1401 break;
1402 case 'u': // 2 strings to match.
1403 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1404 break;
1405 switch (Mnemonic[6]) {
1406 default: break;
1407 case 'd': // 1 string to match.
1408 if (Features.test(Feature_HasVFP2Bit)) // "ftouizd"
1409 Mnemonic = "vcvt.u32.f64";
1410 return;
1411 case 's': // 1 string to match.
1412 if (Features.test(Feature_HasVFP2Bit)) // "ftouizs"
1413 Mnemonic = "vcvt.u32.f32";
1414 return;
1415 }
1416 break;
1417 }
1418 break;
1419 }
1420 break;
1421 case 'v': // 1 string to match.
1422 if (memcmp(Mnemonic.data()+1, "ldrb.8", 6) != 0)
1423 break;
1424 Mnemonic = "vldrb.u8"; // "vldrb.8"
1425 return;
1426 }
1427 break;
1428 case 8: // 13 strings to match.
1429 switch (Mnemonic[0]) {
1430 default: break;
1431 case 'q': // 1 string to match.
1432 if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0)
1433 break;
1434 Mnemonic = "qsax"; // "qsubaddx"
1435 return;
1436 case 's': // 2 strings to match.
1437 switch (Mnemonic[1]) {
1438 default: break;
1439 case 'a': // 1 string to match.
1440 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1441 break;
1442 Mnemonic = "sasx"; // "saddsubx"
1443 return;
1444 case 's': // 1 string to match.
1445 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1446 break;
1447 Mnemonic = "ssax"; // "ssubaddx"
1448 return;
1449 }
1450 break;
1451 case 'u': // 2 strings to match.
1452 switch (Mnemonic[1]) {
1453 default: break;
1454 case 'a': // 1 string to match.
1455 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1456 break;
1457 Mnemonic = "uasx"; // "uaddsubx"
1458 return;
1459 case 's': // 1 string to match.
1460 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1461 break;
1462 Mnemonic = "usax"; // "usubaddx"
1463 return;
1464 }
1465 break;
1466 case 'v': // 8 strings to match.
1467 switch (Mnemonic[1]) {
1468 default: break;
1469 case 'l': // 6 strings to match.
1470 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1471 break;
1472 switch (Mnemonic[4]) {
1473 default: break;
1474 case 'b': // 3 strings to match.
1475 switch (Mnemonic[5]) {
1476 default: break;
1477 case '.': // 1 string to match.
1478 if (memcmp(Mnemonic.data()+6, "s8", 2) != 0)
1479 break;
1480 Mnemonic = "vldrb.u8"; // "vldrb.s8"
1481 return;
1482 case 'e': // 1 string to match.
1483 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0)
1484 break;
1485 Mnemonic = "vldrbe.u8"; // "vldrbe.8"
1486 return;
1487 case 't': // 1 string to match.
1488 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0)
1489 break;
1490 Mnemonic = "vldrbt.u8"; // "vldrbt.8"
1491 return;
1492 }
1493 break;
1494 case 'd': // 1 string to match.
1495 if (memcmp(Mnemonic.data()+5, ".64", 3) != 0)
1496 break;
1497 Mnemonic = "vldrd.u64"; // "vldrd.64"
1498 return;
1499 case 'h': // 1 string to match.
1500 if (memcmp(Mnemonic.data()+5, ".16", 3) != 0)
1501 break;
1502 Mnemonic = "vldrh.u16"; // "vldrh.16"
1503 return;
1504 case 'w': // 1 string to match.
1505 if (memcmp(Mnemonic.data()+5, ".32", 3) != 0)
1506 break;
1507 Mnemonic = "vldrw.u32"; // "vldrw.32"
1508 return;
1509 }
1510 break;
1511 case 's': // 2 strings to match.
1512 if (memcmp(Mnemonic.data()+2, "trb.", 4) != 0)
1513 break;
1514 switch (Mnemonic[6]) {
1515 default: break;
1516 case 's': // 1 string to match.
1517 if (Mnemonic[7] != '8')
1518 break;
1519 Mnemonic = "vstrb.8"; // "vstrb.s8"
1520 return;
1521 case 'u': // 1 string to match.
1522 if (Mnemonic[7] != '8')
1523 break;
1524 Mnemonic = "vstrb.8"; // "vstrb.u8"
1525 return;
1526 }
1527 break;
1528 }
1529 break;
1530 }
1531 break;
1532 case 9: // 35 strings to match.
1533 switch (Mnemonic[0]) {
1534 default: break;
1535 case 's': // 2 strings to match.
1536 if (Mnemonic[1] != 'h')
1537 break;
1538 switch (Mnemonic[2]) {
1539 default: break;
1540 case 'a': // 1 string to match.
1541 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1542 break;
1543 Mnemonic = "shasx"; // "shaddsubx"
1544 return;
1545 case 's': // 1 string to match.
1546 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1547 break;
1548 Mnemonic = "shsax"; // "shsubaddx"
1549 return;
1550 }
1551 break;
1552 case 'u': // 4 strings to match.
1553 switch (Mnemonic[1]) {
1554 default: break;
1555 case 'h': // 2 strings to match.
1556 switch (Mnemonic[2]) {
1557 default: break;
1558 case 'a': // 1 string to match.
1559 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1560 break;
1561 Mnemonic = "uhasx"; // "uhaddsubx"
1562 return;
1563 case 's': // 1 string to match.
1564 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1565 break;
1566 Mnemonic = "uhsax"; // "uhsubaddx"
1567 return;
1568 }
1569 break;
1570 case 'q': // 2 strings to match.
1571 switch (Mnemonic[2]) {
1572 default: break;
1573 case 'a': // 1 string to match.
1574 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1575 break;
1576 Mnemonic = "uqasx"; // "uqaddsubx"
1577 return;
1578 case 's': // 1 string to match.
1579 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1580 break;
1581 Mnemonic = "uqsax"; // "uqsubaddx"
1582 return;
1583 }
1584 break;
1585 }
1586 break;
1587 case 'v': // 29 strings to match.
1588 switch (Mnemonic[1]) {
1589 default: break;
1590 case 'l': // 14 strings to match.
1591 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1592 break;
1593 switch (Mnemonic[4]) {
1594 default: break;
1595 case 'b': // 2 strings to match.
1596 switch (Mnemonic[5]) {
1597 default: break;
1598 case 'e': // 1 string to match.
1599 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0)
1600 break;
1601 Mnemonic = "vldrbe.u8"; // "vldrbe.s8"
1602 return;
1603 case 't': // 1 string to match.
1604 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0)
1605 break;
1606 Mnemonic = "vldrbt.u8"; // "vldrbt.s8"
1607 return;
1608 }
1609 break;
1610 case 'd': // 4 strings to match.
1611 switch (Mnemonic[5]) {
1612 default: break;
1613 case '.': // 2 strings to match.
1614 switch (Mnemonic[6]) {
1615 default: break;
1616 case 'f': // 1 string to match.
1617 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1618 break;
1619 Mnemonic = "vldrd.u64"; // "vldrd.f64"
1620 return;
1621 case 's': // 1 string to match.
1622 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1623 break;
1624 Mnemonic = "vldrd.u64"; // "vldrd.s64"
1625 return;
1626 }
1627 break;
1628 case 'e': // 1 string to match.
1629 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0)
1630 break;
1631 Mnemonic = "vldrde.u64"; // "vldrde.64"
1632 return;
1633 case 't': // 1 string to match.
1634 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0)
1635 break;
1636 Mnemonic = "vldrdt.u64"; // "vldrdt.64"
1637 return;
1638 }
1639 break;
1640 case 'h': // 4 strings to match.
1641 switch (Mnemonic[5]) {
1642 default: break;
1643 case '.': // 2 strings to match.
1644 switch (Mnemonic[6]) {
1645 default: break;
1646 case 'f': // 1 string to match.
1647 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1648 break;
1649 Mnemonic = "vldrh.u16"; // "vldrh.f16"
1650 return;
1651 case 's': // 1 string to match.
1652 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1653 break;
1654 Mnemonic = "vldrh.u16"; // "vldrh.s16"
1655 return;
1656 }
1657 break;
1658 case 'e': // 1 string to match.
1659 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0)
1660 break;
1661 Mnemonic = "vldrhe.u16"; // "vldrhe.16"
1662 return;
1663 case 't': // 1 string to match.
1664 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0)
1665 break;
1666 Mnemonic = "vldrht.u16"; // "vldrht.16"
1667 return;
1668 }
1669 break;
1670 case 'w': // 4 strings to match.
1671 switch (Mnemonic[5]) {
1672 default: break;
1673 case '.': // 2 strings to match.
1674 switch (Mnemonic[6]) {
1675 default: break;
1676 case 'f': // 1 string to match.
1677 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1678 break;
1679 Mnemonic = "vldrw.u32"; // "vldrw.f32"
1680 return;
1681 case 's': // 1 string to match.
1682 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1683 break;
1684 Mnemonic = "vldrw.u32"; // "vldrw.s32"
1685 return;
1686 }
1687 break;
1688 case 'e': // 1 string to match.
1689 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0)
1690 break;
1691 Mnemonic = "vldrwe.u32"; // "vldrwe.32"
1692 return;
1693 case 't': // 1 string to match.
1694 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0)
1695 break;
1696 Mnemonic = "vldrwt.u32"; // "vldrwt.32"
1697 return;
1698 }
1699 break;
1700 }
1701 break;
1702 case 'm': // 2 strings to match.
1703 if (memcmp(Mnemonic.data()+2, "ovq.f", 5) != 0)
1704 break;
1705 switch (Mnemonic[7]) {
1706 default: break;
1707 case '3': // 1 string to match.
1708 if (Mnemonic[8] != '2')
1709 break;
1710 if (Features.test(Feature_HasNEONBit)) // "vmovq.f32"
1711 Mnemonic = "vmov.f32";
1712 return;
1713 case '6': // 1 string to match.
1714 if (Mnemonic[8] != '4')
1715 break;
1716 if (Features.test(Feature_HasNEONBit)) // "vmovq.f64"
1717 Mnemonic = "vmov.f64";
1718 return;
1719 }
1720 break;
1721 case 's': // 13 strings to match.
1722 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0)
1723 break;
1724 switch (Mnemonic[4]) {
1725 default: break;
1726 case 'b': // 4 strings to match.
1727 switch (Mnemonic[5]) {
1728 default: break;
1729 case 'e': // 2 strings to match.
1730 if (Mnemonic[6] != '.')
1731 break;
1732 switch (Mnemonic[7]) {
1733 default: break;
1734 case 's': // 1 string to match.
1735 if (Mnemonic[8] != '8')
1736 break;
1737 Mnemonic = "vstrbe.8"; // "vstrbe.s8"
1738 return;
1739 case 'u': // 1 string to match.
1740 if (Mnemonic[8] != '8')
1741 break;
1742 Mnemonic = "vstrbe.8"; // "vstrbe.u8"
1743 return;
1744 }
1745 break;
1746 case 't': // 2 strings to match.
1747 if (Mnemonic[6] != '.')
1748 break;
1749 switch (Mnemonic[7]) {
1750 default: break;
1751 case 's': // 1 string to match.
1752 if (Mnemonic[8] != '8')
1753 break;
1754 Mnemonic = "vstrbt.8"; // "vstrbt.s8"
1755 return;
1756 case 'u': // 1 string to match.
1757 if (Mnemonic[8] != '8')
1758 break;
1759 Mnemonic = "vstrbt.8"; // "vstrbt.u8"
1760 return;
1761 }
1762 break;
1763 }
1764 break;
1765 case 'd': // 3 strings to match.
1766 if (Mnemonic[5] != '.')
1767 break;
1768 switch (Mnemonic[6]) {
1769 default: break;
1770 case 'f': // 1 string to match.
1771 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1772 break;
1773 Mnemonic = "vstrd.64"; // "vstrd.f64"
1774 return;
1775 case 's': // 1 string to match.
1776 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1777 break;
1778 Mnemonic = "vstrd.64"; // "vstrd.s64"
1779 return;
1780 case 'u': // 1 string to match.
1781 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1782 break;
1783 Mnemonic = "vstrd.64"; // "vstrd.u64"
1784 return;
1785 }
1786 break;
1787 case 'h': // 3 strings to match.
1788 if (Mnemonic[5] != '.')
1789 break;
1790 switch (Mnemonic[6]) {
1791 default: break;
1792 case 'f': // 1 string to match.
1793 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1794 break;
1795 Mnemonic = "vstrh.16"; // "vstrh.f16"
1796 return;
1797 case 's': // 1 string to match.
1798 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1799 break;
1800 Mnemonic = "vstrh.16"; // "vstrh.s16"
1801 return;
1802 case 'u': // 1 string to match.
1803 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1804 break;
1805 Mnemonic = "vstrh.16"; // "vstrh.u16"
1806 return;
1807 }
1808 break;
1809 case 'w': // 3 strings to match.
1810 if (Mnemonic[5] != '.')
1811 break;
1812 switch (Mnemonic[6]) {
1813 default: break;
1814 case 'f': // 1 string to match.
1815 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1816 break;
1817 Mnemonic = "vstrw.32"; // "vstrw.f32"
1818 return;
1819 case 's': // 1 string to match.
1820 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1821 break;
1822 Mnemonic = "vstrw.32"; // "vstrw.s32"
1823 return;
1824 case 'u': // 1 string to match.
1825 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1826 break;
1827 Mnemonic = "vstrw.32"; // "vstrw.u32"
1828 return;
1829 }
1830 break;
1831 }
1832 break;
1833 }
1834 break;
1835 }
1836 break;
1837 case 10: // 30 strings to match.
1838 if (Mnemonic[0] != 'v')
1839 break;
1840 switch (Mnemonic[1]) {
1841 default: break;
1842 case 'l': // 12 strings to match.
1843 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1844 break;
1845 switch (Mnemonic[4]) {
1846 default: break;
1847 case 'd': // 4 strings to match.
1848 switch (Mnemonic[5]) {
1849 default: break;
1850 case 'e': // 2 strings to match.
1851 if (Mnemonic[6] != '.')
1852 break;
1853 switch (Mnemonic[7]) {
1854 default: break;
1855 case 'f': // 1 string to match.
1856 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1857 break;
1858 Mnemonic = "vldrde.u64"; // "vldrde.f64"
1859 return;
1860 case 's': // 1 string to match.
1861 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1862 break;
1863 Mnemonic = "vldrde.u64"; // "vldrde.s64"
1864 return;
1865 }
1866 break;
1867 case 't': // 2 strings to match.
1868 if (Mnemonic[6] != '.')
1869 break;
1870 switch (Mnemonic[7]) {
1871 default: break;
1872 case 'f': // 1 string to match.
1873 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1874 break;
1875 Mnemonic = "vldrdt.u64"; // "vldrdt.f64"
1876 return;
1877 case 's': // 1 string to match.
1878 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1879 break;
1880 Mnemonic = "vldrdt.u64"; // "vldrdt.s64"
1881 return;
1882 }
1883 break;
1884 }
1885 break;
1886 case 'h': // 4 strings to match.
1887 switch (Mnemonic[5]) {
1888 default: break;
1889 case 'e': // 2 strings to match.
1890 if (Mnemonic[6] != '.')
1891 break;
1892 switch (Mnemonic[7]) {
1893 default: break;
1894 case 'f': // 1 string to match.
1895 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1896 break;
1897 Mnemonic = "vldrhe.u16"; // "vldrhe.f16"
1898 return;
1899 case 's': // 1 string to match.
1900 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1901 break;
1902 Mnemonic = "vldrhe.u16"; // "vldrhe.s16"
1903 return;
1904 }
1905 break;
1906 case 't': // 2 strings to match.
1907 if (Mnemonic[6] != '.')
1908 break;
1909 switch (Mnemonic[7]) {
1910 default: break;
1911 case 'f': // 1 string to match.
1912 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1913 break;
1914 Mnemonic = "vldrht.u16"; // "vldrht.f16"
1915 return;
1916 case 's': // 1 string to match.
1917 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1918 break;
1919 Mnemonic = "vldrht.u16"; // "vldrht.s16"
1920 return;
1921 }
1922 break;
1923 }
1924 break;
1925 case 'w': // 4 strings to match.
1926 switch (Mnemonic[5]) {
1927 default: break;
1928 case 'e': // 2 strings to match.
1929 if (Mnemonic[6] != '.')
1930 break;
1931 switch (Mnemonic[7]) {
1932 default: break;
1933 case 'f': // 1 string to match.
1934 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1935 break;
1936 Mnemonic = "vldrwe.u32"; // "vldrwe.f32"
1937 return;
1938 case 's': // 1 string to match.
1939 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1940 break;
1941 Mnemonic = "vldrwe.u32"; // "vldrwe.s32"
1942 return;
1943 }
1944 break;
1945 case 't': // 2 strings to match.
1946 if (Mnemonic[6] != '.')
1947 break;
1948 switch (Mnemonic[7]) {
1949 default: break;
1950 case 'f': // 1 string to match.
1951 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1952 break;
1953 Mnemonic = "vldrwt.u32"; // "vldrwt.f32"
1954 return;
1955 case 's': // 1 string to match.
1956 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1957 break;
1958 Mnemonic = "vldrwt.u32"; // "vldrwt.s32"
1959 return;
1960 }
1961 break;
1962 }
1963 break;
1964 }
1965 break;
1966 case 's': // 18 strings to match.
1967 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0)
1968 break;
1969 switch (Mnemonic[4]) {
1970 default: break;
1971 case 'd': // 6 strings to match.
1972 switch (Mnemonic[5]) {
1973 default: break;
1974 case 'e': // 3 strings to match.
1975 if (Mnemonic[6] != '.')
1976 break;
1977 switch (Mnemonic[7]) {
1978 default: break;
1979 case 'f': // 1 string to match.
1980 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1981 break;
1982 Mnemonic = "vstrde.64"; // "vstrde.f64"
1983 return;
1984 case 's': // 1 string to match.
1985 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1986 break;
1987 Mnemonic = "vstrde.64"; // "vstrde.s64"
1988 return;
1989 case 'u': // 1 string to match.
1990 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1991 break;
1992 Mnemonic = "vstrde.64"; // "vstrde.u64"
1993 return;
1994 }
1995 break;
1996 case 't': // 3 strings to match.
1997 if (Mnemonic[6] != '.')
1998 break;
1999 switch (Mnemonic[7]) {
2000 default: break;
2001 case 'f': // 1 string to match.
2002 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2003 break;
2004 Mnemonic = "vstrdt.64"; // "vstrdt.f64"
2005 return;
2006 case 's': // 1 string to match.
2007 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2008 break;
2009 Mnemonic = "vstrdt.64"; // "vstrdt.s64"
2010 return;
2011 case 'u': // 1 string to match.
2012 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2013 break;
2014 Mnemonic = "vstrdt.64"; // "vstrdt.u64"
2015 return;
2016 }
2017 break;
2018 }
2019 break;
2020 case 'h': // 6 strings to match.
2021 switch (Mnemonic[5]) {
2022 default: break;
2023 case 'e': // 3 strings to match.
2024 if (Mnemonic[6] != '.')
2025 break;
2026 switch (Mnemonic[7]) {
2027 default: break;
2028 case 'f': // 1 string to match.
2029 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2030 break;
2031 Mnemonic = "vstrhe.16"; // "vstrhe.f16"
2032 return;
2033 case 's': // 1 string to match.
2034 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2035 break;
2036 Mnemonic = "vstrhe.16"; // "vstrhe.s16"
2037 return;
2038 case 'u': // 1 string to match.
2039 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2040 break;
2041 Mnemonic = "vstrhe.16"; // "vstrhe.u16"
2042 return;
2043 }
2044 break;
2045 case 't': // 3 strings to match.
2046 if (Mnemonic[6] != '.')
2047 break;
2048 switch (Mnemonic[7]) {
2049 default: break;
2050 case 'f': // 1 string to match.
2051 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2052 break;
2053 Mnemonic = "vstrht.16"; // "vstrht.f16"
2054 return;
2055 case 's': // 1 string to match.
2056 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2057 break;
2058 Mnemonic = "vstrht.16"; // "vstrht.s16"
2059 return;
2060 case 'u': // 1 string to match.
2061 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2062 break;
2063 Mnemonic = "vstrht.16"; // "vstrht.u16"
2064 return;
2065 }
2066 break;
2067 }
2068 break;
2069 case 'w': // 6 strings to match.
2070 switch (Mnemonic[5]) {
2071 default: break;
2072 case 'e': // 3 strings to match.
2073 if (Mnemonic[6] != '.')
2074 break;
2075 switch (Mnemonic[7]) {
2076 default: break;
2077 case 'f': // 1 string to match.
2078 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2079 break;
2080 Mnemonic = "vstrwe.32"; // "vstrwe.f32"
2081 return;
2082 case 's': // 1 string to match.
2083 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2084 break;
2085 Mnemonic = "vstrwe.32"; // "vstrwe.s32"
2086 return;
2087 case 'u': // 1 string to match.
2088 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2089 break;
2090 Mnemonic = "vstrwe.32"; // "vstrwe.u32"
2091 return;
2092 }
2093 break;
2094 case 't': // 3 strings to match.
2095 if (Mnemonic[6] != '.')
2096 break;
2097 switch (Mnemonic[7]) {
2098 default: break;
2099 case 'f': // 1 string to match.
2100 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2101 break;
2102 Mnemonic = "vstrwt.32"; // "vstrwt.f32"
2103 return;
2104 case 's': // 1 string to match.
2105 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2106 break;
2107 Mnemonic = "vstrwt.32"; // "vstrwt.s32"
2108 return;
2109 case 'u': // 1 string to match.
2110 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2111 break;
2112 Mnemonic = "vstrwt.32"; // "vstrwt.u32"
2113 return;
2114 }
2115 break;
2116 }
2117 break;
2118 }
2119 break;
2120 }
2121 break;
2122 case 11: // 2 strings to match.
2123 if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0)
2124 break;
2125 switch (Mnemonic[8]) {
2126 default: break;
2127 case 'f': // 1 string to match.
2128 if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
2129 break;
2130 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.f32"
2131 Mnemonic = "vrecpe.f32";
2132 return;
2133 case 'u': // 1 string to match.
2134 if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
2135 break;
2136 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.u32"
2137 Mnemonic = "vrecpe.u32";
2138 return;
2139 }
2140 break;
2141 }
2142}
2143
2144enum {
2145 Tie0_1_1,
2146 Tie0_2_2,
2147 Tie0_2_4,
2148 Tie0_3_3,
2149 Tie0_4_4,
2150 Tie0_4_5,
2151 Tie1_1_1,
2152 Tie1_2_2,
2153 Tie1_3_3,
2154 Tie1_4_4,
2155 Tie2_4_4,
2156};
2157
2158static const uint8_t TiedAsmOperandTable[][3] = {
2159 /* Tie0_1_1 */ { 0, 1, 1 },
2160 /* Tie0_2_2 */ { 0, 2, 2 },
2161 /* Tie0_2_4 */ { 0, 2, 4 },
2162 /* Tie0_3_3 */ { 0, 3, 3 },
2163 /* Tie0_4_4 */ { 0, 4, 4 },
2164 /* Tie0_4_5 */ { 0, 4, 5 },
2165 /* Tie1_1_1 */ { 1, 1, 1 },
2166 /* Tie1_2_2 */ { 1, 2, 2 },
2167 /* Tie1_3_3 */ { 1, 3, 3 },
2168 /* Tie1_4_4 */ { 1, 4, 4 },
2169 /* Tie2_4_4 */ { 2, 4, 4 },
2170};
2171
2172namespace {
2173enum OperatorConversionKind {
2174 CVT_Done,
2175 CVT_Reg,
2176 CVT_Tied,
2177 CVT_95_Reg,
2178 CVT_95_addCCOutOperands_95_defaultCCOutOp,
2179 CVT_95_addCondCodeOperands_95_defaultCondCodeOp,
2180 CVT_95_addRegShiftedImmOperands,
2181 CVT_95_addImmOperands,
2182 CVT_95_addT2SOImmNotOperands,
2183 CVT_95_addRegShiftedRegOperands,
2184 CVT_95_addModImmOperands,
2185 CVT_95_addModImmNotOperands,
2186 CVT_95_addImm0_95_508s4Operands,
2187 CVT_regSP,
2188 CVT_95_addImm0_95_508s4NegOperands,
2189 CVT_95_addThumbModImmNeg8_95_255Operands,
2190 CVT_95_addImm0_95_1020s4Operands,
2191 CVT_95_addThumbModImmNeg1_95_7Operands,
2192 CVT_95_addImm0_95_4095NegOperands,
2193 CVT_95_addT2SOImmNegOperands,
2194 CVT_95_addModImmNegOperands,
2195 CVT_95_addUnsignedOffset_95_b8s2Operands,
2196 CVT_95_addAdrLabelOperands,
2197 CVT_imm_95_45,
2198 CVT_cvtThumbBranches,
2199 CVT_95_addARMBranchTargetOperands,
2200 CVT_95_addBitfieldOperands,
2201 CVT_95_addITCondCodeOperands,
2202 CVT_imm_95_0,
2203 CVT_95_addThumbBranchTargetOperands,
2204 CVT_imm_95_15,
2205 CVT_95_addCoprocNumOperands,
2206 CVT_95_addCoprocRegOperands,
2207 CVT_95_addITCondCodeInvOperands,
2208 CVT_imm_95_22,
2209 CVT_95_addRegListWithAPSROperands,
2210 CVT_95_addProcIFlagsOperands,
2211 CVT_imm_95_20,
2212 CVT_regZR,
2213 CVT_imm_95_12,
2214 CVT_95_addMemBarrierOptOperands,
2215 CVT_imm_95_16,
2216 CVT_95_addFPImmOperands,
2217 CVT_95_addDPRRegListOperands,
2218 CVT_imm_95_1,
2219 CVT_95_addInstSyncBarrierOptOperands,
2220 CVT_95_addITMaskOperands,
2221 CVT_95_addMemNoOffsetOperands,
2222 CVT_95_addAddrMode5Operands,
2223 CVT_95_addCoprocOptionOperands,
2224 CVT_95_addPostIdxImm8s4Operands,
2225 CVT_95_addRegListOperands,
2226 CVT_95_addThumbMemPCOperands,
2227 CVT_95_addMemThumbRIs4Operands,
2228 CVT_95_addMemThumbRROperands,
2229 CVT_95_addMemThumbSPIOperands,
2230 CVT_95_addConstPoolAsmImmOperands,
2231 CVT_95_addMemImm12OffsetOperands,
2232 CVT_95_addMemImmOffsetOperands,
2233 CVT_95_addMemRegOffsetOperands,
2234 CVT_95_addMemUImm12OffsetOperands,
2235 CVT_95_addT2MemRegOffsetOperands,
2236 CVT_95_addMemPCRelImm12Operands,
2237 CVT_95_addAM2OffsetImmOperands,
2238 CVT_95_addPostIdxRegShiftedOperands,
2239 CVT_95_addMemThumbRIs1Operands,
2240 CVT_95_addMemImm8s4OffsetOperands,
2241 CVT_95_addAddrMode3Operands,
2242 CVT_95_addAM3OffsetOperands,
2243 CVT_95_addMemImm0_95_1020s4OffsetOperands,
2244 CVT_95_addMemThumbRIs2Operands,
2245 CVT_95_addPostIdxRegOperands,
2246 CVT_95_addPostIdxImm8Operands,
2247 CVT_reg0,
2248 CVT_regCPSR,
2249 CVT_imm_95_14,
2250 CVT_95_addBankedRegOperands,
2251 CVT_95_addMSRMaskOperands,
2252 CVT_cvtThumbMultiply,
2253 CVT_regR8,
2254 CVT_regR0,
2255 CVT_imm_95_29,
2256 CVT_imm_95_13,
2257 CVT_95_addPKHASRImmOperands,
2258 CVT_imm_95_4,
2259 CVT_95_addImm1_95_32Operands,
2260 CVT_imm_95_5,
2261 CVT_95_addMveSaturateOperands,
2262 CVT_95_addShifterImmOperands,
2263 CVT_95_addImm1_95_16Operands,
2264 CVT_95_addRotImmOperands,
2265 CVT_95_addMemTBBOperands,
2266 CVT_95_addMemTBHOperands,
2267 CVT_95_addTraceSyncBarrierOptOperands,
2268 CVT_95_addVPTPredNOperands_95_defaultVPTPredOp,
2269 CVT_95_addVPTPredROperands_95_defaultVPTPredOp,
2270 CVT_95_addNEONi16splatNotOperands,
2271 CVT_95_addNEONi32splatNotOperands,
2272 CVT_95_addNEONi16splatOperands,
2273 CVT_95_addNEONi32splatOperands,
2274 CVT_95_addComplexRotationOddOperands,
2275 CVT_95_addComplexRotationEvenOperands,
2276 CVT_95_addVectorIndex64Operands,
2277 CVT_95_addVectorIndex32Operands,
2278 CVT_95_addFBits16Operands,
2279 CVT_95_addFBits32Operands,
2280 CVT_95_addPowerTwoOperands,
2281 CVT_95_addVectorIndex16Operands,
2282 CVT_95_addVectorIndex8Operands,
2283 CVT_95_addVecListOperands,
2284 CVT_95_addDupAlignedMemory16Operands,
2285 CVT_95_addAlignedMemory64or128Operands,
2286 CVT_95_addAlignedMemory64or128or256Operands,
2287 CVT_95_addAlignedMemory64Operands,
2288 CVT_95_addVecListIndexedOperands,
2289 CVT_95_addAlignedMemory16Operands,
2290 CVT_95_addDupAlignedMemory32Operands,
2291 CVT_95_addAlignedMemory32Operands,
2292 CVT_95_addDupAlignedMemoryNoneOperands,
2293 CVT_95_addAlignedMemoryNoneOperands,
2294 CVT_95_addAlignedMemoryOperands,
2295 CVT_95_addDupAlignedMemory64Operands,
2296 CVT_95_addMVEVecListOperands,
2297 CVT_95_addMemNoOffsetT2Operands,
2298 CVT_95_addMemNoOffsetT2NoSpOperands,
2299 CVT_95_addDupAlignedMemory64or128Operands,
2300 CVT_95_addSPRRegListOperands,
2301 CVT_95_addMemImm7s4OffsetOperands,
2302 CVT_95_addAddrMode5FP16Operands,
2303 CVT_95_addImm7s4Operands,
2304 CVT_95_addMemRegRQOffsetOperands,
2305 CVT_95_addMemNoOffsetTOperands,
2306 CVT_95_addImm7Shift0Operands,
2307 CVT_95_addImm7Shift1Operands,
2308 CVT_95_addImm7Shift2Operands,
2309 CVT_95_addNEONi32vmovOperands,
2310 CVT_95_addNEONvmovi8ReplicateOperands,
2311 CVT_95_addNEONvmovi16ReplicateOperands,
2312 CVT_95_addNEONi32vmovNegOperands,
2313 CVT_95_addNEONvmovi32ReplicateOperands,
2314 CVT_95_addNEONi64splatOperands,
2315 CVT_95_addNEONi8splatOperands,
2316 CVT_95_addMVEVectorIndexOperands,
2317 CVT_95_addMVEPairVectorIndexOperands,
2318 CVT_cvtMVEVMOVQtoDReg,
2319 CVT_95_addNEONinvi8ReplicateOperands,
2320 CVT_95_addFPDRegListWithVPROperands,
2321 CVT_95_addFPSRegListWithVPROperands,
2322 CVT_imm_95_2,
2323 CVT_imm_95_3,
2324 CVT_NUM_CONVERTERS
2325};
2326
2327enum InstructionConversionKind {
2328 Convert_NoOperands,
2329 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1,
2330 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
2331 Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
2332 Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
2333 Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
2334 Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
2335 Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
2336 Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
2337 Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2338 Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2339 Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2340 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2341 Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2342 Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2343 Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
2344 Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0,
2345 Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0,
2346 Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0,
2347 Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
2348 Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0,
2349 Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0,
2350 Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0,
2351 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0,
2352 Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1,
2353 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1,
2354 Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1,
2355 Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0,
2356 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0,
2357 Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0,
2358 Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0,
2359 Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1,
2360 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1,
2361 Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1,
2362 Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0,
2363 Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0,
2364 Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0,
2365 Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0,
2366 Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0,
2367 Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0,
2368 Convert__Reg1_1__Imm0_40951_3__CondCode2_0,
2369 Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
2370 Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
2371 Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0,
2372 Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0,
2373 Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0,
2374 Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0,
2375 Convert__Reg1_1__Imm1_2__CondCode2_0,
2376 Convert__Reg1_1__AdrLabel1_2__CondCode2_0,
2377 Convert__Reg1_2__Imm1_3__CondCode2_0,
2378 Convert__Reg1_1__Tie0_1_1__Reg1_2,
2379 Convert__Reg1_1__Reg1_2,
2380 Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
2381 Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0,
2382 Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1,
2383 Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1,
2384 Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0,
2385 Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0,
2386 Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
2387 Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
2388 Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0,
2389 Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0,
2390 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0,
2391 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0,
2392 Convert__imm_95_45__CondCode2_0,
2393 Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3,
2394 ConvertCustom_cvtThumbBranches,
2395 Convert__ARMBranchTarget1_1__CondCode2_0,
2396 Convert__Imm1_1__Imm1_2__CondCode2_0,
2397 Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0,
2398 Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3,
2399 Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0,
2400 Convert__Imm1_1__Reg1_2__CondCode2_0,
2401 Convert__imm_95_0,
2402 Convert__Imm0_2551_0,
2403 Convert__Imm0_655351_0,
2404 Convert__ARMBranchTarget1_0,
2405 Convert__CondCode2_0__ThumbBranchTarget1_1,
2406 Convert__CondCode2_0__ThumbBranchTarget1_2,
2407 Convert__CondCode2_0__Reg1_1,
2408 Convert__Reg1_0,
2409 Convert__ThumbBranchTarget1_0,
2410 Convert__Reg1_1__CondCode2_0,
2411 Convert__CondCode2_0__ARMBranchTarget1_1,
2412 Convert__imm_95_15__CondCode2_0,
2413 Convert__CondCode2_0,
2414 Convert__Reg1_0__ThumbBranchTarget1_1,
2415 Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2416 Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2417 Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2,
2418 Convert__imm_95_22__CondCode2_0,
2419 Convert__CondCode2_0__RegListWithAPSR1_1,
2420 Convert__Reg1_1__Reg1_2__CondCode2_0,
2421 Convert__Reg1_1__ModImmNeg1_2__CondCode2_0,
2422 Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0,
2423 Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0,
2424 Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0,
2425 Convert__Reg1_1__T2SOImm1_2__CondCode2_0,
2426 Convert__Reg1_1__ModImm1_2__CondCode2_0,
2427 Convert__Reg1_2__Reg1_3__CondCode2_0,
2428 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0,
2429 Convert__Reg1_2__T2SOImm1_3__CondCode2_0,
2430 Convert__Reg1_1__Imm0_2551_2__CondCode2_0,
2431 Convert__Imm1_0__ProcIFlags1_1,
2432 Convert__Imm0_311_0,
2433 Convert__Imm0_311_1,
2434 Convert__Imm1_0__ProcIFlags1_2,
2435 Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2,
2436 Convert__Imm1_0__ProcIFlags1_1__Imm1_2,
2437 Convert__Imm1_0__ProcIFlags1_2__Imm1_3,
2438 Convert__Reg1_0__Reg1_1__Reg1_2,
2439 Convert__imm_95_20__CondCode2_0,
2440 Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3,
2441 Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1,
2442 Convert__Reg1_1__CoprocNum1_0__Imm13b1_2,
2443 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0,
2444 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3,
2445 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0,
2446 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4,
2447 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0,
2448 Convert__Imm0_151_1__CondCode2_0,
2449 Convert__Imm0_151_2__CondCode2_0,
2450 Convert__imm_95_12,
2451 Convert__imm_95_12__CondCode2_0,
2452 Convert__Reg1_0__Reg1_1,
2453 Convert__imm_95_15,
2454 Convert__MemBarrierOpt1_0,
2455 Convert__MemBarrierOpt1_1__CondCode2_0,
2456 Convert__MemBarrierOpt1_2__CondCode2_0,
2457 Convert__imm_95_0__CondCode2_0,
2458 Convert__imm_95_16__CondCode2_0,
2459 Convert__Reg1_1__FPImm1_2__CondCode2_0,
2460 Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3,
2461 Convert__Reg1_1__CondCode2_0__DPRRegList1_2,
2462 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0,
2463 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0,
2464 Convert__Imm0_2391_1__CondCode2_0,
2465 Convert__Imm0_2391_2__CondCode2_0,
2466 Convert__Imm0_631_0,
2467 Convert__Imm0_655351_1,
2468 Convert__InstSyncBarrierOpt1_0,
2469 Convert__InstSyncBarrierOpt1_1__CondCode2_0,
2470 Convert__InstSyncBarrierOpt1_2__CondCode2_0,
2471 Convert__ITCondCode1_1__ITMask1_0,
2472 Convert__Reg1_1__MemNoOffset1_2__CondCode2_0,
2473 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0,
2474 Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0,
2475 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0,
2476 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0,
2477 Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2,
2478 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3,
2479 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3,
2480 Convert__Reg1_1__CondCode2_0__RegList1_2,
2481 Convert__Reg1_1__CondCode2_0__RegList1_3,
2482 Convert__Reg1_2__CondCode2_0__RegList1_3,
2483 Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3,
2484 Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4,
2485 Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0,
2486 Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0,
2487 Convert__Reg1_1__MemThumbRR2_2__CondCode2_0,
2488 Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0,
2489 Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0,
2490 Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0,
2491 Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0,
2492 Convert__Reg1_1__MemRegOffset3_2__CondCode2_0,
2493 Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0,
2494 Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0,
2495 Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0,
2496 Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0,
2497 Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0,
2498 Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0,
2499 Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0,
2500 Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0,
2501 Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0,
2502 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0,
2503 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0,
2504 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0,
2505 Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0,
2506 Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0,
2507 Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0,
2508 Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0,
2509 Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0,
2510 Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0,
2511 Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
2512 Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
2513 Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0,
2514 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0,
2515 Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0,
2516 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0,
2517 Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0,
2518 Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0,
2519 Convert__Reg1_1__AddrMode33_2__CondCode2_0,
2520 Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0,
2521 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0,
2522 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0,
2523 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0,
2524 Convert__LELabel1_0,
2525 Convert__imm_95_0__Reg1_0__LELabel1_1,
2526 Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1,
2527 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1,
2528 Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0,
2529 Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0,
2530 Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
2531 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
2532 Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
2533 Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
2534 Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0,
2535 Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2536 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
2537 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2538 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0,
2539 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2540 Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0,
2541 Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4,
2542 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
2543 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
2544 Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1,
2545 Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0,
2546 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0,
2547 Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0,
2548 Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0,
2549 Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
2550 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
2551 Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
2552 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
2553 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0,
2554 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0,
2555 Convert__Reg1_2__Reg1_3__CondCode2_0__reg0,
2556 Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2557 Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0,
2558 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR,
2559 Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR,
2560 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR,
2561 Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR,
2562 Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0,
2563 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
2564 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2565 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0,
2566 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2567 Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0,
2568 Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4,
2569 Convert__Reg1_1__BankedReg1_2__CondCode2_0,
2570 Convert__Reg1_1__MSRMask1_2__CondCode2_0,
2571 Convert__BankedReg1_1__Reg1_2__CondCode2_0,
2572 Convert__MSRMask1_1__Reg1_2__CondCode2_0,
2573 Convert__MSRMask1_1__ModImm1_2__CondCode2_0,
2574 ConvertCustom_cvtThumbMultiply,
2575 Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0,
2576 Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1,
2577 Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
2578 Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
2579 Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2580 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0,
2581 Convert__regR8__regR8__imm_95_14__reg0,
2582 Convert__regR0__regR0__CondCode2_0__reg0,
2583 Convert__imm_95_29__CondCode2_0,
2584 Convert__imm_95_13__CondCode2_0,
2585 Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3,
2586 Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
2587 Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0,
2588 Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0,
2589 Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0,
2590 Convert__MemImm12Offset2_0,
2591 Convert__MemRegOffset3_0,
2592 Convert__Imm1_1__CondCode2_0,
2593 Convert__MemNegImm8Offset2_1__CondCode2_0,
2594 Convert__MemUImm12Offset2_1__CondCode2_0,
2595 Convert__T2MemRegOffset3_1__CondCode2_0,
2596 Convert__MemPCRelImm121_1__CondCode2_0,
2597 Convert__Imm1_2__CondCode2_0,
2598 Convert__MemNegImm8Offset2_2__CondCode2_0,
2599 Convert__MemUImm12Offset2_2__CondCode2_0,
2600 Convert__T2MemRegOffset3_2__CondCode2_0,
2601 Convert__MemPCRelImm121_2__CondCode2_0,
2602 Convert__CondCode2_0__RegList1_1,
2603 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1,
2604 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2,
2605 Convert__imm_95_4__imm_95_14__reg0,
2606 Convert__imm_95_4,
2607 Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0,
2608 Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0,
2609 Convert__SetEndImm1_0,
2610 Convert__Imm0_11_0,
2611 Convert__imm_95_4__CondCode2_0,
2612 Convert__imm_95_5__CondCode2_0,
2613 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3,
2614 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0,
2615 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0,
2616 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0,
2617 Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0,
2618 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0,
2619 Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0,
2620 Convert__Imm0_311_2,
2621 Convert__Imm0_311_1__CondCode2_0,
2622 Convert__Imm0_311_2__CondCode2_0,
2623 Convert__Imm0_311_3__CondCode2_0,
2624 Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0,
2625 Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0,
2626 Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0,
2627 Convert__imm_95_0__imm_95_14__reg0,
2628 Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0,
2629 Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0,
2630 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0,
2631 Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0,
2632 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0,
2633 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0,
2634 Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0,
2635 Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
2636 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0,
2637 Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
2638 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0,
2639 Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0,
2640 Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0,
2641 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0,
2642 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0,
2643 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0,
2644 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1,
2645 Convert__Imm0_2551_3__CondCode2_0,
2646 Convert__Imm0_2551_1__CondCode2_0,
2647 Convert__Imm24bit1_1__CondCode2_0,
2648 Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
2649 Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0,
2650 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
2651 Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0,
2652 Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
2653 Convert__MemTBB2_1__CondCode2_0,
2654 Convert__MemTBH2_1__CondCode2_0,
2655 Convert__TraceSyncBarrierOpt1_0,
2656 Convert__TraceSyncBarrierOpt1_1__CondCode2_0,
2657 Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0,
2658 Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0,
2659 Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0,
2660 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0,
2661 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0,
2662 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0,
2663 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
2664 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0,
2665 Convert__Reg1_2__Reg1_3__VPTPredR4_0,
2666 Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0,
2667 Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0,
2668 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0,
2669 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0,
2670 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0,
2671 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0,
2672 Convert__Reg1_2__Reg1_3__VPTPredN3_0,
2673 Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0,
2674 Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0,
2675 Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0,
2676 Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0,
2677 Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0,
2678 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0,
2679 Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0,
2680 Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0,
2681 Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0,
2682 Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0,
2683 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0,
2684 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0,
2685 Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4,
2686 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0,
2687 Convert__Reg1_2__Reg1_2__CondCode2_0,
2688 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4,
2689 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5,
2690 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5,
2691 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0,
2692 Convert__Reg1_2__CondCode2_0,
2693 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0,
2694 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0,
2695 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0,
2696 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0,
2697 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0,
2698 Convert__imm_95_0__Reg1_2__VPTPredN3_0,
2699 Convert__Reg1_3__Reg1_4__CondCode2_0,
2700 Convert__Reg1_3__Reg1_4__VPTPredR4_0,
2701 Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0,
2702 Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0,
2703 Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0,
2704 Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0,
2705 Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0,
2706 Convert__Reg1_2__Reg1_3,
2707 Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0,
2708 Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0,
2709 Convert__Reg1_1__CoprocNum1_0__Imm11b1_2,
2710 Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0,
2711 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2,
2712 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0,
2713 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3,
2714 Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0,
2715 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3,
2716 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0,
2717 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4,
2718 Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0,
2719 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4,
2720 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0,
2721 Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0,
2722 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3,
2723 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4,
2724 Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2725 Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2726 Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0,
2727 Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0,
2728 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0,
2729 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0,
2730 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0,
2731 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0,
2732 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0,
2733 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0,
2734 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0,
2735 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0,
2736 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4,
2737 Convert__Reg1_1__Reg1_2__Reg1_3,
2738 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4,
2739 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4,
2740 Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2741 Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0,
2742 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2743 Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2744 Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0,
2745 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0,
2746 Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0,
2747 Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2748 Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2749 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2750 Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2751 Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2752 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2753 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2754 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2755 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
2756 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2757 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0,
2758 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2759 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2760 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2761 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
2762 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
2763 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
2764 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
2765 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
2766 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2767 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2768 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2769 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2770 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2771 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
2772 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2773 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
2774 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2775 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2776 Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0,
2777 Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
2778 Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
2779 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2780 Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0,
2781 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2782 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2783 Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2784 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2785 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2786 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2787 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2788 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0,
2789 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2790 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2791 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
2792 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2793 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2794 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2795 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
2796 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2797 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
2798 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2799 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2800 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2801 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2802 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2803 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
2804 Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2,
2805 Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3,
2806 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2807 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2808 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2809 Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0,
2810 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2811 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2812 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2813 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2814 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2815 Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2816 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2817 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2818 Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2819 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2820 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2821 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2822 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2823 Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0,
2824 Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0,
2825 Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0,
2826 Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0,
2827 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2828 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2829 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2830 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2831 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2832 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2833 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2834 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2835 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2836 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2837 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0,
2838 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2839 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2840 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2841 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2842 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2843 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2844 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2845 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2846 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2847 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2848 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2849 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2850 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2851 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2852 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0,
2853 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0,
2854 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0,
2855 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0,
2856 Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2,
2857 Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3,
2858 Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3,
2859 Convert__Reg1_1__CondCode2_0__SPRRegList1_2,
2860 Convert__MemImm7s4Offset2_2__CondCode2_0,
2861 Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0,
2862 Convert__Reg1_1__AddrMode52_2__CondCode2_0,
2863 Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0,
2864 Convert__Reg1_2__AddrMode52_3__CondCode2_0,
2865 Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0,
2866 Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0,
2867 Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0,
2868 Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0,
2869 Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0,
2870 Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0,
2871 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0,
2872 Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0,
2873 Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0,
2874 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0,
2875 Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0,
2876 Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0,
2877 Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0,
2878 Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0,
2879 Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0,
2880 Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0,
2881 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0,
2882 Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0,
2883 Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0,
2884 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0,
2885 Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0,
2886 Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0,
2887 Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0,
2888 Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0,
2889 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0,
2890 Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0,
2891 Convert__Reg1_1__CondCode2_0__imm_95_0,
2892 Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0,
2893 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2894 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2895 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0,
2896 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0,
2897 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0,
2898 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0,
2899 Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0,
2900 Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0,
2901 Convert__Reg1_2__FPImm1_3__CondCode2_0,
2902 Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0,
2903 Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0,
2904 Convert__Reg1_2__NEONi16splat1_3__CondCode2_0,
2905 Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0,
2906 Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0,
2907 Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0,
2908 Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0,
2909 Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0,
2910 Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0,
2911 Convert__Reg1_2__NEONi64splat1_3__CondCode2_0,
2912 Convert__Reg1_2__NEONi8splat1_3__CondCode2_0,
2913 Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0,
2914 Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0,
2915 Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0,
2916 Convert__Reg1_2__FPImm1_3__VPTPredR4_0,
2917 Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0,
2918 Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0,
2919 Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0,
2920 Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0,
2921 Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0,
2922 Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0,
2923 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0,
2924 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0,
2925 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0,
2926 Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0,
2927 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0,
2928 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0,
2929 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0,
2930 Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0,
2931 ConvertCustom_cvtMVEVMOVQtoDReg,
2932 Convert__Reg1_1__imm_95_0__CondCode2_0,
2933 Convert__imm_95_0__Reg1_2__CondCode2_0,
2934 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2935 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2936 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2937 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2938 Convert__Reg1_1__Reg1_2__VPTPredR4_0,
2939 Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0,
2940 Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0,
2941 Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0,
2942 Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0,
2943 Convert__imm_95_0__imm_95_0__VPTPredN3_0,
2944 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1,
2945 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1,
2946 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2,
2947 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2,
2948 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0,
2949 Convert__ITMask1_0,
2950 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2,
2951 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2,
2952 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2,
2953 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2,
2954 Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0,
2955 Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0,
2956 Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0,
2957 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0,
2958 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0,
2959 Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0,
2960 Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0,
2961 Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0,
2962 Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0,
2963 Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0,
2964 Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0,
2965 Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0,
2966 Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0,
2967 Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0,
2968 Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0,
2969 Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0,
2970 Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0,
2971 Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0,
2972 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,
2973 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0,
2974 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0,
2975 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0,
2976 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0,
2977 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0,
2978 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0,
2979 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0,
2980 Convert__CondCode2_0__FPDRegListWithVPR1_1,
2981 Convert__CondCode2_0__FPSRegListWithVPR1_1,
2982 Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0,
2983 Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0,
2984 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0,
2985 Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0,
2986 Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0,
2987 Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0,
2988 Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0,
2989 Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0,
2990 Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0,
2991 Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0,
2992 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0,
2993 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0,
2994 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0,
2995 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0,
2996 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0,
2997 Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
2998 Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
2999 Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
3000 Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
3001 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
3002 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0,
3003 Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
3004 Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0,
3005 Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
3006 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0,
3007 Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
3008 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0,
3009 Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0,
3010 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
3011 Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
3012 Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0,
3013 Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
3014 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
3015 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0,
3016 Convert__VecListTwoMQ1_1__MemNoOffsetT21_2,
3017 Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3,
3018 Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
3019 Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
3020 Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
3021 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
3022 Convert__VecListFourMQ1_1__MemNoOffsetT21_2,
3023 Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3,
3024 Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0,
3025 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0,
3026 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0,
3027 Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0,
3028 Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0,
3029 Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0,
3030 Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0,
3031 Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0,
3032 Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0,
3033 Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0,
3034 Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0,
3035 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0,
3036 Convert__imm_95_2__CondCode2_0,
3037 Convert__imm_95_3__CondCode2_0,
3038 Convert__Reg1_0__Reg1_1__WLSLabel1_2,
3039 Convert__Reg1_1__Reg1_2__WLSLabel1_3,
3040 Convert__imm_95_1__CondCode2_0,
3041 CVT_NUM_SIGNATURES
3042};
3043
3044} // end anonymous namespace
3045
3046static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = {
3047 // Convert_NoOperands
3048 { CVT_Done },
3049 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1
3050 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3051 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
3052 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3053 // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
3054 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3055 // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
3056 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3057 // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
3058 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3059 // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
3060 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3061 // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
3062 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3063 // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
3064 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3065 // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3066 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3067 // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3068 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3069 // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3070 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3071 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3072 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3073 // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3074 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3075 // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3076 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3077 // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
3078 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3079 // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0
3080 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3081 // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0
3082 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3083 // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0
3084 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3085 // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
3086 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3087 // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0
3088 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3089 // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0
3090 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3091 // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0
3092 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3093 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0
3094 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3095 // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1
3096 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3097 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1
3098 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3099 // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1
3100 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3101 // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0
3102 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3103 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0
3104 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3105 // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0
3106 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3107 // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0
3108 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3109 // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1
3110 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3111 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1
3112 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3113 // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1
3114 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3115 // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0
3116 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3117 // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0
3118 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3119 // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0
3120 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3121 // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0
3122 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3123 // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0
3124 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3125 // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0
3126 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3127 // Convert__Reg1_1__Imm0_40951_3__CondCode2_0
3128 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3129 // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
3130 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3131 // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
3132 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3133 // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0
3134 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3135 // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0
3136 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3137 // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0
3138 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3139 // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0
3140 { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3141 // Convert__Reg1_1__Imm1_2__CondCode2_0
3142 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3143 // Convert__Reg1_1__AdrLabel1_2__CondCode2_0
3144 { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3145 // Convert__Reg1_2__Imm1_3__CondCode2_0
3146 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3147 // Convert__Reg1_1__Tie0_1_1__Reg1_2
3148 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done },
3149 // Convert__Reg1_1__Reg1_2
3150 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3151 // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
3152 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3153 // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0
3154 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3155 // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1
3156 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3157 // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1
3158 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3159 // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0
3160 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3161 // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0
3162 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3163 // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
3164 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3165 // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
3166 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3167 // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0
3168 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3169 // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0
3170 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3171 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0
3172 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3173 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0
3174 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3175 // Convert__imm_95_45__CondCode2_0
3176 { CVT_imm_95_45, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3177 // Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3
3178 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3179 // ConvertCustom_cvtThumbBranches
3180 { CVT_cvtThumbBranches, 0, CVT_Done },
3181 // Convert__ARMBranchTarget1_1__CondCode2_0
3182 { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3183 // Convert__Imm1_1__Imm1_2__CondCode2_0
3184 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3185 // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0
3186 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3187 // Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3
3188 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done },
3189 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0
3190 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3191 // Convert__Imm1_1__Reg1_2__CondCode2_0
3192 { CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3193 // Convert__imm_95_0
3194 { CVT_imm_95_0, 0, CVT_Done },
3195 // Convert__Imm0_2551_0
3196 { CVT_95_addImmOperands, 1, CVT_Done },
3197 // Convert__Imm0_655351_0
3198 { CVT_95_addImmOperands, 1, CVT_Done },
3199 // Convert__ARMBranchTarget1_0
3200 { CVT_95_addARMBranchTargetOperands, 1, CVT_Done },
3201 // Convert__CondCode2_0__ThumbBranchTarget1_1
3202 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
3203 // Convert__CondCode2_0__ThumbBranchTarget1_2
3204 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addThumbBranchTargetOperands, 3, CVT_Done },
3205 // Convert__CondCode2_0__Reg1_1
3206 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 2, CVT_Done },
3207 // Convert__Reg1_0
3208 { CVT_95_Reg, 1, CVT_Done },
3209 // Convert__ThumbBranchTarget1_0
3210 { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done },
3211 // Convert__Reg1_1__CondCode2_0
3212 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3213 // Convert__CondCode2_0__ARMBranchTarget1_1
3214 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done },
3215 // Convert__imm_95_15__CondCode2_0
3216 { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3217 // Convert__CondCode2_0
3218 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3219 // Convert__Reg1_0__ThumbBranchTarget1_1
3220 { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
3221 // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3222 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3223 // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3224 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3225 // Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2
3226 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addITCondCodeInvOperands, 3, CVT_Done },
3227 // Convert__imm_95_22__CondCode2_0
3228 { CVT_imm_95_22, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3229 // Convert__CondCode2_0__RegListWithAPSR1_1
3230 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListWithAPSROperands, 2, CVT_Done },
3231 // Convert__Reg1_1__Reg1_2__CondCode2_0
3232 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3233 // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0
3234 { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3235 // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0
3236 { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3237 // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0
3238 { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3239 // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0
3240 { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3241 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0
3242 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3243 // Convert__Reg1_1__ModImm1_2__CondCode2_0
3244 { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3245 // Convert__Reg1_2__Reg1_3__CondCode2_0
3246 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3247 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0
3248 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3249 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0
3250 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3251 // Convert__Reg1_1__Imm0_2551_2__CondCode2_0
3252 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3253 // Convert__Imm1_0__ProcIFlags1_1
3254 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done },
3255 // Convert__Imm0_311_0
3256 { CVT_95_addImmOperands, 1, CVT_Done },
3257 // Convert__Imm0_311_1
3258 { CVT_95_addImmOperands, 2, CVT_Done },
3259 // Convert__Imm1_0__ProcIFlags1_2
3260 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done },
3261 // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2
3262 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3263 // Convert__Imm1_0__ProcIFlags1_1__Imm1_2
3264 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3265 // Convert__Imm1_0__ProcIFlags1_2__Imm1_3
3266 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3267 // Convert__Reg1_0__Reg1_1__Reg1_2
3268 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3269 // Convert__imm_95_20__CondCode2_0
3270 { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3271 // Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3
3272 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done },
3273 // Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1
3274 { CVT_95_Reg, 1, CVT_regZR, 0, CVT_regZR, 0, CVT_95_addITCondCodeInvOperands, 2, CVT_Done },
3275 // Convert__Reg1_1__CoprocNum1_0__Imm13b1_2
3276 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
3277 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0
3278 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3279 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3
3280 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3281 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0
3282 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3283 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4
3284 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3285 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0
3286 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3287 // Convert__Imm0_151_1__CondCode2_0
3288 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3289 // Convert__Imm0_151_2__CondCode2_0
3290 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3291 // Convert__imm_95_12
3292 { CVT_imm_95_12, 0, CVT_Done },
3293 // Convert__imm_95_12__CondCode2_0
3294 { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3295 // Convert__Reg1_0__Reg1_1
3296 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
3297 // Convert__imm_95_15
3298 { CVT_imm_95_15, 0, CVT_Done },
3299 // Convert__MemBarrierOpt1_0
3300 { CVT_95_addMemBarrierOptOperands, 1, CVT_Done },
3301 // Convert__MemBarrierOpt1_1__CondCode2_0
3302 { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3303 // Convert__MemBarrierOpt1_2__CondCode2_0
3304 { CVT_95_addMemBarrierOptOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3305 // Convert__imm_95_0__CondCode2_0
3306 { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3307 // Convert__imm_95_16__CondCode2_0
3308 { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3309 // Convert__Reg1_1__FPImm1_2__CondCode2_0
3310 { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3311 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3
3312 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done },
3313 // Convert__Reg1_1__CondCode2_0__DPRRegList1_2
3314 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
3315 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0
3316 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3317 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0
3318 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3319 // Convert__Imm0_2391_1__CondCode2_0
3320 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3321 // Convert__Imm0_2391_2__CondCode2_0
3322 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3323 // Convert__Imm0_631_0
3324 { CVT_95_addImmOperands, 1, CVT_Done },
3325 // Convert__Imm0_655351_1
3326 { CVT_95_addImmOperands, 2, CVT_Done },
3327 // Convert__InstSyncBarrierOpt1_0
3328 { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done },
3329 // Convert__InstSyncBarrierOpt1_1__CondCode2_0
3330 { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3331 // Convert__InstSyncBarrierOpt1_2__CondCode2_0
3332 { CVT_95_addInstSyncBarrierOptOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3333 // Convert__ITCondCode1_1__ITMask1_0
3334 { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done },
3335 // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0
3336 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3337 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0
3338 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3339 // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0
3340 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3341 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0
3342 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3343 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0
3344 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3345 // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2
3346 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done },
3347 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3
3348 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done },
3349 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3
3350 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done },
3351 // Convert__Reg1_1__CondCode2_0__RegList1_2
3352 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 3, CVT_Done },
3353 // Convert__Reg1_1__CondCode2_0__RegList1_3
3354 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3355 // Convert__Reg1_2__CondCode2_0__RegList1_3
3356 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3357 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3
3358 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3359 // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4
3360 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 5, CVT_Done },
3361 // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0
3362 { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3363 // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0
3364 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3365 // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0
3366 { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3367 // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0
3368 { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3369 // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0
3370 { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3371 // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0
3372 { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3373 // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0
3374 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3375 // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0
3376 { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3377 // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0
3378 { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3379 // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0
3380 { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3381 // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0
3382 { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3383 // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0
3384 { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3385 // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0
3386 { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3387 // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0
3388 { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3389 // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0
3390 { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3391 // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0
3392 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3393 // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0
3394 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3395 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0
3396 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3397 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0
3398 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3399 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0
3400 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3401 // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0
3402 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3403 // Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0
3404 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3405 // Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0
3406 { CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3407 // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0
3408 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3409 // Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0
3410 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3411 // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0
3412 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3413 // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
3414 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3415 // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
3416 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3417 // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0
3418 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3419 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0
3420 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3421 // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0
3422 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3423 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0
3424 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3425 // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0
3426 { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3427 // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0
3428 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3429 // Convert__Reg1_1__AddrMode33_2__CondCode2_0
3430 { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3431 // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0
3432 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3433 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0
3434 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3435 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0
3436 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3437 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0
3438 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3439 // Convert__LELabel1_0
3440 { CVT_95_addImmOperands, 1, CVT_Done },
3441 // Convert__imm_95_0__Reg1_0__LELabel1_1
3442 { CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3443 // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1
3444 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3445 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1
3446 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3447 // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0
3448 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3449 // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0
3450 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3451 // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
3452 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3453 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
3454 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3455 // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
3456 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3457 // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
3458 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3459 // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0
3460 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3461 // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3462 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3463 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
3464 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3465 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3466 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3467 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0
3468 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
3469 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3470 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3471 // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0
3472 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3473 // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4
3474 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done },
3475 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
3476 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3477 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
3478 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3479 // Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1
3480 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3481 // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0
3482 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3483 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0
3484 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3485 // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0
3486 { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3487 // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0
3488 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3489 // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
3490 { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3491 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
3492 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3493 // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
3494 { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3495 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
3496 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3497 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0
3498 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3499 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0
3500 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3501 // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0
3502 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3503 // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3504 { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3505 // Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0
3506 { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3507 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR
3508 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3509 // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR
3510 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3511 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR
3512 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3513 // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR
3514 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3515 // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0
3516 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3517 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
3518 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3519 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3520 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3521 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0
3522 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
3523 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3524 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3525 // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0
3526 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3527 // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4
3528 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done },
3529 // Convert__Reg1_1__BankedReg1_2__CondCode2_0
3530 { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3531 // Convert__Reg1_1__MSRMask1_2__CondCode2_0
3532 { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3533 // Convert__BankedReg1_1__Reg1_2__CondCode2_0
3534 { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3535 // Convert__MSRMask1_1__Reg1_2__CondCode2_0
3536 { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3537 // Convert__MSRMask1_1__ModImm1_2__CondCode2_0
3538 { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3539 // ConvertCustom_cvtThumbMultiply
3540 { CVT_cvtThumbMultiply, 0, CVT_Done },
3541 // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0
3542 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3543 // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1
3544 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3545 // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
3546 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3547 // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
3548 { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3549 // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3550 { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3551 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0
3552 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3553 // Convert__regR8__regR8__imm_95_14__reg0
3554 { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3555 // Convert__regR0__regR0__CondCode2_0__reg0
3556 { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3557 // Convert__imm_95_29__CondCode2_0
3558 { CVT_imm_95_29, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3559 // Convert__imm_95_13__CondCode2_0
3560 { CVT_imm_95_13, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3561 // Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3
3562 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3563 // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
3564 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3565 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0
3566 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3567 // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0
3568 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3569 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0
3570 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3571 // Convert__MemImm12Offset2_0
3572 { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done },
3573 // Convert__MemRegOffset3_0
3574 { CVT_95_addMemRegOffsetOperands, 1, CVT_Done },
3575 // Convert__Imm1_1__CondCode2_0
3576 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3577 // Convert__MemNegImm8Offset2_1__CondCode2_0
3578 { CVT_95_addMemImmOffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3579 // Convert__MemUImm12Offset2_1__CondCode2_0
3580 { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3581 // Convert__T2MemRegOffset3_1__CondCode2_0
3582 { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3583 // Convert__MemPCRelImm121_1__CondCode2_0
3584 { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3585 // Convert__Imm1_2__CondCode2_0
3586 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3587 // Convert__MemNegImm8Offset2_2__CondCode2_0
3588 { CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3589 // Convert__MemUImm12Offset2_2__CondCode2_0
3590 { CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3591 // Convert__T2MemRegOffset3_2__CondCode2_0
3592 { CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3593 // Convert__MemPCRelImm121_2__CondCode2_0
3594 { CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3595 // Convert__CondCode2_0__RegList1_1
3596 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 2, CVT_Done },
3597 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1
3598 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 2, CVT_Done },
3599 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2
3600 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 3, CVT_Done },
3601 // Convert__imm_95_4__imm_95_14__reg0
3602 { CVT_imm_95_4, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3603 // Convert__imm_95_4
3604 { CVT_imm_95_4, 0, CVT_Done },
3605 // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0
3606 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3607 // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0
3608 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3609 // Convert__SetEndImm1_0
3610 { CVT_95_addImmOperands, 1, CVT_Done },
3611 // Convert__Imm0_11_0
3612 { CVT_95_addImmOperands, 1, CVT_Done },
3613 // Convert__imm_95_4__CondCode2_0
3614 { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3615 // Convert__imm_95_5__CondCode2_0
3616 { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3617 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3
3618 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3619 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0
3620 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3621 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0
3622 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3623 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0
3624 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3625 // Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0
3626 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3627 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0
3628 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addMveSaturateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3629 // Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0
3630 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3631 // Convert__Imm0_311_2
3632 { CVT_95_addImmOperands, 3, CVT_Done },
3633 // Convert__Imm0_311_1__CondCode2_0
3634 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3635 // Convert__Imm0_311_2__CondCode2_0
3636 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3637 // Convert__Imm0_311_3__CondCode2_0
3638 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3639 // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0
3640 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3641 // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0
3642 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3643 // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0
3644 { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3645 // Convert__imm_95_0__imm_95_14__reg0
3646 { CVT_imm_95_0, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3647 // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0
3648 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3649 // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0
3650 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3651 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0
3652 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3653 // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0
3654 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3655 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0
3656 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3657 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0
3658 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3659 // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0
3660 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3661 // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
3662 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3663 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0
3664 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3665 // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
3666 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3667 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0
3668 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3669 // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0
3670 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3671 // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0
3672 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3673 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0
3674 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3675 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0
3676 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3677 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0
3678 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3679 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1
3680 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3681 // Convert__Imm0_2551_3__CondCode2_0
3682 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3683 // Convert__Imm0_2551_1__CondCode2_0
3684 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3685 // Convert__Imm24bit1_1__CondCode2_0
3686 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3687 // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
3688 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3689 // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0
3690 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3691 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
3692 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3693 // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0
3694 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3695 // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
3696 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3697 // Convert__MemTBB2_1__CondCode2_0
3698 { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3699 // Convert__MemTBH2_1__CondCode2_0
3700 { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3701 // Convert__TraceSyncBarrierOpt1_0
3702 { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done },
3703 // Convert__TraceSyncBarrierOpt1_1__CondCode2_0
3704 { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3705 // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0
3706 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3707 // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0
3708 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3709 // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0
3710 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3711 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0
3712 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3713 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0
3714 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3715 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0
3716 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3717 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
3718 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3719 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0
3720 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3721 // Convert__Reg1_2__Reg1_3__VPTPredR4_0
3722 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3723 // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0
3724 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3725 // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0
3726 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3727 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0
3728 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_imm_95_0, 0, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3729 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0
3730 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3731 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0
3732 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3733 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0
3734 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3735 // Convert__Reg1_2__Reg1_3__VPTPredN3_0
3736 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3737 // Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0
3738 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3739 // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0
3740 { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3741 // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0
3742 { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3743 // Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0
3744 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addNEONi16splatNotOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3745 // Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0
3746 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addNEONi32splatNotOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3747 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0
3748 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3749 // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0
3750 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3751 // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0
3752 { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3753 // Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0
3754 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3755 // Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0
3756 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addNEONi32splatOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3757 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0
3758 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3759 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0
3760 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3761 // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4
3762 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
3763 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0
3764 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationOddOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3765 // Convert__Reg1_2__Reg1_2__CondCode2_0
3766 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3767 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4
3768 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
3769 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5
3770 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3771 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5
3772 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3773 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0
3774 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3775 // Convert__Reg1_2__CondCode2_0
3776 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3777 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0
3778 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3779 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0
3780 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3781 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0
3782 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3783 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0
3784 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3785 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0
3786 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3787 // Convert__imm_95_0__Reg1_2__VPTPredN3_0
3788 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3789 // Convert__Reg1_3__Reg1_4__CondCode2_0
3790 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3791 // Convert__Reg1_3__Reg1_4__VPTPredR4_0
3792 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3793 // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0
3794 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3795 // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0
3796 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3797 // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0
3798 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3799 // Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0
3800 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3801 // Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0
3802 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3803 // Convert__Reg1_2__Reg1_3
3804 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3805 // Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0
3806 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3807 // Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0
3808 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3809 // Convert__Reg1_1__CoprocNum1_0__Imm11b1_2
3810 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
3811 // Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0
3812 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3813 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2
3814 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_Done },
3815 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0
3816 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3817 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3
3818 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3819 // Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0
3820 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3821 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3
3822 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3823 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0
3824 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3825 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4
3826 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3827 // Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0
3828 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3829 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4
3830 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3831 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0
3832 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3833 // Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0
3834 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_addPowerTwoOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3835 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3
3836 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3837 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4
3838 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3839 // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
3840 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3841 // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
3842 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3843 // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0
3844 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3845 // Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0
3846 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addPowerTwoOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3847 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0
3848 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3849 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0
3850 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3851 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0
3852 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3853 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0
3854 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3855 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0
3856 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3857 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0
3858 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3859 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0
3860 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3861 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0
3862 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3863 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4
3864 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
3865 // Convert__Reg1_1__Reg1_2__Reg1_3
3866 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3867 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4
3868 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
3869 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4
3870 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3871 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3872 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3873 // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0
3874 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3875 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0
3876 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3877 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3878 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3879 // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0
3880 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3881 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0
3882 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3883 // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0
3884 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3885 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3886 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3887 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3888 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3889 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3890 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3891 // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
3892 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3893 // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
3894 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3895 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
3896 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3897 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3898 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3899 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3900 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3901 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
3902 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3903 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3904 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3905 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0
3906 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3907 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3908 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3909 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3910 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3911 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3912 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3913 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
3914 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3915 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
3916 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3917 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
3918 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3919 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
3920 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3921 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
3922 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3923 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3924 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3925 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3926 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3927 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3928 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3929 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3930 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3931 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3932 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3933 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
3934 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3935 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
3936 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3937 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
3938 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3939 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
3940 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3941 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
3942 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3943 // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0
3944 { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3945 // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
3946 { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3947 // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
3948 { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3949 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3950 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3951 // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0
3952 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3953 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3954 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3955 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3956 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3957 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
3958 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3959 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
3960 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3961 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0
3962 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3963 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0
3964 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3965 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3966 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3967 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0
3968 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3969 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3970 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3971 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3972 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3973 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
3974 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3975 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3976 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3977 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3978 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3979 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3980 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3981 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
3982 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3983 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3984 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3985 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
3986 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3987 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3988 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3989 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3990 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3991 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3992 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3993 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3994 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3995 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3996 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3997 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
3998 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3999 // Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2
4000 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4001 // Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3
4002 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done },
4003 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
4004 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4005 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4006 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4007 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
4008 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4009 // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0
4010 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4011 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4012 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4013 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4014 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4015 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4016 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4017 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4018 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4019 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
4020 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4021 // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4022 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4023 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4024 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4025 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
4026 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4027 // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4028 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4029 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4030 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4031 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4032 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4033 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4034 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4035 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4036 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4037 // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0
4038 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4039 // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0
4040 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4041 // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0
4042 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4043 // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0
4044 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4045 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
4046 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4047 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
4048 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4049 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
4050 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4051 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0
4052 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4053 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
4054 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4055 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
4056 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4057 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
4058 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4059 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
4060 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4061 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
4062 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4063 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
4064 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4065 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0
4066 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4067 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
4068 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4069 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
4070 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4071 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
4072 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4073 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4074 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4075 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
4076 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4077 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
4078 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4079 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4080 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4081 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
4082 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4083 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
4084 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4085 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
4086 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4087 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
4088 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4089 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
4090 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4091 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
4092 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4093 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
4094 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4095 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0
4096 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4097 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0
4098 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4099 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0
4100 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4101 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0
4102 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4103 // Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2
4104 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4105 // Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3
4106 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done },
4107 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3
4108 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done },
4109 // Convert__Reg1_1__CondCode2_0__SPRRegList1_2
4110 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
4111 // Convert__MemImm7s4Offset2_2__CondCode2_0
4112 { CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4113 // Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0
4114 { CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4115 // Convert__Reg1_1__AddrMode52_2__CondCode2_0
4116 { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4117 // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0
4118 { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4119 // Convert__Reg1_2__AddrMode52_3__CondCode2_0
4120 { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4121 // Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0
4122 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4123 // Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0
4124 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4125 // Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0
4126 { CVT_imm_95_0, 0, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4127 // Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0
4128 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4129 // Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0
4130 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4131 // Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0
4132 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4133 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0
4134 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4135 // Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0
4136 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4137 // Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0
4138 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4139 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0
4140 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4141 // Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0
4142 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4143 // Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0
4144 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4145 // Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0
4146 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4147 // Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0
4148 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4149 // Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0
4150 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4151 // Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0
4152 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4153 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0
4154 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4155 // Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0
4156 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4157 // Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0
4158 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4159 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0
4160 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4161 // Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0
4162 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4163 // Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0
4164 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4165 // Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0
4166 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4167 // Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0
4168 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4169 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0
4170 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift2Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4171 // Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0
4172 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4173 // Convert__Reg1_1__CondCode2_0__imm_95_0
4174 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_imm_95_0, 0, CVT_Done },
4175 // Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0
4176 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4177 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
4178 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4179 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
4180 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4181 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0
4182 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4183 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0
4184 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4185 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0
4186 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4187 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0
4188 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4189 // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0
4190 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4191 // Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0
4192 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4193 // Convert__Reg1_2__FPImm1_3__CondCode2_0
4194 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4195 // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0
4196 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4197 // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0
4198 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4199 // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0
4200 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4201 // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0
4202 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4203 // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0
4204 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4205 // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0
4206 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4207 // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0
4208 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4209 // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0
4210 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4211 // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0
4212 { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4213 // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0
4214 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4215 // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0
4216 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4217 // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0
4218 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4219 // Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0
4220 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4221 // Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0
4222 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4223 // Convert__Reg1_2__FPImm1_3__VPTPredR4_0
4224 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4225 // Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0
4226 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4227 // Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0
4228 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4229 // Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0
4230 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4231 // Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0
4232 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4233 // Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0
4234 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4235 // Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0
4236 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4237 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0
4238 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4239 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0
4240 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4241 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0
4242 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4243 // Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0
4244 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4245 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0
4246 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4247 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0
4248 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4249 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0
4250 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4251 // Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0
4252 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_4, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addMVEPairVectorIndexOperands, 3, CVT_95_addMVEPairVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4253 // ConvertCustom_cvtMVEVMOVQtoDReg
4254 { CVT_cvtMVEVMOVQtoDReg, 0, CVT_Done },
4255 // Convert__Reg1_1__imm_95_0__CondCode2_0
4256 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4257 // Convert__imm_95_0__Reg1_2__CondCode2_0
4258 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4259 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
4260 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4261 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
4262 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4263 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
4264 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4265 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
4266 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4267 // Convert__Reg1_1__Reg1_2__VPTPredR4_0
4268 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4269 // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0
4270 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4271 // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0
4272 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4273 // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0
4274 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4275 // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0
4276 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4277 // Convert__imm_95_0__imm_95_0__VPTPredN3_0
4278 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4279 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1
4280 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done },
4281 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1
4282 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done },
4283 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2
4284 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
4285 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2
4286 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
4287 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0
4288 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4289 // Convert__ITMask1_0
4290 { CVT_95_addITMaskOperands, 1, CVT_Done },
4291 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2
4292 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4293 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2
4294 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4295 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2
4296 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4297 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2
4298 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4299 // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0
4300 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4301 // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0
4302 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4303 // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0
4304 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4305 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0
4306 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4307 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0
4308 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4309 // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0
4310 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4311 // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0
4312 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4313 // Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0
4314 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4315 // Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0
4316 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4317 // Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0
4318 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4319 // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0
4320 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4321 // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0
4322 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4323 // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0
4324 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4325 // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0
4326 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4327 // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0
4328 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4329 // Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0
4330 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4331 // Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0
4332 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4333 // Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0
4334 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4335 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0
4336 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4337 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0
4338 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4339 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0
4340 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4341 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0
4342 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4343 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0
4344 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4345 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0
4346 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4347 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0
4348 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4349 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0
4350 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4351 // Convert__CondCode2_0__FPDRegListWithVPR1_1
4352 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addFPDRegListWithVPROperands, 2, CVT_Done },
4353 // Convert__CondCode2_0__FPSRegListWithVPR1_1
4354 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addFPSRegListWithVPROperands, 2, CVT_Done },
4355 // Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0
4356 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4357 // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0
4358 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4359 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0
4360 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4361 // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0
4362 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4363 // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0
4364 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4365 // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0
4366 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4367 // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0
4368 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4369 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0
4370 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4371 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0
4372 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4373 // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0
4374 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4375 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0
4376 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4377 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0
4378 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4379 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0
4380 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4381 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0
4382 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4383 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0
4384 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4385 // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
4386 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4387 // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
4388 { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4389 // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
4390 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4391 // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
4392 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4393 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
4394 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4395 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0
4396 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4397 // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
4398 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4399 // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0
4400 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4401 // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
4402 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4403 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0
4404 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4405 // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
4406 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4407 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0
4408 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4409 // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0
4410 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4411 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
4412 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4413 // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
4414 { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4415 // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0
4416 { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4417 // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
4418 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4419 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
4420 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4421 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0
4422 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4423 // Convert__VecListTwoMQ1_1__MemNoOffsetT21_2
4424 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4425 // Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3
4426 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done },
4427 // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
4428 { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4429 // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
4430 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4431 // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
4432 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4433 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
4434 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4435 // Convert__VecListFourMQ1_1__MemNoOffsetT21_2
4436 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4437 // Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3
4438 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done },
4439 // Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0
4440 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_imm_95_0, 0, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4441 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0
4442 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4443 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0
4444 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4445 // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0
4446 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4447 // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0
4448 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4449 // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0
4450 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4451 // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0
4452 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4453 // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0
4454 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4455 // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0
4456 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4457 // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0
4458 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4459 // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0
4460 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4461 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0
4462 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4463 // Convert__imm_95_2__CondCode2_0
4464 { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4465 // Convert__imm_95_3__CondCode2_0
4466 { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4467 // Convert__Reg1_0__Reg1_1__WLSLabel1_2
4468 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
4469 // Convert__Reg1_1__Reg1_2__WLSLabel1_3
4470 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4471 // Convert__imm_95_1__CondCode2_0
4472 { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4473};
4474
4475void ARMAsmParser::
4476convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
4477 const OperandVector &Operands,
4478 const SmallBitVector &OptionalOperandsMask,
4479 ArrayRef<unsigned> DefaultsOffset) {
4480 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4481 const uint8_t *Converter = ConversionTable[Kind];
4482 Inst.setOpcode(Opcode);
4483 for (const uint8_t *p = Converter; *p; p += 2) {
4484 unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
4485 switch (*p) {
4486 default: llvm_unreachable("invalid conversion entry!");
4487 case CVT_Reg:
4488 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4489 break;
4490 case CVT_Tied: {
4491 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
4492 std::begin(TiedAsmOperandTable)) &&
4493 "Tied operand not found");
4494 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
4495 if (TiedResOpnd != (uint8_t)-1)
4496 Inst.addOperand(Inst.getOperand(TiedResOpnd));
4497 break;
4498 }
4499 case CVT_95_Reg:
4500 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4501 break;
4502 case CVT_95_addCCOutOperands_95_defaultCCOutOp:
4503 if (OptionalOperandsMask[*(p + 1) - 1]) {
4504 defaultCCOutOp()->addCCOutOperands(Inst, 1);
4505 } else {
4506 static_cast<ARMOperand &>(*Operands[OpIdx]).addCCOutOperands(Inst, 1);
4507 }
4508 break;
4509 case CVT_95_addCondCodeOperands_95_defaultCondCodeOp:
4510 if (OptionalOperandsMask[*(p + 1) - 1]) {
4511 defaultCondCodeOp()->addCondCodeOperands(Inst, 2);
4512 } else {
4513 static_cast<ARMOperand &>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2);
4514 }
4515 break;
4516 case CVT_95_addRegShiftedImmOperands:
4517 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2);
4518 break;
4519 case CVT_95_addImmOperands:
4520 static_cast<ARMOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
4521 break;
4522 case CVT_95_addT2SOImmNotOperands:
4523 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1);
4524 break;
4525 case CVT_95_addRegShiftedRegOperands:
4526 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3);
4527 break;
4528 case CVT_95_addModImmOperands:
4529 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmOperands(Inst, 1);
4530 break;
4531 case CVT_95_addModImmNotOperands:
4532 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1);
4533 break;
4534 case CVT_95_addImm0_95_508s4Operands:
4535 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1);
4536 break;
4537 case CVT_regSP:
4538 Inst.addOperand(MCOperand::createReg(ARM::SP));
4539 break;
4540 case CVT_95_addImm0_95_508s4NegOperands:
4541 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1);
4542 break;
4543 case CVT_95_addThumbModImmNeg8_95_255Operands:
4544 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1);
4545 break;
4546 case CVT_95_addImm0_95_1020s4Operands:
4547 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1);
4548 break;
4549 case CVT_95_addThumbModImmNeg1_95_7Operands:
4550 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1);
4551 break;
4552 case CVT_95_addImm0_95_4095NegOperands:
4553 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1);
4554 break;
4555 case CVT_95_addT2SOImmNegOperands:
4556 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1);
4557 break;
4558 case CVT_95_addModImmNegOperands:
4559 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1);
4560 break;
4561 case CVT_95_addUnsignedOffset_95_b8s2Operands:
4562 static_cast<ARMOperand &>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1);
4563 break;
4564 case CVT_95_addAdrLabelOperands:
4565 static_cast<ARMOperand &>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
4566 break;
4567 case CVT_imm_95_45:
4568 Inst.addOperand(MCOperand::createImm(45));
4569 break;
4570 case CVT_cvtThumbBranches:
4571 cvtThumbBranches(Inst, Operands);
4572 break;
4573 case CVT_95_addARMBranchTargetOperands:
4574 static_cast<ARMOperand &>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1);
4575 break;
4576 case CVT_95_addBitfieldOperands:
4577 static_cast<ARMOperand &>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1);
4578 break;
4579 case CVT_95_addITCondCodeOperands:
4580 static_cast<ARMOperand &>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1);
4581 break;
4582 case CVT_imm_95_0:
4583 Inst.addOperand(MCOperand::createImm(0));
4584 break;
4585 case CVT_95_addThumbBranchTargetOperands:
4586 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1);
4587 break;
4588 case CVT_imm_95_15:
4589 Inst.addOperand(MCOperand::createImm(15));
4590 break;
4591 case CVT_95_addCoprocNumOperands:
4592 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1);
4593 break;
4594 case CVT_95_addCoprocRegOperands:
4595 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1);
4596 break;
4597 case CVT_95_addITCondCodeInvOperands:
4598 static_cast<ARMOperand &>(*Operands[OpIdx]).addITCondCodeInvOperands(Inst, 1);
4599 break;
4600 case CVT_imm_95_22:
4601 Inst.addOperand(MCOperand::createImm(22));
4602 break;
4603 case CVT_95_addRegListWithAPSROperands:
4604 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegListWithAPSROperands(Inst, 1);
4605 break;
4606 case CVT_95_addProcIFlagsOperands:
4607 static_cast<ARMOperand &>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1);
4608 break;
4609 case CVT_imm_95_20:
4610 Inst.addOperand(MCOperand::createImm(20));
4611 break;
4612 case CVT_regZR:
4613 Inst.addOperand(MCOperand::createReg(ARM::ZR));
4614 break;
4615 case CVT_imm_95_12:
4616 Inst.addOperand(MCOperand::createImm(12));
4617 break;
4618 case CVT_95_addMemBarrierOptOperands:
4619 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1);
4620 break;
4621 case CVT_imm_95_16:
4622 Inst.addOperand(MCOperand::createImm(16));
4623 break;
4624 case CVT_95_addFPImmOperands:
4625 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
4626 break;
4627 case CVT_95_addDPRRegListOperands:
4628 static_cast<ARMOperand &>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1);
4629 break;
4630 case CVT_imm_95_1:
4631 Inst.addOperand(MCOperand::createImm(1));
4632 break;
4633 case CVT_95_addInstSyncBarrierOptOperands:
4634 static_cast<ARMOperand &>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1);
4635 break;
4636 case CVT_95_addITMaskOperands:
4637 static_cast<ARMOperand &>(*Operands[OpIdx]).addITMaskOperands(Inst, 1);
4638 break;
4639 case CVT_95_addMemNoOffsetOperands:
4640 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1);
4641 break;
4642 case CVT_95_addAddrMode5Operands:
4643 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2);
4644 break;
4645 case CVT_95_addCoprocOptionOperands:
4646 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1);
4647 break;
4648 case CVT_95_addPostIdxImm8s4Operands:
4649 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1);
4650 break;
4651 case CVT_95_addRegListOperands:
4652 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
4653 break;
4654 case CVT_95_addThumbMemPCOperands:
4655 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1);
4656 break;
4657 case CVT_95_addMemThumbRIs4Operands:
4658 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2);
4659 break;
4660 case CVT_95_addMemThumbRROperands:
4661 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2);
4662 break;
4663 case CVT_95_addMemThumbSPIOperands:
4664 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2);
4665 break;
4666 case CVT_95_addConstPoolAsmImmOperands:
4667 static_cast<ARMOperand &>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1);
4668 break;
4669 case CVT_95_addMemImm12OffsetOperands:
4670 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2);
4671 break;
4672 case CVT_95_addMemImmOffsetOperands:
4673 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImmOffsetOperands(Inst, 2);
4674 break;
4675 case CVT_95_addMemRegOffsetOperands:
4676 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3);
4677 break;
4678 case CVT_95_addMemUImm12OffsetOperands:
4679 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2);
4680 break;
4681 case CVT_95_addT2MemRegOffsetOperands:
4682 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3);
4683 break;
4684 case CVT_95_addMemPCRelImm12Operands:
4685 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1);
4686 break;
4687 case CVT_95_addAM2OffsetImmOperands:
4688 static_cast<ARMOperand &>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2);
4689 break;
4690 case CVT_95_addPostIdxRegShiftedOperands:
4691 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2);
4692 break;
4693 case CVT_95_addMemThumbRIs1Operands:
4694 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2);
4695 break;
4696 case CVT_95_addMemImm8s4OffsetOperands:
4697 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2);
4698 break;
4699 case CVT_95_addAddrMode3Operands:
4700 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3);
4701 break;
4702 case CVT_95_addAM3OffsetOperands:
4703 static_cast<ARMOperand &>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2);
4704 break;
4705 case CVT_95_addMemImm0_95_1020s4OffsetOperands:
4706 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2);
4707 break;
4708 case CVT_95_addMemThumbRIs2Operands:
4709 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2);
4710 break;
4711 case CVT_95_addPostIdxRegOperands:
4712 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2);
4713 break;
4714 case CVT_95_addPostIdxImm8Operands:
4715 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1);
4716 break;
4717 case CVT_reg0:
4718 Inst.addOperand(MCOperand::createReg(0));
4719 break;
4720 case CVT_regCPSR:
4721 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
4722 break;
4723 case CVT_imm_95_14:
4724 Inst.addOperand(MCOperand::createImm(14));
4725 break;
4726 case CVT_95_addBankedRegOperands:
4727 static_cast<ARMOperand &>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1);
4728 break;
4729 case CVT_95_addMSRMaskOperands:
4730 static_cast<ARMOperand &>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1);
4731 break;
4732 case CVT_cvtThumbMultiply:
4733 cvtThumbMultiply(Inst, Operands);
4734 break;
4735 case CVT_regR8:
4736 Inst.addOperand(MCOperand::createReg(ARM::R8));
4737 break;
4738 case CVT_regR0:
4739 Inst.addOperand(MCOperand::createReg(ARM::R0));
4740 break;
4741 case CVT_imm_95_29:
4742 Inst.addOperand(MCOperand::createImm(29));
4743 break;
4744 case CVT_imm_95_13:
4745 Inst.addOperand(MCOperand::createImm(13));
4746 break;
4747 case CVT_95_addPKHASRImmOperands:
4748 static_cast<ARMOperand &>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1);
4749 break;
4750 case CVT_imm_95_4:
4751 Inst.addOperand(MCOperand::createImm(4));
4752 break;
4753 case CVT_95_addImm1_95_32Operands:
4754 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1);
4755 break;
4756 case CVT_imm_95_5:
4757 Inst.addOperand(MCOperand::createImm(5));
4758 break;
4759 case CVT_95_addMveSaturateOperands:
4760 static_cast<ARMOperand &>(*Operands[OpIdx]).addMveSaturateOperands(Inst, 1);
4761 break;
4762 case CVT_95_addShifterImmOperands:
4763 static_cast<ARMOperand &>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1);
4764 break;
4765 case CVT_95_addImm1_95_16Operands:
4766 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1);
4767 break;
4768 case CVT_95_addRotImmOperands:
4769 static_cast<ARMOperand &>(*Operands[OpIdx]).addRotImmOperands(Inst, 1);
4770 break;
4771 case CVT_95_addMemTBBOperands:
4772 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2);
4773 break;
4774 case CVT_95_addMemTBHOperands:
4775 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2);
4776 break;
4777 case CVT_95_addTraceSyncBarrierOptOperands:
4778 static_cast<ARMOperand &>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1);
4779 break;
4780 case CVT_95_addVPTPredNOperands_95_defaultVPTPredOp:
4781 if (OptionalOperandsMask[*(p + 1) - 1]) {
4782 defaultVPTPredOp()->addVPTPredNOperands(Inst, 3);
4783 } else {
4784 static_cast<ARMOperand &>(*Operands[OpIdx]).addVPTPredNOperands(Inst, 3);
4785 }
4786 break;
4787 case CVT_95_addVPTPredROperands_95_defaultVPTPredOp:
4788 if (OptionalOperandsMask[*(p + 1) - 1]) {
4789 defaultVPTPredOp()->addVPTPredROperands(Inst, 4);
4790 } else {
4791 static_cast<ARMOperand &>(*Operands[OpIdx]).addVPTPredROperands(Inst, 4);
4792 }
4793 break;
4794 case CVT_95_addNEONi16splatNotOperands:
4795 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1);
4796 break;
4797 case CVT_95_addNEONi32splatNotOperands:
4798 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1);
4799 break;
4800 case CVT_95_addNEONi16splatOperands:
4801 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1);
4802 break;
4803 case CVT_95_addNEONi32splatOperands:
4804 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1);
4805 break;
4806 case CVT_95_addComplexRotationOddOperands:
4807 static_cast<ARMOperand &>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
4808 break;
4809 case CVT_95_addComplexRotationEvenOperands:
4810 static_cast<ARMOperand &>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
4811 break;
4812 case CVT_95_addVectorIndex64Operands:
4813 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1);
4814 break;
4815 case CVT_95_addVectorIndex32Operands:
4816 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1);
4817 break;
4818 case CVT_95_addFBits16Operands:
4819 static_cast<ARMOperand &>(*Operands[OpIdx]).addFBits16Operands(Inst, 1);
4820 break;
4821 case CVT_95_addFBits32Operands:
4822 static_cast<ARMOperand &>(*Operands[OpIdx]).addFBits32Operands(Inst, 1);
4823 break;
4824 case CVT_95_addPowerTwoOperands:
4825 static_cast<ARMOperand &>(*Operands[OpIdx]).addPowerTwoOperands(Inst, 1);
4826 break;
4827 case CVT_95_addVectorIndex16Operands:
4828 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1);
4829 break;
4830 case CVT_95_addVectorIndex8Operands:
4831 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1);
4832 break;
4833 case CVT_95_addVecListOperands:
4834 static_cast<ARMOperand &>(*Operands[OpIdx]).addVecListOperands(Inst, 1);
4835 break;
4836 case CVT_95_addDupAlignedMemory16Operands:
4837 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2);
4838 break;
4839 case CVT_95_addAlignedMemory64or128Operands:
4840 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2);
4841 break;
4842 case CVT_95_addAlignedMemory64or128or256Operands:
4843 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2);
4844 break;
4845 case CVT_95_addAlignedMemory64Operands:
4846 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2);
4847 break;
4848 case CVT_95_addVecListIndexedOperands:
4849 static_cast<ARMOperand &>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2);
4850 break;
4851 case CVT_95_addAlignedMemory16Operands:
4852 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2);
4853 break;
4854 case CVT_95_addDupAlignedMemory32Operands:
4855 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2);
4856 break;
4857 case CVT_95_addAlignedMemory32Operands:
4858 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2);
4859 break;
4860 case CVT_95_addDupAlignedMemoryNoneOperands:
4861 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2);
4862 break;
4863 case CVT_95_addAlignedMemoryNoneOperands:
4864 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2);
4865 break;
4866 case CVT_95_addAlignedMemoryOperands:
4867 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2);
4868 break;
4869 case CVT_95_addDupAlignedMemory64Operands:
4870 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2);
4871 break;
4872 case CVT_95_addMVEVecListOperands:
4873 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEVecListOperands(Inst, 1);
4874 break;
4875 case CVT_95_addMemNoOffsetT2Operands:
4876 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetT2Operands(Inst, 1);
4877 break;
4878 case CVT_95_addMemNoOffsetT2NoSpOperands:
4879 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetT2NoSpOperands(Inst, 1);
4880 break;
4881 case CVT_95_addDupAlignedMemory64or128Operands:
4882 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2);
4883 break;
4884 case CVT_95_addSPRRegListOperands:
4885 static_cast<ARMOperand &>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1);
4886 break;
4887 case CVT_95_addMemImm7s4OffsetOperands:
4888 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm7s4OffsetOperands(Inst, 2);
4889 break;
4890 case CVT_95_addAddrMode5FP16Operands:
4891 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2);
4892 break;
4893 case CVT_95_addImm7s4Operands:
4894 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7s4Operands(Inst, 1);
4895 break;
4896 case CVT_95_addMemRegRQOffsetOperands:
4897 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemRegRQOffsetOperands(Inst, 2);
4898 break;
4899 case CVT_95_addMemNoOffsetTOperands:
4900 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetTOperands(Inst, 1);
4901 break;
4902 case CVT_95_addImm7Shift0Operands:
4903 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift0Operands(Inst, 1);
4904 break;
4905 case CVT_95_addImm7Shift1Operands:
4906 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift1Operands(Inst, 1);
4907 break;
4908 case CVT_95_addImm7Shift2Operands:
4909 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift2Operands(Inst, 1);
4910 break;
4911 case CVT_95_addNEONi32vmovOperands:
4912 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1);
4913 break;
4914 case CVT_95_addNEONvmovi8ReplicateOperands:
4915 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1);
4916 break;
4917 case CVT_95_addNEONvmovi16ReplicateOperands:
4918 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1);
4919 break;
4920 case CVT_95_addNEONi32vmovNegOperands:
4921 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1);
4922 break;
4923 case CVT_95_addNEONvmovi32ReplicateOperands:
4924 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1);
4925 break;
4926 case CVT_95_addNEONi64splatOperands:
4927 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1);
4928 break;
4929 case CVT_95_addNEONi8splatOperands:
4930 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1);
4931 break;
4932 case CVT_95_addMVEVectorIndexOperands:
4933 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEVectorIndexOperands(Inst, 1);
4934 break;
4935 case CVT_95_addMVEPairVectorIndexOperands:
4936 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEPairVectorIndexOperands(Inst, 1);
4937 break;
4938 case CVT_cvtMVEVMOVQtoDReg:
4939 cvtMVEVMOVQtoDReg(Inst, Operands);
4940 break;
4941 case CVT_95_addNEONinvi8ReplicateOperands:
4942 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1);
4943 break;
4944 case CVT_95_addFPDRegListWithVPROperands:
4945 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPDRegListWithVPROperands(Inst, 1);
4946 break;
4947 case CVT_95_addFPSRegListWithVPROperands:
4948 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPSRegListWithVPROperands(Inst, 1);
4949 break;
4950 case CVT_imm_95_2:
4951 Inst.addOperand(MCOperand::createImm(2));
4952 break;
4953 case CVT_imm_95_3:
4954 Inst.addOperand(MCOperand::createImm(3));
4955 break;
4956 }
4957 }
4958}
4959
4960void ARMAsmParser::
4961convertToMapAndConstraints(unsigned Kind,
4962 const OperandVector &Operands) {
4963 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4964 unsigned NumMCOperands = 0;
4965 const uint8_t *Converter = ConversionTable[Kind];
4966 for (const uint8_t *p = Converter; *p; p += 2) {
4967 switch (*p) {
4968 default: llvm_unreachable("invalid conversion entry!");
4969 case CVT_Reg:
4970 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4971 Operands[*(p + 1)]->setConstraint("r");
4972 ++NumMCOperands;
4973 break;
4974 case CVT_Tied:
4975 ++NumMCOperands;
4976 break;
4977 case CVT_95_Reg:
4978 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4979 Operands[*(p + 1)]->setConstraint("r");
4980 NumMCOperands += 1;
4981 break;
4982 case CVT_95_addCCOutOperands_95_defaultCCOutOp:
4983 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4984 Operands[*(p + 1)]->setConstraint("m");
4985 NumMCOperands += 1;
4986 break;
4987 case CVT_95_addCondCodeOperands_95_defaultCondCodeOp:
4988 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4989 Operands[*(p + 1)]->setConstraint("m");
4990 NumMCOperands += 2;
4991 break;
4992 case CVT_95_addRegShiftedImmOperands:
4993 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4994 Operands[*(p + 1)]->setConstraint("m");
4995 NumMCOperands += 2;
4996 break;
4997 case CVT_95_addImmOperands:
4998 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4999 Operands[*(p + 1)]->setConstraint("m");
5000 NumMCOperands += 1;
5001 break;
5002 case CVT_95_addT2SOImmNotOperands:
5003 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5004 Operands[*(p + 1)]->setConstraint("m");
5005 NumMCOperands += 1;
5006 break;
5007 case CVT_95_addRegShiftedRegOperands:
5008 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5009 Operands[*(p + 1)]->setConstraint("m");
5010 NumMCOperands += 3;
5011 break;
5012 case CVT_95_addModImmOperands:
5013 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5014 Operands[*(p + 1)]->setConstraint("m");
5015 NumMCOperands += 1;
5016 break;
5017 case CVT_95_addModImmNotOperands:
5018 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5019 Operands[*(p + 1)]->setConstraint("m");
5020 NumMCOperands += 1;
5021 break;
5022 case CVT_95_addImm0_95_508s4Operands:
5023 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5024 Operands[*(p + 1)]->setConstraint("m");
5025 NumMCOperands += 1;
5026 break;
5027 case CVT_regSP:
5028 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5029 Operands[*(p + 1)]->setConstraint("m");
5030 ++NumMCOperands;
5031 break;
5032 case CVT_95_addImm0_95_508s4NegOperands:
5033 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5034 Operands[*(p + 1)]->setConstraint("m");
5035 NumMCOperands += 1;
5036 break;
5037 case CVT_95_addThumbModImmNeg8_95_255Operands:
5038 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5039 Operands[*(p + 1)]->setConstraint("m");
5040 NumMCOperands += 1;
5041 break;
5042 case CVT_95_addImm0_95_1020s4Operands:
5043 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5044 Operands[*(p + 1)]->setConstraint("m");
5045 NumMCOperands += 1;
5046 break;
5047 case CVT_95_addThumbModImmNeg1_95_7Operands:
5048 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5049 Operands[*(p + 1)]->setConstraint("m");
5050 NumMCOperands += 1;
5051 break;
5052 case CVT_95_addImm0_95_4095NegOperands:
5053 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5054 Operands[*(p + 1)]->setConstraint("m");
5055 NumMCOperands += 1;
5056 break;
5057 case CVT_95_addT2SOImmNegOperands:
5058 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5059 Operands[*(p + 1)]->setConstraint("m");
5060 NumMCOperands += 1;
5061 break;
5062 case CVT_95_addModImmNegOperands:
5063 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5064 Operands[*(p + 1)]->setConstraint("m");
5065 NumMCOperands += 1;
5066 break;
5067 case CVT_95_addUnsignedOffset_95_b8s2Operands:
5068 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5069 Operands[*(p + 1)]->setConstraint("m");
5070 NumMCOperands += 1;
5071 break;
5072 case CVT_95_addAdrLabelOperands:
5073 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5074 Operands[*(p + 1)]->setConstraint("m");
5075 NumMCOperands += 1;
5076 break;
5077 case CVT_imm_95_45:
5078 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5079 Operands[*(p + 1)]->setConstraint("");
5080 ++NumMCOperands;
5081 break;
5082 case CVT_95_addARMBranchTargetOperands:
5083 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5084 Operands[*(p + 1)]->setConstraint("m");
5085 NumMCOperands += 1;
5086 break;
5087 case CVT_95_addBitfieldOperands:
5088 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5089 Operands[*(p + 1)]->setConstraint("m");
5090 NumMCOperands += 1;
5091 break;
5092 case CVT_95_addITCondCodeOperands:
5093 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5094 Operands[*(p + 1)]->setConstraint("m");
5095 NumMCOperands += 1;
5096 break;
5097 case CVT_imm_95_0:
5098 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5099 Operands[*(p + 1)]->setConstraint("");
5100 ++NumMCOperands;
5101 break;
5102 case CVT_95_addThumbBranchTargetOperands:
5103 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5104 Operands[*(p + 1)]->setConstraint("m");
5105 NumMCOperands += 1;
5106 break;
5107 case CVT_imm_95_15:
5108 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5109 Operands[*(p + 1)]->setConstraint("");
5110 ++NumMCOperands;
5111 break;
5112 case CVT_95_addCoprocNumOperands:
5113 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5114 Operands[*(p + 1)]->setConstraint("m");
5115 NumMCOperands += 1;
5116 break;
5117 case CVT_95_addCoprocRegOperands:
5118 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5119 Operands[*(p + 1)]->setConstraint("m");
5120 NumMCOperands += 1;
5121 break;
5122 case CVT_95_addITCondCodeInvOperands:
5123 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5124 Operands[*(p + 1)]->setConstraint("m");
5125 NumMCOperands += 1;
5126 break;
5127 case CVT_imm_95_22:
5128 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5129 Operands[*(p + 1)]->setConstraint("");
5130 ++NumMCOperands;
5131 break;
5132 case CVT_95_addRegListWithAPSROperands:
5133 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5134 Operands[*(p + 1)]->setConstraint("m");
5135 NumMCOperands += 1;
5136 break;
5137 case CVT_95_addProcIFlagsOperands:
5138 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5139 Operands[*(p + 1)]->setConstraint("m");
5140 NumMCOperands += 1;
5141 break;
5142 case CVT_imm_95_20:
5143 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5144 Operands[*(p + 1)]->setConstraint("");
5145 ++NumMCOperands;
5146 break;
5147 case CVT_regZR:
5148 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5149 Operands[*(p + 1)]->setConstraint("m");
5150 ++NumMCOperands;
5151 break;
5152 case CVT_imm_95_12:
5153 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5154 Operands[*(p + 1)]->setConstraint("");
5155 ++NumMCOperands;
5156 break;
5157 case CVT_95_addMemBarrierOptOperands:
5158 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5159 Operands[*(p + 1)]->setConstraint("m");
5160 NumMCOperands += 1;
5161 break;
5162 case CVT_imm_95_16:
5163 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5164 Operands[*(p + 1)]->setConstraint("");
5165 ++NumMCOperands;
5166 break;
5167 case CVT_95_addFPImmOperands:
5168 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5169 Operands[*(p + 1)]->setConstraint("m");
5170 NumMCOperands += 1;
5171 break;
5172 case CVT_95_addDPRRegListOperands:
5173 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5174 Operands[*(p + 1)]->setConstraint("m");
5175 NumMCOperands += 1;
5176 break;
5177 case CVT_imm_95_1:
5178 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5179 Operands[*(p + 1)]->setConstraint("");
5180 ++NumMCOperands;
5181 break;
5182 case CVT_95_addInstSyncBarrierOptOperands:
5183 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5184 Operands[*(p + 1)]->setConstraint("m");
5185 NumMCOperands += 1;
5186 break;
5187 case CVT_95_addITMaskOperands:
5188 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5189 Operands[*(p + 1)]->setConstraint("m");
5190 NumMCOperands += 1;
5191 break;
5192 case CVT_95_addMemNoOffsetOperands:
5193 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5194 Operands[*(p + 1)]->setConstraint("m");
5195 NumMCOperands += 1;
5196 break;
5197 case CVT_95_addAddrMode5Operands:
5198 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5199 Operands[*(p + 1)]->setConstraint("m");
5200 NumMCOperands += 2;
5201 break;
5202 case CVT_95_addCoprocOptionOperands:
5203 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5204 Operands[*(p + 1)]->setConstraint("m");
5205 NumMCOperands += 1;
5206 break;
5207 case CVT_95_addPostIdxImm8s4Operands:
5208 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5209 Operands[*(p + 1)]->setConstraint("m");
5210 NumMCOperands += 1;
5211 break;
5212 case CVT_95_addRegListOperands:
5213 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5214 Operands[*(p + 1)]->setConstraint("m");
5215 NumMCOperands += 1;
5216 break;
5217 case CVT_95_addThumbMemPCOperands:
5218 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5219 Operands[*(p + 1)]->setConstraint("m");
5220 NumMCOperands += 1;
5221 break;
5222 case CVT_95_addMemThumbRIs4Operands:
5223 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5224 Operands[*(p + 1)]->setConstraint("m");
5225 NumMCOperands += 2;
5226 break;
5227 case CVT_95_addMemThumbRROperands:
5228 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5229 Operands[*(p + 1)]->setConstraint("m");
5230 NumMCOperands += 2;
5231 break;
5232 case CVT_95_addMemThumbSPIOperands:
5233 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5234 Operands[*(p + 1)]->setConstraint("m");
5235 NumMCOperands += 2;
5236 break;
5237 case CVT_95_addConstPoolAsmImmOperands:
5238 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5239 Operands[*(p + 1)]->setConstraint("m");
5240 NumMCOperands += 1;
5241 break;
5242 case CVT_95_addMemImm12OffsetOperands:
5243 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5244 Operands[*(p + 1)]->setConstraint("m");
5245 NumMCOperands += 2;
5246 break;
5247 case CVT_95_addMemImmOffsetOperands:
5248 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5249 Operands[*(p + 1)]->setConstraint("m");
5250 NumMCOperands += 2;
5251 break;
5252 case CVT_95_addMemRegOffsetOperands:
5253 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5254 Operands[*(p + 1)]->setConstraint("m");
5255 NumMCOperands += 3;
5256 break;
5257 case CVT_95_addMemUImm12OffsetOperands:
5258 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5259 Operands[*(p + 1)]->setConstraint("m");
5260 NumMCOperands += 2;
5261 break;
5262 case CVT_95_addT2MemRegOffsetOperands:
5263 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5264 Operands[*(p + 1)]->setConstraint("m");
5265 NumMCOperands += 3;
5266 break;
5267 case CVT_95_addMemPCRelImm12Operands:
5268 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5269 Operands[*(p + 1)]->setConstraint("m");
5270 NumMCOperands += 1;
5271 break;
5272 case CVT_95_addAM2OffsetImmOperands:
5273 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5274 Operands[*(p + 1)]->setConstraint("m");
5275 NumMCOperands += 2;
5276 break;
5277 case CVT_95_addPostIdxRegShiftedOperands:
5278 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5279 Operands[*(p + 1)]->setConstraint("m");
5280 NumMCOperands += 2;
5281 break;
5282 case CVT_95_addMemThumbRIs1Operands:
5283 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5284 Operands[*(p + 1)]->setConstraint("m");
5285 NumMCOperands += 2;
5286 break;
5287 case CVT_95_addMemImm8s4OffsetOperands:
5288 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5289 Operands[*(p + 1)]->setConstraint("m");
5290 NumMCOperands += 2;
5291 break;
5292 case CVT_95_addAddrMode3Operands:
5293 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5294 Operands[*(p + 1)]->setConstraint("m");
5295 NumMCOperands += 3;
5296 break;
5297 case CVT_95_addAM3OffsetOperands:
5298 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5299 Operands[*(p + 1)]->setConstraint("m");
5300 NumMCOperands += 2;
5301 break;
5302 case CVT_95_addMemImm0_95_1020s4OffsetOperands:
5303 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5304 Operands[*(p + 1)]->setConstraint("m");
5305 NumMCOperands += 2;
5306 break;
5307 case CVT_95_addMemThumbRIs2Operands:
5308 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5309 Operands[*(p + 1)]->setConstraint("m");
5310 NumMCOperands += 2;
5311 break;
5312 case CVT_95_addPostIdxRegOperands:
5313 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5314 Operands[*(p + 1)]->setConstraint("m");
5315 NumMCOperands += 2;
5316 break;
5317 case CVT_95_addPostIdxImm8Operands:
5318 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5319 Operands[*(p + 1)]->setConstraint("m");
5320 NumMCOperands += 1;
5321 break;
5322 case CVT_reg0:
5323 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5324 Operands[*(p + 1)]->setConstraint("m");
5325 ++NumMCOperands;
5326 break;
5327 case CVT_regCPSR:
5328 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5329 Operands[*(p + 1)]->setConstraint("m");
5330 ++NumMCOperands;
5331 break;
5332 case CVT_imm_95_14:
5333 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5334 Operands[*(p + 1)]->setConstraint("");
5335 ++NumMCOperands;
5336 break;
5337 case CVT_95_addBankedRegOperands:
5338 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5339 Operands[*(p + 1)]->setConstraint("m");
5340 NumMCOperands += 1;
5341 break;
5342 case CVT_95_addMSRMaskOperands:
5343 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5344 Operands[*(p + 1)]->setConstraint("m");
5345 NumMCOperands += 1;
5346 break;
5347 case CVT_regR8:
5348 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5349 Operands[*(p + 1)]->setConstraint("m");
5350 ++NumMCOperands;
5351 break;
5352 case CVT_regR0:
5353 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5354 Operands[*(p + 1)]->setConstraint("m");
5355 ++NumMCOperands;
5356 break;
5357 case CVT_imm_95_29:
5358 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5359 Operands[*(p + 1)]->setConstraint("");
5360 ++NumMCOperands;
5361 break;
5362 case CVT_imm_95_13:
5363 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5364 Operands[*(p + 1)]->setConstraint("");
5365 ++NumMCOperands;
5366 break;
5367 case CVT_95_addPKHASRImmOperands:
5368 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5369 Operands[*(p + 1)]->setConstraint("m");
5370 NumMCOperands += 1;
5371 break;
5372 case CVT_imm_95_4:
5373 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5374 Operands[*(p + 1)]->setConstraint("");
5375 ++NumMCOperands;
5376 break;
5377 case CVT_95_addImm1_95_32Operands:
5378 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5379 Operands[*(p + 1)]->setConstraint("m");
5380 NumMCOperands += 1;
5381 break;
5382 case CVT_imm_95_5:
5383 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5384 Operands[*(p + 1)]->setConstraint("");
5385 ++NumMCOperands;
5386 break;
5387 case CVT_95_addMveSaturateOperands:
5388 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5389 Operands[*(p + 1)]->setConstraint("m");
5390 NumMCOperands += 1;
5391 break;
5392 case CVT_95_addShifterImmOperands:
5393 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5394 Operands[*(p + 1)]->setConstraint("m");
5395 NumMCOperands += 1;
5396 break;
5397 case CVT_95_addImm1_95_16Operands:
5398 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5399 Operands[*(p + 1)]->setConstraint("m");
5400 NumMCOperands += 1;
5401 break;
5402 case CVT_95_addRotImmOperands:
5403 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5404 Operands[*(p + 1)]->setConstraint("m");
5405 NumMCOperands += 1;
5406 break;
5407 case CVT_95_addMemTBBOperands:
5408 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5409 Operands[*(p + 1)]->setConstraint("m");
5410 NumMCOperands += 2;
5411 break;
5412 case CVT_95_addMemTBHOperands:
5413 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5414 Operands[*(p + 1)]->setConstraint("m");
5415 NumMCOperands += 2;
5416 break;
5417 case CVT_95_addTraceSyncBarrierOptOperands:
5418 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5419 Operands[*(p + 1)]->setConstraint("m");
5420 NumMCOperands += 1;
5421 break;
5422 case CVT_95_addVPTPredNOperands_95_defaultVPTPredOp:
5423 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5424 Operands[*(p + 1)]->setConstraint("m");
5425 NumMCOperands += 3;
5426 break;
5427 case CVT_95_addVPTPredROperands_95_defaultVPTPredOp:
5428 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5429 Operands[*(p + 1)]->setConstraint("m");
5430 NumMCOperands += 4;
5431 break;
5432 case CVT_95_addNEONi16splatNotOperands:
5433 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5434 Operands[*(p + 1)]->setConstraint("m");
5435 NumMCOperands += 1;
5436 break;
5437 case CVT_95_addNEONi32splatNotOperands:
5438 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5439 Operands[*(p + 1)]->setConstraint("m");
5440 NumMCOperands += 1;
5441 break;
5442 case CVT_95_addNEONi16splatOperands:
5443 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5444 Operands[*(p + 1)]->setConstraint("m");
5445 NumMCOperands += 1;
5446 break;
5447 case CVT_95_addNEONi32splatOperands:
5448 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5449 Operands[*(p + 1)]->setConstraint("m");
5450 NumMCOperands += 1;
5451 break;
5452 case CVT_95_addComplexRotationOddOperands:
5453 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5454 Operands[*(p + 1)]->setConstraint("m");
5455 NumMCOperands += 1;
5456 break;
5457 case CVT_95_addComplexRotationEvenOperands:
5458 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5459 Operands[*(p + 1)]->setConstraint("m");
5460 NumMCOperands += 1;
5461 break;
5462 case CVT_95_addVectorIndex64Operands:
5463 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5464 Operands[*(p + 1)]->setConstraint("m");
5465 NumMCOperands += 1;
5466 break;
5467 case CVT_95_addVectorIndex32Operands:
5468 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5469 Operands[*(p + 1)]->setConstraint("m");
5470 NumMCOperands += 1;
5471 break;
5472 case CVT_95_addFBits16Operands:
5473 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5474 Operands[*(p + 1)]->setConstraint("m");
5475 NumMCOperands += 1;
5476 break;
5477 case CVT_95_addFBits32Operands:
5478 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5479 Operands[*(p + 1)]->setConstraint("m");
5480 NumMCOperands += 1;
5481 break;
5482 case CVT_95_addPowerTwoOperands:
5483 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5484 Operands[*(p + 1)]->setConstraint("m");
5485 NumMCOperands += 1;
5486 break;
5487 case CVT_95_addVectorIndex16Operands:
5488 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5489 Operands[*(p + 1)]->setConstraint("m");
5490 NumMCOperands += 1;
5491 break;
5492 case CVT_95_addVectorIndex8Operands:
5493 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5494 Operands[*(p + 1)]->setConstraint("m");
5495 NumMCOperands += 1;
5496 break;
5497 case CVT_95_addVecListOperands:
5498 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5499 Operands[*(p + 1)]->setConstraint("m");
5500 NumMCOperands += 1;
5501 break;
5502 case CVT_95_addDupAlignedMemory16Operands:
5503 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5504 Operands[*(p + 1)]->setConstraint("m");
5505 NumMCOperands += 2;
5506 break;
5507 case CVT_95_addAlignedMemory64or128Operands:
5508 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5509 Operands[*(p + 1)]->setConstraint("m");
5510 NumMCOperands += 2;
5511 break;
5512 case CVT_95_addAlignedMemory64or128or256Operands:
5513 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5514 Operands[*(p + 1)]->setConstraint("m");
5515 NumMCOperands += 2;
5516 break;
5517 case CVT_95_addAlignedMemory64Operands:
5518 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5519 Operands[*(p + 1)]->setConstraint("m");
5520 NumMCOperands += 2;
5521 break;
5522 case CVT_95_addVecListIndexedOperands:
5523 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5524 Operands[*(p + 1)]->setConstraint("m");
5525 NumMCOperands += 2;
5526 break;
5527 case CVT_95_addAlignedMemory16Operands:
5528 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5529 Operands[*(p + 1)]->setConstraint("m");
5530 NumMCOperands += 2;
5531 break;
5532 case CVT_95_addDupAlignedMemory32Operands:
5533 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5534 Operands[*(p + 1)]->setConstraint("m");
5535 NumMCOperands += 2;
5536 break;
5537 case CVT_95_addAlignedMemory32Operands:
5538 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5539 Operands[*(p + 1)]->setConstraint("m");
5540 NumMCOperands += 2;
5541 break;
5542 case CVT_95_addDupAlignedMemoryNoneOperands:
5543 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5544 Operands[*(p + 1)]->setConstraint("m");
5545 NumMCOperands += 2;
5546 break;
5547 case CVT_95_addAlignedMemoryNoneOperands:
5548 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5549 Operands[*(p + 1)]->setConstraint("m");
5550 NumMCOperands += 2;
5551 break;
5552 case CVT_95_addAlignedMemoryOperands:
5553 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5554 Operands[*(p + 1)]->setConstraint("m");
5555 NumMCOperands += 2;
5556 break;
5557 case CVT_95_addDupAlignedMemory64Operands:
5558 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5559 Operands[*(p + 1)]->setConstraint("m");
5560 NumMCOperands += 2;
5561 break;
5562 case CVT_95_addMVEVecListOperands:
5563 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5564 Operands[*(p + 1)]->setConstraint("m");
5565 NumMCOperands += 1;
5566 break;
5567 case CVT_95_addMemNoOffsetT2Operands:
5568 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5569 Operands[*(p + 1)]->setConstraint("m");
5570 NumMCOperands += 1;
5571 break;
5572 case CVT_95_addMemNoOffsetT2NoSpOperands:
5573 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5574 Operands[*(p + 1)]->setConstraint("m");
5575 NumMCOperands += 1;
5576 break;
5577 case CVT_95_addDupAlignedMemory64or128Operands:
5578 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5579 Operands[*(p + 1)]->setConstraint("m");
5580 NumMCOperands += 2;
5581 break;
5582 case CVT_95_addSPRRegListOperands:
5583 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5584 Operands[*(p + 1)]->setConstraint("m");
5585 NumMCOperands += 1;
5586 break;
5587 case CVT_95_addMemImm7s4OffsetOperands:
5588 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5589 Operands[*(p + 1)]->setConstraint("m");
5590 NumMCOperands += 2;
5591 break;
5592 case CVT_95_addAddrMode5FP16Operands:
5593 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5594 Operands[*(p + 1)]->setConstraint("m");
5595 NumMCOperands += 2;
5596 break;
5597 case CVT_95_addImm7s4Operands:
5598 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5599 Operands[*(p + 1)]->setConstraint("m");
5600 NumMCOperands += 1;
5601 break;
5602 case CVT_95_addMemRegRQOffsetOperands:
5603 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5604 Operands[*(p + 1)]->setConstraint("m");
5605 NumMCOperands += 2;
5606 break;
5607 case CVT_95_addMemNoOffsetTOperands:
5608 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5609 Operands[*(p + 1)]->setConstraint("m");
5610 NumMCOperands += 1;
5611 break;
5612 case CVT_95_addImm7Shift0Operands:
5613 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5614 Operands[*(p + 1)]->setConstraint("m");
5615 NumMCOperands += 1;
5616 break;
5617 case CVT_95_addImm7Shift1Operands:
5618 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5619 Operands[*(p + 1)]->setConstraint("m");
5620 NumMCOperands += 1;
5621 break;
5622 case CVT_95_addImm7Shift2Operands:
5623 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5624 Operands[*(p + 1)]->setConstraint("m");
5625 NumMCOperands += 1;
5626 break;
5627 case CVT_95_addNEONi32vmovOperands:
5628 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5629 Operands[*(p + 1)]->setConstraint("m");
5630 NumMCOperands += 1;
5631 break;
5632 case CVT_95_addNEONvmovi8ReplicateOperands:
5633 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5634 Operands[*(p + 1)]->setConstraint("m");
5635 NumMCOperands += 1;
5636 break;
5637 case CVT_95_addNEONvmovi16ReplicateOperands:
5638 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5639 Operands[*(p + 1)]->setConstraint("m");
5640 NumMCOperands += 1;
5641 break;
5642 case CVT_95_addNEONi32vmovNegOperands:
5643 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5644 Operands[*(p + 1)]->setConstraint("m");
5645 NumMCOperands += 1;
5646 break;
5647 case CVT_95_addNEONvmovi32ReplicateOperands:
5648 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5649 Operands[*(p + 1)]->setConstraint("m");
5650 NumMCOperands += 1;
5651 break;
5652 case CVT_95_addNEONi64splatOperands:
5653 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5654 Operands[*(p + 1)]->setConstraint("m");
5655 NumMCOperands += 1;
5656 break;
5657 case CVT_95_addNEONi8splatOperands:
5658 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5659 Operands[*(p + 1)]->setConstraint("m");
5660 NumMCOperands += 1;
5661 break;
5662 case CVT_95_addMVEVectorIndexOperands:
5663 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5664 Operands[*(p + 1)]->setConstraint("m");
5665 NumMCOperands += 1;
5666 break;
5667 case CVT_95_addMVEPairVectorIndexOperands:
5668 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5669 Operands[*(p + 1)]->setConstraint("m");
5670 NumMCOperands += 1;
5671 break;
5672 case CVT_95_addNEONinvi8ReplicateOperands:
5673 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5674 Operands[*(p + 1)]->setConstraint("m");
5675 NumMCOperands += 1;
5676 break;
5677 case CVT_95_addFPDRegListWithVPROperands:
5678 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5679 Operands[*(p + 1)]->setConstraint("m");
5680 NumMCOperands += 1;
5681 break;
5682 case CVT_95_addFPSRegListWithVPROperands:
5683 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5684 Operands[*(p + 1)]->setConstraint("m");
5685 NumMCOperands += 1;
5686 break;
5687 case CVT_imm_95_2:
5688 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5689 Operands[*(p + 1)]->setConstraint("");
5690 ++NumMCOperands;
5691 break;
5692 case CVT_imm_95_3:
5693 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5694 Operands[*(p + 1)]->setConstraint("");
5695 ++NumMCOperands;
5696 break;
5697 }
5698 }
5699}
5700
5701namespace {
5702
5703/// MatchClassKind - The kinds of classes which participate in
5704/// instruction matching.
5705enum MatchClassKind {
5706 InvalidMatchClass = 0,
5707 OptionalMatchClass = 1,
5708 MCK__DOT_d, // '.d'
5709 MCK__DOT_f, // '.f'
5710 MCK__DOT_s16, // '.s16'
5711 MCK__DOT_s32, // '.s32'
5712 MCK__DOT_s64, // '.s64'
5713 MCK__DOT_s8, // '.s8'
5714 MCK__DOT_u16, // '.u16'
5715 MCK__DOT_u32, // '.u32'
5716 MCK__DOT_u64, // '.u64'
5717 MCK__DOT_u8, // '.u8'
5718 MCK__DOT_f32, // '.f32'
5719 MCK__DOT_f64, // '.f64'
5720 MCK__DOT_i16, // '.i16'
5721 MCK__DOT_i32, // '.i32'
5722 MCK__DOT_i64, // '.i64'
5723 MCK__DOT_i8, // '.i8'
5724 MCK__DOT_p16, // '.p16'
5725 MCK__DOT_p8, // '.p8'
5726 MCK__EXCLAIM_, // '!'
5727 MCK__HASH_0, // '#0'
5728 MCK__HASH_16, // '#16'
5729 MCK__HASH_8, // '#8'
5730 MCK__DOT_16, // '.16'
5731 MCK__DOT_32, // '.32'
5732 MCK__DOT_64, // '.64'
5733 MCK__DOT_8, // '.8'
5734 MCK__DOT_bf16, // '.bf16'
5735 MCK__DOT_f16, // '.f16'
5736 MCK__DOT_p64, // '.p64'
5737 MCK__DOT_w, // '.w'
5738 MCK__91_, // '['
5739 MCK__93_, // ']'
5740 MCK__94_, // '^'
5741 MCK__123_, // '{'
5742 MCK__125_, // '}'
5743 MCK_LAST_TOKEN = MCK__125_,
5744 MCK_Reg108, // derived register class
5745 MCK_Reg92, // derived register class
5746 MCK_APSR, // register class 'APSR'
5747 MCK_APSR_NZCV, // register class 'APSR_NZCV'
5748 MCK_CCR, // register class 'CCR,CPSR'
5749 MCK_FPCXTRegs, // register class 'FPCXTRegs,FPCXTNS'
5750 MCK_FPCXTS, // register class 'FPCXTS'
5751 MCK_FPEXC, // register class 'FPEXC'
5752 MCK_FPINST, // register class 'FPINST'
5753 MCK_FPINST2, // register class 'FPINST2'
5754 MCK_FPSCR, // register class 'FPSCR'
5755 MCK_FPSCR_NZCVQC, // register class 'FPSCR_NZCVQC'
5756 MCK_FPSID, // register class 'FPSID'
5757 MCK_GPRlr, // register class 'GPRlr,LR'
5758 MCK_GPRsp, // register class 'GPRsp,SP'
5759 MCK_MVFR0, // register class 'MVFR0'
5760 MCK_MVFR1, // register class 'MVFR1'
5761 MCK_MVFR2, // register class 'MVFR2'
5762 MCK_P0, // register class 'P0'
5763 MCK_PC, // register class 'PC'
5764 MCK_R12, // register class 'R12'
5765 MCK_SPSR, // register class 'SPSR'
5766 MCK_VCCR, // register class 'VCCR,VPR'
5767 MCK_cl_FPSCR_NZCV, // register class 'cl_FPSCR_NZCV'
5768 MCK_Reg133, // derived register class
5769 MCK_Reg106, // derived register class
5770 MCK_Reg101, // derived register class
5771 MCK_Reg93, // derived register class
5772 MCK_Reg35, // derived register class
5773 MCK_Reg33, // derived register class
5774 MCK_Reg22, // derived register class
5775 MCK_Reg17, // derived register class
5776 MCK_FP_STATUS_REGS, // register class 'FP_STATUS_REGS'
5777 MCK_Reg134, // derived register class
5778 MCK_Reg121, // derived register class
5779 MCK_Reg116, // derived register class
5780 MCK_Reg107, // derived register class
5781 MCK_Reg105, // derived register class
5782 MCK_Reg94, // derived register class
5783 MCK_Reg78, // derived register class
5784 MCK_Reg21, // derived register class
5785 MCK_Reg135, // derived register class
5786 MCK_Reg126, // derived register class
5787 MCK_Reg122, // derived register class
5788 MCK_Reg117, // derived register class
5789 MCK_Reg102, // derived register class
5790 MCK_Reg95, // derived register class
5791 MCK_Reg79, // derived register class
5792 MCK_Reg34, // derived register class
5793 MCK_Reg25, // derived register class
5794 MCK_Reg23, // derived register class
5795 MCK_Reg18, // derived register class
5796 MCK_QPR_8, // register class 'QPR_8'
5797 MCK_tcGPRnotr12, // register class 'tcGPRnotr12'
5798 MCK_Reg90, // derived register class
5799 MCK_Reg32, // derived register class
5800 MCK_Reg30, // derived register class
5801 MCK_MQQQQPR, // register class 'MQQQQPR'
5802 MCK_tcGPR, // register class 'tcGPR'
5803 MCK_Reg136, // derived register class
5804 MCK_Reg127, // derived register class
5805 MCK_Reg109, // derived register class
5806 MCK_Reg97, // derived register class
5807 MCK_Reg91, // derived register class
5808 MCK_Reg73, // derived register class
5809 MCK_Reg31, // derived register class
5810 MCK_Reg28, // derived register class
5811 MCK_Reg19, // derived register class
5812 MCK_GPRPairnosp, // register class 'GPRPairnosp'
5813 MCK_tGPROdd, // register class 'tGPROdd'
5814 MCK_Reg137, // derived register class
5815 MCK_Reg123, // derived register class
5816 MCK_Reg118, // derived register class
5817 MCK_Reg110, // derived register class
5818 MCK_Reg98, // derived register class
5819 MCK_Reg88, // derived register class
5820 MCK_Reg52, // derived register class
5821 MCK_Reg29, // derived register class
5822 MCK_Reg26, // derived register class
5823 MCK_GPRPair, // register class 'GPRPair'
5824 MCK_MQQPR, // register class 'MQQPR'
5825 MCK_Reg138, // derived register class
5826 MCK_Reg128, // derived register class
5827 MCK_Reg124, // derived register class
5828 MCK_Reg119, // derived register class
5829 MCK_Reg111, // derived register class
5830 MCK_Reg99, // derived register class
5831 MCK_Reg89, // derived register class
5832 MCK_Reg81, // derived register class
5833 MCK_Reg74, // derived register class
5834 MCK_Reg53, // derived register class
5835 MCK_DPR_8, // register class 'DPR_8'
5836 MCK_MQPR, // register class 'MQPR,QPR_VFP2'
5837 MCK_hGPR, // register class 'hGPR'
5838 MCK_tGPR, // register class 'tGPR'
5839 MCK_tGPREven, // register class 'tGPREven'
5840 MCK_tGPRwithpc, // register class 'tGPRwithpc'
5841 MCK_Reg129, // derived register class
5842 MCK_Reg2, // derived register class
5843 MCK_Reg86, // derived register class
5844 MCK_Reg14, // derived register class
5845 MCK_Reg12, // derived register class
5846 MCK_QQQQPR, // register class 'QQQQPR'
5847 MCK_Reg139, // derived register class
5848 MCK_Reg130, // derived register class
5849 MCK_Reg112, // derived register class
5850 MCK_Reg87, // derived register class
5851 MCK_Reg75, // derived register class
5852 MCK_GPRnoip, // register class 'GPRnoip'
5853 MCK_rGPR, // register class 'rGPR'
5854 MCK_Reg125, // derived register class
5855 MCK_Reg120, // derived register class
5856 MCK_Reg113, // derived register class
5857 MCK_Reg84, // derived register class
5858 MCK_Reg50, // derived register class
5859 MCK_GPRnopc, // register class 'GPRnopc'
5860 MCK_GPRnosp, // register class 'GPRnosp'
5861 MCK_GPRwithAPSR_NZCVnosp, // register class 'GPRwithAPSR_NZCVnosp'
5862 MCK_GPRwithAPSRnosp, // register class 'GPRwithAPSRnosp'
5863 MCK_GPRwithZRnosp, // register class 'GPRwithZRnosp'
5864 MCK_QQPR, // register class 'QQPR'
5865 MCK_Reg131, // derived register class
5866 MCK_Reg114, // derived register class
5867 MCK_Reg85, // derived register class
5868 MCK_Reg76, // derived register class
5869 MCK_Reg51, // derived register class
5870 MCK_DPR_VFP2, // register class 'DPR_VFP2'
5871 MCK_GPR, // register class 'GPR'
5872 MCK_GPRwithAPSR, // register class 'GPRwithAPSR'
5873 MCK_GPRwithZR, // register class 'GPRwithZR'
5874 MCK_QPR, // register class 'QPR'
5875 MCK_SPR_8, // register class 'SPR_8'
5876 MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc'
5877 MCK_DQuad, // register class 'DQuad'
5878 MCK_DPairSpc, // register class 'DPairSpc'
5879 MCK_DTriple, // register class 'DTriple'
5880 MCK_DPair, // register class 'DPair'
5881 MCK_DPR, // register class 'DPR'
5882 MCK_HPR, // register class 'HPR,SPR'
5883 MCK_FPWithVPR, // register class 'FPWithVPR'
5884 MCK_LAST_REGISTER = MCK_FPWithVPR,
5885 MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand'
5886 MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand'
5887 MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget'
5888 MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand'
5889 MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand'
5890 MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand'
5891 MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand'
5892 MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand'
5893 MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand'
5894 MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand'
5895 MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand'
5896 MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand'
5897 MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand'
5898 MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand'
5899 MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand'
5900 MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand'
5901 MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand'
5902 MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand'
5903 MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand'
5904 MCK_BankedReg, // user defined class 'BankedRegOperand'
5905 MCK_Bitfield, // user defined class 'BitfieldAsmOperand'
5906 MCK_CCOut, // user defined class 'CCOutOperand'
5907 MCK_CondCode, // user defined class 'CondCodeOperand'
5908 MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand'
5909 MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand'
5910 MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand'
5911 MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand'
5912 MCK_FPDRegListWithVPR, // user defined class 'FPDRegListWithVPRAsmOperand'
5913 MCK_FPImm, // user defined class 'FPImmOperand'
5914 MCK_FPSRegListWithVPR, // user defined class 'FPSRegListWithVPRAsmOperand'
5915 MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand'
5916 MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand'
5917 MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand'
5918 MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand'
5919 MCK_Imm0_255Expr, // user defined class 'Imm0_255ExprAsmOperand'
5920 MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand'
5921 MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand'
5922 MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand'
5923 MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand'
5924 MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand'
5925 MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand'
5926 MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand'
5927 MCK_Imm16, // user defined class 'Imm16AsmOperand'
5928 MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand'
5929 MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand'
5930 MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand'
5931 MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand'
5932 MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand'
5933 MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand'
5934 MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand'
5935 MCK_Imm32, // user defined class 'Imm32AsmOperand'
5936 MCK_Imm8, // user defined class 'Imm8AsmOperand'
5937 MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand'
5938 MCK_Imm, // user defined class 'ImmAsmOperand'
5939 MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand'
5940 MCK_MSRMask, // user defined class 'MSRMaskOperand'
5941 MCK_MVEShiftImm1_15, // user defined class 'MVEShiftImm1_15AsmOperand'
5942 MCK_MVEShiftImm1_7, // user defined class 'MVEShiftImm1_7AsmOperand'
5943 MCK_VIDUP_imm, // user defined class 'MVE_VIDUP_imm_asmoperand'
5944 MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand'
5945 MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand'
5946 MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand'
5947 MCK_MemImm7Shift0Offset, // user defined class 'MemImm7Shift0OffsetAsmOperand'
5948 MCK_MemImm7Shift0OffsetWB, // user defined class 'MemImm7Shift0OffsetWBAsmOperand'
5949 MCK_MemImm7Shift1Offset, // user defined class 'MemImm7Shift1OffsetAsmOperand'
5950 MCK_MemImm7Shift1OffsetWB, // user defined class 'MemImm7Shift1OffsetWBAsmOperand'
5951 MCK_MemImm7Shift2Offset, // user defined class 'MemImm7Shift2OffsetAsmOperand'
5952 MCK_MemImm7Shift2OffsetWB, // user defined class 'MemImm7Shift2OffsetWBAsmOperand'
5953 MCK_MemImm7s4Offset, // user defined class 'MemImm7s4OffsetAsmOperand'
5954 MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand'
5955 MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand'
5956 MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand'
5957 MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand'
5958 MCK_MemNoOffsetT2, // user defined class 'MemNoOffsetT2AsmOperand'
5959 MCK_MemNoOffsetT2NoSp, // user defined class 'MemNoOffsetT2NoSpAsmOperand'
5960 MCK_MemNoOffsetT, // user defined class 'MemNoOffsetTAsmOperand'
5961 MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand'
5962 MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand'
5963 MCK_MemRegQS2Offset, // user defined class 'MemRegQS2OffsetAsmOperand'
5964 MCK_MemRegQS3Offset, // user defined class 'MemRegQS3OffsetAsmOperand'
5965 MCK_MemRegRQS0Offset, // user defined class 'MemRegRQS0OffsetAsmOperand'
5966 MCK_MemRegRQS1Offset, // user defined class 'MemRegRQS1OffsetAsmOperand'
5967 MCK_MemRegRQS2Offset, // user defined class 'MemRegRQS2OffsetAsmOperand'
5968 MCK_MemRegRQS3Offset, // user defined class 'MemRegRQS3OffsetAsmOperand'
5969 MCK_ModImm, // user defined class 'ModImmAsmOperand'
5970 MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand'
5971 MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand'
5972 MCK_MveSaturate, // user defined class 'MveSaturateOperand'
5973 MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand'
5974 MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand'
5975 MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand'
5976 MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand'
5977 MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand'
5978 MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand'
5979 MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand'
5980 MCK_RegList, // user defined class 'RegListAsmOperand'
5981 MCK_RegListWithAPSR, // user defined class 'RegListWithAPSRAsmOperand'
5982 MCK_RotImm, // user defined class 'RotImmAsmOperand'
5983 MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand'
5984 MCK_SetEndImm, // user defined class 'SetEndAsmOperand'
5985 MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand'
5986 MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand'
5987 MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand'
5988 MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget'
5989 MCK_ThumbMemPC, // user defined class 'ThumbMemPC'
5990 MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand'
5991 MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand'
5992 MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand'
5993 MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand'
5994 MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2'
5995 MCK_VPTPredN, // user defined class 'VPTPredNOperand'
5996 MCK_VPTPredR, // user defined class 'VPTPredROperand'
5997 MCK_VecListTwoMQ, // user defined class 'VecList2QAsmOperand'
5998 MCK_VecListFourMQ, // user defined class 'VecList4QAsmOperand'
5999 MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand'
6000 MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand'
6001 MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand'
6002 MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand'
6003 MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand'
6004 MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand'
6005 MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand'
6006 MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand'
6007 MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand'
6008 MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand'
6009 MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand'
6010 MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand'
6011 MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand'
6012 MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand'
6013 MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand'
6014 MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand'
6015 MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand'
6016 MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand'
6017 MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand'
6018 MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand'
6019 MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand'
6020 MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand'
6021 MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand'
6022 MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand'
6023 MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand'
6024 MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand'
6025 MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand'
6026 MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand'
6027 MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand'
6028 MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand'
6029 MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand'
6030 MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand'
6031 MCK_VectorIndex16, // user defined class 'VectorIndex16Operand'
6032 MCK_VectorIndex32, // user defined class 'VectorIndex32Operand'
6033 MCK_VectorIndex64, // user defined class 'VectorIndex64Operand'
6034 MCK_VectorIndex8, // user defined class 'VectorIndex8Operand'
6035 MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand'
6036 MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand'
6037 MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_10210'
6038 MCK_NEONi16invi8Replicate, // user defined class 'anonymous_10212'
6039 MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_10215'
6040 MCK_NEONi32invi8Replicate, // user defined class 'anonymous_10217'
6041 MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_10224'
6042 MCK_NEONi64invi8Replicate, // user defined class 'anonymous_10226'
6043 MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_10237'
6044 MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_10240'
6045 MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_10247'
6046 MCK_MVEVectorIndex4, // user defined class 'anonymous_11524'
6047 MCK_MVEVectorIndex8, // user defined class 'anonymous_11526'
6048 MCK_MVEVectorIndex16, // user defined class 'anonymous_11528'
6049 MCK_MVEVcvtImm32, // user defined class 'anonymous_12270'
6050 MCK_MVEVcvtImm16, // user defined class 'anonymous_12272'
6051 MCK_TMemImm7Shift2Offset, // user defined class 'anonymous_12517'
6052 MCK_TMemImm7Shift0Offset, // user defined class 'anonymous_13262'
6053 MCK_TMemImm7Shift1Offset, // user defined class 'anonymous_13265'
6054 MCK_Imm3b, // user defined class 'anonymous_13797'
6055 MCK_Imm4b, // user defined class 'anonymous_13798'
6056 MCK_Imm6b, // user defined class 'anonymous_13799'
6057 MCK_Imm7b, // user defined class 'anonymous_13800'
6058 MCK_Imm9b, // user defined class 'anonymous_13801'
6059 MCK_Imm11b, // user defined class 'anonymous_13802'
6060 MCK_Imm12b, // user defined class 'anonymous_13803'
6061 MCK_Imm13b, // user defined class 'anonymous_13804'
6062 MCK_MVEPairVectorIndex0, // user defined class 'anonymous_8834'
6063 MCK_MVEPairVectorIndex2, // user defined class 'anonymous_8835'
6064 MCK_ComplexRotationEven, // user defined class 'anonymous_8844'
6065 MCK_ComplexRotationOdd, // user defined class 'anonymous_8845'
6066 MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand'
6067 MCK_FBits16, // user defined class 'fbits16_asm_operand'
6068 MCK_FBits32, // user defined class 'fbits32_asm_operand'
6069 MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand'
6070 MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand'
6071 MCK_ITMask, // user defined class 'it_mask_asmoperand'
6072 MCK_ITCondCode, // user defined class 'it_pred_asmoperand'
6073 MCK_LELabel, // user defined class 'lelabel_u11_asmoperand'
6074 MCK_MVELongShift, // user defined class 'mve_shift_imm'
6075 MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand'
6076 MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand'
6077 MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand'
6078 MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand'
6079 MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand'
6080 MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand'
6081 MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand'
6082 MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand'
6083 MCK_CondCodeNoAL, // user defined class 'pred_noal_asmoperand'
6084 MCK_CondCodeNoALInv, // user defined class 'pred_noal_inv_asmoperand'
6085 MCK_CondCodeRestrictedFP, // user defined class 'pred_restricted_fp_asmoperand'
6086 MCK_CondCodeRestrictedI, // user defined class 'pred_restricted_i_asmoperand'
6087 MCK_CondCodeRestrictedS, // user defined class 'pred_restricted_s_asmoperand'
6088 MCK_CondCodeRestrictedU, // user defined class 'pred_restricted_u_asmoperand'
6089 MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand'
6090 MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand'
6091 MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand'
6092 MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand'
6093 MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand'
6094 MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand'
6095 MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand'
6096 MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand'
6097 MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand'
6098 MCK_Imm7s4, // user defined class 't2am_imm7s4_offset_asmoperand'
6099 MCK_Imm7Shift0, // user defined class 't2am_imm7shift0OffsetAsmOperand'
6100 MCK_Imm7Shift1, // user defined class 't2am_imm7shift1OffsetAsmOperand'
6101 MCK_Imm7Shift2, // user defined class 't2am_imm7shift2OffsetAsmOperand'
6102 MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand'
6103 MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand'
6104 MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand'
6105 MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand'
6106 MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand'
6107 MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand'
6108 MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand'
6109 MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand'
6110 MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand'
6111 MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand'
6112 MCK_WLSLabel, // user defined class 'wlslabel_u11_asmoperand'
6113 NumMatchClassKinds
6114};
6115
6116} // end anonymous namespace
6117
6118static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) {
6119 switch (MatchResult) {
6120 case ARMAsmParser::Match_GPRsp:
6121 return "operand must be a register sp";
6122 case ARMAsmParser::Match_QPR_8:
6123 return "operand must be a register in range [q0, q3]";
6124 case ARMAsmParser::Match_tGPROdd:
6125 return "operand must be an odd-numbered register in range [r1,r11]";
6126 case ARMAsmParser::Match_DPR_8:
6127 return "operand must be a register in range [d0, d7]";
6128 case ARMAsmParser::Match_QPR_VFP2:
6129 return "operand must be a register in range [q0, q7]";
6130 case ARMAsmParser::Match_hGPR:
6131 return "operand must be a register in range [r8, r15]";
6132 case ARMAsmParser::Match_tGPR:
6133 return "operand must be a register in range [r0, r7]";
6134 case ARMAsmParser::Match_tGPREven:
6135 return "operand must be an even-numbered register";
6136 case ARMAsmParser::Match_GPRnoip:
6137 return "operand must be a register in range [r0, r14]";
6138 case ARMAsmParser::Match_GPRnopc:
6139 return "operand must be a register in range [r0, r14]";
6140 case ARMAsmParser::Match_GPRnosp:
6141 return "operand must be a register in range [r0, r12] or LR or PC";
6142 case ARMAsmParser::Match_GPRwithAPSR_NZCVnosp:
6143 return "operand must be a register in the range [r0, r12], r14 or apsr_nzcv";
6144 case ARMAsmParser::Match_GPRwithZRnosp:
6145 return "operand must be a register in range [r0, r12] or r14 or zr";
6146 case ARMAsmParser::Match_DPR_VFP2:
6147 return "operand must be a register in range [d0, d15]";
6148 case ARMAsmParser::Match_GPR:
6149 return "operand must be a register in range [r0, r15]";
6150 case ARMAsmParser::Match_GPRwithAPSR:
6151 return "operand must be a register in range [r0, r14] or apsr_nzcv";
6152 case ARMAsmParser::Match_GPRwithZR:
6153 return "operand must be a register in range [r0, r14] or zr";
6154 case ARMAsmParser::Match_QPR:
6155 return "operand must be a register in range [q0, q15]";
6156 case ARMAsmParser::Match_SPR_8:
6157 return "operand must be a register in range [s0, s15]";
6158 case ARMAsmParser::Match_SPR:
6159 return "operand must be a register in range [s0, s31]";
6160 case ARMAsmParser::Match_AlignedMemory16:
6161 return "alignment must be 16 or omitted";
6162 case ARMAsmParser::Match_AlignedMemory32:
6163 return "alignment must be 32 or omitted";
6164 case ARMAsmParser::Match_AlignedMemory64:
6165 return "alignment must be 64 or omitted";
6166 case ARMAsmParser::Match_AlignedMemory64or128:
6167 return "alignment must be 64, 128 or omitted";
6168 case ARMAsmParser::Match_AlignedMemory64or128or256:
6169 return "alignment must be 64, 128, 256 or omitted";
6170 case ARMAsmParser::Match_AlignedMemoryNone:
6171 return "alignment must be omitted";
6172 case ARMAsmParser::Match_DupAlignedMemory16:
6173 return "alignment must be 16 or omitted";
6174 case ARMAsmParser::Match_DupAlignedMemory32:
6175 return "alignment must be 32 or omitted";
6176 case ARMAsmParser::Match_DupAlignedMemory64:
6177 return "alignment must be 64 or omitted";
6178 case ARMAsmParser::Match_DupAlignedMemory64or128:
6179 return "alignment must be 64, 128 or omitted";
6180 case ARMAsmParser::Match_DupAlignedMemoryNone:
6181 return "alignment must be omitted";
6182 case ARMAsmParser::Match_Imm0_15:
6183 return "operand must be an immediate in the range [0,15]";
6184 case ARMAsmParser::Match_Imm0_1:
6185 return "operand must be an immediate in the range [0,1]";
6186 case ARMAsmParser::Match_Imm0_239:
6187 return "operand must be an immediate in the range [0,239]";
6188 case ARMAsmParser::Match_Imm0_255:
6189 return "operand must be an immediate in the range [0,255]";
6190 case ARMAsmParser::Match_Imm0_255Expr:
6191 return "operand must be an immediate in the range [0,255] or a relocatable expression";
6192 case ARMAsmParser::Match_Imm0_31:
6193 return "operand must be an immediate in the range [0,31]";
6194 case ARMAsmParser::Match_Imm0_32:
6195 return "operand must be an immediate in the range [0,32]";
6196 case ARMAsmParser::Match_Imm0_3:
6197 return "operand must be an immediate in the range [0,3]";
6198 case ARMAsmParser::Match_Imm0_63:
6199 return "operand must be an immediate in the range [0,63]";
6200 case ARMAsmParser::Match_Imm0_65535:
6201 return "operand must be an immediate in the range [0,65535]";
6202 case ARMAsmParser::Match_Imm0_65535Expr:
6203 return "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
6204 case ARMAsmParser::Match_Imm0_7:
6205 return "operand must be an immediate in the range [0,7]";
6206 case ARMAsmParser::Match_Imm16:
6207 return "operand must be an immediate in the range [16,16]";
6208 case ARMAsmParser::Match_Imm1_15:
6209 return "operand must be an immediate in the range [1,15]";
6210 case ARMAsmParser::Match_ImmRange1_16:
6211 return "operand must be an immediate in the range [1,16]";
6212 case ARMAsmParser::Match_Imm1_31:
6213 return "operand must be an immediate in the range [1,31]";
6214 case ARMAsmParser::Match_ImmRange1_32:
6215 return "operand must be an immediate in the range [1,32]";
6216 case ARMAsmParser::Match_Imm1_7:
6217 return "operand must be an immediate in the range [1,7]";
6218 case ARMAsmParser::Match_Imm24bit:
6219 return "operand must be an immediate in the range [0,0xffffff]";
6220 case ARMAsmParser::Match_Imm256_65535Expr:
6221 return "operand must be an immediate in the range [256,65535]";
6222 case ARMAsmParser::Match_Imm32:
6223 return "operand must be an immediate in the range [32,32]";
6224 case ARMAsmParser::Match_Imm8:
6225 return "operand must be an immediate in the range [8,8]";
6226 case ARMAsmParser::Match_Imm8_255:
6227 return "operand must be an immediate in the range [8,255]";
6228 case ARMAsmParser::Match_MVEShiftImm1_15:
6229 return "operand must be an immediate in the range [1,16]";
6230 case ARMAsmParser::Match_MVEShiftImm1_7:
6231 return "operand must be an immediate in the range [1,8]";
6232 case ARMAsmParser::Match_VIDUP_imm:
6233 return "vector increment immediate must be 1, 2, 4 or 8";
6234 case ARMAsmParser::Match_MveSaturate:
6235 return "saturate operand must be 48 or 64";
6236 case ARMAsmParser::Match_PKHLSLImm:
6237 return "operand must be an immediate in the range [0,31]";
6238 case ARMAsmParser::Match_SPRRegList:
6239 return "operand must be a list of registers in range [s0, s31]";
6240 case ARMAsmParser::Match_SetEndImm:
6241 return "operand must be an immediate in the range [0,1]";
6242 case ARMAsmParser::Match_ImmThumbSR:
6243 return "operand must be an immediate in the range [1,32]";
6244 case ARMAsmParser::Match_VecListTwoMQ:
6245 return "operand must be a list of two consecutive q-registers in range [q0,q7]";
6246 case ARMAsmParser::Match_VecListFourMQ:
6247 return "operand must be a list of four consecutive q-registers in range [q0,q7]";
6248 case ARMAsmParser::Match_MVEVcvtImm32:
6249 return "MVE fixed-point immediate operand must be between 1 and 32";
6250 case ARMAsmParser::Match_MVEVcvtImm16:
6251 return "MVE fixed-point immediate operand must be between 1 and 16";
6252 case ARMAsmParser::Match_Imm3b:
6253 return "operand must be an immediate in the range [0,7]";
6254 case ARMAsmParser::Match_Imm4b:
6255 return "operand must be an immediate in the range [0,15]";
6256 case ARMAsmParser::Match_Imm6b:
6257 return "operand must be an immediate in the range [0,63]";
6258 case ARMAsmParser::Match_Imm7b:
6259 return "operand must be an immediate in the range [0,127]";
6260 case ARMAsmParser::Match_Imm9b:
6261 return "operand must be an immediate in the range [0,511]";
6262 case ARMAsmParser::Match_Imm11b:
6263 return "operand must be an immediate in the range [0,2047]";
6264 case ARMAsmParser::Match_Imm12b:
6265 return "operand must be an immediate in the range [0,4095]";
6266 case ARMAsmParser::Match_Imm13b:
6267 return "operand must be an immediate in the range [0,8191]";
6268 case ARMAsmParser::Match_ComplexRotationEven:
6269 return "complex rotation must be 0, 90, 180 or 270";
6270 case ARMAsmParser::Match_ComplexRotationOdd:
6271 return "complex rotation must be 90 or 270";
6272 case ARMAsmParser::Match_Imm0_4095:
6273 return "operand must be an immediate in the range [0,4095]";
6274 case ARMAsmParser::Match_LELabel:
6275 return "loop start is out of range or not a negative multiple of 2";
6276 case ARMAsmParser::Match_MVELongShift:
6277 return "operand must be an immediate in the range [1,32]";
6278 case ARMAsmParser::Match_CondCodeRestrictedFP:
6279 return "condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE";
6280 case ARMAsmParser::Match_CondCodeRestrictedI:
6281 return "condition code for sign-independent integer comparison must be EQ or NE";
6282 case ARMAsmParser::Match_CondCodeRestrictedS:
6283 return "condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE";
6284 case ARMAsmParser::Match_CondCodeRestrictedU:
6285 return "condition code for unsigned integer comparison must be EQ, NE, HS or HI";
6286 case ARMAsmParser::Match_ShrImm16:
6287 return "operand must be an immediate in the range [1,16]";
6288 case ARMAsmParser::Match_ShrImm32:
6289 return "operand must be an immediate in the range [1,32]";
6290 case ARMAsmParser::Match_ShrImm64:
6291 return "operand must be an immediate in the range [1,64]";
6292 case ARMAsmParser::Match_ShrImm8:
6293 return "operand must be an immediate in the range [1,8]";
6294 case ARMAsmParser::Match_WLSLabel:
6295 return "loop end is out of range or not a positive multiple of 2";
6296 default:
6297 return nullptr;
6298 }
6299}
6300
6301static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
6302 switch (RegisterClass) {
6303 case MCK_GPRsp:
6304 return ARMAsmParser::Match_GPRsp;
6305 case MCK_QPR_8:
6306 return ARMAsmParser::Match_QPR_8;
6307 case MCK_tGPROdd:
6308 return ARMAsmParser::Match_tGPROdd;
6309 case MCK_DPR_8:
6310 return ARMAsmParser::Match_DPR_8;
6311 case MCK_MQPR:
6312 return ARMAsmParser::Match_QPR_VFP2;
6313 case MCK_hGPR:
6314 return ARMAsmParser::Match_hGPR;
6315 case MCK_tGPR:
6316 return ARMAsmParser::Match_tGPR;
6317 case MCK_tGPREven:
6318 return ARMAsmParser::Match_tGPREven;
6319 case MCK_GPRnoip:
6320 return ARMAsmParser::Match_GPRnoip;
6321 case MCK_rGPR:
6322 return ARMAsmParser::Match_rGPR;
6323 case MCK_GPRnopc:
6324 return ARMAsmParser::Match_GPRnopc;
6325 case MCK_GPRnosp:
6326 return ARMAsmParser::Match_GPRnosp;
6327 case MCK_GPRwithAPSR_NZCVnosp:
6328 return ARMAsmParser::Match_GPRwithAPSR_NZCVnosp;
6329 case MCK_GPRwithZRnosp:
6330 return ARMAsmParser::Match_GPRwithZRnosp;
6331 case MCK_DPR_VFP2:
6332 return ARMAsmParser::Match_DPR_VFP2;
6333 case MCK_GPR:
6334 return ARMAsmParser::Match_GPR;
6335 case MCK_GPRwithAPSR:
6336 return ARMAsmParser::Match_GPRwithAPSR;
6337 case MCK_GPRwithZR:
6338 return ARMAsmParser::Match_GPRwithZR;
6339 case MCK_QPR:
6340 return ARMAsmParser::Match_QPR;
6341 case MCK_SPR_8:
6342 return ARMAsmParser::Match_SPR_8;
6343 case MCK_DPR:
6344 return ARMAsmParser::Match_DPR;
6345 case MCK_HPR:
6346 return ARMAsmParser::Match_SPR;
6347 default:
6348 return MCTargetAsmParser::Match_InvalidOperand;
6349 }
6350}
6351
6352static MatchClassKind matchTokenString(StringRef Name) {
6353 switch (Name.size()) {
6354 default: break;
6355 case 1: // 6 strings to match.
6356 switch (Name[0]) {
6357 default: break;
6358 case '!': // 1 string to match.
6359 return MCK__EXCLAIM_; // "!"
6360 case '[': // 1 string to match.
6361 return MCK__91_; // "["
6362 case ']': // 1 string to match.
6363 return MCK__93_; // "]"
6364 case '^': // 1 string to match.
6365 return MCK__94_; // "^"
6366 case '{': // 1 string to match.
6367 return MCK__123_; // "{"
6368 case '}': // 1 string to match.
6369 return MCK__125_; // "}"
6370 }
6371 break;
6372 case 2: // 6 strings to match.
6373 switch (Name[0]) {
6374 default: break;
6375 case '#': // 2 strings to match.
6376 switch (Name[1]) {
6377 default: break;
6378 case '0': // 1 string to match.
6379 return MCK__HASH_0; // "#0"
6380 case '8': // 1 string to match.
6381 return MCK__HASH_8; // "#8"
6382 }
6383 break;
6384 case '.': // 4 strings to match.
6385 switch (Name[1]) {
6386 default: break;
6387 case '8': // 1 string to match.
6388 return MCK__DOT_8; // ".8"
6389 case 'd': // 1 string to match.
6390 return MCK__DOT_d; // ".d"
6391 case 'f': // 1 string to match.
6392 return MCK__DOT_f; // ".f"
6393 case 'w': // 1 string to match.
6394 return MCK__DOT_w; // ".w"
6395 }
6396 break;
6397 }
6398 break;
6399 case 3: // 8 strings to match.
6400 switch (Name[0]) {
6401 default: break;
6402 case '#': // 1 string to match.
6403 if (memcmp(Name.data()+1, "16", 2) != 0)
6404 break;
6405 return MCK__HASH_16; // "#16"
6406 case '.': // 7 strings to match.
6407 switch (Name[1]) {
6408 default: break;
6409 case '1': // 1 string to match.
6410 if (Name[2] != '6')
6411 break;
6412 return MCK__DOT_16; // ".16"
6413 case '3': // 1 string to match.
6414 if (Name[2] != '2')
6415 break;
6416 return MCK__DOT_32; // ".32"
6417 case '6': // 1 string to match.
6418 if (Name[2] != '4')
6419 break;
6420 return MCK__DOT_64; // ".64"
6421 case 'i': // 1 string to match.
6422 if (Name[2] != '8')
6423 break;
6424 return MCK__DOT_i8; // ".i8"
6425 case 'p': // 1 string to match.
6426 if (Name[2] != '8')
6427 break;
6428 return MCK__DOT_p8; // ".p8"
6429 case 's': // 1 string to match.
6430 if (Name[2] != '8')
6431 break;
6432 return MCK__DOT_s8; // ".s8"
6433 case 'u': // 1 string to match.
6434 if (Name[2] != '8')
6435 break;
6436 return MCK__DOT_u8; // ".u8"
6437 }
6438 break;
6439 }
6440 break;
6441 case 4: // 14 strings to match.
6442 if (Name[0] != '.')
6443 break;
6444 switch (Name[1]) {
6445 default: break;
6446 case 'f': // 3 strings to match.
6447 switch (Name[2]) {
6448 default: break;
6449 case '1': // 1 string to match.
6450 if (Name[3] != '6')
6451 break;
6452 return MCK__DOT_f16; // ".f16"
6453 case '3': // 1 string to match.
6454 if (Name[3] != '2')
6455 break;
6456 return MCK__DOT_f32; // ".f32"
6457 case '6': // 1 string to match.
6458 if (Name[3] != '4')
6459 break;
6460 return MCK__DOT_f64; // ".f64"
6461 }
6462 break;
6463 case 'i': // 3 strings to match.
6464 switch (Name[2]) {
6465 default: break;
6466 case '1': // 1 string to match.
6467 if (Name[3] != '6')
6468 break;
6469 return MCK__DOT_i16; // ".i16"
6470 case '3': // 1 string to match.
6471 if (Name[3] != '2')
6472 break;
6473 return MCK__DOT_i32; // ".i32"
6474 case '6': // 1 string to match.
6475 if (Name[3] != '4')
6476 break;
6477 return MCK__DOT_i64; // ".i64"
6478 }
6479 break;
6480 case 'p': // 2 strings to match.
6481 switch (Name[2]) {
6482 default: break;
6483 case '1': // 1 string to match.
6484 if (Name[3] != '6')
6485 break;
6486 return MCK__DOT_p16; // ".p16"
6487 case '6': // 1 string to match.
6488 if (Name[3] != '4')
6489 break;
6490 return MCK__DOT_p64; // ".p64"
6491 }
6492 break;
6493 case 's': // 3 strings to match.
6494 switch (Name[2]) {
6495 default: break;
6496 case '1': // 1 string to match.
6497 if (Name[3] != '6')
6498 break;
6499 return MCK__DOT_s16; // ".s16"
6500 case '3': // 1 string to match.
6501 if (Name[3] != '2')
6502 break;
6503 return MCK__DOT_s32; // ".s32"
6504 case '6': // 1 string to match.
6505 if (Name[3] != '4')
6506 break;
6507 return MCK__DOT_s64; // ".s64"
6508 }
6509 break;
6510 case 'u': // 3 strings to match.
6511 switch (Name[2]) {
6512 default: break;
6513 case '1': // 1 string to match.
6514 if (Name[3] != '6')
6515 break;
6516 return MCK__DOT_u16; // ".u16"
6517 case '3': // 1 string to match.
6518 if (Name[3] != '2')
6519 break;
6520 return MCK__DOT_u32; // ".u32"
6521 case '6': // 1 string to match.
6522 if (Name[3] != '4')
6523 break;
6524 return MCK__DOT_u64; // ".u64"
6525 }
6526 break;
6527 }
6528 break;
6529 case 5: // 1 string to match.
6530 if (memcmp(Name.data()+0, ".bf16", 5) != 0)
6531 break;
6532 return MCK__DOT_bf16; // ".bf16"
6533 }
6534 return InvalidMatchClass;
6535}
6536
6537/// isSubclass - Compute whether \p A is a subclass of \p B.
6538static bool isSubclass(MatchClassKind A, MatchClassKind B) {
6539 if (A == B)
6540 return true;
6541
6542 [[maybe_unused]] static constexpr struct {
6543 uint32_t Offset;
6544 uint16_t Start;
6545 uint16_t Length;
6546 } Table[] = {
6547 {0, 0, 0},
6548 {0, 0, 0},
6549 {0, 13, 14},
6550 {14, 12, 14},
6551 {28, 14, 11},
6552 {39, 15, 11},
6553 {50, 16, 11},
6554 {61, 17, 11},
6555 {72, 14, 11},
6556 {83, 15, 11},
6557 {94, 16, 11},
6558 {105, 17, 11},
6559 {116, 25, 1},
6560 {117, 26, 1},
6561 {118, 24, 1},
6562 {119, 25, 1},
6563 {120, 26, 1},
6564 {121, 27, 1},
6565 {122, 24, 1},
6566 {123, 27, 1},
6567 {124, 0, 0},
6568 {124, 0, 0},
6569 {124, 0, 0},
6570 {124, 0, 0},
6571 {124, 0, 0},
6572 {124, 0, 0},
6573 {124, 0, 0},
6574 {124, 0, 0},
6575 {124, 0, 0},
6576 {124, 0, 0},
6577 {124, 0, 0},
6578 {124, 0, 0},
6579 {124, 0, 0},
6580 {124, 0, 0},
6581 {124, 0, 0},
6582 {124, 0, 0},
6583 {124, 0, 0},
6584 {124, 73, 44},
6585 {168, 64, 76},
6586 {244, 155, 1},
6587 {245, 154, 12},
6588 {257, 0, 0},
6589 {257, 0, 0},
6590 {257, 0, 0},
6591 {257, 69, 1},
6592 {258, 0, 0},
6593 {258, 0, 0},
6594 {258, 69, 1},
6595 {259, 0, 0},
6596 {259, 0, 0},
6597 {259, 85, 82},
6598 {341, 93, 74},
6599 {415, 0, 0},
6600 {415, 0, 0},
6601 {415, 0, 0},
6602 {415, 0, 0},
6603 {415, 92, 73},
6604 {488, 77, 90},
6605 {578, 0, 0},
6606 {578, 176, 1},
6607 {579, 0, 0},
6608 {579, 70, 101},
6609 {680, 73, 44},
6610 {724, 74, 43},
6611 {767, 75, 65},
6612 {832, 86, 81},
6613 {913, 85, 82},
6614 {995, 87, 80},
6615 {1075, 77, 90},
6616 {1165, 0, 0},
6617 {1165, 78, 93},
6618 {1258, 80, 93},
6619 {1351, 81, 92},
6620 {1443, 116, 1},
6621 {1444, 116, 1},
6622 {1445, 83, 57},
6623 {1502, 84, 87},
6624 {1589, 95, 72},
6625 {1661, 96, 75},
6626 {1736, 97, 73},
6627 {1809, 108, 65},
6628 {1874, 109, 64},
6629 {1938, 105, 12},
6630 {1950, 94, 46},
6631 {1996, 112, 59},
6632 {2055, 103, 64},
6633 {2119, 92, 75},
6634 {2194, 106, 61},
6635 {2255, 104, 63},
6636 {2318, 113, 61},
6637 {2379, 95, 72},
6638 {2451, 100, 71},
6639 {2522, 102, 63},
6640 {2585, 102, 65},
6641 {2650, 99, 41},
6642 {2691, 146, 21},
6643 {2712, 107, 64},
6644 {2776, 119, 51},
6645 {2827, 110, 63},
6646 {2890, 111, 29},
6647 {2919, 112, 59},
6648 {2978, 126, 46},
6649 {3024, 130, 35},
6650 {3059, 114, 53},
6651 {3112, 132, 35},
6652 {3147, 116, 1},
6653 {3148, 135, 32},
6654 {3180, 118, 53},
6655 {3233, 120, 53},
6656 {3286, 121, 52},
6657 {3338, 122, 51},
6658 {3389, 123, 17},
6659 {3406, 124, 47},
6660 {3453, 127, 47},
6661 {3500, 130, 35},
6662 {3535, 130, 37},
6663 {3572, 0, 0},
6664 {3572, 125, 46},
6665 {3618, 140, 31},
6666 {3649, 134, 36},
6667 {3685, 147, 26},
6668 {3711, 148, 25},
6669 {3736, 142, 31},
6670 {3767, 139, 1},
6671 {3768, 136, 35},
6672 {3803, 150, 21},
6673 {3824, 144, 28},
6674 {3852, 151, 23},
6675 {3875, 163, 14},
6676 {3889, 151, 23},
6677 {3912, 164, 1},
6678 {3913, 133, 34},
6679 {3947, 146, 21},
6680 {3968, 137, 28},
6681 {3996, 141, 29},
6682 {4025, 137, 30},
6683 {4055, 143, 28},
6684 {4083, 145, 20},
6685 {4103, 145, 22},
6686 {4125, 0, 0},
6687 {4125, 170, 1},
6688 {4126, 158, 12},
6689 {4138, 149, 24},
6690 {4162, 150, 21},
6691 {4183, 161, 11},
6692 {4194, 164, 1},
6693 {4195, 152, 15},
6694 {4210, 172, 1},
6695 {4211, 172, 1},
6696 {4212, 159, 14},
6697 {4226, 160, 11},
6698 {4237, 162, 12},
6699 {4249, 164, 3},
6700 {4252, 164, 1},
6701 {4253, 165, 1},
6702 {4254, 0, 0},
6703 {4254, 166, 1},
6704 {4255, 170, 1},
6705 {4256, 169, 1},
6706 {4257, 172, 1},
6707 {4258, 170, 1},
6708 {4259, 171, 1},
6709 {4260, 173, 1},
6710 {4261, 174, 3},
6711 {4264, 0, 0},
6712 {4264, 0, 0},
6713 {4264, 0, 0},
6714 {4264, 173, 1},
6715 {4265, 175, 2},
6716 {4267, 0, 0},
6717 {4267, 0, 0},
6718 {4267, 0, 0},
6719 {4267, 0, 0},
6720 {4267, 0, 0},
6721 {4267, 176, 1},
6722 {4268, 176, 1},
6723 {4269, 0, 0},
6724 {4269, 0, 0},
6725 {4269, 0, 0},
6726 {4269, 0, 0},
6727 {4269, 0, 0},
6728 {4269, 0, 0},
6729 {4269, 0, 0},
6730 {4269, 0, 0},
6731 {4269, 0, 0},
6732 {4269, 0, 0},
6733 {4269, 0, 0},
6734 {4269, 0, 0},
6735 {4269, 0, 0},
6736 {4269, 0, 0},
6737 {4269, 0, 0},
6738 {4269, 0, 0},
6739 {4269, 0, 0},
6740 {4269, 0, 0},
6741 {4269, 0, 0},
6742 {4269, 0, 0},
6743 {4269, 0, 0},
6744 {4269, 0, 0},
6745 {4269, 1, 1},
6746 {4270, 1, 1},
6747 {4271, 0, 0},
6748 {4271, 0, 0},
6749 {4271, 0, 0},
6750 {4271, 0, 0},
6751 {4271, 0, 0},
6752 {4271, 0, 0},
6753 {4271, 0, 0},
6754 {4271, 0, 0},
6755 {4271, 0, 0},
6756 {4271, 0, 0},
6757 {4271, 0, 0},
6758 {4271, 0, 0},
6759 {4271, 0, 0},
6760 {4271, 0, 0},
6761 {4271, 0, 0},
6762 {4271, 0, 0},
6763 {4271, 0, 0},
6764 {4271, 0, 0},
6765 {4271, 0, 0},
6766 {4271, 0, 0},
6767 {4271, 0, 0},
6768 {4271, 0, 0},
6769 {4271, 0, 0},
6770 {4271, 0, 0},
6771 {4271, 0, 0},
6772 {4271, 0, 0},
6773 {4271, 0, 0},
6774 {4271, 0, 0},
6775 {4271, 0, 0},
6776 {4271, 0, 0},
6777 {4271, 0, 0},
6778 {4271, 0, 0},
6779 {4271, 0, 0},
6780 {4271, 0, 0},
6781 {4271, 0, 0},
6782 {4271, 0, 0},
6783 {4271, 0, 0},
6784 {4271, 0, 0},
6785 {4271, 0, 0},
6786 {4271, 0, 0},
6787 {4271, 0, 0},
6788 {4271, 0, 0},
6789 {4271, 0, 0},
6790 {4271, 0, 0},
6791 {4271, 0, 0},
6792 {4271, 0, 0},
6793 {4271, 0, 0},
6794 {4271, 0, 0},
6795 {4271, 0, 0},
6796 {4271, 0, 0},
6797 {4271, 0, 0},
6798 {4271, 0, 0},
6799 {4271, 0, 0},
6800 {4271, 0, 0},
6801 {4271, 0, 0},
6802 {4271, 0, 0},
6803 {4271, 0, 0},
6804 {4271, 0, 0},
6805 {4271, 0, 0},
6806 {4271, 0, 0},
6807 {4271, 0, 0},
6808 {4271, 0, 0},
6809 {4271, 0, 0},
6810 {4271, 0, 0},
6811 {4271, 0, 0},
6812 {4271, 0, 0},
6813 {4271, 0, 0},
6814 {4271, 0, 0},
6815 {4271, 0, 0},
6816 {4271, 0, 0},
6817 {4271, 0, 0},
6818 {4271, 0, 0},
6819 {4271, 0, 0},
6820 {4271, 0, 0},
6821 {4271, 0, 0},
6822 {4271, 0, 0},
6823 {4271, 0, 0},
6824 {4271, 0, 0},
6825 {4271, 0, 0},
6826 {4271, 0, 0},
6827 {4271, 0, 0},
6828 {4271, 0, 0},
6829 {4271, 0, 0},
6830 {4271, 0, 0},
6831 {4271, 0, 0},
6832 {4271, 0, 0},
6833 {4271, 0, 0},
6834 {4271, 1, 1},
6835 {4272, 1, 1},
6836 {4273, 0, 0},
6837 {4273, 0, 0},
6838 {4273, 0, 0},
6839 {4273, 0, 0},
6840 {4273, 0, 0},
6841 {4273, 0, 0},
6842 {4273, 0, 0},
6843 {4273, 0, 0},
6844 {4273, 0, 0},
6845 {4273, 0, 0},
6846 {4273, 0, 0},
6847 {4273, 0, 0},
6848 {4273, 0, 0},
6849 {4273, 0, 0},
6850 {4273, 0, 0},
6851 {4273, 0, 0},
6852 {4273, 0, 0},
6853 {4273, 0, 0},
6854 {4273, 0, 0},
6855 {4273, 0, 0},
6856 {4273, 0, 0},
6857 {4273, 0, 0},
6858 {4273, 0, 0},
6859 {4273, 0, 0},
6860 {4273, 0, 0},
6861 {4273, 0, 0},
6862 {4273, 0, 0},
6863 {4273, 0, 0},
6864 {4273, 0, 0},
6865 {4273, 0, 0},
6866 {4273, 0, 0},
6867 {4273, 0, 0},
6868 {4273, 0, 0},
6869 {4273, 0, 0},
6870 {4273, 0, 0},
6871 {4273, 0, 0},
6872 {4273, 0, 0},
6873 {4273, 0, 0},
6874 {4273, 0, 0},
6875 {4273, 0, 0},
6876 {4273, 0, 0},
6877 {4273, 0, 0},
6878 {4273, 0, 0},
6879 {4273, 0, 0},
6880 {4273, 0, 0},
6881 {4273, 0, 0},
6882 {4273, 0, 0},
6883 {4273, 0, 0},
6884 {4273, 0, 0},
6885 {4273, 0, 0},
6886 {4273, 0, 0},
6887 {4273, 0, 0},
6888 {4273, 0, 0},
6889 {4273, 0, 0},
6890 {4273, 0, 0},
6891 {4273, 0, 0},
6892 {4273, 0, 0},
6893 {4273, 0, 0},
6894 {4273, 0, 0},
6895 {4273, 0, 0},
6896 {4273, 0, 0},
6897 {4273, 0, 0},
6898 {4273, 0, 0},
6899 {4273, 0, 0},
6900 {4273, 0, 0},
6901 {4273, 0, 0},
6902 {4273, 0, 0},
6903 {4273, 0, 0},
6904 {4273, 0, 0},
6905 {4273, 0, 0},
6906 {4273, 0, 0},
6907 {4273, 0, 0},
6908 {4273, 0, 0},
6909 {4273, 0, 0},
6910 {4273, 0, 0},
6911 {4273, 0, 0},
6912 {4273, 0, 0},
6913 {4273, 0, 0},
6914 {4273, 0, 0},
6915 {4273, 0, 0},
6916 {4273, 0, 0},
6917 {4273, 0, 0},
6918 {4273, 0, 0},
6919 {4273, 0, 0},
6920 {4273, 0, 0},
6921 {4273, 0, 0},
6922 {4273, 0, 0},
6923 {4273, 0, 0},
6924 {4273, 0, 0},
6925 {4273, 0, 0},
6926 {4273, 0, 0},
6927 {4273, 0, 0},
6928 {4273, 0, 0},
6929 {4273, 0, 0},
6930 {4273, 0, 0},
6931 {4273, 0, 0},
6932 {4273, 0, 0},
6933 {4273, 0, 0},
6934 {4273, 0, 0},
6935 {4273, 0, 0},
6936 {4273, 0, 0},
6937 {4273, 0, 0},
6938 {4273, 0, 0},
6939 {4273, 0, 0},
6940 {4273, 0, 0},
6941 {4273, 0, 0},
6942 {4273, 0, 0},
6943 {4273, 0, 0},
6944 {4273, 0, 0},
6945 {4273, 0, 0},
6946 {4273, 0, 0},
6947 {4273, 0, 0},
6948 {4273, 0, 0},
6949 {4273, 0, 0},
6950 {4273, 0, 0},
6951 {4273, 0, 0},
6952 };
6953
6954 static constexpr uint8_t Data[] = {
6955 0x01,
6956 0x60,
6957 0x00,
6958 0x18,
6959 0xC0,
6960 0x00,
6961 0x06,
6962 0x30,
6963 0x80,
6964 0x01,
6965 0x0C,
6966 0x60,
6967 0x00,
6968 0x03,
6969 0xF8,
6970 0x3F,
6971 0x00,
6972 0x00,
6973 0x00,
6974 0x00,
6975 0x80,
6976 0x01,
6977 0x08,
6978 0x08,
6979 0x40,
6980 0x08,
6981 0x80,
6982 0x00,
6983 0x08,
6984 0x00,
6985 0x38,
6986 0x00,
6987 0x0F,
6988 0x00,
6989 0x20,
6990 0x00,
6991 0x03,
6992 0x00,
6993 0x05,
6994 0x00,
6995 0xC1,
6996 0x07,
6997 0x3C,
6998 0x40,
6999 0x00,
7000 0x08,
7001 0x00,
7002 0x04,
7003 0x04,
7004 0x02,
7005 0x01,
7006 0xF0,
7007 0x00,
7008 0x02,
7009 0x20,
7010 0x00,
7011 0x20,
7012 0x11,
7013 0x10,
7014 0x10,
7015 0x80,
7016 0x01,
7017 0x01,
7018 0x04,
7019 0x04,
7020 0x60,
7021 0x00,
7022 0xA0,
7023 0x00,
7024 0x20,
7025 0xF8,
7026 0x80,
7027 0x0F,
7028 0x08,
7029 0x00,
7030 0x21,
7031 0x02,
7032 0x21,
7033 0x08,
7034 0x02,
7035 0x20,
7036 0x12,
7037 0x08,
7038 0x20,
7039 0x80,
7040 0x01,
7041 0x00,
7042 0x00,
7043 0x00,
7044 0x01,
7045 0x18,
7046 0x10,
7047 0x00,
7048 0x00,
7049 0x08,
7050 0xC0,
7051 0x80,
7052 0x00,
7053 0x84,
7054 0x00,
7055 0x08,
7056 0x80,
7057 0x00,
7058 0x80,
7059 0xC1,
7060 0x00,
7061 0x13,
7062 0x30,
7063 0x00,
7064 0x10,
7065 0x1A,
7066 0x18,
7067 0x7C,
7068 0xC0,
7069 0x07,
7070 0x03,
7071 0x1C,
7072 0xC0,
7073 0x00,
7074 0x40,
7075 0x69,
7076 0x60,
7077 0xF0,
7078 0x01,
7079 0x4F,
7080 0x08,
7081 0x40,
7082 0x00,
7083 0x00,
7084 0x80,
7085 0x6A,
7086 0x60,
7087 0xF0,
7088 0x01,
7089 0x0F,
7090 0x40,
7091 0x21,
7092 0x40,
7093 0x00,
7094 0x00,
7095 0x00,
7096 0xAE,
7097 0x81,
7098 0xC1,
7099 0x07,
7100 0x3C,
7101 0x00,
7102 0x80,
7103 0x08,
7104 0x84,
7105 0x20,
7106 0x08,
7107 0x80,
7108 0x48,
7109 0x20,
7110 0x80,
7111 0x00,
7112 0x06,
7113 0x00,
7114 0x10,
7115 0x40,
7116 0x01,
7117 0x14,
7118 0x00,
7119 0x00,
7120 0xA1,
7121 0x00,
7122 0x02,
7123 0xC0,
7124 0x00,
7125 0x00,
7126 0x01,
7127 0x18,
7128 0x80,
7129 0x01,
7130 0x00,
7131 0x10,
7132 0x0C,
7133 0x20,
7134 0x00,
7135 0x3C,
7136 0x00,
7137 0x21,
7138 0x00,
7139 0x02,
7140 0x20,
7141 0x00,
7142 0x60,
7143 0x20,
7144 0x40,
7145 0x00,
7146 0x84,
7147 0xC0,
7148 0x00,
7149 0x04,
7150 0x02,
7151 0x81,
7152 0x04,
7153 0x30,
7154 0x00,
7155 0x00,
7156 0x00,
7157 0x00,
7158 0x04,
7159 0x00,
7160 0xC1,
7161 0x07,
7162 0x3C,
7163 0x00,
7164 0x01,
7165 0x08,
7166 0x02,
7167 0x20,
7168 0x12,
7169 0x08,
7170 0x20,
7171 0x80,
7172 0x01,
7173 0x00,
7174 0x40,
7175 0x00,
7176 0x20,
7177 0x10,
7178 0x00,
7179 0x20,
7180 0x00,
7181 0x03,
7182 0xA0,
7183 0x00,
7184 0x00,
7185 0x08,
7186 0x05,
7187 0x10,
7188 0x00,
7189 0x0E,
7190 0xC0,
7191 0x00,
7192 0x00,
7193 0x08,
7194 0x06,
7195 0x10,
7196 0x00,
7197 0x06,
7198 0x60,
7199 0x08,
7200 0x80,
7201 0x00,
7202 0x08,
7203 0x00,
7204 0x18,
7205 0x02,
7206 0x03,
7207 0x10,
7208 0x08,
7209 0x04,
7210 0x12,
7211 0xC0,
7212 0x00,
7213 0x0C,
7214 0x00,
7215 0x14,
7216 0x00,
7217 0x04,
7218 0x1F,
7219 0xF0,
7220 0x01,
7221 0x06,
7222 0x60,
7223 0x00,
7224 0x20,
7225 0x34,
7226 0x30,
7227 0xF8,
7228 0x80,
7229 0x07,
7230 0x00,
7231 0x00,
7232 0xA8,
7233 0x06,
7234 0x06,
7235 0x1F,
7236 0xF0,
7237 0x00,
7238 0x00,
7239 0x00,
7240 0x5C,
7241 0x03,
7242 0x83,
7243 0x0F,
7244 0x78,
7245 0x00,
7246 0x50,
7247 0x00,
7248 0x00,
7249 0x10,
7250 0x80,
7251 0x10,
7252 0x0C,
7253 0x00,
7254 0x00,
7255 0x00,
7256 0x80,
7257 0x6A,
7258 0x60,
7259 0xF0,
7260 0x01,
7261 0x0F,
7262 0x80,
7263 0x00,
7264 0x08,
7265 0x80,
7266 0x40,
7267 0x20,
7268 0x80,
7269 0x00,
7270 0x06,
7271 0x40,
7272 0x00,
7273 0x40,
7274 0x20,
7275 0x20,
7276 0x20,
7277 0x00,
7278 0x03,
7279 0x40,
7280 0x00,
7281 0x20,
7282 0x20,
7283 0x10,
7284 0x08,
7285 0x80,
7286 0x07,
7287 0x40,
7288 0x00,
7289 0x04,
7290 0x00,
7291 0x0C,
7292 0x3E,
7293 0xE0,
7294 0x01,
7295 0x08,
7296 0x00,
7297 0x20,
7298 0x12,
7299 0x08,
7300 0x20,
7301 0x80,
7302 0x01,
7303 0x80,
7304 0x40,
7305 0x00,
7306 0x80,
7307 0x00,
7308 0x0C,
7309 0x80,
7310 0x00,
7311 0x00,
7312 0x08,
7313 0x04,
7314 0x10,
7315 0x00,
7316 0x06,
7317 0x40,
7318 0x00,
7319 0xC0,
7320 0x00,
7321 0x08,
7322 0x80,
7323 0x40,
7324 0x20,
7325 0x80,
7326 0x00,
7327 0x06,
7328 0x00,
7329 0x10,
7330 0x00,
7331 0x20,
7332 0x80,
7333 0x01,
7334 0x80,
7335 0x00,
7336 0x00,
7337 0x1C,
7338 0x00,
7339 0x08,
7340 0x00,
7341 0x08,
7342 0x3E,
7343 0xE0,
7344 0x69,
7345 0x60,
7346 0xF0,
7347 0x01,
7348 0xDF,
7349 0xC0,
7350 0xE0,
7351 0x03,
7352 0x1E,
7353 0x00,
7354 0x00,
7355 0x24,
7356 0x10,
7357 0x40,
7358 0x00,
7359 0x03,
7360 0x00,
7361 0x80,
7362 0x50,
7363 0x00,
7364 0x01,
7365 0x60,
7366 0x00,
7367 0x00,
7368 0x08,
7369 0x06,
7370 0x10,
7371 0x00,
7372 0x06,
7373 0x00,
7374 0x40,
7375 0x20,
7376 0x80,
7377 0x00,
7378 0x30,
7379 0x00,
7380 0x60,
7381 0x00,
7382 0x04,
7383 0x02,
7384 0x01,
7385 0x04,
7386 0x30,
7387 0x00,
7388 0x00,
7389 0x20,
7390 0x00,
7391 0x01,
7392 0x18,
7393 0x00,
7394 0x00,
7395 0x08,
7396 0xC0,
7397 0x00,
7398 0x00,
7399 0x20,
7400 0x00,
7401 0x1E,
7402 0x80,
7403 0x40,
7404 0x20,
7405 0x90,
7406 0x00,
7407 0x06,
7408 0x00,
7409 0x40,
7410 0x00,
7411 0x03,
7412 0x01,
7413 0x00,
7414 0x02,
7415 0x30,
7416 0x00,
7417 0x02,
7418 0xC0,
7419 0x01,
7420 0x04,
7421 0x80,
7422 0x81,
7423 0x00,
7424 0x02,
7425 0xC0,
7426 0x81,
7427 0x40,
7428 0x00,
7429 0x01,
7430 0x0C,
7431 0x24,
7432 0x80,
7433 0x01,
7434 0x00,
7435 0x02,
7436 0x18,
7437 0x80,
7438 0x00,
7439 0x0C,
7440 0x40,
7441 0x03,
7442 0x10,
7443 0x82,
7444 0x6B,
7445 0x60,
7446 0xF0,
7447 0x01,
7448 0x0F,
7449 0x3E,
7450 0xE0,
7451 0x01,
7452 0x01,
7453 0x01,
7454 0x18,
7455 0x00,
7456 0x20,
7457 0x00,
7458 0x07,
7459 0x06,
7460 0x1F,
7461 0xF0,
7462 0x40,
7463 0x00,
7464 0x01,
7465 0x0C,
7466 0x08,
7467 0xC0,
7468 0x40,
7469 0x00,
7470 0x7C,
7471 0x00,
7472 0x06,
7473 0x10,
7474 0x00,
7475 0x06,
7476 0x10,
7477 0xC0,
7478 0x00,
7479 0xFE,
7480 0x80,
7481 0x1F,
7482 0x00,
7483 0x06,
7484 0x30,
7485 0x00,
7486 0xFF,
7487 0xBF,
7488 0xFF,
7489 0x01,
7490 };
7491
7492 auto &Entry = Table[A];
7493 unsigned Idx = B - Entry.Start;
7494 if (Idx >= Entry.Length)
7495 return false;
7496 Idx += Entry.Offset;
7497 return (Data[Idx / 8] >> (Idx % 8)) & 1;
7498}
7499
7500static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
7501 ARMOperand &Operand = (ARMOperand &)GOp;
7502 if (Kind == InvalidMatchClass)
7503 return MCTargetAsmParser::Match_InvalidOperand;
7504
7505 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
7506 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
7507 MCTargetAsmParser::Match_Success :
7508 MCTargetAsmParser::Match_InvalidOperand;
7509
7510 switch (Kind) {
7511 default: break;
7512 case MCK_AM2OffsetImm: {
7513 DiagnosticPredicate DP(Operand.isAM2OffsetImm());
7514 if (DP.isMatch())
7515 return MCTargetAsmParser::Match_Success;
7516 break;
7517 }
7518 case MCK_AM3Offset: {
7519 DiagnosticPredicate DP(Operand.isAM3Offset());
7520 if (DP.isMatch())
7521 return MCTargetAsmParser::Match_Success;
7522 break;
7523 }
7524 case MCK_ARMBranchTarget: {
7525 DiagnosticPredicate DP(Operand.isARMBranchTarget());
7526 if (DP.isMatch())
7527 return MCTargetAsmParser::Match_Success;
7528 break;
7529 }
7530 case MCK_AddrMode3: {
7531 DiagnosticPredicate DP(Operand.isAddrMode3());
7532 if (DP.isMatch())
7533 return MCTargetAsmParser::Match_Success;
7534 break;
7535 }
7536 case MCK_AddrMode5: {
7537 DiagnosticPredicate DP(Operand.isAddrMode5());
7538 if (DP.isMatch())
7539 return MCTargetAsmParser::Match_Success;
7540 break;
7541 }
7542 case MCK_AddrMode5FP16: {
7543 DiagnosticPredicate DP(Operand.isAddrMode5FP16());
7544 if (DP.isMatch())
7545 return MCTargetAsmParser::Match_Success;
7546 break;
7547 }
7548 case MCK_AlignedMemory16: {
7549 DiagnosticPredicate DP(Operand.isAlignedMemory16());
7550 if (DP.isMatch())
7551 return MCTargetAsmParser::Match_Success;
7552 if (DP.isNearMatch())
7553 return ARMAsmParser::Match_AlignedMemory16;
7554 break;
7555 }
7556 case MCK_AlignedMemory32: {
7557 DiagnosticPredicate DP(Operand.isAlignedMemory32());
7558 if (DP.isMatch())
7559 return MCTargetAsmParser::Match_Success;
7560 if (DP.isNearMatch())
7561 return ARMAsmParser::Match_AlignedMemory32;
7562 break;
7563 }
7564 case MCK_AlignedMemory64: {
7565 DiagnosticPredicate DP(Operand.isAlignedMemory64());
7566 if (DP.isMatch())
7567 return MCTargetAsmParser::Match_Success;
7568 if (DP.isNearMatch())
7569 return ARMAsmParser::Match_AlignedMemory64;
7570 break;
7571 }
7572 case MCK_AlignedMemory64or128: {
7573 DiagnosticPredicate DP(Operand.isAlignedMemory64or128());
7574 if (DP.isMatch())
7575 return MCTargetAsmParser::Match_Success;
7576 if (DP.isNearMatch())
7577 return ARMAsmParser::Match_AlignedMemory64or128;
7578 break;
7579 }
7580 case MCK_AlignedMemory64or128or256: {
7581 DiagnosticPredicate DP(Operand.isAlignedMemory64or128or256());
7582 if (DP.isMatch())
7583 return MCTargetAsmParser::Match_Success;
7584 if (DP.isNearMatch())
7585 return ARMAsmParser::Match_AlignedMemory64or128or256;
7586 break;
7587 }
7588 case MCK_AlignedMemoryNone: {
7589 DiagnosticPredicate DP(Operand.isAlignedMemoryNone());
7590 if (DP.isMatch())
7591 return MCTargetAsmParser::Match_Success;
7592 if (DP.isNearMatch())
7593 return ARMAsmParser::Match_AlignedMemoryNone;
7594 break;
7595 }
7596 case MCK_AlignedMemory: {
7597 DiagnosticPredicate DP(Operand.isAlignedMemory());
7598 if (DP.isMatch())
7599 return MCTargetAsmParser::Match_Success;
7600 break;
7601 }
7602 case MCK_DupAlignedMemory16: {
7603 DiagnosticPredicate DP(Operand.isDupAlignedMemory16());
7604 if (DP.isMatch())
7605 return MCTargetAsmParser::Match_Success;
7606 if (DP.isNearMatch())
7607 return ARMAsmParser::Match_DupAlignedMemory16;
7608 break;
7609 }
7610 case MCK_DupAlignedMemory32: {
7611 DiagnosticPredicate DP(Operand.isDupAlignedMemory32());
7612 if (DP.isMatch())
7613 return MCTargetAsmParser::Match_Success;
7614 if (DP.isNearMatch())
7615 return ARMAsmParser::Match_DupAlignedMemory32;
7616 break;
7617 }
7618 case MCK_DupAlignedMemory64: {
7619 DiagnosticPredicate DP(Operand.isDupAlignedMemory64());
7620 if (DP.isMatch())
7621 return MCTargetAsmParser::Match_Success;
7622 if (DP.isNearMatch())
7623 return ARMAsmParser::Match_DupAlignedMemory64;
7624 break;
7625 }
7626 case MCK_DupAlignedMemory64or128: {
7627 DiagnosticPredicate DP(Operand.isDupAlignedMemory64or128());
7628 if (DP.isMatch())
7629 return MCTargetAsmParser::Match_Success;
7630 if (DP.isNearMatch())
7631 return ARMAsmParser::Match_DupAlignedMemory64or128;
7632 break;
7633 }
7634 case MCK_DupAlignedMemoryNone: {
7635 DiagnosticPredicate DP(Operand.isDupAlignedMemoryNone());
7636 if (DP.isMatch())
7637 return MCTargetAsmParser::Match_Success;
7638 if (DP.isNearMatch())
7639 return ARMAsmParser::Match_DupAlignedMemoryNone;
7640 break;
7641 }
7642 case MCK_AdrLabel: {
7643 DiagnosticPredicate DP(Operand.isAdrLabel());
7644 if (DP.isMatch())
7645 return MCTargetAsmParser::Match_Success;
7646 break;
7647 }
7648 case MCK_BankedReg: {
7649 DiagnosticPredicate DP(Operand.isBankedReg());
7650 if (DP.isMatch())
7651 return MCTargetAsmParser::Match_Success;
7652 break;
7653 }
7654 case MCK_Bitfield: {
7655 DiagnosticPredicate DP(Operand.isBitfield());
7656 if (DP.isMatch())
7657 return MCTargetAsmParser::Match_Success;
7658 break;
7659 }
7660 case MCK_CCOut: {
7661 DiagnosticPredicate DP(Operand.isCCOut());
7662 if (DP.isMatch())
7663 return MCTargetAsmParser::Match_Success;
7664 break;
7665 }
7666 case MCK_CondCode: {
7667 DiagnosticPredicate DP(Operand.isCondCode());
7668 if (DP.isMatch())
7669 return MCTargetAsmParser::Match_Success;
7670 break;
7671 }
7672 case MCK_CoprocNum: {
7673 DiagnosticPredicate DP(Operand.isCoprocNum());
7674 if (DP.isMatch())
7675 return MCTargetAsmParser::Match_Success;
7676 break;
7677 }
7678 case MCK_CoprocOption: {
7679 DiagnosticPredicate DP(Operand.isCoprocOption());
7680 if (DP.isMatch())
7681 return MCTargetAsmParser::Match_Success;
7682 break;
7683 }
7684 case MCK_CoprocReg: {
7685 DiagnosticPredicate DP(Operand.isCoprocReg());
7686 if (DP.isMatch())
7687 return MCTargetAsmParser::Match_Success;
7688 break;
7689 }
7690 case MCK_DPRRegList: {
7691 DiagnosticPredicate DP(Operand.isDPRRegList());
7692 if (DP.isMatch())
7693 return MCTargetAsmParser::Match_Success;
7694 if (DP.isNearMatch())
7695 return ARMAsmParser::Match_DPR_RegList;
7696 break;
7697 }
7698 case MCK_FPDRegListWithVPR: {
7699 DiagnosticPredicate DP(Operand.isFPDRegListWithVPR());
7700 if (DP.isMatch())
7701 return MCTargetAsmParser::Match_Success;
7702 break;
7703 }
7704 case MCK_FPImm: {
7705 DiagnosticPredicate DP(Operand.isFPImm());
7706 if (DP.isMatch())
7707 return MCTargetAsmParser::Match_Success;
7708 break;
7709 }
7710 case MCK_FPSRegListWithVPR: {
7711 DiagnosticPredicate DP(Operand.isFPSRegListWithVPR());
7712 if (DP.isMatch())
7713 return MCTargetAsmParser::Match_Success;
7714 break;
7715 }
7716 case MCK_Imm0_15: {
7717 DiagnosticPredicate DP(Operand.isImmediate<0,15>());
7718 if (DP.isMatch())
7719 return MCTargetAsmParser::Match_Success;
7720 if (DP.isNearMatch())
7721 return ARMAsmParser::Match_Imm0_15;
7722 break;
7723 }
7724 case MCK_Imm0_1: {
7725 DiagnosticPredicate DP(Operand.isImmediate<0,1>());
7726 if (DP.isMatch())
7727 return MCTargetAsmParser::Match_Success;
7728 if (DP.isNearMatch())
7729 return ARMAsmParser::Match_Imm0_1;
7730 break;
7731 }
7732 case MCK_Imm0_239: {
7733 DiagnosticPredicate DP(Operand.isImmediate<0,239>());
7734 if (DP.isMatch())
7735 return MCTargetAsmParser::Match_Success;
7736 if (DP.isNearMatch())
7737 return ARMAsmParser::Match_Imm0_239;
7738 break;
7739 }
7740 case MCK_Imm0_255: {
7741 DiagnosticPredicate DP(Operand.isImmediate<0,255>());
7742 if (DP.isMatch())
7743 return MCTargetAsmParser::Match_Success;
7744 if (DP.isNearMatch())
7745 return ARMAsmParser::Match_Imm0_255;
7746 break;
7747 }
7748 case MCK_Imm0_255Expr: {
7749 DiagnosticPredicate DP(Operand.isImm0_255Expr());
7750 if (DP.isMatch())
7751 return MCTargetAsmParser::Match_Success;
7752 if (DP.isNearMatch())
7753 return ARMAsmParser::Match_Imm0_255Expr;
7754 break;
7755 }
7756 case MCK_Imm0_31: {
7757 DiagnosticPredicate DP(Operand.isImmediate<0,31>());
7758 if (DP.isMatch())
7759 return MCTargetAsmParser::Match_Success;
7760 if (DP.isNearMatch())
7761 return ARMAsmParser::Match_Imm0_31;
7762 break;
7763 }
7764 case MCK_Imm0_32: {
7765 DiagnosticPredicate DP(Operand.isImmediate<0,32>());
7766 if (DP.isMatch())
7767 return MCTargetAsmParser::Match_Success;
7768 if (DP.isNearMatch())
7769 return ARMAsmParser::Match_Imm0_32;
7770 break;
7771 }
7772 case MCK_Imm0_3: {
7773 DiagnosticPredicate DP(Operand.isImmediate<0,3>());
7774 if (DP.isMatch())
7775 return MCTargetAsmParser::Match_Success;
7776 if (DP.isNearMatch())
7777 return ARMAsmParser::Match_Imm0_3;
7778 break;
7779 }
7780 case MCK_Imm0_63: {
7781 DiagnosticPredicate DP(Operand.isImmediate<0,63>());
7782 if (DP.isMatch())
7783 return MCTargetAsmParser::Match_Success;
7784 if (DP.isNearMatch())
7785 return ARMAsmParser::Match_Imm0_63;
7786 break;
7787 }
7788 case MCK_Imm0_65535: {
7789 DiagnosticPredicate DP(Operand.isImmediate<0,65535>());
7790 if (DP.isMatch())
7791 return MCTargetAsmParser::Match_Success;
7792 if (DP.isNearMatch())
7793 return ARMAsmParser::Match_Imm0_65535;
7794 break;
7795 }
7796 case MCK_Imm0_65535Expr: {
7797 DiagnosticPredicate DP(Operand.isImm0_65535Expr());
7798 if (DP.isMatch())
7799 return MCTargetAsmParser::Match_Success;
7800 if (DP.isNearMatch())
7801 return ARMAsmParser::Match_Imm0_65535Expr;
7802 break;
7803 }
7804 case MCK_Imm0_7: {
7805 DiagnosticPredicate DP(Operand.isImmediate<0,7>());
7806 if (DP.isMatch())
7807 return MCTargetAsmParser::Match_Success;
7808 if (DP.isNearMatch())
7809 return ARMAsmParser::Match_Imm0_7;
7810 break;
7811 }
7812 case MCK_Imm16: {
7813 DiagnosticPredicate DP(Operand.isImmediate<16,16>());
7814 if (DP.isMatch())
7815 return MCTargetAsmParser::Match_Success;
7816 if (DP.isNearMatch())
7817 return ARMAsmParser::Match_Imm16;
7818 break;
7819 }
7820 case MCK_Imm1_15: {
7821 DiagnosticPredicate DP(Operand.isImmediate<1,15>());
7822 if (DP.isMatch())
7823 return MCTargetAsmParser::Match_Success;
7824 if (DP.isNearMatch())
7825 return ARMAsmParser::Match_Imm1_15;
7826 break;
7827 }
7828 case MCK_Imm1_16: {
7829 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
7830 if (DP.isMatch())
7831 return MCTargetAsmParser::Match_Success;
7832 if (DP.isNearMatch())
7833 return ARMAsmParser::Match_ImmRange1_16;
7834 break;
7835 }
7836 case MCK_Imm1_31: {
7837 DiagnosticPredicate DP(Operand.isImmediate<1,31>());
7838 if (DP.isMatch())
7839 return MCTargetAsmParser::Match_Success;
7840 if (DP.isNearMatch())
7841 return ARMAsmParser::Match_Imm1_31;
7842 break;
7843 }
7844 case MCK_Imm1_32: {
7845 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
7846 if (DP.isMatch())
7847 return MCTargetAsmParser::Match_Success;
7848 if (DP.isNearMatch())
7849 return ARMAsmParser::Match_ImmRange1_32;
7850 break;
7851 }
7852 case MCK_Imm1_7: {
7853 DiagnosticPredicate DP(Operand.isImmediate<1,7>());
7854 if (DP.isMatch())
7855 return MCTargetAsmParser::Match_Success;
7856 if (DP.isNearMatch())
7857 return ARMAsmParser::Match_Imm1_7;
7858 break;
7859 }
7860 case MCK_Imm24bit: {
7861 DiagnosticPredicate DP(Operand.isImmediate<0,16777215>());
7862 if (DP.isMatch())
7863 return MCTargetAsmParser::Match_Success;
7864 if (DP.isNearMatch())
7865 return ARMAsmParser::Match_Imm24bit;
7866 break;
7867 }
7868 case MCK_Imm256_65535Expr: {
7869 DiagnosticPredicate DP(Operand.isImmediate<256,65535>());
7870 if (DP.isMatch())
7871 return MCTargetAsmParser::Match_Success;
7872 if (DP.isNearMatch())
7873 return ARMAsmParser::Match_Imm256_65535Expr;
7874 break;
7875 }
7876 case MCK_Imm32: {
7877 DiagnosticPredicate DP(Operand.isImmediate<32,32>());
7878 if (DP.isMatch())
7879 return MCTargetAsmParser::Match_Success;
7880 if (DP.isNearMatch())
7881 return ARMAsmParser::Match_Imm32;
7882 break;
7883 }
7884 case MCK_Imm8: {
7885 DiagnosticPredicate DP(Operand.isImmediate<8,8>());
7886 if (DP.isMatch())
7887 return MCTargetAsmParser::Match_Success;
7888 if (DP.isNearMatch())
7889 return ARMAsmParser::Match_Imm8;
7890 break;
7891 }
7892 case MCK_Imm8_255: {
7893 DiagnosticPredicate DP(Operand.isImmediate<8,255>());
7894 if (DP.isMatch())
7895 return MCTargetAsmParser::Match_Success;
7896 if (DP.isNearMatch())
7897 return ARMAsmParser::Match_Imm8_255;
7898 break;
7899 }
7900 case MCK_Imm: {
7901 DiagnosticPredicate DP(Operand.isImm());
7902 if (DP.isMatch())
7903 return MCTargetAsmParser::Match_Success;
7904 break;
7905 }
7906 case MCK_InstSyncBarrierOpt: {
7907 DiagnosticPredicate DP(Operand.isInstSyncBarrierOpt());
7908 if (DP.isMatch())
7909 return MCTargetAsmParser::Match_Success;
7910 break;
7911 }
7912 case MCK_MSRMask: {
7913 DiagnosticPredicate DP(Operand.isMSRMask());
7914 if (DP.isMatch())
7915 return MCTargetAsmParser::Match_Success;
7916 break;
7917 }
7918 case MCK_MVEShiftImm1_15: {
7919 DiagnosticPredicate DP(Operand.isImmediate<1,15>());
7920 if (DP.isMatch())
7921 return MCTargetAsmParser::Match_Success;
7922 if (DP.isNearMatch())
7923 return ARMAsmParser::Match_MVEShiftImm1_15;
7924 break;
7925 }
7926 case MCK_MVEShiftImm1_7: {
7927 DiagnosticPredicate DP(Operand.isImmediate<1,7>());
7928 if (DP.isMatch())
7929 return MCTargetAsmParser::Match_Success;
7930 if (DP.isNearMatch())
7931 return ARMAsmParser::Match_MVEShiftImm1_7;
7932 break;
7933 }
7934 case MCK_VIDUP_imm: {
7935 DiagnosticPredicate DP(Operand.isPowerTwoInRange<1,8>());
7936 if (DP.isMatch())
7937 return MCTargetAsmParser::Match_Success;
7938 if (DP.isNearMatch())
7939 return ARMAsmParser::Match_VIDUP_imm;
7940 break;
7941 }
7942 case MCK_MemBarrierOpt: {
7943 DiagnosticPredicate DP(Operand.isMemBarrierOpt());
7944 if (DP.isMatch())
7945 return MCTargetAsmParser::Match_Success;
7946 break;
7947 }
7948 case MCK_MemImm0_1020s4Offset: {
7949 DiagnosticPredicate DP(Operand.isMemImm0_1020s4Offset());
7950 if (DP.isMatch())
7951 return MCTargetAsmParser::Match_Success;
7952 break;
7953 }
7954 case MCK_MemImm12Offset: {
7955 DiagnosticPredicate DP(Operand.isMemImm12Offset());
7956 if (DP.isMatch())
7957 return MCTargetAsmParser::Match_Success;
7958 break;
7959 }
7960 case MCK_MemImm7Shift0Offset: {
7961 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::GPRnopcRegClassID>());
7962 if (DP.isMatch())
7963 return MCTargetAsmParser::Match_Success;
7964 break;
7965 }
7966 case MCK_MemImm7Shift0OffsetWB: {
7967 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::rGPRRegClassID>());
7968 if (DP.isMatch())
7969 return MCTargetAsmParser::Match_Success;
7970 break;
7971 }
7972 case MCK_MemImm7Shift1Offset: {
7973 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::GPRnopcRegClassID>());
7974 if (DP.isMatch())
7975 return MCTargetAsmParser::Match_Success;
7976 break;
7977 }
7978 case MCK_MemImm7Shift1OffsetWB: {
7979 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::rGPRRegClassID>());
7980 if (DP.isMatch())
7981 return MCTargetAsmParser::Match_Success;
7982 break;
7983 }
7984 case MCK_MemImm7Shift2Offset: {
7985 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::GPRnopcRegClassID>());
7986 if (DP.isMatch())
7987 return MCTargetAsmParser::Match_Success;
7988 break;
7989 }
7990 case MCK_MemImm7Shift2OffsetWB: {
7991 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::rGPRRegClassID>());
7992 if (DP.isMatch())
7993 return MCTargetAsmParser::Match_Success;
7994 break;
7995 }
7996 case MCK_MemImm7s4Offset: {
7997 DiagnosticPredicate DP(Operand.isMemImm7s4Offset());
7998 if (DP.isMatch())
7999 return MCTargetAsmParser::Match_Success;
8000 break;
8001 }
8002 case MCK_MemImm8Offset: {
8003 DiagnosticPredicate DP(Operand.isMemImm8Offset());
8004 if (DP.isMatch())
8005 return MCTargetAsmParser::Match_Success;
8006 break;
8007 }
8008 case MCK_MemImm8s4Offset: {
8009 DiagnosticPredicate DP(Operand.isMemImm8s4Offset());
8010 if (DP.isMatch())
8011 return MCTargetAsmParser::Match_Success;
8012 break;
8013 }
8014 case MCK_MemNegImm8Offset: {
8015 DiagnosticPredicate DP(Operand.isMemNegImm8Offset());
8016 if (DP.isMatch())
8017 return MCTargetAsmParser::Match_Success;
8018 break;
8019 }
8020 case MCK_MemNoOffset: {
8021 DiagnosticPredicate DP(Operand.isMemNoOffset());
8022 if (DP.isMatch())
8023 return MCTargetAsmParser::Match_Success;
8024 break;
8025 }
8026 case MCK_MemNoOffsetT2: {
8027 DiagnosticPredicate DP(Operand.isMemNoOffsetT2());
8028 if (DP.isMatch())
8029 return MCTargetAsmParser::Match_Success;
8030 break;
8031 }
8032 case MCK_MemNoOffsetT2NoSp: {
8033 DiagnosticPredicate DP(Operand.isMemNoOffsetT2NoSp());
8034 if (DP.isMatch())
8035 return MCTargetAsmParser::Match_Success;
8036 break;
8037 }
8038 case MCK_MemNoOffsetT: {
8039 DiagnosticPredicate DP(Operand.isMemNoOffsetT());
8040 if (DP.isMatch())
8041 return MCTargetAsmParser::Match_Success;
8042 break;
8043 }
8044 case MCK_MemPosImm8Offset: {
8045 DiagnosticPredicate DP(Operand.isMemPosImm8Offset());
8046 if (DP.isMatch())
8047 return MCTargetAsmParser::Match_Success;
8048 break;
8049 }
8050 case MCK_MemRegOffset: {
8051 DiagnosticPredicate DP(Operand.isMemRegOffset());
8052 if (DP.isMatch())
8053 return MCTargetAsmParser::Match_Success;
8054 break;
8055 }
8056 case MCK_MemRegQS2Offset: {
8057 DiagnosticPredicate DP(Operand.isMemRegQOffset<2>());
8058 if (DP.isMatch())
8059 return MCTargetAsmParser::Match_Success;
8060 break;
8061 }
8062 case MCK_MemRegQS3Offset: {
8063 DiagnosticPredicate DP(Operand.isMemRegQOffset<3>());
8064 if (DP.isMatch())
8065 return MCTargetAsmParser::Match_Success;
8066 break;
8067 }
8068 case MCK_MemRegRQS0Offset: {
8069 DiagnosticPredicate DP(Operand.isMemRegRQOffset<0>());
8070 if (DP.isMatch())
8071 return MCTargetAsmParser::Match_Success;
8072 break;
8073 }
8074 case MCK_MemRegRQS1Offset: {
8075 DiagnosticPredicate DP(Operand.isMemRegRQOffset<1>());
8076 if (DP.isMatch())
8077 return MCTargetAsmParser::Match_Success;
8078 break;
8079 }
8080 case MCK_MemRegRQS2Offset: {
8081 DiagnosticPredicate DP(Operand.isMemRegRQOffset<2>());
8082 if (DP.isMatch())
8083 return MCTargetAsmParser::Match_Success;
8084 break;
8085 }
8086 case MCK_MemRegRQS3Offset: {
8087 DiagnosticPredicate DP(Operand.isMemRegRQOffset<3>());
8088 if (DP.isMatch())
8089 return MCTargetAsmParser::Match_Success;
8090 break;
8091 }
8092 case MCK_ModImm: {
8093 DiagnosticPredicate DP(Operand.isModImm());
8094 if (DP.isMatch())
8095 return MCTargetAsmParser::Match_Success;
8096 break;
8097 }
8098 case MCK_ModImmNeg: {
8099 DiagnosticPredicate DP(Operand.isModImmNeg());
8100 if (DP.isMatch())
8101 return MCTargetAsmParser::Match_Success;
8102 break;
8103 }
8104 case MCK_ModImmNot: {
8105 DiagnosticPredicate DP(Operand.isModImmNot());
8106 if (DP.isMatch())
8107 return MCTargetAsmParser::Match_Success;
8108 break;
8109 }
8110 case MCK_MveSaturate: {
8111 DiagnosticPredicate DP(Operand.isMveSaturateOp());
8112 if (DP.isMatch())
8113 return MCTargetAsmParser::Match_Success;
8114 if (DP.isNearMatch())
8115 return ARMAsmParser::Match_MveSaturate;
8116 break;
8117 }
8118 case MCK_PKHASRImm: {
8119 DiagnosticPredicate DP(Operand.isPKHASRImm());
8120 if (DP.isMatch())
8121 return MCTargetAsmParser::Match_Success;
8122 break;
8123 }
8124 case MCK_PKHLSLImm: {
8125 DiagnosticPredicate DP(Operand.isImmediate<0,31>());
8126 if (DP.isMatch())
8127 return MCTargetAsmParser::Match_Success;
8128 if (DP.isNearMatch())
8129 return ARMAsmParser::Match_PKHLSLImm;
8130 break;
8131 }
8132 case MCK_PostIdxImm8: {
8133 DiagnosticPredicate DP(Operand.isPostIdxImm8());
8134 if (DP.isMatch())
8135 return MCTargetAsmParser::Match_Success;
8136 break;
8137 }
8138 case MCK_PostIdxImm8s4: {
8139 DiagnosticPredicate DP(Operand.isPostIdxImm8s4());
8140 if (DP.isMatch())
8141 return MCTargetAsmParser::Match_Success;
8142 break;
8143 }
8144 case MCK_PostIdxReg: {
8145 DiagnosticPredicate DP(Operand.isPostIdxReg());
8146 if (DP.isMatch())
8147 return MCTargetAsmParser::Match_Success;
8148 break;
8149 }
8150 case MCK_PostIdxRegShifted: {
8151 DiagnosticPredicate DP(Operand.isPostIdxRegShifted());
8152 if (DP.isMatch())
8153 return MCTargetAsmParser::Match_Success;
8154 break;
8155 }
8156 case MCK_ProcIFlags: {
8157 DiagnosticPredicate DP(Operand.isProcIFlags());
8158 if (DP.isMatch())
8159 return MCTargetAsmParser::Match_Success;
8160 break;
8161 }
8162 case MCK_RegList: {
8163 DiagnosticPredicate DP(Operand.isRegList());
8164 if (DP.isMatch())
8165 return MCTargetAsmParser::Match_Success;
8166 break;
8167 }
8168 case MCK_RegListWithAPSR: {
8169 DiagnosticPredicate DP(Operand.isRegListWithAPSR());
8170 if (DP.isMatch())
8171 return MCTargetAsmParser::Match_Success;
8172 break;
8173 }
8174 case MCK_RotImm: {
8175 DiagnosticPredicate DP(Operand.isRotImm());
8176 if (DP.isMatch())
8177 return MCTargetAsmParser::Match_Success;
8178 break;
8179 }
8180 case MCK_SPRRegList: {
8181 DiagnosticPredicate DP(Operand.isSPRRegList());
8182 if (DP.isMatch())
8183 return MCTargetAsmParser::Match_Success;
8184 if (DP.isNearMatch())
8185 return ARMAsmParser::Match_SPRRegList;
8186 break;
8187 }
8188 case MCK_SetEndImm: {
8189 DiagnosticPredicate DP(Operand.isImmediate<0,1>());
8190 if (DP.isMatch())
8191 return MCTargetAsmParser::Match_Success;
8192 if (DP.isNearMatch())
8193 return ARMAsmParser::Match_SetEndImm;
8194 break;
8195 }
8196 case MCK_RegShiftedImm: {
8197 DiagnosticPredicate DP(Operand.isRegShiftedImm());
8198 if (DP.isMatch())
8199 return MCTargetAsmParser::Match_Success;
8200 break;
8201 }
8202 case MCK_RegShiftedReg: {
8203 DiagnosticPredicate DP(Operand.isRegShiftedReg());
8204 if (DP.isMatch())
8205 return MCTargetAsmParser::Match_Success;
8206 break;
8207 }
8208 case MCK_ShifterImm: {
8209 DiagnosticPredicate DP(Operand.isShifterImm());
8210 if (DP.isMatch())
8211 return MCTargetAsmParser::Match_Success;
8212 break;
8213 }
8214 case MCK_ThumbBranchTarget: {
8215 DiagnosticPredicate DP(Operand.isThumbBranchTarget());
8216 if (DP.isMatch())
8217 return MCTargetAsmParser::Match_Success;
8218 break;
8219 }
8220 case MCK_ThumbMemPC: {
8221 DiagnosticPredicate DP(Operand.isThumbMemPC());
8222 if (DP.isMatch())
8223 return MCTargetAsmParser::Match_Success;
8224 break;
8225 }
8226 case MCK_ThumbModImmNeg1_7: {
8227 DiagnosticPredicate DP(Operand.isThumbModImmNeg1_7());
8228 if (DP.isMatch())
8229 return MCTargetAsmParser::Match_Success;
8230 break;
8231 }
8232 case MCK_ThumbModImmNeg8_255: {
8233 DiagnosticPredicate DP(Operand.isThumbModImmNeg8_255());
8234 if (DP.isMatch())
8235 return MCTargetAsmParser::Match_Success;
8236 break;
8237 }
8238 case MCK_ImmThumbSR: {
8239 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
8240 if (DP.isMatch())
8241 return MCTargetAsmParser::Match_Success;
8242 if (DP.isNearMatch())
8243 return ARMAsmParser::Match_ImmThumbSR;
8244 break;
8245 }
8246 case MCK_TraceSyncBarrierOpt: {
8247 DiagnosticPredicate DP(Operand.isTraceSyncBarrierOpt());
8248 if (DP.isMatch())
8249 return MCTargetAsmParser::Match_Success;
8250 break;
8251 }
8252 case MCK_UnsignedOffset_b8s2: {
8253 DiagnosticPredicate DP(Operand.isUnsignedOffset<8, 2>());
8254 if (DP.isMatch())
8255 return MCTargetAsmParser::Match_Success;
8256 break;
8257 }
8258 case MCK_VPTPredN: {
8259 DiagnosticPredicate DP(Operand.isVPTPred());
8260 if (DP.isMatch())
8261 return MCTargetAsmParser::Match_Success;
8262 break;
8263 }
8264 case MCK_VPTPredR: {
8265 DiagnosticPredicate DP(Operand.isVPTPred());
8266 if (DP.isMatch())
8267 return MCTargetAsmParser::Match_Success;
8268 break;
8269 }
8270 case MCK_VecListTwoMQ: {
8271 DiagnosticPredicate DP(Operand.isVecListTwoMQ());
8272 if (DP.isMatch())
8273 return MCTargetAsmParser::Match_Success;
8274 if (DP.isNearMatch())
8275 return ARMAsmParser::Match_VecListTwoMQ;
8276 break;
8277 }
8278 case MCK_VecListFourMQ: {
8279 DiagnosticPredicate DP(Operand.isVecListFourMQ());
8280 if (DP.isMatch())
8281 return MCTargetAsmParser::Match_Success;
8282 if (DP.isNearMatch())
8283 return ARMAsmParser::Match_VecListFourMQ;
8284 break;
8285 }
8286 case MCK_VecListDPairAllLanes: {
8287 DiagnosticPredicate DP(Operand.isVecListDPairAllLanes());
8288 if (DP.isMatch())
8289 return MCTargetAsmParser::Match_Success;
8290 break;
8291 }
8292 case MCK_VecListDPair: {
8293 DiagnosticPredicate DP(Operand.isVecListDPair());
8294 if (DP.isMatch())
8295 return MCTargetAsmParser::Match_Success;
8296 break;
8297 }
8298 case MCK_VecListDPairSpacedAllLanes: {
8299 DiagnosticPredicate DP(Operand.isVecListDPairSpacedAllLanes());
8300 if (DP.isMatch())
8301 return MCTargetAsmParser::Match_Success;
8302 break;
8303 }
8304 case MCK_VecListDPairSpaced: {
8305 DiagnosticPredicate DP(Operand.isVecListDPairSpaced());
8306 if (DP.isMatch())
8307 return MCTargetAsmParser::Match_Success;
8308 break;
8309 }
8310 case MCK_VecListFourDAllLanes: {
8311 DiagnosticPredicate DP(Operand.isVecListFourDAllLanes());
8312 if (DP.isMatch())
8313 return MCTargetAsmParser::Match_Success;
8314 break;
8315 }
8316 case MCK_VecListFourD: {
8317 DiagnosticPredicate DP(Operand.isVecListFourD());
8318 if (DP.isMatch())
8319 return MCTargetAsmParser::Match_Success;
8320 break;
8321 }
8322 case MCK_VecListFourDByteIndexed: {
8323 DiagnosticPredicate DP(Operand.isVecListFourDByteIndexed());
8324 if (DP.isMatch())
8325 return MCTargetAsmParser::Match_Success;
8326 break;
8327 }
8328 case MCK_VecListFourDHWordIndexed: {
8329 DiagnosticPredicate DP(Operand.isVecListFourDHWordIndexed());
8330 if (DP.isMatch())
8331 return MCTargetAsmParser::Match_Success;
8332 break;
8333 }
8334 case MCK_VecListFourDWordIndexed: {
8335 DiagnosticPredicate DP(Operand.isVecListFourDWordIndexed());
8336 if (DP.isMatch())
8337 return MCTargetAsmParser::Match_Success;
8338 break;
8339 }
8340 case MCK_VecListFourQAllLanes: {
8341 DiagnosticPredicate DP(Operand.isVecListFourQAllLanes());
8342 if (DP.isMatch())
8343 return MCTargetAsmParser::Match_Success;
8344 break;
8345 }
8346 case MCK_VecListFourQ: {
8347 DiagnosticPredicate DP(Operand.isVecListFourQ());
8348 if (DP.isMatch())
8349 return MCTargetAsmParser::Match_Success;
8350 break;
8351 }
8352 case MCK_VecListFourQHWordIndexed: {
8353 DiagnosticPredicate DP(Operand.isVecListFourQHWordIndexed());
8354 if (DP.isMatch())
8355 return MCTargetAsmParser::Match_Success;
8356 break;
8357 }
8358 case MCK_VecListFourQWordIndexed: {
8359 DiagnosticPredicate DP(Operand.isVecListFourQWordIndexed());
8360 if (DP.isMatch())
8361 return MCTargetAsmParser::Match_Success;
8362 break;
8363 }
8364 case MCK_VecListOneDAllLanes: {
8365 DiagnosticPredicate DP(Operand.isVecListOneDAllLanes());
8366 if (DP.isMatch())
8367 return MCTargetAsmParser::Match_Success;
8368 break;
8369 }
8370 case MCK_VecListOneD: {
8371 DiagnosticPredicate DP(Operand.isVecListOneD());
8372 if (DP.isMatch())
8373 return MCTargetAsmParser::Match_Success;
8374 break;
8375 }
8376 case MCK_VecListOneDByteIndexed: {
8377 DiagnosticPredicate DP(Operand.isVecListOneDByteIndexed());
8378 if (DP.isMatch())
8379 return MCTargetAsmParser::Match_Success;
8380 break;
8381 }
8382 case MCK_VecListOneDHWordIndexed: {
8383 DiagnosticPredicate DP(Operand.isVecListOneDHWordIndexed());
8384 if (DP.isMatch())
8385 return MCTargetAsmParser::Match_Success;
8386 break;
8387 }
8388 case MCK_VecListOneDWordIndexed: {
8389 DiagnosticPredicate DP(Operand.isVecListOneDWordIndexed());
8390 if (DP.isMatch())
8391 return MCTargetAsmParser::Match_Success;
8392 break;
8393 }
8394 case MCK_VecListThreeDAllLanes: {
8395 DiagnosticPredicate DP(Operand.isVecListThreeDAllLanes());
8396 if (DP.isMatch())
8397 return MCTargetAsmParser::Match_Success;
8398 break;
8399 }
8400 case MCK_VecListThreeD: {
8401 DiagnosticPredicate DP(Operand.isVecListThreeD());
8402 if (DP.isMatch())
8403 return MCTargetAsmParser::Match_Success;
8404 break;
8405 }
8406 case MCK_VecListThreeDByteIndexed: {
8407 DiagnosticPredicate DP(Operand.isVecListThreeDByteIndexed());
8408 if (DP.isMatch())
8409 return MCTargetAsmParser::Match_Success;
8410 break;
8411 }
8412 case MCK_VecListThreeDHWordIndexed: {
8413 DiagnosticPredicate DP(Operand.isVecListThreeDHWordIndexed());
8414 if (DP.isMatch())
8415 return MCTargetAsmParser::Match_Success;
8416 break;
8417 }
8418 case MCK_VecListThreeDWordIndexed: {
8419 DiagnosticPredicate DP(Operand.isVecListThreeDWordIndexed());
8420 if (DP.isMatch())
8421 return MCTargetAsmParser::Match_Success;
8422 break;
8423 }
8424 case MCK_VecListThreeQAllLanes: {
8425 DiagnosticPredicate DP(Operand.isVecListThreeQAllLanes());
8426 if (DP.isMatch())
8427 return MCTargetAsmParser::Match_Success;
8428 break;
8429 }
8430 case MCK_VecListThreeQ: {
8431 DiagnosticPredicate DP(Operand.isVecListThreeQ());
8432 if (DP.isMatch())
8433 return MCTargetAsmParser::Match_Success;
8434 break;
8435 }
8436 case MCK_VecListThreeQHWordIndexed: {
8437 DiagnosticPredicate DP(Operand.isVecListThreeQHWordIndexed());
8438 if (DP.isMatch())
8439 return MCTargetAsmParser::Match_Success;
8440 break;
8441 }
8442 case MCK_VecListThreeQWordIndexed: {
8443 DiagnosticPredicate DP(Operand.isVecListThreeQWordIndexed());
8444 if (DP.isMatch())
8445 return MCTargetAsmParser::Match_Success;
8446 break;
8447 }
8448 case MCK_VecListTwoDByteIndexed: {
8449 DiagnosticPredicate DP(Operand.isVecListTwoDByteIndexed());
8450 if (DP.isMatch())
8451 return MCTargetAsmParser::Match_Success;
8452 break;
8453 }
8454 case MCK_VecListTwoDHWordIndexed: {
8455 DiagnosticPredicate DP(Operand.isVecListTwoDHWordIndexed());
8456 if (DP.isMatch())
8457 return MCTargetAsmParser::Match_Success;
8458 break;
8459 }
8460 case MCK_VecListTwoDWordIndexed: {
8461 DiagnosticPredicate DP(Operand.isVecListTwoDWordIndexed());
8462 if (DP.isMatch())
8463 return MCTargetAsmParser::Match_Success;
8464 break;
8465 }
8466 case MCK_VecListTwoQHWordIndexed: {
8467 DiagnosticPredicate DP(Operand.isVecListTwoQHWordIndexed());
8468 if (DP.isMatch())
8469 return MCTargetAsmParser::Match_Success;
8470 break;
8471 }
8472 case MCK_VecListTwoQWordIndexed: {
8473 DiagnosticPredicate DP(Operand.isVecListTwoQWordIndexed());
8474 if (DP.isMatch())
8475 return MCTargetAsmParser::Match_Success;
8476 break;
8477 }
8478 case MCK_VectorIndex16: {
8479 DiagnosticPredicate DP(Operand.isVectorIndex16());
8480 if (DP.isMatch())
8481 return MCTargetAsmParser::Match_Success;
8482 break;
8483 }
8484 case MCK_VectorIndex32: {
8485 DiagnosticPredicate DP(Operand.isVectorIndex32());
8486 if (DP.isMatch())
8487 return MCTargetAsmParser::Match_Success;
8488 break;
8489 }
8490 case MCK_VectorIndex64: {
8491 DiagnosticPredicate DP(Operand.isVectorIndex64());
8492 if (DP.isMatch())
8493 return MCTargetAsmParser::Match_Success;
8494 break;
8495 }
8496 case MCK_VectorIndex8: {
8497 DiagnosticPredicate DP(Operand.isVectorIndex8());
8498 if (DP.isMatch())
8499 return MCTargetAsmParser::Match_Success;
8500 break;
8501 }
8502 case MCK_MemTBB: {
8503 DiagnosticPredicate DP(Operand.isMemTBB());
8504 if (DP.isMatch())
8505 return MCTargetAsmParser::Match_Success;
8506 break;
8507 }
8508 case MCK_MemTBH: {
8509 DiagnosticPredicate DP(Operand.isMemTBH());
8510 if (DP.isMatch())
8511 return MCTargetAsmParser::Match_Success;
8512 break;
8513 }
8514 case MCK_NEONi16vmovi8Replicate: {
8515 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 16>());
8516 if (DP.isMatch())
8517 return MCTargetAsmParser::Match_Success;
8518 break;
8519 }
8520 case MCK_NEONi16invi8Replicate: {
8521 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 16>());
8522 if (DP.isMatch())
8523 return MCTargetAsmParser::Match_Success;
8524 break;
8525 }
8526 case MCK_NEONi32vmovi8Replicate: {
8527 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 32>());
8528 if (DP.isMatch())
8529 return MCTargetAsmParser::Match_Success;
8530 break;
8531 }
8532 case MCK_NEONi32invi8Replicate: {
8533 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 32>());
8534 if (DP.isMatch())
8535 return MCTargetAsmParser::Match_Success;
8536 break;
8537 }
8538 case MCK_NEONi64vmovi8Replicate: {
8539 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 64>());
8540 if (DP.isMatch())
8541 return MCTargetAsmParser::Match_Success;
8542 break;
8543 }
8544 case MCK_NEONi64invi8Replicate: {
8545 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 64>());
8546 if (DP.isMatch())
8547 return MCTargetAsmParser::Match_Success;
8548 break;
8549 }
8550 case MCK_NEONi32vmovi16Replicate: {
8551 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 32>());
8552 if (DP.isMatch())
8553 return MCTargetAsmParser::Match_Success;
8554 break;
8555 }
8556 case MCK_NEONi64vmovi16Replicate: {
8557 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 64>());
8558 if (DP.isMatch())
8559 return MCTargetAsmParser::Match_Success;
8560 break;
8561 }
8562 case MCK_NEONi64vmovi32Replicate: {
8563 DiagnosticPredicate DP(Operand.isNEONmovReplicate<32, 64>());
8564 if (DP.isMatch())
8565 return MCTargetAsmParser::Match_Success;
8566 break;
8567 }
8568 case MCK_MVEVectorIndex4: {
8569 DiagnosticPredicate DP(Operand.isVectorIndexInRange<4>());
8570 if (DP.isMatch())
8571 return MCTargetAsmParser::Match_Success;
8572 break;
8573 }
8574 case MCK_MVEVectorIndex8: {
8575 DiagnosticPredicate DP(Operand.isVectorIndexInRange<8>());
8576 if (DP.isMatch())
8577 return MCTargetAsmParser::Match_Success;
8578 break;
8579 }
8580 case MCK_MVEVectorIndex16: {
8581 DiagnosticPredicate DP(Operand.isVectorIndexInRange<16>());
8582 if (DP.isMatch())
8583 return MCTargetAsmParser::Match_Success;
8584 break;
8585 }
8586 case MCK_MVEVcvtImm32: {
8587 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
8588 if (DP.isMatch())
8589 return MCTargetAsmParser::Match_Success;
8590 if (DP.isNearMatch())
8591 return ARMAsmParser::Match_MVEVcvtImm32;
8592 break;
8593 }
8594 case MCK_MVEVcvtImm16: {
8595 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
8596 if (DP.isMatch())
8597 return MCTargetAsmParser::Match_Success;
8598 if (DP.isNearMatch())
8599 return ARMAsmParser::Match_MVEVcvtImm16;
8600 break;
8601 }
8602 case MCK_TMemImm7Shift2Offset: {
8603 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::tGPRRegClassID>());
8604 if (DP.isMatch())
8605 return MCTargetAsmParser::Match_Success;
8606 break;
8607 }
8608 case MCK_TMemImm7Shift0Offset: {
8609 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::tGPRRegClassID>());
8610 if (DP.isMatch())
8611 return MCTargetAsmParser::Match_Success;
8612 break;
8613 }
8614 case MCK_TMemImm7Shift1Offset: {
8615 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::tGPRRegClassID>());
8616 if (DP.isMatch())
8617 return MCTargetAsmParser::Match_Success;
8618 break;
8619 }
8620 case MCK_Imm3b: {
8621 DiagnosticPredicate DP(Operand.isImmediate<0,7>());
8622 if (DP.isMatch())
8623 return MCTargetAsmParser::Match_Success;
8624 if (DP.isNearMatch())
8625 return ARMAsmParser::Match_Imm3b;
8626 break;
8627 }
8628 case MCK_Imm4b: {
8629 DiagnosticPredicate DP(Operand.isImmediate<0,15>());
8630 if (DP.isMatch())
8631 return MCTargetAsmParser::Match_Success;
8632 if (DP.isNearMatch())
8633 return ARMAsmParser::Match_Imm4b;
8634 break;
8635 }
8636 case MCK_Imm6b: {
8637 DiagnosticPredicate DP(Operand.isImmediate<0,63>());
8638 if (DP.isMatch())
8639 return MCTargetAsmParser::Match_Success;
8640 if (DP.isNearMatch())
8641 return ARMAsmParser::Match_Imm6b;
8642 break;
8643 }
8644 case MCK_Imm7b: {
8645 DiagnosticPredicate DP(Operand.isImmediate<0,127>());
8646 if (DP.isMatch())
8647 return MCTargetAsmParser::Match_Success;
8648 if (DP.isNearMatch())
8649 return ARMAsmParser::Match_Imm7b;
8650 break;
8651 }
8652 case MCK_Imm9b: {
8653 DiagnosticPredicate DP(Operand.isImmediate<0,511>());
8654 if (DP.isMatch())
8655 return MCTargetAsmParser::Match_Success;
8656 if (DP.isNearMatch())
8657 return ARMAsmParser::Match_Imm9b;
8658 break;
8659 }
8660 case MCK_Imm11b: {
8661 DiagnosticPredicate DP(Operand.isImmediate<0,2047>());
8662 if (DP.isMatch())
8663 return MCTargetAsmParser::Match_Success;
8664 if (DP.isNearMatch())
8665 return ARMAsmParser::Match_Imm11b;
8666 break;
8667 }
8668 case MCK_Imm12b: {
8669 DiagnosticPredicate DP(Operand.isImmediate<0,4095>());
8670 if (DP.isMatch())
8671 return MCTargetAsmParser::Match_Success;
8672 if (DP.isNearMatch())
8673 return ARMAsmParser::Match_Imm12b;
8674 break;
8675 }
8676 case MCK_Imm13b: {
8677 DiagnosticPredicate DP(Operand.isImmediate<0,8191>());
8678 if (DP.isMatch())
8679 return MCTargetAsmParser::Match_Success;
8680 if (DP.isNearMatch())
8681 return ARMAsmParser::Match_Imm13b;
8682 break;
8683 }
8684 case MCK_MVEPairVectorIndex0: {
8685 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<0, 1>());
8686 if (DP.isMatch())
8687 return MCTargetAsmParser::Match_Success;
8688 break;
8689 }
8690 case MCK_MVEPairVectorIndex2: {
8691 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<2, 3>());
8692 if (DP.isMatch())
8693 return MCTargetAsmParser::Match_Success;
8694 break;
8695 }
8696 case MCK_ComplexRotationEven: {
8697 DiagnosticPredicate DP(Operand.isComplexRotation<90, 0>());
8698 if (DP.isMatch())
8699 return MCTargetAsmParser::Match_Success;
8700 if (DP.isNearMatch())
8701 return ARMAsmParser::Match_ComplexRotationEven;
8702 break;
8703 }
8704 case MCK_ComplexRotationOdd: {
8705 DiagnosticPredicate DP(Operand.isComplexRotation<180, 90>());
8706 if (DP.isMatch())
8707 return MCTargetAsmParser::Match_Success;
8708 if (DP.isNearMatch())
8709 return ARMAsmParser::Match_ComplexRotationOdd;
8710 break;
8711 }
8712 case MCK_ConstPoolAsmImm: {
8713 DiagnosticPredicate DP(Operand.isConstPoolAsmImm());
8714 if (DP.isMatch())
8715 return MCTargetAsmParser::Match_Success;
8716 break;
8717 }
8718 case MCK_FBits16: {
8719 DiagnosticPredicate DP(Operand.isFBits16());
8720 if (DP.isMatch())
8721 return MCTargetAsmParser::Match_Success;
8722 break;
8723 }
8724 case MCK_FBits32: {
8725 DiagnosticPredicate DP(Operand.isFBits32());
8726 if (DP.isMatch())
8727 return MCTargetAsmParser::Match_Success;
8728 break;
8729 }
8730 case MCK_Imm0_4095: {
8731 DiagnosticPredicate DP(Operand.isImmediate<0,4095>());
8732 if (DP.isMatch())
8733 return MCTargetAsmParser::Match_Success;
8734 if (DP.isNearMatch())
8735 return ARMAsmParser::Match_Imm0_4095;
8736 break;
8737 }
8738 case MCK_Imm0_4095Neg: {
8739 DiagnosticPredicate DP(Operand.isImm0_4095Neg());
8740 if (DP.isMatch())
8741 return MCTargetAsmParser::Match_Success;
8742 break;
8743 }
8744 case MCK_ITMask: {
8745 DiagnosticPredicate DP(Operand.isITMask());
8746 if (DP.isMatch())
8747 return MCTargetAsmParser::Match_Success;
8748 break;
8749 }
8750 case MCK_ITCondCode: {
8751 DiagnosticPredicate DP(Operand.isITCondCode());
8752 if (DP.isMatch())
8753 return MCTargetAsmParser::Match_Success;
8754 break;
8755 }
8756 case MCK_LELabel: {
8757 DiagnosticPredicate DP(Operand.isLEOffset());
8758 if (DP.isMatch())
8759 return MCTargetAsmParser::Match_Success;
8760 if (DP.isNearMatch())
8761 return ARMAsmParser::Match_LELabel;
8762 break;
8763 }
8764 case MCK_MVELongShift: {
8765 DiagnosticPredicate DP(Operand.isMVELongShift());
8766 if (DP.isMatch())
8767 return MCTargetAsmParser::Match_Success;
8768 if (DP.isNearMatch())
8769 return ARMAsmParser::Match_MVELongShift;
8770 break;
8771 }
8772 case MCK_NEONi16splat: {
8773 DiagnosticPredicate DP(Operand.isNEONi16splat());
8774 if (DP.isMatch())
8775 return MCTargetAsmParser::Match_Success;
8776 break;
8777 }
8778 case MCK_NEONi32splat: {
8779 DiagnosticPredicate DP(Operand.isNEONi32splat());
8780 if (DP.isMatch())
8781 return MCTargetAsmParser::Match_Success;
8782 break;
8783 }
8784 case MCK_NEONi64splat: {
8785 DiagnosticPredicate DP(Operand.isNEONi64splat());
8786 if (DP.isMatch())
8787 return MCTargetAsmParser::Match_Success;
8788 break;
8789 }
8790 case MCK_NEONi8splat: {
8791 DiagnosticPredicate DP(Operand.isNEONi8splat());
8792 if (DP.isMatch())
8793 return MCTargetAsmParser::Match_Success;
8794 break;
8795 }
8796 case MCK_NEONi16splatNot: {
8797 DiagnosticPredicate DP(Operand.isNEONi16splatNot());
8798 if (DP.isMatch())
8799 return MCTargetAsmParser::Match_Success;
8800 break;
8801 }
8802 case MCK_NEONi32splatNot: {
8803 DiagnosticPredicate DP(Operand.isNEONi32splatNot());
8804 if (DP.isMatch())
8805 return MCTargetAsmParser::Match_Success;
8806 break;
8807 }
8808 case MCK_NEONi32vmov: {
8809 DiagnosticPredicate DP(Operand.isNEONi32vmov());
8810 if (DP.isMatch())
8811 return MCTargetAsmParser::Match_Success;
8812 break;
8813 }
8814 case MCK_NEONi32vmovNeg: {
8815 DiagnosticPredicate DP(Operand.isNEONi32vmovNeg());
8816 if (DP.isMatch())
8817 return MCTargetAsmParser::Match_Success;
8818 break;
8819 }
8820 case MCK_CondCodeNoAL: {
8821 DiagnosticPredicate DP(Operand.isITCondCodeNoAL());
8822 if (DP.isMatch())
8823 return MCTargetAsmParser::Match_Success;
8824 break;
8825 }
8826 case MCK_CondCodeNoALInv: {
8827 DiagnosticPredicate DP(Operand.isITCondCodeNoAL());
8828 if (DP.isMatch())
8829 return MCTargetAsmParser::Match_Success;
8830 break;
8831 }
8832 case MCK_CondCodeRestrictedFP: {
8833 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedFP());
8834 if (DP.isMatch())
8835 return MCTargetAsmParser::Match_Success;
8836 if (DP.isNearMatch())
8837 return ARMAsmParser::Match_CondCodeRestrictedFP;
8838 break;
8839 }
8840 case MCK_CondCodeRestrictedI: {
8841 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedI());
8842 if (DP.isMatch())
8843 return MCTargetAsmParser::Match_Success;
8844 if (DP.isNearMatch())
8845 return ARMAsmParser::Match_CondCodeRestrictedI;
8846 break;
8847 }
8848 case MCK_CondCodeRestrictedS: {
8849 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedS());
8850 if (DP.isMatch())
8851 return MCTargetAsmParser::Match_Success;
8852 if (DP.isNearMatch())
8853 return ARMAsmParser::Match_CondCodeRestrictedS;
8854 break;
8855 }
8856 case MCK_CondCodeRestrictedU: {
8857 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedU());
8858 if (DP.isMatch())
8859 return MCTargetAsmParser::Match_Success;
8860 if (DP.isNearMatch())
8861 return ARMAsmParser::Match_CondCodeRestrictedU;
8862 break;
8863 }
8864 case MCK_ShrImm16: {
8865 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
8866 if (DP.isMatch())
8867 return MCTargetAsmParser::Match_Success;
8868 if (DP.isNearMatch())
8869 return ARMAsmParser::Match_ShrImm16;
8870 break;
8871 }
8872 case MCK_ShrImm32: {
8873 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
8874 if (DP.isMatch())
8875 return MCTargetAsmParser::Match_Success;
8876 if (DP.isNearMatch())
8877 return ARMAsmParser::Match_ShrImm32;
8878 break;
8879 }
8880 case MCK_ShrImm64: {
8881 DiagnosticPredicate DP(Operand.isImmediate<1,64>());
8882 if (DP.isMatch())
8883 return MCTargetAsmParser::Match_Success;
8884 if (DP.isNearMatch())
8885 return ARMAsmParser::Match_ShrImm64;
8886 break;
8887 }
8888 case MCK_ShrImm8: {
8889 DiagnosticPredicate DP(Operand.isImmediate<1,8>());
8890 if (DP.isMatch())
8891 return MCTargetAsmParser::Match_Success;
8892 if (DP.isNearMatch())
8893 return ARMAsmParser::Match_ShrImm8;
8894 break;
8895 }
8896 case MCK_T2SOImm: {
8897 DiagnosticPredicate DP(Operand.isT2SOImm());
8898 if (DP.isMatch())
8899 return MCTargetAsmParser::Match_Success;
8900 break;
8901 }
8902 case MCK_T2SOImmNeg: {
8903 DiagnosticPredicate DP(Operand.isT2SOImmNeg());
8904 if (DP.isMatch())
8905 return MCTargetAsmParser::Match_Success;
8906 break;
8907 }
8908 case MCK_T2SOImmNot: {
8909 DiagnosticPredicate DP(Operand.isT2SOImmNot());
8910 if (DP.isMatch())
8911 return MCTargetAsmParser::Match_Success;
8912 break;
8913 }
8914 case MCK_MemUImm12Offset: {
8915 DiagnosticPredicate DP(Operand.isMemUImm12Offset());
8916 if (DP.isMatch())
8917 return MCTargetAsmParser::Match_Success;
8918 break;
8919 }
8920 case MCK_T2MemRegOffset: {
8921 DiagnosticPredicate DP(Operand.isT2MemRegOffset());
8922 if (DP.isMatch())
8923 return MCTargetAsmParser::Match_Success;
8924 break;
8925 }
8926 case MCK_Imm7s4: {
8927 DiagnosticPredicate DP(Operand.isImm7s4());
8928 if (DP.isMatch())
8929 return MCTargetAsmParser::Match_Success;
8930 break;
8931 }
8932 case MCK_Imm7Shift0: {
8933 DiagnosticPredicate DP(Operand.isImm7Shift0());
8934 if (DP.isMatch())
8935 return MCTargetAsmParser::Match_Success;
8936 break;
8937 }
8938 case MCK_Imm7Shift1: {
8939 DiagnosticPredicate DP(Operand.isImm7Shift1());
8940 if (DP.isMatch())
8941 return MCTargetAsmParser::Match_Success;
8942 break;
8943 }
8944 case MCK_Imm7Shift2: {
8945 DiagnosticPredicate DP(Operand.isImm7Shift2());
8946 if (DP.isMatch())
8947 return MCTargetAsmParser::Match_Success;
8948 break;
8949 }
8950 case MCK_Imm8s4: {
8951 DiagnosticPredicate DP(Operand.isImm8s4());
8952 if (DP.isMatch())
8953 return MCTargetAsmParser::Match_Success;
8954 break;
8955 }
8956 case MCK_MemPCRelImm12: {
8957 DiagnosticPredicate DP(Operand.isMemPCRelImm12());
8958 if (DP.isMatch())
8959 return MCTargetAsmParser::Match_Success;
8960 break;
8961 }
8962 case MCK_MemThumbRIs1: {
8963 DiagnosticPredicate DP(Operand.isMemThumbRIs1());
8964 if (DP.isMatch())
8965 return MCTargetAsmParser::Match_Success;
8966 break;
8967 }
8968 case MCK_MemThumbRIs2: {
8969 DiagnosticPredicate DP(Operand.isMemThumbRIs2());
8970 if (DP.isMatch())
8971 return MCTargetAsmParser::Match_Success;
8972 break;
8973 }
8974 case MCK_MemThumbRIs4: {
8975 DiagnosticPredicate DP(Operand.isMemThumbRIs4());
8976 if (DP.isMatch())
8977 return MCTargetAsmParser::Match_Success;
8978 break;
8979 }
8980 case MCK_MemThumbRR: {
8981 DiagnosticPredicate DP(Operand.isMemThumbRR());
8982 if (DP.isMatch())
8983 return MCTargetAsmParser::Match_Success;
8984 break;
8985 }
8986 case MCK_MemThumbSPI: {
8987 DiagnosticPredicate DP(Operand.isMemThumbSPI());
8988 if (DP.isMatch())
8989 return MCTargetAsmParser::Match_Success;
8990 break;
8991 }
8992 case MCK_Imm0_1020s4: {
8993 DiagnosticPredicate DP(Operand.isImm0_1020s4());
8994 if (DP.isMatch())
8995 return MCTargetAsmParser::Match_Success;
8996 break;
8997 }
8998 case MCK_Imm0_508s4: {
8999 DiagnosticPredicate DP(Operand.isImm0_508s4());
9000 if (DP.isMatch())
9001 return MCTargetAsmParser::Match_Success;
9002 break;
9003 }
9004 case MCK_Imm0_508s4Neg: {
9005 DiagnosticPredicate DP(Operand.isImm0_508s4Neg());
9006 if (DP.isMatch())
9007 return MCTargetAsmParser::Match_Success;
9008 break;
9009 }
9010 case MCK_WLSLabel: {
9011 DiagnosticPredicate DP(Operand.isUnsignedOffset<11, 1>());
9012 if (DP.isMatch())
9013 return MCTargetAsmParser::Match_Success;
9014 if (DP.isNearMatch())
9015 return ARMAsmParser::Match_WLSLabel;
9016 break;
9017 }
9018 } // end switch (Kind)
9019
9020 if (Operand.isReg()) {
9021 static constexpr uint16_t Table[ARM::NUM_TARGET_REGS] = {
9022 InvalidMatchClass,
9023 MCK_APSR,
9024 MCK_APSR_NZCV,
9025 MCK_CCR,
9026 MCK_FPCXTRegs,
9027 MCK_FPCXTS,
9028 MCK_FPEXC,
9029 MCK_FPINST,
9030 MCK_FPSCR,
9031 MCK_cl_FPSCR_NZCV,
9032 MCK_FPSCR_NZCVQC,
9033 MCK_FPSID,
9034 InvalidMatchClass,
9035 MCK_GPRlr,
9036 MCK_PC,
9037 InvalidMatchClass,
9038 MCK_GPRsp,
9039 MCK_SPSR,
9040 MCK_VCCR,
9041 MCK_GPRwithZRnosp,
9042 MCK_DPR_8,
9043 MCK_DPR_8,
9044 MCK_DPR_8,
9045 MCK_DPR_8,
9046 MCK_DPR_8,
9047 MCK_DPR_8,
9048 MCK_DPR_8,
9049 MCK_DPR_8,
9050 MCK_DPR_VFP2,
9051 MCK_DPR_VFP2,
9052 MCK_DPR_VFP2,
9053 MCK_DPR_VFP2,
9054 MCK_DPR_VFP2,
9055 MCK_DPR_VFP2,
9056 MCK_DPR_VFP2,
9057 MCK_DPR_VFP2,
9058 MCK_DPR,
9059 MCK_DPR,
9060 MCK_DPR,
9061 MCK_DPR,
9062 MCK_DPR,
9063 MCK_DPR,
9064 MCK_DPR,
9065 MCK_DPR,
9066 MCK_DPR,
9067 MCK_DPR,
9068 MCK_DPR,
9069 MCK_DPR,
9070 MCK_DPR,
9071 MCK_DPR,
9072 MCK_DPR,
9073 MCK_DPR,
9074 MCK_FPINST2,
9075 MCK_MVFR0,
9076 MCK_MVFR1,
9077 MCK_MVFR2,
9078 MCK_P0,
9079 MCK_QPR_8,
9080 MCK_QPR_8,
9081 MCK_QPR_8,
9082 MCK_QPR_8,
9083 MCK_MQPR,
9084 MCK_MQPR,
9085 MCK_MQPR,
9086 MCK_MQPR,
9087 MCK_QPR,
9088 MCK_QPR,
9089 MCK_QPR,
9090 MCK_QPR,
9091 MCK_QPR,
9092 MCK_QPR,
9093 MCK_QPR,
9094 MCK_QPR,
9095 MCK_Reg17,
9096 MCK_Reg22,
9097 MCK_Reg17,
9098 MCK_Reg22,
9099 MCK_Reg18,
9100 MCK_Reg23,
9101 MCK_Reg18,
9102 MCK_Reg23,
9103 MCK_Reg33,
9104 MCK_Reg35,
9105 MCK_Reg33,
9106 MCK_Reg35,
9107 MCK_R12,
9108 MCK_SPR_8,
9109 MCK_SPR_8,
9110 MCK_SPR_8,
9111 MCK_SPR_8,
9112 MCK_SPR_8,
9113 MCK_SPR_8,
9114 MCK_SPR_8,
9115 MCK_SPR_8,
9116 MCK_SPR_8,
9117 MCK_SPR_8,
9118 MCK_SPR_8,
9119 MCK_SPR_8,
9120 MCK_SPR_8,
9121 MCK_SPR_8,
9122 MCK_SPR_8,
9123 MCK_SPR_8,
9124 MCK_HPR,
9125 MCK_HPR,
9126 MCK_HPR,
9127 MCK_HPR,
9128 MCK_HPR,
9129 MCK_HPR,
9130 MCK_HPR,
9131 MCK_HPR,
9132 MCK_HPR,
9133 MCK_HPR,
9134 MCK_HPR,
9135 MCK_HPR,
9136 MCK_HPR,
9137 MCK_HPR,
9138 MCK_HPR,
9139 MCK_HPR,
9140 MCK_Reg73,
9141 MCK_Reg73,
9142 MCK_Reg73,
9143 MCK_Reg73,
9144 MCK_Reg73,
9145 MCK_Reg73,
9146 MCK_Reg74,
9147 MCK_Reg74,
9148 MCK_Reg75,
9149 MCK_Reg75,
9150 MCK_Reg75,
9151 MCK_Reg75,
9152 MCK_Reg75,
9153 MCK_Reg75,
9154 MCK_Reg76,
9155 MCK_Reg76,
9156 MCK_DPairSpc,
9157 MCK_DPairSpc,
9158 MCK_DPairSpc,
9159 MCK_DPairSpc,
9160 MCK_DPairSpc,
9161 MCK_DPairSpc,
9162 MCK_DPairSpc,
9163 MCK_DPairSpc,
9164 MCK_DPairSpc,
9165 MCK_DPairSpc,
9166 MCK_DPairSpc,
9167 MCK_DPairSpc,
9168 MCK_DPairSpc,
9169 MCK_DPairSpc,
9170 MCK_Reg78,
9171 MCK_Reg78,
9172 MCK_Reg78,
9173 MCK_Reg79,
9174 MCK_MQQPR,
9175 MCK_MQQPR,
9176 MCK_MQQPR,
9177 MCK_Reg81,
9178 MCK_QQPR,
9179 MCK_QQPR,
9180 MCK_QQPR,
9181 MCK_QQPR,
9182 MCK_QQPR,
9183 MCK_QQPR,
9184 MCK_QQPR,
9185 MCK_Reg92,
9186 MCK_Reg93,
9187 MCK_Reg94,
9188 MCK_Reg95,
9189 MCK_MQQQQPR,
9190 MCK_Reg97,
9191 MCK_Reg98,
9192 MCK_Reg99,
9193 MCK_QQQQPR,
9194 MCK_QQQQPR,
9195 MCK_QQQQPR,
9196 MCK_QQQQPR,
9197 MCK_QQQQPR,
9198 MCK_Reg101,
9199 MCK_Reg101,
9200 MCK_Reg102,
9201 MCK_Reg102,
9202 MCK_Reg106,
9203 MCK_Reg106,
9204 MCK_Reg108,
9205 MCK_Reg116,
9206 MCK_Reg121,
9207 MCK_Reg116,
9208 MCK_Reg121,
9209 MCK_Reg116,
9210 MCK_Reg121,
9211 MCK_Reg117,
9212 MCK_Reg122,
9213 MCK_Reg118,
9214 MCK_Reg123,
9215 MCK_Reg118,
9216 MCK_Reg123,
9217 MCK_Reg118,
9218 MCK_Reg123,
9219 MCK_Reg119,
9220 MCK_Reg124,
9221 MCK_Reg120,
9222 MCK_Reg125,
9223 MCK_Reg120,
9224 MCK_Reg125,
9225 MCK_Reg120,
9226 MCK_Reg125,
9227 MCK_Reg120,
9228 MCK_Reg125,
9229 MCK_Reg120,
9230 MCK_Reg125,
9231 MCK_Reg120,
9232 MCK_Reg125,
9233 MCK_Reg120,
9234 MCK_Reg125,
9235 MCK_Reg126,
9236 MCK_Reg126,
9237 MCK_Reg126,
9238 MCK_Reg126,
9239 MCK_Reg127,
9240 MCK_Reg127,
9241 MCK_Reg128,
9242 MCK_Reg128,
9243 MCK_Reg129,
9244 MCK_Reg129,
9245 MCK_Reg129,
9246 MCK_Reg129,
9247 MCK_Reg130,
9248 MCK_Reg130,
9249 MCK_Reg131,
9250 MCK_Reg131,
9251 MCK_DTripleSpc,
9252 MCK_DTripleSpc,
9253 MCK_DTripleSpc,
9254 MCK_DTripleSpc,
9255 MCK_DTripleSpc,
9256 MCK_DTripleSpc,
9257 MCK_DTripleSpc,
9258 MCK_DTripleSpc,
9259 MCK_DTripleSpc,
9260 MCK_DTripleSpc,
9261 MCK_DTripleSpc,
9262 MCK_DTripleSpc,
9263 InvalidMatchClass,
9264 InvalidMatchClass,
9265 InvalidMatchClass,
9266 InvalidMatchClass,
9267 InvalidMatchClass,
9268 InvalidMatchClass,
9269 InvalidMatchClass,
9270 InvalidMatchClass,
9271 InvalidMatchClass,
9272 InvalidMatchClass,
9273 InvalidMatchClass,
9274 InvalidMatchClass,
9275 InvalidMatchClass,
9276 InvalidMatchClass,
9277 InvalidMatchClass,
9278 InvalidMatchClass,
9279 InvalidMatchClass,
9280 InvalidMatchClass,
9281 InvalidMatchClass,
9282 InvalidMatchClass,
9283 InvalidMatchClass,
9284 InvalidMatchClass,
9285 InvalidMatchClass,
9286 InvalidMatchClass,
9287 InvalidMatchClass,
9288 InvalidMatchClass,
9289 MCK_Reg52,
9290 MCK_Reg52,
9291 MCK_Reg52,
9292 MCK_Reg53,
9293 MCK_Reg50,
9294 MCK_Reg50,
9295 MCK_Reg50,
9296 MCK_Reg51,
9297 MCK_DPair,
9298 MCK_DPair,
9299 MCK_DPair,
9300 MCK_DPair,
9301 MCK_DPair,
9302 MCK_DPair,
9303 MCK_DPair,
9304 MCK_Reg133,
9305 MCK_Reg133,
9306 MCK_Reg134,
9307 MCK_Reg135,
9308 MCK_Reg136,
9309 MCK_Reg136,
9310 MCK_Reg137,
9311 MCK_Reg138,
9312 MCK_Reg139,
9313 MCK_Reg139,
9314 MCK_Reg139,
9315 MCK_Reg139,
9316 MCK_Reg139,
9317 MCK_Reg139,
9318 };
9319
9320 MCRegister Reg = Operand.getReg();
9321 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
9322 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
9323 getDiagKindFromRegisterClass(Kind);
9324 }
9325
9326 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
9327 return getDiagKindFromRegisterClass(Kind);
9328
9329 return MCTargetAsmParser::Match_InvalidOperand;
9330}
9331
9332#ifndef NDEBUG
9333const char *getMatchClassName(MatchClassKind Kind) {
9334 switch (Kind) {
9335 case InvalidMatchClass: return "InvalidMatchClass";
9336 case OptionalMatchClass: return "OptionalMatchClass";
9337 case MCK__DOT_d: return "MCK__DOT_d";
9338 case MCK__DOT_f: return "MCK__DOT_f";
9339 case MCK__DOT_s16: return "MCK__DOT_s16";
9340 case MCK__DOT_s32: return "MCK__DOT_s32";
9341 case MCK__DOT_s64: return "MCK__DOT_s64";
9342 case MCK__DOT_s8: return "MCK__DOT_s8";
9343 case MCK__DOT_u16: return "MCK__DOT_u16";
9344 case MCK__DOT_u32: return "MCK__DOT_u32";
9345 case MCK__DOT_u64: return "MCK__DOT_u64";
9346 case MCK__DOT_u8: return "MCK__DOT_u8";
9347 case MCK__DOT_f32: return "MCK__DOT_f32";
9348 case MCK__DOT_f64: return "MCK__DOT_f64";
9349 case MCK__DOT_i16: return "MCK__DOT_i16";
9350 case MCK__DOT_i32: return "MCK__DOT_i32";
9351 case MCK__DOT_i64: return "MCK__DOT_i64";
9352 case MCK__DOT_i8: return "MCK__DOT_i8";
9353 case MCK__DOT_p16: return "MCK__DOT_p16";
9354 case MCK__DOT_p8: return "MCK__DOT_p8";
9355 case MCK__EXCLAIM_: return "MCK__EXCLAIM_";
9356 case MCK__HASH_0: return "MCK__HASH_0";
9357 case MCK__HASH_16: return "MCK__HASH_16";
9358 case MCK__HASH_8: return "MCK__HASH_8";
9359 case MCK__DOT_16: return "MCK__DOT_16";
9360 case MCK__DOT_32: return "MCK__DOT_32";
9361 case MCK__DOT_64: return "MCK__DOT_64";
9362 case MCK__DOT_8: return "MCK__DOT_8";
9363 case MCK__DOT_bf16: return "MCK__DOT_bf16";
9364 case MCK__DOT_f16: return "MCK__DOT_f16";
9365 case MCK__DOT_p64: return "MCK__DOT_p64";
9366 case MCK__DOT_w: return "MCK__DOT_w";
9367 case MCK__91_: return "MCK__91_";
9368 case MCK__93_: return "MCK__93_";
9369 case MCK__94_: return "MCK__94_";
9370 case MCK__123_: return "MCK__123_";
9371 case MCK__125_: return "MCK__125_";
9372 case MCK_Reg108: return "MCK_Reg108";
9373 case MCK_Reg92: return "MCK_Reg92";
9374 case MCK_APSR: return "MCK_APSR";
9375 case MCK_APSR_NZCV: return "MCK_APSR_NZCV";
9376 case MCK_CCR: return "MCK_CCR";
9377 case MCK_FPCXTRegs: return "MCK_FPCXTRegs";
9378 case MCK_FPCXTS: return "MCK_FPCXTS";
9379 case MCK_FPEXC: return "MCK_FPEXC";
9380 case MCK_FPINST: return "MCK_FPINST";
9381 case MCK_FPINST2: return "MCK_FPINST2";
9382 case MCK_FPSCR: return "MCK_FPSCR";
9383 case MCK_FPSCR_NZCVQC: return "MCK_FPSCR_NZCVQC";
9384 case MCK_FPSID: return "MCK_FPSID";
9385 case MCK_GPRlr: return "MCK_GPRlr";
9386 case MCK_GPRsp: return "MCK_GPRsp";
9387 case MCK_MVFR0: return "MCK_MVFR0";
9388 case MCK_MVFR1: return "MCK_MVFR1";
9389 case MCK_MVFR2: return "MCK_MVFR2";
9390 case MCK_P0: return "MCK_P0";
9391 case MCK_PC: return "MCK_PC";
9392 case MCK_R12: return "MCK_R12";
9393 case MCK_SPSR: return "MCK_SPSR";
9394 case MCK_VCCR: return "MCK_VCCR";
9395 case MCK_cl_FPSCR_NZCV: return "MCK_cl_FPSCR_NZCV";
9396 case MCK_Reg133: return "MCK_Reg133";
9397 case MCK_Reg106: return "MCK_Reg106";
9398 case MCK_Reg101: return "MCK_Reg101";
9399 case MCK_Reg93: return "MCK_Reg93";
9400 case MCK_Reg35: return "MCK_Reg35";
9401 case MCK_Reg33: return "MCK_Reg33";
9402 case MCK_Reg22: return "MCK_Reg22";
9403 case MCK_Reg17: return "MCK_Reg17";
9404 case MCK_FP_STATUS_REGS: return "MCK_FP_STATUS_REGS";
9405 case MCK_Reg134: return "MCK_Reg134";
9406 case MCK_Reg121: return "MCK_Reg121";
9407 case MCK_Reg116: return "MCK_Reg116";
9408 case MCK_Reg107: return "MCK_Reg107";
9409 case MCK_Reg105: return "MCK_Reg105";
9410 case MCK_Reg94: return "MCK_Reg94";
9411 case MCK_Reg78: return "MCK_Reg78";
9412 case MCK_Reg21: return "MCK_Reg21";
9413 case MCK_Reg135: return "MCK_Reg135";
9414 case MCK_Reg126: return "MCK_Reg126";
9415 case MCK_Reg122: return "MCK_Reg122";
9416 case MCK_Reg117: return "MCK_Reg117";
9417 case MCK_Reg102: return "MCK_Reg102";
9418 case MCK_Reg95: return "MCK_Reg95";
9419 case MCK_Reg79: return "MCK_Reg79";
9420 case MCK_Reg34: return "MCK_Reg34";
9421 case MCK_Reg25: return "MCK_Reg25";
9422 case MCK_Reg23: return "MCK_Reg23";
9423 case MCK_Reg18: return "MCK_Reg18";
9424 case MCK_QPR_8: return "MCK_QPR_8";
9425 case MCK_tcGPRnotr12: return "MCK_tcGPRnotr12";
9426 case MCK_Reg90: return "MCK_Reg90";
9427 case MCK_Reg32: return "MCK_Reg32";
9428 case MCK_Reg30: return "MCK_Reg30";
9429 case MCK_MQQQQPR: return "MCK_MQQQQPR";
9430 case MCK_tcGPR: return "MCK_tcGPR";
9431 case MCK_Reg136: return "MCK_Reg136";
9432 case MCK_Reg127: return "MCK_Reg127";
9433 case MCK_Reg109: return "MCK_Reg109";
9434 case MCK_Reg97: return "MCK_Reg97";
9435 case MCK_Reg91: return "MCK_Reg91";
9436 case MCK_Reg73: return "MCK_Reg73";
9437 case MCK_Reg31: return "MCK_Reg31";
9438 case MCK_Reg28: return "MCK_Reg28";
9439 case MCK_Reg19: return "MCK_Reg19";
9440 case MCK_GPRPairnosp: return "MCK_GPRPairnosp";
9441 case MCK_tGPROdd: return "MCK_tGPROdd";
9442 case MCK_Reg137: return "MCK_Reg137";
9443 case MCK_Reg123: return "MCK_Reg123";
9444 case MCK_Reg118: return "MCK_Reg118";
9445 case MCK_Reg110: return "MCK_Reg110";
9446 case MCK_Reg98: return "MCK_Reg98";
9447 case MCK_Reg88: return "MCK_Reg88";
9448 case MCK_Reg52: return "MCK_Reg52";
9449 case MCK_Reg29: return "MCK_Reg29";
9450 case MCK_Reg26: return "MCK_Reg26";
9451 case MCK_GPRPair: return "MCK_GPRPair";
9452 case MCK_MQQPR: return "MCK_MQQPR";
9453 case MCK_Reg138: return "MCK_Reg138";
9454 case MCK_Reg128: return "MCK_Reg128";
9455 case MCK_Reg124: return "MCK_Reg124";
9456 case MCK_Reg119: return "MCK_Reg119";
9457 case MCK_Reg111: return "MCK_Reg111";
9458 case MCK_Reg99: return "MCK_Reg99";
9459 case MCK_Reg89: return "MCK_Reg89";
9460 case MCK_Reg81: return "MCK_Reg81";
9461 case MCK_Reg74: return "MCK_Reg74";
9462 case MCK_Reg53: return "MCK_Reg53";
9463 case MCK_DPR_8: return "MCK_DPR_8";
9464 case MCK_MQPR: return "MCK_MQPR";
9465 case MCK_hGPR: return "MCK_hGPR";
9466 case MCK_tGPR: return "MCK_tGPR";
9467 case MCK_tGPREven: return "MCK_tGPREven";
9468 case MCK_tGPRwithpc: return "MCK_tGPRwithpc";
9469 case MCK_Reg129: return "MCK_Reg129";
9470 case MCK_Reg2: return "MCK_Reg2";
9471 case MCK_Reg86: return "MCK_Reg86";
9472 case MCK_Reg14: return "MCK_Reg14";
9473 case MCK_Reg12: return "MCK_Reg12";
9474 case MCK_QQQQPR: return "MCK_QQQQPR";
9475 case MCK_Reg139: return "MCK_Reg139";
9476 case MCK_Reg130: return "MCK_Reg130";
9477 case MCK_Reg112: return "MCK_Reg112";
9478 case MCK_Reg87: return "MCK_Reg87";
9479 case MCK_Reg75: return "MCK_Reg75";
9480 case MCK_GPRnoip: return "MCK_GPRnoip";
9481 case MCK_rGPR: return "MCK_rGPR";
9482 case MCK_Reg125: return "MCK_Reg125";
9483 case MCK_Reg120: return "MCK_Reg120";
9484 case MCK_Reg113: return "MCK_Reg113";
9485 case MCK_Reg84: return "MCK_Reg84";
9486 case MCK_Reg50: return "MCK_Reg50";
9487 case MCK_GPRnopc: return "MCK_GPRnopc";
9488 case MCK_GPRnosp: return "MCK_GPRnosp";
9489 case MCK_GPRwithAPSR_NZCVnosp: return "MCK_GPRwithAPSR_NZCVnosp";
9490 case MCK_GPRwithAPSRnosp: return "MCK_GPRwithAPSRnosp";
9491 case MCK_GPRwithZRnosp: return "MCK_GPRwithZRnosp";
9492 case MCK_QQPR: return "MCK_QQPR";
9493 case MCK_Reg131: return "MCK_Reg131";
9494 case MCK_Reg114: return "MCK_Reg114";
9495 case MCK_Reg85: return "MCK_Reg85";
9496 case MCK_Reg76: return "MCK_Reg76";
9497 case MCK_Reg51: return "MCK_Reg51";
9498 case MCK_DPR_VFP2: return "MCK_DPR_VFP2";
9499 case MCK_GPR: return "MCK_GPR";
9500 case MCK_GPRwithAPSR: return "MCK_GPRwithAPSR";
9501 case MCK_GPRwithZR: return "MCK_GPRwithZR";
9502 case MCK_QPR: return "MCK_QPR";
9503 case MCK_SPR_8: return "MCK_SPR_8";
9504 case MCK_DTripleSpc: return "MCK_DTripleSpc";
9505 case MCK_DQuad: return "MCK_DQuad";
9506 case MCK_DPairSpc: return "MCK_DPairSpc";
9507 case MCK_DTriple: return "MCK_DTriple";
9508 case MCK_DPair: return "MCK_DPair";
9509 case MCK_DPR: return "MCK_DPR";
9510 case MCK_HPR: return "MCK_HPR";
9511 case MCK_FPWithVPR: return "MCK_FPWithVPR";
9512 case MCK_AM2OffsetImm: return "MCK_AM2OffsetImm";
9513 case MCK_AM3Offset: return "MCK_AM3Offset";
9514 case MCK_ARMBranchTarget: return "MCK_ARMBranchTarget";
9515 case MCK_AddrMode3: return "MCK_AddrMode3";
9516 case MCK_AddrMode5: return "MCK_AddrMode5";
9517 case MCK_AddrMode5FP16: return "MCK_AddrMode5FP16";
9518 case MCK_AlignedMemory16: return "MCK_AlignedMemory16";
9519 case MCK_AlignedMemory32: return "MCK_AlignedMemory32";
9520 case MCK_AlignedMemory64: return "MCK_AlignedMemory64";
9521 case MCK_AlignedMemory64or128: return "MCK_AlignedMemory64or128";
9522 case MCK_AlignedMemory64or128or256: return "MCK_AlignedMemory64or128or256";
9523 case MCK_AlignedMemoryNone: return "MCK_AlignedMemoryNone";
9524 case MCK_AlignedMemory: return "MCK_AlignedMemory";
9525 case MCK_DupAlignedMemory16: return "MCK_DupAlignedMemory16";
9526 case MCK_DupAlignedMemory32: return "MCK_DupAlignedMemory32";
9527 case MCK_DupAlignedMemory64: return "MCK_DupAlignedMemory64";
9528 case MCK_DupAlignedMemory64or128: return "MCK_DupAlignedMemory64or128";
9529 case MCK_DupAlignedMemoryNone: return "MCK_DupAlignedMemoryNone";
9530 case MCK_AdrLabel: return "MCK_AdrLabel";
9531 case MCK_BankedReg: return "MCK_BankedReg";
9532 case MCK_Bitfield: return "MCK_Bitfield";
9533 case MCK_CCOut: return "MCK_CCOut";
9534 case MCK_CondCode: return "MCK_CondCode";
9535 case MCK_CoprocNum: return "MCK_CoprocNum";
9536 case MCK_CoprocOption: return "MCK_CoprocOption";
9537 case MCK_CoprocReg: return "MCK_CoprocReg";
9538 case MCK_DPRRegList: return "MCK_DPRRegList";
9539 case MCK_FPDRegListWithVPR: return "MCK_FPDRegListWithVPR";
9540 case MCK_FPImm: return "MCK_FPImm";
9541 case MCK_FPSRegListWithVPR: return "MCK_FPSRegListWithVPR";
9542 case MCK_Imm0_15: return "MCK_Imm0_15";
9543 case MCK_Imm0_1: return "MCK_Imm0_1";
9544 case MCK_Imm0_239: return "MCK_Imm0_239";
9545 case MCK_Imm0_255: return "MCK_Imm0_255";
9546 case MCK_Imm0_255Expr: return "MCK_Imm0_255Expr";
9547 case MCK_Imm0_31: return "MCK_Imm0_31";
9548 case MCK_Imm0_32: return "MCK_Imm0_32";
9549 case MCK_Imm0_3: return "MCK_Imm0_3";
9550 case MCK_Imm0_63: return "MCK_Imm0_63";
9551 case MCK_Imm0_65535: return "MCK_Imm0_65535";
9552 case MCK_Imm0_65535Expr: return "MCK_Imm0_65535Expr";
9553 case MCK_Imm0_7: return "MCK_Imm0_7";
9554 case MCK_Imm16: return "MCK_Imm16";
9555 case MCK_Imm1_15: return "MCK_Imm1_15";
9556 case MCK_Imm1_16: return "MCK_Imm1_16";
9557 case MCK_Imm1_31: return "MCK_Imm1_31";
9558 case MCK_Imm1_32: return "MCK_Imm1_32";
9559 case MCK_Imm1_7: return "MCK_Imm1_7";
9560 case MCK_Imm24bit: return "MCK_Imm24bit";
9561 case MCK_Imm256_65535Expr: return "MCK_Imm256_65535Expr";
9562 case MCK_Imm32: return "MCK_Imm32";
9563 case MCK_Imm8: return "MCK_Imm8";
9564 case MCK_Imm8_255: return "MCK_Imm8_255";
9565 case MCK_Imm: return "MCK_Imm";
9566 case MCK_InstSyncBarrierOpt: return "MCK_InstSyncBarrierOpt";
9567 case MCK_MSRMask: return "MCK_MSRMask";
9568 case MCK_MVEShiftImm1_15: return "MCK_MVEShiftImm1_15";
9569 case MCK_MVEShiftImm1_7: return "MCK_MVEShiftImm1_7";
9570 case MCK_VIDUP_imm: return "MCK_VIDUP_imm";
9571 case MCK_MemBarrierOpt: return "MCK_MemBarrierOpt";
9572 case MCK_MemImm0_1020s4Offset: return "MCK_MemImm0_1020s4Offset";
9573 case MCK_MemImm12Offset: return "MCK_MemImm12Offset";
9574 case MCK_MemImm7Shift0Offset: return "MCK_MemImm7Shift0Offset";
9575 case MCK_MemImm7Shift0OffsetWB: return "MCK_MemImm7Shift0OffsetWB";
9576 case MCK_MemImm7Shift1Offset: return "MCK_MemImm7Shift1Offset";
9577 case MCK_MemImm7Shift1OffsetWB: return "MCK_MemImm7Shift1OffsetWB";
9578 case MCK_MemImm7Shift2Offset: return "MCK_MemImm7Shift2Offset";
9579 case MCK_MemImm7Shift2OffsetWB: return "MCK_MemImm7Shift2OffsetWB";
9580 case MCK_MemImm7s4Offset: return "MCK_MemImm7s4Offset";
9581 case MCK_MemImm8Offset: return "MCK_MemImm8Offset";
9582 case MCK_MemImm8s4Offset: return "MCK_MemImm8s4Offset";
9583 case MCK_MemNegImm8Offset: return "MCK_MemNegImm8Offset";
9584 case MCK_MemNoOffset: return "MCK_MemNoOffset";
9585 case MCK_MemNoOffsetT2: return "MCK_MemNoOffsetT2";
9586 case MCK_MemNoOffsetT2NoSp: return "MCK_MemNoOffsetT2NoSp";
9587 case MCK_MemNoOffsetT: return "MCK_MemNoOffsetT";
9588 case MCK_MemPosImm8Offset: return "MCK_MemPosImm8Offset";
9589 case MCK_MemRegOffset: return "MCK_MemRegOffset";
9590 case MCK_MemRegQS2Offset: return "MCK_MemRegQS2Offset";
9591 case MCK_MemRegQS3Offset: return "MCK_MemRegQS3Offset";
9592 case MCK_MemRegRQS0Offset: return "MCK_MemRegRQS0Offset";
9593 case MCK_MemRegRQS1Offset: return "MCK_MemRegRQS1Offset";
9594 case MCK_MemRegRQS2Offset: return "MCK_MemRegRQS2Offset";
9595 case MCK_MemRegRQS3Offset: return "MCK_MemRegRQS3Offset";
9596 case MCK_ModImm: return "MCK_ModImm";
9597 case MCK_ModImmNeg: return "MCK_ModImmNeg";
9598 case MCK_ModImmNot: return "MCK_ModImmNot";
9599 case MCK_MveSaturate: return "MCK_MveSaturate";
9600 case MCK_PKHASRImm: return "MCK_PKHASRImm";
9601 case MCK_PKHLSLImm: return "MCK_PKHLSLImm";
9602 case MCK_PostIdxImm8: return "MCK_PostIdxImm8";
9603 case MCK_PostIdxImm8s4: return "MCK_PostIdxImm8s4";
9604 case MCK_PostIdxReg: return "MCK_PostIdxReg";
9605 case MCK_PostIdxRegShifted: return "MCK_PostIdxRegShifted";
9606 case MCK_ProcIFlags: return "MCK_ProcIFlags";
9607 case MCK_RegList: return "MCK_RegList";
9608 case MCK_RegListWithAPSR: return "MCK_RegListWithAPSR";
9609 case MCK_RotImm: return "MCK_RotImm";
9610 case MCK_SPRRegList: return "MCK_SPRRegList";
9611 case MCK_SetEndImm: return "MCK_SetEndImm";
9612 case MCK_RegShiftedImm: return "MCK_RegShiftedImm";
9613 case MCK_RegShiftedReg: return "MCK_RegShiftedReg";
9614 case MCK_ShifterImm: return "MCK_ShifterImm";
9615 case MCK_ThumbBranchTarget: return "MCK_ThumbBranchTarget";
9616 case MCK_ThumbMemPC: return "MCK_ThumbMemPC";
9617 case MCK_ThumbModImmNeg1_7: return "MCK_ThumbModImmNeg1_7";
9618 case MCK_ThumbModImmNeg8_255: return "MCK_ThumbModImmNeg8_255";
9619 case MCK_ImmThumbSR: return "MCK_ImmThumbSR";
9620 case MCK_TraceSyncBarrierOpt: return "MCK_TraceSyncBarrierOpt";
9621 case MCK_UnsignedOffset_b8s2: return "MCK_UnsignedOffset_b8s2";
9622 case MCK_VPTPredN: return "MCK_VPTPredN";
9623 case MCK_VPTPredR: return "MCK_VPTPredR";
9624 case MCK_VecListTwoMQ: return "MCK_VecListTwoMQ";
9625 case MCK_VecListFourMQ: return "MCK_VecListFourMQ";
9626 case MCK_VecListDPairAllLanes: return "MCK_VecListDPairAllLanes";
9627 case MCK_VecListDPair: return "MCK_VecListDPair";
9628 case MCK_VecListDPairSpacedAllLanes: return "MCK_VecListDPairSpacedAllLanes";
9629 case MCK_VecListDPairSpaced: return "MCK_VecListDPairSpaced";
9630 case MCK_VecListFourDAllLanes: return "MCK_VecListFourDAllLanes";
9631 case MCK_VecListFourD: return "MCK_VecListFourD";
9632 case MCK_VecListFourDByteIndexed: return "MCK_VecListFourDByteIndexed";
9633 case MCK_VecListFourDHWordIndexed: return "MCK_VecListFourDHWordIndexed";
9634 case MCK_VecListFourDWordIndexed: return "MCK_VecListFourDWordIndexed";
9635 case MCK_VecListFourQAllLanes: return "MCK_VecListFourQAllLanes";
9636 case MCK_VecListFourQ: return "MCK_VecListFourQ";
9637 case MCK_VecListFourQHWordIndexed: return "MCK_VecListFourQHWordIndexed";
9638 case MCK_VecListFourQWordIndexed: return "MCK_VecListFourQWordIndexed";
9639 case MCK_VecListOneDAllLanes: return "MCK_VecListOneDAllLanes";
9640 case MCK_VecListOneD: return "MCK_VecListOneD";
9641 case MCK_VecListOneDByteIndexed: return "MCK_VecListOneDByteIndexed";
9642 case MCK_VecListOneDHWordIndexed: return "MCK_VecListOneDHWordIndexed";
9643 case MCK_VecListOneDWordIndexed: return "MCK_VecListOneDWordIndexed";
9644 case MCK_VecListThreeDAllLanes: return "MCK_VecListThreeDAllLanes";
9645 case MCK_VecListThreeD: return "MCK_VecListThreeD";
9646 case MCK_VecListThreeDByteIndexed: return "MCK_VecListThreeDByteIndexed";
9647 case MCK_VecListThreeDHWordIndexed: return "MCK_VecListThreeDHWordIndexed";
9648 case MCK_VecListThreeDWordIndexed: return "MCK_VecListThreeDWordIndexed";
9649 case MCK_VecListThreeQAllLanes: return "MCK_VecListThreeQAllLanes";
9650 case MCK_VecListThreeQ: return "MCK_VecListThreeQ";
9651 case MCK_VecListThreeQHWordIndexed: return "MCK_VecListThreeQHWordIndexed";
9652 case MCK_VecListThreeQWordIndexed: return "MCK_VecListThreeQWordIndexed";
9653 case MCK_VecListTwoDByteIndexed: return "MCK_VecListTwoDByteIndexed";
9654 case MCK_VecListTwoDHWordIndexed: return "MCK_VecListTwoDHWordIndexed";
9655 case MCK_VecListTwoDWordIndexed: return "MCK_VecListTwoDWordIndexed";
9656 case MCK_VecListTwoQHWordIndexed: return "MCK_VecListTwoQHWordIndexed";
9657 case MCK_VecListTwoQWordIndexed: return "MCK_VecListTwoQWordIndexed";
9658 case MCK_VectorIndex16: return "MCK_VectorIndex16";
9659 case MCK_VectorIndex32: return "MCK_VectorIndex32";
9660 case MCK_VectorIndex64: return "MCK_VectorIndex64";
9661 case MCK_VectorIndex8: return "MCK_VectorIndex8";
9662 case MCK_MemTBB: return "MCK_MemTBB";
9663 case MCK_MemTBH: return "MCK_MemTBH";
9664 case MCK_NEONi16vmovi8Replicate: return "MCK_NEONi16vmovi8Replicate";
9665 case MCK_NEONi16invi8Replicate: return "MCK_NEONi16invi8Replicate";
9666 case MCK_NEONi32vmovi8Replicate: return "MCK_NEONi32vmovi8Replicate";
9667 case MCK_NEONi32invi8Replicate: return "MCK_NEONi32invi8Replicate";
9668 case MCK_NEONi64vmovi8Replicate: return "MCK_NEONi64vmovi8Replicate";
9669 case MCK_NEONi64invi8Replicate: return "MCK_NEONi64invi8Replicate";
9670 case MCK_NEONi32vmovi16Replicate: return "MCK_NEONi32vmovi16Replicate";
9671 case MCK_NEONi64vmovi16Replicate: return "MCK_NEONi64vmovi16Replicate";
9672 case MCK_NEONi64vmovi32Replicate: return "MCK_NEONi64vmovi32Replicate";
9673 case MCK_MVEVectorIndex4: return "MCK_MVEVectorIndex4";
9674 case MCK_MVEVectorIndex8: return "MCK_MVEVectorIndex8";
9675 case MCK_MVEVectorIndex16: return "MCK_MVEVectorIndex16";
9676 case MCK_MVEVcvtImm32: return "MCK_MVEVcvtImm32";
9677 case MCK_MVEVcvtImm16: return "MCK_MVEVcvtImm16";
9678 case MCK_TMemImm7Shift2Offset: return "MCK_TMemImm7Shift2Offset";
9679 case MCK_TMemImm7Shift0Offset: return "MCK_TMemImm7Shift0Offset";
9680 case MCK_TMemImm7Shift1Offset: return "MCK_TMemImm7Shift1Offset";
9681 case MCK_Imm3b: return "MCK_Imm3b";
9682 case MCK_Imm4b: return "MCK_Imm4b";
9683 case MCK_Imm6b: return "MCK_Imm6b";
9684 case MCK_Imm7b: return "MCK_Imm7b";
9685 case MCK_Imm9b: return "MCK_Imm9b";
9686 case MCK_Imm11b: return "MCK_Imm11b";
9687 case MCK_Imm12b: return "MCK_Imm12b";
9688 case MCK_Imm13b: return "MCK_Imm13b";
9689 case MCK_MVEPairVectorIndex0: return "MCK_MVEPairVectorIndex0";
9690 case MCK_MVEPairVectorIndex2: return "MCK_MVEPairVectorIndex2";
9691 case MCK_ComplexRotationEven: return "MCK_ComplexRotationEven";
9692 case MCK_ComplexRotationOdd: return "MCK_ComplexRotationOdd";
9693 case MCK_ConstPoolAsmImm: return "MCK_ConstPoolAsmImm";
9694 case MCK_FBits16: return "MCK_FBits16";
9695 case MCK_FBits32: return "MCK_FBits32";
9696 case MCK_Imm0_4095: return "MCK_Imm0_4095";
9697 case MCK_Imm0_4095Neg: return "MCK_Imm0_4095Neg";
9698 case MCK_ITMask: return "MCK_ITMask";
9699 case MCK_ITCondCode: return "MCK_ITCondCode";
9700 case MCK_LELabel: return "MCK_LELabel";
9701 case MCK_MVELongShift: return "MCK_MVELongShift";
9702 case MCK_NEONi16splat: return "MCK_NEONi16splat";
9703 case MCK_NEONi32splat: return "MCK_NEONi32splat";
9704 case MCK_NEONi64splat: return "MCK_NEONi64splat";
9705 case MCK_NEONi8splat: return "MCK_NEONi8splat";
9706 case MCK_NEONi16splatNot: return "MCK_NEONi16splatNot";
9707 case MCK_NEONi32splatNot: return "MCK_NEONi32splatNot";
9708 case MCK_NEONi32vmov: return "MCK_NEONi32vmov";
9709 case MCK_NEONi32vmovNeg: return "MCK_NEONi32vmovNeg";
9710 case MCK_CondCodeNoAL: return "MCK_CondCodeNoAL";
9711 case MCK_CondCodeNoALInv: return "MCK_CondCodeNoALInv";
9712 case MCK_CondCodeRestrictedFP: return "MCK_CondCodeRestrictedFP";
9713 case MCK_CondCodeRestrictedI: return "MCK_CondCodeRestrictedI";
9714 case MCK_CondCodeRestrictedS: return "MCK_CondCodeRestrictedS";
9715 case MCK_CondCodeRestrictedU: return "MCK_CondCodeRestrictedU";
9716 case MCK_ShrImm16: return "MCK_ShrImm16";
9717 case MCK_ShrImm32: return "MCK_ShrImm32";
9718 case MCK_ShrImm64: return "MCK_ShrImm64";
9719 case MCK_ShrImm8: return "MCK_ShrImm8";
9720 case MCK_T2SOImm: return "MCK_T2SOImm";
9721 case MCK_T2SOImmNeg: return "MCK_T2SOImmNeg";
9722 case MCK_T2SOImmNot: return "MCK_T2SOImmNot";
9723 case MCK_MemUImm12Offset: return "MCK_MemUImm12Offset";
9724 case MCK_T2MemRegOffset: return "MCK_T2MemRegOffset";
9725 case MCK_Imm7s4: return "MCK_Imm7s4";
9726 case MCK_Imm7Shift0: return "MCK_Imm7Shift0";
9727 case MCK_Imm7Shift1: return "MCK_Imm7Shift1";
9728 case MCK_Imm7Shift2: return "MCK_Imm7Shift2";
9729 case MCK_Imm8s4: return "MCK_Imm8s4";
9730 case MCK_MemPCRelImm12: return "MCK_MemPCRelImm12";
9731 case MCK_MemThumbRIs1: return "MCK_MemThumbRIs1";
9732 case MCK_MemThumbRIs2: return "MCK_MemThumbRIs2";
9733 case MCK_MemThumbRIs4: return "MCK_MemThumbRIs4";
9734 case MCK_MemThumbRR: return "MCK_MemThumbRR";
9735 case MCK_MemThumbSPI: return "MCK_MemThumbSPI";
9736 case MCK_Imm0_1020s4: return "MCK_Imm0_1020s4";
9737 case MCK_Imm0_508s4: return "MCK_Imm0_508s4";
9738 case MCK_Imm0_508s4Neg: return "MCK_Imm0_508s4Neg";
9739 case MCK_WLSLabel: return "MCK_WLSLabel";
9740 case NumMatchClassKinds: return "NumMatchClassKinds";
9741 }
9742 llvm_unreachable("unhandled MatchClassKind!");
9743}
9744
9745#endif // NDEBUG
9746FeatureBitset ARMAsmParser::
9747ComputeAvailableFeatures(const FeatureBitset &FB) const {
9748 FeatureBitset Features;
9749 if (FB[ARM::HasV4TOps])
9750 Features.set(Feature_HasV4TBit);
9751 if (FB[ARM::HasV5TOps])
9752 Features.set(Feature_HasV5TBit);
9753 if (FB[ARM::HasV5TEOps])
9754 Features.set(Feature_HasV5TEBit);
9755 if (FB[ARM::HasV6Ops])
9756 Features.set(Feature_HasV6Bit);
9757 if (FB[ARM::HasV6MOps])
9758 Features.set(Feature_HasV6MBit);
9759 if (FB[ARM::HasV8MBaselineOps])
9760 Features.set(Feature_HasV8MBaselineBit);
9761 if (FB[ARM::HasV8MMainlineOps])
9762 Features.set(Feature_HasV8MMainlineBit);
9763 if (FB[ARM::HasV8_1MMainlineOps])
9764 Features.set(Feature_HasV8_1MMainlineBit);
9765 if (FB[ARM::HasMVEIntegerOps])
9766 Features.set(Feature_HasMVEIntBit);
9767 if (FB[ARM::HasMVEFloatOps])
9768 Features.set(Feature_HasMVEFloatBit);
9769 if (FB[ARM::HasCDEOps])
9770 Features.set(Feature_HasCDEBit);
9771 if (FB[ARM::FeatureFPRegs])
9772 Features.set(Feature_HasFPRegsBit);
9773 if (FB[ARM::FeatureFPRegs16])
9774 Features.set(Feature_HasFPRegs16Bit);
9775 if (!FB[ARM::FeatureFPRegs16])
9776 Features.set(Feature_HasNoFPRegs16Bit);
9777 if (FB[ARM::FeatureFPRegs64])
9778 Features.set(Feature_HasFPRegs64Bit);
9779 if (FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps])
9780 Features.set(Feature_HasFPRegsV8_1MBit);
9781 if (FB[ARM::HasV6T2Ops])
9782 Features.set(Feature_HasV6T2Bit);
9783 if (FB[ARM::HasV6KOps])
9784 Features.set(Feature_HasV6KBit);
9785 if (FB[ARM::HasV7Ops])
9786 Features.set(Feature_HasV7Bit);
9787 if (FB[ARM::HasV8Ops])
9788 Features.set(Feature_HasV8Bit);
9789 if (!FB[ARM::HasV8Ops])
9790 Features.set(Feature_PreV8Bit);
9791 if (FB[ARM::HasV8_1aOps])
9792 Features.set(Feature_HasV8_1aBit);
9793 if (FB[ARM::HasV8_2aOps])
9794 Features.set(Feature_HasV8_2aBit);
9795 if (FB[ARM::HasV8_3aOps])
9796 Features.set(Feature_HasV8_3aBit);
9797 if (FB[ARM::HasV8_4aOps])
9798 Features.set(Feature_HasV8_4aBit);
9799 if (FB[ARM::HasV8_5aOps])
9800 Features.set(Feature_HasV8_5aBit);
9801 if (FB[ARM::HasV8_6aOps])
9802 Features.set(Feature_HasV8_6aBit);
9803 if (FB[ARM::HasV8_7aOps])
9804 Features.set(Feature_HasV8_7aBit);
9805 if (FB[ARM::FeatureVFP2_SP])
9806 Features.set(Feature_HasVFP2Bit);
9807 if (FB[ARM::FeatureVFP3_D16_SP])
9808 Features.set(Feature_HasVFP3Bit);
9809 if (FB[ARM::FeatureVFP4_D16_SP])
9810 Features.set(Feature_HasVFP4Bit);
9811 if (FB[ARM::FeatureFP64])
9812 Features.set(Feature_HasDPVFPBit);
9813 if (FB[ARM::FeatureFPARMv8_D16_SP])
9814 Features.set(Feature_HasFPARMv8Bit);
9815 if (FB[ARM::FeatureNEON])
9816 Features.set(Feature_HasNEONBit);
9817 if (FB[ARM::FeatureSHA2])
9818 Features.set(Feature_HasSHA2Bit);
9819 if (FB[ARM::FeatureAES])
9820 Features.set(Feature_HasAESBit);
9821 if (FB[ARM::FeatureCrypto])
9822 Features.set(Feature_HasCryptoBit);
9823 if (FB[ARM::FeatureDotProd])
9824 Features.set(Feature_HasDotProdBit);
9825 if (FB[ARM::FeatureCRC])
9826 Features.set(Feature_HasCRCBit);
9827 if (FB[ARM::FeatureRAS])
9828 Features.set(Feature_HasRASBit);
9829 if (FB[ARM::FeatureLOB])
9830 Features.set(Feature_HasLOBBit);
9831 if (FB[ARM::FeaturePACBTI])
9832 Features.set(Feature_HasPACBTIBit);
9833 if (FB[ARM::FeatureFP16])
9834 Features.set(Feature_HasFP16Bit);
9835 if (FB[ARM::FeatureFullFP16])
9836 Features.set(Feature_HasFullFP16Bit);
9837 if (FB[ARM::FeatureFP16FML])
9838 Features.set(Feature_HasFP16FMLBit);
9839 if (FB[ARM::FeatureBF16])
9840 Features.set(Feature_HasBF16Bit);
9841 if (FB[ARM::FeatureMatMulInt8])
9842 Features.set(Feature_HasMatMulInt8Bit);
9843 if (FB[ARM::FeatureHWDivThumb])
9844 Features.set(Feature_HasDivideInThumbBit);
9845 if (FB[ARM::FeatureHWDivARM])
9846 Features.set(Feature_HasDivideInARMBit);
9847 if (FB[ARM::FeatureDSP])
9848 Features.set(Feature_HasDSPBit);
9849 if (FB[ARM::FeatureDB])
9850 Features.set(Feature_HasDBBit);
9851 if (FB[ARM::FeatureDFB])
9852 Features.set(Feature_HasDFBBit);
9853 if (FB[ARM::FeatureV7Clrex])
9854 Features.set(Feature_HasV7ClrexBit);
9855 if (FB[ARM::FeatureAcquireRelease])
9856 Features.set(Feature_HasAcquireReleaseBit);
9857 if (FB[ARM::FeatureMP])
9858 Features.set(Feature_HasMPBit);
9859 if (FB[ARM::FeatureVirtualization])
9860 Features.set(Feature_HasVirtualizationBit);
9861 if (FB[ARM::FeatureTrustZone])
9862 Features.set(Feature_HasTrustZoneBit);
9863 if (FB[ARM::Feature8MSecExt])
9864 Features.set(Feature_Has8MSecExtBit);
9865 if (FB[ARM::ModeThumb])
9866 Features.set(Feature_IsThumbBit);
9867 if (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2])
9868 Features.set(Feature_IsThumb2Bit);
9869 if (FB[ARM::FeatureMClass])
9870 Features.set(Feature_IsMClassBit);
9871 if (!FB[ARM::FeatureMClass])
9872 Features.set(Feature_IsNotMClassBit);
9873 if (!FB[ARM::ModeThumb])
9874 Features.set(Feature_IsARMBit);
9875 if (FB[ARM::FeatureNaClTrap])
9876 Features.set(Feature_UseNaClTrapBit);
9877 if (!FB[ARM::FeatureNoNegativeImmediates])
9878 Features.set(Feature_UseNegativeImmediatesBit);
9879 if (FB[ARM::FeatureSB])
9880 Features.set(Feature_HasSBBit);
9881 if (FB[ARM::FeatureCLRBHB])
9882 Features.set(Feature_HasCLRBHBBit);
9883 return Features;
9884}
9885
9886static const char MnemonicTable[] =
9887 "\000\t__brkdiv0\003adc\003add\004addw\003adr\004aesd\004aese\006aesimc\005"
9888 "aesmc\003and\003asr\004asrl\003aut\004autg\001b\002bf\003bfc\006bfcsel\003"
9889 "bfi\003bfl\004bflx\003bfx\003bic\004bkpt\002bl\003blx\005blxns\003bti\002"
9890 "bx\005bxaut\003bxj\004bxns\004cbnz\003cbz\003cdp\004cdp2\004cinc\004cin"
9891 "v\006clrbhb\005clrex\004clrm\003clz\003cmn\003cmp\004cneg\003cps\006crc"
9892 "32b\007crc32cb\007crc32ch\007crc32cw\006crc32h\006crc32w\004csdb\004cse"
9893 "l\004cset\005csetm\005csinc\005csinv\005csneg\003cx1\004cx1a\004cx1d\005"
9894 "cx1da\003cx2\004cx2a\004cx2d\005cx2da\003cx3\004cx3a\004cx3d\005cx3da\003"
9895 "dbg\005dcps1\005dcps2\005dcps3\003dfb\003dls\005dlstp\003dmb\003dsb\003"
9896 "eor\004eret\003esb\005faddd\005fadds\006fcmpzd\006fcmpzs\007fconstd\007"
9897 "fconsts\007fldmdbx\007fldmiax\005fmdhr\005fmdlr\006fmstat\007fstmdbx\007"
9898 "fstmiax\005fsubd\005fsubs\004hint\003hlt\003hvc\003isb\002it\004lctp\003"
9899 "lda\004ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ld"
9900 "c2\005ldc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004ldrb\005"
9901 "ldrbt\004ldrd\005ldrex\006ldrexb\006ldrexd\006ldrexh\004ldrh\005ldrht\005"
9902 "ldrsb\006ldrsbt\005ldrsh\006ldrsht\004ldrt\002le\004letp\003lsl\004lsll"
9903 "\003lsr\004lsrl\003mcr\004mcr2\004mcrr\005mcrr2\003mla\003mls\003mov\004"
9904 "movs\004movt\004movw\003mrc\004mrc2\004mrrc\005mrrc2\003mrs\003msr\003m"
9905 "ul\003mvn\003neg\003nop\003orn\003orr\003pac\006pacbti\004pacg\005pkhbt"
9906 "\005pkhtb\003pld\004pldw\003pli\003pop\005pssbb\004push\004qadd\006qadd"
9907 "16\005qadd8\004qasx\005qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub"
9908 "8\004rbit\003rev\005rev16\005revsh\005rfeda\005rfedb\005rfeia\005rfeib\003"
9909 "ror\003rrx\003rsb\003rsc\006sadd16\005sadd8\004sasx\002sb\003sbc\004sbf"
9910 "x\004sdiv\003sel\006setend\006setpan\003sev\004sevl\002sg\005sha1c\005s"
9911 "ha1h\005sha1m\005sha1p\007sha1su0\007sha1su1\007sha256h\010sha256h2\tsh"
9912 "a256su0\tsha256su1\007shadd16\006shadd8\005shasx\005shsax\007shsub16\006"
9913 "shsub8\003smc\006smlabb\006smlabt\005smlad\006smladx\005smlal\007smlalb"
9914 "b\007smlalbt\006smlald\007smlaldx\007smlaltb\007smlaltt\006smlatb\006sm"
9915 "latt\006smlawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smm"
9916 "la\006smmlar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006"
9917 "smulbb\006smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005sm"
9918 "usd\006smusdx\006sqrshr\007sqrshrl\005sqshl\006sqshll\005srsda\005srsdb"
9919 "\005srshr\006srshrl\005srsia\005srsib\004ssat\006ssat16\004ssax\004ssbb"
9920 "\006ssub16\005ssub8\003stc\004stc2\005stc2l\004stcl\003stl\004stlb\005s"
9921 "tlex\006stlexb\006stlexd\006stlexh\004stlh\003stm\005stmda\005stmdb\005"
9922 "stmib\003str\004strb\005strbt\004strd\005strex\006strexb\006strexd\006s"
9923 "trexh\004strh\005strht\004strt\003sub\004subs\004subw\003svc\003swp\004"
9924 "swpb\005sxtab\007sxtab16\005sxtah\004sxtb\006sxtb16\004sxth\003tbb\003t"
9925 "bh\003teq\004trap\003tsb\003tst\002tt\003tta\004ttat\003ttt\006uadd16\005"
9926 "uadd8\004uasx\004ubfx\003udf\004udiv\007uhadd16\006uhadd8\005uhasx\005u"
9927 "hsax\007uhsub16\006uhsub8\005umaal\005umlal\005umull\007uqadd16\006uqad"
9928 "d8\005uqasx\006uqrshl\007uqrshll\005uqsax\005uqshl\006uqshll\007uqsub16"
9929 "\006uqsub8\005urshr\006urshrl\005usad8\006usada8\004usat\006usat16\004u"
9930 "sax\006usub16\005usub8\005uxtab\007uxtab16\005uxtah\004uxtb\006uxtb16\004"
9931 "uxth\004vaba\005vabal\005vabav\004vabd\005vabdl\004vabs\005vacge\005vac"
9932 "gt\005vacle\005vaclt\004vadc\005vadci\004vadd\006vaddhn\005vaddl\006vad"
9933 "dlv\007vaddlva\005vaddv\006vaddva\005vaddw\004vand\004vbic\004vbif\004v"
9934 "bit\005vbrsr\004vbsl\005vcadd\004vceq\004vcge\004vcgt\004vcle\004vcls\004"
9935 "vclt\004vclz\005vcmla\004vcmp\005vcmpe\005vcmul\004vcnt\004vctp\004vcvt"
9936 "\005vcvta\005vcvtb\005vcvtm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\004vcx1"
9937 "\005vcx1a\004vcx2\005vcx2a\004vcx3\005vcx3a\005vddup\004vdiv\004vdot\004"
9938 "vdup\006vdwdup\004veor\004vext\004vfma\005vfmab\005vfmal\005vfmas\005vf"
9939 "mat\004vfms\005vfmsl\005vfnma\005vfnms\005vhadd\006vhcadd\005vhsub\005v"
9940 "idup\004vins\006viwdup\005vjcvt\004vld1\004vld2\005vld20\005vld21\004vl"
9941 "d3\004vld4\005vld40\005vld41\005vld42\005vld43\006vldmdb\006vldmia\004v"
9942 "ldr\005vldrb\005vldrd\005vldrh\005vldrw\005vlldm\005vlstm\004vmax\005vm"
9943 "axa\006vmaxav\006vmaxnm\007vmaxnma\010vmaxnmav\007vmaxnmv\005vmaxv\004v"
9944 "min\005vmina\006vminav\006vminnm\007vminnma\010vminnmav\007vminnmv\005v"
9945 "minv\004vmla\007vmladav\010vmladava\tvmladavax\010vmladavx\005vmlal\010"
9946 "vmlaldav\tvmlaldava\nvmlaldavax\tvmlaldavx\006vmlalv\007vmlalva\005vmla"
9947 "s\005vmlav\006vmlava\004vmls\007vmlsdav\010vmlsdava\tvmlsdavax\010vmlsd"
9948 "avx\005vmlsl\010vmlsldav\tvmlsldava\nvmlsldavax\tvmlsldavx\005vmmla\004"
9949 "vmov\005vmovl\006vmovlb\006vmovlt\005vmovn\006vmovnb\006vmovnt\005vmovx"
9950 "\004vmrs\004vmsr\004vmul\005vmulh\005vmull\006vmullb\006vmullt\004vmvn\004"
9951 "vneg\005vnmla\005vnmls\005vnmul\004vorn\004vorr\006vpadal\005vpadd\006v"
9952 "paddl\005vpmax\005vpmin\005vpnot\004vpop\005vpsel\004vpst\003vpt\005vpu"
9953 "sh\005vqabs\005vqadd\010vqdmladh\tvqdmladhx\007vqdmlah\007vqdmlal\010vq"
9954 "dmlash\010vqdmlsdh\tvqdmlsdhx\007vqdmlsl\007vqdmulh\007vqdmull\010vqdmu"
9955 "llb\010vqdmullt\006vqmovn\007vqmovnb\007vqmovnt\007vqmovun\010vqmovunb\010"
9956 "vqmovunt\005vqneg\tvqrdmladh\nvqrdmladhx\010vqrdmlah\tvqrdmlash\tvqrdml"
9957 "sdh\nvqrdmlsdhx\010vqrdmlsh\010vqrdmulh\006vqrshl\007vqrshrn\010vqrshrn"
9958 "b\010vqrshrnt\010vqrshrun\tvqrshrunb\tvqrshrunt\005vqshl\006vqshlu\006v"
9959 "qshrn\007vqshrnb\007vqshrnt\007vqshrun\010vqshrunb\010vqshrunt\005vqsub"
9960 "\007vraddhn\006vrecpe\006vrecps\006vrev16\006vrev32\006vrev64\006vrhadd"
9961 "\006vrinta\006vrintm\006vrintn\006vrintp\006vrintr\006vrintx\006vrintz\n"
9962 "vrmlaldavh\013vrmlaldavha\014vrmlaldavhax\013vrmlaldavhx\010vrmlalvh\tv"
9963 "rmlalvha\nvrmlsldavh\013vrmlsldavha\014vrmlsldavhax\013vrmlsldavhx\006v"
9964 "rmulh\005vrshl\005vrshr\006vrshrn\007vrshrnb\007vrshrnt\007vrsqrte\007v"
9965 "rsqrts\005vrsra\007vrsubhn\004vsbc\005vsbci\007vscclrm\005vsdot\006vsel"
9966 "eq\006vselge\006vselgt\006vselvs\004vshl\005vshlc\005vshll\006vshllb\006"
9967 "vshllt\004vshr\005vshrn\006vshrnb\006vshrnt\004vsli\006vsmmla\005vsqrt\004"
9968 "vsra\004vsri\004vst1\004vst2\005vst20\005vst21\004vst3\004vst4\005vst40"
9969 "\005vst41\005vst42\005vst43\006vstmdb\006vstmia\004vstr\005vstrb\005vst"
9970 "rd\005vstrh\005vstrw\004vsub\006vsubhn\005vsubl\005vsubw\006vsudot\004v"
9971 "swp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\006vummla\006vusdot\007vus"
9972 "mmla\004vuzp\004vzip\003wfe\003wfi\003wls\005wlstp\005yield";
9973
9974// Feature bitsets.
9975enum : uint8_t {
9976 AMFBS_None,
9977 AMFBS_Has8MSecExt,
9978 AMFBS_HasBF16,
9979 AMFBS_HasCDE,
9980 AMFBS_HasDB,
9981 AMFBS_HasDFB,
9982 AMFBS_HasDotProd,
9983 AMFBS_HasFP16,
9984 AMFBS_HasFPARMv8,
9985 AMFBS_HasFPRegs,
9986 AMFBS_HasFPRegs16,
9987 AMFBS_HasFPRegs64,
9988 AMFBS_HasFPRegsV8_1M,
9989 AMFBS_HasFullFP16,
9990 AMFBS_HasMVEFloat,
9991 AMFBS_HasMVEInt,
9992 AMFBS_HasMatMulInt8,
9993 AMFBS_HasNEON,
9994 AMFBS_HasV8_1MMainline,
9995 AMFBS_HasVFP2,
9996 AMFBS_HasVFP3,
9997 AMFBS_HasVFP4,
9998 AMFBS_IsARM,
9999 AMFBS_IsThumb,
10000 AMFBS_IsThumb2,
10001 AMFBS_HasBF16_HasNEON,
10002 AMFBS_HasCDE_HasFPRegs,
10003 AMFBS_HasCDE_HasMVEInt,
10004 AMFBS_HasDB_IsThumb2,
10005 AMFBS_HasDSP_IsThumb2,
10006 AMFBS_HasFPARMv8_HasDPVFP,
10007 AMFBS_HasFPARMv8_HasNEON,
10008 AMFBS_HasFPARMv8_HasV8_3a,
10009 AMFBS_HasFPRegs_HasV8_1MMainline,
10010 AMFBS_HasMVEInt_IsThumb,
10011 AMFBS_HasNEON_HasFP16,
10012 AMFBS_HasNEON_HasFP16FML,
10013 AMFBS_HasNEON_HasFullFP16,
10014 AMFBS_HasNEON_HasV8_1a,
10015 AMFBS_HasNEON_HasV8_3a,
10016 AMFBS_HasNEON_HasVFP4,
10017 AMFBS_HasV7_IsMClass,
10018 AMFBS_HasV8_HasAES,
10019 AMFBS_HasV8_HasNEON,
10020 AMFBS_HasV8_HasSHA2,
10021 AMFBS_HasV8MMainline_Has8MSecExt,
10022 AMFBS_HasV8_1MMainline_Has8MSecExt,
10023 AMFBS_HasV8_1MMainline_HasFPRegs,
10024 AMFBS_HasV8_1MMainline_HasMVEInt,
10025 AMFBS_HasVFP2_HasDPVFP,
10026 AMFBS_HasVFP3_HasDPVFP,
10027 AMFBS_HasVFP4_HasDPVFP,
10028 AMFBS_IsARM_HasAcquireRelease,
10029 AMFBS_IsARM_HasCRC,
10030 AMFBS_IsARM_HasDB,
10031 AMFBS_IsARM_HasDFB,
10032 AMFBS_IsARM_HasDivideInARM,
10033 AMFBS_IsARM_HasRAS,
10034 AMFBS_IsARM_HasSB,
10035 AMFBS_IsARM_HasTrustZone,
10036 AMFBS_IsARM_HasV4T,
10037 AMFBS_IsARM_HasV5T,
10038 AMFBS_IsARM_HasV5TE,
10039 AMFBS_IsARM_HasV6,
10040 AMFBS_IsARM_HasV6K,
10041 AMFBS_IsARM_HasV6T2,
10042 AMFBS_IsARM_HasV7,
10043 AMFBS_IsARM_HasV8,
10044 AMFBS_IsARM_HasV8_4a,
10045 AMFBS_IsARM_HasVirtualization,
10046 AMFBS_IsARM_PreV8,
10047 AMFBS_IsARM_UseNaClTrap,
10048 AMFBS_IsARM_UseNegativeImmediates,
10049 AMFBS_IsThumb_Has8MSecExt,
10050 AMFBS_IsThumb_HasAcquireRelease,
10051 AMFBS_IsThumb_HasDB,
10052 AMFBS_IsThumb_HasV5T,
10053 AMFBS_IsThumb_HasV6,
10054 AMFBS_IsThumb_HasV6M,
10055 AMFBS_IsThumb_HasV7Clrex,
10056 AMFBS_IsThumb_HasV8,
10057 AMFBS_IsThumb_HasV8MBaseline,
10058 AMFBS_IsThumb_HasV8_4a,
10059 AMFBS_IsThumb_HasVirtualization,
10060 AMFBS_IsThumb_IsMClass,
10061 AMFBS_IsThumb_IsNotMClass,
10062 AMFBS_IsThumb_UseNegativeImmediates,
10063 AMFBS_IsThumb2_HasCRC,
10064 AMFBS_IsThumb2_HasDSP,
10065 AMFBS_IsThumb2_HasRAS,
10066 AMFBS_IsThumb2_HasSB,
10067 AMFBS_IsThumb2_HasTrustZone,
10068 AMFBS_IsThumb2_HasV7,
10069 AMFBS_IsThumb2_HasV8,
10070 AMFBS_IsThumb2_HasVirtualization,
10071 AMFBS_IsThumb2_IsNotMClass,
10072 AMFBS_IsThumb2_PreV8,
10073 AMFBS_IsThumb2_UseNegativeImmediates,
10074 AMFBS_PreV8_IsThumb2,
10075 AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline,
10076 AMFBS_HasFPARMv8_HasNEON_HasFullFP16,
10077 AMFBS_HasNEON_HasV8_3a_HasFullFP16,
10078 AMFBS_HasV8_HasNEON_HasFullFP16,
10079 AMFBS_IsARM_HasAcquireRelease_HasV7Clrex,
10080 AMFBS_IsARM_HasV7_HasMP,
10081 AMFBS_IsARM_HasV8_HasCLRBHB,
10082 AMFBS_IsARM_HasV8_HasV8_1a,
10083 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex,
10084 AMFBS_IsThumb_HasV5T_IsNotMClass,
10085 AMFBS_IsThumb2_HasV7_HasMP,
10086 AMFBS_IsThumb2_HasV8_HasCLRBHB,
10087 AMFBS_IsThumb2_HasV8_HasV8_1a,
10088 AMFBS_IsThumb2_HasV8_1MMainline_HasLOB,
10089 AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI,
10090 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass,
10091};
10092
10093static constexpr FeatureBitset FeatureBitsets[] = {
10094 {}, // AMFBS_None
10095 {Feature_Has8MSecExtBit, },
10096 {Feature_HasBF16Bit, },
10097 {Feature_HasCDEBit, },
10098 {Feature_HasDBBit, },
10099 {Feature_HasDFBBit, },
10100 {Feature_HasDotProdBit, },
10101 {Feature_HasFP16Bit, },
10102 {Feature_HasFPARMv8Bit, },
10103 {Feature_HasFPRegsBit, },
10104 {Feature_HasFPRegs16Bit, },
10105 {Feature_HasFPRegs64Bit, },
10106 {Feature_HasFPRegsV8_1MBit, },
10107 {Feature_HasFullFP16Bit, },
10108 {Feature_HasMVEFloatBit, },
10109 {Feature_HasMVEIntBit, },
10110 {Feature_HasMatMulInt8Bit, },
10111 {Feature_HasNEONBit, },
10112 {Feature_HasV8_1MMainlineBit, },
10113 {Feature_HasVFP2Bit, },
10114 {Feature_HasVFP3Bit, },
10115 {Feature_HasVFP4Bit, },
10116 {Feature_IsARMBit, },
10117 {Feature_IsThumbBit, },
10118 {Feature_IsThumb2Bit, },
10119 {Feature_HasBF16Bit, Feature_HasNEONBit, },
10120 {Feature_HasCDEBit, Feature_HasFPRegsBit, },
10121 {Feature_HasCDEBit, Feature_HasMVEIntBit, },
10122 {Feature_HasDBBit, Feature_IsThumb2Bit, },
10123 {Feature_HasDSPBit, Feature_IsThumb2Bit, },
10124 {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, },
10125 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, },
10126 {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, },
10127 {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, },
10128 {Feature_HasMVEIntBit, Feature_IsThumbBit, },
10129 {Feature_HasNEONBit, Feature_HasFP16Bit, },
10130 {Feature_HasNEONBit, Feature_HasFP16FMLBit, },
10131 {Feature_HasNEONBit, Feature_HasFullFP16Bit, },
10132 {Feature_HasNEONBit, Feature_HasV8_1aBit, },
10133 {Feature_HasNEONBit, Feature_HasV8_3aBit, },
10134 {Feature_HasNEONBit, Feature_HasVFP4Bit, },
10135 {Feature_HasV7Bit, Feature_IsMClassBit, },
10136 {Feature_HasV8Bit, Feature_HasAESBit, },
10137 {Feature_HasV8Bit, Feature_HasNEONBit, },
10138 {Feature_HasV8Bit, Feature_HasSHA2Bit, },
10139 {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, },
10140 {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, },
10141 {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, },
10142 {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, },
10143 {Feature_HasVFP2Bit, Feature_HasDPVFPBit, },
10144 {Feature_HasVFP3Bit, Feature_HasDPVFPBit, },
10145 {Feature_HasVFP4Bit, Feature_HasDPVFPBit, },
10146 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, },
10147 {Feature_IsARMBit, Feature_HasCRCBit, },
10148 {Feature_IsARMBit, Feature_HasDBBit, },
10149 {Feature_IsARMBit, Feature_HasDFBBit, },
10150 {Feature_IsARMBit, Feature_HasDivideInARMBit, },
10151 {Feature_IsARMBit, Feature_HasRASBit, },
10152 {Feature_IsARMBit, Feature_HasSBBit, },
10153 {Feature_IsARMBit, Feature_HasTrustZoneBit, },
10154 {Feature_IsARMBit, Feature_HasV4TBit, },
10155 {Feature_IsARMBit, Feature_HasV5TBit, },
10156 {Feature_IsARMBit, Feature_HasV5TEBit, },
10157 {Feature_IsARMBit, Feature_HasV6Bit, },
10158 {Feature_IsARMBit, Feature_HasV6KBit, },
10159 {Feature_IsARMBit, Feature_HasV6T2Bit, },
10160 {Feature_IsARMBit, Feature_HasV7Bit, },
10161 {Feature_IsARMBit, Feature_HasV8Bit, },
10162 {Feature_IsARMBit, Feature_HasV8_4aBit, },
10163 {Feature_IsARMBit, Feature_HasVirtualizationBit, },
10164 {Feature_IsARMBit, Feature_PreV8Bit, },
10165 {Feature_IsARMBit, Feature_UseNaClTrapBit, },
10166 {Feature_IsARMBit, Feature_UseNegativeImmediatesBit, },
10167 {Feature_IsThumbBit, Feature_Has8MSecExtBit, },
10168 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, },
10169 {Feature_IsThumbBit, Feature_HasDBBit, },
10170 {Feature_IsThumbBit, Feature_HasV5TBit, },
10171 {Feature_IsThumbBit, Feature_HasV6Bit, },
10172 {Feature_IsThumbBit, Feature_HasV6MBit, },
10173 {Feature_IsThumbBit, Feature_HasV7ClrexBit, },
10174 {Feature_IsThumbBit, Feature_HasV8Bit, },
10175 {Feature_IsThumbBit, Feature_HasV8MBaselineBit, },
10176 {Feature_IsThumbBit, Feature_HasV8_4aBit, },
10177 {Feature_IsThumbBit, Feature_HasVirtualizationBit, },
10178 {Feature_IsThumbBit, Feature_IsMClassBit, },
10179 {Feature_IsThumbBit, Feature_IsNotMClassBit, },
10180 {Feature_IsThumbBit, Feature_UseNegativeImmediatesBit, },
10181 {Feature_IsThumb2Bit, Feature_HasCRCBit, },
10182 {Feature_IsThumb2Bit, Feature_HasDSPBit, },
10183 {Feature_IsThumb2Bit, Feature_HasRASBit, },
10184 {Feature_IsThumb2Bit, Feature_HasSBBit, },
10185 {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, },
10186 {Feature_IsThumb2Bit, Feature_HasV7Bit, },
10187 {Feature_IsThumb2Bit, Feature_HasV8Bit, },
10188 {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, },
10189 {Feature_IsThumb2Bit, Feature_IsNotMClassBit, },
10190 {Feature_IsThumb2Bit, Feature_PreV8Bit, },
10191 {Feature_IsThumb2Bit, Feature_UseNegativeImmediatesBit, },
10192 {Feature_PreV8Bit, Feature_IsThumb2Bit, },
10193 {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, },
10194 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, },
10195 {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, },
10196 {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, },
10197 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, },
10198 {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, },
10199 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCLRBHBBit, },
10200 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, },
10201 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, },
10202 {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, },
10203 {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, },
10204 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCLRBHBBit, },
10205 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, },
10206 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, },
10207 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasPACBTIBit, },
10208 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, },
10209};
10210
10211namespace {
10212 struct MatchEntry {
10213 uint16_t Mnemonic;
10214 uint16_t Opcode;
10215 uint16_t ConvertFn;
10216 uint8_t RequiredFeaturesIdx;
10217 uint16_t Classes[18];
10218 StringRef getMnemonic() const {
10219 return StringRef(MnemonicTable + Mnemonic + 1,
10220 MnemonicTable[Mnemonic]);
10221 }
10222 };
10223
10224 // Predicate for searching for an opcode.
10225 struct LessOpcode {
10226 bool operator()(const MatchEntry &LHS, StringRef RHS) {
10227 return LHS.getMnemonic() < RHS;
10228 }
10229 bool operator()(StringRef LHS, const MatchEntry &RHS) {
10230 return LHS < RHS.getMnemonic();
10231 }
10232 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
10233 return LHS.getMnemonic() < RHS.getMnemonic();
10234 }
10235 };
10236} // end anonymous namespace
10237
10238static const MatchEntry MatchTable0[] = {
10239 { 1 /* __brkdiv0 */, ARM::t__brkdiv0, Convert_NoOperands, AMFBS_IsThumb, { }, },
10240 { 11 /* adc */, ARM::tADC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10241 { 11 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10242 { 11 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10243 { 11 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10244 { 11 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10245 { 11 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10246 { 11 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10247 { 11 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10248 { 11 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10249 { 11 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10250 { 11 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10251 { 11 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10252 { 11 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10253 { 11 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10254 { 11 /* adc */, ARM::t2ADCri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10255 { 11 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10256 { 11 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10257 { 11 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10258 { 11 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10259 { 11 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
10260 { 11 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10261 { 11 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10262 { 11 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10263 { 11 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10264 { 11 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10265 { 11 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10266 { 15 /* add */, ARM::tADDspr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPR }, },
10267 { 15 /* add */, ARM::tADDspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
10268 { 15 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
10269 { 15 /* add */, ARM::tADDhirr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10270 { 15 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10271 { 15 /* add */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255Expr }, },
10272 { 15 /* add */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
10273 { 15 /* add */, ARM::tADDspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
10274 { 15 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
10275 { 15 /* add */, ARM::tADDrSPi, Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_GPRsp, MCK_Imm0_1020s4 }, },
10276 { 15 /* add */, ARM::tADDrSP, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPRsp, MCK_GPR }, },
10277 { 15 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
10278 { 15 /* add */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
10279 { 15 /* add */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
10280 { 15 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
10281 { 15 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10282 { 15 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
10283 { 15 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, },
10284 { 15 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, },
10285 { 15 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, },
10286 { 15 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, },
10287 { 15 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10288 { 15 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10289 { 15 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10290 { 15 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
10291 { 15 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
10292 { 15 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10293 { 15 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10294 { 15 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
10295 { 15 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10296 { 15 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10297 { 15 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
10298 { 15 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10299 { 15 /* add */, ARM::t2ADR, Convert__Reg1_1__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_PC, MCK_Imm0_4095 }, },
10300 { 15 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
10301 { 15 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
10302 { 15 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, },
10303 { 15 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImmNeg }, },
10304 { 15 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNeg }, },
10305 { 15 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
10306 { 15 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10307 { 15 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10308 { 15 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
10309 { 15 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10310 { 15 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10311 { 15 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
10312 { 15 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
10313 { 15 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10314 { 15 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10315 { 15 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
10316 { 15 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10317 { 15 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10318 { 15 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
10319 { 15 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10320 { 15 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10321 { 15 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
10322 { 15 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10323 { 15 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10324 { 15 /* add */, ARM::t2ADDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
10325 { 15 /* add */, ARM::t2ADDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
10326 { 19 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
10327 { 19 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10328 { 19 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
10329 { 19 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, },
10330 { 19 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
10331 { 19 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10332 { 19 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_4095Neg }, },
10333 { 19 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
10334 { 24 /* adr */, ARM::tADR, Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_UnsignedOffset_b8s2 }, },
10335 { 24 /* adr */, ARM::t2ADR, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10336 { 24 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, },
10337 { 24 /* adr */, ARM::t2ADR, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm }, },
10338 { 28 /* aesd */, ARM::AESD, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10339 { 33 /* aese */, ARM::AESE, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10340 { 38 /* aesimc */, ARM::AESIMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10341 { 45 /* aesmc */, ARM::AESMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10342 { 51 /* and */, ARM::tAND, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10343 { 51 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10344 { 51 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10345 { 51 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10346 { 51 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10347 { 51 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10348 { 51 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10349 { 51 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10350 { 51 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10351 { 51 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10352 { 51 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10353 { 51 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10354 { 51 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10355 { 51 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, },
10356 { 51 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10357 { 51 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10358 { 51 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10359 { 51 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10360 { 51 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10361 { 51 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10362 { 51 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10363 { 51 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10364 { 51 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10365 { 51 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10366 { 51 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10367 { 51 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10368 { 51 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10369 { 55 /* asr */, ARM::tASRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10370 { 55 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
10371 { 55 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
10372 { 55 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10373 { 55 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
10374 { 55 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10375 { 55 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
10376 { 55 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10377 { 55 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
10378 { 55 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10379 { 55 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
10380 { 55 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10381 { 55 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
10382 { 55 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10383 { 55 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
10384 { 59 /* asrl */, ARM::MVE_ASRLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, },
10385 { 59 /* asrl */, ARM::MVE_ASRLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
10386 { 64 /* aut */, ARM::t2AUT, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
10387 { 64 /* aut */, ARM::t2HINT, Convert__imm_95_45__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
10388 { 68 /* autg */, ARM::t2AUTG, Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_GPRnosp, MCK_GPRnopc, MCK_GPRnopc }, },
10389 { 73 /* b */, ARM::tB, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm }, },
10390 { 73 /* b */, ARM::tBcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
10391 { 73 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
10392 { 73 /* b */, ARM::t2Bcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
10393 { 73 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, },
10394 { 75 /* bf */, ARM::t2BFi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, },
10395 { 78 /* bfc */, ARM::t2BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Bitfield }, },
10396 { 78 /* bfc */, ARM::BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Bitfield }, },
10397 { 82 /* bfcsel */, ARM::t2BFic, Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_Imm, MCK_Imm, MCK_Imm, MCK_CondCodeNoAL }, },
10398 { 89 /* bfi */, ARM::t2BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Bitfield }, },
10399 { 89 /* bfi */, ARM::BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Bitfield }, },
10400 { 93 /* bfl */, ARM::t2BFLi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, },
10401 { 97 /* bflx */, ARM::t2BFLr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, },
10402 { 102 /* bfx */, ARM::t2BFr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, },
10403 { 106 /* bic */, ARM::tBIC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10404 { 106 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10405 { 106 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10406 { 106 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10407 { 106 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10408 { 106 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10409 { 106 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10410 { 106 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10411 { 106 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10412 { 106 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10413 { 106 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10414 { 106 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10415 { 106 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10416 { 106 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, },
10417 { 106 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10418 { 106 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10419 { 106 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10420 { 106 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10421 { 106 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10422 { 106 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10423 { 106 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10424 { 106 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10425 { 106 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10426 { 106 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10427 { 106 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10428 { 106 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10429 { 106 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10430 { 110 /* bkpt */, ARM::tBKPT, Convert__imm_95_0, AMFBS_IsThumb, { }, },
10431 { 110 /* bkpt */, ARM::tBKPT, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, },
10432 { 110 /* bkpt */, ARM::BKPT, Convert__imm_95_0, AMFBS_IsARM, { }, },
10433 { 110 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, },
10434 { 115 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, AMFBS_IsARM, { MCK_ARMBranchTarget }, },
10435 { 115 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
10436 { 115 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
10437 { 115 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, },
10438 { 118 /* blx */, ARM::tBLXr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_HasV5T, { MCK_CondCode, MCK_GPR }, },
10439 { 118 /* blx */, ARM::BLX, Convert__Reg1_0, AMFBS_IsARM_HasV5T, { MCK_GPR }, },
10440 { 118 /* blx */, ARM::BLXi, Convert__ThumbBranchTarget1_0, AMFBS_IsARM_HasV5T, { MCK_ThumbBranchTarget }, },
10441 { 118 /* blx */, ARM::BLX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR }, },
10442 { 118 /* blx */, ARM::tBLXi, Convert__CondCode2_0__ARMBranchTarget1_1, AMFBS_IsThumb_HasV5T_IsNotMClass, { MCK_CondCode, MCK_ARMBranchTarget }, },
10443 { 122 /* blxns */, ARM::tBLXNSr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
10444 { 128 /* bti */, ARM::t2BTI, Convert_NoOperands, AMFBS_HasV7_IsMClass, { }, },
10445 { 128 /* bti */, ARM::t2HINT, Convert__imm_95_15__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, },
10446 { 132 /* bx */, ARM::tBX, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR }, },
10447 { 132 /* bx */, ARM::BX, Convert__Reg1_0, AMFBS_IsARM_HasV4T, { MCK_GPR }, },
10448 { 132 /* bx */, ARM::BX_RET, Convert__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPRlr }, },
10449 { 132 /* bx */, ARM::BX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPR }, },
10450 { 135 /* bxaut */, ARM::t2BXAUT, Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_GPRnosp, MCK_rGPR, MCK_GPRnopc }, },
10451 { 141 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, },
10452 { 141 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR }, },
10453 { 145 /* bxns */, ARM::tBXNS, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPR }, },
10454 { 150 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
10455 { 155 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
10456 { 159 /* cdp */, ARM::CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10457 { 159 /* cdp */, ARM::t2CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10458 { 163 /* cdp2 */, ARM::CDP2, Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10459 { 163 /* cdp2 */, ARM::t2CDP2, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10460 { 168 /* cinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
10461 { 173 /* cinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
10462 { 178 /* clrbhb */, ARM::HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsARM_HasV8_HasCLRBHB, { MCK_CondCode }, },
10463 { 178 /* clrbhb */, ARM::t2HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsThumb2_HasV8_HasCLRBHB, { MCK_CondCode }, },
10464 { 178 /* clrbhb */, ARM::HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, },
10465 { 178 /* clrbhb */, ARM::t2HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
10466 { 185 /* clrex */, ARM::CLREX, Convert_NoOperands, AMFBS_IsARM_HasV6K, { }, },
10467 { 185 /* clrex */, ARM::t2CLREX, Convert__CondCode2_0, AMFBS_IsThumb_HasV7Clrex, { MCK_CondCode }, },
10468 { 191 /* clrm */, ARM::t2CLRM, Convert__CondCode2_0__RegListWithAPSR1_1, AMFBS_HasV8_1MMainline, { MCK_CondCode, MCK_RegListWithAPSR }, },
10469 { 196 /* clz */, ARM::t2CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10470 { 196 /* clz */, ARM::CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10471 { 200 /* cmn */, ARM::tCMNz, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10472 { 200 /* cmn */, ARM::CMPri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
10473 { 200 /* cmn */, ARM::t2CMPri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10474 { 200 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
10475 { 200 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
10476 { 200 /* cmn */, ARM::CMNzrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10477 { 200 /* cmn */, ARM::t2CMNri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
10478 { 200 /* cmn */, ARM::CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10479 { 200 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10480 { 200 /* cmn */, ARM::CMNzrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10481 { 200 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
10482 { 200 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
10483 { 200 /* cmn */, ARM::t2CMNri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
10484 { 204 /* cmp */, ARM::tCMPr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10485 { 204 /* cmp */, ARM::tCMPi8, Convert__Reg1_1__Imm0_2551_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
10486 { 204 /* cmp */, ARM::tCMPhir, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10487 { 204 /* cmp */, ARM::CMNri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
10488 { 204 /* cmp */, ARM::t2CMNri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10489 { 204 /* cmp */, ARM::t2CMPrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
10490 { 204 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10491 { 204 /* cmp */, ARM::t2CMPri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
10492 { 204 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10493 { 204 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10494 { 204 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10495 { 204 /* cmp */, ARM::t2CMPrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
10496 { 204 /* cmp */, ARM::t2CMPrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
10497 { 204 /* cmp */, ARM::t2CMPri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
10498 { 208 /* cneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
10499 { 213 /* cps */, ARM::tCPS, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsThumb, { MCK_Imm, MCK_ProcIFlags }, },
10500 { 213 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm0_31 }, },
10501 { 213 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
10502 { 213 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_31 }, },
10503 { 213 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags }, },
10504 { 213 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, },
10505 { 213 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, },
10506 { 213 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, },
10507 { 213 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_2__Imm1_3, AMFBS_IsThumb2, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags, MCK_Imm }, },
10508 { 217 /* crc32b */, ARM::t2CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10509 { 217 /* crc32b */, ARM::CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10510 { 224 /* crc32cb */, ARM::t2CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10511 { 224 /* crc32cb */, ARM::CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10512 { 232 /* crc32ch */, ARM::t2CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10513 { 232 /* crc32ch */, ARM::CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10514 { 240 /* crc32cw */, ARM::t2CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10515 { 240 /* crc32cw */, ARM::CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10516 { 248 /* crc32h */, ARM::t2CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10517 { 248 /* crc32h */, ARM::CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10518 { 255 /* crc32w */, ARM::t2CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10519 { 255 /* crc32w */, ARM::CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10520 { 262 /* csdb */, ARM::HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
10521 { 262 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, },
10522 { 262 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
10523 { 267 /* csel */, ARM::t2CSEL, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
10524 { 272 /* cset */, ARM::t2CSINC, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, },
10525 { 277 /* csetm */, ARM::t2CSINV, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, },
10526 { 283 /* csinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
10527 { 289 /* csinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
10528 { 295 /* csneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
10529 { 301 /* cx1 */, ARM::CDE_CX1, Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm13b }, },
10530 { 305 /* cx1a */, ARM::CDE_CX1A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm13b }, },
10531 { 310 /* cx1d */, ARM::CDE_CX1D, Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_Imm13b }, },
10532 { 315 /* cx1da */, ARM::CDE_CX1DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_Imm13b }, },
10533 { 321 /* cx2 */, ARM::CDE_CX2, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
10534 { 325 /* cx2a */, ARM::CDE_CX2A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
10535 { 330 /* cx2d */, ARM::CDE_CX2D, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
10536 { 335 /* cx2da */, ARM::CDE_CX2DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
10537 { 341 /* cx3 */, ARM::CDE_CX3, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
10538 { 345 /* cx3a */, ARM::CDE_CX3A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
10539 { 350 /* cx3d */, ARM::CDE_CX3D, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
10540 { 355 /* cx3da */, ARM::CDE_CX3DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
10541 { 361 /* dbg */, ARM::DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasV7, { MCK_CondCode, MCK_Imm0_15 }, },
10542 { 361 /* dbg */, ARM::t2DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_15 }, },
10543 { 361 /* dbg */, ARM::t2DBG, Convert__Imm0_151_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_15 }, },
10544 { 365 /* dcps1 */, ARM::t2DCPS1, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
10545 { 371 /* dcps2 */, ARM::t2DCPS2, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
10546 { 377 /* dcps3 */, ARM::t2DCPS3, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
10547 { 383 /* dfb */, ARM::DSB, Convert__imm_95_12, AMFBS_IsARM_HasDFB, { }, },
10548 { 383 /* dfb */, ARM::t2DSB, Convert__imm_95_12__CondCode2_0, AMFBS_HasDFB, { MCK_CondCode }, },
10549 { 387 /* dls */, ARM::t2DLS, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR }, },
10550 { 391 /* dlstp */, ARM::MVE_DLSTP_16, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR }, },
10551 { 391 /* dlstp */, ARM::MVE_DLSTP_32, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR }, },
10552 { 391 /* dlstp */, ARM::MVE_DLSTP_64, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR }, },
10553 { 391 /* dlstp */, ARM::MVE_DLSTP_8, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR }, },
10554 { 397 /* dmb */, ARM::DMB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
10555 { 397 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
10556 { 397 /* dmb */, ARM::DMB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, },
10557 { 397 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
10558 { 397 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
10559 { 397 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, },
10560 { 401 /* dsb */, ARM::DSB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
10561 { 401 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
10562 { 401 /* dsb */, ARM::DSB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, },
10563 { 401 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
10564 { 401 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
10565 { 401 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, },
10566 { 405 /* eor */, ARM::tEOR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10567 { 405 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10568 { 405 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10569 { 405 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10570 { 405 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10571 { 405 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10572 { 405 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10573 { 405 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10574 { 405 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10575 { 405 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10576 { 405 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10577 { 405 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10578 { 405 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10579 { 405 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10580 { 405 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10581 { 405 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10582 { 405 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10583 { 405 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10584 { 405 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10585 { 405 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10586 { 405 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10587 { 409 /* eret */, ARM::ERET, Convert__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode }, },
10588 { 409 /* eret */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2_HasVirtualization, { MCK_CondCode }, },
10589 { 414 /* esb */, ARM::HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsARM_HasRAS, { MCK_CondCode }, },
10590 { 414 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode }, },
10591 { 414 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode, MCK__DOT_w }, },
10592 { 418 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
10593 { 424 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10594 { 430 /* fcmpzd */, ARM::VCMPZD, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR }, },
10595 { 437 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR }, },
10596 { 444 /* fconstd */, ARM::FCONSTD, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_DPR, MCK_FPImm }, },
10597 { 452 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_HPR, MCK_FPImm }, },
10598 { 460 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10599 { 468 /* fldmiax */, ARM::FLDMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
10600 { 468 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10601 { 476 /* fmdhr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
10602 { 482 /* fmdlr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
10603 { 488 /* fmstat */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode }, },
10604 { 495 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10605 { 503 /* fstmiax */, ARM::FSTMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
10606 { 503 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10607 { 511 /* fsubd */, ARM::VSUBD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
10608 { 517 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10609 { 523 /* hint */, ARM::tHINT, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode, MCK_Imm0_15 }, },
10610 { 523 /* hint */, ARM::HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_Imm0_239 }, },
10611 { 523 /* hint */, ARM::t2HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_239 }, },
10612 { 523 /* hint */, ARM::t2HINT, Convert__Imm0_2391_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_239 }, },
10613 { 528 /* hlt */, ARM::tHLT, Convert__Imm0_631_0, AMFBS_IsThumb_HasV8, { MCK_Imm0_63 }, },
10614 { 528 /* hlt */, ARM::HLT, Convert__Imm0_655351_0, AMFBS_IsARM_HasV8, { MCK_Imm0_65535 }, },
10615 { 532 /* hvc */, ARM::HVC, Convert__Imm0_655351_0, AMFBS_IsARM_HasVirtualization, { MCK_Imm0_65535 }, },
10616 { 532 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_0, AMFBS_IsThumb2, { MCK_Imm0_65535 }, },
10617 { 532 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_1, AMFBS_IsThumb2_HasVirtualization, { MCK__DOT_w, MCK_Imm0_65535 }, },
10618 { 536 /* isb */, ARM::ISB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
10619 { 536 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
10620 { 536 /* isb */, ARM::ISB, Convert__InstSyncBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_InstSyncBarrierOpt }, },
10621 { 536 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
10622 { 536 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_InstSyncBarrierOpt }, },
10623 { 536 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_InstSyncBarrierOpt }, },
10624 { 540 /* it */, ARM::t2IT, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsThumb2, { MCK_ITMask, MCK_ITCondCode }, },
10625 { 540 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsARM, { MCK_ITMask, MCK_ITCondCode }, },
10626 { 543 /* lctp */, ARM::MVE_LCTP, Convert__CondCode2_0, AMFBS_HasMVEInt, { MCK_CondCode }, },
10627 { 548 /* lda */, ARM::t2LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10628 { 548 /* lda */, ARM::LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10629 { 552 /* ldab */, ARM::t2LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10630 { 552 /* ldab */, ARM::LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10631 { 557 /* ldaex */, ARM::t2LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10632 { 557 /* ldaex */, ARM::LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10633 { 563 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10634 { 563 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10635 { 570 /* ldaexd */, ARM::LDAEXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
10636 { 570 /* ldaexd */, ARM::t2LDAEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
10637 { 577 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10638 { 577 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10639 { 584 /* ldah */, ARM::t2LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10640 { 584 /* ldah */, ARM::LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10641 { 589 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10642 { 589 /* ldc */, ARM::t2LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10643 { 589 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10644 { 589 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10645 { 589 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10646 { 589 /* ldc */, ARM::t2LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10647 { 589 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10648 { 589 /* ldc */, ARM::t2LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10649 { 593 /* ldc2 */, ARM::LDC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10650 { 593 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10651 { 593 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10652 { 593 /* ldc2 */, ARM::LDC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10653 { 593 /* ldc2 */, ARM::LDC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10654 { 593 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10655 { 593 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10656 { 593 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10657 { 598 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10658 { 598 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10659 { 598 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10660 { 598 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10661 { 598 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10662 { 598 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10663 { 598 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10664 { 598 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10665 { 604 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10666 { 604 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10667 { 604 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10668 { 604 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10669 { 604 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10670 { 604 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10671 { 604 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10672 { 604 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10673 { 609 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_RegList }, },
10674 { 609 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
10675 { 609 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10676 { 609 /* ldm */, ARM::t2LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10677 { 609 /* ldm */, ARM::t2LDMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
10678 { 609 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10679 { 609 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10680 { 609 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10681 { 609 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10682 { 609 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10683 { 613 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10684 { 613 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10685 { 613 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10686 { 613 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10687 { 619 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10688 { 619 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10689 { 619 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
10690 { 619 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10691 { 619 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10692 { 619 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10693 { 619 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10694 { 619 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10695 { 625 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10696 { 625 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10697 { 625 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10698 { 625 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10699 { 631 /* ldr */, ARM::tLDRpci, Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ThumbMemPC }, },
10700 { 631 /* ldr */, ARM::tLDRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
10701 { 631 /* ldr */, ARM::tLDRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10702 { 631 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
10703 { 631 /* ldr */, ARM::tLDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ConstPoolAsmImm }, },
10704 { 631 /* ldr */, ARM::t2LDRpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_Imm }, },
10705 { 631 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
10706 { 631 /* ldr */, ARM::t2LDRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
10707 { 631 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
10708 { 631 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
10709 { 631 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
10710 { 631 /* ldr */, ARM::t2LDRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
10711 { 631 /* ldr */, ARM::t2LDRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
10712 { 631 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemPCRelImm12 }, },
10713 { 631 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_ConstPoolAsmImm }, },
10714 { 631 /* ldr */, ARM::t2LDRpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_Imm }, },
10715 { 631 /* ldr */, ARM::t2LDRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
10716 { 631 /* ldr */, ARM::t2LDRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
10717 { 631 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemPCRelImm12 }, },
10718 { 631 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
10719 { 631 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10720 { 631 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10721 { 631 /* ldr */, ARM::t2LDR_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10722 { 631 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10723 { 631 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
10724 { 631 /* ldr */, ARM::t2LDR_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10725 { 631 /* ldr */, ARM::t2LDR_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10726 { 635 /* ldrb */, ARM::tLDRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
10727 { 635 /* ldrb */, ARM::tLDRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10728 { 635 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10729 { 635 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
10730 { 635 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
10731 { 635 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
10732 { 635 /* ldrb */, ARM::t2LDRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
10733 { 635 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
10734 { 635 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10735 { 635 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
10736 { 635 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
10737 { 635 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
10738 { 635 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10739 { 635 /* ldrb */, ARM::t2LDRB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
10740 { 635 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
10741 { 635 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10742 { 635 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10743 { 635 /* ldrb */, ARM::t2LDRB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10744 { 635 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10745 { 635 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
10746 { 635 /* ldrb */, ARM::t2LDRB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10747 { 635 /* ldrb */, ARM::t2LDRB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10748 { 640 /* ldrbt */, ARM::t2LDRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10749 { 640 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10750 { 640 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10751 { 640 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10752 { 646 /* ldrd */, ARM::t2LDRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
10753 { 646 /* ldrd */, ARM::LDRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
10754 { 646 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
10755 { 646 /* ldrd */, ARM::t2LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
10756 { 646 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10757 { 646 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10758 { 651 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
10759 { 651 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10760 { 657 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10761 { 657 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10762 { 664 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
10763 { 664 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
10764 { 671 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10765 { 671 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10766 { 678 /* ldrh */, ARM::tLDRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
10767 { 678 /* ldrh */, ARM::tLDRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10768 { 678 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10769 { 678 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
10770 { 678 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
10771 { 678 /* ldrh */, ARM::t2LDRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
10772 { 678 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10773 { 678 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10774 { 678 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
10775 { 678 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
10776 { 678 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
10777 { 678 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10778 { 678 /* ldrh */, ARM::t2LDRH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
10779 { 678 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10780 { 678 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10781 { 678 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10782 { 678 /* ldrh */, ARM::t2LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10783 { 678 /* ldrh */, ARM::t2LDRH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10784 { 678 /* ldrh */, ARM::t2LDRH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10785 { 683 /* ldrht */, ARM::t2LDRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10786 { 683 /* ldrht */, ARM::LDRHTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10787 { 683 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10788 { 683 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10789 { 689 /* ldrsb */, ARM::tLDRSB, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10790 { 689 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10791 { 689 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
10792 { 689 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
10793 { 689 /* ldrsb */, ARM::t2LDRSBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
10794 { 689 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10795 { 689 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10796 { 689 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
10797 { 689 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
10798 { 689 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
10799 { 689 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10800 { 689 /* ldrsb */, ARM::t2LDRSB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
10801 { 689 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10802 { 689 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10803 { 689 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10804 { 689 /* ldrsb */, ARM::t2LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10805 { 689 /* ldrsb */, ARM::t2LDRSB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10806 { 689 /* ldrsb */, ARM::t2LDRSB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10807 { 695 /* ldrsbt */, ARM::t2LDRSBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10808 { 695 /* ldrsbt */, ARM::LDRSBTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10809 { 695 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10810 { 695 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10811 { 702 /* ldrsh */, ARM::tLDRSH, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10812 { 702 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10813 { 702 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
10814 { 702 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
10815 { 702 /* ldrsh */, ARM::t2LDRSHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
10816 { 702 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10817 { 702 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10818 { 702 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
10819 { 702 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
10820 { 702 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
10821 { 702 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10822 { 702 /* ldrsh */, ARM::t2LDRSH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
10823 { 702 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10824 { 702 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10825 { 702 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10826 { 702 /* ldrsh */, ARM::t2LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10827 { 702 /* ldrsh */, ARM::t2LDRSH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10828 { 702 /* ldrsh */, ARM::t2LDRSH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10829 { 708 /* ldrsht */, ARM::t2LDRSHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10830 { 708 /* ldrsht */, ARM::LDRSHTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10831 { 708 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10832 { 708 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10833 { 715 /* ldrt */, ARM::t2LDRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10834 { 715 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10835 { 715 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10836 { 715 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10837 { 720 /* le */, ARM::t2LE, Convert__LELabel1_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_LELabel }, },
10838 { 720 /* le */, ARM::t2LEUpdate, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_LELabel }, },
10839 { 723 /* letp */, ARM::MVE_LETP, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_HasMVEInt, { MCK_GPRlr, MCK_LELabel }, },
10840 { 728 /* lsl */, ARM::tLSLrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10841 { 728 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, },
10842 { 728 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, },
10843 { 728 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10844 { 728 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, },
10845 { 728 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10846 { 728 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
10847 { 728 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10848 { 728 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, },
10849 { 728 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10850 { 728 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
10851 { 728 /* lsl */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, },
10852 { 728 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10853 { 728 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
10854 { 728 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10855 { 728 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
10856 { 728 /* lsl */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, },
10857 { 732 /* lsll */, ARM::MVE_LSLLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, },
10858 { 732 /* lsll */, ARM::MVE_LSLLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
10859 { 737 /* lsr */, ARM::tLSRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10860 { 737 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
10861 { 737 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
10862 { 737 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10863 { 737 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
10864 { 737 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10865 { 737 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
10866 { 737 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10867 { 737 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
10868 { 737 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10869 { 737 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
10870 { 737 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10871 { 737 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
10872 { 737 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10873 { 737 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
10874 { 741 /* lsrl */, ARM::MVE_LSRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
10875 { 746 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
10876 { 746 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
10877 { 746 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10878 { 746 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10879 { 750 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
10880 { 750 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
10881 { 750 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10882 { 750 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10883 { 755 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
10884 { 755 /* mcrr */, ARM::t2MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
10885 { 760 /* mcrr2 */, ARM::MCRR2, Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
10886 { 760 /* mcrr2 */, ARM::t2MCRR2, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
10887 { 766 /* mla */, ARM::t2MLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10888 { 766 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10889 { 766 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10890 { 770 /* mls */, ARM::t2MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10891 { 770 /* mls */, ARM::MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
10892 { 774 /* mov */, ARM::tMOVr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10893 { 774 /* mov */, ARM::tMOVi8, Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255Expr }, },
10894 { 774 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_PC, MCK_GPRlr }, },
10895 { 774 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, },
10896 { 774 /* mov */, ARM::t2MOVsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10897 { 774 /* mov */, ARM::t2MOVsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
10898 { 774 /* mov */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10899 { 774 /* mov */, ARM::t2MVNi, Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10900 { 774 /* mov */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
10901 { 774 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, },
10902 { 774 /* mov */, ARM::MVNi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
10903 { 774 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10904 { 774 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10905 { 774 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10906 { 774 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10907 { 774 /* mov */, ARM::t2MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10908 { 774 /* mov */, ARM::t2MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
10909 { 774 /* mov */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10910 { 774 /* mov */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
10911 { 774 /* mov */, ARM::t2MOVi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10912 { 774 /* mov */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
10913 { 778 /* movs */, ARM::tMOVSr, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb, { MCK_tGPR, MCK_tGPR }, },
10914 { 778 /* movs */, ARM::tMOVi8, Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0, AMFBS_IsThumb, { MCK_tGPR, MCK_Imm0_255Expr }, },
10915 { 778 /* movs */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_PC, MCK_GPRlr }, },
10916 { 778 /* movs */, ARM::t2MOVSsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10917 { 778 /* movs */, ARM::t2MOVSsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
10918 { 778 /* movs */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10919 { 778 /* movs */, ARM::t2MOVr, Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10920 { 778 /* movs */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_PC, MCK_GPRlr }, },
10921 { 778 /* movs */, ARM::t2MOVSsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10922 { 778 /* movs */, ARM::t2MOVSsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
10923 { 778 /* movs */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10924 { 778 /* movs */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
10925 { 783 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
10926 { 783 /* movt */, ARM::MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_65535Expr }, },
10927 { 788 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
10928 { 788 /* movw */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
10929 { 793 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
10930 { 793 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
10931 { 793 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10932 { 793 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10933 { 797 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
10934 { 797 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
10935 { 797 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10936 { 797 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10937 { 802 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
10938 { 802 /* mrrc */, ARM::t2MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
10939 { 807 /* mrrc2 */, ARM::MRRC2, Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
10940 { 807 /* mrrc2 */, ARM::t2MRRC2, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
10941 { 813 /* mrs */, ARM::t2MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_rGPR, MCK_BankedReg }, },
10942 { 813 /* mrs */, ARM::t2MRS_M, Convert__Reg1_1__MSRMask1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_rGPR, MCK_MSRMask }, },
10943 { 813 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, },
10944 { 813 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, },
10945 { 813 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, },
10946 { 813 /* mrs */, ARM::MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_GPRnopc, MCK_BankedReg }, },
10947 { 813 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, },
10948 { 813 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_CCR }, },
10949 { 813 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, },
10950 { 817 /* msr */, ARM::t2MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_rGPR }, },
10951 { 817 /* msr */, ARM::MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_GPRnopc }, },
10952 { 817 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
10953 { 817 /* msr */, ARM::t2MSR_M, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
10954 { 817 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, },
10955 { 817 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, },
10956 { 821 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10957 { 821 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
10958 { 821 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10959 { 821 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10960 { 821 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10961 { 821 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10962 { 821 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10963 { 825 /* mvn */, ARM::tMVN, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10964 { 825 /* mvn */, ARM::t2MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10965 { 825 /* mvn */, ARM::MOVi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
10966 { 825 /* mvn */, ARM::t2MVNs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10967 { 825 /* mvn */, ARM::t2MVNi, Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10968 { 825 /* mvn */, ARM::t2MOVi, Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10969 { 825 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10970 { 825 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10971 { 825 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10972 { 825 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10973 { 825 /* mvn */, ARM::t2MVNr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10974 { 825 /* mvn */, ARM::t2MVNs, Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10975 { 825 /* mvn */, ARM::t2MVNi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10976 { 829 /* neg */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10977 { 829 /* neg */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10978 { 829 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10979 { 833 /* nop */, ARM::tMOVr, Convert__regR8__regR8__imm_95_14__reg0, AMFBS_IsThumb, { }, },
10980 { 833 /* nop */, ARM::tHINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
10981 { 833 /* nop */, ARM::HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
10982 { 833 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, AMFBS_IsARM, { MCK_CondCode }, },
10983 { 833 /* nop */, ARM::t2HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
10984 { 837 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10985 { 837 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10986 { 837 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10987 { 837 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10988 { 837 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10989 { 837 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10990 { 837 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10991 { 837 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10992 { 837 /* orn */, ARM::t2ORNrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10993 { 837 /* orn */, ARM::t2ORNrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10994 { 837 /* orn */, ARM::t2ORNri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10995 { 841 /* orr */, ARM::tORR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10996 { 841 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10997 { 841 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10998 { 841 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10999 { 841 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11000 { 841 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11001 { 841 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11002 { 841 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11003 { 841 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11004 { 841 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11005 { 841 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11006 { 841 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11007 { 841 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11008 { 841 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11009 { 841 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11010 { 841 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
11011 { 841 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11012 { 841 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11013 { 841 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11014 { 841 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11015 { 841 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11016 { 841 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11017 { 841 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11018 { 845 /* pac */, ARM::t2PAC, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11019 { 845 /* pac */, ARM::t2HINT, Convert__imm_95_29__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11020 { 849 /* pacbti */, ARM::t2PACBTI, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11021 { 849 /* pacbti */, ARM::t2HINT, Convert__imm_95_13__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11022 { 856 /* pacg */, ARM::t2PACG, Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_GPRnopc }, },
11023 { 861 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11024 { 861 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11025 { 861 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHLSLImm }, },
11026 { 861 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHLSLImm }, },
11027 { 867 /* pkhtb */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11028 { 867 /* pkhtb */, ARM::PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11029 { 867 /* pkhtb */, ARM::t2PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHASRImm }, },
11030 { 867 /* pkhtb */, ARM::PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHASRImm }, },
11031 { 873 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, AMFBS_IsARM, { MCK_MemImm12Offset }, },
11032 { 873 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, AMFBS_IsARM, { MCK_MemRegOffset }, },
11033 { 873 /* pld */, ARM::t2PLDpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm }, },
11034 { 873 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11035 { 873 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemUImm12Offset }, },
11036 { 873 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_T2MemRegOffset }, },
11037 { 873 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemPCRelImm12 }, },
11038 { 873 /* pld */, ARM::t2PLDpci, Convert__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
11039 { 873 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11040 { 873 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11041 { 873 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11042 { 873 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemPCRelImm12 }, },
11043 { 877 /* pldw */, ARM::PLDWi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemImm12Offset }, },
11044 { 877 /* pldw */, ARM::PLDWrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemRegOffset }, },
11045 { 877 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11046 { 877 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemUImm12Offset }, },
11047 { 877 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_T2MemRegOffset }, },
11048 { 877 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11049 { 877 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11050 { 877 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11051 { 882 /* pli */, ARM::PLIi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7, { MCK_MemImm12Offset }, },
11052 { 882 /* pli */, ARM::PLIrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7, { MCK_MemRegOffset }, },
11053 { 882 /* pli */, ARM::t2PLIpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_Imm }, },
11054 { 882 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11055 { 882 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemUImm12Offset }, },
11056 { 882 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_T2MemRegOffset }, },
11057 { 882 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemPCRelImm12 }, },
11058 { 882 /* pli */, ARM::t2PLIpci, Convert__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
11059 { 882 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11060 { 882 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11061 { 882 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11062 { 882 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemPCRelImm12 }, },
11063 { 886 /* pop */, ARM::tPOP, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, },
11064 { 886 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, },
11065 { 886 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, },
11066 { 886 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
11067 { 890 /* pssbb */, ARM::t2DSB, Convert__imm_95_4__imm_95_14__reg0, AMFBS_HasDB_IsThumb2, { }, },
11068 { 890 /* pssbb */, ARM::DSB, Convert__imm_95_4, AMFBS_IsARM_HasDB, { }, },
11069 { 896 /* push */, ARM::tPUSH, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, },
11070 { 896 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, },
11071 { 896 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, },
11072 { 896 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
11073 { 901 /* qadd */, ARM::t2QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11074 { 901 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11075 { 906 /* qadd16 */, ARM::t2QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11076 { 906 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11077 { 913 /* qadd8 */, ARM::t2QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11078 { 913 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11079 { 919 /* qasx */, ARM::t2QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11080 { 919 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11081 { 924 /* qdadd */, ARM::t2QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11082 { 924 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11083 { 930 /* qdsub */, ARM::t2QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11084 { 930 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11085 { 936 /* qsax */, ARM::t2QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11086 { 936 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11087 { 941 /* qsub */, ARM::t2QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11088 { 941 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11089 { 946 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11090 { 946 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11091 { 953 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11092 { 953 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11093 { 959 /* rbit */, ARM::t2RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11094 { 959 /* rbit */, ARM::RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11095 { 964 /* rev */, ARM::tREV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11096 { 964 /* rev */, ARM::t2REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11097 { 964 /* rev */, ARM::REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11098 { 964 /* rev */, ARM::t2REV, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11099 { 968 /* rev16 */, ARM::tREV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11100 { 968 /* rev16 */, ARM::t2REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11101 { 968 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11102 { 968 /* rev16 */, ARM::t2REV16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11103 { 974 /* revsh */, ARM::tREVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11104 { 974 /* revsh */, ARM::t2REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11105 { 974 /* revsh */, ARM::REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11106 { 974 /* revsh */, ARM::t2REVSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11107 { 980 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11108 { 980 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11109 { 986 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11110 { 986 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11111 { 986 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
11112 { 986 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
11113 { 992 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11114 { 992 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11115 { 992 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
11116 { 992 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
11117 { 998 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11118 { 998 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11119 { 1004 /* ror */, ARM::tROR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11120 { 1004 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11121 { 1004 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, },
11122 { 1004 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11123 { 1004 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
11124 { 1004 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11125 { 1004 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, },
11126 { 1004 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11127 { 1004 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11128 { 1004 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11129 { 1004 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
11130 { 1004 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11131 { 1004 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11132 { 1008 /* rrx */, ARM::t2RRX, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11133 { 1008 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11134 { 1012 /* rsb */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK__HASH_0 }, },
11135 { 1012 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11136 { 1012 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11137 { 1012 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11138 { 1012 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11139 { 1012 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11140 { 1012 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11141 { 1012 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11142 { 1012 /* rsb */, ARM::t2RSBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11143 { 1012 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11144 { 1012 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11145 { 1012 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11146 { 1012 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11147 { 1012 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11148 { 1012 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11149 { 1012 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11150 { 1012 /* rsb */, ARM::t2RSBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11151 { 1012 /* rsb */, ARM::t2RSBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11152 { 1012 /* rsb */, ARM::t2RSBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11153 { 1016 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11154 { 1016 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11155 { 1016 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11156 { 1016 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11157 { 1016 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11158 { 1016 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11159 { 1016 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11160 { 1016 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11161 { 1020 /* sadd16 */, ARM::t2SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11162 { 1020 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11163 { 1027 /* sadd8 */, ARM::t2SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11164 { 1027 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11165 { 1033 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11166 { 1033 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11167 { 1038 /* sb */, ARM::SB, Convert_NoOperands, AMFBS_IsARM_HasSB, { }, },
11168 { 1038 /* sb */, ARM::t2SB, Convert_NoOperands, AMFBS_IsThumb2_HasSB, { }, },
11169 { 1041 /* sbc */, ARM::tSBC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11170 { 1041 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11171 { 1041 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11172 { 1041 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11173 { 1041 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11174 { 1041 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11175 { 1041 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11176 { 1041 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11177 { 1041 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
11178 { 1041 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11179 { 1041 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11180 { 1041 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11181 { 1041 /* sbc */, ARM::t2SBCri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11182 { 1041 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11183 { 1041 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11184 { 1041 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11185 { 1041 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
11186 { 1041 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
11187 { 1041 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11188 { 1041 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11189 { 1041 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
11190 { 1041 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11191 { 1041 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11192 { 1041 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11193 { 1045 /* sbfx */, ARM::t2SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
11194 { 1045 /* sbfx */, ARM::SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
11195 { 1050 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11196 { 1050 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11197 { 1050 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11198 { 1050 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11199 { 1055 /* sel */, ARM::SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11200 { 1055 /* sel */, ARM::t2SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11201 { 1059 /* setend */, ARM::tSETEND, Convert__SetEndImm1_0, AMFBS_IsThumb_IsNotMClass, { MCK_SetEndImm }, },
11202 { 1059 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, AMFBS_IsARM, { MCK_SetEndImm }, },
11203 { 1066 /* setpan */, ARM::t2SETPAN, Convert__Imm0_11_0, AMFBS_IsThumb2_HasV8_HasV8_1a, { MCK_Imm0_1 }, },
11204 { 1066 /* setpan */, ARM::SETPAN, Convert__Imm0_11_0, AMFBS_IsARM_HasV8_HasV8_1a, { MCK_Imm0_1 }, },
11205 { 1073 /* sev */, ARM::tHINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
11206 { 1073 /* sev */, ARM::HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
11207 { 1073 /* sev */, ARM::t2HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11208 { 1077 /* sevl */, ARM::tHINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
11209 { 1077 /* sevl */, ARM::HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, },
11210 { 1077 /* sevl */, ARM::t2HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode, MCK__DOT_w }, },
11211 { 1082 /* sg */, ARM::t2SG, Convert__CondCode2_0, AMFBS_Has8MSecExt, { MCK_CondCode }, },
11212 { 1085 /* sha1c */, ARM::SHA1C, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11213 { 1091 /* sha1h */, ARM::SHA1H, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11214 { 1097 /* sha1m */, ARM::SHA1M, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11215 { 1103 /* sha1p */, ARM::SHA1P, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11216 { 1109 /* sha1su0 */, ARM::SHA1SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11217 { 1117 /* sha1su1 */, ARM::SHA1SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11218 { 1125 /* sha256h */, ARM::SHA256H, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11219 { 1133 /* sha256h2 */, ARM::SHA256H2, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11220 { 1142 /* sha256su0 */, ARM::SHA256SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11221 { 1152 /* sha256su1 */, ARM::SHA256SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11222 { 1162 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11223 { 1162 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11224 { 1170 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11225 { 1170 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11226 { 1177 /* shasx */, ARM::t2SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11227 { 1177 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11228 { 1183 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11229 { 1183 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11230 { 1189 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11231 { 1189 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11232 { 1197 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11233 { 1197 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11234 { 1204 /* smc */, ARM::SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
11235 { 1204 /* smc */, ARM::t2SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
11236 { 1208 /* smlabb */, ARM::t2SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11237 { 1208 /* smlabb */, ARM::SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11238 { 1215 /* smlabt */, ARM::t2SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11239 { 1215 /* smlabt */, ARM::SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11240 { 1222 /* smlad */, ARM::t2SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11241 { 1222 /* smlad */, ARM::SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11242 { 1228 /* smladx */, ARM::t2SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11243 { 1228 /* smladx */, ARM::SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11244 { 1235 /* smlal */, ARM::t2SMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11245 { 1235 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11246 { 1235 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11247 { 1241 /* smlalbb */, ARM::t2SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11248 { 1241 /* smlalbb */, ARM::SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11249 { 1249 /* smlalbt */, ARM::t2SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11250 { 1249 /* smlalbt */, ARM::SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11251 { 1257 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11252 { 1257 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11253 { 1264 /* smlaldx */, ARM::t2SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11254 { 1264 /* smlaldx */, ARM::SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11255 { 1272 /* smlaltb */, ARM::t2SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11256 { 1272 /* smlaltb */, ARM::SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11257 { 1280 /* smlaltt */, ARM::t2SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11258 { 1280 /* smlaltt */, ARM::SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11259 { 1288 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11260 { 1288 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11261 { 1295 /* smlatt */, ARM::t2SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11262 { 1295 /* smlatt */, ARM::SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11263 { 1302 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11264 { 1302 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11265 { 1309 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11266 { 1309 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11267 { 1316 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11268 { 1316 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11269 { 1322 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11270 { 1322 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11271 { 1329 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11272 { 1329 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11273 { 1336 /* smlsldx */, ARM::t2SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11274 { 1336 /* smlsldx */, ARM::SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11275 { 1344 /* smmla */, ARM::t2SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11276 { 1344 /* smmla */, ARM::SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11277 { 1350 /* smmlar */, ARM::t2SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11278 { 1350 /* smmlar */, ARM::SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11279 { 1357 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11280 { 1357 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11281 { 1363 /* smmlsr */, ARM::t2SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11282 { 1363 /* smmlsr */, ARM::SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11283 { 1370 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11284 { 1370 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11285 { 1376 /* smmulr */, ARM::t2SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11286 { 1376 /* smmulr */, ARM::SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11287 { 1383 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11288 { 1383 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11289 { 1389 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11290 { 1389 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11291 { 1396 /* smulbb */, ARM::t2SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11292 { 1396 /* smulbb */, ARM::SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11293 { 1403 /* smulbt */, ARM::t2SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11294 { 1403 /* smulbt */, ARM::SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11295 { 1410 /* smull */, ARM::t2SMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11296 { 1410 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11297 { 1410 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11298 { 1416 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11299 { 1416 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11300 { 1423 /* smultt */, ARM::t2SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11301 { 1423 /* smultt */, ARM::SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11302 { 1430 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11303 { 1430 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11304 { 1437 /* smulwt */, ARM::t2SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11305 { 1437 /* smulwt */, ARM::SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11306 { 1444 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11307 { 1444 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11308 { 1450 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11309 { 1450 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11310 { 1457 /* sqrshr */, ARM::MVE_SQRSHR, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11311 { 1464 /* sqrshrl */, ARM::MVE_SQRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, },
11312 { 1472 /* sqshl */, ARM::MVE_SQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11313 { 1478 /* sqshll */, ARM::MVE_SQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11314 { 1485 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11315 { 1485 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11316 { 1485 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11317 { 1485 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11318 { 1491 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11319 { 1491 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11320 { 1491 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
11321 { 1491 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11322 { 1491 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11323 { 1491 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
11324 { 1491 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
11325 { 1491 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11326 { 1497 /* srshr */, ARM::MVE_SRSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11327 { 1503 /* srshrl */, ARM::MVE_SRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11328 { 1510 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11329 { 1510 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11330 { 1510 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
11331 { 1510 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11332 { 1510 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11333 { 1510 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
11334 { 1510 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
11335 { 1510 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11336 { 1516 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11337 { 1516 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11338 { 1516 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11339 { 1516 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11340 { 1522 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR }, },
11341 { 1522 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, },
11342 { 1522 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR, MCK_ShifterImm }, },
11343 { 1522 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc, MCK_ShifterImm }, },
11344 { 1527 /* ssat16 */, ARM::t2SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm1_16, MCK_rGPR }, },
11345 { 1527 /* ssat16 */, ARM::SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_16, MCK_GPRnopc }, },
11346 { 1534 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11347 { 1534 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11348 { 1539 /* ssbb */, ARM::t2DSB, Convert__imm_95_0__imm_95_14__reg0, AMFBS_HasDB_IsThumb2, { }, },
11349 { 1539 /* ssbb */, ARM::DSB, Convert__imm_95_0, AMFBS_IsARM_HasDB, { }, },
11350 { 1544 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11351 { 1544 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11352 { 1551 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11353 { 1551 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11354 { 1557 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11355 { 1557 /* stc */, ARM::t2STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11356 { 1557 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11357 { 1557 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11358 { 1557 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11359 { 1557 /* stc */, ARM::t2STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11360 { 1557 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11361 { 1557 /* stc */, ARM::t2STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11362 { 1561 /* stc2 */, ARM::STC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11363 { 1561 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11364 { 1561 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11365 { 1561 /* stc2 */, ARM::STC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11366 { 1561 /* stc2 */, ARM::STC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11367 { 1561 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11368 { 1561 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11369 { 1561 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11370 { 1566 /* stc2l */, ARM::STC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11371 { 1566 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11372 { 1566 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11373 { 1566 /* stc2l */, ARM::STC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11374 { 1566 /* stc2l */, ARM::STC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11375 { 1566 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11376 { 1566 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11377 { 1566 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11378 { 1572 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11379 { 1572 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11380 { 1572 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11381 { 1572 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11382 { 1572 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11383 { 1572 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11384 { 1572 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11385 { 1572 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11386 { 1577 /* stl */, ARM::t2STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11387 { 1577 /* stl */, ARM::STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11388 { 1581 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11389 { 1581 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11390 { 1586 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11391 { 1586 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11392 { 1592 /* stlexb */, ARM::t2STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11393 { 1592 /* stlexb */, ARM::STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11394 { 1599 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
11395 { 1599 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11396 { 1606 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11397 { 1606 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11398 { 1613 /* stlh */, ARM::t2STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11399 { 1613 /* stlh */, ARM::STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11400 { 1618 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
11401 { 1618 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11402 { 1618 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11403 { 1618 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11404 { 1618 /* stm */, ARM::t2STMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
11405 { 1618 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11406 { 1618 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11407 { 1618 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11408 { 1618 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11409 { 1618 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11410 { 1622 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11411 { 1622 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11412 { 1622 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11413 { 1622 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11414 { 1628 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11415 { 1628 /* stmdb */, ARM::t2STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11416 { 1628 /* stmdb */, ARM::t2STMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
11417 { 1628 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11418 { 1628 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11419 { 1628 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11420 { 1628 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11421 { 1628 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11422 { 1634 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11423 { 1634 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11424 { 1634 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11425 { 1634 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11426 { 1640 /* str */, ARM::tSTRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
11427 { 1640 /* str */, ARM::tSTRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11428 { 1640 /* str */, ARM::tSTRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
11429 { 1640 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
11430 { 1640 /* str */, ARM::t2STRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
11431 { 1640 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
11432 { 1640 /* str */, ARM::t2STRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
11433 { 1640 /* str */, ARM::t2STRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
11434 { 1640 /* str */, ARM::t2STRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
11435 { 1640 /* str */, ARM::t2STRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
11436 { 1640 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11437 { 1640 /* str */, ARM::t2STR_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_Imm }, },
11438 { 1640 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11439 { 1640 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11440 { 1640 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11441 { 1640 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11442 { 1640 /* str */, ARM::t2STR_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11443 { 1640 /* str */, ARM::t2STR_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11444 { 1644 /* strb */, ARM::tSTRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
11445 { 1644 /* strb */, ARM::tSTRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11446 { 1644 /* strb */, ARM::t2STRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
11447 { 1644 /* strb */, ARM::t2STRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11448 { 1644 /* strb */, ARM::t2STRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11449 { 1644 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
11450 { 1644 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
11451 { 1644 /* strb */, ARM::t2STRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
11452 { 1644 /* strb */, ARM::t2STRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
11453 { 1644 /* strb */, ARM::t2STRB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11454 { 1644 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11455 { 1644 /* strb */, ARM::t2STRB_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
11456 { 1644 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11457 { 1644 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11458 { 1644 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11459 { 1644 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11460 { 1644 /* strb */, ARM::t2STRB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11461 { 1644 /* strb */, ARM::t2STRB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11462 { 1649 /* strbt */, ARM::t2STRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11463 { 1649 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11464 { 1649 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11465 { 1649 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11466 { 1655 /* strd */, ARM::t2STRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
11467 { 1655 /* strd */, ARM::STRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
11468 { 1655 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
11469 { 1655 /* strd */, ARM::t2STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
11470 { 1655 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11471 { 1655 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11472 { 1660 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
11473 { 1660 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11474 { 1666 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11475 { 1666 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11476 { 1673 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
11477 { 1673 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11478 { 1680 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11479 { 1680 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11480 { 1687 /* strh */, ARM::tSTRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
11481 { 1687 /* strh */, ARM::tSTRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11482 { 1687 /* strh */, ARM::t2STRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
11483 { 1687 /* strh */, ARM::t2STRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11484 { 1687 /* strh */, ARM::t2STRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11485 { 1687 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
11486 { 1687 /* strh */, ARM::t2STRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
11487 { 1687 /* strh */, ARM::t2STRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
11488 { 1687 /* strh */, ARM::t2STRH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11489 { 1687 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11490 { 1687 /* strh */, ARM::t2STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
11491 { 1687 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11492 { 1687 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11493 { 1687 /* strh */, ARM::t2STRH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11494 { 1687 /* strh */, ARM::t2STRH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11495 { 1692 /* strht */, ARM::t2STRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11496 { 1692 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
11497 { 1692 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, },
11498 { 1698 /* strt */, ARM::t2STRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11499 { 1698 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11500 { 1698 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11501 { 1698 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11502 { 1703 /* sub */, ARM::tSUBspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
11503 { 1703 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11504 { 1703 /* sub */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
11505 { 1703 /* sub */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
11506 { 1703 /* sub */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
11507 { 1703 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
11508 { 1703 /* sub */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
11509 { 1703 /* sub */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
11510 { 1703 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
11511 { 1703 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
11512 { 1703 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, },
11513 { 1703 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11514 { 1703 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
11515 { 1703 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
11516 { 1703 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11517 { 1703 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11518 { 1703 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
11519 { 1703 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11520 { 1703 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11521 { 1703 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
11522 { 1703 /* sub */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
11523 { 1703 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
11524 { 1703 /* sub */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
11525 { 1703 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, },
11526 { 1703 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
11527 { 1703 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
11528 { 1703 /* sub */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
11529 { 1703 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
11530 { 1703 /* sub */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
11531 { 1703 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
11532 { 1703 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
11533 { 1703 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11534 { 1703 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11535 { 1703 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
11536 { 1703 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11537 { 1703 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11538 { 1703 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
11539 { 1703 /* sub */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
11540 { 1703 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
11541 { 1703 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
11542 { 1703 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
11543 { 1703 /* sub */, ARM::t2SUBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
11544 { 1707 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_GPRlr, MCK_Imm0_255 }, },
11545 { 1712 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
11546 { 1712 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
11547 { 1712 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
11548 { 1712 /* subw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
11549 { 1712 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
11550 { 1712 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
11551 { 1717 /* svc */, ARM::tSVC, Convert__Imm0_2551_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm0_255 }, },
11552 { 1717 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_Imm24bit }, },
11553 { 1721 /* swp */, ARM::SWP, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
11554 { 1725 /* swpb */, ARM::SWPB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
11555 { 1730 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11556 { 1730 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11557 { 1730 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11558 { 1730 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11559 { 1736 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11560 { 1736 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11561 { 1736 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11562 { 1736 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11563 { 1744 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11564 { 1744 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11565 { 1744 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11566 { 1744 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11567 { 1750 /* sxtb */, ARM::tSXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11568 { 1750 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11569 { 1750 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11570 { 1750 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11571 { 1750 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11572 { 1750 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11573 { 1750 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11574 { 1755 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11575 { 1755 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11576 { 1755 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11577 { 1755 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11578 { 1755 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11579 { 1762 /* sxth */, ARM::tSXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11580 { 1762 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11581 { 1762 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11582 { 1762 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11583 { 1762 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11584 { 1762 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11585 { 1762 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11586 { 1767 /* tbb */, ARM::t2TBB, Convert__MemTBB2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBB }, },
11587 { 1771 /* tbh */, ARM::t2TBH, Convert__MemTBH2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBH }, },
11588 { 1775 /* teq */, ARM::t2TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11589 { 1775 /* teq */, ARM::t2TEQrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11590 { 1775 /* teq */, ARM::t2TEQri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11591 { 1775 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11592 { 1775 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11593 { 1775 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11594 { 1775 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11595 { 1775 /* teq */, ARM::t2TEQrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11596 { 1775 /* teq */, ARM::t2TEQrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11597 { 1775 /* teq */, ARM::t2TEQri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11598 { 1779 /* trap */, ARM::tTRAP, Convert_NoOperands, AMFBS_IsThumb, { }, },
11599 { 1779 /* trap */, ARM::TRAPNaCl, Convert_NoOperands, AMFBS_IsARM_UseNaClTrap, { }, },
11600 { 1779 /* trap */, ARM::TRAP, Convert_NoOperands, AMFBS_IsARM, { }, },
11601 { 1784 /* tsb */, ARM::TSB, Convert__TraceSyncBarrierOpt1_0, AMFBS_IsARM_HasV8_4a, { MCK_TraceSyncBarrierOpt }, },
11602 { 1784 /* tsb */, ARM::t2TSB, Convert__TraceSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasV8_4a, { MCK_CondCode, MCK_TraceSyncBarrierOpt }, },
11603 { 1788 /* tst */, ARM::tTST, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11604 { 1788 /* tst */, ARM::t2TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11605 { 1788 /* tst */, ARM::t2TSTrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11606 { 1788 /* tst */, ARM::t2TSTri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11607 { 1788 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11608 { 1788 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11609 { 1788 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11610 { 1788 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11611 { 1788 /* tst */, ARM::t2TSTrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11612 { 1788 /* tst */, ARM::t2TSTrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11613 { 1788 /* tst */, ARM::t2TSTri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11614 { 1792 /* tt */, ARM::t2TT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
11615 { 1795 /* tta */, ARM::t2TTA, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
11616 { 1799 /* ttat */, ARM::t2TTAT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
11617 { 1804 /* ttt */, ARM::t2TTT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
11618 { 1808 /* uadd16 */, ARM::t2UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11619 { 1808 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11620 { 1815 /* uadd8 */, ARM::t2UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11621 { 1815 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11622 { 1821 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11623 { 1821 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11624 { 1826 /* ubfx */, ARM::t2UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
11625 { 1826 /* ubfx */, ARM::UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
11626 { 1831 /* udf */, ARM::tUDF, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, },
11627 { 1831 /* udf */, ARM::UDF, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, },
11628 { 1831 /* udf */, ARM::t2UDF, Convert__Imm0_655351_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_65535 }, },
11629 { 1835 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11630 { 1835 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11631 { 1835 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11632 { 1835 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11633 { 1840 /* uhadd16 */, ARM::t2UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11634 { 1840 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11635 { 1848 /* uhadd8 */, ARM::t2UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11636 { 1848 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11637 { 1855 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11638 { 1855 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11639 { 1861 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11640 { 1861 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11641 { 1867 /* uhsub16 */, ARM::t2UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11642 { 1867 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11643 { 1875 /* uhsub8 */, ARM::t2UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11644 { 1875 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11645 { 1882 /* umaal */, ARM::t2UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11646 { 1882 /* umaal */, ARM::UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11647 { 1888 /* umlal */, ARM::t2UMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11648 { 1888 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11649 { 1888 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11650 { 1894 /* umull */, ARM::t2UMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11651 { 1894 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11652 { 1894 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11653 { 1900 /* uqadd16 */, ARM::t2UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11654 { 1900 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11655 { 1908 /* uqadd8 */, ARM::t2UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11656 { 1908 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11657 { 1915 /* uqasx */, ARM::t2UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11658 { 1915 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11659 { 1921 /* uqrshl */, ARM::MVE_UQRSHL, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11660 { 1928 /* uqrshll */, ARM::MVE_UQRSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, },
11661 { 1936 /* uqsax */, ARM::t2UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11662 { 1936 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11663 { 1942 /* uqshl */, ARM::MVE_UQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11664 { 1948 /* uqshll */, ARM::MVE_UQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11665 { 1955 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11666 { 1955 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11667 { 1963 /* uqsub8 */, ARM::t2UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11668 { 1963 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11669 { 1970 /* urshr */, ARM::MVE_URSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11670 { 1976 /* urshrl */, ARM::MVE_URSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11671 { 1983 /* usad8 */, ARM::t2USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11672 { 1983 /* usad8 */, ARM::USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11673 { 1989 /* usada8 */, ARM::t2USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11674 { 1989 /* usada8 */, ARM::USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11675 { 1996 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR }, },
11676 { 1996 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, },
11677 { 1996 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR, MCK_ShifterImm }, },
11678 { 1996 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc, MCK_ShifterImm }, },
11679 { 2001 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm0_15, MCK_rGPR }, },
11680 { 2001 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_15, MCK_GPRnopc }, },
11681 { 2008 /* usax */, ARM::t2USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11682 { 2008 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11683 { 2013 /* usub16 */, ARM::t2USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11684 { 2013 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11685 { 2020 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11686 { 2020 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11687 { 2026 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11688 { 2026 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11689 { 2026 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11690 { 2026 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11691 { 2032 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11692 { 2032 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11693 { 2032 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11694 { 2032 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11695 { 2040 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11696 { 2040 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11697 { 2040 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11698 { 2040 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11699 { 2046 /* uxtb */, ARM::tUXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11700 { 2046 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11701 { 2046 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11702 { 2046 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11703 { 2046 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11704 { 2046 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11705 { 2046 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11706 { 2051 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11707 { 2051 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11708 { 2051 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11709 { 2051 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11710 { 2051 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11711 { 2058 /* uxth */, ARM::tUXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11712 { 2058 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11713 { 2058 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11714 { 2058 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11715 { 2058 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11716 { 2058 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11717 { 2058 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11718 { 2063 /* vaba */, ARM::VABAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11719 { 2063 /* vaba */, ARM::VABAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11720 { 2063 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11721 { 2063 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11722 { 2063 /* vaba */, ARM::VABAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11723 { 2063 /* vaba */, ARM::VABAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11724 { 2063 /* vaba */, ARM::VABAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11725 { 2063 /* vaba */, ARM::VABAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11726 { 2063 /* vaba */, ARM::VABAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11727 { 2063 /* vaba */, ARM::VABAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11728 { 2063 /* vaba */, ARM::VABAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11729 { 2063 /* vaba */, ARM::VABAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11730 { 2068 /* vabal */, ARM::VABALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11731 { 2068 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11732 { 2068 /* vabal */, ARM::VABALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11733 { 2068 /* vabal */, ARM::VABALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11734 { 2068 /* vabal */, ARM::VABALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11735 { 2068 /* vabal */, ARM::VABALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11736 { 2074 /* vabav */, ARM::MVE_VABAVs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11737 { 2074 /* vabav */, ARM::MVE_VABAVs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11738 { 2074 /* vabav */, ARM::MVE_VABAVs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11739 { 2074 /* vabav */, ARM::MVE_VABAVu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11740 { 2074 /* vabav */, ARM::MVE_VABAVu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11741 { 2074 /* vabav */, ARM::MVE_VABAVu8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11742 { 2080 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
11743 { 2080 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
11744 { 2080 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11745 { 2080 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11746 { 2080 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
11747 { 2080 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
11748 { 2080 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
11749 { 2080 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
11750 { 2080 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
11751 { 2080 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
11752 { 2080 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
11753 { 2080 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
11754 { 2080 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11755 { 2080 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11756 { 2080 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11757 { 2080 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11758 { 2080 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11759 { 2080 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11760 { 2080 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11761 { 2080 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11762 { 2080 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11763 { 2080 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11764 { 2080 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11765 { 2080 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11766 { 2080 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11767 { 2080 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11768 { 2080 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11769 { 2080 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11770 { 2080 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11771 { 2080 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11772 { 2080 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11773 { 2080 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11774 { 2080 /* vabd */, ARM::MVE_VABDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11775 { 2080 /* vabd */, ARM::MVE_VABDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11776 { 2080 /* vabd */, ARM::MVE_VABDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11777 { 2080 /* vabd */, ARM::MVE_VABDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11778 { 2080 /* vabd */, ARM::MVE_VABDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11779 { 2080 /* vabd */, ARM::MVE_VABDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11780 { 2080 /* vabd */, ARM::MVE_VABDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11781 { 2080 /* vabd */, ARM::MVE_VABDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11782 { 2085 /* vabdl */, ARM::VABDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11783 { 2085 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11784 { 2085 /* vabdl */, ARM::VABDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11785 { 2085 /* vabdl */, ARM::VABDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11786 { 2085 /* vabdl */, ARM::VABDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11787 { 2085 /* vabdl */, ARM::VABDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11788 { 2091 /* vabs */, ARM::VABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
11789 { 2091 /* vabs */, ARM::VABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
11790 { 2091 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11791 { 2091 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11792 { 2091 /* vabs */, ARM::VABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
11793 { 2091 /* vabs */, ARM::VABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
11794 { 2091 /* vabs */, ARM::VABSfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11795 { 2091 /* vabs */, ARM::VABSfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11796 { 2091 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11797 { 2091 /* vabs */, ARM::VABSD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11798 { 2091 /* vabs */, ARM::VABShq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11799 { 2091 /* vabs */, ARM::VABShd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11800 { 2091 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11801 { 2091 /* vabs */, ARM::MVE_VABSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
11802 { 2091 /* vabs */, ARM::MVE_VABSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
11803 { 2091 /* vabs */, ARM::MVE_VABSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
11804 { 2091 /* vabs */, ARM::MVE_VABSf32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
11805 { 2091 /* vabs */, ARM::MVE_VABSf16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
11806 { 2096 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11807 { 2096 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11808 { 2096 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11809 { 2096 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11810 { 2096 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11811 { 2096 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11812 { 2096 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11813 { 2096 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11814 { 2102 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11815 { 2102 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11816 { 2102 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11817 { 2102 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11818 { 2102 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11819 { 2102 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11820 { 2102 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11821 { 2102 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11822 { 2108 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11823 { 2108 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11824 { 2108 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11825 { 2108 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11826 { 2108 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11827 { 2108 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11828 { 2108 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11829 { 2108 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11830 { 2114 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11831 { 2114 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11832 { 2114 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11833 { 2114 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11834 { 2114 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11835 { 2114 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11836 { 2114 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11837 { 2114 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11838 { 2120 /* vadc */, ARM::MVE_VADC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11839 { 2125 /* vadci */, ARM::MVE_VADCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11840 { 2131 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11841 { 2131 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11842 { 2131 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11843 { 2131 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11844 { 2131 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
11845 { 2131 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
11846 { 2131 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
11847 { 2131 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
11848 { 2131 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
11849 { 2131 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
11850 { 2131 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
11851 { 2131 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
11852 { 2131 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11853 { 2131 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11854 { 2131 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11855 { 2131 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11856 { 2131 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11857 { 2131 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11858 { 2131 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11859 { 2131 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11860 { 2131 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11861 { 2131 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11862 { 2131 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11863 { 2131 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11864 { 2131 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11865 { 2131 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11866 { 2131 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11867 { 2131 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11868 { 2131 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11869 { 2131 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
11870 { 2131 /* vadd */, ARM::MVE_VADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11871 { 2131 /* vadd */, ARM::MVE_VADD_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11872 { 2131 /* vadd */, ARM::MVE_VADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11873 { 2131 /* vadd */, ARM::MVE_VADD_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11874 { 2131 /* vadd */, ARM::MVE_VADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11875 { 2131 /* vadd */, ARM::MVE_VADD_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11876 { 2131 /* vadd */, ARM::MVE_VADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11877 { 2131 /* vadd */, ARM::MVE_VADD_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11878 { 2131 /* vadd */, ARM::MVE_VADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11879 { 2131 /* vadd */, ARM::MVE_VADD_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11880 { 2136 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
11881 { 2136 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
11882 { 2136 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
11883 { 2143 /* vaddl */, ARM::VADDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11884 { 2143 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11885 { 2143 /* vaddl */, ARM::VADDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11886 { 2143 /* vaddl */, ARM::VADDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11887 { 2143 /* vaddl */, ARM::VADDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11888 { 2143 /* vaddl */, ARM::VADDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11889 { 2149 /* vaddlv */, ARM::MVE_VADDLVs32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
11890 { 2149 /* vaddlv */, ARM::MVE_VADDLVu32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
11891 { 2156 /* vaddlva */, ARM::MVE_VADDLVs32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
11892 { 2156 /* vaddlva */, ARM::MVE_VADDLVu32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
11893 { 2164 /* vaddv */, ARM::MVE_VADDVs16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, },
11894 { 2164 /* vaddv */, ARM::MVE_VADDVs32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, },
11895 { 2164 /* vaddv */, ARM::MVE_VADDVs8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, },
11896 { 2164 /* vaddv */, ARM::MVE_VADDVu16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, },
11897 { 2164 /* vaddv */, ARM::MVE_VADDVu32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, },
11898 { 2164 /* vaddv */, ARM::MVE_VADDVu8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, },
11899 { 2170 /* vaddva */, ARM::MVE_VADDVs16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, },
11900 { 2170 /* vaddva */, ARM::MVE_VADDVs32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, },
11901 { 2170 /* vaddva */, ARM::MVE_VADDVs8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, },
11902 { 2170 /* vaddva */, ARM::MVE_VADDVu16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, },
11903 { 2170 /* vaddva */, ARM::MVE_VADDVu32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, },
11904 { 2170 /* vaddva */, ARM::MVE_VADDVu8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, },
11905 { 2177 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
11906 { 2177 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
11907 { 2177 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
11908 { 2177 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
11909 { 2177 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
11910 { 2177 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
11911 { 2177 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
11912 { 2177 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
11913 { 2177 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
11914 { 2177 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
11915 { 2177 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
11916 { 2177 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
11917 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
11918 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
11919 { 2183 /* vand */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splatNot }, },
11920 { 2183 /* vand */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splatNot }, },
11921 { 2183 /* vand */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splatNot }, },
11922 { 2183 /* vand */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splatNot }, },
11923 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
11924 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
11925 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11926 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
11927 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
11928 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
11929 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
11930 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
11931 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
11932 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
11933 { 2183 /* vand */, ARM::MVE_VBICimmi16, Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splatNot }, },
11934 { 2183 /* vand */, ARM::MVE_VBICimmi32, Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splatNot }, },
11935 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11936 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11937 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11938 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11939 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11940 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11941 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11942 { 2183 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11943 { 2183 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11944 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11945 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11946 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11947 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11948 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11949 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11950 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11951 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11952 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11953 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11954 { 2183 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11955 { 2188 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
11956 { 2188 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
11957 { 2188 /* vbic */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
11958 { 2188 /* vbic */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
11959 { 2188 /* vbic */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, },
11960 { 2188 /* vbic */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, },
11961 { 2188 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
11962 { 2188 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
11963 { 2188 /* vbic */, ARM::MVE_VBICimmi16, Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
11964 { 2188 /* vbic */, ARM::MVE_VBICimmi32, Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splat }, },
11965 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11966 { 2188 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11967 { 2188 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11968 { 2188 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11969 { 2188 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11970 { 2188 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11971 { 2188 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11972 { 2188 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11973 { 2188 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11974 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11975 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11976 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11977 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11978 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11979 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11980 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11981 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11982 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11983 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11984 { 2188 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11985 { 2193 /* vbif */, ARM::VBIFq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
11986 { 2193 /* vbif */, ARM::VBIFd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
11987 { 2193 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11988 { 2193 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11989 { 2193 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11990 { 2193 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11991 { 2193 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11992 { 2193 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11993 { 2193 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11994 { 2193 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11995 { 2198 /* vbit */, ARM::VBITq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
11996 { 2198 /* vbit */, ARM::VBITd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
11997 { 2198 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11998 { 2198 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11999 { 2198 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12000 { 2198 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12001 { 2198 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12002 { 2198 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12003 { 2198 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12004 { 2198 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12005 { 2203 /* vbrsr */, ARM::MVE_VBRSR16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12006 { 2203 /* vbrsr */, ARM::MVE_VBRSR32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12007 { 2203 /* vbrsr */, ARM::MVE_VBRSR8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12008 { 2209 /* vbsl */, ARM::VBSLq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12009 { 2209 /* vbsl */, ARM::VBSLd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12010 { 2209 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12011 { 2209 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12012 { 2209 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12013 { 2209 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12014 { 2209 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12015 { 2209 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12016 { 2209 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12017 { 2209 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12018 { 2214 /* vcadd */, ARM::VCADDv4f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, },
12019 { 2214 /* vcadd */, ARM::VCADDv2f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, },
12020 { 2214 /* vcadd */, ARM::VCADDv8f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, },
12021 { 2214 /* vcadd */, ARM::VCADDv4f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, },
12022 { 2214 /* vcadd */, ARM::MVE_VCADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12023 { 2214 /* vcadd */, ARM::MVE_VCADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12024 { 2214 /* vcadd */, ARM::MVE_VCADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12025 { 2214 /* vcadd */, ARM::MVE_VCADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12026 { 2214 /* vcadd */, ARM::MVE_VCADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12027 { 2220 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12028 { 2220 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12029 { 2220 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12030 { 2220 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12031 { 2220 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK__HASH_0 }, },
12032 { 2220 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
12033 { 2220 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK__HASH_0 }, },
12034 { 2220 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
12035 { 2220 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK__HASH_0 }, },
12036 { 2220 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
12037 { 2220 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK__HASH_0 }, },
12038 { 2220 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
12039 { 2220 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK__HASH_0 }, },
12040 { 2220 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
12041 { 2220 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK__HASH_0 }, },
12042 { 2220 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
12043 { 2220 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12044 { 2220 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12045 { 2220 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12046 { 2220 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12047 { 2220 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12048 { 2220 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12049 { 2220 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12050 { 2220 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12051 { 2220 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12052 { 2220 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12053 { 2220 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12054 { 2220 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12055 { 2220 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12056 { 2220 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12057 { 2220 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12058 { 2220 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12059 { 2220 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12060 { 2220 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12061 { 2220 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12062 { 2220 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12063 { 2220 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12064 { 2220 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12065 { 2220 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12066 { 2220 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12067 { 2225 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12068 { 2225 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12069 { 2225 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12070 { 2225 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12071 { 2225 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12072 { 2225 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12073 { 2225 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12074 { 2225 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12075 { 2225 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12076 { 2225 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12077 { 2225 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12078 { 2225 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12079 { 2225 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12080 { 2225 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12081 { 2225 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12082 { 2225 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12083 { 2225 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12084 { 2225 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12085 { 2225 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12086 { 2225 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12087 { 2225 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12088 { 2225 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12089 { 2225 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12090 { 2225 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12091 { 2225 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12092 { 2225 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12093 { 2225 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12094 { 2225 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12095 { 2225 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12096 { 2225 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12097 { 2225 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12098 { 2225 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12099 { 2225 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12100 { 2225 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12101 { 2225 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12102 { 2225 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12103 { 2225 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12104 { 2225 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12105 { 2225 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12106 { 2225 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12107 { 2225 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12108 { 2225 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12109 { 2225 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12110 { 2225 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12111 { 2225 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12112 { 2225 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12113 { 2225 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12114 { 2225 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12115 { 2225 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12116 { 2225 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12117 { 2225 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12118 { 2225 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12119 { 2230 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12120 { 2230 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12121 { 2230 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12122 { 2230 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12123 { 2230 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12124 { 2230 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12125 { 2230 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12126 { 2230 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12127 { 2230 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12128 { 2230 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12129 { 2230 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12130 { 2230 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12131 { 2230 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12132 { 2230 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12133 { 2230 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12134 { 2230 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12135 { 2230 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12136 { 2230 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12137 { 2230 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12138 { 2230 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12139 { 2230 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12140 { 2230 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12141 { 2230 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12142 { 2230 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12143 { 2230 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12144 { 2230 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12145 { 2230 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12146 { 2230 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12147 { 2230 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12148 { 2230 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12149 { 2230 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12150 { 2230 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12151 { 2230 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12152 { 2230 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12153 { 2230 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12154 { 2230 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12155 { 2230 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12156 { 2230 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12157 { 2230 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12158 { 2230 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12159 { 2230 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12160 { 2230 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12161 { 2230 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12162 { 2230 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12163 { 2230 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12164 { 2230 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12165 { 2230 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12166 { 2230 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12167 { 2230 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12168 { 2230 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12169 { 2230 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12170 { 2230 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12171 { 2235 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12172 { 2235 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12173 { 2235 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12174 { 2235 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12175 { 2235 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12176 { 2235 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12177 { 2235 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12178 { 2235 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12179 { 2235 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12180 { 2235 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12181 { 2235 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12182 { 2235 /* vcle */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12183 { 2235 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12184 { 2235 /* vcle */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12185 { 2235 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12186 { 2235 /* vcle */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12187 { 2235 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12188 { 2235 /* vcle */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12189 { 2235 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12190 { 2235 /* vcle */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12191 { 2235 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12192 { 2235 /* vcle */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12193 { 2235 /* vcle */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12194 { 2235 /* vcle */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12195 { 2235 /* vcle */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12196 { 2235 /* vcle */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12197 { 2235 /* vcle */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12198 { 2235 /* vcle */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12199 { 2235 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12200 { 2235 /* vcle */, ARM::VCGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12201 { 2235 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12202 { 2235 /* vcle */, ARM::VCGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12203 { 2235 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12204 { 2235 /* vcle */, ARM::VCGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12205 { 2235 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12206 { 2235 /* vcle */, ARM::VCGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12207 { 2240 /* vcls */, ARM::VCLSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12208 { 2240 /* vcls */, ARM::VCLSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12209 { 2240 /* vcls */, ARM::VCLSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12210 { 2240 /* vcls */, ARM::VCLSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12211 { 2240 /* vcls */, ARM::VCLSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12212 { 2240 /* vcls */, ARM::VCLSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12213 { 2240 /* vcls */, ARM::MVE_VCLSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12214 { 2240 /* vcls */, ARM::MVE_VCLSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12215 { 2240 /* vcls */, ARM::MVE_VCLSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
12216 { 2245 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12217 { 2245 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12218 { 2245 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12219 { 2245 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12220 { 2245 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12221 { 2245 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12222 { 2245 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12223 { 2245 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12224 { 2245 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12225 { 2245 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12226 { 2245 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12227 { 2245 /* vclt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12228 { 2245 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12229 { 2245 /* vclt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12230 { 2245 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12231 { 2245 /* vclt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12232 { 2245 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12233 { 2245 /* vclt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12234 { 2245 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12235 { 2245 /* vclt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12236 { 2245 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12237 { 2245 /* vclt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12238 { 2245 /* vclt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12239 { 2245 /* vclt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12240 { 2245 /* vclt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12241 { 2245 /* vclt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12242 { 2245 /* vclt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12243 { 2245 /* vclt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12244 { 2245 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12245 { 2245 /* vclt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12246 { 2245 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12247 { 2245 /* vclt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12248 { 2245 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12249 { 2245 /* vclt */, ARM::VCGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12250 { 2245 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12251 { 2245 /* vclt */, ARM::VCGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12252 { 2250 /* vclz */, ARM::VCLZv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
12253 { 2250 /* vclz */, ARM::VCLZv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
12254 { 2250 /* vclz */, ARM::VCLZv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
12255 { 2250 /* vclz */, ARM::VCLZv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
12256 { 2250 /* vclz */, ARM::VCLZv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
12257 { 2250 /* vclz */, ARM::VCLZv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
12258 { 2250 /* vclz */, ARM::MVE_VCLZs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
12259 { 2250 /* vclz */, ARM::MVE_VCLZs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
12260 { 2250 /* vclz */, ARM::MVE_VCLZs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR }, },
12261 { 2255 /* vcmla */, ARM::VCMLAv4f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, },
12262 { 2255 /* vcmla */, ARM::VCMLAv2f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, },
12263 { 2255 /* vcmla */, ARM::VCMLAv8f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, },
12264 { 2255 /* vcmla */, ARM::VCMLAv4f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, },
12265 { 2255 /* vcmla */, ARM::VCMLAv4f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, },
12266 { 2255 /* vcmla */, ARM::VCMLAv2f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, },
12267 { 2255 /* vcmla */, ARM::VCMLAv8f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, },
12268 { 2255 /* vcmla */, ARM::VCMLAv4f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, },
12269 { 2255 /* vcmla */, ARM::MVE_VCMLAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12270 { 2255 /* vcmla */, ARM::MVE_VCMLAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12271 { 2261 /* vcmp */, ARM::VCMPZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, },
12272 { 2261 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12273 { 2261 /* vcmp */, ARM::VCMPZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, },
12274 { 2261 /* vcmp */, ARM::VCMPD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12275 { 2261 /* vcmp */, ARM::VCMPZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, },
12276 { 2261 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12277 { 2261 /* vcmp */, ARM::MVE_VCMPs16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12278 { 2261 /* vcmp */, ARM::MVE_VCMPs16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12279 { 2261 /* vcmp */, ARM::MVE_VCMPs32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12280 { 2261 /* vcmp */, ARM::MVE_VCMPs32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12281 { 2261 /* vcmp */, ARM::MVE_VCMPs8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12282 { 2261 /* vcmp */, ARM::MVE_VCMPs8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12283 { 2261 /* vcmp */, ARM::MVE_VCMPu16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12284 { 2261 /* vcmp */, ARM::MVE_VCMPu16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12285 { 2261 /* vcmp */, ARM::MVE_VCMPu32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12286 { 2261 /* vcmp */, ARM::MVE_VCMPu32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12287 { 2261 /* vcmp */, ARM::MVE_VCMPu8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12288 { 2261 /* vcmp */, ARM::MVE_VCMPu8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12289 { 2261 /* vcmp */, ARM::MVE_VCMPf32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
12290 { 2261 /* vcmp */, ARM::MVE_VCMPf32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
12291 { 2261 /* vcmp */, ARM::MVE_VCMPi16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12292 { 2261 /* vcmp */, ARM::MVE_VCMPi16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12293 { 2261 /* vcmp */, ARM::MVE_VCMPi32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12294 { 2261 /* vcmp */, ARM::MVE_VCMPi32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12295 { 2261 /* vcmp */, ARM::MVE_VCMPi8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12296 { 2261 /* vcmp */, ARM::MVE_VCMPi8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12297 { 2261 /* vcmp */, ARM::MVE_VCMPf16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
12298 { 2261 /* vcmp */, ARM::MVE_VCMPf16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
12299 { 2266 /* vcmpe */, ARM::VCMPEZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, },
12300 { 2266 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12301 { 2266 /* vcmpe */, ARM::VCMPEZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, },
12302 { 2266 /* vcmpe */, ARM::VCMPED, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12303 { 2266 /* vcmpe */, ARM::VCMPEZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, },
12304 { 2266 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12305 { 2272 /* vcmul */, ARM::MVE_VCMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12306 { 2272 /* vcmul */, ARM::MVE_VCMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12307 { 2278 /* vcnt */, ARM::VCNTq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
12308 { 2278 /* vcnt */, ARM::VCNTd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
12309 { 2283 /* vctp */, ARM::MVE_VCTP16, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_rGPR }, },
12310 { 2283 /* vctp */, ARM::MVE_VCTP32, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_rGPR }, },
12311 { 2283 /* vctp */, ARM::MVE_VCTP64, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_rGPR }, },
12312 { 2283 /* vctp */, ARM::MVE_VCTP8, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_rGPR }, },
12313 { 2288 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12314 { 2288 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12315 { 2288 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12316 { 2288 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12317 { 2288 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12318 { 2288 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12319 { 2288 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12320 { 2288 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12321 { 2288 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12322 { 2288 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12323 { 2288 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12324 { 2288 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12325 { 2288 /* vcvt */, ARM::VTOUIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12326 { 2288 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12327 { 2288 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12328 { 2288 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12329 { 2288 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12330 { 2288 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12331 { 2288 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12332 { 2288 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12333 { 2288 /* vcvt */, ARM::VCVTSD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12334 { 2288 /* vcvt */, ARM::VCVTh2f, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_QPR, MCK_DPR }, },
12335 { 2288 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, },
12336 { 2288 /* vcvt */, ARM::VUITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_HPR }, },
12337 { 2288 /* vcvt */, ARM::VCVTDS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f32, MCK_DPR, MCK_HPR }, },
12338 { 2288 /* vcvt */, ARM::BF16_VCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasBF16_HasNEON, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, },
12339 { 2288 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12340 { 2288 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12341 { 2288 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12342 { 2288 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12343 { 2288 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12344 { 2288 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12345 { 2288 /* vcvt */, ARM::VCVTf2h, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, },
12346 { 2288 /* vcvt */, ARM::MVE_VCVTs16f16z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12347 { 2288 /* vcvt */, ARM::MVE_VCVTs32f32z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12348 { 2288 /* vcvt */, ARM::MVE_VCVTu16f16z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12349 { 2288 /* vcvt */, ARM::MVE_VCVTu32f32z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12350 { 2288 /* vcvt */, ARM::MVE_VCVTf32s32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12351 { 2288 /* vcvt */, ARM::MVE_VCVTf32u32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
12352 { 2288 /* vcvt */, ARM::MVE_VCVTf16s16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12353 { 2288 /* vcvt */, ARM::MVE_VCVTf16u16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
12354 { 2288 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12355 { 2288 /* vcvt */, ARM::VTOSHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12356 { 2288 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12357 { 2288 /* vcvt */, ARM::VCVTh2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12358 { 2288 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12359 { 2288 /* vcvt */, ARM::VCVTh2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12360 { 2288 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12361 { 2288 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12362 { 2288 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12363 { 2288 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12364 { 2288 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12365 { 2288 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12366 { 2288 /* vcvt */, ARM::VTOSLD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12367 { 2288 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12368 { 2288 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12369 { 2288 /* vcvt */, ARM::VTOUHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12370 { 2288 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12371 { 2288 /* vcvt */, ARM::VCVTh2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12372 { 2288 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12373 { 2288 /* vcvt */, ARM::VCVTh2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12374 { 2288 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12375 { 2288 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12376 { 2288 /* vcvt */, ARM::VCVTf2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12377 { 2288 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12378 { 2288 /* vcvt */, ARM::VCVTf2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12379 { 2288 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12380 { 2288 /* vcvt */, ARM::VTOULD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12381 { 2288 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12382 { 2288 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12383 { 2288 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12384 { 2288 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12385 { 2288 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12386 { 2288 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12387 { 2288 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12388 { 2288 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12389 { 2288 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12390 { 2288 /* vcvt */, ARM::VCVTxu2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12391 { 2288 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12392 { 2288 /* vcvt */, ARM::VCVTxu2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12393 { 2288 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12394 { 2288 /* vcvt */, ARM::VSHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12395 { 2288 /* vcvt */, ARM::VSLTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12396 { 2288 /* vcvt */, ARM::VUHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12397 { 2288 /* vcvt */, ARM::VULTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12398 { 2288 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12399 { 2288 /* vcvt */, ARM::VCVTxs2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12400 { 2288 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12401 { 2288 /* vcvt */, ARM::VCVTxs2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12402 { 2288 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12403 { 2288 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12404 { 2288 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12405 { 2288 /* vcvt */, ARM::VCVTxu2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12406 { 2288 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12407 { 2288 /* vcvt */, ARM::VCVTxu2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12408 { 2288 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12409 { 2288 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12410 { 2288 /* vcvt */, ARM::MVE_VCVTs16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12411 { 2288 /* vcvt */, ARM::MVE_VCVTs32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12412 { 2288 /* vcvt */, ARM::MVE_VCVTu16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12413 { 2288 /* vcvt */, ARM::MVE_VCVTu32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12414 { 2288 /* vcvt */, ARM::MVE_VCVTf32s32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12415 { 2288 /* vcvt */, ARM::MVE_VCVTf32u32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12416 { 2288 /* vcvt */, ARM::MVE_VCVTf16s16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12417 { 2288 /* vcvt */, ARM::MVE_VCVTf16u16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12418 { 2293 /* vcvta */, ARM::VCVTANSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12419 { 2293 /* vcvta */, ARM::VCVTANSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12420 { 2293 /* vcvta */, ARM::VCVTANSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12421 { 2293 /* vcvta */, ARM::VCVTANSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12422 { 2293 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12423 { 2293 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12424 { 2293 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12425 { 2293 /* vcvta */, ARM::VCVTANUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12426 { 2293 /* vcvta */, ARM::VCVTANUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12427 { 2293 /* vcvta */, ARM::VCVTANUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12428 { 2293 /* vcvta */, ARM::VCVTANUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12429 { 2293 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12430 { 2293 /* vcvta */, ARM::VCVTAUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12431 { 2293 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12432 { 2293 /* vcvta */, ARM::MVE_VCVTs16f16a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12433 { 2293 /* vcvta */, ARM::MVE_VCVTs32f32a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12434 { 2293 /* vcvta */, ARM::MVE_VCVTu16f16a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12435 { 2293 /* vcvta */, ARM::MVE_VCVTu32f32a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12436 { 2299 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12437 { 2299 /* vcvtb */, ARM::VCVTBHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
12438 { 2299 /* vcvtb */, ARM::BF16_VCVTB, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasBF16, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12439 { 2299 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12440 { 2299 /* vcvtb */, ARM::VCVTBDH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12441 { 2299 /* vcvtb */, ARM::MVE_VCVTf16f32bh, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12442 { 2299 /* vcvtb */, ARM::MVE_VCVTf32f16bh, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12443 { 2305 /* vcvtm */, ARM::VCVTMNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12444 { 2305 /* vcvtm */, ARM::VCVTMNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12445 { 2305 /* vcvtm */, ARM::VCVTMNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12446 { 2305 /* vcvtm */, ARM::VCVTMNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12447 { 2305 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12448 { 2305 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12449 { 2305 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12450 { 2305 /* vcvtm */, ARM::VCVTMNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12451 { 2305 /* vcvtm */, ARM::VCVTMNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12452 { 2305 /* vcvtm */, ARM::VCVTMNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12453 { 2305 /* vcvtm */, ARM::VCVTMNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12454 { 2305 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12455 { 2305 /* vcvtm */, ARM::VCVTMUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12456 { 2305 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12457 { 2305 /* vcvtm */, ARM::MVE_VCVTs16f16m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12458 { 2305 /* vcvtm */, ARM::MVE_VCVTs32f32m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12459 { 2305 /* vcvtm */, ARM::MVE_VCVTu16f16m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12460 { 2305 /* vcvtm */, ARM::MVE_VCVTu32f32m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12461 { 2311 /* vcvtn */, ARM::VCVTNNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12462 { 2311 /* vcvtn */, ARM::VCVTNNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12463 { 2311 /* vcvtn */, ARM::VCVTNNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12464 { 2311 /* vcvtn */, ARM::VCVTNNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12465 { 2311 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12466 { 2311 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12467 { 2311 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12468 { 2311 /* vcvtn */, ARM::VCVTNNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12469 { 2311 /* vcvtn */, ARM::VCVTNNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12470 { 2311 /* vcvtn */, ARM::VCVTNNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12471 { 2311 /* vcvtn */, ARM::VCVTNNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12472 { 2311 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12473 { 2311 /* vcvtn */, ARM::VCVTNUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12474 { 2311 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12475 { 2311 /* vcvtn */, ARM::MVE_VCVTs16f16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12476 { 2311 /* vcvtn */, ARM::MVE_VCVTs32f32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12477 { 2311 /* vcvtn */, ARM::MVE_VCVTu16f16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12478 { 2311 /* vcvtn */, ARM::MVE_VCVTu32f32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12479 { 2317 /* vcvtp */, ARM::VCVTPNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12480 { 2317 /* vcvtp */, ARM::VCVTPNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12481 { 2317 /* vcvtp */, ARM::VCVTPNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12482 { 2317 /* vcvtp */, ARM::VCVTPNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12483 { 2317 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12484 { 2317 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12485 { 2317 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12486 { 2317 /* vcvtp */, ARM::VCVTPNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12487 { 2317 /* vcvtp */, ARM::VCVTPNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12488 { 2317 /* vcvtp */, ARM::VCVTPNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12489 { 2317 /* vcvtp */, ARM::VCVTPNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12490 { 2317 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12491 { 2317 /* vcvtp */, ARM::VCVTPUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12492 { 2317 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12493 { 2317 /* vcvtp */, ARM::MVE_VCVTs16f16p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12494 { 2317 /* vcvtp */, ARM::MVE_VCVTs32f32p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12495 { 2317 /* vcvtp */, ARM::MVE_VCVTu16f16p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12496 { 2317 /* vcvtp */, ARM::MVE_VCVTu32f32p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12497 { 2323 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12498 { 2323 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12499 { 2323 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12500 { 2323 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12501 { 2323 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12502 { 2323 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12503 { 2329 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12504 { 2329 /* vcvtt */, ARM::VCVTTHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
12505 { 2329 /* vcvtt */, ARM::BF16_VCVTT, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasBF16, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12506 { 2329 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12507 { 2329 /* vcvtt */, ARM::VCVTTDH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12508 { 2329 /* vcvtt */, ARM::MVE_VCVTf16f32th, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12509 { 2329 /* vcvtt */, ARM::MVE_VCVTf32f16th, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12510 { 2335 /* vcx1 */, ARM::CDE_VCX1_fpdp, Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_Imm11b }, },
12511 { 2335 /* vcx1 */, ARM::CDE_VCX1_fpsp, Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_Imm11b }, },
12512 { 2335 /* vcx1 */, ARM::CDE_VCX1_vec, Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_Imm12b }, },
12513 { 2340 /* vcx1a */, ARM::CDE_VCX1A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_Imm11b }, },
12514 { 2340 /* vcx1a */, ARM::CDE_VCX1A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_Imm11b }, },
12515 { 2340 /* vcx1a */, ARM::CDE_VCX1A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_Imm12b }, },
12516 { 2346 /* vcx2 */, ARM::CDE_VCX2_fpdp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm6b }, },
12517 { 2346 /* vcx2 */, ARM::CDE_VCX2_fpsp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_Imm6b }, },
12518 { 2346 /* vcx2 */, ARM::CDE_VCX2_vec, Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_Imm7b }, },
12519 { 2351 /* vcx2a */, ARM::CDE_VCX2A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm6b }, },
12520 { 2351 /* vcx2a */, ARM::CDE_VCX2A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_Imm6b }, },
12521 { 2351 /* vcx2a */, ARM::CDE_VCX2A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_Imm7b }, },
12522 { 2357 /* vcx3 */, ARM::CDE_VCX3_fpdp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm3b }, },
12523 { 2357 /* vcx3 */, ARM::CDE_VCX3_fpsp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_HPR, MCK_Imm3b }, },
12524 { 2357 /* vcx3 */, ARM::CDE_VCX3_vec, Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_Imm4b }, },
12525 { 2362 /* vcx3a */, ARM::CDE_VCX3A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm3b }, },
12526 { 2362 /* vcx3a */, ARM::CDE_VCX3A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_HPR, MCK_Imm3b }, },
12527 { 2362 /* vcx3a */, ARM::CDE_VCX3A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_Imm4b }, },
12528 { 2368 /* vddup */, ARM::MVE_VDDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12529 { 2368 /* vddup */, ARM::MVE_VDDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12530 { 2368 /* vddup */, ARM::MVE_VDDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12531 { 2374 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12532 { 2374 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12533 { 2374 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12534 { 2374 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12535 { 2374 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12536 { 2374 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12537 { 2379 /* vdot */, ARM::BF16VDOTS_VDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12538 { 2379 /* vdot */, ARM::BF16VDOTS_VDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12539 { 2379 /* vdot */, ARM::BF16VDOTI_VDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
12540 { 2379 /* vdot */, ARM::BF16VDOTI_VDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
12541 { 2384 /* vdup */, ARM::VDUP16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_GPR }, },
12542 { 2384 /* vdup */, ARM::VDUP16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_GPR }, },
12543 { 2384 /* vdup */, ARM::VDUP32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_GPR }, },
12544 { 2384 /* vdup */, ARM::VDUP32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_GPR }, },
12545 { 2384 /* vdup */, ARM::VDUP8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_GPR }, },
12546 { 2384 /* vdup */, ARM::VDUP8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_GPR }, },
12547 { 2384 /* vdup */, ARM::MVE_VDUP16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_rGPR }, },
12548 { 2384 /* vdup */, ARM::MVE_VDUP32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_rGPR }, },
12549 { 2384 /* vdup */, ARM::MVE_VDUP8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_rGPR }, },
12550 { 2384 /* vdup */, ARM::VDUPLN16q, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_DPR, MCK_VectorIndex16 }, },
12551 { 2384 /* vdup */, ARM::VDUPLN16d, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, },
12552 { 2384 /* vdup */, ARM::VDUPLN32q, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_DPR, MCK_VectorIndex32 }, },
12553 { 2384 /* vdup */, ARM::VDUPLN32d, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_VectorIndex32 }, },
12554 { 2384 /* vdup */, ARM::VDUPLN8q, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_DPR, MCK_VectorIndex8 }, },
12555 { 2384 /* vdup */, ARM::VDUPLN8d, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_VectorIndex8 }, },
12556 { 2389 /* vdwdup */, ARM::MVE_VDWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12557 { 2389 /* vdwdup */, ARM::MVE_VDWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12558 { 2389 /* vdwdup */, ARM::MVE_VDWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12559 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
12560 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
12561 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
12562 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
12563 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
12564 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
12565 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
12566 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
12567 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
12568 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
12569 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12570 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12571 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12572 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12573 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12574 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12575 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12576 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12577 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12578 { 2396 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12579 { 2396 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12580 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12581 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12582 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12583 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12584 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12585 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12586 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12587 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12588 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12589 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12590 { 2396 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12591 { 2401 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm0_7 }, },
12592 { 2401 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, },
12593 { 2401 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm0_3 }, },
12594 { 2401 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, },
12595 { 2401 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm0_1 }, },
12596 { 2401 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
12597 { 2401 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, },
12598 { 2401 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_7 }, },
12599 { 2401 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, },
12600 { 2401 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_3 }, },
12601 { 2401 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, },
12602 { 2401 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_1 }, },
12603 { 2401 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
12604 { 2401 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, },
12605 { 2406 /* vfma */, ARM::VFMAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12606 { 2406 /* vfma */, ARM::VFMAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12607 { 2406 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12608 { 2406 /* vfma */, ARM::VFMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12609 { 2406 /* vfma */, ARM::VFMAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12610 { 2406 /* vfma */, ARM::VFMAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12611 { 2406 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12612 { 2406 /* vfma */, ARM::MVE_VFMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12613 { 2406 /* vfma */, ARM::MVE_VFMA_qr_f32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12614 { 2406 /* vfma */, ARM::MVE_VFMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12615 { 2406 /* vfma */, ARM::MVE_VFMA_qr_f16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12616 { 2411 /* vfmab */, ARM::VBF16MALBQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12617 { 2411 /* vfmab */, ARM::VBF16MALBQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
12618 { 2417 /* vfmal */, ARM::VFMALQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12619 { 2417 /* vfmal */, ARM::VFMALD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
12620 { 2417 /* vfmal */, ARM::VFMALQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
12621 { 2417 /* vfmal */, ARM::VFMALDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, },
12622 { 2423 /* vfmas */, ARM::MVE_VFMA_qr_Sf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12623 { 2423 /* vfmas */, ARM::MVE_VFMA_qr_Sf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12624 { 2429 /* vfmat */, ARM::VBF16MALTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12625 { 2429 /* vfmat */, ARM::VBF16MALTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
12626 { 2435 /* vfms */, ARM::VFMSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12627 { 2435 /* vfms */, ARM::VFMSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12628 { 2435 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12629 { 2435 /* vfms */, ARM::VFMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12630 { 2435 /* vfms */, ARM::VFMShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12631 { 2435 /* vfms */, ARM::VFMShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12632 { 2435 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12633 { 2435 /* vfms */, ARM::MVE_VFMSf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12634 { 2435 /* vfms */, ARM::MVE_VFMSf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12635 { 2440 /* vfmsl */, ARM::VFMSLQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12636 { 2440 /* vfmsl */, ARM::VFMSLD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
12637 { 2440 /* vfmsl */, ARM::VFMSLQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
12638 { 2440 /* vfmsl */, ARM::VFMSLDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, },
12639 { 2446 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12640 { 2446 /* vfnma */, ARM::VFNMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12641 { 2446 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12642 { 2452 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12643 { 2452 /* vfnms */, ARM::VFNMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12644 { 2452 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12645 { 2458 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12646 { 2458 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12647 { 2458 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12648 { 2458 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12649 { 2458 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12650 { 2458 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12651 { 2458 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12652 { 2458 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12653 { 2458 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12654 { 2458 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12655 { 2458 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12656 { 2458 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12657 { 2458 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12658 { 2458 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12659 { 2458 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12660 { 2458 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12661 { 2458 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12662 { 2458 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12663 { 2458 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12664 { 2458 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12665 { 2458 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12666 { 2458 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12667 { 2458 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12668 { 2458 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12669 { 2458 /* vhadd */, ARM::MVE_VHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12670 { 2458 /* vhadd */, ARM::MVE_VHADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12671 { 2458 /* vhadd */, ARM::MVE_VHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12672 { 2458 /* vhadd */, ARM::MVE_VHADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12673 { 2458 /* vhadd */, ARM::MVE_VHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12674 { 2458 /* vhadd */, ARM::MVE_VHADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12675 { 2458 /* vhadd */, ARM::MVE_VHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12676 { 2458 /* vhadd */, ARM::MVE_VHADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12677 { 2458 /* vhadd */, ARM::MVE_VHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12678 { 2458 /* vhadd */, ARM::MVE_VHADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12679 { 2458 /* vhadd */, ARM::MVE_VHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12680 { 2458 /* vhadd */, ARM::MVE_VHADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12681 { 2464 /* vhcadd */, ARM::MVE_VHCADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12682 { 2464 /* vhcadd */, ARM::MVE_VHCADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12683 { 2464 /* vhcadd */, ARM::MVE_VHCADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12684 { 2471 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12685 { 2471 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12686 { 2471 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12687 { 2471 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12688 { 2471 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12689 { 2471 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12690 { 2471 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12691 { 2471 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12692 { 2471 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12693 { 2471 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12694 { 2471 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12695 { 2471 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12696 { 2471 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12697 { 2471 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12698 { 2471 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12699 { 2471 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12700 { 2471 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12701 { 2471 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12702 { 2471 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12703 { 2471 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12704 { 2471 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12705 { 2471 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12706 { 2471 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12707 { 2471 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12708 { 2471 /* vhsub */, ARM::MVE_VHSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12709 { 2471 /* vhsub */, ARM::MVE_VHSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12710 { 2471 /* vhsub */, ARM::MVE_VHSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12711 { 2471 /* vhsub */, ARM::MVE_VHSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12712 { 2471 /* vhsub */, ARM::MVE_VHSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12713 { 2471 /* vhsub */, ARM::MVE_VHSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12714 { 2471 /* vhsub */, ARM::MVE_VHSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12715 { 2471 /* vhsub */, ARM::MVE_VHSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12716 { 2471 /* vhsub */, ARM::MVE_VHSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12717 { 2471 /* vhsub */, ARM::MVE_VHSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12718 { 2471 /* vhsub */, ARM::MVE_VHSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12719 { 2471 /* vhsub */, ARM::MVE_VHSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12720 { 2477 /* vidup */, ARM::MVE_VIDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12721 { 2477 /* vidup */, ARM::MVE_VIDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12722 { 2477 /* vidup */, ARM::MVE_VIDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12723 { 2483 /* vins */, ARM::VINSH, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12724 { 2488 /* viwdup */, ARM::MVE_VIWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12725 { 2488 /* viwdup */, ARM::MVE_VIWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12726 { 2488 /* viwdup */, ARM::MVE_VIWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12727 { 2495 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12728 { 2501 /* vld1 */, ARM::VLD1DUPq16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, },
12729 { 2501 /* vld1 */, ARM::VLD1q16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12730 { 2501 /* vld1 */, ARM::VLD1d16Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12731 { 2501 /* vld1 */, ARM::VLD1DUPd16, Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16 }, },
12732 { 2501 /* vld1 */, ARM::VLD1d16, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, },
12733 { 2501 /* vld1 */, ARM::VLD1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, },
12734 { 2501 /* vld1 */, ARM::VLD1d16T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12735 { 2501 /* vld1 */, ARM::VLD1DUPq32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, },
12736 { 2501 /* vld1 */, ARM::VLD1q32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12737 { 2501 /* vld1 */, ARM::VLD1d32Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12738 { 2501 /* vld1 */, ARM::VLD1DUPd32, Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32 }, },
12739 { 2501 /* vld1 */, ARM::VLD1d32, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, },
12740 { 2501 /* vld1 */, ARM::VLD1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, },
12741 { 2501 /* vld1 */, ARM::VLD1d32T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12742 { 2501 /* vld1 */, ARM::VLD1q64, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12743 { 2501 /* vld1 */, ARM::VLD1d64Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12744 { 2501 /* vld1 */, ARM::VLD1d64, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, },
12745 { 2501 /* vld1 */, ARM::VLD1d64T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12746 { 2501 /* vld1 */, ARM::VLD1DUPq8, Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone }, },
12747 { 2501 /* vld1 */, ARM::VLD1q8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12748 { 2501 /* vld1 */, ARM::VLD1d8Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12749 { 2501 /* vld1 */, ARM::VLD1DUPd8, Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone }, },
12750 { 2501 /* vld1 */, ARM::VLD1d8, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, },
12751 { 2501 /* vld1 */, ARM::VLD1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, },
12752 { 2501 /* vld1 */, ARM::VLD1d8T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12753 { 2501 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12754 { 2501 /* vld1 */, ARM::VLD1DUPq16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
12755 { 2501 /* vld1 */, ARM::VLD1q16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12756 { 2501 /* vld1 */, ARM::VLD1q16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12757 { 2501 /* vld1 */, ARM::VLD1d16Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12758 { 2501 /* vld1 */, ARM::VLD1d16Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12759 { 2501 /* vld1 */, ARM::VLD1DUPd16wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12760 { 2501 /* vld1 */, ARM::VLD1DUPd16wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
12761 { 2501 /* vld1 */, ARM::VLD1d16wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12762 { 2501 /* vld1 */, ARM::VLD1d16wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
12763 { 2501 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
12764 { 2501 /* vld1 */, ARM::VLD1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
12765 { 2501 /* vld1 */, ARM::VLD1d16Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12766 { 2501 /* vld1 */, ARM::VLD1d16Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12767 { 2501 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12768 { 2501 /* vld1 */, ARM::VLD1DUPq32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12769 { 2501 /* vld1 */, ARM::VLD1q32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12770 { 2501 /* vld1 */, ARM::VLD1q32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12771 { 2501 /* vld1 */, ARM::VLD1d32Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12772 { 2501 /* vld1 */, ARM::VLD1d32Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12773 { 2501 /* vld1 */, ARM::VLD1DUPd32wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12774 { 2501 /* vld1 */, ARM::VLD1DUPd32wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12775 { 2501 /* vld1 */, ARM::VLD1d32wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12776 { 2501 /* vld1 */, ARM::VLD1d32wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
12777 { 2501 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12778 { 2501 /* vld1 */, ARM::VLD1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
12779 { 2501 /* vld1 */, ARM::VLD1d32Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12780 { 2501 /* vld1 */, ARM::VLD1d32Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12781 { 2501 /* vld1 */, ARM::VLD1q64wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12782 { 2501 /* vld1 */, ARM::VLD1q64wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12783 { 2501 /* vld1 */, ARM::VLD1d64Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12784 { 2501 /* vld1 */, ARM::VLD1d64Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12785 { 2501 /* vld1 */, ARM::VLD1d64wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12786 { 2501 /* vld1 */, ARM::VLD1d64wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
12787 { 2501 /* vld1 */, ARM::VLD1d64Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12788 { 2501 /* vld1 */, ARM::VLD1d64Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12789 { 2501 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12790 { 2501 /* vld1 */, ARM::VLD1DUPq8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12791 { 2501 /* vld1 */, ARM::VLD1q8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12792 { 2501 /* vld1 */, ARM::VLD1q8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12793 { 2501 /* vld1 */, ARM::VLD1d8Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12794 { 2501 /* vld1 */, ARM::VLD1d8Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12795 { 2501 /* vld1 */, ARM::VLD1DUPd8wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12796 { 2501 /* vld1 */, ARM::VLD1DUPd8wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12797 { 2501 /* vld1 */, ARM::VLD1d8wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12798 { 2501 /* vld1 */, ARM::VLD1d8wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
12799 { 2501 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12800 { 2501 /* vld1 */, ARM::VLD1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
12801 { 2501 /* vld1 */, ARM::VLD1d8Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12802 { 2501 /* vld1 */, ARM::VLD1d8Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12803 { 2501 /* vld1 */, ARM::VLD1LNd16, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12804 { 2501 /* vld1 */, ARM::VLD1LNd8, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12805 { 2501 /* vld1 */, ARM::VLD1LNd16_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12806 { 2501 /* vld1 */, ARM::VLD1LNd32, Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
12807 { 2501 /* vld1 */, ARM::VLD1LNd32_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12808 { 2501 /* vld1 */, ARM::VLD1LNd8_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12809 { 2506 /* vld2 */, ARM::VLD2DUPd16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, },
12810 { 2506 /* vld2 */, ARM::VLD2d16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12811 { 2506 /* vld2 */, ARM::VLD2DUPd16x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32 }, },
12812 { 2506 /* vld2 */, ARM::VLD2b16, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
12813 { 2506 /* vld2 */, ARM::VLD2q16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12814 { 2506 /* vld2 */, ARM::VLD2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, },
12815 { 2506 /* vld2 */, ARM::VLD2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, },
12816 { 2506 /* vld2 */, ARM::VLD2DUPd32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64 }, },
12817 { 2506 /* vld2 */, ARM::VLD2d32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12818 { 2506 /* vld2 */, ARM::VLD2DUPd32x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64 }, },
12819 { 2506 /* vld2 */, ARM::VLD2b32, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
12820 { 2506 /* vld2 */, ARM::VLD2q32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12821 { 2506 /* vld2 */, ARM::VLD2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, },
12822 { 2506 /* vld2 */, ARM::VLD2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, },
12823 { 2506 /* vld2 */, ARM::VLD2DUPd8, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, },
12824 { 2506 /* vld2 */, ARM::VLD2d8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12825 { 2506 /* vld2 */, ARM::VLD2DUPd8x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16 }, },
12826 { 2506 /* vld2 */, ARM::VLD2b8, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
12827 { 2506 /* vld2 */, ARM::VLD2q8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12828 { 2506 /* vld2 */, ARM::VLD2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, },
12829 { 2506 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12830 { 2506 /* vld2 */, ARM::VLD2DUPd16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12831 { 2506 /* vld2 */, ARM::VLD2d16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12832 { 2506 /* vld2 */, ARM::VLD2d16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12833 { 2506 /* vld2 */, ARM::VLD2DUPd16x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12834 { 2506 /* vld2 */, ARM::VLD2DUPd16x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12835 { 2506 /* vld2 */, ARM::VLD2b16wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12836 { 2506 /* vld2 */, ARM::VLD2b16wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
12837 { 2506 /* vld2 */, ARM::VLD2q16wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12838 { 2506 /* vld2 */, ARM::VLD2q16wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12839 { 2506 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12840 { 2506 /* vld2 */, ARM::VLD2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
12841 { 2506 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12842 { 2506 /* vld2 */, ARM::VLD2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
12843 { 2506 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12844 { 2506 /* vld2 */, ARM::VLD2DUPd32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
12845 { 2506 /* vld2 */, ARM::VLD2d32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12846 { 2506 /* vld2 */, ARM::VLD2d32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12847 { 2506 /* vld2 */, ARM::VLD2DUPd32x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12848 { 2506 /* vld2 */, ARM::VLD2DUPd32x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
12849 { 2506 /* vld2 */, ARM::VLD2b32wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12850 { 2506 /* vld2 */, ARM::VLD2b32wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
12851 { 2506 /* vld2 */, ARM::VLD2q32wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12852 { 2506 /* vld2 */, ARM::VLD2q32wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12853 { 2506 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12854 { 2506 /* vld2 */, ARM::VLD2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
12855 { 2506 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12856 { 2506 /* vld2 */, ARM::VLD2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
12857 { 2506 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12858 { 2506 /* vld2 */, ARM::VLD2DUPd8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
12859 { 2506 /* vld2 */, ARM::VLD2d8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12860 { 2506 /* vld2 */, ARM::VLD2d8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12861 { 2506 /* vld2 */, ARM::VLD2DUPd8x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12862 { 2506 /* vld2 */, ARM::VLD2DUPd8x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
12863 { 2506 /* vld2 */, ARM::VLD2b8wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12864 { 2506 /* vld2 */, ARM::VLD2b8wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
12865 { 2506 /* vld2 */, ARM::VLD2q8wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12866 { 2506 /* vld2 */, ARM::VLD2q8wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12867 { 2506 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
12868 { 2506 /* vld2 */, ARM::VLD2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
12869 { 2511 /* vld20 */, ARM::MVE_VLD20_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
12870 { 2511 /* vld20 */, ARM::MVE_VLD20_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
12871 { 2511 /* vld20 */, ARM::MVE_VLD20_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
12872 { 2511 /* vld20 */, ARM::MVE_VLD20_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12873 { 2511 /* vld20 */, ARM::MVE_VLD20_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12874 { 2511 /* vld20 */, ARM::MVE_VLD20_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12875 { 2517 /* vld21 */, ARM::MVE_VLD21_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
12876 { 2517 /* vld21 */, ARM::MVE_VLD21_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
12877 { 2517 /* vld21 */, ARM::MVE_VLD21_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
12878 { 2517 /* vld21 */, ARM::MVE_VLD21_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12879 { 2517 /* vld21 */, ARM::MVE_VLD21_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12880 { 2517 /* vld21 */, ARM::MVE_VLD21_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12881 { 2523 /* vld3 */, ARM::VLD3DUPdAsm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
12882 { 2523 /* vld3 */, ARM::VLD3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12883 { 2523 /* vld3 */, ARM::VLD3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, },
12884 { 2523 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
12885 { 2523 /* vld3 */, ARM::VLD3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
12886 { 2523 /* vld3 */, ARM::VLD3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, },
12887 { 2523 /* vld3 */, ARM::VLD3DUPdAsm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
12888 { 2523 /* vld3 */, ARM::VLD3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12889 { 2523 /* vld3 */, ARM::VLD3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, },
12890 { 2523 /* vld3 */, ARM::VLD3DUPqAsm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
12891 { 2523 /* vld3 */, ARM::VLD3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
12892 { 2523 /* vld3 */, ARM::VLD3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, },
12893 { 2523 /* vld3 */, ARM::VLD3DUPdAsm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
12894 { 2523 /* vld3 */, ARM::VLD3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12895 { 2523 /* vld3 */, ARM::VLD3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, },
12896 { 2523 /* vld3 */, ARM::VLD3DUPqAsm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
12897 { 2523 /* vld3 */, ARM::VLD3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
12898 { 2523 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12899 { 2523 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12900 { 2523 /* vld3 */, ARM::VLD3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12901 { 2523 /* vld3 */, ARM::VLD3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12902 { 2523 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12903 { 2523 /* vld3 */, ARM::VLD3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
12904 { 2523 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12905 { 2523 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12906 { 2523 /* vld3 */, ARM::VLD3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12907 { 2523 /* vld3 */, ARM::VLD3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
12908 { 2523 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12909 { 2523 /* vld3 */, ARM::VLD3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
12910 { 2523 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12911 { 2523 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12912 { 2523 /* vld3 */, ARM::VLD3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12913 { 2523 /* vld3 */, ARM::VLD3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12914 { 2523 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12915 { 2523 /* vld3 */, ARM::VLD3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
12916 { 2523 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12917 { 2523 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12918 { 2523 /* vld3 */, ARM::VLD3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12919 { 2523 /* vld3 */, ARM::VLD3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
12920 { 2523 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12921 { 2523 /* vld3 */, ARM::VLD3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
12922 { 2523 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12923 { 2523 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12924 { 2523 /* vld3 */, ARM::VLD3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12925 { 2523 /* vld3 */, ARM::VLD3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12926 { 2523 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12927 { 2523 /* vld3 */, ARM::VLD3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
12928 { 2523 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12929 { 2523 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12930 { 2523 /* vld3 */, ARM::VLD3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12931 { 2523 /* vld3 */, ARM::VLD3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
12932 { 2523 /* vld3 */, ARM::VLD3d16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
12933 { 2523 /* vld3 */, ARM::VLD3q16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
12934 { 2523 /* vld3 */, ARM::VLD3d32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
12935 { 2523 /* vld3 */, ARM::VLD3q32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
12936 { 2523 /* vld3 */, ARM::VLD3d8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
12937 { 2523 /* vld3 */, ARM::VLD3q8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
12938 { 2523 /* vld3 */, ARM::VLD3d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12939 { 2523 /* vld3 */, ARM::VLD3q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12940 { 2523 /* vld3 */, ARM::VLD3d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12941 { 2523 /* vld3 */, ARM::VLD3q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12942 { 2523 /* vld3 */, ARM::VLD3d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12943 { 2523 /* vld3 */, ARM::VLD3q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12944 { 2523 /* vld3 */, ARM::VLD3DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12945 { 2523 /* vld3 */, ARM::VLD3DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12946 { 2523 /* vld3 */, ARM::VLD3DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12947 { 2523 /* vld3 */, ARM::VLD3DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12948 { 2523 /* vld3 */, ARM::VLD3DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12949 { 2523 /* vld3 */, ARM::VLD3DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12950 { 2523 /* vld3 */, ARM::VLD3DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
12951 { 2523 /* vld3 */, ARM::VLD3DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
12952 { 2523 /* vld3 */, ARM::VLD3DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
12953 { 2523 /* vld3 */, ARM::VLD3DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
12954 { 2523 /* vld3 */, ARM::VLD3DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
12955 { 2523 /* vld3 */, ARM::VLD3DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
12956 { 2528 /* vld4 */, ARM::VLD4DUPdAsm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64 }, },
12957 { 2528 /* vld4 */, ARM::VLD4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12958 { 2528 /* vld4 */, ARM::VLD4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, },
12959 { 2528 /* vld4 */, ARM::VLD4DUPqAsm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64 }, },
12960 { 2528 /* vld4 */, ARM::VLD4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
12961 { 2528 /* vld4 */, ARM::VLD4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, },
12962 { 2528 /* vld4 */, ARM::VLD4DUPdAsm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128 }, },
12963 { 2528 /* vld4 */, ARM::VLD4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12964 { 2528 /* vld4 */, ARM::VLD4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, },
12965 { 2528 /* vld4 */, ARM::VLD4DUPqAsm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128 }, },
12966 { 2528 /* vld4 */, ARM::VLD4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
12967 { 2528 /* vld4 */, ARM::VLD4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, },
12968 { 2528 /* vld4 */, ARM::VLD4DUPdAsm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32 }, },
12969 { 2528 /* vld4 */, ARM::VLD4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12970 { 2528 /* vld4 */, ARM::VLD4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, },
12971 { 2528 /* vld4 */, ARM::VLD4DUPqAsm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32 }, },
12972 { 2528 /* vld4 */, ARM::VLD4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
12973 { 2528 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12974 { 2528 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
12975 { 2528 /* vld4 */, ARM::VLD4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12976 { 2528 /* vld4 */, ARM::VLD4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12977 { 2528 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12978 { 2528 /* vld4 */, ARM::VLD4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
12979 { 2528 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12980 { 2528 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
12981 { 2528 /* vld4 */, ARM::VLD4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12982 { 2528 /* vld4 */, ARM::VLD4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12983 { 2528 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12984 { 2528 /* vld4 */, ARM::VLD4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
12985 { 2528 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
12986 { 2528 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
12987 { 2528 /* vld4 */, ARM::VLD4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12988 { 2528 /* vld4 */, ARM::VLD4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12989 { 2528 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12990 { 2528 /* vld4 */, ARM::VLD4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
12991 { 2528 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
12992 { 2528 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
12993 { 2528 /* vld4 */, ARM::VLD4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12994 { 2528 /* vld4 */, ARM::VLD4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12995 { 2528 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12996 { 2528 /* vld4 */, ARM::VLD4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
12997 { 2528 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12998 { 2528 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12999 { 2528 /* vld4 */, ARM::VLD4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13000 { 2528 /* vld4 */, ARM::VLD4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13001 { 2528 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
13002 { 2528 /* vld4 */, ARM::VLD4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
13003 { 2528 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13004 { 2528 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13005 { 2528 /* vld4 */, ARM::VLD4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13006 { 2528 /* vld4 */, ARM::VLD4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13007 { 2528 /* vld4 */, ARM::VLD4d16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13008 { 2528 /* vld4 */, ARM::VLD4q16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13009 { 2528 /* vld4 */, ARM::VLD4d32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13010 { 2528 /* vld4 */, ARM::VLD4q32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13011 { 2528 /* vld4 */, ARM::VLD4d8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13012 { 2528 /* vld4 */, ARM::VLD4q8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13013 { 2528 /* vld4 */, ARM::VLD4d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13014 { 2528 /* vld4 */, ARM::VLD4q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13015 { 2528 /* vld4 */, ARM::VLD4d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13016 { 2528 /* vld4 */, ARM::VLD4q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13017 { 2528 /* vld4 */, ARM::VLD4d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13018 { 2528 /* vld4 */, ARM::VLD4q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13019 { 2528 /* vld4 */, ARM::VLD4DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13020 { 2528 /* vld4 */, ARM::VLD4DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13021 { 2528 /* vld4 */, ARM::VLD4DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13022 { 2528 /* vld4 */, ARM::VLD4DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13023 { 2528 /* vld4 */, ARM::VLD4DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13024 { 2528 /* vld4 */, ARM::VLD4DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13025 { 2528 /* vld4 */, ARM::VLD4DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13026 { 2528 /* vld4 */, ARM::VLD4DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13027 { 2528 /* vld4 */, ARM::VLD4DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13028 { 2528 /* vld4 */, ARM::VLD4DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13029 { 2528 /* vld4 */, ARM::VLD4DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13030 { 2528 /* vld4 */, ARM::VLD4DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13031 { 2533 /* vld40 */, ARM::MVE_VLD40_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13032 { 2533 /* vld40 */, ARM::MVE_VLD40_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13033 { 2533 /* vld40 */, ARM::MVE_VLD40_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13034 { 2533 /* vld40 */, ARM::MVE_VLD40_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13035 { 2533 /* vld40 */, ARM::MVE_VLD40_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13036 { 2533 /* vld40 */, ARM::MVE_VLD40_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13037 { 2539 /* vld41 */, ARM::MVE_VLD41_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13038 { 2539 /* vld41 */, ARM::MVE_VLD41_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13039 { 2539 /* vld41 */, ARM::MVE_VLD41_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13040 { 2539 /* vld41 */, ARM::MVE_VLD41_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13041 { 2539 /* vld41 */, ARM::MVE_VLD41_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13042 { 2539 /* vld41 */, ARM::MVE_VLD41_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13043 { 2545 /* vld42 */, ARM::MVE_VLD42_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13044 { 2545 /* vld42 */, ARM::MVE_VLD42_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13045 { 2545 /* vld42 */, ARM::MVE_VLD42_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13046 { 2545 /* vld42 */, ARM::MVE_VLD42_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13047 { 2545 /* vld42 */, ARM::MVE_VLD42_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13048 { 2545 /* vld42 */, ARM::MVE_VLD42_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13049 { 2551 /* vld43 */, ARM::MVE_VLD43_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13050 { 2551 /* vld43 */, ARM::MVE_VLD43_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13051 { 2551 /* vld43 */, ARM::MVE_VLD43_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13052 { 2551 /* vld43 */, ARM::MVE_VLD43_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13053 { 2551 /* vld43 */, ARM::MVE_VLD43_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13054 { 2551 /* vld43 */, ARM::MVE_VLD43_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13055 { 2557 /* vldmdb */, ARM::VLDMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
13056 { 2557 /* vldmdb */, ARM::VLDMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
13057 { 2564 /* vldmia */, ARM::VLDMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
13058 { 2564 /* vldmia */, ARM::VLDMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, },
13059 { 2564 /* vldmia */, ARM::VLDMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
13060 { 2564 /* vldmia */, ARM::VLDMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
13061 { 2571 /* vldr */, ARM::VLDR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset }, },
13062 { 2571 /* vldr */, ARM::VLDR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, },
13063 { 2571 /* vldr */, ARM::VLDR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, },
13064 { 2571 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, },
13065 { 2571 /* vldr */, ARM::VLDR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, },
13066 { 2571 /* vldr */, ARM::VLDR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, },
13067 { 2571 /* vldr */, ARM::VLDRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, },
13068 { 2571 /* vldr */, ARM::VLDRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
13069 { 2571 /* vldr */, ARM::VLDRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
13070 { 2571 /* vldr */, ARM::VLDRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
13071 { 2571 /* vldr */, ARM::VLDRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, },
13072 { 2571 /* vldr */, ARM::VLDR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13073 { 2571 /* vldr */, ARM::VLDR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13074 { 2571 /* vldr */, ARM::VLDR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13075 { 2571 /* vldr */, ARM::VLDR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13076 { 2571 /* vldr */, ARM::VLDR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13077 { 2571 /* vldr */, ARM::VLDR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13078 { 2571 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13079 { 2571 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_post, Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13080 { 2571 /* vldr */, ARM::VLDR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13081 { 2571 /* vldr */, ARM::VLDR_P0_post, Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13082 { 2571 /* vldr */, ARM::VLDR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13083 { 2571 /* vldr */, ARM::VLDR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13084 { 2576 /* vldrb */, ARM::MVE_VLDRBS16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13085 { 2576 /* vldrb */, ARM::MVE_VLDRBS16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13086 { 2576 /* vldrb */, ARM::MVE_VLDRBS32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13087 { 2576 /* vldrb */, ARM::MVE_VLDRBS32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13088 { 2576 /* vldrb */, ARM::MVE_VLDRBU16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13089 { 2576 /* vldrb */, ARM::MVE_VLDRBU16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13090 { 2576 /* vldrb */, ARM::MVE_VLDRBU32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13091 { 2576 /* vldrb */, ARM::MVE_VLDRBU32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13092 { 2576 /* vldrb */, ARM::MVE_VLDRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0Offset }, },
13093 { 2576 /* vldrb */, ARM::MVE_VLDRBU8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13094 { 2576 /* vldrb */, ARM::MVE_VLDRBS16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13095 { 2576 /* vldrb */, ARM::MVE_VLDRBS16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13096 { 2576 /* vldrb */, ARM::MVE_VLDRBS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13097 { 2576 /* vldrb */, ARM::MVE_VLDRBS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13098 { 2576 /* vldrb */, ARM::MVE_VLDRBU16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13099 { 2576 /* vldrb */, ARM::MVE_VLDRBU16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13100 { 2576 /* vldrb */, ARM::MVE_VLDRBU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13101 { 2576 /* vldrb */, ARM::MVE_VLDRBU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13102 { 2576 /* vldrb */, ARM::MVE_VLDRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, },
13103 { 2576 /* vldrb */, ARM::MVE_VLDRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, },
13104 { 2582 /* vldrd */, ARM::MVE_VLDRDU64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset }, },
13105 { 2582 /* vldrd */, ARM::MVE_VLDRDU64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13106 { 2582 /* vldrd */, ARM::MVE_VLDRDU64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS3Offset }, },
13107 { 2582 /* vldrd */, ARM::MVE_VLDRDU64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, },
13108 { 2588 /* vldrh */, ARM::MVE_VLDRHS32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13109 { 2588 /* vldrh */, ARM::MVE_VLDRHS32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13110 { 2588 /* vldrh */, ARM::MVE_VLDRHS32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
13111 { 2588 /* vldrh */, ARM::MVE_VLDRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1Offset }, },
13112 { 2588 /* vldrh */, ARM::MVE_VLDRHU16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13113 { 2588 /* vldrh */, ARM::MVE_VLDRHU16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13114 { 2588 /* vldrh */, ARM::MVE_VLDRHU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13115 { 2588 /* vldrh */, ARM::MVE_VLDRHU32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13116 { 2588 /* vldrh */, ARM::MVE_VLDRHU32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
13117 { 2588 /* vldrh */, ARM::MVE_VLDRHS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
13118 { 2588 /* vldrh */, ARM::MVE_VLDRHS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
13119 { 2588 /* vldrh */, ARM::MVE_VLDRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, },
13120 { 2588 /* vldrh */, ARM::MVE_VLDRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, },
13121 { 2588 /* vldrh */, ARM::MVE_VLDRHU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
13122 { 2588 /* vldrh */, ARM::MVE_VLDRHU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
13123 { 2594 /* vldrw */, ARM::MVE_VLDRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2Offset }, },
13124 { 2594 /* vldrw */, ARM::MVE_VLDRWU32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset }, },
13125 { 2594 /* vldrw */, ARM::MVE_VLDRWU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13126 { 2594 /* vldrw */, ARM::MVE_VLDRWU32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS2Offset }, },
13127 { 2594 /* vldrw */, ARM::MVE_VLDRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, },
13128 { 2594 /* vldrw */, ARM::MVE_VLDRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, },
13129 { 2594 /* vldrw */, ARM::MVE_VLDRWU32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, },
13130 { 2600 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0__imm_95_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
13131 { 2600 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13132 { 2600 /* vlldm */, ARM::VLLDM_T2, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13133 { 2606 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0__imm_95_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
13134 { 2606 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13135 { 2606 /* vlstm */, ARM::VLSTM_T2, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13136 { 2612 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13137 { 2612 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13138 { 2612 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13139 { 2612 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13140 { 2612 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13141 { 2612 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13142 { 2612 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13143 { 2612 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13144 { 2612 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13145 { 2612 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13146 { 2612 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13147 { 2612 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13148 { 2612 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13149 { 2612 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13150 { 2612 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13151 { 2612 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13152 { 2612 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13153 { 2612 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13154 { 2612 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13155 { 2612 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13156 { 2612 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13157 { 2612 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13158 { 2612 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13159 { 2612 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13160 { 2612 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13161 { 2612 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13162 { 2612 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13163 { 2612 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13164 { 2612 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13165 { 2612 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13166 { 2612 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13167 { 2612 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13168 { 2612 /* vmax */, ARM::MVE_VMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13169 { 2612 /* vmax */, ARM::MVE_VMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13170 { 2612 /* vmax */, ARM::MVE_VMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13171 { 2612 /* vmax */, ARM::MVE_VMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13172 { 2612 /* vmax */, ARM::MVE_VMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13173 { 2612 /* vmax */, ARM::MVE_VMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13174 { 2617 /* vmaxa */, ARM::MVE_VMAXAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13175 { 2617 /* vmaxa */, ARM::MVE_VMAXAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13176 { 2617 /* vmaxa */, ARM::MVE_VMAXAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13177 { 2623 /* vmaxav */, ARM::MVE_VMAXAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13178 { 2623 /* vmaxav */, ARM::MVE_VMAXAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13179 { 2623 /* vmaxav */, ARM::MVE_VMAXAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13180 { 2630 /* vmaxnm */, ARM::NEON_VMAXNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13181 { 2630 /* vmaxnm */, ARM::NEON_VMAXNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13182 { 2630 /* vmaxnm */, ARM::VFP_VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13183 { 2630 /* vmaxnm */, ARM::VFP_VMAXNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13184 { 2630 /* vmaxnm */, ARM::NEON_VMAXNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13185 { 2630 /* vmaxnm */, ARM::NEON_VMAXNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13186 { 2630 /* vmaxnm */, ARM::VFP_VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13187 { 2630 /* vmaxnm */, ARM::MVE_VMAXNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13188 { 2630 /* vmaxnm */, ARM::MVE_VMAXNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13189 { 2637 /* vmaxnma */, ARM::MVE_VMAXNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13190 { 2637 /* vmaxnma */, ARM::MVE_VMAXNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13191 { 2645 /* vmaxnmav */, ARM::MVE_VMAXNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13192 { 2645 /* vmaxnmav */, ARM::MVE_VMAXNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13193 { 2654 /* vmaxnmv */, ARM::MVE_VMAXNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13194 { 2654 /* vmaxnmv */, ARM::MVE_VMAXNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13195 { 2662 /* vmaxv */, ARM::MVE_VMAXVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13196 { 2662 /* vmaxv */, ARM::MVE_VMAXVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13197 { 2662 /* vmaxv */, ARM::MVE_VMAXVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13198 { 2662 /* vmaxv */, ARM::MVE_VMAXVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, },
13199 { 2662 /* vmaxv */, ARM::MVE_VMAXVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, },
13200 { 2662 /* vmaxv */, ARM::MVE_VMAXVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, },
13201 { 2668 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13202 { 2668 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13203 { 2668 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13204 { 2668 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13205 { 2668 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13206 { 2668 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13207 { 2668 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13208 { 2668 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13209 { 2668 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13210 { 2668 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13211 { 2668 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13212 { 2668 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13213 { 2668 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13214 { 2668 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13215 { 2668 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13216 { 2668 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13217 { 2668 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13218 { 2668 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13219 { 2668 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13220 { 2668 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13221 { 2668 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13222 { 2668 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13223 { 2668 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13224 { 2668 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13225 { 2668 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13226 { 2668 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13227 { 2668 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13228 { 2668 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13229 { 2668 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13230 { 2668 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13231 { 2668 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13232 { 2668 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13233 { 2668 /* vmin */, ARM::MVE_VMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13234 { 2668 /* vmin */, ARM::MVE_VMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13235 { 2668 /* vmin */, ARM::MVE_VMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13236 { 2668 /* vmin */, ARM::MVE_VMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13237 { 2668 /* vmin */, ARM::MVE_VMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13238 { 2668 /* vmin */, ARM::MVE_VMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13239 { 2673 /* vmina */, ARM::MVE_VMINAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13240 { 2673 /* vmina */, ARM::MVE_VMINAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13241 { 2673 /* vmina */, ARM::MVE_VMINAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13242 { 2679 /* vminav */, ARM::MVE_VMINAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13243 { 2679 /* vminav */, ARM::MVE_VMINAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13244 { 2679 /* vminav */, ARM::MVE_VMINAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13245 { 2686 /* vminnm */, ARM::NEON_VMINNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13246 { 2686 /* vminnm */, ARM::NEON_VMINNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13247 { 2686 /* vminnm */, ARM::VFP_VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13248 { 2686 /* vminnm */, ARM::VFP_VMINNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13249 { 2686 /* vminnm */, ARM::NEON_VMINNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13250 { 2686 /* vminnm */, ARM::NEON_VMINNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13251 { 2686 /* vminnm */, ARM::VFP_VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13252 { 2686 /* vminnm */, ARM::MVE_VMINNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13253 { 2686 /* vminnm */, ARM::MVE_VMINNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13254 { 2693 /* vminnma */, ARM::MVE_VMINNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13255 { 2693 /* vminnma */, ARM::MVE_VMINNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13256 { 2701 /* vminnmav */, ARM::MVE_VMINNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13257 { 2701 /* vminnmav */, ARM::MVE_VMINNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13258 { 2710 /* vminnmv */, ARM::MVE_VMINNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13259 { 2710 /* vminnmv */, ARM::MVE_VMINNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13260 { 2718 /* vminv */, ARM::MVE_VMINVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13261 { 2718 /* vminv */, ARM::MVE_VMINVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13262 { 2718 /* vminv */, ARM::MVE_VMINVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13263 { 2718 /* vminv */, ARM::MVE_VMINVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, },
13264 { 2718 /* vminv */, ARM::MVE_VMINVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, },
13265 { 2718 /* vminv */, ARM::MVE_VMINVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, },
13266 { 2724 /* vmla */, ARM::VMLAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13267 { 2724 /* vmla */, ARM::VMLAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13268 { 2724 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13269 { 2724 /* vmla */, ARM::VMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13270 { 2724 /* vmla */, ARM::VMLAv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13271 { 2724 /* vmla */, ARM::VMLAv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13272 { 2724 /* vmla */, ARM::VMLAv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13273 { 2724 /* vmla */, ARM::VMLAv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13274 { 2724 /* vmla */, ARM::VMLAv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13275 { 2724 /* vmla */, ARM::VMLAv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13276 { 2724 /* vmla */, ARM::VMLAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13277 { 2724 /* vmla */, ARM::VMLAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13278 { 2724 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13279 { 2724 /* vmla */, ARM::MVE_VMLA_qr_i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13280 { 2724 /* vmla */, ARM::MVE_VMLA_qr_i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13281 { 2724 /* vmla */, ARM::MVE_VMLA_qr_i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13282 { 2724 /* vmla */, ARM::VMLAslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13283 { 2724 /* vmla */, ARM::VMLAslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13284 { 2724 /* vmla */, ARM::VMLAslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13285 { 2724 /* vmla */, ARM::VMLAslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13286 { 2724 /* vmla */, ARM::VMLAslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13287 { 2724 /* vmla */, ARM::VMLAslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13288 { 2724 /* vmla */, ARM::VMLAslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13289 { 2724 /* vmla */, ARM::VMLAslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13290 { 2729 /* vmladav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13291 { 2729 /* vmladav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13292 { 2729 /* vmladav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13293 { 2729 /* vmladav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13294 { 2729 /* vmladav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13295 { 2729 /* vmladav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13296 { 2737 /* vmladava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13297 { 2737 /* vmladava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13298 { 2737 /* vmladava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13299 { 2737 /* vmladava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13300 { 2737 /* vmladava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13301 { 2737 /* vmladava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13302 { 2746 /* vmladavax */, ARM::MVE_VMLADAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13303 { 2746 /* vmladavax */, ARM::MVE_VMLADAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13304 { 2746 /* vmladavax */, ARM::MVE_VMLADAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13305 { 2756 /* vmladavx */, ARM::MVE_VMLADAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13306 { 2756 /* vmladavx */, ARM::MVE_VMLADAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13307 { 2756 /* vmladavx */, ARM::MVE_VMLADAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13308 { 2765 /* vmlal */, ARM::VMLALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13309 { 2765 /* vmlal */, ARM::VMLALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13310 { 2765 /* vmlal */, ARM::VMLALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13311 { 2765 /* vmlal */, ARM::VMLALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13312 { 2765 /* vmlal */, ARM::VMLALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13313 { 2765 /* vmlal */, ARM::VMLALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13314 { 2765 /* vmlal */, ARM::VMLALslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13315 { 2765 /* vmlal */, ARM::VMLALslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13316 { 2765 /* vmlal */, ARM::VMLALsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13317 { 2765 /* vmlal */, ARM::VMLALsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13318 { 2771 /* vmlaldav */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13319 { 2771 /* vmlaldav */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13320 { 2771 /* vmlaldav */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13321 { 2771 /* vmlaldav */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13322 { 2780 /* vmlaldava */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13323 { 2780 /* vmlaldava */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13324 { 2780 /* vmlaldava */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13325 { 2780 /* vmlaldava */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13326 { 2790 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13327 { 2790 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13328 { 2801 /* vmlaldavx */, ARM::MVE_VMLALDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13329 { 2801 /* vmlaldavx */, ARM::MVE_VMLALDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13330 { 2811 /* vmlalv */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13331 { 2811 /* vmlalv */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13332 { 2811 /* vmlalv */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13333 { 2811 /* vmlalv */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13334 { 2818 /* vmlalva */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13335 { 2818 /* vmlalva */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13336 { 2818 /* vmlalva */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13337 { 2818 /* vmlalva */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13338 { 2826 /* vmlas */, ARM::MVE_VMLAS_qr_i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13339 { 2826 /* vmlas */, ARM::MVE_VMLAS_qr_i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13340 { 2826 /* vmlas */, ARM::MVE_VMLAS_qr_i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13341 { 2832 /* vmlav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13342 { 2832 /* vmlav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13343 { 2832 /* vmlav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13344 { 2832 /* vmlav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13345 { 2832 /* vmlav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13346 { 2832 /* vmlav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13347 { 2838 /* vmlava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13348 { 2838 /* vmlava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13349 { 2838 /* vmlava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13350 { 2838 /* vmlava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13351 { 2838 /* vmlava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13352 { 2838 /* vmlava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13353 { 2845 /* vmls */, ARM::VMLSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13354 { 2845 /* vmls */, ARM::VMLSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13355 { 2845 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13356 { 2845 /* vmls */, ARM::VMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13357 { 2845 /* vmls */, ARM::VMLSv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13358 { 2845 /* vmls */, ARM::VMLSv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13359 { 2845 /* vmls */, ARM::VMLSv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13360 { 2845 /* vmls */, ARM::VMLSv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13361 { 2845 /* vmls */, ARM::VMLSv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13362 { 2845 /* vmls */, ARM::VMLSv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13363 { 2845 /* vmls */, ARM::VMLShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13364 { 2845 /* vmls */, ARM::VMLShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13365 { 2845 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13366 { 2845 /* vmls */, ARM::VMLSslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13367 { 2845 /* vmls */, ARM::VMLSslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13368 { 2845 /* vmls */, ARM::VMLSslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13369 { 2845 /* vmls */, ARM::VMLSslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13370 { 2845 /* vmls */, ARM::VMLSslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13371 { 2845 /* vmls */, ARM::VMLSslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13372 { 2845 /* vmls */, ARM::VMLSslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13373 { 2845 /* vmls */, ARM::VMLSslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13374 { 2850 /* vmlsdav */, ARM::MVE_VMLSDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13375 { 2850 /* vmlsdav */, ARM::MVE_VMLSDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13376 { 2850 /* vmlsdav */, ARM::MVE_VMLSDAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13377 { 2858 /* vmlsdava */, ARM::MVE_VMLSDAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13378 { 2858 /* vmlsdava */, ARM::MVE_VMLSDAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13379 { 2858 /* vmlsdava */, ARM::MVE_VMLSDAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13380 { 2867 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13381 { 2867 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13382 { 2867 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13383 { 2877 /* vmlsdavx */, ARM::MVE_VMLSDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13384 { 2877 /* vmlsdavx */, ARM::MVE_VMLSDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13385 { 2877 /* vmlsdavx */, ARM::MVE_VMLSDAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13386 { 2886 /* vmlsl */, ARM::VMLSLsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13387 { 2886 /* vmlsl */, ARM::VMLSLsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13388 { 2886 /* vmlsl */, ARM::VMLSLsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13389 { 2886 /* vmlsl */, ARM::VMLSLuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13390 { 2886 /* vmlsl */, ARM::VMLSLuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13391 { 2886 /* vmlsl */, ARM::VMLSLuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13392 { 2886 /* vmlsl */, ARM::VMLSLslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13393 { 2886 /* vmlsl */, ARM::VMLSLslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13394 { 2886 /* vmlsl */, ARM::VMLSLsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13395 { 2886 /* vmlsl */, ARM::VMLSLsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13396 { 2892 /* vmlsldav */, ARM::MVE_VMLSLDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13397 { 2892 /* vmlsldav */, ARM::MVE_VMLSLDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13398 { 2901 /* vmlsldava */, ARM::MVE_VMLSLDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13399 { 2901 /* vmlsldava */, ARM::MVE_VMLSLDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13400 { 2911 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13401 { 2911 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13402 { 2922 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13403 { 2922 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13404 { 2932 /* vmmla */, ARM::VMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13405 { 2938 /* vmov */, ARM::VMOVRS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_HPR }, },
13406 { 2938 /* vmov */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
13407 { 2938 /* vmov */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
13408 { 2938 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_GPR }, },
13409 { 2938 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
13410 { 2938 /* vmov */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, },
13411 { 2938 /* vmov */, ARM::VMOVv4f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_FPImm }, },
13412 { 2938 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_NEONi32vmov }, },
13413 { 2938 /* vmov */, ARM::VMOVv2f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_FPImm }, },
13414 { 2938 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_NEONi32vmov }, },
13415 { 2938 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13416 { 2938 /* vmov */, ARM::FCONSTS, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_FPImm }, },
13417 { 2938 /* vmov */, ARM::VMOVD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs64, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13418 { 2938 /* vmov */, ARM::FCONSTD, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_FPImm }, },
13419 { 2938 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16vmovi8Replicate }, },
13420 { 2938 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
13421 { 2938 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16vmovi8Replicate }, },
13422 { 2938 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
13423 { 2938 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi8Replicate }, },
13424 { 2938 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, },
13425 { 2938 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, },
13426 { 2938 /* vmov */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, },
13427 { 2938 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi8Replicate }, },
13428 { 2938 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, },
13429 { 2938 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, },
13430 { 2938 /* vmov */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, },
13431 { 2938 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi8Replicate }, },
13432 { 2938 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, },
13433 { 2938 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, },
13434 { 2938 /* vmov */, ARM::VMOVv2i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64splat }, },
13435 { 2938 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi8Replicate }, },
13436 { 2938 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, },
13437 { 2938 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, },
13438 { 2938 /* vmov */, ARM::VMOVv1i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64splat }, },
13439 { 2938 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_NEONi8splat }, },
13440 { 2938 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_NEONi8splat }, },
13441 { 2938 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_GPR, MCK_HPR }, },
13442 { 2938 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
13443 { 2938 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
13444 { 2938 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_GPR }, },
13445 { 2938 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_HPR }, },
13446 { 2938 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
13447 { 2938 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
13448 { 2938 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_GPR }, },
13449 { 2938 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
13450 { 2938 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
13451 { 2938 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_GPR, MCK_HPR }, },
13452 { 2938 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
13453 { 2938 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
13454 { 2938 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_HPR, MCK_GPR }, },
13455 { 2938 /* vmov */, ARM::VMOVRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_rGPR, MCK_HPR }, },
13456 { 2938 /* vmov */, ARM::VMOVHR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_rGPR }, },
13457 { 2938 /* vmov */, ARM::FCONSTH, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_FPImm }, },
13458 { 2938 /* vmov */, ARM::VMOVRRD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_DPR }, },
13459 { 2938 /* vmov */, ARM::VGETLNi32, Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, },
13460 { 2938 /* vmov */, ARM::VMOVDRR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_GPR, MCK_GPR }, },
13461 { 2938 /* vmov */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, },
13462 { 2938 /* vmov */, ARM::MVE_VMOVimmf32, Convert__Reg1_2__FPImm1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_FPImm }, },
13463 { 2938 /* vmov */, ARM::MVE_VMOVimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13464 { 2938 /* vmov */, ARM::MVE_VMOVimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, },
13465 { 2938 /* vmov */, ARM::MVE_VMOVimmi64, Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i64, MCK_MQPR, MCK_NEONi64splat }, },
13466 { 2938 /* vmov */, ARM::MVE_VMOVimmi8, Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_NEONi8splat }, },
13467 { 2938 /* vmov */, ARM::MVE_VMOV_from_lane_s16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, },
13468 { 2938 /* vmov */, ARM::VGETLNs16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, },
13469 { 2938 /* vmov */, ARM::MVE_VMOV_from_lane_s8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, },
13470 { 2938 /* vmov */, ARM::VGETLNs8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, },
13471 { 2938 /* vmov */, ARM::MVE_VMOV_from_lane_u16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, },
13472 { 2938 /* vmov */, ARM::VGETLNu16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, },
13473 { 2938 /* vmov */, ARM::MVE_VMOV_from_lane_u8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, },
13474 { 2938 /* vmov */, ARM::VGETLNu8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, },
13475 { 2938 /* vmov */, ARM::VMOVRRD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_GPR, MCK_GPR, MCK_DPR }, },
13476 { 2938 /* vmov */, ARM::VMOVDRR, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_GPR, MCK_GPR }, },
13477 { 2938 /* vmov */, ARM::MVE_VMOV_to_lane_16, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_16, MCK_MQPR, MCK_MVEVectorIndex8, MCK_rGPR }, },
13478 { 2938 /* vmov */, ARM::VSETLNi16, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_VectorIndex16, MCK_GPR }, },
13479 { 2938 /* vmov */, ARM::MVE_VMOV_to_lane_32, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_MQPR, MCK_MVEVectorIndex4, MCK_rGPR }, },
13480 { 2938 /* vmov */, ARM::MVE_VMOV_from_lane_32, Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex4 }, },
13481 { 2938 /* vmov */, ARM::VGETLNi32, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, },
13482 { 2938 /* vmov */, ARM::VSETLNi32, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, },
13483 { 2938 /* vmov */, ARM::MVE_VMOV_to_lane_8, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_8, MCK_MQPR, MCK_MVEVectorIndex16, MCK_rGPR }, },
13484 { 2938 /* vmov */, ARM::VSETLNi8, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VectorIndex8, MCK_GPR }, },
13485 { 2938 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, },
13486 { 2938 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, },
13487 { 2938 /* vmov */, ARM::MVE_VMOV_q_rr, Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0, MCK_rGPR, MCK_rGPR }, },
13488 { 2938 /* vmov */, ARM::MVE_VMOV_rr_q, ConvertCustom_cvtMVEVMOVQtoDReg, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0 }, },
13489 { 2943 /* vmovl */, ARM::VMOVLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
13490 { 2943 /* vmovl */, ARM::VMOVLsv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
13491 { 2943 /* vmovl */, ARM::VMOVLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
13492 { 2943 /* vmovl */, ARM::VMOVLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
13493 { 2943 /* vmovl */, ARM::VMOVLuv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
13494 { 2943 /* vmovl */, ARM::VMOVLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
13495 { 2949 /* vmovlb */, ARM::MVE_VMOVLs16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13496 { 2949 /* vmovlb */, ARM::MVE_VMOVLs8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13497 { 2949 /* vmovlb */, ARM::MVE_VMOVLu16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
13498 { 2949 /* vmovlb */, ARM::MVE_VMOVLu8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, },
13499 { 2956 /* vmovlt */, ARM::MVE_VMOVLs16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13500 { 2956 /* vmovlt */, ARM::MVE_VMOVLs8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13501 { 2956 /* vmovlt */, ARM::MVE_VMOVLu16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
13502 { 2956 /* vmovlt */, ARM::MVE_VMOVLu8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, },
13503 { 2963 /* vmovn */, ARM::VMOVNv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR }, },
13504 { 2963 /* vmovn */, ARM::VMOVNv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR }, },
13505 { 2963 /* vmovn */, ARM::VMOVNv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR }, },
13506 { 2969 /* vmovnb */, ARM::MVE_VMOVNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
13507 { 2969 /* vmovnb */, ARM::MVE_VMOVNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
13508 { 2976 /* vmovnt */, ARM::MVE_VMOVNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
13509 { 2976 /* vmovnt */, ARM::MVE_VMOVNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
13510 { 2983 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13511 { 2989 /* vmrs */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_APSR_NZCV, MCK_FPSCR }, },
13512 { 2989 /* vmrs */, ARM::VMRS_FPEXC, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPEXC }, },
13513 { 2989 /* vmrs */, ARM::VMRS_FPINST, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST }, },
13514 { 2989 /* vmrs */, ARM::VMRS_FPINST2, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST2 }, },
13515 { 2989 /* vmrs */, ARM::VMRS, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPRnopc, MCK_FPSCR }, },
13516 { 2989 /* vmrs */, ARM::VMRS_FPSID, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSID }, },
13517 { 2989 /* vmrs */, ARM::VMRS_MVFR0, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR0 }, },
13518 { 2989 /* vmrs */, ARM::VMRS_MVFR1, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR1 }, },
13519 { 2989 /* vmrs */, ARM::VMRS_MVFR2, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR2 }, },
13520 { 2989 /* vmrs */, ARM::VMRS_FPCXTNS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTRegs }, },
13521 { 2989 /* vmrs */, ARM::VMRS_FPCXTS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTS }, },
13522 { 2989 /* vmrs */, ARM::VMRS_FPSCR_NZCVQC, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_FPSCR_NZCVQC }, },
13523 { 2989 /* vmrs */, ARM::VMRS_P0, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_P0 }, },
13524 { 2989 /* vmrs */, ARM::VMRS_VPR, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_VCCR }, },
13525 { 2994 /* vmsr */, ARM::VMSR_FPCXTNS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_GPR }, },
13526 { 2994 /* vmsr */, ARM::VMSR_FPCXTS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_GPR }, },
13527 { 2994 /* vmsr */, ARM::VMSR_FPEXC, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPEXC, MCK_GPRnopc }, },
13528 { 2994 /* vmsr */, ARM::VMSR_FPINST, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST, MCK_GPRnopc }, },
13529 { 2994 /* vmsr */, ARM::VMSR_FPINST2, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST2, MCK_GPRnopc }, },
13530 { 2994 /* vmsr */, ARM::VMSR, Convert__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_FPSCR, MCK_GPRnopc }, },
13531 { 2994 /* vmsr */, ARM::VMSR_FPSCR_NZCVQC, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_GPR }, },
13532 { 2994 /* vmsr */, ARM::VMSR_FPSID, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPSID, MCK_GPRnopc }, },
13533 { 2994 /* vmsr */, ARM::VMSR_P0, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_GPR }, },
13534 { 2994 /* vmsr */, ARM::VMSR_VPR, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_GPR }, },
13535 { 2999 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13536 { 2999 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13537 { 2999 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13538 { 2999 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13539 { 2999 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
13540 { 2999 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
13541 { 2999 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
13542 { 2999 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
13543 { 2999 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
13544 { 2999 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
13545 { 2999 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR }, },
13546 { 2999 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR }, },
13547 { 2999 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13548 { 2999 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13549 { 2999 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13550 { 2999 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13551 { 2999 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13552 { 2999 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13553 { 2999 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13554 { 2999 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13555 { 2999 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13556 { 2999 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13557 { 2999 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13558 { 2999 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13559 { 2999 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13560 { 2999 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13561 { 2999 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13562 { 2999 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13563 { 2999 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13564 { 2999 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13565 { 2999 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13566 { 2999 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13567 { 2999 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13568 { 2999 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13569 { 2999 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13570 { 2999 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13571 { 2999 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13572 { 2999 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13573 { 2999 /* vmul */, ARM::MVE_VMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13574 { 2999 /* vmul */, ARM::MVE_VMUL_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13575 { 2999 /* vmul */, ARM::MVE_VMULi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13576 { 2999 /* vmul */, ARM::MVE_VMUL_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13577 { 2999 /* vmul */, ARM::MVE_VMULi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13578 { 2999 /* vmul */, ARM::MVE_VMUL_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13579 { 2999 /* vmul */, ARM::MVE_VMULi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13580 { 2999 /* vmul */, ARM::MVE_VMUL_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13581 { 2999 /* vmul */, ARM::MVE_VMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13582 { 2999 /* vmul */, ARM::MVE_VMUL_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13583 { 2999 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13584 { 2999 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13585 { 2999 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13586 { 2999 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13587 { 2999 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13588 { 2999 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13589 { 2999 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13590 { 2999 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13591 { 3004 /* vmulh */, ARM::MVE_VMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13592 { 3004 /* vmulh */, ARM::MVE_VMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13593 { 3004 /* vmulh */, ARM::MVE_VMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13594 { 3004 /* vmulh */, ARM::MVE_VMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13595 { 3004 /* vmulh */, ARM::MVE_VMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13596 { 3004 /* vmulh */, ARM::MVE_VMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13597 { 3010 /* vmull */, ARM::VMULLp64, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasAES, { MCK__DOT_p64, MCK_QPR, MCK_DPR, MCK_DPR }, },
13598 { 3010 /* vmull */, ARM::VMULLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13599 { 3010 /* vmull */, ARM::VMULLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13600 { 3010 /* vmull */, ARM::VMULLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13601 { 3010 /* vmull */, ARM::VMULLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13602 { 3010 /* vmull */, ARM::VMULLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13603 { 3010 /* vmull */, ARM::VMULLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13604 { 3010 /* vmull */, ARM::VMULLp8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13605 { 3010 /* vmull */, ARM::VMULLslsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13606 { 3010 /* vmull */, ARM::VMULLslsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13607 { 3010 /* vmull */, ARM::VMULLsluv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13608 { 3010 /* vmull */, ARM::VMULLsluv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13609 { 3016 /* vmullb */, ARM::MVE_VMULLBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13610 { 3016 /* vmullb */, ARM::MVE_VMULLBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13611 { 3016 /* vmullb */, ARM::MVE_VMULLBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13612 { 3016 /* vmullb */, ARM::MVE_VMULLBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13613 { 3016 /* vmullb */, ARM::MVE_VMULLBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13614 { 3016 /* vmullb */, ARM::MVE_VMULLBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13615 { 3016 /* vmullb */, ARM::MVE_VMULLBp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13616 { 3016 /* vmullb */, ARM::MVE_VMULLBp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13617 { 3023 /* vmullt */, ARM::MVE_VMULLTs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13618 { 3023 /* vmullt */, ARM::MVE_VMULLTs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13619 { 3023 /* vmullt */, ARM::MVE_VMULLTs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13620 { 3023 /* vmullt */, ARM::MVE_VMULLTu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13621 { 3023 /* vmullt */, ARM::MVE_VMULLTu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13622 { 3023 /* vmullt */, ARM::MVE_VMULLTu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13623 { 3023 /* vmullt */, ARM::MVE_VMULLTp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13624 { 3023 /* vmullt */, ARM::MVE_VMULLTp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13625 { 3030 /* vmvn */, ARM::VMVNq, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
13626 { 3030 /* vmvn */, ARM::VMVNd, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
13627 { 3030 /* vmvn */, ARM::MVE_VMVN, Convert__Reg1_1__Reg1_2__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, },
13628 { 3030 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16invi8Replicate }, },
13629 { 3030 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
13630 { 3030 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16invi8Replicate }, },
13631 { 3030 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
13632 { 3030 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32invi8Replicate }, },
13633 { 3030 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, },
13634 { 3030 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, },
13635 { 3030 /* vmvn */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, },
13636 { 3030 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32invi8Replicate }, },
13637 { 3030 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, },
13638 { 3030 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, },
13639 { 3030 /* vmvn */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, },
13640 { 3030 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64invi8Replicate }, },
13641 { 3030 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, },
13642 { 3030 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, },
13643 { 3030 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64invi8Replicate }, },
13644 { 3030 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, },
13645 { 3030 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, },
13646 { 3030 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
13647 { 3030 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
13648 { 3030 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
13649 { 3030 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
13650 { 3030 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
13651 { 3030 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
13652 { 3030 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
13653 { 3030 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
13654 { 3030 /* vmvn */, ARM::MVE_VMVNimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13655 { 3030 /* vmvn */, ARM::MVE_VMVNimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, },
13656 { 3035 /* vneg */, ARM::VNEGs16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13657 { 3035 /* vneg */, ARM::VNEGs16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13658 { 3035 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13659 { 3035 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13660 { 3035 /* vneg */, ARM::VNEGs8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13661 { 3035 /* vneg */, ARM::VNEGs8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13662 { 3035 /* vneg */, ARM::VNEGf32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13663 { 3035 /* vneg */, ARM::VNEGfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13664 { 3035 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13665 { 3035 /* vneg */, ARM::VNEGD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13666 { 3035 /* vneg */, ARM::VNEGhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13667 { 3035 /* vneg */, ARM::VNEGhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13668 { 3035 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13669 { 3035 /* vneg */, ARM::MVE_VNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13670 { 3035 /* vneg */, ARM::MVE_VNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13671 { 3035 /* vneg */, ARM::MVE_VNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13672 { 3035 /* vneg */, ARM::MVE_VNEGf32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13673 { 3035 /* vneg */, ARM::MVE_VNEGf16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13674 { 3040 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13675 { 3040 /* vnmla */, ARM::VNMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13676 { 3040 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13677 { 3046 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13678 { 3046 /* vnmls */, ARM::VNMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13679 { 3046 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13680 { 3052 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13681 { 3052 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13682 { 3052 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13683 { 3052 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13684 { 3052 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13685 { 3052 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13686 { 3058 /* vorn */, ARM::VORNq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
13687 { 3058 /* vorn */, ARM::VORNd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
13688 { 3058 /* vorn */, ARM::MVE_VORRimmi16, Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splatNot }, },
13689 { 3058 /* vorn */, ARM::MVE_VORRimmi32, Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splatNot }, },
13690 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13691 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13692 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13693 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13694 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13695 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13696 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13697 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13698 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13699 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13700 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13701 { 3058 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13702 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
13703 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
13704 { 3063 /* vorr */, ARM::VORRiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
13705 { 3063 /* vorr */, ARM::VORRiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
13706 { 3063 /* vorr */, ARM::VORRiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, },
13707 { 3063 /* vorr */, ARM::VORRiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, },
13708 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
13709 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
13710 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
13711 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
13712 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
13713 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
13714 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
13715 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
13716 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
13717 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
13718 { 3063 /* vorr */, ARM::MVE_VORRimmi16, Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13719 { 3063 /* vorr */, ARM::MVE_VORRimmi32, Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splat }, },
13720 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13721 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13722 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13723 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13724 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13725 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
13726 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13727 { 3063 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13728 { 3063 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13729 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13730 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13731 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13732 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13733 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13734 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13735 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13736 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13737 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13738 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13739 { 3063 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13740 { 3068 /* vpadal */, ARM::VPADALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13741 { 3068 /* vpadal */, ARM::VPADALsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13742 { 3068 /* vpadal */, ARM::VPADALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13743 { 3068 /* vpadal */, ARM::VPADALsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13744 { 3068 /* vpadal */, ARM::VPADALsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13745 { 3068 /* vpadal */, ARM::VPADALsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13746 { 3068 /* vpadal */, ARM::VPADALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13747 { 3068 /* vpadal */, ARM::VPADALuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13748 { 3068 /* vpadal */, ARM::VPADALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13749 { 3068 /* vpadal */, ARM::VPADALuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13750 { 3068 /* vpadal */, ARM::VPADALuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13751 { 3068 /* vpadal */, ARM::VPADALuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13752 { 3075 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13753 { 3075 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
13754 { 3075 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
13755 { 3075 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
13756 { 3075 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13757 { 3075 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13758 { 3075 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13759 { 3075 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13760 { 3075 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13761 { 3075 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13762 { 3081 /* vpaddl */, ARM::VPADDLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13763 { 3081 /* vpaddl */, ARM::VPADDLsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13764 { 3081 /* vpaddl */, ARM::VPADDLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13765 { 3081 /* vpaddl */, ARM::VPADDLsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13766 { 3081 /* vpaddl */, ARM::VPADDLsv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13767 { 3081 /* vpaddl */, ARM::VPADDLsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13768 { 3081 /* vpaddl */, ARM::VPADDLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13769 { 3081 /* vpaddl */, ARM::VPADDLuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13770 { 3081 /* vpaddl */, ARM::VPADDLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13771 { 3081 /* vpaddl */, ARM::VPADDLuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13772 { 3081 /* vpaddl */, ARM::VPADDLuv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13773 { 3081 /* vpaddl */, ARM::VPADDLuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13774 { 3088 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13775 { 3088 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13776 { 3088 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13777 { 3088 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13778 { 3088 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13779 { 3088 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13780 { 3088 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13781 { 3088 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13782 { 3088 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13783 { 3088 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13784 { 3088 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13785 { 3088 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13786 { 3088 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13787 { 3088 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13788 { 3088 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13789 { 3088 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13790 { 3094 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13791 { 3094 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13792 { 3094 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13793 { 3094 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13794 { 3094 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13795 { 3094 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13796 { 3094 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13797 { 3094 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13798 { 3094 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13799 { 3094 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13800 { 3094 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13801 { 3094 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13802 { 3094 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13803 { 3094 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13804 { 3094 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13805 { 3094 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13806 { 3100 /* vpnot */, ARM::MVE_VPNOT, Convert__imm_95_0__imm_95_0__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN }, },
13807 { 3106 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, },
13808 { 3106 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, },
13809 { 3106 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, },
13810 { 3106 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, },
13811 { 3106 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, },
13812 { 3106 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, },
13813 { 3106 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, },
13814 { 3106 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, },
13815 { 3106 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, },
13816 { 3106 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, },
13817 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13818 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13819 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13820 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13821 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13822 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13823 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13824 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13825 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13826 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13827 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13828 { 3111 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13829 { 3117 /* vpst */, ARM::MVE_VPST, Convert__ITMask1_0, AMFBS_HasMVEInt, { MCK_ITMask }, },
13830 { 3122 /* vpt */, ARM::MVE_VPTv8s16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
13831 { 3122 /* vpt */, ARM::MVE_VPTv8s16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
13832 { 3122 /* vpt */, ARM::MVE_VPTv4s32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
13833 { 3122 /* vpt */, ARM::MVE_VPTv4s32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
13834 { 3122 /* vpt */, ARM::MVE_VPTv16s8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
13835 { 3122 /* vpt */, ARM::MVE_VPTv16s8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
13836 { 3122 /* vpt */, ARM::MVE_VPTv8u16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
13837 { 3122 /* vpt */, ARM::MVE_VPTv8u16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
13838 { 3122 /* vpt */, ARM::MVE_VPTv4u32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
13839 { 3122 /* vpt */, ARM::MVE_VPTv4u32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
13840 { 3122 /* vpt */, ARM::MVE_VPTv16u8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
13841 { 3122 /* vpt */, ARM::MVE_VPTv16u8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
13842 { 3122 /* vpt */, ARM::MVE_VPTv4f32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
13843 { 3122 /* vpt */, ARM::MVE_VPTv4f32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
13844 { 3122 /* vpt */, ARM::MVE_VPTv8i16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
13845 { 3122 /* vpt */, ARM::MVE_VPTv8i16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
13846 { 3122 /* vpt */, ARM::MVE_VPTv4i32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
13847 { 3122 /* vpt */, ARM::MVE_VPTv4i32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
13848 { 3122 /* vpt */, ARM::MVE_VPTv16i8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
13849 { 3122 /* vpt */, ARM::MVE_VPTv16i8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
13850 { 3122 /* vpt */, ARM::MVE_VPTv8f16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
13851 { 3122 /* vpt */, ARM::MVE_VPTv8f16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
13852 { 3126 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, },
13853 { 3126 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, },
13854 { 3126 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, },
13855 { 3126 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, },
13856 { 3126 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, },
13857 { 3126 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, },
13858 { 3126 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, },
13859 { 3126 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, },
13860 { 3126 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, },
13861 { 3126 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, },
13862 { 3132 /* vqabs */, ARM::VQABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13863 { 3132 /* vqabs */, ARM::VQABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13864 { 3132 /* vqabs */, ARM::VQABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13865 { 3132 /* vqabs */, ARM::VQABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13866 { 3132 /* vqabs */, ARM::VQABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13867 { 3132 /* vqabs */, ARM::VQABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13868 { 3132 /* vqabs */, ARM::MVE_VQABSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13869 { 3132 /* vqabs */, ARM::MVE_VQABSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13870 { 3132 /* vqabs */, ARM::MVE_VQABSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13871 { 3138 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13872 { 3138 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13873 { 3138 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13874 { 3138 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13875 { 3138 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
13876 { 3138 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
13877 { 3138 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13878 { 3138 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13879 { 3138 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13880 { 3138 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13881 { 3138 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13882 { 3138 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13883 { 3138 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
13884 { 3138 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
13885 { 3138 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13886 { 3138 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13887 { 3138 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13888 { 3138 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13889 { 3138 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13890 { 3138 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13891 { 3138 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
13892 { 3138 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13893 { 3138 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13894 { 3138 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13895 { 3138 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13896 { 3138 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13897 { 3138 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13898 { 3138 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13899 { 3138 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
13900 { 3138 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13901 { 3138 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13902 { 3138 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13903 { 3138 /* vqadd */, ARM::MVE_VQADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13904 { 3138 /* vqadd */, ARM::MVE_VQADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13905 { 3138 /* vqadd */, ARM::MVE_VQADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13906 { 3138 /* vqadd */, ARM::MVE_VQADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13907 { 3138 /* vqadd */, ARM::MVE_VQADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13908 { 3138 /* vqadd */, ARM::MVE_VQADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13909 { 3138 /* vqadd */, ARM::MVE_VQADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13910 { 3138 /* vqadd */, ARM::MVE_VQADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13911 { 3138 /* vqadd */, ARM::MVE_VQADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13912 { 3138 /* vqadd */, ARM::MVE_VQADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13913 { 3138 /* vqadd */, ARM::MVE_VQADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13914 { 3138 /* vqadd */, ARM::MVE_VQADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13915 { 3144 /* vqdmladh */, ARM::MVE_VQDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13916 { 3144 /* vqdmladh */, ARM::MVE_VQDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13917 { 3144 /* vqdmladh */, ARM::MVE_VQDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13918 { 3153 /* vqdmladhx */, ARM::MVE_VQDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13919 { 3153 /* vqdmladhx */, ARM::MVE_VQDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13920 { 3153 /* vqdmladhx */, ARM::MVE_VQDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13921 { 3163 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13922 { 3163 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13923 { 3163 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13924 { 3171 /* vqdmlal */, ARM::VQDMLALv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13925 { 3171 /* vqdmlal */, ARM::VQDMLALv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13926 { 3171 /* vqdmlal */, ARM::VQDMLALslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13927 { 3171 /* vqdmlal */, ARM::VQDMLALslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13928 { 3179 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13929 { 3179 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13930 { 3179 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13931 { 3188 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13932 { 3188 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13933 { 3188 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13934 { 3197 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13935 { 3197 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13936 { 3197 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13937 { 3207 /* vqdmlsl */, ARM::VQDMLSLv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13938 { 3207 /* vqdmlsl */, ARM::VQDMLSLv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13939 { 3207 /* vqdmlsl */, ARM::VQDMLSLslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13940 { 3207 /* vqdmlsl */, ARM::VQDMLSLslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13941 { 3215 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13942 { 3215 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13943 { 3215 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13944 { 3215 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13945 { 3215 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13946 { 3215 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13947 { 3215 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13948 { 3215 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13949 { 3215 /* vqdmulh */, ARM::MVE_VQDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13950 { 3215 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13951 { 3215 /* vqdmulh */, ARM::MVE_VQDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13952 { 3215 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13953 { 3215 /* vqdmulh */, ARM::MVE_VQDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13954 { 3215 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13955 { 3215 /* vqdmulh */, ARM::VQDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13956 { 3215 /* vqdmulh */, ARM::VQDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13957 { 3215 /* vqdmulh */, ARM::VQDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13958 { 3215 /* vqdmulh */, ARM::VQDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13959 { 3223 /* vqdmull */, ARM::VQDMULLv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13960 { 3223 /* vqdmull */, ARM::VQDMULLv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13961 { 3223 /* vqdmull */, ARM::VQDMULLslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13962 { 3223 /* vqdmull */, ARM::VQDMULLslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13963 { 3231 /* vqdmullb */, ARM::MVE_VQDMULLs16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13964 { 3231 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13965 { 3231 /* vqdmullb */, ARM::MVE_VQDMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13966 { 3231 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13967 { 3240 /* vqdmullt */, ARM::MVE_VQDMULLs16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13968 { 3240 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13969 { 3240 /* vqdmullt */, ARM::MVE_VQDMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13970 { 3240 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13971 { 3249 /* vqmovn */, ARM::VQMOVNsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, },
13972 { 3249 /* vqmovn */, ARM::VQMOVNsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
13973 { 3249 /* vqmovn */, ARM::VQMOVNsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, },
13974 { 3249 /* vqmovn */, ARM::VQMOVNuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR }, },
13975 { 3249 /* vqmovn */, ARM::VQMOVNuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR }, },
13976 { 3249 /* vqmovn */, ARM::VQMOVNuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR }, },
13977 { 3256 /* vqmovnb */, ARM::MVE_VQMOVNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13978 { 3256 /* vqmovnb */, ARM::MVE_VQMOVNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13979 { 3256 /* vqmovnb */, ARM::MVE_VQMOVNu16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
13980 { 3256 /* vqmovnb */, ARM::MVE_VQMOVNu32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
13981 { 3264 /* vqmovnt */, ARM::MVE_VQMOVNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13982 { 3264 /* vqmovnt */, ARM::MVE_VQMOVNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13983 { 3264 /* vqmovnt */, ARM::MVE_VQMOVNu16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
13984 { 3264 /* vqmovnt */, ARM::MVE_VQMOVNu32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
13985 { 3272 /* vqmovun */, ARM::VQMOVNsuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, },
13986 { 3272 /* vqmovun */, ARM::VQMOVNsuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
13987 { 3272 /* vqmovun */, ARM::VQMOVNsuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, },
13988 { 3280 /* vqmovunb */, ARM::MVE_VQMOVUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13989 { 3280 /* vqmovunb */, ARM::MVE_VQMOVUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13990 { 3289 /* vqmovunt */, ARM::MVE_VQMOVUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13991 { 3289 /* vqmovunt */, ARM::MVE_VQMOVUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13992 { 3298 /* vqneg */, ARM::VQNEGv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13993 { 3298 /* vqneg */, ARM::VQNEGv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13994 { 3298 /* vqneg */, ARM::VQNEGv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13995 { 3298 /* vqneg */, ARM::VQNEGv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13996 { 3298 /* vqneg */, ARM::VQNEGv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13997 { 3298 /* vqneg */, ARM::VQNEGv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13998 { 3298 /* vqneg */, ARM::MVE_VQNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13999 { 3298 /* vqneg */, ARM::MVE_VQNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14000 { 3298 /* vqneg */, ARM::MVE_VQNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
14001 { 3304 /* vqrdmladh */, ARM::MVE_VQRDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14002 { 3304 /* vqrdmladh */, ARM::MVE_VQRDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14003 { 3304 /* vqrdmladh */, ARM::MVE_VQRDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14004 { 3314 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14005 { 3314 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14006 { 3314 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14007 { 3325 /* vqrdmlah */, ARM::VQRDMLAHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14008 { 3325 /* vqrdmlah */, ARM::VQRDMLAHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14009 { 3325 /* vqrdmlah */, ARM::VQRDMLAHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14010 { 3325 /* vqrdmlah */, ARM::VQRDMLAHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14011 { 3325 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14012 { 3325 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14013 { 3325 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14014 { 3325 /* vqrdmlah */, ARM::VQRDMLAHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14015 { 3325 /* vqrdmlah */, ARM::VQRDMLAHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14016 { 3325 /* vqrdmlah */, ARM::VQRDMLAHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14017 { 3325 /* vqrdmlah */, ARM::VQRDMLAHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14018 { 3334 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14019 { 3334 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14020 { 3334 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14021 { 3344 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14022 { 3344 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14023 { 3344 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14024 { 3354 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14025 { 3354 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14026 { 3354 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14027 { 3365 /* vqrdmlsh */, ARM::VQRDMLSHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14028 { 3365 /* vqrdmlsh */, ARM::VQRDMLSHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14029 { 3365 /* vqrdmlsh */, ARM::VQRDMLSHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14030 { 3365 /* vqrdmlsh */, ARM::VQRDMLSHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14031 { 3365 /* vqrdmlsh */, ARM::VQRDMLSHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14032 { 3365 /* vqrdmlsh */, ARM::VQRDMLSHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14033 { 3365 /* vqrdmlsh */, ARM::VQRDMLSHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14034 { 3365 /* vqrdmlsh */, ARM::VQRDMLSHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14035 { 3374 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14036 { 3374 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14037 { 3374 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14038 { 3374 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14039 { 3374 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14040 { 3374 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14041 { 3374 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14042 { 3374 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14043 { 3374 /* vqrdmulh */, ARM::MVE_VQRDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14044 { 3374 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14045 { 3374 /* vqrdmulh */, ARM::MVE_VQRDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14046 { 3374 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14047 { 3374 /* vqrdmulh */, ARM::MVE_VQRDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14048 { 3374 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14049 { 3374 /* vqrdmulh */, ARM::VQRDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14050 { 3374 /* vqrdmulh */, ARM::VQRDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14051 { 3374 /* vqrdmulh */, ARM::VQRDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14052 { 3374 /* vqrdmulh */, ARM::VQRDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14053 { 3383 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14054 { 3383 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14055 { 3383 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14056 { 3383 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14057 { 3383 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14058 { 3383 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14059 { 3383 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14060 { 3383 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14061 { 3383 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14062 { 3383 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14063 { 3383 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14064 { 3383 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14065 { 3383 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14066 { 3383 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14067 { 3383 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14068 { 3383 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14069 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14070 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14071 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14072 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14073 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14074 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14075 { 3383 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14076 { 3383 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14077 { 3383 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14078 { 3383 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14079 { 3383 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14080 { 3383 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14081 { 3383 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14082 { 3383 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14083 { 3383 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14084 { 3383 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14085 { 3383 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14086 { 3383 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14087 { 3383 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14088 { 3383 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14089 { 3383 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14090 { 3383 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14091 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14092 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14093 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14094 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14095 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14096 { 3383 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14097 { 3390 /* vqrshrn */, ARM::VQRSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14098 { 3390 /* vqrshrn */, ARM::VQRSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14099 { 3390 /* vqrshrn */, ARM::VQRSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14100 { 3390 /* vqrshrn */, ARM::VQRSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14101 { 3390 /* vqrshrn */, ARM::VQRSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14102 { 3390 /* vqrshrn */, ARM::VQRSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14103 { 3398 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14104 { 3398 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14105 { 3398 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14106 { 3398 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14107 { 3407 /* vqrshrnt */, ARM::MVE_VQRSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14108 { 3407 /* vqrshrnt */, ARM::MVE_VQRSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14109 { 3407 /* vqrshrnt */, ARM::MVE_VQRSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14110 { 3407 /* vqrshrnt */, ARM::MVE_VQRSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14111 { 3416 /* vqrshrun */, ARM::VQRSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14112 { 3416 /* vqrshrun */, ARM::VQRSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14113 { 3416 /* vqrshrun */, ARM::VQRSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14114 { 3425 /* vqrshrunb */, ARM::MVE_VQRSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14115 { 3425 /* vqrshrunb */, ARM::MVE_VQRSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14116 { 3435 /* vqrshrunt */, ARM::MVE_VQRSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14117 { 3435 /* vqrshrunt */, ARM::MVE_VQRSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14118 { 3445 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14119 { 3445 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, },
14120 { 3445 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14121 { 3445 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, },
14122 { 3445 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14123 { 3445 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
14124 { 3445 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14125 { 3445 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
14126 { 3445 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14127 { 3445 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, },
14128 { 3445 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14129 { 3445 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, },
14130 { 3445 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14131 { 3445 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, },
14132 { 3445 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14133 { 3445 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, },
14134 { 3445 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14135 { 3445 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_Imm }, },
14136 { 3445 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14137 { 3445 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_Imm }, },
14138 { 3445 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14139 { 3445 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_Imm }, },
14140 { 3445 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14141 { 3445 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_Imm }, },
14142 { 3445 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14143 { 3445 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_Imm }, },
14144 { 3445 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14145 { 3445 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_Imm }, },
14146 { 3445 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14147 { 3445 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_Imm }, },
14148 { 3445 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14149 { 3445 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_Imm }, },
14150 { 3445 /* vqshl */, ARM::MVE_VQSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14151 { 3445 /* vqshl */, ARM::MVE_VQSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14152 { 3445 /* vqshl */, ARM::MVE_VQSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14153 { 3445 /* vqshl */, ARM::MVE_VQSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14154 { 3445 /* vqshl */, ARM::MVE_VQSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14155 { 3445 /* vqshl */, ARM::MVE_VQSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14156 { 3445 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14157 { 3445 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14158 { 3445 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14159 { 3445 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14160 { 3445 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14161 { 3445 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14162 { 3445 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14163 { 3445 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14164 { 3445 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14165 { 3445 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14166 { 3445 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14167 { 3445 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14168 { 3445 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14169 { 3445 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14170 { 3445 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14171 { 3445 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14172 { 3445 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14173 { 3445 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14174 { 3445 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14175 { 3445 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14176 { 3445 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14177 { 3445 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14178 { 3445 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14179 { 3445 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14180 { 3445 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14181 { 3445 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14182 { 3445 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14183 { 3445 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14184 { 3445 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14185 { 3445 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14186 { 3445 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14187 { 3445 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14188 { 3445 /* vqshl */, ARM::MVE_VQSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14189 { 3445 /* vqshl */, ARM::MVE_VQSHLimms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14190 { 3445 /* vqshl */, ARM::MVE_VQSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14191 { 3445 /* vqshl */, ARM::MVE_VQSHLimms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14192 { 3445 /* vqshl */, ARM::MVE_VQSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14193 { 3445 /* vqshl */, ARM::MVE_VQSHLimms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14194 { 3445 /* vqshl */, ARM::MVE_VQSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14195 { 3445 /* vqshl */, ARM::MVE_VQSHLimmu16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14196 { 3445 /* vqshl */, ARM::MVE_VQSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14197 { 3445 /* vqshl */, ARM::MVE_VQSHLimmu32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14198 { 3445 /* vqshl */, ARM::MVE_VQSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14199 { 3445 /* vqshl */, ARM::MVE_VQSHLimmu8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14200 { 3451 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, },
14201 { 3451 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, },
14202 { 3451 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
14203 { 3451 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
14204 { 3451 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, },
14205 { 3451 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, },
14206 { 3451 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, },
14207 { 3451 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, },
14208 { 3451 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14209 { 3451 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14210 { 3451 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14211 { 3451 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14212 { 3451 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14213 { 3451 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14214 { 3451 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14215 { 3451 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14216 { 3451 /* vqshlu */, ARM::MVE_VQSHLU_imms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14217 { 3451 /* vqshlu */, ARM::MVE_VQSHLU_imms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14218 { 3451 /* vqshlu */, ARM::MVE_VQSHLU_imms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14219 { 3458 /* vqshrn */, ARM::VQSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14220 { 3458 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14221 { 3458 /* vqshrn */, ARM::VQSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14222 { 3458 /* vqshrn */, ARM::VQSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14223 { 3458 /* vqshrn */, ARM::VQSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14224 { 3458 /* vqshrn */, ARM::VQSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14225 { 3465 /* vqshrnb */, ARM::MVE_VQSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14226 { 3465 /* vqshrnb */, ARM::MVE_VQSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14227 { 3465 /* vqshrnb */, ARM::MVE_VQSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14228 { 3465 /* vqshrnb */, ARM::MVE_VQSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14229 { 3473 /* vqshrnt */, ARM::MVE_VQSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14230 { 3473 /* vqshrnt */, ARM::MVE_VQSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14231 { 3473 /* vqshrnt */, ARM::MVE_VQSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14232 { 3473 /* vqshrnt */, ARM::MVE_VQSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14233 { 3481 /* vqshrun */, ARM::VQSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14234 { 3481 /* vqshrun */, ARM::VQSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14235 { 3481 /* vqshrun */, ARM::VQSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14236 { 3489 /* vqshrunb */, ARM::MVE_VQSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14237 { 3489 /* vqshrunb */, ARM::MVE_VQSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14238 { 3498 /* vqshrunt */, ARM::MVE_VQSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14239 { 3498 /* vqshrunt */, ARM::MVE_VQSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14240 { 3507 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14241 { 3507 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14242 { 3507 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14243 { 3507 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14244 { 3507 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14245 { 3507 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14246 { 3507 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14247 { 3507 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14248 { 3507 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14249 { 3507 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14250 { 3507 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14251 { 3507 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14252 { 3507 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14253 { 3507 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14254 { 3507 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14255 { 3507 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14256 { 3507 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14257 { 3507 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14258 { 3507 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14259 { 3507 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14260 { 3507 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14261 { 3507 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14262 { 3507 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14263 { 3507 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14264 { 3507 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14265 { 3507 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14266 { 3507 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14267 { 3507 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14268 { 3507 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14269 { 3507 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14270 { 3507 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14271 { 3507 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14272 { 3507 /* vqsub */, ARM::MVE_VQSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14273 { 3507 /* vqsub */, ARM::MVE_VQSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14274 { 3507 /* vqsub */, ARM::MVE_VQSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14275 { 3507 /* vqsub */, ARM::MVE_VQSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14276 { 3507 /* vqsub */, ARM::MVE_VQSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14277 { 3507 /* vqsub */, ARM::MVE_VQSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14278 { 3507 /* vqsub */, ARM::MVE_VQSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14279 { 3507 /* vqsub */, ARM::MVE_VQSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14280 { 3507 /* vqsub */, ARM::MVE_VQSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14281 { 3507 /* vqsub */, ARM::MVE_VQSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14282 { 3507 /* vqsub */, ARM::MVE_VQSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14283 { 3507 /* vqsub */, ARM::MVE_VQSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14284 { 3513 /* vraddhn */, ARM::VRADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
14285 { 3513 /* vraddhn */, ARM::VRADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
14286 { 3513 /* vraddhn */, ARM::VRADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
14287 { 3521 /* vrecpe */, ARM::VRECPEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14288 { 3521 /* vrecpe */, ARM::VRECPEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14289 { 3521 /* vrecpe */, ARM::VRECPEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14290 { 3521 /* vrecpe */, ARM::VRECPEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14291 { 3521 /* vrecpe */, ARM::VRECPEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14292 { 3521 /* vrecpe */, ARM::VRECPEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14293 { 3528 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14294 { 3528 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14295 { 3528 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14296 { 3528 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14297 { 3528 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14298 { 3528 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14299 { 3528 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14300 { 3528 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14301 { 3535 /* vrev16 */, ARM::VREV16q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14302 { 3535 /* vrev16 */, ARM::VREV16d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14303 { 3535 /* vrev16 */, ARM::MVE_VREV16_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14304 { 3542 /* vrev32 */, ARM::VREV32q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
14305 { 3542 /* vrev32 */, ARM::VREV32d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
14306 { 3542 /* vrev32 */, ARM::VREV32q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14307 { 3542 /* vrev32 */, ARM::VREV32d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14308 { 3542 /* vrev32 */, ARM::MVE_VREV32_16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, },
14309 { 3542 /* vrev32 */, ARM::MVE_VREV32_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14310 { 3549 /* vrev64 */, ARM::VREV64q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
14311 { 3549 /* vrev64 */, ARM::VREV64d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
14312 { 3549 /* vrev64 */, ARM::VREV64q32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
14313 { 3549 /* vrev64 */, ARM::VREV64d32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
14314 { 3549 /* vrev64 */, ARM::VREV64q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14315 { 3549 /* vrev64 */, ARM::VREV64d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14316 { 3549 /* vrev64 */, ARM::MVE_VREV64_16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, },
14317 { 3549 /* vrev64 */, ARM::MVE_VREV64_32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR }, },
14318 { 3549 /* vrev64 */, ARM::MVE_VREV64_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14319 { 3556 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14320 { 3556 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14321 { 3556 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14322 { 3556 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14323 { 3556 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14324 { 3556 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14325 { 3556 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14326 { 3556 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14327 { 3556 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14328 { 3556 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14329 { 3556 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14330 { 3556 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14331 { 3556 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14332 { 3556 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14333 { 3556 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14334 { 3556 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14335 { 3556 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14336 { 3556 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14337 { 3556 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14338 { 3556 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14339 { 3556 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14340 { 3556 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14341 { 3556 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14342 { 3556 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14343 { 3556 /* vrhadd */, ARM::MVE_VRHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14344 { 3556 /* vrhadd */, ARM::MVE_VRHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14345 { 3556 /* vrhadd */, ARM::MVE_VRHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14346 { 3556 /* vrhadd */, ARM::MVE_VRHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14347 { 3556 /* vrhadd */, ARM::MVE_VRHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14348 { 3556 /* vrhadd */, ARM::MVE_VRHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14349 { 3563 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14350 { 3563 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14351 { 3563 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14352 { 3563 /* vrinta */, ARM::VRINTAD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14353 { 3563 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14354 { 3563 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14355 { 3563 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14356 { 3563 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14357 { 3563 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14358 { 3563 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14359 { 3563 /* vrinta */, ARM::VRINTAD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14360 { 3563 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14361 { 3563 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14362 { 3563 /* vrinta */, ARM::VRINTAH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14363 { 3563 /* vrinta */, ARM::MVE_VRINTf32A, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14364 { 3563 /* vrinta */, ARM::MVE_VRINTf16A, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14365 { 3570 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14366 { 3570 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14367 { 3570 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14368 { 3570 /* vrintm */, ARM::VRINTMD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14369 { 3570 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14370 { 3570 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14371 { 3570 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14372 { 3570 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14373 { 3570 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14374 { 3570 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14375 { 3570 /* vrintm */, ARM::VRINTMD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14376 { 3570 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14377 { 3570 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14378 { 3570 /* vrintm */, ARM::VRINTMH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14379 { 3570 /* vrintm */, ARM::MVE_VRINTf32M, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14380 { 3570 /* vrintm */, ARM::MVE_VRINTf16M, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14381 { 3577 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14382 { 3577 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14383 { 3577 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14384 { 3577 /* vrintn */, ARM::VRINTND, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14385 { 3577 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14386 { 3577 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14387 { 3577 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14388 { 3577 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14389 { 3577 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14390 { 3577 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14391 { 3577 /* vrintn */, ARM::VRINTND, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14392 { 3577 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14393 { 3577 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14394 { 3577 /* vrintn */, ARM::VRINTNH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14395 { 3577 /* vrintn */, ARM::MVE_VRINTf32N, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14396 { 3577 /* vrintn */, ARM::MVE_VRINTf16N, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14397 { 3584 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14398 { 3584 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14399 { 3584 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14400 { 3584 /* vrintp */, ARM::VRINTPD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14401 { 3584 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14402 { 3584 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14403 { 3584 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14404 { 3584 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14405 { 3584 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14406 { 3584 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14407 { 3584 /* vrintp */, ARM::VRINTPD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14408 { 3584 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14409 { 3584 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14410 { 3584 /* vrintp */, ARM::VRINTPH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14411 { 3584 /* vrintp */, ARM::MVE_VRINTf32P, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14412 { 3584 /* vrintp */, ARM::MVE_VRINTf16P, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14413 { 3591 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14414 { 3591 /* vrintr */, ARM::VRINTRD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14415 { 3591 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14416 { 3591 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14417 { 3591 /* vrintr */, ARM::VRINTRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14418 { 3591 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14419 { 3598 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14420 { 3598 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14421 { 3598 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14422 { 3598 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14423 { 3598 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14424 { 3598 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14425 { 3598 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14426 { 3598 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14427 { 3598 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14428 { 3598 /* vrintx */, ARM::VRINTXD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14429 { 3598 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14430 { 3598 /* vrintx */, ARM::MVE_VRINTf32X, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14431 { 3598 /* vrintx */, ARM::MVE_VRINTf16X, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14432 { 3598 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14433 { 3598 /* vrintx */, ARM::VRINTXD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14434 { 3598 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14435 { 3605 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14436 { 3605 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14437 { 3605 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14438 { 3605 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14439 { 3605 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14440 { 3605 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14441 { 3605 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14442 { 3605 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14443 { 3605 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14444 { 3605 /* vrintz */, ARM::VRINTZD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14445 { 3605 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14446 { 3605 /* vrintz */, ARM::MVE_VRINTf32Z, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14447 { 3605 /* vrintz */, ARM::MVE_VRINTf16Z, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14448 { 3605 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14449 { 3605 /* vrintz */, ARM::VRINTZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14450 { 3605 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14451 { 3612 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14452 { 3612 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14453 { 3623 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14454 { 3623 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14455 { 3635 /* vrmlaldavhax */, ARM::MVE_VRMLALDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14456 { 3648 /* vrmlaldavhx */, ARM::MVE_VRMLALDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14457 { 3660 /* vrmlalvh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14458 { 3660 /* vrmlalvh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14459 { 3669 /* vrmlalvha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14460 { 3669 /* vrmlalvha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14461 { 3679 /* vrmlsldavh */, ARM::MVE_VRMLSLDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14462 { 3690 /* vrmlsldavha */, ARM::MVE_VRMLSLDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14463 { 3702 /* vrmlsldavhax */, ARM::MVE_VRMLSLDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14464 { 3715 /* vrmlsldavhx */, ARM::MVE_VRMLSLDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14465 { 3727 /* vrmulh */, ARM::MVE_VRMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14466 { 3727 /* vrmulh */, ARM::MVE_VRMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14467 { 3727 /* vrmulh */, ARM::MVE_VRMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14468 { 3727 /* vrmulh */, ARM::MVE_VRMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14469 { 3727 /* vrmulh */, ARM::MVE_VRMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14470 { 3727 /* vrmulh */, ARM::MVE_VRMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14471 { 3734 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14472 { 3734 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14473 { 3734 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14474 { 3734 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14475 { 3734 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14476 { 3734 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14477 { 3734 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14478 { 3734 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14479 { 3734 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14480 { 3734 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14481 { 3734 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14482 { 3734 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14483 { 3734 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14484 { 3734 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14485 { 3734 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14486 { 3734 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14487 { 3734 /* vrshl */, ARM::MVE_VRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14488 { 3734 /* vrshl */, ARM::MVE_VRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14489 { 3734 /* vrshl */, ARM::MVE_VRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14490 { 3734 /* vrshl */, ARM::MVE_VRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14491 { 3734 /* vrshl */, ARM::MVE_VRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14492 { 3734 /* vrshl */, ARM::MVE_VRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14493 { 3734 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14494 { 3734 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14495 { 3734 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14496 { 3734 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14497 { 3734 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14498 { 3734 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14499 { 3734 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14500 { 3734 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14501 { 3734 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14502 { 3734 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14503 { 3734 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14504 { 3734 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14505 { 3734 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14506 { 3734 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14507 { 3734 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14508 { 3734 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14509 { 3734 /* vrshl */, ARM::MVE_VRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14510 { 3734 /* vrshl */, ARM::MVE_VRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14511 { 3734 /* vrshl */, ARM::MVE_VRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14512 { 3734 /* vrshl */, ARM::MVE_VRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14513 { 3734 /* vrshl */, ARM::MVE_VRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14514 { 3734 /* vrshl */, ARM::MVE_VRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14515 { 3740 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
14516 { 3740 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
14517 { 3740 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14518 { 3740 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14519 { 3740 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
14520 { 3740 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
14521 { 3740 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
14522 { 3740 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
14523 { 3740 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
14524 { 3740 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
14525 { 3740 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
14526 { 3740 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
14527 { 3740 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
14528 { 3740 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
14529 { 3740 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
14530 { 3740 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
14531 { 3740 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14532 { 3740 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14533 { 3740 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14534 { 3740 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14535 { 3740 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14536 { 3740 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14537 { 3740 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14538 { 3740 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14539 { 3740 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14540 { 3740 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14541 { 3740 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14542 { 3740 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14543 { 3740 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14544 { 3740 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14545 { 3740 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14546 { 3740 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14547 { 3740 /* vrshr */, ARM::MVE_VRSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14548 { 3740 /* vrshr */, ARM::MVE_VRSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14549 { 3740 /* vrshr */, ARM::MVE_VRSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14550 { 3740 /* vrshr */, ARM::MVE_VRSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14551 { 3740 /* vrshr */, ARM::MVE_VRSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14552 { 3740 /* vrshr */, ARM::MVE_VRSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14553 { 3746 /* vrshrn */, ARM::VRSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14554 { 3746 /* vrshrn */, ARM::VRSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14555 { 3746 /* vrshrn */, ARM::VRSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14556 { 3753 /* vrshrnb */, ARM::MVE_VRSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14557 { 3753 /* vrshrnb */, ARM::MVE_VRSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14558 { 3761 /* vrshrnt */, ARM::MVE_VRSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14559 { 3761 /* vrshrnt */, ARM::MVE_VRSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14560 { 3769 /* vrsqrte */, ARM::VRSQRTEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14561 { 3769 /* vrsqrte */, ARM::VRSQRTEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14562 { 3769 /* vrsqrte */, ARM::VRSQRTEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14563 { 3769 /* vrsqrte */, ARM::VRSQRTEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14564 { 3769 /* vrsqrte */, ARM::VRSQRTEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14565 { 3769 /* vrsqrte */, ARM::VRSQRTEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14566 { 3777 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14567 { 3777 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14568 { 3777 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14569 { 3777 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14570 { 3777 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14571 { 3777 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14572 { 3777 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14573 { 3777 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14574 { 3785 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
14575 { 3785 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
14576 { 3785 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14577 { 3785 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14578 { 3785 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
14579 { 3785 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
14580 { 3785 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
14581 { 3785 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
14582 { 3785 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
14583 { 3785 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
14584 { 3785 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
14585 { 3785 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
14586 { 3785 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
14587 { 3785 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
14588 { 3785 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
14589 { 3785 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
14590 { 3785 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14591 { 3785 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14592 { 3785 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14593 { 3785 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14594 { 3785 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14595 { 3785 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14596 { 3785 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14597 { 3785 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14598 { 3785 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14599 { 3785 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14600 { 3785 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14601 { 3785 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14602 { 3785 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14603 { 3785 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14604 { 3785 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14605 { 3785 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14606 { 3791 /* vrsubhn */, ARM::VRSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
14607 { 3791 /* vrsubhn */, ARM::VRSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
14608 { 3791 /* vrsubhn */, ARM::VRSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
14609 { 3799 /* vsbc */, ARM::MVE_VSBC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14610 { 3804 /* vsbci */, ARM::MVE_VSBCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14611 { 3810 /* vscclrm */, ARM::VSCCLRMD, Convert__CondCode2_0__FPDRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPDRegListWithVPR }, },
14612 { 3810 /* vscclrm */, ARM::VSCCLRMS, Convert__CondCode2_0__FPSRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPSRegListWithVPR }, },
14613 { 3818 /* vsdot */, ARM::VSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14614 { 3818 /* vsdot */, ARM::VSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14615 { 3818 /* vsdot */, ARM::VSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14616 { 3818 /* vsdot */, ARM::VSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14617 { 3824 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14618 { 3824 /* vseleq */, ARM::VSELEQD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14619 { 3824 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14620 { 3831 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14621 { 3831 /* vselge */, ARM::VSELGED, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14622 { 3831 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14623 { 3838 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14624 { 3838 /* vselgt */, ARM::VSELGTD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14625 { 3838 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14626 { 3845 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14627 { 3845 /* vselvs */, ARM::VSELVSD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14628 { 3845 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14629 { 3852 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14630 { 3852 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14631 { 3852 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14632 { 3852 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14633 { 3852 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14634 { 3852 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14635 { 3852 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14636 { 3852 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14637 { 3852 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14638 { 3852 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14639 { 3852 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14640 { 3852 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14641 { 3852 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14642 { 3852 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14643 { 3852 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14644 { 3852 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14645 { 3852 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_Imm }, },
14646 { 3852 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_Imm }, },
14647 { 3852 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_Imm }, },
14648 { 3852 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_Imm }, },
14649 { 3852 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_Imm }, },
14650 { 3852 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_Imm }, },
14651 { 3852 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_Imm }, },
14652 { 3852 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_Imm }, },
14653 { 3852 /* vshl */, ARM::MVE_VSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14654 { 3852 /* vshl */, ARM::MVE_VSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14655 { 3852 /* vshl */, ARM::MVE_VSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14656 { 3852 /* vshl */, ARM::MVE_VSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14657 { 3852 /* vshl */, ARM::MVE_VSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14658 { 3852 /* vshl */, ARM::MVE_VSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14659 { 3852 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14660 { 3852 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14661 { 3852 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14662 { 3852 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14663 { 3852 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14664 { 3852 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14665 { 3852 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14666 { 3852 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14667 { 3852 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14668 { 3852 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14669 { 3852 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14670 { 3852 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14671 { 3852 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14672 { 3852 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14673 { 3852 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14674 { 3852 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14675 { 3852 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14676 { 3852 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14677 { 3852 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14678 { 3852 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14679 { 3852 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14680 { 3852 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14681 { 3852 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14682 { 3852 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14683 { 3852 /* vshl */, ARM::MVE_VSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14684 { 3852 /* vshl */, ARM::MVE_VSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14685 { 3852 /* vshl */, ARM::MVE_VSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14686 { 3852 /* vshl */, ARM::MVE_VSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14687 { 3852 /* vshl */, ARM::MVE_VSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14688 { 3852 /* vshl */, ARM::MVE_VSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14689 { 3852 /* vshl */, ARM::MVE_VSHL_immi16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14690 { 3852 /* vshl */, ARM::MVE_VSHL_immi32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14691 { 3852 /* vshl */, ARM::MVE_VSHL_immi8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14692 { 3857 /* vshlc */, ARM::MVE_VSHLC, Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_rGPR, MCK_MVELongShift }, },
14693 { 3863 /* vshll */, ARM::VSHLLsv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, },
14694 { 3863 /* vshll */, ARM::VSHLLsv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
14695 { 3863 /* vshll */, ARM::VSHLLsv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, },
14696 { 3863 /* vshll */, ARM::VSHLLuv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, },
14697 { 3863 /* vshll */, ARM::VSHLLuv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
14698 { 3863 /* vshll */, ARM::VSHLLuv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, },
14699 { 3863 /* vshll */, ARM::VSHLLi16, Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR, MCK_Imm16 }, },
14700 { 3863 /* vshll */, ARM::VSHLLi32, Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR, MCK_Imm32 }, },
14701 { 3863 /* vshll */, ARM::VSHLLi8, Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_DPR, MCK_Imm8 }, },
14702 { 3869 /* vshllb */, ARM::MVE_VSHLL_lws16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14703 { 3869 /* vshllb */, ARM::MVE_VSHLL_imms16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14704 { 3869 /* vshllb */, ARM::MVE_VSHLL_lws8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14705 { 3869 /* vshllb */, ARM::MVE_VSHLL_imms8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14706 { 3869 /* vshllb */, ARM::MVE_VSHLL_lwu16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14707 { 3869 /* vshllb */, ARM::MVE_VSHLL_immu16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14708 { 3869 /* vshllb */, ARM::MVE_VSHLL_lwu8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14709 { 3869 /* vshllb */, ARM::MVE_VSHLL_immu8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14710 { 3876 /* vshllt */, ARM::MVE_VSHLL_lws16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14711 { 3876 /* vshllt */, ARM::MVE_VSHLL_imms16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14712 { 3876 /* vshllt */, ARM::MVE_VSHLL_lws8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14713 { 3876 /* vshllt */, ARM::MVE_VSHLL_imms8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14714 { 3876 /* vshllt */, ARM::MVE_VSHLL_lwu16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14715 { 3876 /* vshllt */, ARM::MVE_VSHLL_immu16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14716 { 3876 /* vshllt */, ARM::MVE_VSHLL_lwu8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14717 { 3876 /* vshllt */, ARM::MVE_VSHLL_immu8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14718 { 3883 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
14719 { 3883 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
14720 { 3883 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14721 { 3883 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14722 { 3883 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
14723 { 3883 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
14724 { 3883 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
14725 { 3883 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
14726 { 3883 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
14727 { 3883 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
14728 { 3883 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
14729 { 3883 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
14730 { 3883 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
14731 { 3883 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
14732 { 3883 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
14733 { 3883 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
14734 { 3883 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14735 { 3883 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14736 { 3883 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14737 { 3883 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14738 { 3883 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14739 { 3883 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14740 { 3883 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14741 { 3883 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14742 { 3883 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14743 { 3883 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14744 { 3883 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14745 { 3883 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14746 { 3883 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14747 { 3883 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14748 { 3883 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14749 { 3883 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14750 { 3883 /* vshr */, ARM::MVE_VSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14751 { 3883 /* vshr */, ARM::MVE_VSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14752 { 3883 /* vshr */, ARM::MVE_VSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14753 { 3883 /* vshr */, ARM::MVE_VSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14754 { 3883 /* vshr */, ARM::MVE_VSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14755 { 3883 /* vshr */, ARM::MVE_VSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14756 { 3888 /* vshrn */, ARM::VSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14757 { 3888 /* vshrn */, ARM::VSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14758 { 3888 /* vshrn */, ARM::VSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14759 { 3894 /* vshrnb */, ARM::MVE_VSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14760 { 3894 /* vshrnb */, ARM::MVE_VSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14761 { 3901 /* vshrnt */, ARM::MVE_VSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14762 { 3901 /* vshrnt */, ARM::MVE_VSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14763 { 3908 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_Imm }, },
14764 { 3908 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_Imm }, },
14765 { 3908 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_Imm }, },
14766 { 3908 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_Imm }, },
14767 { 3908 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_Imm }, },
14768 { 3908 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_Imm }, },
14769 { 3908 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_Imm }, },
14770 { 3908 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_Imm }, },
14771 { 3908 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14772 { 3908 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14773 { 3908 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14774 { 3908 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14775 { 3908 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14776 { 3908 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14777 { 3908 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14778 { 3908 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14779 { 3908 /* vsli */, ARM::MVE_VSLIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14780 { 3908 /* vsli */, ARM::MVE_VSLIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14781 { 3908 /* vsli */, ARM::MVE_VSLIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14782 { 3913 /* vsmmla */, ARM::VSMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14783 { 3920 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
14784 { 3920 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
14785 { 3920 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14786 { 3920 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14787 { 3920 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14788 { 3926 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
14789 { 3926 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
14790 { 3926 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14791 { 3926 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14792 { 3926 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
14793 { 3926 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
14794 { 3926 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
14795 { 3926 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
14796 { 3926 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
14797 { 3926 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
14798 { 3926 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
14799 { 3926 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
14800 { 3926 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
14801 { 3926 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
14802 { 3926 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
14803 { 3926 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
14804 { 3926 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14805 { 3926 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14806 { 3926 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14807 { 3926 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14808 { 3926 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14809 { 3926 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14810 { 3926 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14811 { 3926 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14812 { 3926 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14813 { 3926 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14814 { 3926 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14815 { 3926 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14816 { 3926 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14817 { 3926 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14818 { 3926 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14819 { 3926 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14820 { 3931 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_ShrImm16 }, },
14821 { 3931 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_ShrImm16 }, },
14822 { 3931 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_ShrImm32 }, },
14823 { 3931 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_ShrImm32 }, },
14824 { 3931 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_ShrImm64 }, },
14825 { 3931 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_ShrImm64 }, },
14826 { 3931 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_ShrImm8 }, },
14827 { 3931 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_ShrImm8 }, },
14828 { 3931 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14829 { 3931 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14830 { 3931 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14831 { 3931 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14832 { 3931 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14833 { 3931 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14834 { 3931 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14835 { 3931 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14836 { 3931 /* vsri */, ARM::MVE_VSRIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14837 { 3931 /* vsri */, ARM::MVE_VSRIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14838 { 3931 /* vsri */, ARM::MVE_VSRIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14839 { 3936 /* vst1 */, ARM::VST1q16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
14840 { 3936 /* vst1 */, ARM::VST1d16Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
14841 { 3936 /* vst1 */, ARM::VST1d16, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, },
14842 { 3936 /* vst1 */, ARM::VST1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, },
14843 { 3936 /* vst1 */, ARM::VST1d16T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
14844 { 3936 /* vst1 */, ARM::VST1q32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
14845 { 3936 /* vst1 */, ARM::VST1d32Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
14846 { 3936 /* vst1 */, ARM::VST1d32, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, },
14847 { 3936 /* vst1 */, ARM::VST1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, },
14848 { 3936 /* vst1 */, ARM::VST1d32T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
14849 { 3936 /* vst1 */, ARM::VST1q64, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
14850 { 3936 /* vst1 */, ARM::VST1d64Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
14851 { 3936 /* vst1 */, ARM::VST1d64, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, },
14852 { 3936 /* vst1 */, ARM::VST1d64T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
14853 { 3936 /* vst1 */, ARM::VST1q8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
14854 { 3936 /* vst1 */, ARM::VST1d8Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
14855 { 3936 /* vst1 */, ARM::VST1d8, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, },
14856 { 3936 /* vst1 */, ARM::VST1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, },
14857 { 3936 /* vst1 */, ARM::VST1d8T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
14858 { 3936 /* vst1 */, ARM::VST1q16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14859 { 3936 /* vst1 */, ARM::VST1q16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
14860 { 3936 /* vst1 */, ARM::VST1d16Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14861 { 3936 /* vst1 */, ARM::VST1d16Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
14862 { 3936 /* vst1 */, ARM::VST1d16wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14863 { 3936 /* vst1 */, ARM::VST1d16wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
14864 { 3936 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
14865 { 3936 /* vst1 */, ARM::VST1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
14866 { 3936 /* vst1 */, ARM::VST1d16Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14867 { 3936 /* vst1 */, ARM::VST1d16Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
14868 { 3936 /* vst1 */, ARM::VST1q32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14869 { 3936 /* vst1 */, ARM::VST1q32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
14870 { 3936 /* vst1 */, ARM::VST1d32Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14871 { 3936 /* vst1 */, ARM::VST1d32Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
14872 { 3936 /* vst1 */, ARM::VST1d32wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14873 { 3936 /* vst1 */, ARM::VST1d32wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
14874 { 3936 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
14875 { 3936 /* vst1 */, ARM::VST1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
14876 { 3936 /* vst1 */, ARM::VST1d32Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14877 { 3936 /* vst1 */, ARM::VST1d32Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
14878 { 3936 /* vst1 */, ARM::VST1q64wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14879 { 3936 /* vst1 */, ARM::VST1q64wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
14880 { 3936 /* vst1 */, ARM::VST1d64Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14881 { 3936 /* vst1 */, ARM::VST1d64Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
14882 { 3936 /* vst1 */, ARM::VST1d64wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14883 { 3936 /* vst1 */, ARM::VST1d64wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
14884 { 3936 /* vst1 */, ARM::VST1d64Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14885 { 3936 /* vst1 */, ARM::VST1d64Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
14886 { 3936 /* vst1 */, ARM::VST1q8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14887 { 3936 /* vst1 */, ARM::VST1q8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
14888 { 3936 /* vst1 */, ARM::VST1d8Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14889 { 3936 /* vst1 */, ARM::VST1d8Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
14890 { 3936 /* vst1 */, ARM::VST1d8wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14891 { 3936 /* vst1 */, ARM::VST1d8wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
14892 { 3936 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14893 { 3936 /* vst1 */, ARM::VST1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
14894 { 3936 /* vst1 */, ARM::VST1d8Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14895 { 3936 /* vst1 */, ARM::VST1d8Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
14896 { 3936 /* vst1 */, ARM::VST1LNd16, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
14897 { 3936 /* vst1 */, ARM::VST1LNd8, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
14898 { 3936 /* vst1 */, ARM::VST1LNd16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
14899 { 3936 /* vst1 */, ARM::VST1LNd32, Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
14900 { 3936 /* vst1 */, ARM::VST1LNd8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
14901 { 3936 /* vst1 */, ARM::VST1LNd32_UPD, Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm, MCK_Imm }, },
14902 { 3941 /* vst2 */, ARM::VST2d16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
14903 { 3941 /* vst2 */, ARM::VST2b16, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
14904 { 3941 /* vst2 */, ARM::VST2q16, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
14905 { 3941 /* vst2 */, ARM::VST2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, },
14906 { 3941 /* vst2 */, ARM::VST2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, },
14907 { 3941 /* vst2 */, ARM::VST2d32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
14908 { 3941 /* vst2 */, ARM::VST2b32, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
14909 { 3941 /* vst2 */, ARM::VST2q32, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
14910 { 3941 /* vst2 */, ARM::VST2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, },
14911 { 3941 /* vst2 */, ARM::VST2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, },
14912 { 3941 /* vst2 */, ARM::VST2d8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
14913 { 3941 /* vst2 */, ARM::VST2b8, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
14914 { 3941 /* vst2 */, ARM::VST2q8, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
14915 { 3941 /* vst2 */, ARM::VST2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, },
14916 { 3941 /* vst2 */, ARM::VST2d16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14917 { 3941 /* vst2 */, ARM::VST2d16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
14918 { 3941 /* vst2 */, ARM::VST2b16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14919 { 3941 /* vst2 */, ARM::VST2b16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
14920 { 3941 /* vst2 */, ARM::VST2q16wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14921 { 3941 /* vst2 */, ARM::VST2q16wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
14922 { 3941 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
14923 { 3941 /* vst2 */, ARM::VST2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
14924 { 3941 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
14925 { 3941 /* vst2 */, ARM::VST2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
14926 { 3941 /* vst2 */, ARM::VST2d32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14927 { 3941 /* vst2 */, ARM::VST2d32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
14928 { 3941 /* vst2 */, ARM::VST2b32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14929 { 3941 /* vst2 */, ARM::VST2b32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
14930 { 3941 /* vst2 */, ARM::VST2q32wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14931 { 3941 /* vst2 */, ARM::VST2q32wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
14932 { 3941 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14933 { 3941 /* vst2 */, ARM::VST2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
14934 { 3941 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14935 { 3941 /* vst2 */, ARM::VST2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
14936 { 3941 /* vst2 */, ARM::VST2d8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14937 { 3941 /* vst2 */, ARM::VST2d8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
14938 { 3941 /* vst2 */, ARM::VST2b8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14939 { 3941 /* vst2 */, ARM::VST2b8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
14940 { 3941 /* vst2 */, ARM::VST2q8wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14941 { 3941 /* vst2 */, ARM::VST2q8wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
14942 { 3941 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
14943 { 3941 /* vst2 */, ARM::VST2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
14944 { 3946 /* vst20 */, ARM::MVE_VST20_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
14945 { 3946 /* vst20 */, ARM::MVE_VST20_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
14946 { 3946 /* vst20 */, ARM::MVE_VST20_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
14947 { 3946 /* vst20 */, ARM::MVE_VST20_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14948 { 3946 /* vst20 */, ARM::MVE_VST20_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14949 { 3946 /* vst20 */, ARM::MVE_VST20_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14950 { 3952 /* vst21 */, ARM::MVE_VST21_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
14951 { 3952 /* vst21 */, ARM::MVE_VST21_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
14952 { 3952 /* vst21 */, ARM::MVE_VST21_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
14953 { 3952 /* vst21 */, ARM::MVE_VST21_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14954 { 3952 /* vst21 */, ARM::MVE_VST21_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14955 { 3952 /* vst21 */, ARM::MVE_VST21_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14956 { 3958 /* vst3 */, ARM::VST3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
14957 { 3958 /* vst3 */, ARM::VST3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, },
14958 { 3958 /* vst3 */, ARM::VST3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
14959 { 3958 /* vst3 */, ARM::VST3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, },
14960 { 3958 /* vst3 */, ARM::VST3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
14961 { 3958 /* vst3 */, ARM::VST3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, },
14962 { 3958 /* vst3 */, ARM::VST3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
14963 { 3958 /* vst3 */, ARM::VST3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, },
14964 { 3958 /* vst3 */, ARM::VST3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
14965 { 3958 /* vst3 */, ARM::VST3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, },
14966 { 3958 /* vst3 */, ARM::VST3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
14967 { 3958 /* vst3 */, ARM::VST3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14968 { 3958 /* vst3 */, ARM::VST3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
14969 { 3958 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14970 { 3958 /* vst3 */, ARM::VST3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
14971 { 3958 /* vst3 */, ARM::VST3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14972 { 3958 /* vst3 */, ARM::VST3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
14973 { 3958 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14974 { 3958 /* vst3 */, ARM::VST3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
14975 { 3958 /* vst3 */, ARM::VST3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14976 { 3958 /* vst3 */, ARM::VST3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
14977 { 3958 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14978 { 3958 /* vst3 */, ARM::VST3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
14979 { 3958 /* vst3 */, ARM::VST3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14980 { 3958 /* vst3 */, ARM::VST3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
14981 { 3958 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14982 { 3958 /* vst3 */, ARM::VST3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
14983 { 3958 /* vst3 */, ARM::VST3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14984 { 3958 /* vst3 */, ARM::VST3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
14985 { 3958 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14986 { 3958 /* vst3 */, ARM::VST3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
14987 { 3958 /* vst3 */, ARM::VST3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14988 { 3958 /* vst3 */, ARM::VST3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
14989 { 3958 /* vst3 */, ARM::VST3d16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
14990 { 3958 /* vst3 */, ARM::VST3q16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
14991 { 3958 /* vst3 */, ARM::VST3d32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
14992 { 3958 /* vst3 */, ARM::VST3q32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
14993 { 3958 /* vst3 */, ARM::VST3d8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
14994 { 3958 /* vst3 */, ARM::VST3q8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
14995 { 3958 /* vst3 */, ARM::VST3d16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
14996 { 3958 /* vst3 */, ARM::VST3q16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
14997 { 3958 /* vst3 */, ARM::VST3d32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
14998 { 3958 /* vst3 */, ARM::VST3q32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
14999 { 3958 /* vst3 */, ARM::VST3d8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15000 { 3958 /* vst3 */, ARM::VST3q8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15001 { 3963 /* vst4 */, ARM::VST4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15002 { 3963 /* vst4 */, ARM::VST4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, },
15003 { 3963 /* vst4 */, ARM::VST4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15004 { 3963 /* vst4 */, ARM::VST4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, },
15005 { 3963 /* vst4 */, ARM::VST4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15006 { 3963 /* vst4 */, ARM::VST4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, },
15007 { 3963 /* vst4 */, ARM::VST4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15008 { 3963 /* vst4 */, ARM::VST4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, },
15009 { 3963 /* vst4 */, ARM::VST4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15010 { 3963 /* vst4 */, ARM::VST4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, },
15011 { 3963 /* vst4 */, ARM::VST4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15012 { 3963 /* vst4 */, ARM::VST4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15013 { 3963 /* vst4 */, ARM::VST4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15014 { 3963 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15015 { 3963 /* vst4 */, ARM::VST4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15016 { 3963 /* vst4 */, ARM::VST4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15017 { 3963 /* vst4 */, ARM::VST4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15018 { 3963 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15019 { 3963 /* vst4 */, ARM::VST4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15020 { 3963 /* vst4 */, ARM::VST4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15021 { 3963 /* vst4 */, ARM::VST4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15022 { 3963 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15023 { 3963 /* vst4 */, ARM::VST4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
15024 { 3963 /* vst4 */, ARM::VST4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15025 { 3963 /* vst4 */, ARM::VST4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15026 { 3963 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15027 { 3963 /* vst4 */, ARM::VST4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
15028 { 3963 /* vst4 */, ARM::VST4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15029 { 3963 /* vst4 */, ARM::VST4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15030 { 3963 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15031 { 3963 /* vst4 */, ARM::VST4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15032 { 3963 /* vst4 */, ARM::VST4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15033 { 3963 /* vst4 */, ARM::VST4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15034 { 3963 /* vst4 */, ARM::VST4d16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15035 { 3963 /* vst4 */, ARM::VST4q16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15036 { 3963 /* vst4 */, ARM::VST4d32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15037 { 3963 /* vst4 */, ARM::VST4q32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15038 { 3963 /* vst4 */, ARM::VST4d8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15039 { 3963 /* vst4 */, ARM::VST4q8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15040 { 3963 /* vst4 */, ARM::VST4d16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15041 { 3963 /* vst4 */, ARM::VST4q16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15042 { 3963 /* vst4 */, ARM::VST4d32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15043 { 3963 /* vst4 */, ARM::VST4q32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15044 { 3963 /* vst4 */, ARM::VST4d8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15045 { 3963 /* vst4 */, ARM::VST4q8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15046 { 3968 /* vst40 */, ARM::MVE_VST40_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15047 { 3968 /* vst40 */, ARM::MVE_VST40_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15048 { 3968 /* vst40 */, ARM::MVE_VST40_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15049 { 3968 /* vst40 */, ARM::MVE_VST40_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15050 { 3968 /* vst40 */, ARM::MVE_VST40_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15051 { 3968 /* vst40 */, ARM::MVE_VST40_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15052 { 3974 /* vst41 */, ARM::MVE_VST41_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15053 { 3974 /* vst41 */, ARM::MVE_VST41_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15054 { 3974 /* vst41 */, ARM::MVE_VST41_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15055 { 3974 /* vst41 */, ARM::MVE_VST41_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15056 { 3974 /* vst41 */, ARM::MVE_VST41_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15057 { 3974 /* vst41 */, ARM::MVE_VST41_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15058 { 3980 /* vst42 */, ARM::MVE_VST42_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15059 { 3980 /* vst42 */, ARM::MVE_VST42_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15060 { 3980 /* vst42 */, ARM::MVE_VST42_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15061 { 3980 /* vst42 */, ARM::MVE_VST42_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15062 { 3980 /* vst42 */, ARM::MVE_VST42_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15063 { 3980 /* vst42 */, ARM::MVE_VST42_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15064 { 3986 /* vst43 */, ARM::MVE_VST43_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15065 { 3986 /* vst43 */, ARM::MVE_VST43_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15066 { 3986 /* vst43 */, ARM::MVE_VST43_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15067 { 3986 /* vst43 */, ARM::MVE_VST43_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15068 { 3986 /* vst43 */, ARM::MVE_VST43_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15069 { 3986 /* vst43 */, ARM::MVE_VST43_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15070 { 3992 /* vstmdb */, ARM::VSTMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
15071 { 3992 /* vstmdb */, ARM::VSTMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
15072 { 3999 /* vstmia */, ARM::VSTMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
15073 { 3999 /* vstmia */, ARM::VSTMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, },
15074 { 3999 /* vstmia */, ARM::VSTMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
15075 { 3999 /* vstmia */, ARM::VSTMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
15076 { 4006 /* vstr */, ARM::VSTR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset }, },
15077 { 4006 /* vstr */, ARM::VSTR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, },
15078 { 4006 /* vstr */, ARM::VSTR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, },
15079 { 4006 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, },
15080 { 4006 /* vstr */, ARM::VSTR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, },
15081 { 4006 /* vstr */, ARM::VSTR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, },
15082 { 4006 /* vstr */, ARM::VSTRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, },
15083 { 4006 /* vstr */, ARM::VSTRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
15084 { 4006 /* vstr */, ARM::VSTRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
15085 { 4006 /* vstr */, ARM::VSTRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
15086 { 4006 /* vstr */, ARM::VSTRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, },
15087 { 4006 /* vstr */, ARM::VSTR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15088 { 4006 /* vstr */, ARM::VSTR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15089 { 4006 /* vstr */, ARM::VSTR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15090 { 4006 /* vstr */, ARM::VSTR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15091 { 4006 /* vstr */, ARM::VSTR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15092 { 4006 /* vstr */, ARM::VSTR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15093 { 4006 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15094 { 4006 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_post, Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15095 { 4006 /* vstr */, ARM::VSTR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15096 { 4006 /* vstr */, ARM::VSTR_P0_post, Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15097 { 4006 /* vstr */, ARM::VSTR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15098 { 4006 /* vstr */, ARM::VSTR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15099 { 4011 /* vstrb */, ARM::MVE_VSTRB16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15100 { 4011 /* vstrb */, ARM::MVE_VSTRB16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
15101 { 4011 /* vstrb */, ARM::MVE_VSTRB32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15102 { 4011 /* vstrb */, ARM::MVE_VSTRB32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
15103 { 4011 /* vstrb */, ARM::MVE_VSTRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0Offset }, },
15104 { 4011 /* vstrb */, ARM::MVE_VSTRB8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15105 { 4011 /* vstrb */, ARM::MVE_VSTRB16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
15106 { 4011 /* vstrb */, ARM::MVE_VSTRB16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
15107 { 4011 /* vstrb */, ARM::MVE_VSTRB32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
15108 { 4011 /* vstrb */, ARM::MVE_VSTRB32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
15109 { 4011 /* vstrb */, ARM::MVE_VSTRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, },
15110 { 4011 /* vstrb */, ARM::MVE_VSTRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, },
15111 { 4017 /* vstrd */, ARM::MVE_VSTRD64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset }, },
15112 { 4017 /* vstrd */, ARM::MVE_VSTRD64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15113 { 4017 /* vstrd */, ARM::MVE_VSTRD64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS3Offset }, },
15114 { 4017 /* vstrd */, ARM::MVE_VSTRD64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, },
15115 { 4023 /* vstrh */, ARM::MVE_VSTRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1Offset }, },
15116 { 4023 /* vstrh */, ARM::MVE_VSTRH16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15117 { 4023 /* vstrh */, ARM::MVE_VSTRH16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS1Offset }, },
15118 { 4023 /* vstrh */, ARM::MVE_VSTRH32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15119 { 4023 /* vstrh */, ARM::MVE_VSTRH32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
15120 { 4023 /* vstrh */, ARM::MVE_VSTRH32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
15121 { 4023 /* vstrh */, ARM::MVE_VSTRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, },
15122 { 4023 /* vstrh */, ARM::MVE_VSTRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, },
15123 { 4023 /* vstrh */, ARM::MVE_VSTRH32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
15124 { 4023 /* vstrh */, ARM::MVE_VSTRH32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
15125 { 4029 /* vstrw */, ARM::MVE_VSTRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2Offset }, },
15126 { 4029 /* vstrw */, ARM::MVE_VSTRW32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset }, },
15127 { 4029 /* vstrw */, ARM::MVE_VSTRW32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15128 { 4029 /* vstrw */, ARM::MVE_VSTRW32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS2Offset }, },
15129 { 4029 /* vstrw */, ARM::MVE_VSTRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, },
15130 { 4029 /* vstrw */, ARM::MVE_VSTRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, },
15131 { 4029 /* vstrw */, ARM::MVE_VSTRW32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, },
15132 { 4035 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
15133 { 4035 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
15134 { 4035 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
15135 { 4035 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
15136 { 4035 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
15137 { 4035 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
15138 { 4035 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
15139 { 4035 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
15140 { 4035 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
15141 { 4035 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
15142 { 4035 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
15143 { 4035 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
15144 { 4035 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
15145 { 4035 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
15146 { 4035 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
15147 { 4035 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15148 { 4035 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15149 { 4035 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
15150 { 4035 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15151 { 4035 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15152 { 4035 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15153 { 4035 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15154 { 4035 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15155 { 4035 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
15156 { 4035 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15157 { 4035 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15158 { 4035 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15159 { 4035 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15160 { 4035 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15161 { 4035 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
15162 { 4035 /* vsub */, ARM::MVE_VSUBf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15163 { 4035 /* vsub */, ARM::MVE_VSUB_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15164 { 4035 /* vsub */, ARM::MVE_VSUBi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15165 { 4035 /* vsub */, ARM::MVE_VSUB_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15166 { 4035 /* vsub */, ARM::MVE_VSUBi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15167 { 4035 /* vsub */, ARM::MVE_VSUB_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15168 { 4035 /* vsub */, ARM::MVE_VSUBi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15169 { 4035 /* vsub */, ARM::MVE_VSUB_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15170 { 4035 /* vsub */, ARM::MVE_VSUBf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15171 { 4035 /* vsub */, ARM::MVE_VSUB_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15172 { 4040 /* vsubhn */, ARM::VSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
15173 { 4040 /* vsubhn */, ARM::VSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
15174 { 4040 /* vsubhn */, ARM::VSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
15175 { 4047 /* vsubl */, ARM::VSUBLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
15176 { 4047 /* vsubl */, ARM::VSUBLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
15177 { 4047 /* vsubl */, ARM::VSUBLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
15178 { 4047 /* vsubl */, ARM::VSUBLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
15179 { 4047 /* vsubl */, ARM::VSUBLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
15180 { 4047 /* vsubl */, ARM::VSUBLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
15181 { 4053 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
15182 { 4053 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
15183 { 4053 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
15184 { 4053 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
15185 { 4053 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
15186 { 4053 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
15187 { 4053 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
15188 { 4053 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
15189 { 4053 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
15190 { 4053 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
15191 { 4053 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
15192 { 4053 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
15193 { 4059 /* vsudot */, ARM::VSUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15194 { 4059 /* vsudot */, ARM::VSUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15195 { 4066 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
15196 { 4066 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
15197 { 4066 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15198 { 4066 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15199 { 4066 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15200 { 4066 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15201 { 4066 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
15202 { 4066 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
15203 { 4066 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15204 { 4066 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15205 { 4071 /* vtbl */, ARM::VTBL2, Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, },
15206 { 4071 /* vtbl */, ARM::VTBL4, Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, },
15207 { 4071 /* vtbl */, ARM::VTBL1, Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, },
15208 { 4071 /* vtbl */, ARM::VTBL3, Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, },
15209 { 4076 /* vtbx */, ARM::VTBX2, Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, },
15210 { 4076 /* vtbx */, ARM::VTBX4, Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, },
15211 { 4076 /* vtbx */, ARM::VTBX1, Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, },
15212 { 4076 /* vtbx */, ARM::VTBX3, Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, },
15213 { 4081 /* vtrn */, ARM::VTRNq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15214 { 4081 /* vtrn */, ARM::VTRNd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15215 { 4081 /* vtrn */, ARM::VTRNq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15216 { 4081 /* vtrn */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15217 { 4081 /* vtrn */, ARM::VTRNq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15218 { 4081 /* vtrn */, ARM::VTRNd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15219 { 4086 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15220 { 4086 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15221 { 4086 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15222 { 4086 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15223 { 4086 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15224 { 4086 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15225 { 4086 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15226 { 4086 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15227 { 4086 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15228 { 4086 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15229 { 4086 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15230 { 4086 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15231 { 4091 /* vudot */, ARM::VUDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15232 { 4091 /* vudot */, ARM::VUDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15233 { 4091 /* vudot */, ARM::VUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15234 { 4091 /* vudot */, ARM::VUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15235 { 4097 /* vummla */, ARM::VUMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15236 { 4104 /* vusdot */, ARM::VUSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15237 { 4104 /* vusdot */, ARM::VUSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15238 { 4104 /* vusdot */, ARM::VUSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15239 { 4104 /* vusdot */, ARM::VUSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15240 { 4111 /* vusmmla */, ARM::VUSMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15241 { 4119 /* vuzp */, ARM::VUZPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15242 { 4119 /* vuzp */, ARM::VUZPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15243 { 4119 /* vuzp */, ARM::VUZPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15244 { 4119 /* vuzp */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15245 { 4119 /* vuzp */, ARM::VUZPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15246 { 4119 /* vuzp */, ARM::VUZPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15247 { 4124 /* vzip */, ARM::VZIPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15248 { 4124 /* vzip */, ARM::VZIPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15249 { 4124 /* vzip */, ARM::VZIPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15250 { 4124 /* vzip */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15251 { 4124 /* vzip */, ARM::VZIPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15252 { 4124 /* vzip */, ARM::VZIPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15253 { 4129 /* wfe */, ARM::tHINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15254 { 4129 /* wfe */, ARM::HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15255 { 4129 /* wfe */, ARM::t2HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15256 { 4133 /* wfi */, ARM::tHINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15257 { 4133 /* wfi */, ARM::HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15258 { 4133 /* wfi */, ARM::t2HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15259 { 4137 /* wls */, ARM::t2WLS, Convert__Reg1_0__Reg1_1__WLSLabel1_2, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15260 { 4141 /* wlstp */, ARM::MVE_WLSTP_16, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15261 { 4141 /* wlstp */, ARM::MVE_WLSTP_32, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15262 { 4141 /* wlstp */, ARM::MVE_WLSTP_64, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15263 { 4141 /* wlstp */, ARM::MVE_WLSTP_8, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15264 { 4147 /* yield */, ARM::tHINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15265 { 4147 /* yield */, ARM::HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15266 { 4147 /* yield */, ARM::t2HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15267};
15268
15269#include "llvm/Support/Debug.h"
15270#include "llvm/Support/Format.h"
15271
15272unsigned ARMAsmParser::
15273MatchInstructionImpl(const OperandVector &Operands,
15274 MCInst &Inst,
15275 SmallVectorImpl<NearMissInfo> *NearMisses,
15276 bool matchingInlineAsm, unsigned VariantID) {
15277 // Get the current feature set.
15278 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
15279
15280 // Get the instruction mnemonic, which is the first token.
15281 StringRef Mnemonic = ((ARMOperand &)*Operands[0]).getToken();
15282
15283 // Process all MnemonicAliases to remap the mnemonic.
15284 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
15285
15286 SmallBitVector OptionalOperandsMask(18);
15287 // Find the appropriate table for this asm variant.
15288 const MatchEntry *Start, *End;
15289 switch (VariantID) {
15290 default: llvm_unreachable("invalid variant!");
15291 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
15292 }
15293 // Search the table.
15294 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
15295
15296 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
15297 std::distance(MnemonicRange.first, MnemonicRange.second) <<
15298 " encodings with mnemonic '" << Mnemonic << "'\n");
15299
15300 // Return a more specific error code if no mnemonics match.
15301 if (MnemonicRange.first == MnemonicRange.second)
15302 return Match_MnemonicFail;
15303
15304 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
15305 it != ie; ++it) {
15306 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
15307 bool HasRequiredFeatures =
15308 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
15309 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
15310 << MII.getName(it->Opcode) << "\n");
15311 // Some state to record ways in which this instruction did not match.
15312 NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();
15313 NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();
15314 NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();
15315 NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();
15316 bool MultipleInvalidOperands = false;
15317 // equal_range guarantees that instruction mnemonic matches.
15318 assert(Mnemonic == it->getMnemonic());
15319 OptionalOperandsMask.reset(0, 18);
15320 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 18; ++FormalIdx) {
15321 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
15322 DEBUG_WITH_TYPE("asm-matcher",
15323 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
15324 << " against actual operand at index " << ActualIdx);
15325 if (ActualIdx < Operands.size())
15326 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
15327 Operands[ActualIdx]->print(dbgs(), *getContext().getAsmInfo()); dbgs() << "): ");
15328 else
15329 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
15330 if (ActualIdx >= Operands.size()) {
15331 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
15332 bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
15333 if (!ThisOperandValid) {
15334 if (!OperandNearMiss) {
15335 // Record info about match failure for later use.
15336 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n");
15337 OperandNearMiss =
15338 NearMissInfo::getTooFewOperands(Formal, it->Opcode);
15339 } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {
15340 // If more than one operand is invalid, give up on this match entry.
15341 DEBUG_WITH_TYPE(
15342 "asm-matcher",
15343 dbgs() << "second invalid operand, giving up on this opcode\n");
15344 MultipleInvalidOperands = true;
15345 break;
15346 }
15347 } else {
15348 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n");
15349 if (isSubclass(Formal, OptionalMatchClass)) {
15350 OptionalOperandsMask.set(FormalIdx);
15351 }
15352 }
15353 continue;
15354 }
15355 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
15356 unsigned Diag = validateOperandClass(Actual, Formal);
15357 if (Diag == Match_Success) {
15358 DEBUG_WITH_TYPE("asm-matcher",
15359 dbgs() << "match success using generic matcher\n");
15360 ++ActualIdx;
15361 continue;
15362 }
15363 // If the generic handler indicates an invalid operand
15364 // failure, check for a special case.
15365 if (Diag != Match_Success) {
15366 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
15367 if (TargetDiag == Match_Success) {
15368 DEBUG_WITH_TYPE("asm-matcher",
15369 dbgs() << "match success using target matcher\n");
15370 ++ActualIdx;
15371 continue;
15372 }
15373 // If the target matcher returned a specific error code use
15374 // that, else use the one from the generic matcher.
15375 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
15376 Diag = TargetDiag;
15377 }
15378 // If current formal operand wasn't matched and it is optional
15379 // then try to match next formal operand
15380 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
15381 OptionalOperandsMask.set(FormalIdx);
15382 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
15383 continue;
15384 }
15385 if (!OperandNearMiss) {
15386 // If this is the first invalid operand we have seen, record some
15387 // information about it.
15388 DEBUG_WITH_TYPE(
15389 "asm-matcher",
15390 dbgs()
15391 << "operand match failed, recording near-miss with diag code "
15392 << Diag << "\n");
15393 OperandNearMiss =
15394 NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);
15395 ++ActualIdx;
15396 } else {
15397 // If more than one operand is invalid, give up on this match entry.
15398 DEBUG_WITH_TYPE(
15399 "asm-matcher",
15400 dbgs() << "second operand mismatch, skipping this opcode\n");
15401 MultipleInvalidOperands = true;
15402 break;
15403 }
15404 }
15405
15406 if (MultipleInvalidOperands) {
15407 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
15408 "operand mismatches, ignoring "
15409 "this opcode\n");
15410 continue;
15411 }
15412 if (!HasRequiredFeatures) {
15413 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
15414 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
15415 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
15416 if (NewMissingFeatures[I])
15417 dbgs() << ' ' << I;
15418 dbgs() << "\n");
15419 FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);
15420 }
15421
15422 Inst.clear();
15423
15424 Inst.setOpcode(it->Opcode);
15425 // We have a potential match but have not rendered the operands.
15426 // Check the target predicate to handle any context sensitive
15427 // constraints.
15428 // For example, Ties that are referenced multiple times must be
15429 // checked here to ensure the input is the same for each match
15430 // constraints. If we leave it any later the ties will have been
15431 // canonicalized
15432 unsigned MatchResult;
15433 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
15434 Inst.clear();
15435 DEBUG_WITH_TYPE(
15436 "asm-matcher",
15437 dbgs() << "Early target match predicate failed with diag code "
15438 << MatchResult << "\n");
15439 EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
15440 }
15441
15442 // If we did not successfully match the operands, then we can't convert to
15443 // an MCInst, so bail out on this instruction variant now.
15444 if (OperandNearMiss) {
15445 // If the operand mismatch was the only problem, report it as a near-miss.
15446 if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {
15447 DEBUG_WITH_TYPE(
15448 "asm-matcher",
15449 dbgs()
15450 << "Opcode result: one mismatched operand, adding near-miss\n");
15451 NearMisses->push_back(OperandNearMiss);
15452 } else {
15453 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
15454 "types of mismatch, so not "
15455 "reporting near-miss\n");
15456 }
15457 continue;
15458 }
15459
15460 unsigned DefaultsOffset[19] = { 0 };
15461 assert(OptionalOperandsMask.size() == 18);
15462 for (unsigned i = 0, NumDefaults = 0; i < 18; ++i) {
15463 DefaultsOffset[i + 1] = NumDefaults;
15464 NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
15465 }
15466
15467 if (matchingInlineAsm) {
15468 convertToMapAndConstraints(it->ConvertFn, Operands);
15469 return Match_Success;
15470 }
15471
15472 // We have selected a definite instruction, convert the parsed
15473 // operands into the appropriate MCInst.
15474 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
15475 OptionalOperandsMask, DefaultsOffset);
15476
15477 // We have a potential match. Check the target predicate to
15478 // handle any context sensitive constraints.
15479 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
15480 DEBUG_WITH_TYPE("asm-matcher",
15481 dbgs() << "Target match predicate failed with diag code "
15482 << MatchResult << "\n");
15483 Inst.clear();
15484 LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
15485 }
15486
15487 int NumNearMisses = ((int)(bool)OperandNearMiss +
15488 (int)(bool)FeaturesNearMiss +
15489 (int)(bool)EarlyPredicateNearMiss +
15490 (int)(bool)LatePredicateNearMiss);
15491 if (NumNearMisses == 1) {
15492 // We had exactly one type of near-miss, so add that to the list.
15493 assert(!OperandNearMiss && "OperandNearMiss was handled earlier");
15494 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of "
15495 "mismatch, so reporting a "
15496 "near-miss\n");
15497 if (NearMisses && FeaturesNearMiss)
15498 NearMisses->push_back(FeaturesNearMiss);
15499 else if (NearMisses && EarlyPredicateNearMiss)
15500 NearMisses->push_back(EarlyPredicateNearMiss);
15501 else if (NearMisses && LatePredicateNearMiss)
15502 NearMisses->push_back(LatePredicateNearMiss);
15503
15504 continue;
15505 } else if (NumNearMisses > 1) {
15506 // This instruction missed in more than one way, so ignore it.
15507 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
15508 "types of mismatch, so not "
15509 "reporting near-miss\n");
15510 continue;
15511 }
15512 std::string Info;
15513 if (!getParser().getTargetParser().getTargetOptions().MCNoDeprecatedWarn &&
15514 MII.getDeprecatedInfo(Inst, getSTI(), Info)) {
15515 SMLoc Loc = ((ARMOperand &)*Operands[0]).getStartLoc();
15516 getParser().Warning(Loc, Info, std::nullopt);
15517 }
15518 DEBUG_WITH_TYPE(
15519 "asm-matcher",
15520 dbgs() << "Opcode result: complete match, selecting this opcode\n");
15521 return Match_Success;
15522 }
15523
15524 // No instruction variants matched exactly.
15525 return Match_NearMisses;
15526}
15527
15528namespace {
15529 struct OperandMatchEntry {
15530 uint16_t Mnemonic;
15531 uint8_t OperandMask;
15532 uint16_t Class;
15533 uint8_t RequiredFeaturesIdx;
15534
15535 StringRef getMnemonic() const {
15536 return StringRef(MnemonicTable + Mnemonic + 1,
15537 MnemonicTable[Mnemonic]);
15538 }
15539 };
15540
15541 // Predicate for searching for an opcode.
15542 struct LessOpcodeOperand {
15543 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
15544 return LHS.getMnemonic() < RHS;
15545 }
15546 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
15547 return LHS < RHS.getMnemonic();
15548 }
15549 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
15550 return LHS.getMnemonic() < RHS.getMnemonic();
15551 }
15552 };
15553} // end anonymous namespace
15554
15555static const OperandMatchEntry OperandMatchTable[891] = {
15556 /* Operand List Mnemonic, Mask, Operand Class, Features */
15557 { 11 /* adc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15558 { 11 /* adc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15559 { 15 /* add */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15560 { 15 /* add */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15561 { 51 /* and */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15562 { 51 /* and */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15563 { 78 /* bfc */, 6 /* 1, 2 */, MCK_Bitfield, AMFBS_IsThumb2 },
15564 { 78 /* bfc */, 6 /* 1, 2 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 },
15565 { 82 /* bfcsel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB },
15566 { 89 /* bfi */, 12 /* 2, 3 */, MCK_Bitfield, AMFBS_IsThumb2 },
15567 { 89 /* bfi */, 12 /* 2, 3 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 },
15568 { 106 /* bic */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15569 { 106 /* bic */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15570 { 159 /* cdp */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15571 { 159 /* cdp */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15572 { 159 /* cdp */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15573 { 159 /* cdp */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15574 { 163 /* cdp2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15575 { 163 /* cdp2 */, 28 /* 2, 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15576 { 163 /* cdp2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15577 { 163 /* cdp2 */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15578 { 168 /* cinc */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15579 { 173 /* cinv */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15580 { 200 /* cmn */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
15581 { 204 /* cmp */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
15582 { 208 /* cneg */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15583 { 213 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb },
15584 { 213 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM },
15585 { 213 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass },
15586 { 213 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM },
15587 { 213 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass },
15588 { 213 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2 },
15589 { 267 /* csel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
15590 { 272 /* cset */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15591 { 277 /* csetm */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15592 { 283 /* csinc */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
15593 { 289 /* csinv */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
15594 { 295 /* csneg */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
15595 { 301 /* cx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15596 { 305 /* cx1a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15597 { 310 /* cx1d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15598 { 315 /* cx1da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15599 { 321 /* cx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15600 { 325 /* cx2a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15601 { 330 /* cx2d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15602 { 335 /* cx2da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15603 { 341 /* cx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15604 { 345 /* cx3a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15605 { 350 /* cx3d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15606 { 355 /* cx3da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15607 { 397 /* dmb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB },
15608 { 397 /* dmb */, 3 /* 0, 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB },
15609 { 397 /* dmb */, 6 /* 1, 2 */, MCK_MemBarrierOpt, AMFBS_HasDB },
15610 { 401 /* dsb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB },
15611 { 401 /* dsb */, 3 /* 0, 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB },
15612 { 401 /* dsb */, 6 /* 1, 2 */, MCK_MemBarrierOpt, AMFBS_HasDB },
15613 { 405 /* eor */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15614 { 405 /* eor */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15615 { 444 /* fconstd */, 6 /* 1, 2 */, MCK_FPImm, AMFBS_HasVFP3 },
15616 { 452 /* fconsts */, 6 /* 1, 2 */, MCK_FPImm, AMFBS_HasVFP3 },
15617 { 536 /* isb */, 1 /* 0 */, MCK_InstSyncBarrierOpt, AMFBS_IsARM_HasDB },
15618 { 536 /* isb */, 3 /* 0, 1 */, MCK_InstSyncBarrierOpt, AMFBS_IsThumb_HasDB },
15619 { 536 /* isb */, 6 /* 1, 2 */, MCK_InstSyncBarrierOpt, AMFBS_HasDB },
15620 { 540 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsThumb2 },
15621 { 540 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsARM },
15622 { 589 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15623 { 589 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15624 { 589 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15625 { 589 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15626 { 589 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15627 { 589 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15628 { 589 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15629 { 589 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15630 { 589 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15631 { 589 /* ldc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
15632 { 589 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15633 { 589 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15634 { 589 /* ldc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
15635 { 589 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15636 { 589 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15637 { 589 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15638 { 589 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15639 { 589 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15640 { 593 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15641 { 593 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15642 { 593 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15643 { 593 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15644 { 593 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15645 { 593 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15646 { 593 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15647 { 593 /* ldc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
15648 { 593 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15649 { 593 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15650 { 593 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15651 { 593 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15652 { 593 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15653 { 593 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15654 { 593 /* ldc2 */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15655 { 593 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15656 { 593 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15657 { 593 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15658 { 598 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15659 { 598 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15660 { 598 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15661 { 598 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15662 { 598 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15663 { 598 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15664 { 598 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15665 { 598 /* ldc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
15666 { 598 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15667 { 598 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15668 { 598 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15669 { 598 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15670 { 598 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15671 { 598 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15672 { 598 /* ldc2l */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15673 { 598 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15674 { 598 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15675 { 598 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15676 { 604 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15677 { 604 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15678 { 604 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15679 { 604 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15680 { 604 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15681 { 604 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15682 { 604 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15683 { 604 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15684 { 604 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15685 { 604 /* ldcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
15686 { 604 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15687 { 604 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15688 { 604 /* ldcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
15689 { 604 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15690 { 604 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15691 { 604 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15692 { 604 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15693 { 604 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15694 { 631 /* ldr */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15695 { 635 /* ldrb */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15696 { 640 /* ldrbt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15697 { 646 /* ldrd */, 24 /* 3, 4 */, MCK_AM3Offset, AMFBS_IsARM },
15698 { 678 /* ldrh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
15699 { 683 /* ldrht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15700 { 689 /* ldrsb */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
15701 { 695 /* ldrsbt */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15702 { 702 /* ldrsh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
15703 { 708 /* ldrsht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15704 { 715 /* ldrt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15705 { 746 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15706 { 746 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15707 { 746 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15708 { 746 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15709 { 746 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15710 { 746 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15711 { 746 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15712 { 746 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15713 { 750 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM },
15714 { 750 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM },
15715 { 750 /* mcr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15716 { 750 /* mcr2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15717 { 750 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15718 { 750 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15719 { 750 /* mcr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15720 { 750 /* mcr2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15721 { 755 /* mcrr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15722 { 755 /* mcrr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15723 { 755 /* mcrr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15724 { 755 /* mcrr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15725 { 760 /* mcrr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15726 { 760 /* mcrr2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15727 { 760 /* mcrr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15728 { 760 /* mcrr2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15729 { 774 /* mov */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15730 { 793 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15731 { 793 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15732 { 793 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15733 { 793 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15734 { 793 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15735 { 793 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15736 { 793 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15737 { 793 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15738 { 797 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM },
15739 { 797 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM },
15740 { 797 /* mrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15741 { 797 /* mrc2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15742 { 797 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15743 { 797 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15744 { 797 /* mrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15745 { 797 /* mrc2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15746 { 802 /* mrrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15747 { 802 /* mrrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15748 { 802 /* mrrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15749 { 802 /* mrrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15750 { 807 /* mrrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15751 { 807 /* mrrc2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15752 { 807 /* mrrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15753 { 807 /* mrrc2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15754 { 813 /* mrs */, 6 /* 1, 2 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization },
15755 { 813 /* mrs */, 6 /* 1, 2 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass },
15756 { 813 /* mrs */, 6 /* 1, 2 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization },
15757 { 817 /* msr */, 3 /* 0, 1 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization },
15758 { 817 /* msr */, 3 /* 0, 1 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization },
15759 { 817 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsThumb2_IsNotMClass },
15760 { 817 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass },
15761 { 817 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsARM },
15762 { 817 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsARM },
15763 { 817 /* msr */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
15764 { 825 /* mvn */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15765 { 841 /* orr */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15766 { 841 /* orr */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15767 { 861 /* pkhbt */, 24 /* 3, 4 */, MCK_PKHLSLImm, AMFBS_HasDSP_IsThumb2 },
15768 { 861 /* pkhbt */, 24 /* 3, 4 */, MCK_PKHLSLImm, AMFBS_IsARM_HasV6 },
15769 { 867 /* pkhtb */, 24 /* 3, 4 */, MCK_PKHASRImm, AMFBS_HasDSP_IsThumb2 },
15770 { 867 /* pkhtb */, 24 /* 3, 4 */, MCK_PKHASRImm, AMFBS_IsARM_HasV6 },
15771 { 1012 /* rsb */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15772 { 1012 /* rsb */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15773 { 1016 /* rsc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15774 { 1016 /* rsc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15775 { 1041 /* sbc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15776 { 1041 /* sbc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15777 { 1059 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsThumb_IsNotMClass },
15778 { 1059 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsARM },
15779 { 1522 /* ssat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsThumb2 },
15780 { 1522 /* ssat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 },
15781 { 1557 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15782 { 1557 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15783 { 1557 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15784 { 1557 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15785 { 1557 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15786 { 1557 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15787 { 1557 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15788 { 1557 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15789 { 1557 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15790 { 1557 /* stc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
15791 { 1557 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15792 { 1557 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15793 { 1557 /* stc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
15794 { 1557 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15795 { 1557 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15796 { 1557 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15797 { 1557 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15798 { 1557 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15799 { 1561 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15800 { 1561 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15801 { 1561 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15802 { 1561 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15803 { 1561 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15804 { 1561 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15805 { 1561 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15806 { 1561 /* stc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
15807 { 1561 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15808 { 1561 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15809 { 1561 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15810 { 1561 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15811 { 1561 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15812 { 1561 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15813 { 1561 /* stc2 */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15814 { 1561 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15815 { 1561 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15816 { 1561 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15817 { 1566 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15818 { 1566 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15819 { 1566 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15820 { 1566 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15821 { 1566 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15822 { 1566 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15823 { 1566 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15824 { 1566 /* stc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
15825 { 1566 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15826 { 1566 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15827 { 1566 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15828 { 1566 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15829 { 1566 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15830 { 1566 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15831 { 1566 /* stc2l */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15832 { 1566 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15833 { 1566 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15834 { 1566 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15835 { 1572 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15836 { 1572 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15837 { 1572 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15838 { 1572 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15839 { 1572 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15840 { 1572 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15841 { 1572 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15842 { 1572 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15843 { 1572 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15844 { 1572 /* stcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
15845 { 1572 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15846 { 1572 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15847 { 1572 /* stcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
15848 { 1572 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15849 { 1572 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15850 { 1572 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15851 { 1572 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15852 { 1572 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15853 { 1640 /* str */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15854 { 1644 /* strb */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15855 { 1649 /* strbt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15856 { 1655 /* strd */, 24 /* 3, 4 */, MCK_AM3Offset, AMFBS_IsARM },
15857 { 1687 /* strh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
15858 { 1692 /* strht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15859 { 1698 /* strt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15860 { 1703 /* sub */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15861 { 1703 /* sub */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15862 { 1730 /* sxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15863 { 1730 /* sxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15864 { 1736 /* sxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15865 { 1736 /* sxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15866 { 1744 /* sxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15867 { 1744 /* sxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15868 { 1750 /* sxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
15869 { 1750 /* sxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15870 { 1750 /* sxtb */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
15871 { 1755 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15872 { 1755 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15873 { 1755 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15874 { 1762 /* sxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
15875 { 1762 /* sxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15876 { 1762 /* sxth */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
15877 { 1775 /* teq */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
15878 { 1784 /* tsb */, 1 /* 0 */, MCK_TraceSyncBarrierOpt, AMFBS_IsARM_HasV8_4a },
15879 { 1784 /* tsb */, 3 /* 0, 1 */, MCK_TraceSyncBarrierOpt, AMFBS_IsThumb_HasV8_4a },
15880 { 1788 /* tst */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
15881 { 1996 /* usat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsThumb2 },
15882 { 1996 /* usat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 },
15883 { 2026 /* uxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15884 { 2026 /* uxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15885 { 2032 /* uxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15886 { 2032 /* uxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15887 { 2040 /* uxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15888 { 2040 /* uxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15889 { 2046 /* uxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
15890 { 2046 /* uxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15891 { 2046 /* uxtb */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
15892 { 2051 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15893 { 2051 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15894 { 2051 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15895 { 2058 /* uxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
15896 { 2058 /* uxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15897 { 2058 /* uxth */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
15898 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
15899 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
15900 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
15901 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
15902 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
15903 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
15904 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
15905 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
15906 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
15907 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
15908 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
15909 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
15910 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
15911 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
15912 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
15913 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
15914 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
15915 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
15916 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
15917 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
15918 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
15919 { 2261 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
15920 { 2335 /* vcx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15921 { 2335 /* vcx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15922 { 2335 /* vcx1 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
15923 { 2340 /* vcx1a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15924 { 2340 /* vcx1a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15925 { 2340 /* vcx1a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
15926 { 2346 /* vcx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15927 { 2346 /* vcx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15928 { 2346 /* vcx2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
15929 { 2351 /* vcx2a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15930 { 2351 /* vcx2a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15931 { 2351 /* vcx2a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
15932 { 2357 /* vcx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15933 { 2357 /* vcx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15934 { 2357 /* vcx3 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
15935 { 2362 /* vcx3a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15936 { 2362 /* vcx3a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
15937 { 2362 /* vcx3a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
15938 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
15939 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15940 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15941 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
15942 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15943 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
15944 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15945 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
15946 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15947 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15948 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
15949 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15950 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
15951 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15952 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15953 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15954 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15955 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15956 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
15957 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15958 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15959 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
15960 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15961 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
15962 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15963 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
15964 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
15965 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15966 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15967 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15968 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15969 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
15970 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
15971 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15972 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15973 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
15974 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
15975 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15976 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15977 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
15978 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
15979 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15980 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15981 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15982 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15983 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
15984 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
15985 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15986 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15987 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
15988 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
15989 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15990 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15991 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15992 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
15993 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15994 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
15995 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15996 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
15997 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15998 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
15999 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16000 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16001 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16002 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16003 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16004 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16005 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16006 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16007 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16008 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16009 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16010 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16011 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16012 { 2501 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16013 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16014 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16015 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16016 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16017 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16018 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16019 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16020 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16021 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16022 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16023 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16024 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16025 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16026 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16027 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16028 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16029 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16030 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16031 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16032 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16033 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16034 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16035 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16036 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16037 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16038 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16039 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16040 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16041 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16042 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16043 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16044 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16045 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16046 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16047 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16048 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16049 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16050 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16051 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16052 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16053 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16054 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16055 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16056 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16057 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16058 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16059 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16060 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16061 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16062 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16063 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16064 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16065 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16066 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16067 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16068 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16069 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16070 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16071 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16072 { 2506 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16073 { 2511 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16074 { 2511 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16075 { 2511 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16076 { 2511 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16077 { 2511 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16078 { 2511 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16079 { 2517 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16080 { 2517 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16081 { 2517 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16082 { 2517 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16083 { 2517 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16084 { 2517 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16085 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16086 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16087 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16088 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16089 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16090 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16091 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16092 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16093 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16094 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16095 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16096 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16097 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16098 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16099 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16100 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16101 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16102 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16103 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16104 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16105 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16106 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16107 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16108 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16109 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16110 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16111 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16112 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16113 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16114 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16115 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16116 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16117 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16118 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16119 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16120 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16121 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16122 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16123 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16124 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16125 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16126 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16127 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16128 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16129 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16130 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16131 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16132 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16133 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16134 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16135 { 2523 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16136 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16137 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16138 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16139 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16140 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16141 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16142 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16143 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16144 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16145 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16146 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16147 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16148 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16149 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16150 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16151 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16152 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16153 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16154 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16155 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16156 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16157 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16158 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16159 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16160 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16161 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16162 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16163 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16164 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16165 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16166 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16167 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16168 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16169 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16170 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16171 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16172 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16173 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16174 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16175 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16176 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16177 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16178 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16179 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16180 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16181 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16182 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16183 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16184 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16185 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16186 { 2528 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16187 { 2533 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16188 { 2533 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16189 { 2533 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16190 { 2533 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16191 { 2533 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16192 { 2533 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16193 { 2539 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16194 { 2539 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16195 { 2539 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16196 { 2539 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16197 { 2539 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16198 { 2539 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16199 { 2545 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16200 { 2545 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16201 { 2545 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16202 { 2545 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16203 { 2545 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16204 { 2545 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16205 { 2551 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16206 { 2551 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16207 { 2551 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16208 { 2551 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16209 { 2551 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16210 { 2551 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16211 { 2938 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasNEON },
16212 { 2938 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasNEON },
16213 { 2938 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasVFP3 },
16214 { 2938 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasVFP3_HasDPVFP },
16215 { 2938 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasFullFP16 },
16216 { 2938 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasMVEInt },
16217 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16218 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16219 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16220 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16221 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16222 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16223 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16224 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16225 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16226 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16227 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16228 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16229 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16230 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16231 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16232 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16233 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16234 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16235 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16236 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16237 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16238 { 3122 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16239 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16240 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16241 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16242 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16243 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16244 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16245 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16246 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16247 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16248 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16249 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16250 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16251 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16252 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16253 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16254 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16255 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16256 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16257 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16258 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16259 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16260 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16261 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16262 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16263 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16264 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16265 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16266 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16267 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16268 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16269 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16270 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16271 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16272 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16273 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16274 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16275 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16276 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16277 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16278 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16279 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16280 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16281 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16282 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16283 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16284 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16285 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16286 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16287 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16288 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16289 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16290 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16291 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16292 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16293 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16294 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16295 { 3936 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16296 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16297 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16298 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16299 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16300 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16301 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16302 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16303 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16304 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16305 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16306 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16307 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16308 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16309 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16310 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16311 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16312 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16313 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16314 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16315 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16316 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16317 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16318 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16319 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16320 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16321 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16322 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16323 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16324 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16325 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16326 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16327 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16328 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16329 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16330 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16331 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16332 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16333 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16334 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16335 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16336 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16337 { 3941 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16338 { 3946 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16339 { 3946 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16340 { 3946 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16341 { 3946 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16342 { 3946 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16343 { 3946 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16344 { 3952 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16345 { 3952 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16346 { 3952 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16347 { 3952 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16348 { 3952 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16349 { 3952 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16350 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16351 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16352 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16353 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16354 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16355 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16356 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16357 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16358 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16359 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16360 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16361 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16362 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16363 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16364 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16365 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16366 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16367 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16368 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16369 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16370 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16371 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16372 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16373 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16374 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16375 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16376 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16377 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16378 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16379 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16380 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16381 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16382 { 3958 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16383 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16384 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16385 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16386 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16387 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16388 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16389 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16390 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16391 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16392 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16393 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16394 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16395 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16396 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16397 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16398 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16399 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16400 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16401 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16402 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16403 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16404 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16405 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16406 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16407 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16408 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16409 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16410 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16411 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16412 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16413 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16414 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16415 { 3963 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16416 { 3968 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16417 { 3968 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16418 { 3968 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16419 { 3968 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16420 { 3968 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16421 { 3968 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16422 { 3974 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16423 { 3974 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16424 { 3974 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16425 { 3974 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16426 { 3974 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16427 { 3974 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16428 { 3980 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16429 { 3980 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16430 { 3980 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16431 { 3980 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16432 { 3980 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16433 { 3980 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16434 { 3986 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16435 { 3986 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16436 { 3986 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16437 { 3986 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16438 { 3986 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16439 { 3986 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16440 { 4071 /* vtbl */, 12 /* 2, 3 */, MCK_VecListDPair, AMFBS_HasNEON },
16441 { 4071 /* vtbl */, 12 /* 2, 3 */, MCK_VecListFourD, AMFBS_HasNEON },
16442 { 4071 /* vtbl */, 12 /* 2, 3 */, MCK_VecListOneD, AMFBS_HasNEON },
16443 { 4071 /* vtbl */, 12 /* 2, 3 */, MCK_VecListThreeD, AMFBS_HasNEON },
16444 { 4076 /* vtbx */, 12 /* 2, 3 */, MCK_VecListDPair, AMFBS_HasNEON },
16445 { 4076 /* vtbx */, 12 /* 2, 3 */, MCK_VecListFourD, AMFBS_HasNEON },
16446 { 4076 /* vtbx */, 12 /* 2, 3 */, MCK_VecListOneD, AMFBS_HasNEON },
16447 { 4076 /* vtbx */, 12 /* 2, 3 */, MCK_VecListThreeD, AMFBS_HasNEON },
16448};
16449
16450ParseStatus ARMAsmParser::
16451tryCustomParseOperand(OperandVector &Operands,
16452 unsigned MCK) {
16453
16454 switch(MCK) {
16455 case MCK_AM3Offset:
16456 return parseAM3Offset(Operands);
16457 case MCK_BankedReg:
16458 return parseBankedRegOperand(Operands);
16459 case MCK_Bitfield:
16460 return parseBitfield(Operands);
16461 case MCK_CoprocNum:
16462 return parseCoprocNumOperand(Operands);
16463 case MCK_CoprocOption:
16464 return parseCoprocOptionOperand(Operands);
16465 case MCK_CoprocReg:
16466 return parseCoprocRegOperand(Operands);
16467 case MCK_FPImm:
16468 return parseFPImm(Operands);
16469 case MCK_InstSyncBarrierOpt:
16470 return parseInstSyncBarrierOptOperand(Operands);
16471 case MCK_MSRMask:
16472 return parseMSRMaskOperand(Operands);
16473 case MCK_MemBarrierOpt:
16474 return parseMemBarrierOptOperand(Operands);
16475 case MCK_ModImm:
16476 return parseModImm(Operands);
16477 case MCK_PKHASRImm:
16478 return parsePKHASRImm(Operands);
16479 case MCK_PKHLSLImm:
16480 return parsePKHLSLImm(Operands);
16481 case MCK_PostIdxReg:
16482 return parsePostIdxReg(Operands);
16483 case MCK_PostIdxRegShifted:
16484 return parsePostIdxReg(Operands);
16485 case MCK_ProcIFlags:
16486 return parseProcIFlagsOperand(Operands);
16487 case MCK_RotImm:
16488 return parseRotImm(Operands);
16489 case MCK_SetEndImm:
16490 return parseSetEndImm(Operands);
16491 case MCK_ShifterImm:
16492 return parseShifterImm(Operands);
16493 case MCK_TraceSyncBarrierOpt:
16494 return parseTraceSyncBarrierOptOperand(Operands);
16495 case MCK_VecListTwoMQ:
16496 return parseVectorList(Operands);
16497 case MCK_VecListFourMQ:
16498 return parseVectorList(Operands);
16499 case MCK_VecListDPairAllLanes:
16500 return parseVectorList(Operands);
16501 case MCK_VecListDPair:
16502 return parseVectorList(Operands);
16503 case MCK_VecListDPairSpacedAllLanes:
16504 return parseVectorList(Operands);
16505 case MCK_VecListDPairSpaced:
16506 return parseVectorList(Operands);
16507 case MCK_VecListFourDAllLanes:
16508 return parseVectorList(Operands);
16509 case MCK_VecListFourD:
16510 return parseVectorList(Operands);
16511 case MCK_VecListFourDByteIndexed:
16512 return parseVectorList(Operands);
16513 case MCK_VecListFourDHWordIndexed:
16514 return parseVectorList(Operands);
16515 case MCK_VecListFourDWordIndexed:
16516 return parseVectorList(Operands);
16517 case MCK_VecListFourQAllLanes:
16518 return parseVectorList(Operands);
16519 case MCK_VecListFourQ:
16520 return parseVectorList(Operands);
16521 case MCK_VecListFourQHWordIndexed:
16522 return parseVectorList(Operands);
16523 case MCK_VecListFourQWordIndexed:
16524 return parseVectorList(Operands);
16525 case MCK_VecListOneDAllLanes:
16526 return parseVectorList(Operands);
16527 case MCK_VecListOneD:
16528 return parseVectorList(Operands);
16529 case MCK_VecListOneDByteIndexed:
16530 return parseVectorList(Operands);
16531 case MCK_VecListOneDHWordIndexed:
16532 return parseVectorList(Operands);
16533 case MCK_VecListOneDWordIndexed:
16534 return parseVectorList(Operands);
16535 case MCK_VecListThreeDAllLanes:
16536 return parseVectorList(Operands);
16537 case MCK_VecListThreeD:
16538 return parseVectorList(Operands);
16539 case MCK_VecListThreeDByteIndexed:
16540 return parseVectorList(Operands);
16541 case MCK_VecListThreeDHWordIndexed:
16542 return parseVectorList(Operands);
16543 case MCK_VecListThreeDWordIndexed:
16544 return parseVectorList(Operands);
16545 case MCK_VecListThreeQAllLanes:
16546 return parseVectorList(Operands);
16547 case MCK_VecListThreeQ:
16548 return parseVectorList(Operands);
16549 case MCK_VecListThreeQHWordIndexed:
16550 return parseVectorList(Operands);
16551 case MCK_VecListThreeQWordIndexed:
16552 return parseVectorList(Operands);
16553 case MCK_VecListTwoDByteIndexed:
16554 return parseVectorList(Operands);
16555 case MCK_VecListTwoDHWordIndexed:
16556 return parseVectorList(Operands);
16557 case MCK_VecListTwoDWordIndexed:
16558 return parseVectorList(Operands);
16559 case MCK_VecListTwoQHWordIndexed:
16560 return parseVectorList(Operands);
16561 case MCK_VecListTwoQWordIndexed:
16562 return parseVectorList(Operands);
16563 case MCK_ITCondCode:
16564 return parseITCondCode(Operands);
16565 case MCK_CondCodeNoAL:
16566 return parseITCondCode(Operands);
16567 case MCK_CondCodeNoALInv:
16568 return parseITCondCode(Operands);
16569 case MCK_CondCodeRestrictedFP:
16570 return parseITCondCode(Operands);
16571 case MCK_CondCodeRestrictedI:
16572 return parseITCondCode(Operands);
16573 case MCK_CondCodeRestrictedS:
16574 return parseITCondCode(Operands);
16575 case MCK_CondCodeRestrictedU:
16576 return parseITCondCode(Operands);
16577 default:
16578 return ParseStatus::NoMatch;
16579 }
16580 return ParseStatus::NoMatch;
16581}
16582
16583ParseStatus ARMAsmParser::
16584MatchOperandParserImpl(OperandVector &Operands,
16585 StringRef Mnemonic,
16586 bool ParseForAllFeatures) {
16587 // Get the current feature set.
16588 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
16589
16590 // Get the next operand index.
16591 unsigned NextOpNum = Operands.size() - 1;
16592 // Search the table.
16593 auto MnemonicRange =
16594 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
16595 Mnemonic, LessOpcodeOperand());
16596
16597 if (MnemonicRange.first == MnemonicRange.second)
16598 return ParseStatus::NoMatch;
16599
16600 for (const OperandMatchEntry *it = MnemonicRange.first,
16601 *ie = MnemonicRange.second; it != ie; ++it) {
16602 // equal_range guarantees that instruction mnemonic matches.
16603 assert(Mnemonic == it->getMnemonic());
16604
16605 // check if the available features match
16606 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
16607 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
16608 continue;
16609
16610 // check if the operand in question has a custom parser.
16611 if (!(it->OperandMask & (1 << NextOpNum)))
16612 continue;
16613
16614 // call custom parse method to handle the operand
16615 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
16616 if (!Result.isNoMatch())
16617 return Result;
16618 }
16619
16620 // Okay, we had no match.
16621 return ParseStatus::NoMatch;
16622}
16623
16624#endif // GET_MATCHER_IMPLEMENTATION
16625
16626
16627#ifdef GET_MNEMONIC_SPELL_CHECKER
16628#undef GET_MNEMONIC_SPELL_CHECKER
16629
16630static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
16631 const unsigned MaxEditDist = 2;
16632 std::vector<StringRef> Candidates;
16633 StringRef Prev = "";
16634
16635 // Find the appropriate table for this asm variant.
16636 const MatchEntry *Start, *End;
16637 switch (VariantID) {
16638 default: llvm_unreachable("invalid variant!");
16639 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
16640 }
16641
16642 for (auto I = Start; I < End; I++) {
16643 // Ignore unsupported instructions.
16644 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
16645 if ((FBS & RequiredFeatures) != RequiredFeatures)
16646 continue;
16647
16648 StringRef T = I->getMnemonic();
16649 // Avoid recomputing the edit distance for the same string.
16650 if (T == Prev)
16651 continue;
16652
16653 Prev = T;
16654 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
16655 if (Dist <= MaxEditDist)
16656 Candidates.push_back(T);
16657 }
16658
16659 if (Candidates.empty())
16660 return "";
16661
16662 std::string Res = ", did you mean: ";
16663 unsigned i = 0;
16664 for (; i < Candidates.size() - 1; i++)
16665 Res += Candidates[i].str() + ", ";
16666 return Res + Candidates[i].str() + "?";
16667}
16668
16669#endif // GET_MNEMONIC_SPELL_CHECKER
16670
16671
16672#ifdef GET_MNEMONIC_CHECKER
16673#undef GET_MNEMONIC_CHECKER
16674
16675static bool ARMCheckMnemonic(StringRef Mnemonic,
16676 const FeatureBitset &AvailableFeatures,
16677 unsigned VariantID) {
16678 // Process all MnemonicAliases to remap the mnemonic.
16679 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
16680
16681 // Find the appropriate table for this asm variant.
16682 const MatchEntry *Start, *End;
16683 switch (VariantID) {
16684 default: llvm_unreachable("invalid variant!");
16685 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
16686 }
16687
16688 // Search the table.
16689 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
16690
16691 if (MnemonicRange.first == MnemonicRange.second)
16692 return false;
16693
16694 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
16695 it != ie; ++it) {
16696 const FeatureBitset &RequiredFeatures =
16697 FeatureBitsets[it->RequiredFeaturesIdx];
16698 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
16699 return true;
16700 }
16701 return false;
16702}
16703
16704#endif // GET_MNEMONIC_CHECKER
16705
16706