1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, CCState &State);
26bool llvm::CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
29bool llvm::FastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, CCState &State);
32bool llvm::RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, CCState &State);
35static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
38bool llvm::RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, CCState &State);
41bool llvm::RetCC_ARM_APCS(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, CCState &State);
44bool llvm::RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, CCState &State);
47
48
49bool llvm::CC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
50 MVT LocVT, CCValAssign::LocInfo LocInfo,
51 ISD::ArgFlagsTy ArgFlags, CCState &State) {
52
53 if (ArgFlags.isByVal()) {
54 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
55 return false;
56 }
57
58 if (ArgFlags.isNest()) {
59 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R12)) {
60 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
61 return false;
62 }
63 }
64
65 if (LocVT == MVT::v1i64 ||
66 LocVT == MVT::v2i32 ||
67 LocVT == MVT::v4i16 ||
68 LocVT == MVT::v4f16 ||
69 LocVT == MVT::v4bf16 ||
70 LocVT == MVT::v8i8 ||
71 LocVT == MVT::v2f32) {
72 LocVT = MVT::f64;
73 LocInfo = CCValAssign::BCvt;
74 }
75
76 if (LocVT == MVT::v2i64 ||
77 LocVT == MVT::v4i32 ||
78 LocVT == MVT::v8i16 ||
79 LocVT == MVT::v8f16 ||
80 LocVT == MVT::v8bf16 ||
81 LocVT == MVT::v16i8 ||
82 LocVT == MVT::v4f32) {
83 LocVT = MVT::v2f64;
84 LocInfo = CCValAssign::BCvt;
85 }
86
87 if (ArgFlags.isSwiftSelf()) {
88 if (LocVT == MVT::i32) {
89 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
90 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
91 return false;
92 }
93 }
94 }
95
96 if (ArgFlags.isSwiftError()) {
97 if (LocVT == MVT::i32) {
98 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
99 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
100 return false;
101 }
102 }
103 }
104
105 if (LocVT == MVT::f64 ||
106 LocVT == MVT::v2f64) {
107 if (CC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
108 return false;
109 }
110
111 if (LocVT == MVT::f32) {
112 LocVT = MVT::i32;
113 LocInfo = CCValAssign::BCvt;
114 }
115
116 if (LocVT == MVT::f16 ||
117 LocVT == MVT::bf16) {
118 if (CC_ARM_AAPCS_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
119 return false;
120 }
121
122 if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
123 return false;
124
125 return true; // CC didn't match.
126}
127
128
129static bool CC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
130 MVT LocVT, CCValAssign::LocInfo LocInfo,
131 ISD::ArgFlagsTy ArgFlags, CCState &State) {
132
133 if (LocVT == MVT::i1 ||
134 LocVT == MVT::i8 ||
135 LocVT == MVT::i16) {
136 LocVT = MVT::i32;
137 if (ArgFlags.isSExt())
138 LocInfo = CCValAssign::SExt;
139 else if (ArgFlags.isZExt())
140 LocInfo = CCValAssign::ZExt;
141 else
142 LocInfo = CCValAssign::AExt;
143 }
144
145 if (LocVT == MVT::i32) {
146 if (ArgFlags.getNonZeroOrigAlign() == 8) {
147 static const MCPhysReg RegList1[] = {
148 ARM::R0, ARM::R2
149 };
150 static const MCPhysReg RegList2[] = {
151 ARM::R0, ARM::R1
152 };
153 if (MCRegister Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
154 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
155 return false;
156 }
157 }
158 }
159
160 if (LocVT == MVT::i32) {
161 if (ArgFlags.getNonZeroOrigAlign() != Align(8)) {
162 static const MCPhysReg RegList3[] = {
163 ARM::R0, ARM::R1, ARM::R2, ARM::R3
164 };
165 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
166 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
167 return false;
168 }
169 }
170 }
171
172 if (LocVT == MVT::i32) {
173 if (ArgFlags.getNonZeroOrigAlign() == 8) {
174 static const MCPhysReg ShadowRegList4[] = {
175 ARM::R0, ARM::R1, ARM::R2, ARM::R3
176 };
177 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(8), ShadowRegs: ShadowRegList4);
178 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
179 return false;
180 }
181 }
182
183 if (LocVT == MVT::i32) {
184 static const MCPhysReg ShadowRegList6[] = {
185 ARM::R0, ARM::R1, ARM::R2, ARM::R3
186 };
187 int64_t Offset7 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList6);
188 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
189 return false;
190 }
191
192 if (LocVT == MVT::f32) {
193 static const MCPhysReg ShadowRegList8[] = {
194 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
195 };
196 int64_t Offset9 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList8);
197 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
198 return false;
199 }
200
201 if (LocVT == MVT::f16 ||
202 LocVT == MVT::bf16) {
203 if (CC_ARM_AAPCS_Common_Custom_f16_Stack(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
204 return false;
205 }
206
207 if (LocVT == MVT::f64) {
208 static const MCPhysReg ShadowRegList10[] = {
209 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
210 };
211 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8), ShadowRegs: ShadowRegList10);
212 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
213 return false;
214 }
215
216 if (LocVT == MVT::v2f64) {
217 if (ArgFlags.getNonZeroOrigAlign() == 16) {
218 static const MCPhysReg ShadowRegList12[] = {
219 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
220 };
221 int64_t Offset13 = State.AllocateStack(Size: 16, Alignment: Align(16), ShadowRegs: ShadowRegList12);
222 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
223 return false;
224 }
225 }
226
227 if (LocVT == MVT::v2f64) {
228 static const MCPhysReg ShadowRegList14[] = {
229 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
230 };
231 int64_t Offset15 = State.AllocateStack(Size: 16, Alignment: Align(8), ShadowRegs: ShadowRegList14);
232 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
233 return false;
234 }
235
236 return true; // CC didn't match.
237}
238
239
240bool llvm::CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
241 MVT LocVT, CCValAssign::LocInfo LocInfo,
242 ISD::ArgFlagsTy ArgFlags, CCState &State) {
243
244 if (ArgFlags.isByVal()) {
245 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
246 return false;
247 }
248
249 if (LocVT == MVT::v1i64 ||
250 LocVT == MVT::v2i32 ||
251 LocVT == MVT::v4i16 ||
252 LocVT == MVT::v4f16 ||
253 LocVT == MVT::v4bf16 ||
254 LocVT == MVT::v8i8 ||
255 LocVT == MVT::v2f32) {
256 LocVT = MVT::f64;
257 LocInfo = CCValAssign::BCvt;
258 }
259
260 if (LocVT == MVT::v2i64 ||
261 LocVT == MVT::v4i32 ||
262 LocVT == MVT::v8i16 ||
263 LocVT == MVT::v8f16 ||
264 LocVT == MVT::v8bf16 ||
265 LocVT == MVT::v16i8 ||
266 LocVT == MVT::v4f32) {
267 LocVT = MVT::v2f64;
268 LocInfo = CCValAssign::BCvt;
269 }
270
271 if (ArgFlags.isSwiftSelf()) {
272 if (LocVT == MVT::i32) {
273 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
274 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
275 return false;
276 }
277 }
278 }
279
280 if (ArgFlags.isSwiftError()) {
281 if (LocVT == MVT::i32) {
282 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
283 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
284 return false;
285 }
286 }
287 }
288
289 if (ArgFlags.isInConsecutiveRegs()) {
290 if (CC_ARM_AAPCS_Custom_Aggregate(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
291 return false;
292 }
293
294 if (LocVT == MVT::v2f64) {
295 static const MCPhysReg RegList1[] = {
296 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
297 };
298 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
299 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
300 return false;
301 }
302 }
303
304 if (LocVT == MVT::f64) {
305 static const MCPhysReg RegList2[] = {
306 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
307 };
308 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
309 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
310 return false;
311 }
312 }
313
314 if (LocVT == MVT::f32) {
315 static const MCPhysReg RegList3[] = {
316 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
317 };
318 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
319 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
320 return false;
321 }
322 }
323
324 if (LocVT == MVT::f16 ||
325 LocVT == MVT::bf16) {
326 if (CC_ARM_AAPCS_VFP_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
327 return false;
328 }
329
330 if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331 return false;
332
333 return true; // CC didn't match.
334}
335
336
337bool llvm::CC_ARM_APCS(unsigned ValNo, MVT ValVT,
338 MVT LocVT, CCValAssign::LocInfo LocInfo,
339 ISD::ArgFlagsTy ArgFlags, CCState &State) {
340
341 if (ArgFlags.isByVal()) {
342 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 4, MinAlign: Align(4), ArgFlags);
343 return false;
344 }
345
346 if (LocVT == MVT::i1 ||
347 LocVT == MVT::i8 ||
348 LocVT == MVT::i16) {
349 LocVT = MVT::i32;
350 if (ArgFlags.isSExt())
351 LocInfo = CCValAssign::SExt;
352 else if (ArgFlags.isZExt())
353 LocInfo = CCValAssign::ZExt;
354 else
355 LocInfo = CCValAssign::AExt;
356 }
357
358 if (ArgFlags.isSwiftSelf()) {
359 if (LocVT == MVT::i32) {
360 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
361 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
362 return false;
363 }
364 }
365 }
366
367 if (ArgFlags.isSwiftError()) {
368 if (LocVT == MVT::i32) {
369 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
370 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
371 return false;
372 }
373 }
374 }
375
376 if (LocVT == MVT::v1i64 ||
377 LocVT == MVT::v2i32 ||
378 LocVT == MVT::v4i16 ||
379 LocVT == MVT::v4f16 ||
380 LocVT == MVT::v4bf16 ||
381 LocVT == MVT::v8i8 ||
382 LocVT == MVT::v2f32) {
383 LocVT = MVT::f64;
384 LocInfo = CCValAssign::BCvt;
385 }
386
387 if (LocVT == MVT::v2i64 ||
388 LocVT == MVT::v4i32 ||
389 LocVT == MVT::v8i16 ||
390 LocVT == MVT::v8f16 ||
391 LocVT == MVT::v8bf16 ||
392 LocVT == MVT::v16i8 ||
393 LocVT == MVT::v4f32) {
394 LocVT = MVT::v2f64;
395 LocInfo = CCValAssign::BCvt;
396 }
397
398 if (LocVT == MVT::f64 ||
399 LocVT == MVT::v2f64) {
400 if (CC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
401 return false;
402 }
403
404 if (LocVT == MVT::f32) {
405 LocVT = MVT::i32;
406 LocInfo = CCValAssign::BCvt;
407 }
408
409 if (LocVT == MVT::i32) {
410 static const MCPhysReg RegList1[] = {
411 ARM::R0, ARM::R1, ARM::R2, ARM::R3
412 };
413 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
414 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
415 return false;
416 }
417 }
418
419 if (LocVT == MVT::i32) {
420 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
421 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
422 return false;
423 }
424
425 if (LocVT == MVT::f64) {
426 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(4));
427 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
428 return false;
429 }
430
431 if (LocVT == MVT::v2f64) {
432 int64_t Offset4 = State.AllocateStack(Size: 16, Alignment: Align(4));
433 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
434 return false;
435 }
436
437 return true; // CC didn't match.
438}
439
440
441bool llvm::CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT,
442 MVT LocVT, CCValAssign::LocInfo LocInfo,
443 ISD::ArgFlagsTy ArgFlags, CCState &State) {
444
445 if (LocVT == MVT::v1i64 ||
446 LocVT == MVT::v2i32 ||
447 LocVT == MVT::v4i16 ||
448 LocVT == MVT::v4f16 ||
449 LocVT == MVT::v4bf16 ||
450 LocVT == MVT::v8i8 ||
451 LocVT == MVT::v2f32) {
452 LocVT = MVT::f64;
453 LocInfo = CCValAssign::BCvt;
454 }
455
456 if (LocVT == MVT::v2i64 ||
457 LocVT == MVT::v4i32 ||
458 LocVT == MVT::v8i16 ||
459 LocVT == MVT::v8f16 ||
460 LocVT == MVT::v8bf16 ||
461 LocVT == MVT::v16i8 ||
462 LocVT == MVT::v4f32) {
463 LocVT = MVT::v2f64;
464 LocInfo = CCValAssign::BCvt;
465 }
466
467 if (LocVT == MVT::v2f64) {
468 static const MCPhysReg RegList1[] = {
469 ARM::Q4, ARM::Q5
470 };
471 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
472 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
473 return false;
474 }
475 }
476
477 if (LocVT == MVT::f64) {
478 static const MCPhysReg RegList2[] = {
479 ARM::D8, ARM::D9, ARM::D10, ARM::D11
480 };
481 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
482 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
483 return false;
484 }
485 }
486
487 if (LocVT == MVT::f32) {
488 static const MCPhysReg RegList3[] = {
489 ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23
490 };
491 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
492 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
493 return false;
494 }
495 }
496
497 if (LocVT == MVT::i8 ||
498 LocVT == MVT::i16) {
499 LocVT = MVT::i32;
500 if (ArgFlags.isSExt())
501 LocInfo = CCValAssign::SExt;
502 else if (ArgFlags.isZExt())
503 LocInfo = CCValAssign::ZExt;
504 else
505 LocInfo = CCValAssign::AExt;
506 }
507
508 if (LocVT == MVT::i32) {
509 static const MCPhysReg RegList4[] = {
510 ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11
511 };
512 if (MCRegister Reg = State.AllocateReg(Regs: RegList4)) {
513 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
514 return false;
515 }
516 }
517
518 return true; // CC didn't match.
519}
520
521
522bool llvm::CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT,
523 MVT LocVT, CCValAssign::LocInfo LocInfo,
524 ISD::ArgFlagsTy ArgFlags, CCState &State) {
525
526 if (LocVT == MVT::i32) {
527 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R0)) {
528 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
529 return false;
530 }
531 }
532
533 return true; // CC didn't match.
534}
535
536
537bool llvm::FastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
538 MVT LocVT, CCValAssign::LocInfo LocInfo,
539 ISD::ArgFlagsTy ArgFlags, CCState &State) {
540
541 if (LocVT == MVT::v1i64 ||
542 LocVT == MVT::v2i32 ||
543 LocVT == MVT::v4i16 ||
544 LocVT == MVT::v4f16 ||
545 LocVT == MVT::v4bf16 ||
546 LocVT == MVT::v8i8 ||
547 LocVT == MVT::v2f32) {
548 LocVT = MVT::f64;
549 LocInfo = CCValAssign::BCvt;
550 }
551
552 if (LocVT == MVT::v2i64 ||
553 LocVT == MVT::v4i32 ||
554 LocVT == MVT::v8i16 ||
555 LocVT == MVT::v8f16 ||
556 LocVT == MVT::v8bf16 ||
557 LocVT == MVT::v16i8 ||
558 LocVT == MVT::v4f32) {
559 LocVT = MVT::v2f64;
560 LocInfo = CCValAssign::BCvt;
561 }
562
563 if (LocVT == MVT::v2f64) {
564 static const MCPhysReg RegList1[] = {
565 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
566 };
567 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
568 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
569 return false;
570 }
571 }
572
573 if (LocVT == MVT::f64) {
574 static const MCPhysReg RegList2[] = {
575 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
576 };
577 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
578 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
579 return false;
580 }
581 }
582
583 if (LocVT == MVT::f32) {
584 static const MCPhysReg RegList3[] = {
585 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
586 };
587 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
588 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
589 return false;
590 }
591 }
592
593 if (LocVT == MVT::f32) {
594 static const MCPhysReg ShadowRegList4[] = {
595 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
596 };
597 int64_t Offset5 = State.AllocateStack(Size: 4, Alignment: Align(4), ShadowRegs: ShadowRegList4);
598 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset5, LocVT, HTP: LocInfo));
599 return false;
600 }
601
602 if (LocVT == MVT::f64) {
603 static const MCPhysReg ShadowRegList6[] = {
604 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
605 };
606 int64_t Offset7 = State.AllocateStack(Size: 8, Alignment: Align(4), ShadowRegs: ShadowRegList6);
607 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset7, LocVT, HTP: LocInfo));
608 return false;
609 }
610
611 if (LocVT == MVT::v2f64) {
612 static const MCPhysReg ShadowRegList8[] = {
613 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
614 };
615 int64_t Offset9 = State.AllocateStack(Size: 16, Alignment: Align(4), ShadowRegs: ShadowRegList8);
616 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset9, LocVT, HTP: LocInfo));
617 return false;
618 }
619
620 if (!CC_ARM_APCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
621 return false;
622
623 return true; // CC didn't match.
624}
625
626
627bool llvm::RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT,
628 MVT LocVT, CCValAssign::LocInfo LocInfo,
629 ISD::ArgFlagsTy ArgFlags, CCState &State) {
630
631 if (LocVT == MVT::v1i64 ||
632 LocVT == MVT::v2i32 ||
633 LocVT == MVT::v4i16 ||
634 LocVT == MVT::v4f16 ||
635 LocVT == MVT::v4bf16 ||
636 LocVT == MVT::v8i8 ||
637 LocVT == MVT::v2f32) {
638 LocVT = MVT::f64;
639 LocInfo = CCValAssign::BCvt;
640 }
641
642 if (LocVT == MVT::v2i64 ||
643 LocVT == MVT::v4i32 ||
644 LocVT == MVT::v8i16 ||
645 LocVT == MVT::v8f16 ||
646 LocVT == MVT::v8bf16 ||
647 LocVT == MVT::v16i8 ||
648 LocVT == MVT::v4f32) {
649 LocVT = MVT::v2f64;
650 LocInfo = CCValAssign::BCvt;
651 }
652
653 if (ArgFlags.isSwiftSelf()) {
654 if (LocVT == MVT::i32) {
655 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
656 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
657 return false;
658 }
659 }
660 }
661
662 if (ArgFlags.isSwiftError()) {
663 if (LocVT == MVT::i32) {
664 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
665 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
666 return false;
667 }
668 }
669 }
670
671 if (LocVT == MVT::f64 ||
672 LocVT == MVT::v2f64) {
673 if (RetCC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
674 return false;
675 }
676
677 if (LocVT == MVT::f32) {
678 LocVT = MVT::i32;
679 LocInfo = CCValAssign::BCvt;
680 }
681
682 if (LocVT == MVT::f16 ||
683 LocVT == MVT::bf16) {
684 if (CC_ARM_AAPCS_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
685 return false;
686 }
687
688 if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
689 return false;
690
691 return true; // CC didn't match.
692}
693
694
695static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, MVT ValVT,
696 MVT LocVT, CCValAssign::LocInfo LocInfo,
697 ISD::ArgFlagsTy ArgFlags, CCState &State) {
698
699 if (LocVT == MVT::i1 ||
700 LocVT == MVT::i8 ||
701 LocVT == MVT::i16) {
702 LocVT = MVT::i32;
703 if (ArgFlags.isSExt())
704 LocInfo = CCValAssign::SExt;
705 else if (ArgFlags.isZExt())
706 LocInfo = CCValAssign::ZExt;
707 else
708 LocInfo = CCValAssign::AExt;
709 }
710
711 if (LocVT == MVT::i32) {
712 static const MCPhysReg RegList1[] = {
713 ARM::R0, ARM::R1, ARM::R2, ARM::R3
714 };
715 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
716 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
717 return false;
718 }
719 }
720
721 if (LocVT == MVT::i64) {
722 static const MCPhysReg RegList2[] = {
723 ARM::R0, ARM::R2
724 };
725 static const MCPhysReg RegList3[] = {
726 ARM::R1, ARM::R3
727 };
728 if (MCRegister Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
729 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
730 return false;
731 }
732 }
733
734 return true; // CC didn't match.
735}
736
737
738bool llvm::RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT,
739 MVT LocVT, CCValAssign::LocInfo LocInfo,
740 ISD::ArgFlagsTy ArgFlags, CCState &State) {
741
742 if (LocVT == MVT::v1i64 ||
743 LocVT == MVT::v2i32 ||
744 LocVT == MVT::v4i16 ||
745 LocVT == MVT::v4f16 ||
746 LocVT == MVT::v4bf16 ||
747 LocVT == MVT::v8i8 ||
748 LocVT == MVT::v2f32) {
749 LocVT = MVT::f64;
750 LocInfo = CCValAssign::BCvt;
751 }
752
753 if (LocVT == MVT::v2i64 ||
754 LocVT == MVT::v4i32 ||
755 LocVT == MVT::v8i16 ||
756 LocVT == MVT::v8f16 ||
757 LocVT == MVT::v8bf16 ||
758 LocVT == MVT::v16i8 ||
759 LocVT == MVT::v4f32) {
760 LocVT = MVT::v2f64;
761 LocInfo = CCValAssign::BCvt;
762 }
763
764 if (ArgFlags.isSwiftSelf()) {
765 if (LocVT == MVT::i32) {
766 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
767 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
768 return false;
769 }
770 }
771 }
772
773 if (ArgFlags.isSwiftError()) {
774 if (LocVT == MVT::i32) {
775 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
776 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
777 return false;
778 }
779 }
780 }
781
782 if (LocVT == MVT::v2f64) {
783 static const MCPhysReg RegList1[] = {
784 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
785 };
786 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
787 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
788 return false;
789 }
790 }
791
792 if (LocVT == MVT::f64) {
793 static const MCPhysReg RegList2[] = {
794 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
795 };
796 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
797 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
798 return false;
799 }
800 }
801
802 if (LocVT == MVT::f32) {
803 static const MCPhysReg RegList3[] = {
804 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
805 };
806 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
807 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
808 return false;
809 }
810 }
811
812 if (LocVT == MVT::f16 ||
813 LocVT == MVT::bf16) {
814 if (CC_ARM_AAPCS_VFP_Custom_f16(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
815 return false;
816 }
817
818 if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
819 return false;
820
821 return true; // CC didn't match.
822}
823
824
825bool llvm::RetCC_ARM_APCS(unsigned ValNo, MVT ValVT,
826 MVT LocVT, CCValAssign::LocInfo LocInfo,
827 ISD::ArgFlagsTy ArgFlags, CCState &State) {
828
829 if (LocVT == MVT::i1 ||
830 LocVT == MVT::i8 ||
831 LocVT == MVT::i16) {
832 LocVT = MVT::i32;
833 if (ArgFlags.isSExt())
834 LocInfo = CCValAssign::SExt;
835 else if (ArgFlags.isZExt())
836 LocInfo = CCValAssign::ZExt;
837 else
838 LocInfo = CCValAssign::AExt;
839 }
840
841 if (LocVT == MVT::f32) {
842 LocVT = MVT::i32;
843 LocInfo = CCValAssign::BCvt;
844 }
845
846 if (ArgFlags.isSwiftSelf()) {
847 if (LocVT == MVT::i32) {
848 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R10)) {
849 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
850 return false;
851 }
852 }
853 }
854
855 if (ArgFlags.isSwiftError()) {
856 if (LocVT == MVT::i32) {
857 if (MCRegister Reg = State.AllocateReg(Reg: ARM::R8)) {
858 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
859 return false;
860 }
861 }
862 }
863
864 if (LocVT == MVT::v1i64 ||
865 LocVT == MVT::v2i32 ||
866 LocVT == MVT::v4i16 ||
867 LocVT == MVT::v4f16 ||
868 LocVT == MVT::v4bf16 ||
869 LocVT == MVT::v8i8 ||
870 LocVT == MVT::v2f32) {
871 LocVT = MVT::f64;
872 LocInfo = CCValAssign::BCvt;
873 }
874
875 if (LocVT == MVT::v2i64 ||
876 LocVT == MVT::v4i32 ||
877 LocVT == MVT::v8i16 ||
878 LocVT == MVT::v8f16 ||
879 LocVT == MVT::v8bf16 ||
880 LocVT == MVT::v16i8 ||
881 LocVT == MVT::v4f32) {
882 LocVT = MVT::v2f64;
883 LocInfo = CCValAssign::BCvt;
884 }
885
886 if (LocVT == MVT::f64 ||
887 LocVT == MVT::v2f64) {
888 if (RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
889 return false;
890 }
891
892 if (LocVT == MVT::i32) {
893 static const MCPhysReg RegList1[] = {
894 ARM::R0, ARM::R1, ARM::R2, ARM::R3
895 };
896 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
897 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
898 return false;
899 }
900 }
901
902 if (LocVT == MVT::i64) {
903 static const MCPhysReg RegList2[] = {
904 ARM::R0, ARM::R2
905 };
906 static const MCPhysReg RegList3[] = {
907 ARM::R1, ARM::R3
908 };
909 if (MCRegister Reg = State.AllocateReg(Regs: RegList2, ShadowRegs: RegList3)) {
910 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
911 return false;
912 }
913 }
914
915 return true; // CC didn't match.
916}
917
918
919bool llvm::RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT,
920 MVT LocVT, CCValAssign::LocInfo LocInfo,
921 ISD::ArgFlagsTy ArgFlags, CCState &State) {
922
923 if (LocVT == MVT::v1i64 ||
924 LocVT == MVT::v2i32 ||
925 LocVT == MVT::v4i16 ||
926 LocVT == MVT::v4f16 ||
927 LocVT == MVT::v4bf16 ||
928 LocVT == MVT::v8i8 ||
929 LocVT == MVT::v2f32) {
930 LocVT = MVT::f64;
931 LocInfo = CCValAssign::BCvt;
932 }
933
934 if (LocVT == MVT::v2i64 ||
935 LocVT == MVT::v4i32 ||
936 LocVT == MVT::v8i16 ||
937 LocVT == MVT::v8f16 ||
938 LocVT == MVT::v8bf16 ||
939 LocVT == MVT::v16i8 ||
940 LocVT == MVT::v4f32) {
941 LocVT = MVT::v2f64;
942 LocInfo = CCValAssign::BCvt;
943 }
944
945 if (LocVT == MVT::v2f64) {
946 static const MCPhysReg RegList1[] = {
947 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
948 };
949 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
950 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
951 return false;
952 }
953 }
954
955 if (LocVT == MVT::f64) {
956 static const MCPhysReg RegList2[] = {
957 ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
958 };
959 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
960 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
961 return false;
962 }
963 }
964
965 if (LocVT == MVT::f32) {
966 static const MCPhysReg RegList3[] = {
967 ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
968 };
969 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
970 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
971 return false;
972 }
973 }
974
975 if (!RetCC_ARM_APCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
976 return false;
977
978 return true; // CC didn't match.
979}
980
981#else
982
983const MCRegister CC_ARM_AAPCS_ArgRegs[] = { ARM::R12 };
984const MCRegister CC_ARM_AAPCS_Common_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
985const MCRegister CC_ARM_AAPCS_VFP_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
986const MCRegister CC_ARM_APCS_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
987const MCRegister CC_ARM_APCS_GHC_ArgRegs[] = { ARM::D10, ARM::D11, ARM::D8, ARM::D9, ARM::Q4, ARM::Q5, ARM::R10, ARM::R11, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23 };
988const MCRegister CC_ARM_Win32_CFGuard_Check_ArgRegs[] = { ARM::R0 };
989const MCRegister FastCC_ARM_APCS_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
990const MCRegister RetCC_ARM_AAPCS_ArgRegs[] = { 0 };
991const MCRegister RetCC_ARM_AAPCS_Common_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
992const MCRegister RetCC_ARM_AAPCS_VFP_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
993const MCRegister RetCC_ARM_APCS_ArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
994const MCRegister RetFastCC_ARM_APCS_ArgRegs[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::S0, ARM::S1, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9 };
995
996// Registers used by Swift.
997const MCRegister CC_ARM_AAPCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
998const MCRegister CC_ARM_AAPCS_VFP_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
999const MCRegister CC_ARM_APCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1000const MCRegister RetCC_ARM_AAPCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1001const MCRegister RetCC_ARM_AAPCS_VFP_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1002const MCRegister RetCC_ARM_APCS_Swift_ArgRegs[] = { ARM::R10, ARM::R8 };
1003
1004#endif // CC_REGISTER_LIST
1005