1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t AVRMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(7168), // ADCRdRr
419 UINT64_C(3072), // ADDRdRr
420 UINT64_C(38400), // ADIWRdK
421 UINT64_C(28672), // ANDIRdK
422 UINT64_C(8192), // ANDRdRr
423 UINT64_C(37893), // ASRRd
424 UINT64_C(38024), // BCLRs
425 UINT64_C(63488), // BLD
426 UINT64_C(62464), // BRBCsk
427 UINT64_C(61440), // BRBSsk
428 UINT64_C(38296), // BREAK
429 UINT64_C(61441), // BREQk
430 UINT64_C(62468), // BRGEk
431 UINT64_C(61440), // BRLOk
432 UINT64_C(61444), // BRLTk
433 UINT64_C(61442), // BRMIk
434 UINT64_C(62465), // BRNEk
435 UINT64_C(62466), // BRPLk
436 UINT64_C(62464), // BRSHk
437 UINT64_C(37896), // BSETs
438 UINT64_C(64000), // BST
439 UINT64_C(2483945472), // CALLk
440 UINT64_C(38912), // CBIAb
441 UINT64_C(37888), // COMRd
442 UINT64_C(1024), // CPCRdRr
443 UINT64_C(12288), // CPIRdK
444 UINT64_C(5120), // CPRdRr
445 UINT64_C(4096), // CPSE
446 UINT64_C(37898), // DECRd
447 UINT64_C(37899), // DESK
448 UINT64_C(38169), // EICALL
449 UINT64_C(37913), // EIJMP
450 UINT64_C(38360), // ELPM
451 UINT64_C(36870), // ELPMRdZ
452 UINT64_C(36871), // ELPMRdZPi
453 UINT64_C(9216), // EORRdRr
454 UINT64_C(776), // FMUL
455 UINT64_C(896), // FMULS
456 UINT64_C(904), // FMULSU
457 UINT64_C(38153), // ICALL
458 UINT64_C(37897), // IJMP
459 UINT64_C(37891), // INCRd
460 UINT64_C(45056), // INRdA
461 UINT64_C(2483814400), // JMPk
462 UINT64_C(37382), // LACZRd
463 UINT64_C(37381), // LASZRd
464 UINT64_C(37383), // LATZRd
465 UINT64_C(32768), // LDDRdPtrQ
466 UINT64_C(57344), // LDIRdK
467 UINT64_C(32768), // LDRdPtr
468 UINT64_C(32770), // LDRdPtrPd
469 UINT64_C(32769), // LDRdPtrPi
470 UINT64_C(2415919104), // LDSRdK
471 UINT64_C(40960), // LDSRdKTiny
472 UINT64_C(38344), // LPM
473 UINT64_C(36868), // LPMRdZ
474 UINT64_C(36869), // LPMRdZPi
475 UINT64_C(37894), // LSRRd
476 UINT64_C(11264), // MOVRdRr
477 UINT64_C(256), // MOVWRdRr
478 UINT64_C(39936), // MULRdRr
479 UINT64_C(512), // MULSRdRr
480 UINT64_C(768), // MULSURdRr
481 UINT64_C(37889), // NEGRd
482 UINT64_C(0), // NOP
483 UINT64_C(24576), // ORIRdK
484 UINT64_C(10240), // ORRdRr
485 UINT64_C(47104), // OUTARr
486 UINT64_C(36879), // POPRd
487 UINT64_C(37391), // PUSHRr
488 UINT64_C(53248), // RCALLk
489 UINT64_C(38152), // RET
490 UINT64_C(38168), // RETI
491 UINT64_C(49152), // RJMPk
492 UINT64_C(37895), // RORRd
493 UINT64_C(16384), // SBCIRdK
494 UINT64_C(2048), // SBCRdRr
495 UINT64_C(39424), // SBIAb
496 UINT64_C(39168), // SBICAb
497 UINT64_C(39680), // SBISAb
498 UINT64_C(38656), // SBIWRdK
499 UINT64_C(64512), // SBRCRrB
500 UINT64_C(65024), // SBRSRrB
501 UINT64_C(38280), // SLEEP
502 UINT64_C(38376), // SPM
503 UINT64_C(38392), // SPMZPi
504 UINT64_C(33280), // STDPtrQRr
505 UINT64_C(33282), // STPtrPdRr
506 UINT64_C(33281), // STPtrPiRr
507 UINT64_C(33280), // STPtrRr
508 UINT64_C(2449473536), // STSKRr
509 UINT64_C(43008), // STSKRrTiny
510 UINT64_C(20480), // SUBIRdK
511 UINT64_C(6144), // SUBRdRr
512 UINT64_C(37890), // SWAPRd
513 UINT64_C(38312), // WDR
514 UINT64_C(37380), // XCHZRd
515 UINT64_C(0)
516 };
517 const unsigned opcode = MI.getOpcode();
518 uint64_t Value = InstBits[opcode];
519 uint64_t op = 0;
520 (void)op; // suppress warning
521 switch (opcode) {
522 case AVR::BREAK:
523 case AVR::EICALL:
524 case AVR::EIJMP:
525 case AVR::ELPM:
526 case AVR::ICALL:
527 case AVR::IJMP:
528 case AVR::LPM:
529 case AVR::NOP:
530 case AVR::RET:
531 case AVR::RETI:
532 case AVR::SLEEP:
533 case AVR::SPM:
534 case AVR::SPMZPi:
535 case AVR::WDR: {
536 break;
537 }
538 case AVR::OUTARr: {
539 // op: A
540 op = encodeImm<AVR::fixup_port6, 0>(MI, OpNo: 0, Fixups, STI);
541 Value |= (op & UINT64_C(48)) << 5;
542 Value |= (op & UINT64_C(15));
543 // op: rr
544 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
545 op &= UINT64_C(31);
546 op <<= 4;
547 Value |= op;
548 break;
549 }
550 case AVR::CBIAb:
551 case AVR::SBIAb:
552 case AVR::SBICAb:
553 case AVR::SBISAb: {
554 // op: addr
555 op = encodeImm<AVR::fixup_port5, 0>(MI, OpNo: 0, Fixups, STI);
556 op &= UINT64_C(31);
557 op <<= 3;
558 Value |= op;
559 // op: b
560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
561 op &= UINT64_C(7);
562 Value |= op;
563 break;
564 }
565 case AVR::CALLk:
566 case AVR::JMPk: {
567 // op: k
568 op = encodeCallTarget(MI, OpNo: 0, Fixups, STI);
569 Value |= (op & UINT64_C(4063232)) << 3;
570 Value |= (op & UINT64_C(131071));
571 break;
572 }
573 case AVR::RCALLk:
574 case AVR::RJMPk: {
575 // op: k
576 op = encodeRelCondBrTarget<AVR::fixup_13_pcrel>(MI, OpNo: 0, Fixups, STI);
577 op &= UINT64_C(4095);
578 Value |= op;
579 break;
580 }
581 case AVR::BREQk:
582 case AVR::BRGEk:
583 case AVR::BRLOk:
584 case AVR::BRLTk:
585 case AVR::BRMIk:
586 case AVR::BRNEk:
587 case AVR::BRPLk:
588 case AVR::BRSHk: {
589 // op: k
590 op = encodeRelCondBrTarget<AVR::fixup_7_pcrel>(MI, OpNo: 0, Fixups, STI);
591 op &= UINT64_C(127);
592 op <<= 3;
593 Value |= op;
594 break;
595 }
596 case AVR::BRBCsk:
597 case AVR::BRBSsk: {
598 // op: k
599 op = encodeRelCondBrTarget<AVR::fixup_7_pcrel>(MI, OpNo: 1, Fixups, STI);
600 op &= UINT64_C(127);
601 op <<= 3;
602 Value |= op;
603 // op: s
604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
605 op &= UINT64_C(7);
606 Value |= op;
607 break;
608 }
609 case AVR::DESK: {
610 // op: k
611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
612 op &= UINT64_C(15);
613 op <<= 4;
614 Value |= op;
615 break;
616 }
617 case AVR::STDPtrQRr: {
618 // op: memri
619 op = encodeMemri(MI, OpNo: 0, Fixups, STI);
620 Value |= (op & UINT64_C(32)) << 8;
621 Value |= (op & UINT64_C(24)) << 7;
622 Value |= (op & UINT64_C(64)) >> 3;
623 Value |= (op & UINT64_C(7));
624 // op: reg
625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
626 op &= UINT64_C(31);
627 op <<= 4;
628 Value |= op;
629 break;
630 }
631 case AVR::LDDRdPtrQ: {
632 // op: memri
633 op = encodeMemri(MI, OpNo: 1, Fixups, STI);
634 Value |= (op & UINT64_C(32)) << 8;
635 Value |= (op & UINT64_C(24)) << 7;
636 Value |= (op & UINT64_C(64)) >> 3;
637 Value |= (op & UINT64_C(7));
638 // op: reg
639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
640 op &= UINT64_C(31);
641 op <<= 4;
642 Value |= op;
643 break;
644 }
645 case AVR::CPIRdK:
646 case AVR::LDIRdK: {
647 // op: rd
648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
649 op &= UINT64_C(15);
650 op <<= 4;
651 Value |= op;
652 // op: k
653 op = encodeImm<AVR::fixup_ldi, 0>(MI, OpNo: 1, Fixups, STI);
654 Value |= (op & UINT64_C(240)) << 4;
655 Value |= (op & UINT64_C(15));
656 break;
657 }
658 case AVR::ANDIRdK:
659 case AVR::ORIRdK:
660 case AVR::SBCIRdK:
661 case AVR::SUBIRdK: {
662 // op: rd
663 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
664 op &= UINT64_C(15);
665 op <<= 4;
666 Value |= op;
667 // op: k
668 op = encodeImm<AVR::fixup_ldi, 0>(MI, OpNo: 2, Fixups, STI);
669 Value |= (op & UINT64_C(240)) << 4;
670 Value |= (op & UINT64_C(15));
671 break;
672 }
673 case AVR::LDSRdKTiny: {
674 // op: rd
675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
676 op &= UINT64_C(15);
677 op <<= 4;
678 Value |= op;
679 // op: k
680 op = encodeImm<AVR::fixup_lds_sts_16, 0>(MI, OpNo: 1, Fixups, STI);
681 Value |= (op & UINT64_C(112)) << 4;
682 Value |= (op & UINT64_C(15));
683 break;
684 }
685 case AVR::MULSRdRr:
686 case AVR::MULSURdRr: {
687 // op: rd
688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
689 op &= UINT64_C(15);
690 op <<= 4;
691 Value |= op;
692 // op: rr
693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
694 op &= UINT64_C(15);
695 Value |= op;
696 break;
697 }
698 case AVR::MOVWRdRr: {
699 // op: rd
700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
701 op &= UINT64_C(30);
702 op <<= 3;
703 Value |= op;
704 // op: rr
705 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
706 op &= UINT64_C(30);
707 op >>= 1;
708 Value |= op;
709 break;
710 }
711 case AVR::LDSRdK: {
712 // op: rd
713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
714 op &= UINT64_C(31);
715 op <<= 20;
716 Value |= op;
717 // op: k
718 op = encodeImm<AVR::fixup_16, 2>(MI, OpNo: 1, Fixups, STI);
719 op &= UINT64_C(65535);
720 Value |= op;
721 break;
722 }
723 case AVR::ASRRd:
724 case AVR::COMRd:
725 case AVR::DECRd:
726 case AVR::ELPMRdZ:
727 case AVR::ELPMRdZPi:
728 case AVR::INCRd:
729 case AVR::LACZRd:
730 case AVR::LASZRd:
731 case AVR::LATZRd:
732 case AVR::LPMRdZ:
733 case AVR::LPMRdZPi:
734 case AVR::LSRRd:
735 case AVR::NEGRd:
736 case AVR::POPRd:
737 case AVR::PUSHRr:
738 case AVR::RORRd:
739 case AVR::SWAPRd:
740 case AVR::XCHZRd: {
741 // op: rd
742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
743 op &= UINT64_C(31);
744 op <<= 4;
745 Value |= op;
746 break;
747 }
748 case AVR::INRdA: {
749 // op: rd
750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
751 op &= UINT64_C(31);
752 op <<= 4;
753 Value |= op;
754 // op: A
755 op = encodeImm<AVR::fixup_port6, 0>(MI, OpNo: 1, Fixups, STI);
756 Value |= (op & UINT64_C(48)) << 5;
757 Value |= (op & UINT64_C(15));
758 break;
759 }
760 case AVR::BST:
761 case AVR::SBRCRrB:
762 case AVR::SBRSRrB: {
763 // op: rd
764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
765 op &= UINT64_C(31);
766 op <<= 4;
767 Value |= op;
768 // op: b
769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
770 op &= UINT64_C(7);
771 Value |= op;
772 break;
773 }
774 case AVR::BLD: {
775 // op: rd
776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
777 op &= UINT64_C(31);
778 op <<= 4;
779 Value |= op;
780 // op: b
781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
782 op &= UINT64_C(7);
783 Value |= op;
784 break;
785 }
786 case AVR::CPCRdRr:
787 case AVR::CPRdRr:
788 case AVR::CPSE:
789 case AVR::MOVRdRr:
790 case AVR::MULRdRr: {
791 // op: rd
792 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
793 op &= UINT64_C(31);
794 op <<= 4;
795 Value |= op;
796 // op: rr
797 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
798 Value |= (op & UINT64_C(16)) << 5;
799 Value |= (op & UINT64_C(15));
800 break;
801 }
802 case AVR::ADCRdRr:
803 case AVR::ADDRdRr:
804 case AVR::ANDRdRr:
805 case AVR::EORRdRr:
806 case AVR::ORRdRr:
807 case AVR::SBCRdRr:
808 case AVR::SUBRdRr: {
809 // op: rd
810 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
811 op &= UINT64_C(31);
812 op <<= 4;
813 Value |= op;
814 // op: rr
815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
816 Value |= (op & UINT64_C(16)) << 5;
817 Value |= (op & UINT64_C(15));
818 break;
819 }
820 case AVR::ADIWRdK:
821 case AVR::SBIWRdK: {
822 // op: rd
823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
824 op &= UINT64_C(6);
825 op <<= 3;
826 Value |= op;
827 // op: k
828 op = encodeImm<AVR::fixup_6_adiw, 0>(MI, OpNo: 2, Fixups, STI);
829 Value |= (op & UINT64_C(48)) << 2;
830 Value |= (op & UINT64_C(15));
831 break;
832 }
833 case AVR::FMUL:
834 case AVR::FMULS:
835 case AVR::FMULSU: {
836 // op: rd
837 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
838 op &= UINT64_C(7);
839 op <<= 4;
840 Value |= op;
841 // op: rr
842 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
843 op &= UINT64_C(7);
844 Value |= op;
845 break;
846 }
847 case AVR::STSKRrTiny: {
848 // op: rd
849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
850 op &= UINT64_C(15);
851 op <<= 4;
852 Value |= op;
853 // op: k
854 op = encodeImm<AVR::fixup_lds_sts_16, 0>(MI, OpNo: 0, Fixups, STI);
855 Value |= (op & UINT64_C(112)) << 4;
856 Value |= (op & UINT64_C(15));
857 break;
858 }
859 case AVR::STSKRr: {
860 // op: rd
861 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
862 op &= UINT64_C(31);
863 op <<= 20;
864 Value |= op;
865 // op: k
866 op = encodeImm<AVR::fixup_16, 2>(MI, OpNo: 0, Fixups, STI);
867 op &= UINT64_C(65535);
868 Value |= op;
869 break;
870 }
871 case AVR::LDRdPtr:
872 case AVR::LDRdPtrPd:
873 case AVR::LDRdPtrPi: {
874 // op: reg
875 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
876 op &= UINT64_C(31);
877 op <<= 4;
878 Value |= op;
879 Value = loadStorePostEncoder(MI, EncodedValue: Value, STI);
880 break;
881 }
882 case AVR::STPtrRr: {
883 // op: reg
884 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
885 op &= UINT64_C(31);
886 op <<= 4;
887 Value |= op;
888 Value = loadStorePostEncoder(MI, EncodedValue: Value, STI);
889 break;
890 }
891 case AVR::STPtrPdRr:
892 case AVR::STPtrPiRr: {
893 // op: reg
894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
895 op &= UINT64_C(31);
896 op <<= 4;
897 Value |= op;
898 Value = loadStorePostEncoder(MI, EncodedValue: Value, STI);
899 break;
900 }
901 case AVR::BCLRs:
902 case AVR::BSETs: {
903 // op: s
904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
905 op &= UINT64_C(7);
906 op <<= 4;
907 Value |= op;
908 break;
909 }
910 default:
911 std::string msg;
912 raw_string_ostream Msg(msg);
913 Msg << "Not supported instr: " << MI;
914 report_fatal_error(reason: Msg.str().c_str());
915 }
916 return Value;
917}
918
919#ifdef GET_OPERAND_BIT_OFFSET
920#undef GET_OPERAND_BIT_OFFSET
921
922uint32_t AVRMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
923 unsigned OpNum,
924 const MCSubtargetInfo &STI) const {
925 switch (MI.getOpcode()) {
926 case AVR::BREAK:
927 case AVR::EICALL:
928 case AVR::EIJMP:
929 case AVR::ELPM:
930 case AVR::ICALL:
931 case AVR::IJMP:
932 case AVR::LPM:
933 case AVR::NOP:
934 case AVR::RET:
935 case AVR::RETI:
936 case AVR::SLEEP:
937 case AVR::SPM:
938 case AVR::SPMZPi:
939 case AVR::WDR: {
940 break;
941 }
942 case AVR::OUTARr: {
943 switch (OpNum) {
944 case 0:
945 // op: A
946 return 0;
947 case 1:
948 // op: rr
949 return 4;
950 }
951 break;
952 }
953 case AVR::CBIAb:
954 case AVR::SBIAb:
955 case AVR::SBICAb:
956 case AVR::SBISAb: {
957 switch (OpNum) {
958 case 0:
959 // op: addr
960 return 3;
961 case 1:
962 // op: b
963 return 0;
964 }
965 break;
966 }
967 case AVR::CALLk:
968 case AVR::JMPk:
969 case AVR::RCALLk:
970 case AVR::RJMPk: {
971 switch (OpNum) {
972 case 0:
973 // op: k
974 return 0;
975 }
976 break;
977 }
978 case AVR::BREQk:
979 case AVR::BRGEk:
980 case AVR::BRLOk:
981 case AVR::BRLTk:
982 case AVR::BRMIk:
983 case AVR::BRNEk:
984 case AVR::BRPLk:
985 case AVR::BRSHk: {
986 switch (OpNum) {
987 case 0:
988 // op: k
989 return 3;
990 }
991 break;
992 }
993 case AVR::DESK: {
994 switch (OpNum) {
995 case 0:
996 // op: k
997 return 4;
998 }
999 break;
1000 }
1001 case AVR::STDPtrQRr: {
1002 switch (OpNum) {
1003 case 0:
1004 // op: memri
1005 return 0;
1006 case 2:
1007 // op: reg
1008 return 4;
1009 }
1010 break;
1011 }
1012 case AVR::LDSRdK: {
1013 switch (OpNum) {
1014 case 0:
1015 // op: rd
1016 return 20;
1017 case 1:
1018 // op: k
1019 return 0;
1020 }
1021 break;
1022 }
1023 case AVR::INRdA: {
1024 switch (OpNum) {
1025 case 0:
1026 // op: rd
1027 return 4;
1028 case 1:
1029 // op: A
1030 return 0;
1031 }
1032 break;
1033 }
1034 case AVR::BST:
1035 case AVR::SBRCRrB:
1036 case AVR::SBRSRrB: {
1037 switch (OpNum) {
1038 case 0:
1039 // op: rd
1040 return 4;
1041 case 1:
1042 // op: b
1043 return 0;
1044 }
1045 break;
1046 }
1047 case AVR::CPIRdK:
1048 case AVR::LDIRdK:
1049 case AVR::LDSRdKTiny: {
1050 switch (OpNum) {
1051 case 0:
1052 // op: rd
1053 return 4;
1054 case 1:
1055 // op: k
1056 return 0;
1057 }
1058 break;
1059 }
1060 case AVR::CPCRdRr:
1061 case AVR::CPRdRr:
1062 case AVR::CPSE:
1063 case AVR::FMUL:
1064 case AVR::FMULS:
1065 case AVR::FMULSU:
1066 case AVR::MOVRdRr:
1067 case AVR::MOVWRdRr:
1068 case AVR::MULRdRr:
1069 case AVR::MULSRdRr:
1070 case AVR::MULSURdRr: {
1071 switch (OpNum) {
1072 case 0:
1073 // op: rd
1074 return 4;
1075 case 1:
1076 // op: rr
1077 return 0;
1078 }
1079 break;
1080 }
1081 case AVR::BLD: {
1082 switch (OpNum) {
1083 case 0:
1084 // op: rd
1085 return 4;
1086 case 2:
1087 // op: b
1088 return 0;
1089 }
1090 break;
1091 }
1092 case AVR::ADIWRdK:
1093 case AVR::ANDIRdK:
1094 case AVR::ORIRdK:
1095 case AVR::SBCIRdK:
1096 case AVR::SBIWRdK:
1097 case AVR::SUBIRdK: {
1098 switch (OpNum) {
1099 case 0:
1100 // op: rd
1101 return 4;
1102 case 2:
1103 // op: k
1104 return 0;
1105 }
1106 break;
1107 }
1108 case AVR::ADCRdRr:
1109 case AVR::ADDRdRr:
1110 case AVR::ANDRdRr:
1111 case AVR::EORRdRr:
1112 case AVR::ORRdRr:
1113 case AVR::SBCRdRr:
1114 case AVR::SUBRdRr: {
1115 switch (OpNum) {
1116 case 0:
1117 // op: rd
1118 return 4;
1119 case 2:
1120 // op: rr
1121 return 0;
1122 }
1123 break;
1124 }
1125 case AVR::ASRRd:
1126 case AVR::COMRd:
1127 case AVR::DECRd:
1128 case AVR::ELPMRdZ:
1129 case AVR::ELPMRdZPi:
1130 case AVR::INCRd:
1131 case AVR::LACZRd:
1132 case AVR::LASZRd:
1133 case AVR::LATZRd:
1134 case AVR::LPMRdZ:
1135 case AVR::LPMRdZPi:
1136 case AVR::LSRRd:
1137 case AVR::NEGRd:
1138 case AVR::POPRd:
1139 case AVR::PUSHRr:
1140 case AVR::RORRd:
1141 case AVR::SWAPRd:
1142 case AVR::XCHZRd: {
1143 switch (OpNum) {
1144 case 0:
1145 // op: rd
1146 return 4;
1147 }
1148 break;
1149 }
1150 case AVR::LDRdPtr:
1151 case AVR::LDRdPtrPd:
1152 case AVR::LDRdPtrPi: {
1153 switch (OpNum) {
1154 case 0:
1155 // op: reg
1156 return 4;
1157 }
1158 break;
1159 }
1160 case AVR::BCLRs:
1161 case AVR::BSETs: {
1162 switch (OpNum) {
1163 case 0:
1164 // op: s
1165 return 4;
1166 }
1167 break;
1168 }
1169 case AVR::BRBCsk:
1170 case AVR::BRBSsk: {
1171 switch (OpNum) {
1172 case 1:
1173 // op: k
1174 return 3;
1175 case 0:
1176 // op: s
1177 return 0;
1178 }
1179 break;
1180 }
1181 case AVR::LDDRdPtrQ: {
1182 switch (OpNum) {
1183 case 1:
1184 // op: memri
1185 return 0;
1186 case 0:
1187 // op: reg
1188 return 4;
1189 }
1190 break;
1191 }
1192 case AVR::STSKRr: {
1193 switch (OpNum) {
1194 case 1:
1195 // op: rd
1196 return 20;
1197 case 0:
1198 // op: k
1199 return 0;
1200 }
1201 break;
1202 }
1203 case AVR::STSKRrTiny: {
1204 switch (OpNum) {
1205 case 1:
1206 // op: rd
1207 return 4;
1208 case 0:
1209 // op: k
1210 return 0;
1211 }
1212 break;
1213 }
1214 case AVR::STPtrRr: {
1215 switch (OpNum) {
1216 case 1:
1217 // op: reg
1218 return 4;
1219 }
1220 break;
1221 }
1222 case AVR::STPtrPdRr:
1223 case AVR::STPtrPiRr: {
1224 switch (OpNum) {
1225 case 2:
1226 // op: reg
1227 return 4;
1228 }
1229 break;
1230 }
1231 }
1232 std::string msg;
1233 raw_string_ostream Msg(msg);
1234 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
1235 report_fatal_error(Msg.str().c_str());
1236}
1237
1238#endif // GET_OPERAND_BIT_OFFSET
1239
1240