1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t HexagonMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(0),
443 UINT64_C(0),
444 UINT64_C(0),
445 UINT64_C(0),
446 UINT64_C(0),
447 UINT64_C(0),
448 UINT64_C(0),
449 UINT64_C(0),
450 UINT64_C(0),
451 UINT64_C(0),
452 UINT64_C(0),
453 UINT64_C(0),
454 UINT64_C(0),
455 UINT64_C(0),
456 UINT64_C(0),
457 UINT64_C(0),
458 UINT64_C(0),
459 UINT64_C(0),
460 UINT64_C(0),
461 UINT64_C(0),
462 UINT64_C(0),
463 UINT64_C(0),
464 UINT64_C(0),
465 UINT64_C(0),
466 UINT64_C(0),
467 UINT64_C(0),
468 UINT64_C(0),
469 UINT64_C(0),
470 UINT64_C(0),
471 UINT64_C(0),
472 UINT64_C(0),
473 UINT64_C(0),
474 UINT64_C(0),
475 UINT64_C(0),
476 UINT64_C(0),
477 UINT64_C(0),
478 UINT64_C(0),
479 UINT64_C(0),
480 UINT64_C(0),
481 UINT64_C(0),
482 UINT64_C(0),
483 UINT64_C(0),
484 UINT64_C(0),
485 UINT64_C(0),
486 UINT64_C(0),
487 UINT64_C(0),
488 UINT64_C(0),
489 UINT64_C(0),
490 UINT64_C(0),
491 UINT64_C(0),
492 UINT64_C(0),
493 UINT64_C(0),
494 UINT64_C(0),
495 UINT64_C(0),
496 UINT64_C(0),
497 UINT64_C(0),
498 UINT64_C(0),
499 UINT64_C(0),
500 UINT64_C(0),
501 UINT64_C(0),
502 UINT64_C(0),
503 UINT64_C(0),
504 UINT64_C(0),
505 UINT64_C(0),
506 UINT64_C(0),
507 UINT64_C(0),
508 UINT64_C(0),
509 UINT64_C(0),
510 UINT64_C(0),
511 UINT64_C(0),
512 UINT64_C(0),
513 UINT64_C(0),
514 UINT64_C(0),
515 UINT64_C(0),
516 UINT64_C(0),
517 UINT64_C(0),
518 UINT64_C(0),
519 UINT64_C(0),
520 UINT64_C(0),
521 UINT64_C(0),
522 UINT64_C(0),
523 UINT64_C(0),
524 UINT64_C(0),
525 UINT64_C(0),
526 UINT64_C(0),
527 UINT64_C(0),
528 UINT64_C(0),
529 UINT64_C(0),
530 UINT64_C(0),
531 UINT64_C(0),
532 UINT64_C(0),
533 UINT64_C(0),
534 UINT64_C(0),
535 UINT64_C(0),
536 UINT64_C(0),
537 UINT64_C(0),
538 UINT64_C(0),
539 UINT64_C(0),
540 UINT64_C(0),
541 UINT64_C(0),
542 UINT64_C(0),
543 UINT64_C(0),
544 UINT64_C(0),
545 UINT64_C(0),
546 UINT64_C(0),
547 UINT64_C(0),
548 UINT64_C(0),
549 UINT64_C(0),
550 UINT64_C(0),
551 UINT64_C(0),
552 UINT64_C(0),
553 UINT64_C(0),
554 UINT64_C(0),
555 UINT64_C(0),
556 UINT64_C(0),
557 UINT64_C(0),
558 UINT64_C(0),
559 UINT64_C(0),
560 UINT64_C(0),
561 UINT64_C(0),
562 UINT64_C(0),
563 UINT64_C(0),
564 UINT64_C(0),
565 UINT64_C(0),
566 UINT64_C(0),
567 UINT64_C(0),
568 UINT64_C(0),
569 UINT64_C(0),
570 UINT64_C(0),
571 UINT64_C(0),
572 UINT64_C(0),
573 UINT64_C(0),
574 UINT64_C(0),
575 UINT64_C(0),
576 UINT64_C(0),
577 UINT64_C(0),
578 UINT64_C(0),
579 UINT64_C(0),
580 UINT64_C(0),
581 UINT64_C(0),
582 UINT64_C(0),
583 UINT64_C(0),
584 UINT64_C(0),
585 UINT64_C(0),
586 UINT64_C(0),
587 UINT64_C(0),
588 UINT64_C(0),
589 UINT64_C(0),
590 UINT64_C(0),
591 UINT64_C(0),
592 UINT64_C(0),
593 UINT64_C(0),
594 UINT64_C(0),
595 UINT64_C(0),
596 UINT64_C(0),
597 UINT64_C(0),
598 UINT64_C(0),
599 UINT64_C(0),
600 UINT64_C(0),
601 UINT64_C(0),
602 UINT64_C(0),
603 UINT64_C(0),
604 UINT64_C(0),
605 UINT64_C(0),
606 UINT64_C(0),
607 UINT64_C(0),
608 UINT64_C(0),
609 UINT64_C(0),
610 UINT64_C(0),
611 UINT64_C(0),
612 UINT64_C(0),
613 UINT64_C(0),
614 UINT64_C(0),
615 UINT64_C(0),
616 UINT64_C(0),
617 UINT64_C(0),
618 UINT64_C(0),
619 UINT64_C(0),
620 UINT64_C(0),
621 UINT64_C(0),
622 UINT64_C(0),
623 UINT64_C(0),
624 UINT64_C(0),
625 UINT64_C(0),
626 UINT64_C(0),
627 UINT64_C(0),
628 UINT64_C(0),
629 UINT64_C(0),
630 UINT64_C(0),
631 UINT64_C(0),
632 UINT64_C(0),
633 UINT64_C(0),
634 UINT64_C(0),
635 UINT64_C(0),
636 UINT64_C(0),
637 UINT64_C(0),
638 UINT64_C(0),
639 UINT64_C(0),
640 UINT64_C(0),
641 UINT64_C(0),
642 UINT64_C(0),
643 UINT64_C(0),
644 UINT64_C(0),
645 UINT64_C(0),
646 UINT64_C(0),
647 UINT64_C(0),
648 UINT64_C(0),
649 UINT64_C(0),
650 UINT64_C(0),
651 UINT64_C(0),
652 UINT64_C(0),
653 UINT64_C(0),
654 UINT64_C(0),
655 UINT64_C(0),
656 UINT64_C(0),
657 UINT64_C(0),
658 UINT64_C(0),
659 UINT64_C(0),
660 UINT64_C(0),
661 UINT64_C(0),
662 UINT64_C(0),
663 UINT64_C(0),
664 UINT64_C(0),
665 UINT64_C(0),
666 UINT64_C(0),
667 UINT64_C(0),
668 UINT64_C(0),
669 UINT64_C(0),
670 UINT64_C(0),
671 UINT64_C(0),
672 UINT64_C(0),
673 UINT64_C(0),
674 UINT64_C(0),
675 UINT64_C(0),
676 UINT64_C(0),
677 UINT64_C(0),
678 UINT64_C(0),
679 UINT64_C(0),
680 UINT64_C(0),
681 UINT64_C(0),
682 UINT64_C(0),
683 UINT64_C(0),
684 UINT64_C(0),
685 UINT64_C(0),
686 UINT64_C(0),
687 UINT64_C(0),
688 UINT64_C(0),
689 UINT64_C(0),
690 UINT64_C(0),
691 UINT64_C(0),
692 UINT64_C(0),
693 UINT64_C(0),
694 UINT64_C(0),
695 UINT64_C(0),
696 UINT64_C(0),
697 UINT64_C(0),
698 UINT64_C(0),
699 UINT64_C(0),
700 UINT64_C(0),
701 UINT64_C(0),
702 UINT64_C(0),
703 UINT64_C(0),
704 UINT64_C(0),
705 UINT64_C(0),
706 UINT64_C(0),
707 UINT64_C(0),
708 UINT64_C(0),
709 UINT64_C(0),
710 UINT64_C(0),
711 UINT64_C(0),
712 UINT64_C(0),
713 UINT64_C(0),
714 UINT64_C(0),
715 UINT64_C(0),
716 UINT64_C(0),
717 UINT64_C(0),
718 UINT64_C(0),
719 UINT64_C(0),
720 UINT64_C(0),
721 UINT64_C(0),
722 UINT64_C(0),
723 UINT64_C(0),
724 UINT64_C(0),
725 UINT64_C(0),
726 UINT64_C(0),
727 UINT64_C(0),
728 UINT64_C(0),
729 UINT64_C(0),
730 UINT64_C(0),
731 UINT64_C(0),
732 UINT64_C(0),
733 UINT64_C(0),
734 UINT64_C(0),
735 UINT64_C(0),
736 UINT64_C(0),
737 UINT64_C(0),
738 UINT64_C(0),
739 UINT64_C(0),
740 UINT64_C(0),
741 UINT64_C(0),
742 UINT64_C(0),
743 UINT64_C(0),
744 UINT64_C(0),
745 UINT64_C(0),
746 UINT64_C(0),
747 UINT64_C(0),
748 UINT64_C(0),
749 UINT64_C(0),
750 UINT64_C(0),
751 UINT64_C(0),
752 UINT64_C(0),
753 UINT64_C(0),
754 UINT64_C(0),
755 UINT64_C(0),
756 UINT64_C(0),
757 UINT64_C(0),
758 UINT64_C(0),
759 UINT64_C(0),
760 UINT64_C(0),
761 UINT64_C(0),
762 UINT64_C(0),
763 UINT64_C(0),
764 UINT64_C(0),
765 UINT64_C(0),
766 UINT64_C(0),
767 UINT64_C(0),
768 UINT64_C(0),
769 UINT64_C(0),
770 UINT64_C(0),
771 UINT64_C(0),
772 UINT64_C(0),
773 UINT64_C(0),
774 UINT64_C(0),
775 UINT64_C(0),
776 UINT64_C(0),
777 UINT64_C(0),
778 UINT64_C(0),
779 UINT64_C(0),
780 UINT64_C(0),
781 UINT64_C(0),
782 UINT64_C(0),
783 UINT64_C(0),
784 UINT64_C(0),
785 UINT64_C(0),
786 UINT64_C(0),
787 UINT64_C(0),
788 UINT64_C(0),
789 UINT64_C(0),
790 UINT64_C(0),
791 UINT64_C(0),
792 UINT64_C(0),
793 UINT64_C(0),
794 UINT64_C(0),
795 UINT64_C(0),
796 UINT64_C(0),
797 UINT64_C(0),
798 UINT64_C(0),
799 UINT64_C(0),
800 UINT64_C(0),
801 UINT64_C(0),
802 UINT64_C(0),
803 UINT64_C(0),
804 UINT64_C(0),
805 UINT64_C(0),
806 UINT64_C(0),
807 UINT64_C(0),
808 UINT64_C(0),
809 UINT64_C(0),
810 UINT64_C(0),
811 UINT64_C(0),
812 UINT64_C(0),
813 UINT64_C(0),
814 UINT64_C(0),
815 UINT64_C(0),
816 UINT64_C(0),
817 UINT64_C(0),
818 UINT64_C(0),
819 UINT64_C(0),
820 UINT64_C(0),
821 UINT64_C(0),
822 UINT64_C(0),
823 UINT64_C(0),
824 UINT64_C(0),
825 UINT64_C(0),
826 UINT64_C(0),
827 UINT64_C(0),
828 UINT64_C(0),
829 UINT64_C(0),
830 UINT64_C(0),
831 UINT64_C(0),
832 UINT64_C(0),
833 UINT64_C(0),
834 UINT64_C(0),
835 UINT64_C(0),
836 UINT64_C(0),
837 UINT64_C(0),
838 UINT64_C(0),
839 UINT64_C(0),
840 UINT64_C(0),
841 UINT64_C(0),
842 UINT64_C(0),
843 UINT64_C(0),
844 UINT64_C(0),
845 UINT64_C(0),
846 UINT64_C(0),
847 UINT64_C(0),
848 UINT64_C(0),
849 UINT64_C(0),
850 UINT64_C(0),
851 UINT64_C(0),
852 UINT64_C(0),
853 UINT64_C(0),
854 UINT64_C(0),
855 UINT64_C(0),
856 UINT64_C(0),
857 UINT64_C(0),
858 UINT64_C(0),
859 UINT64_C(0),
860 UINT64_C(0),
861 UINT64_C(0),
862 UINT64_C(0),
863 UINT64_C(0),
864 UINT64_C(0),
865 UINT64_C(0),
866 UINT64_C(0),
867 UINT64_C(0),
868 UINT64_C(0),
869 UINT64_C(0),
870 UINT64_C(0),
871 UINT64_C(0),
872 UINT64_C(0),
873 UINT64_C(0),
874 UINT64_C(0),
875 UINT64_C(0),
876 UINT64_C(0),
877 UINT64_C(0),
878 UINT64_C(0),
879 UINT64_C(0),
880 UINT64_C(0),
881 UINT64_C(0),
882 UINT64_C(0),
883 UINT64_C(0),
884 UINT64_C(0),
885 UINT64_C(0),
886 UINT64_C(0),
887 UINT64_C(0),
888 UINT64_C(0),
889 UINT64_C(0),
890 UINT64_C(0),
891 UINT64_C(0),
892 UINT64_C(0),
893 UINT64_C(0),
894 UINT64_C(0),
895 UINT64_C(0),
896 UINT64_C(0),
897 UINT64_C(0),
898 UINT64_C(0),
899 UINT64_C(0),
900 UINT64_C(0),
901 UINT64_C(0),
902 UINT64_C(0),
903 UINT64_C(0),
904 UINT64_C(0),
905 UINT64_C(0),
906 UINT64_C(0),
907 UINT64_C(0),
908 UINT64_C(0),
909 UINT64_C(0),
910 UINT64_C(0),
911 UINT64_C(0),
912 UINT64_C(0),
913 UINT64_C(0),
914 UINT64_C(0),
915 UINT64_C(0),
916 UINT64_C(0),
917 UINT64_C(0),
918 UINT64_C(0),
919 UINT64_C(0),
920 UINT64_C(0),
921 UINT64_C(0),
922 UINT64_C(0),
923 UINT64_C(0),
924 UINT64_C(0),
925 UINT64_C(0),
926 UINT64_C(0),
927 UINT64_C(0),
928 UINT64_C(0),
929 UINT64_C(0),
930 UINT64_C(2357198976), // A2_abs
931 UINT64_C(2155872448), // A2_absp
932 UINT64_C(2357199008), // A2_abssat
933 UINT64_C(4076863488), // A2_add
934 UINT64_C(3577741408), // A2_addh_h16_hh
935 UINT64_C(3577741376), // A2_addh_h16_hl
936 UINT64_C(3577741344), // A2_addh_h16_lh
937 UINT64_C(3577741312), // A2_addh_h16_ll
938 UINT64_C(3577741536), // A2_addh_h16_sat_hh
939 UINT64_C(3577741504), // A2_addh_h16_sat_hl
940 UINT64_C(3577741472), // A2_addh_h16_sat_lh
941 UINT64_C(3577741440), // A2_addh_h16_sat_ll
942 UINT64_C(3573547072), // A2_addh_l16_hl
943 UINT64_C(3573547008), // A2_addh_l16_ll
944 UINT64_C(3573547200), // A2_addh_l16_sat_hl
945 UINT64_C(3573547136), // A2_addh_l16_sat_ll
946 UINT64_C(2952790016), // A2_addi
947 UINT64_C(3539992800), // A2_addp
948 UINT64_C(3546284192), // A2_addpsat
949 UINT64_C(4131389440), // A2_addsat
950 UINT64_C(3546284256), // A2_addsph
951 UINT64_C(3546284224), // A2_addspl
952 UINT64_C(4043309056), // A2_and
953 UINT64_C(1979711488), // A2_andir
954 UINT64_C(3554672640), // A2_andp
955 UINT64_C(1879048192), // A2_aslh
956 UINT64_C(1881145344), // A2_asrh
957 UINT64_C(4085252096), // A2_combine_hh
958 UINT64_C(4087349248), // A2_combine_hl
959 UINT64_C(4089446400), // A2_combine_lh
960 UINT64_C(4091543552), // A2_combine_ll
961 UINT64_C(2080374784), // A2_combineii
962 UINT64_C(4110417920), // A2_combinew
963 UINT64_C(3586129920), // A2_max
964 UINT64_C(3552575616), // A2_maxp
965 UINT64_C(3586130048), // A2_maxu
966 UINT64_C(3552575648), // A2_maxup
967 UINT64_C(3584032768), // A2_min
968 UINT64_C(3550478528), // A2_minp
969 UINT64_C(3584032896), // A2_minu
970 UINT64_C(3550478560), // A2_minup
971 UINT64_C(2155872416), // A2_negp
972 UINT64_C(2357199040), // A2_negsat
973 UINT64_C(2130706432), // A2_nop
974 UINT64_C(2155872384), // A2_notp
975 UINT64_C(4045406208), // A2_or
976 UINT64_C(1988100096), // A2_orir
977 UINT64_C(3554672704), // A2_orp
978 UINT64_C(4211081344), // A2_paddf
979 UINT64_C(4211089536), // A2_paddfnew
980 UINT64_C(1954545664), // A2_paddif
981 UINT64_C(1954553856), // A2_paddifnew
982 UINT64_C(1946157056), // A2_paddit
983 UINT64_C(1946165248), // A2_padditnew
984 UINT64_C(4211081216), // A2_paddt
985 UINT64_C(4211089408), // A2_paddtnew
986 UINT64_C(4177526912), // A2_pandf
987 UINT64_C(4177535104), // A2_pandfnew
988 UINT64_C(4177526784), // A2_pandt
989 UINT64_C(4177534976), // A2_pandtnew
990 UINT64_C(4179624064), // A2_porf
991 UINT64_C(4179632256), // A2_porfnew
992 UINT64_C(4179623936), // A2_port
993 UINT64_C(4179632128), // A2_portnew
994 UINT64_C(4213178496), // A2_psubf
995 UINT64_C(4213186688), // A2_psubfnew
996 UINT64_C(4213178368), // A2_psubt
997 UINT64_C(4213186560), // A2_psubtnew
998 UINT64_C(4183818368), // A2_pxorf
999 UINT64_C(4183826560), // A2_pxorfnew
1000 UINT64_C(4183818240), // A2_pxort
1001 UINT64_C(4183826432), // A2_pxortnew
1002 UINT64_C(2294284320), // A2_roundsat
1003 UINT64_C(2294284288), // A2_sat
1004 UINT64_C(2361393376), // A2_satb
1005 UINT64_C(2361393280), // A2_sath
1006 UINT64_C(2361393344), // A2_satub
1007 UINT64_C(2361393312), // A2_satuh
1008 UINT64_C(4078960640), // A2_sub
1009 UINT64_C(3579838560), // A2_subh_h16_hh
1010 UINT64_C(3579838528), // A2_subh_h16_hl
1011 UINT64_C(3579838496), // A2_subh_h16_lh
1012 UINT64_C(3579838464), // A2_subh_h16_ll
1013 UINT64_C(3579838688), // A2_subh_h16_sat_hh
1014 UINT64_C(3579838656), // A2_subh_h16_sat_hl
1015 UINT64_C(3579838624), // A2_subh_h16_sat_lh
1016 UINT64_C(3579838592), // A2_subh_h16_sat_ll
1017 UINT64_C(3575644224), // A2_subh_l16_hl
1018 UINT64_C(3575644160), // A2_subh_l16_ll
1019 UINT64_C(3575644352), // A2_subh_l16_sat_hl
1020 UINT64_C(3575644288), // A2_subh_l16_sat_ll
1021 UINT64_C(3542089952), // A2_subp
1022 UINT64_C(1983905792), // A2_subri
1023 UINT64_C(4139778048), // A2_subsat
1024 UINT64_C(4127195136), // A2_svaddh
1025 UINT64_C(4129292288), // A2_svaddhs
1026 UINT64_C(4133486592), // A2_svadduhs
1027 UINT64_C(4143972352), // A2_svavgh
1028 UINT64_C(4146069504), // A2_svavghs
1029 UINT64_C(4150263808), // A2_svnavgh
1030 UINT64_C(4135583744), // A2_svsubh
1031 UINT64_C(4137680896), // A2_svsubhs
1032 UINT64_C(4141875200), // A2_svsubuhs
1033 UINT64_C(2357199072), // A2_swiz
1034 UINT64_C(1889533952), // A2_sxtb
1035 UINT64_C(1893728256), // A2_sxth
1036 UINT64_C(2218786816), // A2_sxtw
1037 UINT64_C(1885339648), // A2_tfr
1038 UINT64_C(1778384896), // A2_tfrcrr
1039 UINT64_C(1914699776), // A2_tfrih
1040 UINT64_C(1897922560), // A2_tfril
1041 UINT64_C(1646264320), // A2_tfrrcr
1042 UINT64_C(2013265920), // A2_tfrsi
1043 UINT64_C(2151678080), // A2_vabsh
1044 UINT64_C(2151678112), // A2_vabshsat
1045 UINT64_C(2151678144), // A2_vabsw
1046 UINT64_C(2151678176), // A2_vabswsat
1047 UINT64_C(3539992640), // A2_vaddh
1048 UINT64_C(3539992672), // A2_vaddhs
1049 UINT64_C(3539992576), // A2_vaddub
1050 UINT64_C(3539992608), // A2_vaddubs
1051 UINT64_C(3539992704), // A2_vadduhs
1052 UINT64_C(3539992736), // A2_vaddw
1053 UINT64_C(3539992768), // A2_vaddws
1054 UINT64_C(3544186944), // A2_vavgh
1055 UINT64_C(3544187008), // A2_vavghcr
1056 UINT64_C(3544186976), // A2_vavghr
1057 UINT64_C(3544186880), // A2_vavgub
1058 UINT64_C(3544186912), // A2_vavgubr
1059 UINT64_C(3544187040), // A2_vavguh
1060 UINT64_C(3544187072), // A2_vavguhr
1061 UINT64_C(3546284128), // A2_vavguw
1062 UINT64_C(3546284160), // A2_vavguwr
1063 UINT64_C(3546284032), // A2_vavgw
1064 UINT64_C(3546284096), // A2_vavgwcr
1065 UINT64_C(3546284064), // A2_vavgwr
1066 UINT64_C(3523215552), // A2_vcmpbeq
1067 UINT64_C(3523215584), // A2_vcmpbgtu
1068 UINT64_C(3523215456), // A2_vcmpheq
1069 UINT64_C(3523215488), // A2_vcmphgt
1070 UINT64_C(3523215520), // A2_vcmphgtu
1071 UINT64_C(3523215360), // A2_vcmpweq
1072 UINT64_C(3523215392), // A2_vcmpwgt
1073 UINT64_C(3523215424), // A2_vcmpwgtu
1074 UINT64_C(2155872480), // A2_vconj
1075 UINT64_C(3552575680), // A2_vmaxb
1076 UINT64_C(3552575520), // A2_vmaxh
1077 UINT64_C(3552575488), // A2_vmaxub
1078 UINT64_C(3552575552), // A2_vmaxuh
1079 UINT64_C(3550478496), // A2_vmaxuw
1080 UINT64_C(3552575584), // A2_vmaxw
1081 UINT64_C(3552575712), // A2_vminb
1082 UINT64_C(3550478368), // A2_vminh
1083 UINT64_C(3550478336), // A2_vminub
1084 UINT64_C(3550478400), // A2_vminuh
1085 UINT64_C(3550478464), // A2_vminuw
1086 UINT64_C(3550478432), // A2_vminw
1087 UINT64_C(3548381184), // A2_vnavgh
1088 UINT64_C(3548381248), // A2_vnavghcr
1089 UINT64_C(3548381216), // A2_vnavghr
1090 UINT64_C(3548381280), // A2_vnavgw
1091 UINT64_C(3548381376), // A2_vnavgwcr
1092 UINT64_C(3548381312), // A2_vnavgwr
1093 UINT64_C(3896508448), // A2_vraddub
1094 UINT64_C(3930062880), // A2_vraddub_acc
1095 UINT64_C(3896508480), // A2_vrsadub
1096 UINT64_C(3930062912), // A2_vrsadub_acc
1097 UINT64_C(3542089792), // A2_vsubh
1098 UINT64_C(3542089824), // A2_vsubhs
1099 UINT64_C(3542089728), // A2_vsubub
1100 UINT64_C(3542089760), // A2_vsububs
1101 UINT64_C(3542089856), // A2_vsubuhs
1102 UINT64_C(3542089888), // A2_vsubw
1103 UINT64_C(3542089920), // A2_vsubws
1104 UINT64_C(4049600512), // A2_xor
1105 UINT64_C(3554672768), // A2_xorp
1106 UINT64_C(1891631104), // A2_zxth
1107 UINT64_C(3267362816), // A4_addp_c
1108 UINT64_C(4051697664), // A4_andn
1109 UINT64_C(3554672672), // A4_andnp
1110 UINT64_C(3558866944), // A4_bitsplit
1111 UINT64_C(2294284416), // A4_bitspliti
1112 UINT64_C(3523223712), // A4_boundscheck_hi
1113 UINT64_C(3523223680), // A4_boundscheck_lo
1114 UINT64_C(3351249088), // A4_cmpbeq
1115 UINT64_C(3707764736), // A4_cmpbeqi
1116 UINT64_C(3351248960), // A4_cmpbgt
1117 UINT64_C(3709861888), // A4_cmpbgti
1118 UINT64_C(3351249120), // A4_cmpbgtu
1119 UINT64_C(3711959040), // A4_cmpbgtui
1120 UINT64_C(3351248992), // A4_cmpheq
1121 UINT64_C(3707764744), // A4_cmpheqi
1122 UINT64_C(3351249024), // A4_cmphgt
1123 UINT64_C(3709861896), // A4_cmphgti
1124 UINT64_C(3351249056), // A4_cmphgtu
1125 UINT64_C(3711959048), // A4_cmphgtui
1126 UINT64_C(2088763392), // A4_combineii
1127 UINT64_C(1931485184), // A4_combineir
1128 UINT64_C(1929388032), // A4_combineri
1129 UINT64_C(2363490304), // A4_cround_ri
1130 UINT64_C(3334471680), // A4_cround_rr
1131 UINT64_C(0), // A4_ext
1132 UINT64_C(3554672864), // A4_modwrapu
1133 UINT64_C(4053794816), // A4_orn
1134 UINT64_C(3554672736), // A4_ornp
1135 UINT64_C(1879058432), // A4_paslhf
1136 UINT64_C(1879059456), // A4_paslhfnew
1137 UINT64_C(1879056384), // A4_paslht
1138 UINT64_C(1879057408), // A4_paslhtnew
1139 UINT64_C(1881155584), // A4_pasrhf
1140 UINT64_C(1881156608), // A4_pasrhfnew
1141 UINT64_C(1881153536), // A4_pasrht
1142 UINT64_C(1881154560), // A4_pasrhtnew
1143 UINT64_C(1889544192), // A4_psxtbf
1144 UINT64_C(1889545216), // A4_psxtbfnew
1145 UINT64_C(1889542144), // A4_psxtbt
1146 UINT64_C(1889543168), // A4_psxtbtnew
1147 UINT64_C(1893738496), // A4_psxthf
1148 UINT64_C(1893739520), // A4_psxthfnew
1149 UINT64_C(1893736448), // A4_psxtht
1150 UINT64_C(1893737472), // A4_psxthtnew
1151 UINT64_C(1887447040), // A4_pzxtbf
1152 UINT64_C(1887448064), // A4_pzxtbfnew
1153 UINT64_C(1887444992), // A4_pzxtbt
1154 UINT64_C(1887446016), // A4_pzxtbtnew
1155 UINT64_C(1891641344), // A4_pzxthf
1156 UINT64_C(1891642368), // A4_pzxthfnew
1157 UINT64_C(1891639296), // A4_pzxtht
1158 UINT64_C(1891640320), // A4_pzxthtnew
1159 UINT64_C(4081057792), // A4_rcmpeq
1160 UINT64_C(1933582336), // A4_rcmpeqi
1161 UINT64_C(4083154944), // A4_rcmpneq
1162 UINT64_C(1935679488), // A4_rcmpneqi
1163 UINT64_C(2363490432), // A4_round_ri
1164 UINT64_C(2363490496), // A4_round_ri_sat
1165 UINT64_C(3334471808), // A4_round_rr
1166 UINT64_C(3334471872), // A4_round_rr_sat
1167 UINT64_C(3269459968), // A4_subp_c
1168 UINT64_C(1744830464), // A4_tfrcpp
1169 UINT64_C(1663041536), // A4_tfrpcp
1170 UINT64_C(3523223648), // A4_tlbmatch
1171 UINT64_C(3523223552), // A4_vcmpbeq_any
1172 UINT64_C(3690987520), // A4_vcmpbeqi
1173 UINT64_C(3523223616), // A4_vcmpbgt
1174 UINT64_C(3693084672), // A4_vcmpbgti
1175 UINT64_C(3695181824), // A4_vcmpbgtui
1176 UINT64_C(3690987528), // A4_vcmpheqi
1177 UINT64_C(3693084680), // A4_vcmphgti
1178 UINT64_C(3695181832), // A4_vcmphgtui
1179 UINT64_C(3690987536), // A4_vcmpweqi
1180 UINT64_C(3693084688), // A4_vcmpwgti
1181 UINT64_C(3695181840), // A4_vcmpwgtui
1182 UINT64_C(3407872032), // A4_vrmaxh
1183 UINT64_C(3407880224), // A4_vrmaxuh
1184 UINT64_C(3407880256), // A4_vrmaxuw
1185 UINT64_C(3407872064), // A4_vrmaxw
1186 UINT64_C(3407872160), // A4_vrminh
1187 UINT64_C(3407880352), // A4_vrminuh
1188 UINT64_C(3407880384), // A4_vrminuw
1189 UINT64_C(3407872192), // A4_vrminw
1190 UINT64_C(3936354304), // A5_ACS
1191 UINT64_C(3242197024), // A5_vaddhubs
1192 UINT64_C(3523223584), // A6_vcmpbeq_notany
1193 UINT64_C(3940548608), // A6_vminub_RdP
1194 UINT64_C(2294284448), // A7_clip
1195 UINT64_C(2363490368), // A7_croundd_ri
1196 UINT64_C(3334471744), // A7_croundd_rr
1197 UINT64_C(2294284480), // A7_vclip
1198 UINT64_C(1805647872), // C2_all8
1199 UINT64_C(1795162112), // C2_and
1200 UINT64_C(1801453568), // C2_andn
1201 UINT64_C(1803550720), // C2_any8
1202 UINT64_C(3347054592), // C2_bitsclr
1203 UINT64_C(2239758336), // C2_bitsclri
1204 UINT64_C(3342860288), // C2_bitsset
1205 UINT64_C(4244635776), // C2_ccombinewf
1206 UINT64_C(4244643968), // C2_ccombinewnewf
1207 UINT64_C(4244643840), // C2_ccombinewnewt
1208 UINT64_C(4244635648), // C2_ccombinewt
1209 UINT64_C(2122317824), // C2_cmoveif
1210 UINT64_C(2113929216), // C2_cmoveit
1211 UINT64_C(2122326016), // C2_cmovenewif
1212 UINT64_C(2113937408), // C2_cmovenewit
1213 UINT64_C(4060086272), // C2_cmpeq
1214 UINT64_C(1962934272), // C2_cmpeqi
1215 UINT64_C(3531603968), // C2_cmpeqp
1216 UINT64_C(4064280576), // C2_cmpgt
1217 UINT64_C(1967128576), // C2_cmpgti
1218 UINT64_C(3531604032), // C2_cmpgtp
1219 UINT64_C(4066377728), // C2_cmpgtu
1220 UINT64_C(1971322880), // C2_cmpgtui
1221 UINT64_C(3531604096), // C2_cmpgtup
1222 UINT64_C(2248146944), // C2_mask
1223 UINT64_C(4093640704), // C2_mux
1224 UINT64_C(2046820352), // C2_muxii
1225 UINT64_C(1929379840), // C2_muxir
1226 UINT64_C(1937768448), // C2_muxri
1227 UINT64_C(1807745024), // C2_not
1228 UINT64_C(1797259264), // C2_or
1229 UINT64_C(1809842176), // C2_orn
1230 UINT64_C(2302672896), // C2_tfrpr
1231 UINT64_C(2235564032), // C2_tfrrp
1232 UINT64_C(2298478592), // C2_vitpack
1233 UINT64_C(3506438144), // C2_vmux
1234 UINT64_C(1799356416), // C2_xor
1235 UINT64_C(1783169024), // C4_addipc
1236 UINT64_C(1796210688), // C4_and_and
1237 UINT64_C(1804599296), // C4_and_andn
1238 UINT64_C(1798307840), // C4_and_or
1239 UINT64_C(1806696448), // C4_and_orn
1240 UINT64_C(4064280592), // C4_cmplte
1241 UINT64_C(1967128592), // C4_cmpltei
1242 UINT64_C(4066377744), // C4_cmplteu
1243 UINT64_C(1971322896), // C4_cmplteui
1244 UINT64_C(4060086288), // C4_cmpneq
1245 UINT64_C(1962934288), // C4_cmpneqi
1246 UINT64_C(1795170448), // C4_fastcorner9
1247 UINT64_C(1796219024), // C4_fastcorner9_not
1248 UINT64_C(3349151744), // C4_nbitsclr
1249 UINT64_C(2241855488), // C4_nbitsclri
1250 UINT64_C(3344957440), // C4_nbitsset
1251 UINT64_C(1800404992), // C4_or_and
1252 UINT64_C(1808793600), // C4_or_andn
1253 UINT64_C(1802502144), // C4_or_or
1254 UINT64_C(1810890752), // C4_or_orn
1255 UINT64_C(1509949440), // CALLProfile
1256 UINT64_C(0), // CONST32
1257 UINT64_C(0), // CONST64
1258 UINT64_C(0), // DuplexIClass0
1259 UINT64_C(8192), // DuplexIClass1
1260 UINT64_C(536870912), // DuplexIClass2
1261 UINT64_C(536879104), // DuplexIClass3
1262 UINT64_C(1073741824), // DuplexIClass4
1263 UINT64_C(1073750016), // DuplexIClass5
1264 UINT64_C(1610612736), // DuplexIClass6
1265 UINT64_C(1610620928), // DuplexIClass7
1266 UINT64_C(2147483648), // DuplexIClass8
1267 UINT64_C(2147491840), // DuplexIClass9
1268 UINT64_C(2684354560), // DuplexIClassA
1269 UINT64_C(2684362752), // DuplexIClassB
1270 UINT64_C(3221225472), // DuplexIClassC
1271 UINT64_C(3221233664), // DuplexIClassD
1272 UINT64_C(3758096384), // DuplexIClassE
1273 UINT64_C(3758104576), // DuplexIClassF
1274 UINT64_C(1384120320), // EH_RETURN_JMPR
1275 UINT64_C(2162163808), // F2_conv_d2df
1276 UINT64_C(2285895712), // F2_conv_d2sf
1277 UINT64_C(2162163712), // F2_conv_df2d
1278 UINT64_C(2162163904), // F2_conv_df2d_chop
1279 UINT64_C(2281701408), // F2_conv_df2sf
1280 UINT64_C(2162163744), // F2_conv_df2ud
1281 UINT64_C(2162163936), // F2_conv_df2ud_chop
1282 UINT64_C(2287992864), // F2_conv_df2uw
1283 UINT64_C(2292187168), // F2_conv_df2uw_chop
1284 UINT64_C(2290090016), // F2_conv_df2w
1285 UINT64_C(2296381472), // F2_conv_df2w_chop
1286 UINT64_C(2222981248), // F2_conv_sf2d
1287 UINT64_C(2222981312), // F2_conv_sf2d_chop
1288 UINT64_C(2222981120), // F2_conv_sf2df
1289 UINT64_C(2222981216), // F2_conv_sf2ud
1290 UINT64_C(2222981280), // F2_conv_sf2ud_chop
1291 UINT64_C(2338324480), // F2_conv_sf2uw
1292 UINT64_C(2338324512), // F2_conv_sf2uw_chop
1293 UINT64_C(2340421632), // F2_conv_sf2w
1294 UINT64_C(2340421664), // F2_conv_sf2w_chop
1295 UINT64_C(2162163776), // F2_conv_ud2df
1296 UINT64_C(2283798560), // F2_conv_ud2sf
1297 UINT64_C(2222981152), // F2_conv_uw2df
1298 UINT64_C(2334130176), // F2_conv_uw2sf
1299 UINT64_C(2222981184), // F2_conv_w2df
1300 UINT64_C(2336227328), // F2_conv_w2sf
1301 UINT64_C(3892314208), // F2_dfadd
1302 UINT64_C(3699376144), // F2_dfclass
1303 UINT64_C(3537895424), // F2_dfcmpeq
1304 UINT64_C(3537895488), // F2_dfcmpge
1305 UINT64_C(3537895456), // F2_dfcmpgt
1306 UINT64_C(3537895520), // F2_dfcmpuo
1307 UINT64_C(3644850176), // F2_dfimm_n
1308 UINT64_C(3640655872), // F2_dfimm_p
1309 UINT64_C(3894411360), // F2_dfmax
1310 UINT64_C(3904897120), // F2_dfmin
1311 UINT64_C(3896508512), // F2_dfmpyfix
1312 UINT64_C(3934257248), // F2_dfmpyhh
1313 UINT64_C(3925868640), // F2_dfmpylh
1314 UINT64_C(3902799968), // F2_dfmpyll
1315 UINT64_C(3900702816), // F2_dfsub
1316 UINT64_C(3942645760), // F2_sfadd
1317 UINT64_C(2246049792), // F2_sfclass
1318 UINT64_C(3353346144), // F2_sfcmpeq
1319 UINT64_C(3353346048), // F2_sfcmpge
1320 UINT64_C(3353346176), // F2_sfcmpgt
1321 UINT64_C(3353346080), // F2_sfcmpuo
1322 UINT64_C(3955228704), // F2_sffixupd
1323 UINT64_C(3955228672), // F2_sffixupn
1324 UINT64_C(2342518784), // F2_sffixupr
1325 UINT64_C(4009754752), // F2_sffma
1326 UINT64_C(4009754816), // F2_sffma_lib
1327 UINT64_C(4016046208), // F2_sffma_sc
1328 UINT64_C(4009754784), // F2_sffms
1329 UINT64_C(4009754848), // F2_sffms_lib
1330 UINT64_C(3594518528), // F2_sfimm_n
1331 UINT64_C(3590324224), // F2_sfimm_p
1332 UINT64_C(2346713088), // F2_sfinvsqrta
1333 UINT64_C(3951034368), // F2_sfmax
1334 UINT64_C(3951034400), // F2_sfmin
1335 UINT64_C(3946840064), // F2_sfmpy
1336 UINT64_C(3957325952), // F2_sfrecipa
1337 UINT64_C(3942645792), // F2_sfsub
1338 UINT64_C(1746927616), // G4_tfrgcpp
1339 UINT64_C(1780482048), // G4_tfrgcrr
1340 UINT64_C(1660944384), // G4_tfrgpcp
1341 UINT64_C(1644167168), // G4_tfrgrcr
1342 UINT64_C(35651584), // HI
1343 UINT64_C(1509949440), // J2_call
1344 UINT64_C(1562378240), // J2_callf
1345 UINT64_C(1352663040), // J2_callr
1346 UINT64_C(1361051648), // J2_callrf
1347 UINT64_C(1354760192), // J2_callrh
1348 UINT64_C(1358954496), // J2_callrt
1349 UINT64_C(1560281088), // J2_callt
1350 UINT64_C(1476395008), // J2_jump
1351 UINT64_C(1545601024), // J2_jumpf
1352 UINT64_C(1545603072), // J2_jumpfnew
1353 UINT64_C(1545607168), // J2_jumpfnewpt
1354 UINT64_C(1545605120), // J2_jumpfpt
1355 UINT64_C(1384120320), // J2_jumpr
1356 UINT64_C(1398800384), // J2_jumprf
1357 UINT64_C(1398802432), // J2_jumprfnew
1358 UINT64_C(1398806528), // J2_jumprfnewpt
1359 UINT64_C(1398804480), // J2_jumprfpt
1360 UINT64_C(1631584256), // J2_jumprgtez
1361 UINT64_C(1631588352), // J2_jumprgtezpt
1362 UINT64_C(1388314624), // J2_jumprh
1363 UINT64_C(1639972864), // J2_jumprltez
1364 UINT64_C(1639976960), // J2_jumprltezpt
1365 UINT64_C(1635778560), // J2_jumprnz
1366 UINT64_C(1635782656), // J2_jumprnzpt
1367 UINT64_C(1396703232), // J2_jumprt
1368 UINT64_C(1396705280), // J2_jumprtnew
1369 UINT64_C(1396709376), // J2_jumprtnewpt
1370 UINT64_C(1396707328), // J2_jumprtpt
1371 UINT64_C(1627389952), // J2_jumprz
1372 UINT64_C(1627394048), // J2_jumprzpt
1373 UINT64_C(1543503872), // J2_jumpt
1374 UINT64_C(1543505920), // J2_jumptnew
1375 UINT64_C(1543510016), // J2_jumptnewpt
1376 UINT64_C(1543507968), // J2_jumptpt
1377 UINT64_C(1761607680), // J2_loop0i
1378 UINT64_C(1761607680), // J2_loop0iext
1379 UINT64_C(1610612736), // J2_loop0r
1380 UINT64_C(1610612736), // J2_loop0rext
1381 UINT64_C(1763704832), // J2_loop1i
1382 UINT64_C(1763704832), // J2_loop1iext
1383 UINT64_C(1612709888), // J2_loop1r
1384 UINT64_C(1612709888), // J2_loop1rext
1385 UINT64_C(1413480448), // J2_pause
1386 UINT64_C(1772093440), // J2_ploop1si
1387 UINT64_C(1621098496), // J2_ploop1sr
1388 UINT64_C(1774190592), // J2_ploop2si
1389 UINT64_C(1623195648), // J2_ploop2sr
1390 UINT64_C(1776287744), // J2_ploop3si
1391 UINT64_C(1625292800), // J2_ploop3sr
1392 UINT64_C(1474297856), // J2_rte
1393 UINT64_C(1409286144), // J2_trap0
1394 UINT64_C(1417674752), // J2_trap1
1395 UINT64_C(1474301952), // J2_unpause
1396 UINT64_C(541065216), // J4_cmpeq_f_jumpnv_nt
1397 UINT64_C(541073408), // J4_cmpeq_f_jumpnv_t
1398 UINT64_C(339738624), // J4_cmpeq_fp0_jump_nt
1399 UINT64_C(339746816), // J4_cmpeq_fp0_jump_t
1400 UINT64_C(339742720), // J4_cmpeq_fp1_jump_nt
1401 UINT64_C(339750912), // J4_cmpeq_fp1_jump_t
1402 UINT64_C(536870912), // J4_cmpeq_t_jumpnv_nt
1403 UINT64_C(536879104), // J4_cmpeq_t_jumpnv_t
1404 UINT64_C(335544320), // J4_cmpeq_tp0_jump_nt
1405 UINT64_C(335552512), // J4_cmpeq_tp0_jump_t
1406 UINT64_C(335548416), // J4_cmpeq_tp1_jump_nt
1407 UINT64_C(335556608), // J4_cmpeq_tp1_jump_t
1408 UINT64_C(608174080), // J4_cmpeqi_f_jumpnv_nt
1409 UINT64_C(608182272), // J4_cmpeqi_f_jumpnv_t
1410 UINT64_C(272629760), // J4_cmpeqi_fp0_jump_nt
1411 UINT64_C(272637952), // J4_cmpeqi_fp0_jump_t
1412 UINT64_C(306184192), // J4_cmpeqi_fp1_jump_nt
1413 UINT64_C(306192384), // J4_cmpeqi_fp1_jump_t
1414 UINT64_C(603979776), // J4_cmpeqi_t_jumpnv_nt
1415 UINT64_C(603987968), // J4_cmpeqi_t_jumpnv_t
1416 UINT64_C(268435456), // J4_cmpeqi_tp0_jump_nt
1417 UINT64_C(268443648), // J4_cmpeqi_tp0_jump_t
1418 UINT64_C(301989888), // J4_cmpeqi_tp1_jump_nt
1419 UINT64_C(301998080), // J4_cmpeqi_tp1_jump_t
1420 UINT64_C(641728512), // J4_cmpeqn1_f_jumpnv_nt
1421 UINT64_C(641736704), // J4_cmpeqn1_f_jumpnv_t
1422 UINT64_C(297795584), // J4_cmpeqn1_fp0_jump_nt
1423 UINT64_C(297803776), // J4_cmpeqn1_fp0_jump_t
1424 UINT64_C(331350016), // J4_cmpeqn1_fp1_jump_nt
1425 UINT64_C(331358208), // J4_cmpeqn1_fp1_jump_t
1426 UINT64_C(637534208), // J4_cmpeqn1_t_jumpnv_nt
1427 UINT64_C(637542400), // J4_cmpeqn1_t_jumpnv_t
1428 UINT64_C(293601280), // J4_cmpeqn1_tp0_jump_nt
1429 UINT64_C(293609472), // J4_cmpeqn1_tp0_jump_t
1430 UINT64_C(327155712), // J4_cmpeqn1_tp1_jump_nt
1431 UINT64_C(327163904), // J4_cmpeqn1_tp1_jump_t
1432 UINT64_C(549453824), // J4_cmpgt_f_jumpnv_nt
1433 UINT64_C(549462016), // J4_cmpgt_f_jumpnv_t
1434 UINT64_C(348127232), // J4_cmpgt_fp0_jump_nt
1435 UINT64_C(348135424), // J4_cmpgt_fp0_jump_t
1436 UINT64_C(348131328), // J4_cmpgt_fp1_jump_nt
1437 UINT64_C(348139520), // J4_cmpgt_fp1_jump_t
1438 UINT64_C(545259520), // J4_cmpgt_t_jumpnv_nt
1439 UINT64_C(545267712), // J4_cmpgt_t_jumpnv_t
1440 UINT64_C(343932928), // J4_cmpgt_tp0_jump_nt
1441 UINT64_C(343941120), // J4_cmpgt_tp0_jump_t
1442 UINT64_C(343937024), // J4_cmpgt_tp1_jump_nt
1443 UINT64_C(343945216), // J4_cmpgt_tp1_jump_t
1444 UINT64_C(616562688), // J4_cmpgti_f_jumpnv_nt
1445 UINT64_C(616570880), // J4_cmpgti_f_jumpnv_t
1446 UINT64_C(281018368), // J4_cmpgti_fp0_jump_nt
1447 UINT64_C(281026560), // J4_cmpgti_fp0_jump_t
1448 UINT64_C(314572800), // J4_cmpgti_fp1_jump_nt
1449 UINT64_C(314580992), // J4_cmpgti_fp1_jump_t
1450 UINT64_C(612368384), // J4_cmpgti_t_jumpnv_nt
1451 UINT64_C(612376576), // J4_cmpgti_t_jumpnv_t
1452 UINT64_C(276824064), // J4_cmpgti_tp0_jump_nt
1453 UINT64_C(276832256), // J4_cmpgti_tp0_jump_t
1454 UINT64_C(310378496), // J4_cmpgti_tp1_jump_nt
1455 UINT64_C(310386688), // J4_cmpgti_tp1_jump_t
1456 UINT64_C(650117120), // J4_cmpgtn1_f_jumpnv_nt
1457 UINT64_C(650125312), // J4_cmpgtn1_f_jumpnv_t
1458 UINT64_C(297795840), // J4_cmpgtn1_fp0_jump_nt
1459 UINT64_C(297804032), // J4_cmpgtn1_fp0_jump_t
1460 UINT64_C(331350272), // J4_cmpgtn1_fp1_jump_nt
1461 UINT64_C(331358464), // J4_cmpgtn1_fp1_jump_t
1462 UINT64_C(645922816), // J4_cmpgtn1_t_jumpnv_nt
1463 UINT64_C(645931008), // J4_cmpgtn1_t_jumpnv_t
1464 UINT64_C(293601536), // J4_cmpgtn1_tp0_jump_nt
1465 UINT64_C(293609728), // J4_cmpgtn1_tp0_jump_t
1466 UINT64_C(327155968), // J4_cmpgtn1_tp1_jump_nt
1467 UINT64_C(327164160), // J4_cmpgtn1_tp1_jump_t
1468 UINT64_C(557842432), // J4_cmpgtu_f_jumpnv_nt
1469 UINT64_C(557850624), // J4_cmpgtu_f_jumpnv_t
1470 UINT64_C(356515840), // J4_cmpgtu_fp0_jump_nt
1471 UINT64_C(356524032), // J4_cmpgtu_fp0_jump_t
1472 UINT64_C(356519936), // J4_cmpgtu_fp1_jump_nt
1473 UINT64_C(356528128), // J4_cmpgtu_fp1_jump_t
1474 UINT64_C(553648128), // J4_cmpgtu_t_jumpnv_nt
1475 UINT64_C(553656320), // J4_cmpgtu_t_jumpnv_t
1476 UINT64_C(352321536), // J4_cmpgtu_tp0_jump_nt
1477 UINT64_C(352329728), // J4_cmpgtu_tp0_jump_t
1478 UINT64_C(352325632), // J4_cmpgtu_tp1_jump_nt
1479 UINT64_C(352333824), // J4_cmpgtu_tp1_jump_t
1480 UINT64_C(624951296), // J4_cmpgtui_f_jumpnv_nt
1481 UINT64_C(624959488), // J4_cmpgtui_f_jumpnv_t
1482 UINT64_C(289406976), // J4_cmpgtui_fp0_jump_nt
1483 UINT64_C(289415168), // J4_cmpgtui_fp0_jump_t
1484 UINT64_C(322961408), // J4_cmpgtui_fp1_jump_nt
1485 UINT64_C(322969600), // J4_cmpgtui_fp1_jump_t
1486 UINT64_C(620756992), // J4_cmpgtui_t_jumpnv_nt
1487 UINT64_C(620765184), // J4_cmpgtui_t_jumpnv_t
1488 UINT64_C(285212672), // J4_cmpgtui_tp0_jump_nt
1489 UINT64_C(285220864), // J4_cmpgtui_tp0_jump_t
1490 UINT64_C(318767104), // J4_cmpgtui_tp1_jump_nt
1491 UINT64_C(318775296), // J4_cmpgtui_tp1_jump_t
1492 UINT64_C(566231040), // J4_cmplt_f_jumpnv_nt
1493 UINT64_C(566239232), // J4_cmplt_f_jumpnv_t
1494 UINT64_C(562036736), // J4_cmplt_t_jumpnv_nt
1495 UINT64_C(562044928), // J4_cmplt_t_jumpnv_t
1496 UINT64_C(574619648), // J4_cmpltu_f_jumpnv_nt
1497 UINT64_C(574627840), // J4_cmpltu_f_jumpnv_t
1498 UINT64_C(570425344), // J4_cmpltu_t_jumpnv_nt
1499 UINT64_C(570433536), // J4_cmpltu_t_jumpnv_t
1500 UINT64_C(1386217472), // J4_hintjumpr
1501 UINT64_C(369098752), // J4_jumpseti
1502 UINT64_C(385875968), // J4_jumpsetr
1503 UINT64_C(633339904), // J4_tstbit0_f_jumpnv_nt
1504 UINT64_C(633348096), // J4_tstbit0_f_jumpnv_t
1505 UINT64_C(297796352), // J4_tstbit0_fp0_jump_nt
1506 UINT64_C(297804544), // J4_tstbit0_fp0_jump_t
1507 UINT64_C(331350784), // J4_tstbit0_fp1_jump_nt
1508 UINT64_C(331358976), // J4_tstbit0_fp1_jump_t
1509 UINT64_C(629145600), // J4_tstbit0_t_jumpnv_nt
1510 UINT64_C(629153792), // J4_tstbit0_t_jumpnv_t
1511 UINT64_C(293602048), // J4_tstbit0_tp0_jump_nt
1512 UINT64_C(293610240), // J4_tstbit0_tp0_jump_t
1513 UINT64_C(327156480), // J4_tstbit0_tp1_jump_nt
1514 UINT64_C(327164672), // J4_tstbit0_tp1_jump_t
1515 UINT64_C(2415919104), // L2_deallocframe
1516 UINT64_C(2424307712), // L2_loadalignb_io
1517 UINT64_C(2659188736), // L2_loadalignb_pbr
1518 UINT64_C(2558525440), // L2_loadalignb_pci
1519 UINT64_C(2558525952), // L2_loadalignb_pcr
1520 UINT64_C(2592079872), // L2_loadalignb_pi
1521 UINT64_C(2625634304), // L2_loadalignb_pr
1522 UINT64_C(2420113408), // L2_loadalignh_io
1523 UINT64_C(2654994432), // L2_loadalignh_pbr
1524 UINT64_C(2554331136), // L2_loadalignh_pci
1525 UINT64_C(2554331648), // L2_loadalignh_pcr
1526 UINT64_C(2587885568), // L2_loadalignh_pi
1527 UINT64_C(2621440000), // L2_loadalignh_pr
1528 UINT64_C(2418016256), // L2_loadbsw2_io
1529 UINT64_C(2652897280), // L2_loadbsw2_pbr
1530 UINT64_C(2552233984), // L2_loadbsw2_pci
1531 UINT64_C(2552234496), // L2_loadbsw2_pcr
1532 UINT64_C(2585788416), // L2_loadbsw2_pi
1533 UINT64_C(2619342848), // L2_loadbsw2_pr
1534 UINT64_C(2430599168), // L2_loadbsw4_io
1535 UINT64_C(2665480192), // L2_loadbsw4_pbr
1536 UINT64_C(2564816896), // L2_loadbsw4_pci
1537 UINT64_C(2564817408), // L2_loadbsw4_pcr
1538 UINT64_C(2598371328), // L2_loadbsw4_pi
1539 UINT64_C(2631925760), // L2_loadbsw4_pr
1540 UINT64_C(2422210560), // L2_loadbzw2_io
1541 UINT64_C(2657091584), // L2_loadbzw2_pbr
1542 UINT64_C(2556428288), // L2_loadbzw2_pci
1543 UINT64_C(2556428800), // L2_loadbzw2_pcr
1544 UINT64_C(2589982720), // L2_loadbzw2_pi
1545 UINT64_C(2623537152), // L2_loadbzw2_pr
1546 UINT64_C(2426404864), // L2_loadbzw4_io
1547 UINT64_C(2661285888), // L2_loadbzw4_pbr
1548 UINT64_C(2560622592), // L2_loadbzw4_pci
1549 UINT64_C(2560623104), // L2_loadbzw4_pcr
1550 UINT64_C(2594177024), // L2_loadbzw4_pi
1551 UINT64_C(2627731456), // L2_loadbzw4_pr
1552 UINT64_C(2432696320), // L2_loadrb_io
1553 UINT64_C(2667577344), // L2_loadrb_pbr
1554 UINT64_C(2566914048), // L2_loadrb_pci
1555 UINT64_C(2566914560), // L2_loadrb_pcr
1556 UINT64_C(2600468480), // L2_loadrb_pi
1557 UINT64_C(2634022912), // L2_loadrb_pr
1558 UINT64_C(1224736768), // L2_loadrbgp
1559 UINT64_C(2445279232), // L2_loadrd_io
1560 UINT64_C(2680160256), // L2_loadrd_pbr
1561 UINT64_C(2579496960), // L2_loadrd_pci
1562 UINT64_C(2579497472), // L2_loadrd_pcr
1563 UINT64_C(2613051392), // L2_loadrd_pi
1564 UINT64_C(2646605824), // L2_loadrd_pr
1565 UINT64_C(1237319680), // L2_loadrdgp
1566 UINT64_C(2436890624), // L2_loadrh_io
1567 UINT64_C(2671771648), // L2_loadrh_pbr
1568 UINT64_C(2571108352), // L2_loadrh_pci
1569 UINT64_C(2571108864), // L2_loadrh_pcr
1570 UINT64_C(2604662784), // L2_loadrh_pi
1571 UINT64_C(2638217216), // L2_loadrh_pr
1572 UINT64_C(1228931072), // L2_loadrhgp
1573 UINT64_C(2441084928), // L2_loadri_io
1574 UINT64_C(2675965952), // L2_loadri_pbr
1575 UINT64_C(2575302656), // L2_loadri_pci
1576 UINT64_C(2575303168), // L2_loadri_pcr
1577 UINT64_C(2608857088), // L2_loadri_pi
1578 UINT64_C(2642411520), // L2_loadri_pr
1579 UINT64_C(1233125376), // L2_loadrigp
1580 UINT64_C(2434793472), // L2_loadrub_io
1581 UINT64_C(2669674496), // L2_loadrub_pbr
1582 UINT64_C(2569011200), // L2_loadrub_pci
1583 UINT64_C(2569011712), // L2_loadrub_pcr
1584 UINT64_C(2602565632), // L2_loadrub_pi
1585 UINT64_C(2636120064), // L2_loadrub_pr
1586 UINT64_C(1226833920), // L2_loadrubgp
1587 UINT64_C(2438987776), // L2_loadruh_io
1588 UINT64_C(2673868800), // L2_loadruh_pbr
1589 UINT64_C(2573205504), // L2_loadruh_pci
1590 UINT64_C(2573206016), // L2_loadruh_pcr
1591 UINT64_C(2606759936), // L2_loadruh_pi
1592 UINT64_C(2640314368), // L2_loadruh_pr
1593 UINT64_C(1231028224), // L2_loadruhgp
1594 UINT64_C(2449475584), // L2_loadw_aq
1595 UINT64_C(2449473536), // L2_loadw_locked
1596 UINT64_C(1157627904), // L2_ploadrbf_io
1597 UINT64_C(2600478720), // L2_ploadrbf_pi
1598 UINT64_C(1191182336), // L2_ploadrbfnew_io
1599 UINT64_C(2600482816), // L2_ploadrbfnew_pi
1600 UINT64_C(1090519040), // L2_ploadrbt_io
1601 UINT64_C(2600476672), // L2_ploadrbt_pi
1602 UINT64_C(1124073472), // L2_ploadrbtnew_io
1603 UINT64_C(2600480768), // L2_ploadrbtnew_pi
1604 UINT64_C(1170210816), // L2_ploadrdf_io
1605 UINT64_C(2613061632), // L2_ploadrdf_pi
1606 UINT64_C(1203765248), // L2_ploadrdfnew_io
1607 UINT64_C(2613065728), // L2_ploadrdfnew_pi
1608 UINT64_C(1103101952), // L2_ploadrdt_io
1609 UINT64_C(2613059584), // L2_ploadrdt_pi
1610 UINT64_C(1136656384), // L2_ploadrdtnew_io
1611 UINT64_C(2613063680), // L2_ploadrdtnew_pi
1612 UINT64_C(1161822208), // L2_ploadrhf_io
1613 UINT64_C(2604673024), // L2_ploadrhf_pi
1614 UINT64_C(1195376640), // L2_ploadrhfnew_io
1615 UINT64_C(2604677120), // L2_ploadrhfnew_pi
1616 UINT64_C(1094713344), // L2_ploadrht_io
1617 UINT64_C(2604670976), // L2_ploadrht_pi
1618 UINT64_C(1128267776), // L2_ploadrhtnew_io
1619 UINT64_C(2604675072), // L2_ploadrhtnew_pi
1620 UINT64_C(1166016512), // L2_ploadrif_io
1621 UINT64_C(2608867328), // L2_ploadrif_pi
1622 UINT64_C(1199570944), // L2_ploadrifnew_io
1623 UINT64_C(2608871424), // L2_ploadrifnew_pi
1624 UINT64_C(1098907648), // L2_ploadrit_io
1625 UINT64_C(2608865280), // L2_ploadrit_pi
1626 UINT64_C(1132462080), // L2_ploadritnew_io
1627 UINT64_C(2608869376), // L2_ploadritnew_pi
1628 UINT64_C(1159725056), // L2_ploadrubf_io
1629 UINT64_C(2602575872), // L2_ploadrubf_pi
1630 UINT64_C(1193279488), // L2_ploadrubfnew_io
1631 UINT64_C(2602579968), // L2_ploadrubfnew_pi
1632 UINT64_C(1092616192), // L2_ploadrubt_io
1633 UINT64_C(2602573824), // L2_ploadrubt_pi
1634 UINT64_C(1126170624), // L2_ploadrubtnew_io
1635 UINT64_C(2602577920), // L2_ploadrubtnew_pi
1636 UINT64_C(1163919360), // L2_ploadruhf_io
1637 UINT64_C(2606770176), // L2_ploadruhf_pi
1638 UINT64_C(1197473792), // L2_ploadruhfnew_io
1639 UINT64_C(2606774272), // L2_ploadruhfnew_pi
1640 UINT64_C(1096810496), // L2_ploadruht_io
1641 UINT64_C(2606768128), // L2_ploadruht_pi
1642 UINT64_C(1130364928), // L2_ploadruhtnew_io
1643 UINT64_C(2606772224), // L2_ploadruhtnew_pi
1644 UINT64_C(1040187392), // L4_add_memopb_io
1645 UINT64_C(1042284544), // L4_add_memoph_io
1646 UINT64_C(1044381696), // L4_add_memopw_io
1647 UINT64_C(1040187456), // L4_and_memopb_io
1648 UINT64_C(1042284608), // L4_and_memoph_io
1649 UINT64_C(1044381760), // L4_and_memopw_io
1650 UINT64_C(1056964608), // L4_iadd_memopb_io
1651 UINT64_C(1059061760), // L4_iadd_memoph_io
1652 UINT64_C(1061158912), // L4_iadd_memopw_io
1653 UINT64_C(1056964672), // L4_iand_memopb_io
1654 UINT64_C(1059061824), // L4_iand_memoph_io
1655 UINT64_C(1061158976), // L4_iand_memopw_io
1656 UINT64_C(1056964704), // L4_ior_memopb_io
1657 UINT64_C(1059061856), // L4_ior_memoph_io
1658 UINT64_C(1061159008), // L4_ior_memopw_io
1659 UINT64_C(1056964640), // L4_isub_memopb_io
1660 UINT64_C(1059061792), // L4_isub_memoph_io
1661 UINT64_C(1061158944), // L4_isub_memopw_io
1662 UINT64_C(2592083968), // L4_loadalignb_ap
1663 UINT64_C(2625638400), // L4_loadalignb_ur
1664 UINT64_C(2587889664), // L4_loadalignh_ap
1665 UINT64_C(2621444096), // L4_loadalignh_ur
1666 UINT64_C(2585792512), // L4_loadbsw2_ap
1667 UINT64_C(2619346944), // L4_loadbsw2_ur
1668 UINT64_C(2598375424), // L4_loadbsw4_ap
1669 UINT64_C(2631929856), // L4_loadbsw4_ur
1670 UINT64_C(2589986816), // L4_loadbzw2_ap
1671 UINT64_C(2623541248), // L4_loadbzw2_ur
1672 UINT64_C(2594181120), // L4_loadbzw4_ap
1673 UINT64_C(2627735552), // L4_loadbzw4_ur
1674 UINT64_C(2449479680), // L4_loadd_aq
1675 UINT64_C(2449477632), // L4_loadd_locked
1676 UINT64_C(2600472576), // L4_loadrb_ap
1677 UINT64_C(973078528), // L4_loadrb_rr
1678 UINT64_C(2634027008), // L4_loadrb_ur
1679 UINT64_C(2613055488), // L4_loadrd_ap
1680 UINT64_C(985661440), // L4_loadrd_rr
1681 UINT64_C(2646609920), // L4_loadrd_ur
1682 UINT64_C(2604666880), // L4_loadrh_ap
1683 UINT64_C(977272832), // L4_loadrh_rr
1684 UINT64_C(2638221312), // L4_loadrh_ur
1685 UINT64_C(2608861184), // L4_loadri_ap
1686 UINT64_C(981467136), // L4_loadri_rr
1687 UINT64_C(2642415616), // L4_loadri_ur
1688 UINT64_C(2602569728), // L4_loadrub_ap
1689 UINT64_C(975175680), // L4_loadrub_rr
1690 UINT64_C(2636124160), // L4_loadrub_ur
1691 UINT64_C(2606764032), // L4_loadruh_ap
1692 UINT64_C(979369984), // L4_loadruh_rr
1693 UINT64_C(2640318464), // L4_loadruh_ur
1694 UINT64_C(2449481728), // L4_loadw_phys
1695 UINT64_C(1040187488), // L4_or_memopb_io
1696 UINT64_C(1042284640), // L4_or_memoph_io
1697 UINT64_C(1044381792), // L4_or_memopw_io
1698 UINT64_C(2667587712), // L4_ploadrbf_abs
1699 UINT64_C(822083584), // L4_ploadrbf_rr
1700 UINT64_C(2667591808), // L4_ploadrbfnew_abs
1701 UINT64_C(855638016), // L4_ploadrbfnew_rr
1702 UINT64_C(2667585664), // L4_ploadrbt_abs
1703 UINT64_C(805306368), // L4_ploadrbt_rr
1704 UINT64_C(2667589760), // L4_ploadrbtnew_abs
1705 UINT64_C(838860800), // L4_ploadrbtnew_rr
1706 UINT64_C(2680170624), // L4_ploadrdf_abs
1707 UINT64_C(834666496), // L4_ploadrdf_rr
1708 UINT64_C(2680174720), // L4_ploadrdfnew_abs
1709 UINT64_C(868220928), // L4_ploadrdfnew_rr
1710 UINT64_C(2680168576), // L4_ploadrdt_abs
1711 UINT64_C(817889280), // L4_ploadrdt_rr
1712 UINT64_C(2680172672), // L4_ploadrdtnew_abs
1713 UINT64_C(851443712), // L4_ploadrdtnew_rr
1714 UINT64_C(2671782016), // L4_ploadrhf_abs
1715 UINT64_C(826277888), // L4_ploadrhf_rr
1716 UINT64_C(2671786112), // L4_ploadrhfnew_abs
1717 UINT64_C(859832320), // L4_ploadrhfnew_rr
1718 UINT64_C(2671779968), // L4_ploadrht_abs
1719 UINT64_C(809500672), // L4_ploadrht_rr
1720 UINT64_C(2671784064), // L4_ploadrhtnew_abs
1721 UINT64_C(843055104), // L4_ploadrhtnew_rr
1722 UINT64_C(2675976320), // L4_ploadrif_abs
1723 UINT64_C(830472192), // L4_ploadrif_rr
1724 UINT64_C(2675980416), // L4_ploadrifnew_abs
1725 UINT64_C(864026624), // L4_ploadrifnew_rr
1726 UINT64_C(2675974272), // L4_ploadrit_abs
1727 UINT64_C(813694976), // L4_ploadrit_rr
1728 UINT64_C(2675978368), // L4_ploadritnew_abs
1729 UINT64_C(847249408), // L4_ploadritnew_rr
1730 UINT64_C(2669684864), // L4_ploadrubf_abs
1731 UINT64_C(824180736), // L4_ploadrubf_rr
1732 UINT64_C(2669688960), // L4_ploadrubfnew_abs
1733 UINT64_C(857735168), // L4_ploadrubfnew_rr
1734 UINT64_C(2669682816), // L4_ploadrubt_abs
1735 UINT64_C(807403520), // L4_ploadrubt_rr
1736 UINT64_C(2669686912), // L4_ploadrubtnew_abs
1737 UINT64_C(840957952), // L4_ploadrubtnew_rr
1738 UINT64_C(2673879168), // L4_ploadruhf_abs
1739 UINT64_C(828375040), // L4_ploadruhf_rr
1740 UINT64_C(2673883264), // L4_ploadruhfnew_abs
1741 UINT64_C(861929472), // L4_ploadruhfnew_rr
1742 UINT64_C(2673877120), // L4_ploadruht_abs
1743 UINT64_C(811597824), // L4_ploadruht_rr
1744 UINT64_C(2673881216), // L4_ploadruhtnew_abs
1745 UINT64_C(845152256), // L4_ploadruhtnew_rr
1746 UINT64_C(2516582400), // L4_return
1747 UINT64_C(2516594688), // L4_return_f
1748 UINT64_C(2516592640), // L4_return_fnew_pnt
1749 UINT64_C(2516596736), // L4_return_fnew_pt
1750 UINT64_C(2516586496), // L4_return_t
1751 UINT64_C(2516584448), // L4_return_tnew_pnt
1752 UINT64_C(2516588544), // L4_return_tnew_pt
1753 UINT64_C(1040187424), // L4_sub_memopb_io
1754 UINT64_C(1042284576), // L4_sub_memoph_io
1755 UINT64_C(1044381728), // L4_sub_memopw_io
1756 UINT64_C(2449473600), // L6_memcpy
1757 UINT64_C(18874368), // LO
1758 UINT64_C(4009754656), // M2_acci
1759 UINT64_C(3791650816), // M2_accii
1760 UINT64_C(3875536928), // M2_cmaci_s0
1761 UINT64_C(3875536960), // M2_cmacr_s0
1762 UINT64_C(3875537088), // M2_cmacs_s0
1763 UINT64_C(3883925696), // M2_cmacs_s1
1764 UINT64_C(3879731392), // M2_cmacsc_s0
1765 UINT64_C(3888120000), // M2_cmacsc_s1
1766 UINT64_C(3841982496), // M2_cmpyi_s0
1767 UINT64_C(3841982528), // M2_cmpyr_s0
1768 UINT64_C(3978297536), // M2_cmpyrs_s0
1769 UINT64_C(3986686144), // M2_cmpyrs_s1
1770 UINT64_C(3982491840), // M2_cmpyrsc_s0
1771 UINT64_C(3990880448), // M2_cmpyrsc_s1
1772 UINT64_C(3841982656), // M2_cmpys_s0
1773 UINT64_C(3850371264), // M2_cmpys_s1
1774 UINT64_C(3846176960), // M2_cmpysc_s0
1775 UINT64_C(3854565568), // M2_cmpysc_s1
1776 UINT64_C(3875537120), // M2_cnacs_s0
1777 UINT64_C(3883925728), // M2_cnacs_s1
1778 UINT64_C(3879731424), // M2_cnacsc_s0
1779 UINT64_C(3888120032), // M2_cnacsc_s1
1780 UINT64_C(3875536896), // M2_dpmpyss_acc_s0
1781 UINT64_C(3877634048), // M2_dpmpyss_nac_s0
1782 UINT64_C(3978297376), // M2_dpmpyss_rnd_s0
1783 UINT64_C(3841982464), // M2_dpmpyss_s0
1784 UINT64_C(3879731200), // M2_dpmpyuu_acc_s0
1785 UINT64_C(3881828352), // M2_dpmpyuu_nac_s0
1786 UINT64_C(3846176768), // M2_dpmpyuu_s0
1787 UINT64_C(3986686080), // M2_hmmpyh_rs1
1788 UINT64_C(3986685952), // M2_hmmpyh_s1
1789 UINT64_C(3990880384), // M2_hmmpyl_rs1
1790 UINT64_C(3986685984), // M2_hmmpyl_s1
1791 UINT64_C(4009754624), // M2_maci
1792 UINT64_C(3783262208), // M2_macsin
1793 UINT64_C(3774873600), // M2_macsip
1794 UINT64_C(3927965920), // M2_mmachs_rs0
1795 UINT64_C(3936354528), // M2_mmachs_rs1
1796 UINT64_C(3925868768), // M2_mmachs_s0
1797 UINT64_C(3934257376), // M2_mmachs_s1
1798 UINT64_C(3927965856), // M2_mmacls_rs0
1799 UINT64_C(3936354464), // M2_mmacls_rs1
1800 UINT64_C(3925868704), // M2_mmacls_s0
1801 UINT64_C(3934257312), // M2_mmacls_s1
1802 UINT64_C(3932160224), // M2_mmacuhs_rs0
1803 UINT64_C(3940548832), // M2_mmacuhs_rs1
1804 UINT64_C(3930063072), // M2_mmacuhs_s0
1805 UINT64_C(3938451680), // M2_mmacuhs_s1
1806 UINT64_C(3932160160), // M2_mmaculs_rs0
1807 UINT64_C(3940548768), // M2_mmaculs_rs1
1808 UINT64_C(3930063008), // M2_mmaculs_s0
1809 UINT64_C(3938451616), // M2_mmaculs_s1
1810 UINT64_C(3894411488), // M2_mmpyh_rs0
1811 UINT64_C(3902800096), // M2_mmpyh_rs1
1812 UINT64_C(3892314336), // M2_mmpyh_s0
1813 UINT64_C(3900702944), // M2_mmpyh_s1
1814 UINT64_C(3894411424), // M2_mmpyl_rs0
1815 UINT64_C(3902800032), // M2_mmpyl_rs1
1816 UINT64_C(3892314272), // M2_mmpyl_s0
1817 UINT64_C(3900702880), // M2_mmpyl_s1
1818 UINT64_C(3898605792), // M2_mmpyuh_rs0
1819 UINT64_C(3906994400), // M2_mmpyuh_rs1
1820 UINT64_C(3896508640), // M2_mmpyuh_s0
1821 UINT64_C(3904897248), // M2_mmpyuh_s1
1822 UINT64_C(3898605728), // M2_mmpyul_rs0
1823 UINT64_C(3906994336), // M2_mmpyul_rs1
1824 UINT64_C(3896508576), // M2_mmpyul_s0
1825 UINT64_C(3904897184), // M2_mmpyul_s1
1826 UINT64_C(4018143232), // M2_mnaci
1827 UINT64_C(3992977504), // M2_mpy_acc_hh_s0
1828 UINT64_C(4001366112), // M2_mpy_acc_hh_s1
1829 UINT64_C(3992977472), // M2_mpy_acc_hl_s0
1830 UINT64_C(4001366080), // M2_mpy_acc_hl_s1
1831 UINT64_C(3992977440), // M2_mpy_acc_lh_s0
1832 UINT64_C(4001366048), // M2_mpy_acc_lh_s1
1833 UINT64_C(3992977408), // M2_mpy_acc_ll_s0
1834 UINT64_C(4001366016), // M2_mpy_acc_ll_s1
1835 UINT64_C(3992977632), // M2_mpy_acc_sat_hh_s0
1836 UINT64_C(4001366240), // M2_mpy_acc_sat_hh_s1
1837 UINT64_C(3992977600), // M2_mpy_acc_sat_hl_s0
1838 UINT64_C(4001366208), // M2_mpy_acc_sat_hl_s1
1839 UINT64_C(3992977568), // M2_mpy_acc_sat_lh_s0
1840 UINT64_C(4001366176), // M2_mpy_acc_sat_lh_s1
1841 UINT64_C(3992977536), // M2_mpy_acc_sat_ll_s0
1842 UINT64_C(4001366144), // M2_mpy_acc_sat_ll_s1
1843 UINT64_C(3959423072), // M2_mpy_hh_s0
1844 UINT64_C(3967811680), // M2_mpy_hh_s1
1845 UINT64_C(3959423040), // M2_mpy_hl_s0
1846 UINT64_C(3967811648), // M2_mpy_hl_s1
1847 UINT64_C(3959423008), // M2_mpy_lh_s0
1848 UINT64_C(3967811616), // M2_mpy_lh_s1
1849 UINT64_C(3959422976), // M2_mpy_ll_s0
1850 UINT64_C(3967811584), // M2_mpy_ll_s1
1851 UINT64_C(3995074656), // M2_mpy_nac_hh_s0
1852 UINT64_C(4003463264), // M2_mpy_nac_hh_s1
1853 UINT64_C(3995074624), // M2_mpy_nac_hl_s0
1854 UINT64_C(4003463232), // M2_mpy_nac_hl_s1
1855 UINT64_C(3995074592), // M2_mpy_nac_lh_s0
1856 UINT64_C(4003463200), // M2_mpy_nac_lh_s1
1857 UINT64_C(3995074560), // M2_mpy_nac_ll_s0
1858 UINT64_C(4003463168), // M2_mpy_nac_ll_s1
1859 UINT64_C(3995074784), // M2_mpy_nac_sat_hh_s0
1860 UINT64_C(4003463392), // M2_mpy_nac_sat_hh_s1
1861 UINT64_C(3995074752), // M2_mpy_nac_sat_hl_s0
1862 UINT64_C(4003463360), // M2_mpy_nac_sat_hl_s1
1863 UINT64_C(3995074720), // M2_mpy_nac_sat_lh_s0
1864 UINT64_C(4003463328), // M2_mpy_nac_sat_lh_s1
1865 UINT64_C(3995074688), // M2_mpy_nac_sat_ll_s0
1866 UINT64_C(4003463296), // M2_mpy_nac_sat_ll_s1
1867 UINT64_C(3961520224), // M2_mpy_rnd_hh_s0
1868 UINT64_C(3969908832), // M2_mpy_rnd_hh_s1
1869 UINT64_C(3961520192), // M2_mpy_rnd_hl_s0
1870 UINT64_C(3969908800), // M2_mpy_rnd_hl_s1
1871 UINT64_C(3961520160), // M2_mpy_rnd_lh_s0
1872 UINT64_C(3969908768), // M2_mpy_rnd_lh_s1
1873 UINT64_C(3961520128), // M2_mpy_rnd_ll_s0
1874 UINT64_C(3969908736), // M2_mpy_rnd_ll_s1
1875 UINT64_C(3959423200), // M2_mpy_sat_hh_s0
1876 UINT64_C(3967811808), // M2_mpy_sat_hh_s1
1877 UINT64_C(3959423168), // M2_mpy_sat_hl_s0
1878 UINT64_C(3967811776), // M2_mpy_sat_hl_s1
1879 UINT64_C(3959423136), // M2_mpy_sat_lh_s0
1880 UINT64_C(3967811744), // M2_mpy_sat_lh_s1
1881 UINT64_C(3959423104), // M2_mpy_sat_ll_s0
1882 UINT64_C(3967811712), // M2_mpy_sat_ll_s1
1883 UINT64_C(3961520352), // M2_mpy_sat_rnd_hh_s0
1884 UINT64_C(3969908960), // M2_mpy_sat_rnd_hh_s1
1885 UINT64_C(3961520320), // M2_mpy_sat_rnd_hl_s0
1886 UINT64_C(3969908928), // M2_mpy_sat_rnd_hl_s1
1887 UINT64_C(3961520288), // M2_mpy_sat_rnd_lh_s0
1888 UINT64_C(3969908896), // M2_mpy_sat_rnd_lh_s1
1889 UINT64_C(3961520256), // M2_mpy_sat_rnd_ll_s0
1890 UINT64_C(3969908864), // M2_mpy_sat_rnd_ll_s1
1891 UINT64_C(3976200224), // M2_mpy_up
1892 UINT64_C(3986686016), // M2_mpy_up_s1
1893 UINT64_C(3990880256), // M2_mpy_up_s1_sat
1894 UINT64_C(3858759776), // M2_mpyd_acc_hh_s0
1895 UINT64_C(3867148384), // M2_mpyd_acc_hh_s1
1896 UINT64_C(3858759744), // M2_mpyd_acc_hl_s0
1897 UINT64_C(3867148352), // M2_mpyd_acc_hl_s1
1898 UINT64_C(3858759712), // M2_mpyd_acc_lh_s0
1899 UINT64_C(3867148320), // M2_mpyd_acc_lh_s1
1900 UINT64_C(3858759680), // M2_mpyd_acc_ll_s0
1901 UINT64_C(3867148288), // M2_mpyd_acc_ll_s1
1902 UINT64_C(3825205344), // M2_mpyd_hh_s0
1903 UINT64_C(3833593952), // M2_mpyd_hh_s1
1904 UINT64_C(3825205312), // M2_mpyd_hl_s0
1905 UINT64_C(3833593920), // M2_mpyd_hl_s1
1906 UINT64_C(3825205280), // M2_mpyd_lh_s0
1907 UINT64_C(3833593888), // M2_mpyd_lh_s1
1908 UINT64_C(3825205248), // M2_mpyd_ll_s0
1909 UINT64_C(3833593856), // M2_mpyd_ll_s1
1910 UINT64_C(3860856928), // M2_mpyd_nac_hh_s0
1911 UINT64_C(3869245536), // M2_mpyd_nac_hh_s1
1912 UINT64_C(3860856896), // M2_mpyd_nac_hl_s0
1913 UINT64_C(3869245504), // M2_mpyd_nac_hl_s1
1914 UINT64_C(3860856864), // M2_mpyd_nac_lh_s0
1915 UINT64_C(3869245472), // M2_mpyd_nac_lh_s1
1916 UINT64_C(3860856832), // M2_mpyd_nac_ll_s0
1917 UINT64_C(3869245440), // M2_mpyd_nac_ll_s1
1918 UINT64_C(3827302496), // M2_mpyd_rnd_hh_s0
1919 UINT64_C(3835691104), // M2_mpyd_rnd_hh_s1
1920 UINT64_C(3827302464), // M2_mpyd_rnd_hl_s0
1921 UINT64_C(3835691072), // M2_mpyd_rnd_hl_s1
1922 UINT64_C(3827302432), // M2_mpyd_rnd_lh_s0
1923 UINT64_C(3835691040), // M2_mpyd_rnd_lh_s1
1924 UINT64_C(3827302400), // M2_mpyd_rnd_ll_s0
1925 UINT64_C(3835691008), // M2_mpyd_rnd_ll_s1
1926 UINT64_C(3976200192), // M2_mpyi
1927 UINT64_C(3766484992), // M2_mpysin
1928 UINT64_C(3758096384), // M2_mpysip
1929 UINT64_C(3982491680), // M2_mpysu_up
1930 UINT64_C(3997171808), // M2_mpyu_acc_hh_s0
1931 UINT64_C(4005560416), // M2_mpyu_acc_hh_s1
1932 UINT64_C(3997171776), // M2_mpyu_acc_hl_s0
1933 UINT64_C(4005560384), // M2_mpyu_acc_hl_s1
1934 UINT64_C(3997171744), // M2_mpyu_acc_lh_s0
1935 UINT64_C(4005560352), // M2_mpyu_acc_lh_s1
1936 UINT64_C(3997171712), // M2_mpyu_acc_ll_s0
1937 UINT64_C(4005560320), // M2_mpyu_acc_ll_s1
1938 UINT64_C(3963617376), // M2_mpyu_hh_s0
1939 UINT64_C(3972005984), // M2_mpyu_hh_s1
1940 UINT64_C(3963617344), // M2_mpyu_hl_s0
1941 UINT64_C(3972005952), // M2_mpyu_hl_s1
1942 UINT64_C(3963617312), // M2_mpyu_lh_s0
1943 UINT64_C(3972005920), // M2_mpyu_lh_s1
1944 UINT64_C(3963617280), // M2_mpyu_ll_s0
1945 UINT64_C(3972005888), // M2_mpyu_ll_s1
1946 UINT64_C(3999268960), // M2_mpyu_nac_hh_s0
1947 UINT64_C(4007657568), // M2_mpyu_nac_hh_s1
1948 UINT64_C(3999268928), // M2_mpyu_nac_hl_s0
1949 UINT64_C(4007657536), // M2_mpyu_nac_hl_s1
1950 UINT64_C(3999268896), // M2_mpyu_nac_lh_s0
1951 UINT64_C(4007657504), // M2_mpyu_nac_lh_s1
1952 UINT64_C(3999268864), // M2_mpyu_nac_ll_s0
1953 UINT64_C(4007657472), // M2_mpyu_nac_ll_s1
1954 UINT64_C(3980394528), // M2_mpyu_up
1955 UINT64_C(3862954080), // M2_mpyud_acc_hh_s0
1956 UINT64_C(3871342688), // M2_mpyud_acc_hh_s1
1957 UINT64_C(3862954048), // M2_mpyud_acc_hl_s0
1958 UINT64_C(3871342656), // M2_mpyud_acc_hl_s1
1959 UINT64_C(3862954016), // M2_mpyud_acc_lh_s0
1960 UINT64_C(3871342624), // M2_mpyud_acc_lh_s1
1961 UINT64_C(3862953984), // M2_mpyud_acc_ll_s0
1962 UINT64_C(3871342592), // M2_mpyud_acc_ll_s1
1963 UINT64_C(3829399648), // M2_mpyud_hh_s0
1964 UINT64_C(3837788256), // M2_mpyud_hh_s1
1965 UINT64_C(3829399616), // M2_mpyud_hl_s0
1966 UINT64_C(3837788224), // M2_mpyud_hl_s1
1967 UINT64_C(3829399584), // M2_mpyud_lh_s0
1968 UINT64_C(3837788192), // M2_mpyud_lh_s1
1969 UINT64_C(3829399552), // M2_mpyud_ll_s0
1970 UINT64_C(3837788160), // M2_mpyud_ll_s1
1971 UINT64_C(3865051232), // M2_mpyud_nac_hh_s0
1972 UINT64_C(3873439840), // M2_mpyud_nac_hh_s1
1973 UINT64_C(3865051200), // M2_mpyud_nac_hl_s0
1974 UINT64_C(3873439808), // M2_mpyud_nac_hl_s1
1975 UINT64_C(3865051168), // M2_mpyud_nac_lh_s0
1976 UINT64_C(3873439776), // M2_mpyud_nac_lh_s1
1977 UINT64_C(3865051136), // M2_mpyud_nac_ll_s0
1978 UINT64_C(3873439744), // M2_mpyud_nac_ll_s1
1979 UINT64_C(4018143264), // M2_nacci
1980 UINT64_C(3800039424), // M2_naccii
1981 UINT64_C(4009754720), // M2_subacc
1982 UINT64_C(3898605568), // M2_vabsdiffh
1983 UINT64_C(3894411264), // M2_vabsdiffw
1984 UINT64_C(3930062976), // M2_vcmac_s0_sat_i
1985 UINT64_C(3927965824), // M2_vcmac_s0_sat_r
1986 UINT64_C(3896508608), // M2_vcmpy_s0_sat_i
1987 UINT64_C(3894411456), // M2_vcmpy_s0_sat_r
1988 UINT64_C(3904897216), // M2_vcmpy_s1_sat_i
1989 UINT64_C(3902800064), // M2_vcmpy_s1_sat_r
1990 UINT64_C(3925868672), // M2_vdmacs_s0
1991 UINT64_C(3934257280), // M2_vdmacs_s1
1992 UINT64_C(3909091328), // M2_vdmpyrs_s0
1993 UINT64_C(3917479936), // M2_vdmpyrs_s1
1994 UINT64_C(3892314240), // M2_vdmpys_s0
1995 UINT64_C(3900702848), // M2_vdmpys_s1
1996 UINT64_C(3877634080), // M2_vmac2
1997 UINT64_C(3927965760), // M2_vmac2es
1998 UINT64_C(3925868736), // M2_vmac2es_s0
1999 UINT64_C(3934257344), // M2_vmac2es_s1
2000 UINT64_C(3875537056), // M2_vmac2s_s0
2001 UINT64_C(3883925664), // M2_vmac2s_s1
2002 UINT64_C(3881828512), // M2_vmac2su_s0
2003 UINT64_C(3890217120), // M2_vmac2su_s1
2004 UINT64_C(3892314304), // M2_vmpy2es_s0
2005 UINT64_C(3900702912), // M2_vmpy2es_s1
2006 UINT64_C(3841982624), // M2_vmpy2s_s0
2007 UINT64_C(3978297568), // M2_vmpy2s_s0pack
2008 UINT64_C(3850371232), // M2_vmpy2s_s1
2009 UINT64_C(3986686176), // M2_vmpy2s_s1pack
2010 UINT64_C(3841982688), // M2_vmpy2su_s0
2011 UINT64_C(3850371296), // M2_vmpy2su_s1
2012 UINT64_C(3911188704), // M2_vraddh
2013 UINT64_C(3909091360), // M2_vradduh
2014 UINT64_C(3925868544), // M2_vrcmaci_s0
2015 UINT64_C(3930062848), // M2_vrcmaci_s0c
2016 UINT64_C(3925868576), // M2_vrcmacr_s0
2017 UINT64_C(3932160032), // M2_vrcmacr_s0c
2018 UINT64_C(3892314112), // M2_vrcmpyi_s0
2019 UINT64_C(3896508416), // M2_vrcmpyi_s0c
2020 UINT64_C(3892314144), // M2_vrcmpyr_s0
2021 UINT64_C(3898605600), // M2_vrcmpyr_s0c
2022 UINT64_C(3936354432), // M2_vrcmpys_acc_s1_h
2023 UINT64_C(3940548736), // M2_vrcmpys_acc_s1_l
2024 UINT64_C(3902800000), // M2_vrcmpys_s1_h
2025 UINT64_C(3906994304), // M2_vrcmpys_s1_l
2026 UINT64_C(3919577280), // M2_vrcmpys_s1rp_h
2027 UINT64_C(3919577312), // M2_vrcmpys_s1rp_l
2028 UINT64_C(3925868608), // M2_vrmac_s0
2029 UINT64_C(3892314176), // M2_vrmpy_s0
2030 UINT64_C(4018143328), // M2_xor_xacc
2031 UINT64_C(4013948928), // M4_and_and
2032 UINT64_C(4011851808), // M4_and_andn
2033 UINT64_C(4013948960), // M4_and_or
2034 UINT64_C(4013948992), // M4_and_xor
2035 UINT64_C(3305111680), // M4_cmpyi_wh
2036 UINT64_C(3305111712), // M4_cmpyi_whc
2037 UINT64_C(3305111744), // M4_cmpyr_wh
2038 UINT64_C(3305111776), // M4_cmpyr_whc
2039 UINT64_C(4016046080), // M4_mac_up_s1_sat
2040 UINT64_C(3623878656), // M4_mpyri_addi
2041 UINT64_C(3749707776), // M4_mpyri_addr
2042 UINT64_C(3741319168), // M4_mpyri_addr_u2
2043 UINT64_C(3607101440), // M4_mpyrr_addi
2044 UINT64_C(3808428032), // M4_mpyrr_addr
2045 UINT64_C(4016046112), // M4_nac_up_s1_sat
2046 UINT64_C(4013949024), // M4_or_and
2047 UINT64_C(4011851776), // M4_or_andn
2048 UINT64_C(4022337536), // M4_or_or
2049 UINT64_C(4022337568), // M4_or_xor
2050 UINT64_C(3846176992), // M4_pmpyw
2051 UINT64_C(3877634272), // M4_pmpyw_acc
2052 UINT64_C(3854565600), // M4_vpmpyh
2053 UINT64_C(3886022880), // M4_vpmpyh_acc
2054 UINT64_C(3927965888), // M4_vrmpyeh_acc_s0
2055 UINT64_C(3936354496), // M4_vrmpyeh_acc_s1
2056 UINT64_C(3896508544), // M4_vrmpyeh_s0
2057 UINT64_C(3904897152), // M4_vrmpyeh_s1
2058 UINT64_C(3932160192), // M4_vrmpyoh_acc_s0
2059 UINT64_C(3940548800), // M4_vrmpyoh_acc_s1
2060 UINT64_C(3894411328), // M4_vrmpyoh_s0
2061 UINT64_C(3902799936), // M4_vrmpyoh_s1
2062 UINT64_C(4022337600), // M4_xor_and
2063 UINT64_C(4011851840), // M4_xor_andn
2064 UINT64_C(4022337632), // M4_xor_or
2065 UINT64_C(3397386240), // M4_xor_xacc
2066 UINT64_C(3927965728), // M5_vdmacbsu
2067 UINT64_C(3902799904), // M5_vdmpybsu
2068 UINT64_C(3888119840), // M5_vmacbsu
2069 UINT64_C(3883925536), // M5_vmacbuu
2070 UINT64_C(3846176800), // M5_vmpybsu
2071 UINT64_C(3850371104), // M5_vmpybuu
2072 UINT64_C(3938451488), // M5_vrmacbsu
2073 UINT64_C(3934257184), // M5_vrmacbuu
2074 UINT64_C(3904897056), // M5_vrmpybsu
2075 UINT64_C(3900702752), // M5_vrmpybuu
2076 UINT64_C(3906994176), // M6_vabsdiffb
2077 UINT64_C(3902799872), // M6_vabsdiffub
2078 UINT64_C(3898605632), // M7_dcmpyiw
2079 UINT64_C(3932160064), // M7_dcmpyiw_acc
2080 UINT64_C(3906994240), // M7_dcmpyiwc
2081 UINT64_C(3930063040), // M7_dcmpyiwc_acc
2082 UINT64_C(3900702784), // M7_dcmpyrw
2083 UINT64_C(3934257216), // M7_dcmpyrw_acc
2084 UINT64_C(3904897088), // M7_dcmpyrwc
2085 UINT64_C(3938451520), // M7_dcmpyrwc_acc
2086 UINT64_C(3911188480), // M7_wcmpyiw
2087 UINT64_C(3919577088), // M7_wcmpyiw_rnd
2088 UINT64_C(3909091456), // M7_wcmpyiwc
2089 UINT64_C(3917480064), // M7_wcmpyiwc_rnd
2090 UINT64_C(3913285632), // M7_wcmpyrw
2091 UINT64_C(3921674240), // M7_wcmpyrw_rnd
2092 UINT64_C(3915382784), // M7_wcmpyrwc
2093 UINT64_C(3923771392), // M7_wcmpyrwc_rnd
2094 UINT64_C(1509949440), // PS_call_stk
2095 UINT64_C(1352663040), // PS_callr_nr
2096 UINT64_C(1384120320), // PS_jmpret
2097 UINT64_C(1398800384), // PS_jmpretf
2098 UINT64_C(1398802432), // PS_jmpretfnew
2099 UINT64_C(1398806528), // PS_jmpretfnewpt
2100 UINT64_C(1396703232), // PS_jmprett
2101 UINT64_C(1396705280), // PS_jmprettnew
2102 UINT64_C(1396709376), // PS_jmprettnewpt
2103 UINT64_C(1224736768), // PS_loadrbabs
2104 UINT64_C(1237319680), // PS_loadrdabs
2105 UINT64_C(1228931072), // PS_loadrhabs
2106 UINT64_C(1233125376), // PS_loadriabs
2107 UINT64_C(1226833920), // PS_loadrubabs
2108 UINT64_C(1231028224), // PS_loadruhabs
2109 UINT64_C(1207959552), // PS_storerbabs
2110 UINT64_C(1218445312), // PS_storerbnewabs
2111 UINT64_C(1220542464), // PS_storerdabs
2112 UINT64_C(1214251008), // PS_storerfabs
2113 UINT64_C(1212153856), // PS_storerhabs
2114 UINT64_C(1218447360), // PS_storerhnewabs
2115 UINT64_C(1216348160), // PS_storeriabs
2116 UINT64_C(1218449408), // PS_storerinewabs
2117 UINT64_C(1417674752), // PS_trap1
2118 UINT64_C(2699034636), // R6_release_at_vi
2119 UINT64_C(2699034668), // R6_release_st_vi
2120 UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4
2121 UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT
2122 UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
2123 UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
2124 UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4
2125 UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_EXT
2126 UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
2127 UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_PIC
2128 UINT64_C(3288334336), // S2_addasl_rrri
2129 UINT64_C(2692743168), // S2_allocframe
2130 UINT64_C(2147483712), // S2_asl_i_p
2131 UINT64_C(2181038272), // S2_asl_i_p_acc
2132 UINT64_C(2185232448), // S2_asl_i_p_and
2133 UINT64_C(2181038144), // S2_asl_i_p_nac
2134 UINT64_C(2185232576), // S2_asl_i_p_or
2135 UINT64_C(2189426752), // S2_asl_i_p_xacc
2136 UINT64_C(2348810304), // S2_asl_i_r
2137 UINT64_C(2382364864), // S2_asl_i_r_acc
2138 UINT64_C(2386559040), // S2_asl_i_r_and
2139 UINT64_C(2382364736), // S2_asl_i_r_nac
2140 UINT64_C(2386559168), // S2_asl_i_r_or
2141 UINT64_C(2353004608), // S2_asl_i_r_sat
2142 UINT64_C(2390753344), // S2_asl_i_r_xacc
2143 UINT64_C(2155872320), // S2_asl_i_vh
2144 UINT64_C(2151678016), // S2_asl_i_vw
2145 UINT64_C(3279945856), // S2_asl_r_p
2146 UINT64_C(3418357888), // S2_asl_r_p_acc
2147 UINT64_C(3409969280), // S2_asl_r_p_and
2148 UINT64_C(3414163584), // S2_asl_r_p_nac
2149 UINT64_C(3405774976), // S2_asl_r_p_or
2150 UINT64_C(3412066432), // S2_asl_r_p_xor
2151 UINT64_C(3326083200), // S2_asl_r_r
2152 UINT64_C(3435135104), // S2_asl_r_r_acc
2153 UINT64_C(3426746496), // S2_asl_r_r_and
2154 UINT64_C(3430940800), // S2_asl_r_r_nac
2155 UINT64_C(3422552192), // S2_asl_r_r_or
2156 UINT64_C(3321888896), // S2_asl_r_r_sat
2157 UINT64_C(3275751552), // S2_asl_r_vh
2158 UINT64_C(3271557248), // S2_asl_r_vw
2159 UINT64_C(2147483648), // S2_asr_i_p
2160 UINT64_C(2181038208), // S2_asr_i_p_acc
2161 UINT64_C(2185232384), // S2_asr_i_p_and
2162 UINT64_C(2181038080), // S2_asr_i_p_nac
2163 UINT64_C(2185232512), // S2_asr_i_p_or
2164 UINT64_C(2160066784), // S2_asr_i_p_rnd
2165 UINT64_C(2348810240), // S2_asr_i_r
2166 UINT64_C(2382364800), // S2_asr_i_r_acc
2167 UINT64_C(2386558976), // S2_asr_i_r_and
2168 UINT64_C(2382364672), // S2_asr_i_r_nac
2169 UINT64_C(2386559104), // S2_asr_i_r_or
2170 UINT64_C(2353004544), // S2_asr_i_r_rnd
2171 UINT64_C(2294284352), // S2_asr_i_svw_trun
2172 UINT64_C(2155872256), // S2_asr_i_vh
2173 UINT64_C(2151677952), // S2_asr_i_vw
2174 UINT64_C(3279945728), // S2_asr_r_p
2175 UINT64_C(3418357760), // S2_asr_r_p_acc
2176 UINT64_C(3409969152), // S2_asr_r_p_and
2177 UINT64_C(3414163456), // S2_asr_r_p_nac
2178 UINT64_C(3405774848), // S2_asr_r_p_or
2179 UINT64_C(3412066304), // S2_asr_r_p_xor
2180 UINT64_C(3326083072), // S2_asr_r_r
2181 UINT64_C(3435134976), // S2_asr_r_r_acc
2182 UINT64_C(3426746368), // S2_asr_r_r_and
2183 UINT64_C(3430940672), // S2_asr_r_r_nac
2184 UINT64_C(3422552064), // S2_asr_r_r_or
2185 UINT64_C(3321888768), // S2_asr_r_r_sat
2186 UINT64_C(3305111616), // S2_asr_r_svw_trun
2187 UINT64_C(3275751424), // S2_asr_r_vh
2188 UINT64_C(3271557120), // S2_asr_r_vw
2189 UINT64_C(2353004736), // S2_brev
2190 UINT64_C(2160066752), // S2_brevp
2191 UINT64_C(3250585792), // S2_cabacdecbin
2192 UINT64_C(2348810400), // S2_cl0
2193 UINT64_C(2285895744), // S2_cl0p
2194 UINT64_C(2348810432), // S2_cl1
2195 UINT64_C(2285895808), // S2_cl1p
2196 UINT64_C(2348810368), // S2_clb
2197 UINT64_C(2348810464), // S2_clbnorm
2198 UINT64_C(2285895680), // S2_clbp
2199 UINT64_C(2361393184), // S2_clrbit_i
2200 UINT64_C(3330277440), // S2_clrbit_r
2201 UINT64_C(2353004672), // S2_ct0
2202 UINT64_C(2296381504), // S2_ct0p
2203 UINT64_C(2353004704), // S2_ct1
2204 UINT64_C(2296381568), // S2_ct1p
2205 UINT64_C(2160066688), // S2_deinterleave
2206 UINT64_C(2365587456), // S2_extractu
2207 UINT64_C(3372220416), // S2_extractu_rp
2208 UINT64_C(2164260864), // S2_extractup
2209 UINT64_C(3238002688), // S2_extractup_rp
2210 UINT64_C(2399141888), // S2_insert
2211 UINT64_C(3355443200), // S2_insert_rp
2212 UINT64_C(2197815296), // S2_insertp
2213 UINT64_C(3388997632), // S2_insertp_rp
2214 UINT64_C(2160066720), // S2_interleave
2215 UINT64_C(3246391488), // S2_lfsp
2216 UINT64_C(3279945920), // S2_lsl_r_p
2217 UINT64_C(3418357952), // S2_lsl_r_p_acc
2218 UINT64_C(3409969344), // S2_lsl_r_p_and
2219 UINT64_C(3414163648), // S2_lsl_r_p_nac
2220 UINT64_C(3405775040), // S2_lsl_r_p_or
2221 UINT64_C(3412066496), // S2_lsl_r_p_xor
2222 UINT64_C(3326083264), // S2_lsl_r_r
2223 UINT64_C(3435135168), // S2_lsl_r_r_acc
2224 UINT64_C(3426746560), // S2_lsl_r_r_and
2225 UINT64_C(3430940864), // S2_lsl_r_r_nac
2226 UINT64_C(3422552256), // S2_lsl_r_r_or
2227 UINT64_C(3275751616), // S2_lsl_r_vh
2228 UINT64_C(3271557312), // S2_lsl_r_vw
2229 UINT64_C(2147483680), // S2_lsr_i_p
2230 UINT64_C(2181038240), // S2_lsr_i_p_acc
2231 UINT64_C(2185232416), // S2_lsr_i_p_and
2232 UINT64_C(2181038112), // S2_lsr_i_p_nac
2233 UINT64_C(2185232544), // S2_lsr_i_p_or
2234 UINT64_C(2189426720), // S2_lsr_i_p_xacc
2235 UINT64_C(2348810272), // S2_lsr_i_r
2236 UINT64_C(2382364832), // S2_lsr_i_r_acc
2237 UINT64_C(2386559008), // S2_lsr_i_r_and
2238 UINT64_C(2382364704), // S2_lsr_i_r_nac
2239 UINT64_C(2386559136), // S2_lsr_i_r_or
2240 UINT64_C(2390753312), // S2_lsr_i_r_xacc
2241 UINT64_C(2155872288), // S2_lsr_i_vh
2242 UINT64_C(2151677984), // S2_lsr_i_vw
2243 UINT64_C(3279945792), // S2_lsr_r_p
2244 UINT64_C(3418357824), // S2_lsr_r_p_acc
2245 UINT64_C(3409969216), // S2_lsr_r_p_and
2246 UINT64_C(3414163520), // S2_lsr_r_p_nac
2247 UINT64_C(3405774912), // S2_lsr_r_p_or
2248 UINT64_C(3412066368), // S2_lsr_r_p_xor
2249 UINT64_C(3326083136), // S2_lsr_r_r
2250 UINT64_C(3435135040), // S2_lsr_r_r_acc
2251 UINT64_C(3426746432), // S2_lsr_r_r_and
2252 UINT64_C(3430940736), // S2_lsr_r_r_nac
2253 UINT64_C(3422552128), // S2_lsr_r_r_or
2254 UINT64_C(3275751488), // S2_lsr_r_vh
2255 UINT64_C(3271557184), // S2_lsr_r_vw
2256 UINT64_C(2365595648), // S2_mask
2257 UINT64_C(4118806528), // S2_packhl
2258 UINT64_C(3489660928), // S2_parityp
2259 UINT64_C(1140850688), // S2_pstorerbf_io
2260 UINT64_C(2868912132), // S2_pstorerbf_pi
2261 UINT64_C(2868912260), // S2_pstorerbfnew_pi
2262 UINT64_C(1151336448), // S2_pstorerbnewf_io
2263 UINT64_C(2879397892), // S2_pstorerbnewf_pi
2264 UINT64_C(2879398020), // S2_pstorerbnewfnew_pi
2265 UINT64_C(1084227584), // S2_pstorerbnewt_io
2266 UINT64_C(2879397888), // S2_pstorerbnewt_pi
2267 UINT64_C(2879398016), // S2_pstorerbnewtnew_pi
2268 UINT64_C(1073741824), // S2_pstorerbt_io
2269 UINT64_C(2868912128), // S2_pstorerbt_pi
2270 UINT64_C(2868912256), // S2_pstorerbtnew_pi
2271 UINT64_C(1153433600), // S2_pstorerdf_io
2272 UINT64_C(2881495044), // S2_pstorerdf_pi
2273 UINT64_C(2881495172), // S2_pstorerdfnew_pi
2274 UINT64_C(1086324736), // S2_pstorerdt_io
2275 UINT64_C(2881495040), // S2_pstorerdt_pi
2276 UINT64_C(2881495168), // S2_pstorerdtnew_pi
2277 UINT64_C(1147142144), // S2_pstorerff_io
2278 UINT64_C(2875203588), // S2_pstorerff_pi
2279 UINT64_C(2875203716), // S2_pstorerffnew_pi
2280 UINT64_C(1080033280), // S2_pstorerft_io
2281 UINT64_C(2875203584), // S2_pstorerft_pi
2282 UINT64_C(2875203712), // S2_pstorerftnew_pi
2283 UINT64_C(1145044992), // S2_pstorerhf_io
2284 UINT64_C(2873106436), // S2_pstorerhf_pi
2285 UINT64_C(2873106564), // S2_pstorerhfnew_pi
2286 UINT64_C(1151338496), // S2_pstorerhnewf_io
2287 UINT64_C(2879399940), // S2_pstorerhnewf_pi
2288 UINT64_C(2879400068), // S2_pstorerhnewfnew_pi
2289 UINT64_C(1084229632), // S2_pstorerhnewt_io
2290 UINT64_C(2879399936), // S2_pstorerhnewt_pi
2291 UINT64_C(2879400064), // S2_pstorerhnewtnew_pi
2292 UINT64_C(1077936128), // S2_pstorerht_io
2293 UINT64_C(2873106432), // S2_pstorerht_pi
2294 UINT64_C(2873106560), // S2_pstorerhtnew_pi
2295 UINT64_C(1149239296), // S2_pstorerif_io
2296 UINT64_C(2877300740), // S2_pstorerif_pi
2297 UINT64_C(2877300868), // S2_pstorerifnew_pi
2298 UINT64_C(1151340544), // S2_pstorerinewf_io
2299 UINT64_C(2879401988), // S2_pstorerinewf_pi
2300 UINT64_C(2879402116), // S2_pstorerinewfnew_pi
2301 UINT64_C(1084231680), // S2_pstorerinewt_io
2302 UINT64_C(2879401984), // S2_pstorerinewt_pi
2303 UINT64_C(2879402112), // S2_pstorerinewtnew_pi
2304 UINT64_C(1082130432), // S2_pstorerit_io
2305 UINT64_C(2877300736), // S2_pstorerit_pi
2306 UINT64_C(2877300864), // S2_pstoreritnew_pi
2307 UINT64_C(2361393152), // S2_setbit_i
2308 UINT64_C(3330277376), // S2_setbit_r
2309 UINT64_C(3238002752), // S2_shuffeb
2310 UINT64_C(3238002880), // S2_shuffeh
2311 UINT64_C(3238002816), // S2_shuffob
2312 UINT64_C(3246391296), // S2_shuffoh
2313 UINT64_C(2701131776), // S2_storerb_io
2314 UINT64_C(2936012800), // S2_storerb_pbr
2315 UINT64_C(2835349504), // S2_storerb_pci
2316 UINT64_C(2835349506), // S2_storerb_pcr
2317 UINT64_C(2868903936), // S2_storerb_pi
2318 UINT64_C(2902458368), // S2_storerb_pr
2319 UINT64_C(1207959552), // S2_storerbgp
2320 UINT64_C(2711617536), // S2_storerbnew_io
2321 UINT64_C(2946498560), // S2_storerbnew_pbr
2322 UINT64_C(2845835264), // S2_storerbnew_pci
2323 UINT64_C(2845835266), // S2_storerbnew_pcr
2324 UINT64_C(2879389696), // S2_storerbnew_pi
2325 UINT64_C(2912944128), // S2_storerbnew_pr
2326 UINT64_C(1218445312), // S2_storerbnewgp
2327 UINT64_C(2713714688), // S2_storerd_io
2328 UINT64_C(2948595712), // S2_storerd_pbr
2329 UINT64_C(2847932416), // S2_storerd_pci
2330 UINT64_C(2847932418), // S2_storerd_pcr
2331 UINT64_C(2881486848), // S2_storerd_pi
2332 UINT64_C(2915041280), // S2_storerd_pr
2333 UINT64_C(1220542464), // S2_storerdgp
2334 UINT64_C(2707423232), // S2_storerf_io
2335 UINT64_C(2942304256), // S2_storerf_pbr
2336 UINT64_C(2841640960), // S2_storerf_pci
2337 UINT64_C(2841640962), // S2_storerf_pcr
2338 UINT64_C(2875195392), // S2_storerf_pi
2339 UINT64_C(2908749824), // S2_storerf_pr
2340 UINT64_C(1214251008), // S2_storerfgp
2341 UINT64_C(2705326080), // S2_storerh_io
2342 UINT64_C(2940207104), // S2_storerh_pbr
2343 UINT64_C(2839543808), // S2_storerh_pci
2344 UINT64_C(2839543810), // S2_storerh_pcr
2345 UINT64_C(2873098240), // S2_storerh_pi
2346 UINT64_C(2906652672), // S2_storerh_pr
2347 UINT64_C(1212153856), // S2_storerhgp
2348 UINT64_C(2711619584), // S2_storerhnew_io
2349 UINT64_C(2946500608), // S2_storerhnew_pbr
2350 UINT64_C(2845837312), // S2_storerhnew_pci
2351 UINT64_C(2845837314), // S2_storerhnew_pcr
2352 UINT64_C(2879391744), // S2_storerhnew_pi
2353 UINT64_C(2912946176), // S2_storerhnew_pr
2354 UINT64_C(1218447360), // S2_storerhnewgp
2355 UINT64_C(2709520384), // S2_storeri_io
2356 UINT64_C(2944401408), // S2_storeri_pbr
2357 UINT64_C(2843738112), // S2_storeri_pci
2358 UINT64_C(2843738114), // S2_storeri_pcr
2359 UINT64_C(2877292544), // S2_storeri_pi
2360 UINT64_C(2910846976), // S2_storeri_pr
2361 UINT64_C(1216348160), // S2_storerigp
2362 UINT64_C(2711621632), // S2_storerinew_io
2363 UINT64_C(2946502656), // S2_storerinew_pbr
2364 UINT64_C(2845839360), // S2_storerinew_pci
2365 UINT64_C(2845839362), // S2_storerinew_pcr
2366 UINT64_C(2879393792), // S2_storerinew_pi
2367 UINT64_C(2912948224), // S2_storerinew_pr
2368 UINT64_C(1218449408), // S2_storerinewgp
2369 UINT64_C(2694840320), // S2_storew_locked
2370 UINT64_C(2694840328), // S2_storew_rl_at_vi
2371 UINT64_C(2694840360), // S2_storew_rl_st_vi
2372 UINT64_C(2357198848), // S2_svsathb
2373 UINT64_C(2357198912), // S2_svsathub
2374 UINT64_C(2264924160), // S2_tableidxb
2375 UINT64_C(2277507072), // S2_tableidxd
2376 UINT64_C(2269118464), // S2_tableidxh
2377 UINT64_C(2273312768), // S2_tableidxw
2378 UINT64_C(2361393216), // S2_togglebit_i
2379 UINT64_C(3330277504), // S2_togglebit_r
2380 UINT64_C(2231369728), // S2_tstbit_i
2381 UINT64_C(3338665984), // S2_tstbit_r
2382 UINT64_C(3221225472), // S2_valignib
2383 UINT64_C(3254779904), // S2_valignrb
2384 UINT64_C(3284140096), // S2_vcnegh
2385 UINT64_C(3284140032), // S2_vcrotate
2386 UINT64_C(3407880416), // S2_vrcnegh
2387 UINT64_C(2290090112), // S2_vrndpackwh
2388 UINT64_C(2290090176), // S2_vrndpackwhs
2389 UINT64_C(2281701568), // S2_vsathb
2390 UINT64_C(2147483872), // S2_vsathb_nopack
2391 UINT64_C(2281701376), // S2_vsathub
2392 UINT64_C(2147483776), // S2_vsathub_nopack
2393 UINT64_C(2281701440), // S2_vsatwh
2394 UINT64_C(2147483840), // S2_vsatwh_nopack
2395 UINT64_C(2281701504), // S2_vsatwuh
2396 UINT64_C(2147483808), // S2_vsatwuh_nopack
2397 UINT64_C(2353004768), // S2_vsplatrb
2398 UINT64_C(2218786880), // S2_vsplatrh
2399 UINT64_C(3229614080), // S2_vspliceib
2400 UINT64_C(3263168512), // S2_vsplicerb
2401 UINT64_C(2214592512), // S2_vsxtbh
2402 UINT64_C(2214592640), // S2_vsxthw
2403 UINT64_C(2290090048), // S2_vtrunehb
2404 UINT64_C(3246391360), // S2_vtrunewh
2405 UINT64_C(2290089984), // S2_vtrunohb
2406 UINT64_C(3246391424), // S2_vtrunowh
2407 UINT64_C(2214592576), // S2_vzxtbh
2408 UINT64_C(2214592704), // S2_vzxthw
2409 UINT64_C(3674210304), // S4_addaddi
2410 UINT64_C(3724541956), // S4_addi_asl_ri
2411 UINT64_C(3724541972), // S4_addi_lsr_ri
2412 UINT64_C(3724541952), // S4_andi_asl_ri
2413 UINT64_C(3724541968), // S4_andi_lsr_ri
2414 UINT64_C(2350907392), // S4_clbaddi
2415 UINT64_C(2287992896), // S4_clbpaddi
2416 UINT64_C(2287992832), // S4_clbpnorm
2417 UINT64_C(2373976064), // S4_extract
2418 UINT64_C(3372220480), // S4_extract_rp
2419 UINT64_C(2315255808), // S4_extractp
2420 UINT64_C(3250585728), // S4_extractp_rp
2421 UINT64_C(3330277568), // S4_lsli
2422 UINT64_C(2233466880), // S4_ntstbit_i
2423 UINT64_C(3340763136), // S4_ntstbit_r
2424 UINT64_C(3657433088), // S4_or_andi
2425 UINT64_C(3661627392), // S4_or_andix
2426 UINT64_C(3665821696), // S4_or_ori
2427 UINT64_C(3724541954), // S4_ori_asl_ri
2428 UINT64_C(3724541970), // S4_ori_lsr_ri
2429 UINT64_C(3588227072), // S4_parity
2430 UINT64_C(2936012932), // S4_pstorerbf_abs
2431 UINT64_C(889192448), // S4_pstorerbf_rr
2432 UINT64_C(2936021124), // S4_pstorerbfnew_abs
2433 UINT64_C(1174405120), // S4_pstorerbfnew_io
2434 UINT64_C(922746880), // S4_pstorerbfnew_rr
2435 UINT64_C(2946498692), // S4_pstorerbnewf_abs
2436 UINT64_C(899678208), // S4_pstorerbnewf_rr
2437 UINT64_C(2946506884), // S4_pstorerbnewfnew_abs
2438 UINT64_C(1184890880), // S4_pstorerbnewfnew_io
2439 UINT64_C(933232640), // S4_pstorerbnewfnew_rr
2440 UINT64_C(2946498688), // S4_pstorerbnewt_abs
2441 UINT64_C(882900992), // S4_pstorerbnewt_rr
2442 UINT64_C(2946506880), // S4_pstorerbnewtnew_abs
2443 UINT64_C(1117782016), // S4_pstorerbnewtnew_io
2444 UINT64_C(916455424), // S4_pstorerbnewtnew_rr
2445 UINT64_C(2936012928), // S4_pstorerbt_abs
2446 UINT64_C(872415232), // S4_pstorerbt_rr
2447 UINT64_C(2936021120), // S4_pstorerbtnew_abs
2448 UINT64_C(1107296256), // S4_pstorerbtnew_io
2449 UINT64_C(905969664), // S4_pstorerbtnew_rr
2450 UINT64_C(2948595844), // S4_pstorerdf_abs
2451 UINT64_C(901775360), // S4_pstorerdf_rr
2452 UINT64_C(2948604036), // S4_pstorerdfnew_abs
2453 UINT64_C(1186988032), // S4_pstorerdfnew_io
2454 UINT64_C(935329792), // S4_pstorerdfnew_rr
2455 UINT64_C(2948595840), // S4_pstorerdt_abs
2456 UINT64_C(884998144), // S4_pstorerdt_rr
2457 UINT64_C(2948604032), // S4_pstorerdtnew_abs
2458 UINT64_C(1119879168), // S4_pstorerdtnew_io
2459 UINT64_C(918552576), // S4_pstorerdtnew_rr
2460 UINT64_C(2942304388), // S4_pstorerff_abs
2461 UINT64_C(895483904), // S4_pstorerff_rr
2462 UINT64_C(2942312580), // S4_pstorerffnew_abs
2463 UINT64_C(1180696576), // S4_pstorerffnew_io
2464 UINT64_C(929038336), // S4_pstorerffnew_rr
2465 UINT64_C(2942304384), // S4_pstorerft_abs
2466 UINT64_C(878706688), // S4_pstorerft_rr
2467 UINT64_C(2942312576), // S4_pstorerftnew_abs
2468 UINT64_C(1113587712), // S4_pstorerftnew_io
2469 UINT64_C(912261120), // S4_pstorerftnew_rr
2470 UINT64_C(2940207236), // S4_pstorerhf_abs
2471 UINT64_C(893386752), // S4_pstorerhf_rr
2472 UINT64_C(2940215428), // S4_pstorerhfnew_abs
2473 UINT64_C(1178599424), // S4_pstorerhfnew_io
2474 UINT64_C(926941184), // S4_pstorerhfnew_rr
2475 UINT64_C(2946500740), // S4_pstorerhnewf_abs
2476 UINT64_C(899678216), // S4_pstorerhnewf_rr
2477 UINT64_C(2946508932), // S4_pstorerhnewfnew_abs
2478 UINT64_C(1184892928), // S4_pstorerhnewfnew_io
2479 UINT64_C(933232648), // S4_pstorerhnewfnew_rr
2480 UINT64_C(2946500736), // S4_pstorerhnewt_abs
2481 UINT64_C(882901000), // S4_pstorerhnewt_rr
2482 UINT64_C(2946508928), // S4_pstorerhnewtnew_abs
2483 UINT64_C(1117784064), // S4_pstorerhnewtnew_io
2484 UINT64_C(916455432), // S4_pstorerhnewtnew_rr
2485 UINT64_C(2940207232), // S4_pstorerht_abs
2486 UINT64_C(876609536), // S4_pstorerht_rr
2487 UINT64_C(2940215424), // S4_pstorerhtnew_abs
2488 UINT64_C(1111490560), // S4_pstorerhtnew_io
2489 UINT64_C(910163968), // S4_pstorerhtnew_rr
2490 UINT64_C(2944401540), // S4_pstorerif_abs
2491 UINT64_C(897581056), // S4_pstorerif_rr
2492 UINT64_C(2944409732), // S4_pstorerifnew_abs
2493 UINT64_C(1182793728), // S4_pstorerifnew_io
2494 UINT64_C(931135488), // S4_pstorerifnew_rr
2495 UINT64_C(2946502788), // S4_pstorerinewf_abs
2496 UINT64_C(899678224), // S4_pstorerinewf_rr
2497 UINT64_C(2946510980), // S4_pstorerinewfnew_abs
2498 UINT64_C(1184894976), // S4_pstorerinewfnew_io
2499 UINT64_C(933232656), // S4_pstorerinewfnew_rr
2500 UINT64_C(2946502784), // S4_pstorerinewt_abs
2501 UINT64_C(882901008), // S4_pstorerinewt_rr
2502 UINT64_C(2946510976), // S4_pstorerinewtnew_abs
2503 UINT64_C(1117786112), // S4_pstorerinewtnew_io
2504 UINT64_C(916455440), // S4_pstorerinewtnew_rr
2505 UINT64_C(2944401536), // S4_pstorerit_abs
2506 UINT64_C(880803840), // S4_pstorerit_rr
2507 UINT64_C(2944409728), // S4_pstoreritnew_abs
2508 UINT64_C(1115684864), // S4_pstoreritnew_io
2509 UINT64_C(914358272), // S4_pstoreritnew_rr
2510 UINT64_C(2699034624), // S4_stored_locked
2511 UINT64_C(2699034632), // S4_stored_rl_at_vi
2512 UINT64_C(2699034664), // S4_stored_rl_st_vi
2513 UINT64_C(1006632960), // S4_storeirb_io
2514 UINT64_C(947912704), // S4_storeirbf_io
2515 UINT64_C(964689920), // S4_storeirbfnew_io
2516 UINT64_C(939524096), // S4_storeirbt_io
2517 UINT64_C(956301312), // S4_storeirbtnew_io
2518 UINT64_C(1008730112), // S4_storeirh_io
2519 UINT64_C(950009856), // S4_storeirhf_io
2520 UINT64_C(966787072), // S4_storeirhfnew_io
2521 UINT64_C(941621248), // S4_storeirht_io
2522 UINT64_C(958398464), // S4_storeirhtnew_io
2523 UINT64_C(1010827264), // S4_storeiri_io
2524 UINT64_C(952107008), // S4_storeirif_io
2525 UINT64_C(968884224), // S4_storeirifnew_io
2526 UINT64_C(943718400), // S4_storeirit_io
2527 UINT64_C(960495616), // S4_storeiritnew_io
2528 UINT64_C(2868904064), // S4_storerb_ap
2529 UINT64_C(989855744), // S4_storerb_rr
2530 UINT64_C(2902458496), // S4_storerb_ur
2531 UINT64_C(2879389824), // S4_storerbnew_ap
2532 UINT64_C(1000341504), // S4_storerbnew_rr
2533 UINT64_C(2912944256), // S4_storerbnew_ur
2534 UINT64_C(2881486976), // S4_storerd_ap
2535 UINT64_C(1002438656), // S4_storerd_rr
2536 UINT64_C(2915041408), // S4_storerd_ur
2537 UINT64_C(2875195520), // S4_storerf_ap
2538 UINT64_C(996147200), // S4_storerf_rr
2539 UINT64_C(2908749952), // S4_storerf_ur
2540 UINT64_C(2873098368), // S4_storerh_ap
2541 UINT64_C(994050048), // S4_storerh_rr
2542 UINT64_C(2906652800), // S4_storerh_ur
2543 UINT64_C(2879391872), // S4_storerhnew_ap
2544 UINT64_C(1000341512), // S4_storerhnew_rr
2545 UINT64_C(2912946304), // S4_storerhnew_ur
2546 UINT64_C(2877292672), // S4_storeri_ap
2547 UINT64_C(998244352), // S4_storeri_rr
2548 UINT64_C(2910847104), // S4_storeri_ur
2549 UINT64_C(2879393920), // S4_storerinew_ap
2550 UINT64_C(1000341520), // S4_storerinew_rr
2551 UINT64_C(2912948352), // S4_storerinew_ur
2552 UINT64_C(3682598912), // S4_subaddi
2553 UINT64_C(3724541958), // S4_subi_asl_ri
2554 UINT64_C(3724541974), // S4_subi_lsr_ri
2555 UINT64_C(3284140224), // S4_vrcrotate
2556 UINT64_C(3416260608), // S4_vrcrotate_acc
2557 UINT64_C(3242197120), // S4_vxaddsubh
2558 UINT64_C(3250585600), // S4_vxaddsubhr
2559 UINT64_C(3242196992), // S4_vxaddsubw
2560 UINT64_C(3242197184), // S4_vxsubaddh
2561 UINT64_C(3250585664), // S4_vxsubaddhr
2562 UINT64_C(3242197056), // S4_vxsubaddw
2563 UINT64_C(2287992960), // S5_asrhub_rnd_sat
2564 UINT64_C(2287992992), // S5_asrhub_sat
2565 UINT64_C(2287992928), // S5_popcountp
2566 UINT64_C(2149580800), // S5_vasrhrnd
2567 UINT64_C(2147483744), // S6_rol_i_p
2568 UINT64_C(2181038304), // S6_rol_i_p_acc
2569 UINT64_C(2185232480), // S6_rol_i_p_and
2570 UINT64_C(2181038176), // S6_rol_i_p_nac
2571 UINT64_C(2185232608), // S6_rol_i_p_or
2572 UINT64_C(2189426784), // S6_rol_i_p_xacc
2573 UINT64_C(2348810336), // S6_rol_i_r
2574 UINT64_C(2382364896), // S6_rol_i_r_acc
2575 UINT64_C(2386559072), // S6_rol_i_r_and
2576 UINT64_C(2382364768), // S6_rol_i_r_nac
2577 UINT64_C(2386559200), // S6_rol_i_r_or
2578 UINT64_C(2390753376), // S6_rol_i_r_xacc
2579 UINT64_C(2218786944), // S6_vsplatrbp
2580 UINT64_C(3246391392), // S6_vtrunehb_ppp
2581 UINT64_C(3246391456), // S6_vtrunohb_ppp
2582 UINT64_C(0), // SA1_addi
2583 UINT64_C(6144), // SA1_addrx
2584 UINT64_C(3072), // SA1_addsp
2585 UINT64_C(4608), // SA1_and1
2586 UINT64_C(6768), // SA1_clrf
2587 UINT64_C(6736), // SA1_clrfnew
2588 UINT64_C(6752), // SA1_clrt
2589 UINT64_C(6720), // SA1_clrtnew
2590 UINT64_C(6400), // SA1_cmpeqi
2591 UINT64_C(7168), // SA1_combine0i
2592 UINT64_C(7176), // SA1_combine1i
2593 UINT64_C(7184), // SA1_combine2i
2594 UINT64_C(7192), // SA1_combine3i
2595 UINT64_C(7432), // SA1_combinerz
2596 UINT64_C(7424), // SA1_combinezr
2597 UINT64_C(4864), // SA1_dec
2598 UINT64_C(4352), // SA1_inc
2599 UINT64_C(2048), // SA1_seti
2600 UINT64_C(6656), // SA1_setin1
2601 UINT64_C(5376), // SA1_sxtb
2602 UINT64_C(5120), // SA1_sxth
2603 UINT64_C(4096), // SA1_tfr
2604 UINT64_C(5888), // SA1_zxtb
2605 UINT64_C(5632), // SA1_zxth
2606 UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4
2607 UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK
2608 UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_EXT
2609 UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_EXT_PIC
2610 UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_PIC
2611 UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_EXT
2612 UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_EXT_PIC
2613 UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_PIC
2614 UINT64_C(0), // SL1_loadri_io
2615 UINT64_C(4096), // SL1_loadrub_io
2616 UINT64_C(7936), // SL2_deallocframe
2617 UINT64_C(8128), // SL2_jumpr31
2618 UINT64_C(8133), // SL2_jumpr31_f
2619 UINT64_C(8135), // SL2_jumpr31_fnew
2620 UINT64_C(8132), // SL2_jumpr31_t
2621 UINT64_C(8134), // SL2_jumpr31_tnew
2622 UINT64_C(4096), // SL2_loadrb_io
2623 UINT64_C(7680), // SL2_loadrd_sp
2624 UINT64_C(0), // SL2_loadrh_io
2625 UINT64_C(7168), // SL2_loadri_sp
2626 UINT64_C(2048), // SL2_loadruh_io
2627 UINT64_C(8000), // SL2_return
2628 UINT64_C(8005), // SL2_return_f
2629 UINT64_C(8007), // SL2_return_fnew
2630 UINT64_C(8004), // SL2_return_t
2631 UINT64_C(8006), // SL2_return_tnew
2632 UINT64_C(4096), // SS1_storeb_io
2633 UINT64_C(0), // SS1_storew_io
2634 UINT64_C(7168), // SS2_allocframe
2635 UINT64_C(4608), // SS2_storebi0
2636 UINT64_C(4864), // SS2_storebi1
2637 UINT64_C(2560), // SS2_stored_sp
2638 UINT64_C(0), // SS2_storeh_io
2639 UINT64_C(2048), // SS2_storew_sp
2640 UINT64_C(4096), // SS2_storewi0
2641 UINT64_C(4352), // SS2_storewi1
2642 UINT64_C(0), // TFRI64_V2_ext
2643 UINT64_C(0), // TFRI64_V4
2644 UINT64_C(2449473568), // V6_extractw
2645 UINT64_C(432013536), // V6_get_qfext
2646 UINT64_C(432013504), // V6_get_qfext_oracc
2647 UINT64_C(432013376), // V6_lvsplatb
2648 UINT64_C(432013344), // V6_lvsplath
2649 UINT64_C(429916192), // V6_lvsplatw
2650 UINT64_C(503513088), // V6_pred_and
2651 UINT64_C(503513108), // V6_pred_and_n
2652 UINT64_C(503513096), // V6_pred_not
2653 UINT64_C(503513092), // V6_pred_or
2654 UINT64_C(503513104), // V6_pred_or_n
2655 UINT64_C(429916228), // V6_pred_scalar2
2656 UINT64_C(429916236), // V6_pred_scalar2v2
2657 UINT64_C(503513100), // V6_pred_xor
2658 UINT64_C(432013408), // V6_set_qfext
2659 UINT64_C(503513112), // V6_shuffeqh
2660 UINT64_C(503513116), // V6_shuffeqw
2661 UINT64_C(524296320), // V6_v6mpyhubs10
2662 UINT64_C(522199168), // V6_v6mpyhubs10_vxx
2663 UINT64_C(524296192), // V6_v6mpyvubs10
2664 UINT64_C(522199040), // V6_v6mpyvubs10_vxx
2665 UINT64_C(671088864), // V6_vL32Ub_ai
2666 UINT64_C(687866080), // V6_vL32Ub_pi
2667 UINT64_C(721420512), // V6_vL32Ub_ppu
2668 UINT64_C(671088640), // V6_vL32b_ai
2669 UINT64_C(671088672), // V6_vL32b_cur_ai
2670 UINT64_C(679477408), // V6_vL32b_cur_npred_ai
2671 UINT64_C(696254624), // V6_vL32b_cur_npred_pi
2672 UINT64_C(729809056), // V6_vL32b_cur_npred_ppu
2673 UINT64_C(687865888), // V6_vL32b_cur_pi
2674 UINT64_C(721420320), // V6_vL32b_cur_ppu
2675 UINT64_C(679477376), // V6_vL32b_cur_pred_ai
2676 UINT64_C(696254592), // V6_vL32b_cur_pred_pi
2677 UINT64_C(729809024), // V6_vL32b_cur_pred_ppu
2678 UINT64_C(679477344), // V6_vL32b_npred_ai
2679 UINT64_C(696254560), // V6_vL32b_npred_pi
2680 UINT64_C(729808992), // V6_vL32b_npred_ppu
2681 UINT64_C(675282944), // V6_vL32b_nt_ai
2682 UINT64_C(675282976), // V6_vL32b_nt_cur_ai
2683 UINT64_C(683671712), // V6_vL32b_nt_cur_npred_ai
2684 UINT64_C(700448928), // V6_vL32b_nt_cur_npred_pi
2685 UINT64_C(734003360), // V6_vL32b_nt_cur_npred_ppu
2686 UINT64_C(692060192), // V6_vL32b_nt_cur_pi
2687 UINT64_C(725614624), // V6_vL32b_nt_cur_ppu
2688 UINT64_C(683671680), // V6_vL32b_nt_cur_pred_ai
2689 UINT64_C(700448896), // V6_vL32b_nt_cur_pred_pi
2690 UINT64_C(734003328), // V6_vL32b_nt_cur_pred_ppu
2691 UINT64_C(683671648), // V6_vL32b_nt_npred_ai
2692 UINT64_C(700448864), // V6_vL32b_nt_npred_pi
2693 UINT64_C(734003296), // V6_vL32b_nt_npred_ppu
2694 UINT64_C(692060160), // V6_vL32b_nt_pi
2695 UINT64_C(725614592), // V6_vL32b_nt_ppu
2696 UINT64_C(683671616), // V6_vL32b_nt_pred_ai
2697 UINT64_C(700448832), // V6_vL32b_nt_pred_pi
2698 UINT64_C(734003264), // V6_vL32b_nt_pred_ppu
2699 UINT64_C(675283008), // V6_vL32b_nt_tmp_ai
2700 UINT64_C(683671776), // V6_vL32b_nt_tmp_npred_ai
2701 UINT64_C(700448992), // V6_vL32b_nt_tmp_npred_pi
2702 UINT64_C(734003424), // V6_vL32b_nt_tmp_npred_ppu
2703 UINT64_C(692060224), // V6_vL32b_nt_tmp_pi
2704 UINT64_C(725614656), // V6_vL32b_nt_tmp_ppu
2705 UINT64_C(683671744), // V6_vL32b_nt_tmp_pred_ai
2706 UINT64_C(700448960), // V6_vL32b_nt_tmp_pred_pi
2707 UINT64_C(734003392), // V6_vL32b_nt_tmp_pred_ppu
2708 UINT64_C(687865856), // V6_vL32b_pi
2709 UINT64_C(721420288), // V6_vL32b_ppu
2710 UINT64_C(679477312), // V6_vL32b_pred_ai
2711 UINT64_C(696254528), // V6_vL32b_pred_pi
2712 UINT64_C(729808960), // V6_vL32b_pred_ppu
2713 UINT64_C(671088704), // V6_vL32b_tmp_ai
2714 UINT64_C(679477472), // V6_vL32b_tmp_npred_ai
2715 UINT64_C(696254688), // V6_vL32b_tmp_npred_pi
2716 UINT64_C(729809120), // V6_vL32b_tmp_npred_ppu
2717 UINT64_C(687865920), // V6_vL32b_tmp_pi
2718 UINT64_C(721420352), // V6_vL32b_tmp_ppu
2719 UINT64_C(679477440), // V6_vL32b_tmp_pred_ai
2720 UINT64_C(696254656), // V6_vL32b_tmp_pred_pi
2721 UINT64_C(729809088), // V6_vL32b_tmp_pred_ppu
2722 UINT64_C(673186016), // V6_vS32Ub_ai
2723 UINT64_C(681574624), // V6_vS32Ub_npred_ai
2724 UINT64_C(698351840), // V6_vS32Ub_npred_pi
2725 UINT64_C(731906272), // V6_vS32Ub_npred_ppu
2726 UINT64_C(689963232), // V6_vS32Ub_pi
2727 UINT64_C(723517664), // V6_vS32Ub_ppu
2728 UINT64_C(681574592), // V6_vS32Ub_pred_ai
2729 UINT64_C(698351808), // V6_vS32Ub_pred_pi
2730 UINT64_C(731906240), // V6_vS32Ub_pred_ppu
2731 UINT64_C(673185792), // V6_vS32b_ai
2732 UINT64_C(673185824), // V6_vS32b_new_ai
2733 UINT64_C(681574504), // V6_vS32b_new_npred_ai
2734 UINT64_C(698351720), // V6_vS32b_new_npred_pi
2735 UINT64_C(731906152), // V6_vS32b_new_npred_ppu
2736 UINT64_C(689963040), // V6_vS32b_new_pi
2737 UINT64_C(723517472), // V6_vS32b_new_ppu
2738 UINT64_C(681574464), // V6_vS32b_new_pred_ai
2739 UINT64_C(698351680), // V6_vS32b_new_pred_pi
2740 UINT64_C(731906112), // V6_vS32b_new_pred_ppu
2741 UINT64_C(681574432), // V6_vS32b_npred_ai
2742 UINT64_C(698351648), // V6_vS32b_npred_pi
2743 UINT64_C(731906080), // V6_vS32b_npred_ppu
2744 UINT64_C(679477280), // V6_vS32b_nqpred_ai
2745 UINT64_C(696254496), // V6_vS32b_nqpred_pi
2746 UINT64_C(729808928), // V6_vS32b_nqpred_ppu
2747 UINT64_C(677380096), // V6_vS32b_nt_ai
2748 UINT64_C(677380128), // V6_vS32b_nt_new_ai
2749 UINT64_C(685768824), // V6_vS32b_nt_new_npred_ai
2750 UINT64_C(702546040), // V6_vS32b_nt_new_npred_pi
2751 UINT64_C(736100472), // V6_vS32b_nt_new_npred_ppu
2752 UINT64_C(694157344), // V6_vS32b_nt_new_pi
2753 UINT64_C(727711776), // V6_vS32b_nt_new_ppu
2754 UINT64_C(685768784), // V6_vS32b_nt_new_pred_ai
2755 UINT64_C(702546000), // V6_vS32b_nt_new_pred_pi
2756 UINT64_C(736100432), // V6_vS32b_nt_new_pred_ppu
2757 UINT64_C(685768736), // V6_vS32b_nt_npred_ai
2758 UINT64_C(702545952), // V6_vS32b_nt_npred_pi
2759 UINT64_C(736100384), // V6_vS32b_nt_npred_ppu
2760 UINT64_C(683671584), // V6_vS32b_nt_nqpred_ai
2761 UINT64_C(700448800), // V6_vS32b_nt_nqpred_pi
2762 UINT64_C(734003232), // V6_vS32b_nt_nqpred_ppu
2763 UINT64_C(694157312), // V6_vS32b_nt_pi
2764 UINT64_C(727711744), // V6_vS32b_nt_ppu
2765 UINT64_C(685768704), // V6_vS32b_nt_pred_ai
2766 UINT64_C(702545920), // V6_vS32b_nt_pred_pi
2767 UINT64_C(736100352), // V6_vS32b_nt_pred_ppu
2768 UINT64_C(683671552), // V6_vS32b_nt_qpred_ai
2769 UINT64_C(700448768), // V6_vS32b_nt_qpred_pi
2770 UINT64_C(734003200), // V6_vS32b_nt_qpred_ppu
2771 UINT64_C(689963008), // V6_vS32b_pi
2772 UINT64_C(723517440), // V6_vS32b_ppu
2773 UINT64_C(681574400), // V6_vS32b_pred_ai
2774 UINT64_C(698351616), // V6_vS32b_pred_pi
2775 UINT64_C(731906048), // V6_vS32b_pred_ppu
2776 UINT64_C(679477248), // V6_vS32b_qpred_ai
2777 UINT64_C(696254464), // V6_vS32b_qpred_pi
2778 UINT64_C(729808896), // V6_vS32b_qpred_ppu
2779 UINT64_C(673185832), // V6_vS32b_srls_ai
2780 UINT64_C(689963048), // V6_vS32b_srls_pi
2781 UINT64_C(723517480), // V6_vS32b_srls_ppu
2782 UINT64_C(476455104), // V6_vabs_f8
2783 UINT64_C(503718016), // V6_vabs_hf
2784 UINT64_C(503718048), // V6_vabs_sf
2785 UINT64_C(503382144), // V6_vabsb
2786 UINT64_C(503382176), // V6_vabsb_sat
2787 UINT64_C(482344992), // V6_vabsdiffh
2788 UINT64_C(482344960), // V6_vabsdiffub
2789 UINT64_C(482345024), // V6_vabsdiffuh
2790 UINT64_C(482345056), // V6_vabsdiffw
2791 UINT64_C(503316480), // V6_vabsh
2792 UINT64_C(503316512), // V6_vabsh_sat
2793 UINT64_C(503316544), // V6_vabsw
2794 UINT64_C(503316576), // V6_vabsw_sat
2795 UINT64_C(526393440), // V6_vadd_hf
2796 UINT64_C(528482432), // V6_vadd_hf_f8
2797 UINT64_C(530587872), // V6_vadd_hf_hf
2798 UINT64_C(526393408), // V6_vadd_qf16
2799 UINT64_C(526393472), // V6_vadd_qf16_mix
2800 UINT64_C(530587648), // V6_vadd_qf32
2801 UINT64_C(530587712), // V6_vadd_qf32_mix
2802 UINT64_C(530587680), // V6_vadd_sf
2803 UINT64_C(490741952), // V6_vadd_sf_bf
2804 UINT64_C(528490624), // V6_vadd_sf_hf
2805 UINT64_C(528490688), // V6_vadd_sf_sf
2806 UINT64_C(530579648), // V6_vaddb
2807 UINT64_C(476053632), // V6_vaddb_dv
2808 UINT64_C(503390304), // V6_vaddbnq
2809 UINT64_C(503390208), // V6_vaddbq
2810 UINT64_C(520093696), // V6_vaddbsat
2811 UINT64_C(513802240), // V6_vaddbsat_dv
2812 UINT64_C(480256000), // V6_vaddcarry
2813 UINT64_C(497033216), // V6_vaddcarryo
2814 UINT64_C(494936064), // V6_vaddcarrysat
2815 UINT64_C(520101888), // V6_vaddclbh
2816 UINT64_C(520101920), // V6_vaddclbw
2817 UINT64_C(530579680), // V6_vaddh
2818 UINT64_C(476053664), // V6_vaddh_dv
2819 UINT64_C(503390336), // V6_vaddhnq
2820 UINT64_C(503390240), // V6_vaddhq
2821 UINT64_C(473956448), // V6_vaddhsat
2822 UINT64_C(478150688), // V6_vaddhsat_dv
2823 UINT64_C(480247936), // V6_vaddhw
2824 UINT64_C(471867456), // V6_vaddhw_acc
2825 UINT64_C(480247872), // V6_vaddubh
2826 UINT64_C(473964704), // V6_vaddubh_acc
2827 UINT64_C(473956384), // V6_vaddubsat
2828 UINT64_C(476053728), // V6_vaddubsat_dv
2829 UINT64_C(513802368), // V6_vaddububb_sat
2830 UINT64_C(473956416), // V6_vadduhsat
2831 UINT64_C(478150656), // V6_vadduhsat_dv
2832 UINT64_C(480247904), // V6_vadduhw
2833 UINT64_C(473964672), // V6_vadduhw_acc
2834 UINT64_C(526385184), // V6_vadduwsat
2835 UINT64_C(513802304), // V6_vadduwsat_dv
2836 UINT64_C(473956352), // V6_vaddw
2837 UINT64_C(476053696), // V6_vaddw_dv
2838 UINT64_C(503390368), // V6_vaddwnq
2839 UINT64_C(503390272), // V6_vaddwq
2840 UINT64_C(473956480), // V6_vaddwsat
2841 UINT64_C(478150720), // V6_vaddwsat_dv
2842 UINT64_C(452984832), // V6_valignb
2843 UINT64_C(505421824), // V6_valignbi
2844 UINT64_C(471859360), // V6_vand
2845 UINT64_C(429917344), // V6_vandnqrt
2846 UINT64_C(425731168), // V6_vandnqrt_acc
2847 UINT64_C(429916320), // V6_vandqrt
2848 UINT64_C(425730144), // V6_vandqrt_acc
2849 UINT64_C(503521312), // V6_vandvnqv
2850 UINT64_C(503521280), // V6_vandvqv
2851 UINT64_C(429916232), // V6_vandvrt
2852 UINT64_C(425730176), // V6_vandvrt_acc
2853 UINT64_C(427819008), // V6_vaslh
2854 UINT64_C(429924512), // V6_vaslh_acc
2855 UINT64_C(530579616), // V6_vaslhv
2856 UINT64_C(425722080), // V6_vaslw
2857 UINT64_C(425730112), // V6_vaslw_acc
2858 UINT64_C(530579584), // V6_vaslwv
2859 UINT64_C(446701792), // V6_vasr_into
2860 UINT64_C(425722048), // V6_vasrh
2861 UINT64_C(427827424), // V6_vasrh_acc
2862 UINT64_C(452993024), // V6_vasrhbrndsat
2863 UINT64_C(402653184), // V6_vasrhbsat
2864 UINT64_C(452985056), // V6_vasrhubrndsat
2865 UINT64_C(452985024), // V6_vasrhubsat
2866 UINT64_C(530579552), // V6_vasrhv
2867 UINT64_C(402653408), // V6_vasruhubrndsat
2868 UINT64_C(402661536), // V6_vasruhubsat
2869 UINT64_C(402653216), // V6_vasruwuhrndsat
2870 UINT64_C(402661504), // V6_vasruwuhsat
2871 UINT64_C(486539360), // V6_vasrvuhubrndsat
2872 UINT64_C(486539328), // V6_vasrvuhubsat
2873 UINT64_C(486539296), // V6_vasrvwuhrndsat
2874 UINT64_C(486539264), // V6_vasrvwuhsat
2875 UINT64_C(425722016), // V6_vasrw
2876 UINT64_C(425730208), // V6_vasrw_acc
2877 UINT64_C(452984896), // V6_vasrwh
2878 UINT64_C(452984960), // V6_vasrwhrndsat
2879 UINT64_C(452984928), // V6_vasrwhsat
2880 UINT64_C(402653248), // V6_vasrwuhrndsat
2881 UINT64_C(452984992), // V6_vasrwuhsat
2882 UINT64_C(530579456), // V6_vasrwv
2883 UINT64_C(503521504), // V6_vassign
2884 UINT64_C(503717920), // V6_vassign_fp
2885 UINT64_C(503382208), // V6_vassign_tmp
2886 UINT64_C(520102016), // V6_vavgb
2887 UINT64_C(520102048), // V6_vavgbrnd
2888 UINT64_C(482345152), // V6_vavgh
2889 UINT64_C(484442272), // V6_vavghrnd
2890 UINT64_C(482345088), // V6_vavgub
2891 UINT64_C(484442208), // V6_vavgubrnd
2892 UINT64_C(482345120), // V6_vavguh
2893 UINT64_C(484442240), // V6_vavguhrnd
2894 UINT64_C(520101952), // V6_vavguw
2895 UINT64_C(520101984), // V6_vavguwrnd
2896 UINT64_C(482345184), // V6_vavgw
2897 UINT64_C(484442304), // V6_vavgwrnd
2898 UINT64_C(442499072), // V6_vccombine
2899 UINT64_C(503447776), // V6_vcl0h
2900 UINT64_C(503447712), // V6_vcl0w
2901 UINT64_C(436207616), // V6_vcmov
2902 UINT64_C(524288224), // V6_vcombine
2903 UINT64_C(513802464), // V6_vcombine_tmp
2904 UINT64_C(503652416), // V6_vconv_h_hf
2905 UINT64_C(503652480), // V6_vconv_hf_h
2906 UINT64_C(503586912), // V6_vconv_hf_qf16
2907 UINT64_C(503587008), // V6_vconv_hf_qf32
2908 UINT64_C(503586816), // V6_vconv_sf_qf32
2909 UINT64_C(503652448), // V6_vconv_sf_w
2910 UINT64_C(503652384), // V6_vconv_w_sf
2911 UINT64_C(448798912), // V6_vcvt2_b_hf
2912 UINT64_C(517284032), // V6_vcvt2_hf_b
2913 UINT64_C(517284064), // V6_vcvt2_hf_ub
2914 UINT64_C(448798944), // V6_vcvt2_ub_hf
2915 UINT64_C(532684992), // V6_vcvt_b_hf
2916 UINT64_C(490741856), // V6_vcvt_bf_sf
2917 UINT64_C(534782016), // V6_vcvt_f8_hf
2918 UINT64_C(503717888), // V6_vcvt_h_hf
2919 UINT64_C(503586880), // V6_vcvt_hf_b
2920 UINT64_C(503652512), // V6_vcvt_hf_f8
2921 UINT64_C(503587040), // V6_vcvt_hf_h
2922 UINT64_C(526393376), // V6_vcvt_hf_sf
2923 UINT64_C(503586848), // V6_vcvt_hf_ub
2924 UINT64_C(503586976), // V6_vcvt_hf_uh
2925 UINT64_C(503586944), // V6_vcvt_sf_hf
2926 UINT64_C(532684960), // V6_vcvt_ub_hf
2927 UINT64_C(503652352), // V6_vcvt_uh_hf
2928 UINT64_C(434118720), // V6_vdeal
2929 UINT64_C(503316704), // V6_vdealb
2930 UINT64_C(522191072), // V6_vdealb4w
2931 UINT64_C(503316672), // V6_vdealh
2932 UINT64_C(452993152), // V6_vdealvdd
2933 UINT64_C(522190880), // V6_vdelta
2934 UINT64_C(530587840), // V6_vdmpy_sf_hf
2935 UINT64_C(473964640), // V6_vdmpy_sf_hf_acc
2936 UINT64_C(419430592), // V6_vdmpybus
2937 UINT64_C(419438784), // V6_vdmpybus_acc
2938 UINT64_C(419430624), // V6_vdmpybus_dv
2939 UINT64_C(419438816), // V6_vdmpybus_dv_acc
2940 UINT64_C(419430464), // V6_vdmpyhb
2941 UINT64_C(419438688), // V6_vdmpyhb_acc
2942 UINT64_C(421527680), // V6_vdmpyhb_dv
2943 UINT64_C(421535872), // V6_vdmpyhb_dv_acc
2944 UINT64_C(421527648), // V6_vdmpyhisat
2945 UINT64_C(421535808), // V6_vdmpyhisat_acc
2946 UINT64_C(421527616), // V6_vdmpyhsat
2947 UINT64_C(421535840), // V6_vdmpyhsat_acc
2948 UINT64_C(421527584), // V6_vdmpyhsuisat
2949 UINT64_C(421535776), // V6_vdmpyhsuisat_acc
2950 UINT64_C(421527552), // V6_vdmpyhsusat
2951 UINT64_C(421535744), // V6_vdmpyhsusat_acc
2952 UINT64_C(469762144), // V6_vdmpyhvsat
2953 UINT64_C(469770336), // V6_vdmpyhvsat_acc
2954 UINT64_C(419430560), // V6_vdsaduh
2955 UINT64_C(425730048), // V6_vdsaduh_acc
2956 UINT64_C(528482304), // V6_veqb
2957 UINT64_C(478158848), // V6_veqb_and
2958 UINT64_C(478158912), // V6_veqb_or
2959 UINT64_C(478158976), // V6_veqb_xor
2960 UINT64_C(528482308), // V6_veqh
2961 UINT64_C(478158852), // V6_veqh_and
2962 UINT64_C(478158916), // V6_veqh_or
2963 UINT64_C(478158980), // V6_veqh_xor
2964 UINT64_C(528482312), // V6_veqw
2965 UINT64_C(478158856), // V6_veqw_and
2966 UINT64_C(478158920), // V6_veqw_or
2967 UINT64_C(478158984), // V6_veqw_xor
2968 UINT64_C(476061856), // V6_vfmax_f8
2969 UINT64_C(476061760), // V6_vfmax_hf
2970 UINT64_C(476061792), // V6_vfmax_sf
2971 UINT64_C(476061824), // V6_vfmin_f8
2972 UINT64_C(476061696), // V6_vfmin_hf
2973 UINT64_C(476061728), // V6_vfmin_sf
2974 UINT64_C(476455136), // V6_vfneg_f8
2975 UINT64_C(503717952), // V6_vfneg_hf
2976 UINT64_C(503717984), // V6_vfneg_sf
2977 UINT64_C(788529408), // V6_vgathermh
2978 UINT64_C(788530432), // V6_vgathermhq
2979 UINT64_C(788529664), // V6_vgathermhw
2980 UINT64_C(788530688), // V6_vgathermhwq
2981 UINT64_C(788529152), // V6_vgathermw
2982 UINT64_C(788530176), // V6_vgathermwq
2983 UINT64_C(528482320), // V6_vgtb
2984 UINT64_C(478158864), // V6_vgtb_and
2985 UINT64_C(478158928), // V6_vgtb_or
2986 UINT64_C(478158992), // V6_vgtb_xor
2987 UINT64_C(478158968), // V6_vgtbf
2988 UINT64_C(478159056), // V6_vgtbf_and
2989 UINT64_C(478158904), // V6_vgtbf_or
2990 UINT64_C(478159088), // V6_vgtbf_xor
2991 UINT64_C(528482324), // V6_vgth
2992 UINT64_C(478158868), // V6_vgth_and
2993 UINT64_C(478158932), // V6_vgth_or
2994 UINT64_C(478158996), // V6_vgth_xor
2995 UINT64_C(478158964), // V6_vgthf
2996 UINT64_C(478159052), // V6_vgthf_and
2997 UINT64_C(478158900), // V6_vgthf_or
2998 UINT64_C(478159084), // V6_vgthf_xor
2999 UINT64_C(478158960), // V6_vgtsf
3000 UINT64_C(478159048), // V6_vgtsf_and
3001 UINT64_C(478158896), // V6_vgtsf_or
3002 UINT64_C(478159080), // V6_vgtsf_xor
3003 UINT64_C(528482336), // V6_vgtub
3004 UINT64_C(478158880), // V6_vgtub_and
3005 UINT64_C(478158944), // V6_vgtub_or
3006 UINT64_C(478159008), // V6_vgtub_xor
3007 UINT64_C(528482340), // V6_vgtuh
3008 UINT64_C(478158884), // V6_vgtuh_and
3009 UINT64_C(478158948), // V6_vgtuh_or
3010 UINT64_C(478159012), // V6_vgtuh_xor
3011 UINT64_C(528482344), // V6_vgtuw
3012 UINT64_C(478158888), // V6_vgtuw_and
3013 UINT64_C(478158952), // V6_vgtuw_or
3014 UINT64_C(478159016), // V6_vgtuw_xor
3015 UINT64_C(528482328), // V6_vgtw
3016 UINT64_C(478158872), // V6_vgtw_and
3017 UINT64_C(478158936), // V6_vgtw_or
3018 UINT64_C(478159000), // V6_vgtw_xor
3019 UINT64_C(503324800), // V6_vhist
3020 UINT64_C(503455872), // V6_vhistq
3021 UINT64_C(429924384), // V6_vinsertwr
3022 UINT64_C(452984864), // V6_vlalignb
3023 UINT64_C(509616128), // V6_vlalignbi
3024 UINT64_C(427819104), // V6_vlsrb
3025 UINT64_C(427819072), // V6_vlsrh
3026 UINT64_C(530579520), // V6_vlsrhv
3027 UINT64_C(427819040), // V6_vlsrw
3028 UINT64_C(530579488), // V6_vlsrwv
3029 UINT64_C(425721984), // V6_vlut4
3030 UINT64_C(452993056), // V6_vlutvvb
3031 UINT64_C(402653280), // V6_vlutvvb_nm
3032 UINT64_C(452993184), // V6_vlutvvb_oracc
3033 UINT64_C(482353152), // V6_vlutvvb_oracci
3034 UINT64_C(505413632), // V6_vlutvvbi
3035 UINT64_C(452993216), // V6_vlutvwh
3036 UINT64_C(402653312), // V6_vlutvwh_nm
3037 UINT64_C(452993248), // V6_vlutvwh_oracc
3038 UINT64_C(484450304), // V6_vlutvwh_oracci
3039 UINT64_C(509607936), // V6_vlutvwhi
3040 UINT64_C(490741984), // V6_vmax_bf
3041 UINT64_C(532684896), // V6_vmax_hf
3042 UINT64_C(532684832), // V6_vmax_sf
3043 UINT64_C(522191008), // V6_vmaxb
3044 UINT64_C(520093920), // V6_vmaxh
3045 UINT64_C(520093856), // V6_vmaxub
3046 UINT64_C(520093888), // V6_vmaxuh
3047 UINT64_C(522190848), // V6_vmaxw
3048 UINT64_C(520102112), // V6_vmerge_qf
3049 UINT64_C(490741760), // V6_vmin_bf
3050 UINT64_C(532684928), // V6_vmin_hf
3051 UINT64_C(532684864), // V6_vmin_sf
3052 UINT64_C(522190976), // V6_vminb
3053 UINT64_C(520093792), // V6_vminh
3054 UINT64_C(520093728), // V6_vminub
3055 UINT64_C(520093760), // V6_vminuh
3056 UINT64_C(520093824), // V6_vminw
3057 UINT64_C(421527744), // V6_vmpabus
3058 UINT64_C(421535936), // V6_vmpabus_acc
3059 UINT64_C(471859296), // V6_vmpabusv
3060 UINT64_C(425721952), // V6_vmpabuu
3061 UINT64_C(429924480), // V6_vmpabuu_acc
3062 UINT64_C(484442336), // V6_vmpabuuv
3063 UINT64_C(421527776), // V6_vmpahb
3064 UINT64_C(421535968), // V6_vmpahb_acc
3065 UINT64_C(427827328), // V6_vmpahhsat
3066 UINT64_C(427819168), // V6_vmpauhb
3067 UINT64_C(427827264), // V6_vmpauhb_acc
3068 UINT64_C(427827360), // V6_vmpauhuhsat
3069 UINT64_C(427827392), // V6_vmpsuhuhsat
3070 UINT64_C(528482496), // V6_vmpy_hf_f8
3071 UINT64_C(528482528), // V6_vmpy_hf_f8_acc
3072 UINT64_C(528490592), // V6_vmpy_hf_hf
3073 UINT64_C(473964608), // V6_vmpy_hf_hf_acc
3074 UINT64_C(534782048), // V6_vmpy_qf16
3075 UINT64_C(534782080), // V6_vmpy_qf16_hf
3076 UINT64_C(534782112), // V6_vmpy_qf16_mix_hf
3077 UINT64_C(534781952), // V6_vmpy_qf32
3078 UINT64_C(534782176), // V6_vmpy_qf32_hf
3079 UINT64_C(528490496), // V6_vmpy_qf32_mix_hf
3080 UINT64_C(534782144), // V6_vmpy_qf32_qf16
3081 UINT64_C(534781984), // V6_vmpy_qf32_sf
3082 UINT64_C(436215904), // V6_vmpy_rt_hf
3083 UINT64_C(436215872), // V6_vmpy_rt_qf16
3084 UINT64_C(436215840), // V6_vmpy_rt_sf
3085 UINT64_C(490741888), // V6_vmpy_sf_bf
3086 UINT64_C(486547456), // V6_vmpy_sf_bf_acc
3087 UINT64_C(528490560), // V6_vmpy_sf_hf
3088 UINT64_C(473964576), // V6_vmpy_sf_hf_acc
3089 UINT64_C(528490528), // V6_vmpy_sf_sf
3090 UINT64_C(421527712), // V6_vmpybus
3091 UINT64_C(421535904), // V6_vmpybus_acc
3092 UINT64_C(469762240), // V6_vmpybusv
3093 UINT64_C(469770432), // V6_vmpybusv_acc
3094 UINT64_C(469762176), // V6_vmpybv
3095 UINT64_C(469770368), // V6_vmpybv_acc
3096 UINT64_C(534773920), // V6_vmpyewuh
3097 UINT64_C(513802432), // V6_vmpyewuh_64
3098 UINT64_C(423624704), // V6_vmpyh
3099 UINT64_C(429924544), // V6_vmpyh_acc
3100 UINT64_C(423632896), // V6_vmpyhsat_acc
3101 UINT64_C(423624768), // V6_vmpyhsrs
3102 UINT64_C(423624736), // V6_vmpyhss
3103 UINT64_C(471859264), // V6_vmpyhus
3104 UINT64_C(471867424), // V6_vmpyhus_acc
3105 UINT64_C(469762272), // V6_vmpyhv
3106 UINT64_C(469770464), // V6_vmpyhv_acc
3107 UINT64_C(471859232), // V6_vmpyhvsrs
3108 UINT64_C(526385152), // V6_vmpyieoh
3109 UINT64_C(473964544), // V6_vmpyiewh_acc
3110 UINT64_C(532676608), // V6_vmpyiewuh
3111 UINT64_C(471867552), // V6_vmpyiewuh_acc
3112 UINT64_C(471859328), // V6_vmpyih
3113 UINT64_C(471867520), // V6_vmpyih_acc
3114 UINT64_C(425721856), // V6_vmpyihb
3115 UINT64_C(425730080), // V6_vmpyihb_acc
3116 UINT64_C(532676640), // V6_vmpyiowh
3117 UINT64_C(429916160), // V6_vmpyiwb
3118 UINT64_C(423632960), // V6_vmpyiwb_acc
3119 UINT64_C(427819232), // V6_vmpyiwh
3120 UINT64_C(423632992), // V6_vmpyiwh_acc
3121 UINT64_C(427819200), // V6_vmpyiwub
3122 UINT64_C(427827232), // V6_vmpyiwub_acc
3123 UINT64_C(534773984), // V6_vmpyowh
3124 UINT64_C(471867488), // V6_vmpyowh_64_acc
3125 UINT64_C(524288000), // V6_vmpyowh_rnd
3126 UINT64_C(471867616), // V6_vmpyowh_rnd_sacc
3127 UINT64_C(471867584), // V6_vmpyowh_sacc
3128 UINT64_C(432013312), // V6_vmpyub
3129 UINT64_C(427827200), // V6_vmpyub_acc
3130 UINT64_C(469762208), // V6_vmpyubv
3131 UINT64_C(469770400), // V6_vmpyubv_acc
3132 UINT64_C(423624800), // V6_vmpyuh
3133 UINT64_C(423632928), // V6_vmpyuh_acc
3134 UINT64_C(425721920), // V6_vmpyuhe
3135 UINT64_C(427827296), // V6_vmpyuhe_acc
3136 UINT64_C(471859200), // V6_vmpyuhv
3137 UINT64_C(471867392), // V6_vmpyuhv_acc
3138 UINT64_C(532685024), // V6_vmpyuhvs
3139 UINT64_C(518004736), // V6_vmux
3140 UINT64_C(520102080), // V6_vnavgb
3141 UINT64_C(484442144), // V6_vnavgh
3142 UINT64_C(484442112), // V6_vnavgub
3143 UINT64_C(484442176), // V6_vnavgw
3144 UINT64_C(440401920), // V6_vnccombine
3145 UINT64_C(438304768), // V6_vncmov
3146 UINT64_C(503513248), // V6_vnormamth
3147 UINT64_C(503513216), // V6_vnormamtw
3148 UINT64_C(503316608), // V6_vnot
3149 UINT64_C(471859392), // V6_vor
3150 UINT64_C(532676672), // V6_vpackeb
3151 UINT64_C(532676704), // V6_vpackeh
3152 UINT64_C(532676800), // V6_vpackhb_sat
3153 UINT64_C(532676768), // V6_vpackhub_sat
3154 UINT64_C(534773792), // V6_vpackob
3155 UINT64_C(534773824), // V6_vpackoh
3156 UINT64_C(534773760), // V6_vpackwh_sat
3157 UINT64_C(532676832), // V6_vpackwuh_sat
3158 UINT64_C(503447744), // V6_vpopcounth
3159 UINT64_C(503521344), // V6_vprefixqb
3160 UINT64_C(503521600), // V6_vprefixqh
3161 UINT64_C(503521856), // V6_vprefixqw
3162 UINT64_C(522190944), // V6_vrdelta
3163 UINT64_C(432013472), // V6_vrmpybub_rtt
3164 UINT64_C(429924352), // V6_vrmpybub_rtt_acc
3165 UINT64_C(419430528), // V6_vrmpybus
3166 UINT64_C(419438752), // V6_vrmpybus_acc
3167 UINT64_C(423624832), // V6_vrmpybusi
3168 UINT64_C(423633024), // V6_vrmpybusi_acc
3169 UINT64_C(469762112), // V6_vrmpybusv
3170 UINT64_C(469770304), // V6_vrmpybusv_acc
3171 UINT64_C(469762080), // V6_vrmpybv
3172 UINT64_C(469770272), // V6_vrmpybv_acc
3173 UINT64_C(419430496), // V6_vrmpyub
3174 UINT64_C(419438720), // V6_vrmpyub_acc
3175 UINT64_C(432013440), // V6_vrmpyub_rtt
3176 UINT64_C(429924576), // V6_vrmpyub_rtt_acc
3177 UINT64_C(429916352), // V6_vrmpyubi
3178 UINT64_C(425730240), // V6_vrmpyubi_acc
3179 UINT64_C(469762048), // V6_vrmpyubv
3180 UINT64_C(469770240), // V6_vrmpyubv_acc
3181 UINT64_C(434634752), // V6_vrmpyzbb_rt
3182 UINT64_C(432021568), // V6_vrmpyzbb_rt_acc
3183 UINT64_C(434110464), // V6_vrmpyzbb_rx
3184 UINT64_C(432545856), // V6_vrmpyzbb_rx_acc
3185 UINT64_C(435683392), // V6_vrmpyzbub_rt
3186 UINT64_C(433070112), // V6_vrmpyzbub_rt_acc
3187 UINT64_C(435159104), // V6_vrmpyzbub_rx
3188 UINT64_C(433594400), // V6_vrmpyzbub_rx_acc
3189 UINT64_C(434634784), // V6_vrmpyzcb_rt
3190 UINT64_C(432021600), // V6_vrmpyzcb_rt_acc
3191 UINT64_C(434110496), // V6_vrmpyzcb_rx
3192 UINT64_C(432545888), // V6_vrmpyzcb_rx_acc
3193 UINT64_C(434634816), // V6_vrmpyzcbs_rt
3194 UINT64_C(432021536), // V6_vrmpyzcbs_rt_acc
3195 UINT64_C(434110528), // V6_vrmpyzcbs_rx
3196 UINT64_C(432545824), // V6_vrmpyzcbs_rx_acc
3197 UINT64_C(435683328), // V6_vrmpyznb_rt
3198 UINT64_C(433070144), // V6_vrmpyznb_rt_acc
3199 UINT64_C(435159040), // V6_vrmpyznb_rx
3200 UINT64_C(433594432), // V6_vrmpyznb_rx_acc
3201 UINT64_C(425721888), // V6_vror
3202 UINT64_C(444604640), // V6_vrotr
3203 UINT64_C(526385344), // V6_vroundhb
3204 UINT64_C(526385376), // V6_vroundhub
3205 UINT64_C(534773856), // V6_vrounduhub
3206 UINT64_C(534773888), // V6_vrounduwuh
3207 UINT64_C(526385280), // V6_vroundwh
3208 UINT64_C(526385312), // V6_vroundwuh
3209 UINT64_C(423624896), // V6_vrsadubi
3210 UINT64_C(423633088), // V6_vrsadubi_acc
3211 UINT64_C(494936288), // V6_vsatdw
3212 UINT64_C(526385216), // V6_vsathub
3213 UINT64_C(522191040), // V6_vsatuwuh
3214 UINT64_C(526385248), // V6_vsatwh
3215 UINT64_C(503447648), // V6_vsb
3216 UINT64_C(790626336), // V6_vscattermh
3217 UINT64_C(790626464), // V6_vscattermh_add
3218 UINT64_C(796917888), // V6_vscattermhq
3219 UINT64_C(790626368), // V6_vscattermhw
3220 UINT64_C(790626496), // V6_vscattermhw_add
3221 UINT64_C(799014912), // V6_vscattermhwq
3222 UINT64_C(790626304), // V6_vscattermw
3223 UINT64_C(790626432), // V6_vscattermw_add
3224 UINT64_C(796917760), // V6_vscattermwq
3225 UINT64_C(503447680), // V6_vsh
3226 UINT64_C(524288096), // V6_vshufeh
3227 UINT64_C(434118688), // V6_vshuff
3228 UINT64_C(503447552), // V6_vshuffb
3229 UINT64_C(524288032), // V6_vshuffeb
3230 UINT64_C(503382240), // V6_vshuffh
3231 UINT64_C(524288064), // V6_vshuffob
3232 UINT64_C(452993120), // V6_vshuffvdd
3233 UINT64_C(524288192), // V6_vshufoeb
3234 UINT64_C(524288160), // V6_vshufoeh
3235 UINT64_C(524288128), // V6_vshufoh
3236 UINT64_C(526393536), // V6_vsub_hf
3237 UINT64_C(528482464), // V6_vsub_hf_f8
3238 UINT64_C(526393344), // V6_vsub_hf_hf
3239 UINT64_C(526393504), // V6_vsub_qf16
3240 UINT64_C(526393568), // V6_vsub_qf16_mix
3241 UINT64_C(530587744), // V6_vsub_qf32
3242 UINT64_C(530587808), // V6_vsub_qf32_mix
3243 UINT64_C(530587776), // V6_vsub_sf
3244 UINT64_C(490741920), // V6_vsub_sf_bf
3245 UINT64_C(528490656), // V6_vsub_sf_hf
3246 UINT64_C(528490720), // V6_vsub_sf_sf
3247 UINT64_C(473956512), // V6_vsubb
3248 UINT64_C(478150752), // V6_vsubb_dv
3249 UINT64_C(503455776), // V6_vsubbnq
3250 UINT64_C(503390400), // V6_vsubbq
3251 UINT64_C(522190912), // V6_vsubbsat
3252 UINT64_C(513802272), // V6_vsubbsat_dv
3253 UINT64_C(480256128), // V6_vsubcarry
3254 UINT64_C(497033344), // V6_vsubcarryo
3255 UINT64_C(473956544), // V6_vsubh
3256 UINT64_C(478150784), // V6_vsubh_dv
3257 UINT64_C(503455808), // V6_vsubhnq
3258 UINT64_C(503390432), // V6_vsubhq
3259 UINT64_C(476053568), // V6_vsubhsat
3260 UINT64_C(480247808), // V6_vsubhsat_dv
3261 UINT64_C(480248032), // V6_vsubhw
3262 UINT64_C(480247968), // V6_vsububh
3263 UINT64_C(476053504), // V6_vsububsat
3264 UINT64_C(478150848), // V6_vsububsat_dv
3265 UINT64_C(513802400), // V6_vsubububb_sat
3266 UINT64_C(476053536), // V6_vsubuhsat
3267 UINT64_C(478150880), // V6_vsubuhsat_dv
3268 UINT64_C(480248000), // V6_vsubuhw
3269 UINT64_C(532676736), // V6_vsubuwsat
3270 UINT64_C(513802336), // V6_vsubuwsat_dv
3271 UINT64_C(473956576), // V6_vsubw
3272 UINT64_C(478150816), // V6_vsubw_dv
3273 UINT64_C(503455840), // V6_vsubwnq
3274 UINT64_C(503455744), // V6_vsubwq
3275 UINT64_C(476053600), // V6_vsubwsat
3276 UINT64_C(480247840), // V6_vsubwsat_dv
3277 UINT64_C(513810432), // V6_vswap
3278 UINT64_C(419430400), // V6_vtmpyb
3279 UINT64_C(419438592), // V6_vtmpyb_acc
3280 UINT64_C(419430432), // V6_vtmpybus
3281 UINT64_C(419438624), // V6_vtmpybus_acc
3282 UINT64_C(429916288), // V6_vtmpyhb
3283 UINT64_C(419438656), // V6_vtmpyhb_acc
3284 UINT64_C(503382080), // V6_vunpackb
3285 UINT64_C(503382112), // V6_vunpackh
3286 UINT64_C(503324672), // V6_vunpackob
3287 UINT64_C(503324704), // V6_vunpackoh
3288 UINT64_C(503382016), // V6_vunpackub
3289 UINT64_C(503382048), // V6_vunpackuh
3290 UINT64_C(503325824), // V6_vwhist128
3291 UINT64_C(503326336), // V6_vwhist128m
3292 UINT64_C(503456896), // V6_vwhist128q
3293 UINT64_C(503457408), // V6_vwhist128qm
3294 UINT64_C(503325312), // V6_vwhist256
3295 UINT64_C(503325568), // V6_vwhist256_sat
3296 UINT64_C(503456384), // V6_vwhist256q
3297 UINT64_C(503456640), // V6_vwhist256q_sat
3298 UINT64_C(471859424), // V6_vxor
3299 UINT64_C(503447584), // V6_vzb
3300 UINT64_C(503447616), // V6_vzh
3301 UINT64_C(738197504), // V6_zLd_ai
3302 UINT64_C(754974720), // V6_zLd_pi
3303 UINT64_C(754974721), // V6_zLd_ppu
3304 UINT64_C(746586112), // V6_zLd_pred_ai
3305 UINT64_C(763363328), // V6_zLd_pred_pi
3306 UINT64_C(763363329), // V6_zLd_pred_ppu
3307 UINT64_C(429916448), // V6_zextract
3308 UINT64_C(2818572288), // Y2_barrier
3309 UINT64_C(1814036480), // Y2_break
3310 UINT64_C(1677721696), // Y2_ciad
3311 UINT64_C(1694498816), // Y2_crswap0
3312 UINT64_C(1677721632), // Y2_cswi
3313 UINT64_C(2684354560), // Y2_dccleana
3314 UINT64_C(2720006144), // Y2_dccleanidx
3315 UINT64_C(2688548864), // Y2_dccleaninva
3316 UINT64_C(2724200448), // Y2_dccleaninvidx
3317 UINT64_C(2483027968), // Y2_dcfetchbo
3318 UINT64_C(2686451712), // Y2_dcinva
3319 UINT64_C(2722103296), // Y2_dcinvidx
3320 UINT64_C(2717908992), // Y2_dckill
3321 UINT64_C(2753560576), // Y2_dctagr
3322 UINT64_C(2751463424), // Y2_dctagw
3323 UINT64_C(2696937472), // Y2_dczeroa
3324 UINT64_C(1711276032), // Y2_getimask
3325 UINT64_C(1717567488), // Y2_iassignr
3326 UINT64_C(1677721664), // Y2_iassignw
3327 UINT64_C(1436549120), // Y2_icdatar
3328 UINT64_C(1438654464), // Y2_icdataw
3329 UINT64_C(1455423488), // Y2_icinva
3330 UINT64_C(1455425536), // Y2_icinvidx
3331 UINT64_C(1455427584), // Y2_ickill
3332 UINT64_C(1440743424), // Y2_ictagr
3333 UINT64_C(1438646272), // Y2_ictagw
3334 UINT64_C(1472200706), // Y2_isync
3335 UINT64_C(1814036576), // Y2_k0lock
3336 UINT64_C(1814036608), // Y2_k0unlock
3337 UINT64_C(2824863744), // Y2_l2cleaninvidx
3338 UINT64_C(2820669440), // Y2_l2kill
3339 UINT64_C(1681915936), // Y2_resume
3340 UINT64_C(1686110208), // Y2_setimask
3341 UINT64_C(1686110240), // Y2_setprio
3342 UINT64_C(1684013088), // Y2_start
3343 UINT64_C(1684013056), // Y2_stop
3344 UINT64_C(1677721600), // Y2_swi
3345 UINT64_C(2822766592), // Y2_syncht
3346 UINT64_C(1853882368), // Y2_tfrscrr
3347 UINT64_C(1728053248), // Y2_tfrsrcr
3348 UINT64_C(1814036512), // Y2_tlblock
3349 UINT64_C(1820327936), // Y2_tlbp
3350 UINT64_C(1816133632), // Y2_tlbr
3351 UINT64_C(1814036544), // Y2_tlbunlock
3352 UINT64_C(1811939328), // Y2_tlbw
3353 UINT64_C(1681915904), // Y2_wait
3354 UINT64_C(1696595968), // Y4_crswap1
3355 UINT64_C(1837105152), // Y4_crswap10
3356 UINT64_C(2785017856), // Y4_l2fetch
3357 UINT64_C(2757754880), // Y4_l2tagr
3358 UINT64_C(2755657728), // Y4_l2tagw
3359 UINT64_C(1684013120), // Y4_nmi
3360 UINT64_C(1686110304), // Y4_siad
3361 UINT64_C(1862270976), // Y4_tfrscpp
3362 UINT64_C(1828716544), // Y4_tfrspcp
3363 UINT64_C(1648361472), // Y4_trace
3364 UINT64_C(1824522240), // Y5_ctlbw
3365 UINT64_C(2787115008), // Y5_l2cleanidx
3366 UINT64_C(2793406464), // Y5_l2fetch
3367 UINT64_C(2820673536), // Y5_l2gclean
3368 UINT64_C(2820675584), // Y5_l2gcleaninv
3369 UINT64_C(2820671488), // Y5_l2gunlock
3370 UINT64_C(2789212160), // Y5_l2invidx
3371 UINT64_C(2699042816), // Y5_l2locka
3372 UINT64_C(2791309312), // Y5_l2unlocka
3373 UINT64_C(1822425088), // Y5_tlbasidi
3374 UINT64_C(1826619392), // Y5_tlboc
3375 UINT64_C(1648361504), // Y6_diag
3376 UINT64_C(1648361536), // Y6_diag0
3377 UINT64_C(1648361568), // Y6_diag1
3378 UINT64_C(2785017920), // Y6_dmlink
3379 UINT64_C(2818572384), // Y6_dmpause
3380 UINT64_C(2818572352), // Y6_dmpoll
3381 UINT64_C(2785017984), // Y6_dmresume
3382 UINT64_C(2785017888), // Y6_dmstart
3383 UINT64_C(2818572320), // Y6_dmwait
3384 UINT64_C(2797600768), // Y6_l2gcleaninvpa
3385 UINT64_C(2795503616), // Y6_l2gcleanpa
3386 UINT64_C(3581935616), // dep_A2_addsat
3387 UINT64_C(3581935744), // dep_A2_subsat
3388 UINT64_C(3556769792), // dep_S2_packhl
3389 UINT64_C(0), // invalid_decode
3390 UINT64_C(0)
3391 };
3392 const unsigned opcode = MI.getOpcode();
3393 uint64_t Value = InstBits[opcode];
3394 uint64_t op = 0;
3395 (void)op; // suppress warning
3396 switch (opcode) {
3397 case Hexagon::A2_nop:
3398 case Hexagon::CONST32:
3399 case Hexagon::CONST64:
3400 case Hexagon::DuplexIClass0:
3401 case Hexagon::DuplexIClass1:
3402 case Hexagon::DuplexIClass2:
3403 case Hexagon::DuplexIClass3:
3404 case Hexagon::DuplexIClass4:
3405 case Hexagon::DuplexIClass5:
3406 case Hexagon::DuplexIClass6:
3407 case Hexagon::DuplexIClass7:
3408 case Hexagon::DuplexIClass8:
3409 case Hexagon::DuplexIClass9:
3410 case Hexagon::DuplexIClassA:
3411 case Hexagon::DuplexIClassB:
3412 case Hexagon::DuplexIClassC:
3413 case Hexagon::DuplexIClassD:
3414 case Hexagon::DuplexIClassE:
3415 case Hexagon::DuplexIClassF:
3416 case Hexagon::J2_rte:
3417 case Hexagon::J2_unpause:
3418 case Hexagon::SL2_deallocframe:
3419 case Hexagon::SL2_jumpr31:
3420 case Hexagon::SL2_jumpr31_f:
3421 case Hexagon::SL2_jumpr31_fnew:
3422 case Hexagon::SL2_jumpr31_t:
3423 case Hexagon::SL2_jumpr31_tnew:
3424 case Hexagon::SL2_return:
3425 case Hexagon::SL2_return_f:
3426 case Hexagon::SL2_return_fnew:
3427 case Hexagon::SL2_return_t:
3428 case Hexagon::SL2_return_tnew:
3429 case Hexagon::TFRI64_V2_ext:
3430 case Hexagon::TFRI64_V4:
3431 case Hexagon::V6_vhist:
3432 case Hexagon::V6_vwhist128:
3433 case Hexagon::V6_vwhist256:
3434 case Hexagon::V6_vwhist256_sat:
3435 case Hexagon::Y2_barrier:
3436 case Hexagon::Y2_break:
3437 case Hexagon::Y2_dckill:
3438 case Hexagon::Y2_ickill:
3439 case Hexagon::Y2_isync:
3440 case Hexagon::Y2_k0lock:
3441 case Hexagon::Y2_k0unlock:
3442 case Hexagon::Y2_l2kill:
3443 case Hexagon::Y2_syncht:
3444 case Hexagon::Y2_tlblock:
3445 case Hexagon::Y2_tlbunlock:
3446 case Hexagon::Y5_l2gclean:
3447 case Hexagon::Y5_l2gcleaninv:
3448 case Hexagon::Y5_l2gunlock:
3449 case Hexagon::invalid_decode: {
3450 break;
3451 }
3452 case Hexagon::A2_tfrcrr: {
3453 // op: Cs32
3454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3455 op &= UINT64_C(31);
3456 op <<= 16;
3457 Value |= op;
3458 // op: Rd32
3459 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3460 op &= UINT64_C(31);
3461 Value |= op;
3462 break;
3463 }
3464 case Hexagon::A4_tfrcpp: {
3465 // op: Css32
3466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3467 op &= UINT64_C(31);
3468 op <<= 16;
3469 Value |= op;
3470 // op: Rdd32
3471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3472 op &= UINT64_C(31);
3473 Value |= op;
3474 break;
3475 }
3476 case Hexagon::G4_tfrgcrr: {
3477 // op: Gs32
3478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3479 op &= UINT64_C(31);
3480 op <<= 16;
3481 Value |= op;
3482 // op: Rd32
3483 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3484 op &= UINT64_C(31);
3485 Value |= op;
3486 break;
3487 }
3488 case Hexagon::G4_tfrgcpp: {
3489 // op: Gss32
3490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3491 op &= UINT64_C(31);
3492 op <<= 16;
3493 Value |= op;
3494 // op: Rdd32
3495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3496 op &= UINT64_C(31);
3497 Value |= op;
3498 break;
3499 }
3500 case Hexagon::J4_cmpeqi_f_jumpnv_nt:
3501 case Hexagon::J4_cmpeqi_f_jumpnv_t:
3502 case Hexagon::J4_cmpeqi_t_jumpnv_nt:
3503 case Hexagon::J4_cmpeqi_t_jumpnv_t:
3504 case Hexagon::J4_cmpgti_f_jumpnv_nt:
3505 case Hexagon::J4_cmpgti_f_jumpnv_t:
3506 case Hexagon::J4_cmpgti_t_jumpnv_nt:
3507 case Hexagon::J4_cmpgti_t_jumpnv_t:
3508 case Hexagon::J4_cmpgtui_f_jumpnv_nt:
3509 case Hexagon::J4_cmpgtui_f_jumpnv_t:
3510 case Hexagon::J4_cmpgtui_t_jumpnv_nt:
3511 case Hexagon::J4_cmpgtui_t_jumpnv_t: {
3512 // op: II
3513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3514 op &= UINT64_C(31);
3515 op <<= 8;
3516 Value |= op;
3517 // op: Ii
3518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3519 Value |= (op & UINT64_C(1536)) << 11;
3520 Value |= (op & UINT64_C(508)) >> 1;
3521 // op: Ns8
3522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3523 op &= UINT64_C(7);
3524 op <<= 16;
3525 Value |= op;
3526 break;
3527 }
3528 case Hexagon::J4_cmpeqi_fp0_jump_nt:
3529 case Hexagon::J4_cmpeqi_fp0_jump_t:
3530 case Hexagon::J4_cmpeqi_fp1_jump_nt:
3531 case Hexagon::J4_cmpeqi_fp1_jump_t:
3532 case Hexagon::J4_cmpeqi_tp0_jump_nt:
3533 case Hexagon::J4_cmpeqi_tp0_jump_t:
3534 case Hexagon::J4_cmpeqi_tp1_jump_nt:
3535 case Hexagon::J4_cmpeqi_tp1_jump_t:
3536 case Hexagon::J4_cmpgti_fp0_jump_nt:
3537 case Hexagon::J4_cmpgti_fp0_jump_t:
3538 case Hexagon::J4_cmpgti_fp1_jump_nt:
3539 case Hexagon::J4_cmpgti_fp1_jump_t:
3540 case Hexagon::J4_cmpgti_tp0_jump_nt:
3541 case Hexagon::J4_cmpgti_tp0_jump_t:
3542 case Hexagon::J4_cmpgti_tp1_jump_nt:
3543 case Hexagon::J4_cmpgti_tp1_jump_t:
3544 case Hexagon::J4_cmpgtui_fp0_jump_nt:
3545 case Hexagon::J4_cmpgtui_fp0_jump_t:
3546 case Hexagon::J4_cmpgtui_fp1_jump_nt:
3547 case Hexagon::J4_cmpgtui_fp1_jump_t:
3548 case Hexagon::J4_cmpgtui_tp0_jump_nt:
3549 case Hexagon::J4_cmpgtui_tp0_jump_t:
3550 case Hexagon::J4_cmpgtui_tp1_jump_nt:
3551 case Hexagon::J4_cmpgtui_tp1_jump_t: {
3552 // op: II
3553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3554 op &= UINT64_C(31);
3555 op <<= 8;
3556 Value |= op;
3557 // op: Ii
3558 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3559 Value |= (op & UINT64_C(1536)) << 11;
3560 Value |= (op & UINT64_C(508)) >> 1;
3561 // op: Rs16
3562 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3563 op &= UINT64_C(15);
3564 op <<= 16;
3565 Value |= op;
3566 break;
3567 }
3568 case Hexagon::S4_storerbnew_ap:
3569 case Hexagon::S4_storerhnew_ap:
3570 case Hexagon::S4_storerinew_ap: {
3571 // op: II
3572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3573 op &= UINT64_C(63);
3574 Value |= op;
3575 // op: Nt8
3576 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3577 op &= UINT64_C(7);
3578 op <<= 8;
3579 Value |= op;
3580 // op: Re32
3581 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3582 op &= UINT64_C(31);
3583 op <<= 16;
3584 Value |= op;
3585 break;
3586 }
3587 case Hexagon::S4_storerb_ap:
3588 case Hexagon::S4_storerf_ap:
3589 case Hexagon::S4_storerh_ap:
3590 case Hexagon::S4_storeri_ap: {
3591 // op: II
3592 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3593 op &= UINT64_C(63);
3594 Value |= op;
3595 // op: Rt32
3596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3597 op &= UINT64_C(31);
3598 op <<= 8;
3599 Value |= op;
3600 // op: Re32
3601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3602 op &= UINT64_C(31);
3603 op <<= 16;
3604 Value |= op;
3605 break;
3606 }
3607 case Hexagon::S4_storerd_ap: {
3608 // op: II
3609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3610 op &= UINT64_C(63);
3611 Value |= op;
3612 // op: Rtt32
3613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3614 op &= UINT64_C(31);
3615 op <<= 8;
3616 Value |= op;
3617 // op: Re32
3618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3619 op &= UINT64_C(31);
3620 op <<= 16;
3621 Value |= op;
3622 break;
3623 }
3624 case Hexagon::J4_jumpseti: {
3625 // op: II
3626 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3627 op &= UINT64_C(63);
3628 op <<= 8;
3629 Value |= op;
3630 // op: Ii
3631 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3632 Value |= (op & UINT64_C(1536)) << 11;
3633 Value |= (op & UINT64_C(508)) >> 1;
3634 // op: Rd16
3635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3636 op &= UINT64_C(15);
3637 op <<= 16;
3638 Value |= op;
3639 break;
3640 }
3641 case Hexagon::L4_loadbsw2_ap:
3642 case Hexagon::L4_loadbzw2_ap:
3643 case Hexagon::L4_loadrb_ap:
3644 case Hexagon::L4_loadrh_ap:
3645 case Hexagon::L4_loadri_ap:
3646 case Hexagon::L4_loadrub_ap:
3647 case Hexagon::L4_loadruh_ap: {
3648 // op: II
3649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3650 Value |= (op & UINT64_C(60)) << 6;
3651 Value |= (op & UINT64_C(3)) << 5;
3652 // op: Rd32
3653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3654 op &= UINT64_C(31);
3655 Value |= op;
3656 // op: Re32
3657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3658 op &= UINT64_C(31);
3659 op <<= 16;
3660 Value |= op;
3661 break;
3662 }
3663 case Hexagon::L4_loadbsw4_ap:
3664 case Hexagon::L4_loadbzw4_ap:
3665 case Hexagon::L4_loadrd_ap: {
3666 // op: II
3667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3668 Value |= (op & UINT64_C(60)) << 6;
3669 Value |= (op & UINT64_C(3)) << 5;
3670 // op: Rdd32
3671 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3672 op &= UINT64_C(31);
3673 Value |= op;
3674 // op: Re32
3675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3676 op &= UINT64_C(31);
3677 op <<= 16;
3678 Value |= op;
3679 break;
3680 }
3681 case Hexagon::L4_loadalignb_ap:
3682 case Hexagon::L4_loadalignh_ap: {
3683 // op: II
3684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
3685 Value |= (op & UINT64_C(60)) << 6;
3686 Value |= (op & UINT64_C(3)) << 5;
3687 // op: Ryy32
3688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3689 op &= UINT64_C(31);
3690 Value |= op;
3691 // op: Re32
3692 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3693 op &= UINT64_C(31);
3694 op <<= 16;
3695 Value |= op;
3696 break;
3697 }
3698 case Hexagon::J2_call:
3699 case Hexagon::J2_jump: {
3700 // op: Ii
3701 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3702 Value |= (op & UINT64_C(16744448)) << 1;
3703 Value |= (op & UINT64_C(32764)) >> 1;
3704 break;
3705 }
3706 case Hexagon::PS_storerinewabs:
3707 case Hexagon::S2_storerinewgp: {
3708 // op: Ii
3709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3710 Value |= (op & UINT64_C(196608)) << 9;
3711 Value |= (op & UINT64_C(63488)) << 5;
3712 Value |= (op & UINT64_C(1024)) << 3;
3713 Value |= (op & UINT64_C(1020)) >> 2;
3714 // op: Nt8
3715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3716 op &= UINT64_C(7);
3717 op <<= 8;
3718 Value |= op;
3719 break;
3720 }
3721 case Hexagon::PS_storeriabs:
3722 case Hexagon::S2_storerigp: {
3723 // op: Ii
3724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3725 Value |= (op & UINT64_C(196608)) << 9;
3726 Value |= (op & UINT64_C(63488)) << 5;
3727 Value |= (op & UINT64_C(1024)) << 3;
3728 Value |= (op & UINT64_C(1020)) >> 2;
3729 // op: Rt32
3730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3731 op &= UINT64_C(31);
3732 op <<= 8;
3733 Value |= op;
3734 break;
3735 }
3736 case Hexagon::J2_trap0:
3737 case Hexagon::PS_trap1: {
3738 // op: Ii
3739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3740 Value |= (op & UINT64_C(248)) << 5;
3741 Value |= (op & UINT64_C(7)) << 2;
3742 break;
3743 }
3744 case Hexagon::PS_storerdabs:
3745 case Hexagon::S2_storerdgp: {
3746 // op: Ii
3747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3748 Value |= (op & UINT64_C(393216)) << 8;
3749 Value |= (op & UINT64_C(126976)) << 4;
3750 Value |= (op & UINT64_C(2048)) << 2;
3751 Value |= (op & UINT64_C(2040)) >> 3;
3752 // op: Rtt32
3753 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3754 op &= UINT64_C(31);
3755 op <<= 8;
3756 Value |= op;
3757 break;
3758 }
3759 case Hexagon::A4_ext: {
3760 // op: Ii
3761 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3762 Value |= (op & UINT64_C(4293918720)) >> 4;
3763 Value |= (op & UINT64_C(1048512)) >> 6;
3764 break;
3765 }
3766 case Hexagon::PS_storerbnewabs:
3767 case Hexagon::S2_storerbnewgp: {
3768 // op: Ii
3769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3770 Value |= (op & UINT64_C(49152)) << 11;
3771 Value |= (op & UINT64_C(15872)) << 7;
3772 Value |= (op & UINT64_C(256)) << 5;
3773 Value |= (op & UINT64_C(255));
3774 // op: Nt8
3775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3776 op &= UINT64_C(7);
3777 op <<= 8;
3778 Value |= op;
3779 break;
3780 }
3781 case Hexagon::PS_storerbabs:
3782 case Hexagon::S2_storerbgp: {
3783 // op: Ii
3784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3785 Value |= (op & UINT64_C(49152)) << 11;
3786 Value |= (op & UINT64_C(15872)) << 7;
3787 Value |= (op & UINT64_C(256)) << 5;
3788 Value |= (op & UINT64_C(255));
3789 // op: Rt32
3790 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3791 op &= UINT64_C(31);
3792 op <<= 8;
3793 Value |= op;
3794 break;
3795 }
3796 case Hexagon::J2_loop0i:
3797 case Hexagon::J2_loop1i:
3798 case Hexagon::J2_ploop1si:
3799 case Hexagon::J2_ploop2si:
3800 case Hexagon::J2_ploop3si: {
3801 // op: Ii
3802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3803 Value |= (op & UINT64_C(496)) << 4;
3804 Value |= (op & UINT64_C(12)) << 1;
3805 // op: II
3806 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3807 Value |= (op & UINT64_C(992)) << 11;
3808 Value |= (op & UINT64_C(28)) << 3;
3809 Value |= (op & UINT64_C(3));
3810 break;
3811 }
3812 case Hexagon::J2_loop0r:
3813 case Hexagon::J2_loop1r:
3814 case Hexagon::J2_ploop1sr:
3815 case Hexagon::J2_ploop2sr:
3816 case Hexagon::J2_ploop3sr: {
3817 // op: Ii
3818 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3819 Value |= (op & UINT64_C(496)) << 4;
3820 Value |= (op & UINT64_C(12)) << 1;
3821 // op: Rs32
3822 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3823 op &= UINT64_C(31);
3824 op <<= 16;
3825 Value |= op;
3826 break;
3827 }
3828 case Hexagon::J2_pause: {
3829 // op: Ii
3830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3831 Value |= (op & UINT64_C(768)) << 8;
3832 Value |= (op & UINT64_C(248)) << 5;
3833 Value |= (op & UINT64_C(7)) << 2;
3834 break;
3835 }
3836 case Hexagon::PS_storerhnewabs:
3837 case Hexagon::S2_storerhnewgp: {
3838 // op: Ii
3839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3840 Value |= (op & UINT64_C(98304)) << 10;
3841 Value |= (op & UINT64_C(31744)) << 6;
3842 Value |= (op & UINT64_C(512)) << 4;
3843 Value |= (op & UINT64_C(510)) >> 1;
3844 // op: Nt8
3845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3846 op &= UINT64_C(7);
3847 op <<= 8;
3848 Value |= op;
3849 break;
3850 }
3851 case Hexagon::PS_storerfabs:
3852 case Hexagon::PS_storerhabs:
3853 case Hexagon::S2_storerfgp:
3854 case Hexagon::S2_storerhgp: {
3855 // op: Ii
3856 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3857 Value |= (op & UINT64_C(98304)) << 10;
3858 Value |= (op & UINT64_C(31744)) << 6;
3859 Value |= (op & UINT64_C(512)) << 4;
3860 Value |= (op & UINT64_C(510)) >> 1;
3861 // op: Rt32
3862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3863 op &= UINT64_C(31);
3864 op <<= 8;
3865 Value |= op;
3866 break;
3867 }
3868 case Hexagon::V6_vwhist128m: {
3869 // op: Ii
3870 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3871 op &= UINT64_C(1);
3872 op <<= 8;
3873 Value |= op;
3874 break;
3875 }
3876 case Hexagon::SS2_storew_sp: {
3877 // op: Ii
3878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3879 op &= UINT64_C(124);
3880 op <<= 2;
3881 Value |= op;
3882 // op: Rt16
3883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3884 op &= UINT64_C(15);
3885 Value |= op;
3886 break;
3887 }
3888 case Hexagon::SS2_allocframe: {
3889 // op: Ii
3890 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3891 op &= UINT64_C(248);
3892 op <<= 1;
3893 Value |= op;
3894 break;
3895 }
3896 case Hexagon::SS2_stored_sp: {
3897 // op: Ii
3898 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3899 op &= UINT64_C(504);
3900 Value |= op;
3901 // op: Rtt8
3902 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3903 op &= UINT64_C(7);
3904 Value |= op;
3905 break;
3906 }
3907 case Hexagon::S2_storerd_io: {
3908 // op: Ii
3909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3910 Value |= (op & UINT64_C(12288)) << 13;
3911 Value |= (op & UINT64_C(2048)) << 2;
3912 Value |= (op & UINT64_C(2040)) >> 3;
3913 // op: Rs32
3914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3915 op &= UINT64_C(31);
3916 op <<= 16;
3917 Value |= op;
3918 // op: Rtt32
3919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3920 op &= UINT64_C(31);
3921 op <<= 8;
3922 Value |= op;
3923 break;
3924 }
3925 case Hexagon::J4_tstbit0_f_jumpnv_nt:
3926 case Hexagon::J4_tstbit0_f_jumpnv_t:
3927 case Hexagon::J4_tstbit0_t_jumpnv_nt:
3928 case Hexagon::J4_tstbit0_t_jumpnv_t: {
3929 // op: Ii
3930 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3931 Value |= (op & UINT64_C(1536)) << 11;
3932 Value |= (op & UINT64_C(508)) >> 1;
3933 // op: Ns8
3934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3935 op &= UINT64_C(7);
3936 op <<= 16;
3937 Value |= op;
3938 break;
3939 }
3940 case Hexagon::J4_tstbit0_fp0_jump_nt:
3941 case Hexagon::J4_tstbit0_fp0_jump_t:
3942 case Hexagon::J4_tstbit0_fp1_jump_nt:
3943 case Hexagon::J4_tstbit0_fp1_jump_t:
3944 case Hexagon::J4_tstbit0_tp0_jump_nt:
3945 case Hexagon::J4_tstbit0_tp0_jump_t:
3946 case Hexagon::J4_tstbit0_tp1_jump_nt:
3947 case Hexagon::J4_tstbit0_tp1_jump_t: {
3948 // op: Ii
3949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3950 Value |= (op & UINT64_C(1536)) << 11;
3951 Value |= (op & UINT64_C(508)) >> 1;
3952 // op: Rs16
3953 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3954 op &= UINT64_C(15);
3955 op <<= 16;
3956 Value |= op;
3957 break;
3958 }
3959 case Hexagon::S2_storerbnew_io: {
3960 // op: Ii
3961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3962 Value |= (op & UINT64_C(1536)) << 16;
3963 Value |= (op & UINT64_C(256)) << 5;
3964 Value |= (op & UINT64_C(255));
3965 // op: Rs32
3966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3967 op &= UINT64_C(31);
3968 op <<= 16;
3969 Value |= op;
3970 // op: Nt8
3971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3972 op &= UINT64_C(7);
3973 op <<= 8;
3974 Value |= op;
3975 break;
3976 }
3977 case Hexagon::S2_storerb_io: {
3978 // op: Ii
3979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
3980 Value |= (op & UINT64_C(1536)) << 16;
3981 Value |= (op & UINT64_C(256)) << 5;
3982 Value |= (op & UINT64_C(255));
3983 // op: Rs32
3984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
3985 op &= UINT64_C(31);
3986 op <<= 16;
3987 Value |= op;
3988 // op: Rt32
3989 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
3990 op &= UINT64_C(31);
3991 op <<= 8;
3992 Value |= op;
3993 break;
3994 }
3995 case Hexagon::J2_jumprgtez:
3996 case Hexagon::J2_jumprgtezpt:
3997 case Hexagon::J2_jumprltez:
3998 case Hexagon::J2_jumprltezpt:
3999 case Hexagon::J2_jumprnz:
4000 case Hexagon::J2_jumprnzpt:
4001 case Hexagon::J2_jumprz:
4002 case Hexagon::J2_jumprzpt: {
4003 // op: Ii
4004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4005 Value |= (op & UINT64_C(16384)) << 7;
4006 Value |= (op & UINT64_C(8192));
4007 Value |= (op & UINT64_C(8188)) >> 1;
4008 // op: Rs32
4009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4010 op &= UINT64_C(31);
4011 op <<= 16;
4012 Value |= op;
4013 break;
4014 }
4015 case Hexagon::L2_loadrigp:
4016 case Hexagon::PS_loadriabs: {
4017 // op: Ii
4018 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4019 Value |= (op & UINT64_C(196608)) << 9;
4020 Value |= (op & UINT64_C(63488)) << 5;
4021 Value |= (op & UINT64_C(2044)) << 3;
4022 // op: Rd32
4023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4024 op &= UINT64_C(31);
4025 Value |= op;
4026 break;
4027 }
4028 case Hexagon::S4_storerbnew_ur:
4029 case Hexagon::S4_storerhnew_ur:
4030 case Hexagon::S4_storerinew_ur: {
4031 // op: Ii
4032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4033 Value |= (op & UINT64_C(2)) << 12;
4034 Value |= (op & UINT64_C(1)) << 6;
4035 // op: II
4036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4037 op &= UINT64_C(63);
4038 Value |= op;
4039 // op: Ru32
4040 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4041 op &= UINT64_C(31);
4042 op <<= 16;
4043 Value |= op;
4044 // op: Nt8
4045 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4046 op &= UINT64_C(7);
4047 op <<= 8;
4048 Value |= op;
4049 break;
4050 }
4051 case Hexagon::S4_storerb_ur:
4052 case Hexagon::S4_storerf_ur:
4053 case Hexagon::S4_storerh_ur:
4054 case Hexagon::S4_storeri_ur: {
4055 // op: Ii
4056 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4057 Value |= (op & UINT64_C(2)) << 12;
4058 Value |= (op & UINT64_C(1)) << 6;
4059 // op: II
4060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4061 op &= UINT64_C(63);
4062 Value |= op;
4063 // op: Ru32
4064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4065 op &= UINT64_C(31);
4066 op <<= 16;
4067 Value |= op;
4068 // op: Rt32
4069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4070 op &= UINT64_C(31);
4071 op <<= 8;
4072 Value |= op;
4073 break;
4074 }
4075 case Hexagon::S4_storerd_ur: {
4076 // op: Ii
4077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4078 Value |= (op & UINT64_C(2)) << 12;
4079 Value |= (op & UINT64_C(1)) << 6;
4080 // op: II
4081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4082 op &= UINT64_C(63);
4083 Value |= op;
4084 // op: Ru32
4085 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4086 op &= UINT64_C(31);
4087 op <<= 16;
4088 Value |= op;
4089 // op: Rtt32
4090 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4091 op &= UINT64_C(31);
4092 op <<= 8;
4093 Value |= op;
4094 break;
4095 }
4096 case Hexagon::S4_addi_asl_ri:
4097 case Hexagon::S4_addi_lsr_ri:
4098 case Hexagon::S4_andi_asl_ri:
4099 case Hexagon::S4_andi_lsr_ri:
4100 case Hexagon::S4_ori_asl_ri:
4101 case Hexagon::S4_ori_lsr_ri:
4102 case Hexagon::S4_subi_asl_ri:
4103 case Hexagon::S4_subi_lsr_ri: {
4104 // op: Ii
4105 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4106 Value |= (op & UINT64_C(224)) << 16;
4107 Value |= (op & UINT64_C(16)) << 9;
4108 Value |= (op & UINT64_C(14)) << 4;
4109 Value |= (op & UINT64_C(1)) << 3;
4110 // op: II
4111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4112 op &= UINT64_C(31);
4113 op <<= 8;
4114 Value |= op;
4115 // op: Rx32
4116 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4117 op &= UINT64_C(31);
4118 op <<= 16;
4119 Value |= op;
4120 break;
4121 }
4122 case Hexagon::S2_storerhnew_io: {
4123 // op: Ii
4124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4125 Value |= (op & UINT64_C(3072)) << 15;
4126 Value |= (op & UINT64_C(512)) << 4;
4127 Value |= (op & UINT64_C(510)) >> 1;
4128 // op: Rs32
4129 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4130 op &= UINT64_C(31);
4131 op <<= 16;
4132 Value |= op;
4133 // op: Nt8
4134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4135 op &= UINT64_C(7);
4136 op <<= 8;
4137 Value |= op;
4138 break;
4139 }
4140 case Hexagon::S2_storerf_io:
4141 case Hexagon::S2_storerh_io: {
4142 // op: Ii
4143 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4144 Value |= (op & UINT64_C(3072)) << 15;
4145 Value |= (op & UINT64_C(512)) << 4;
4146 Value |= (op & UINT64_C(510)) >> 1;
4147 // op: Rs32
4148 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4149 op &= UINT64_C(31);
4150 op <<= 16;
4151 Value |= op;
4152 // op: Rt32
4153 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4154 op &= UINT64_C(31);
4155 op <<= 8;
4156 Value |= op;
4157 break;
4158 }
4159 case Hexagon::L2_loadrdgp:
4160 case Hexagon::PS_loadrdabs: {
4161 // op: Ii
4162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4163 Value |= (op & UINT64_C(393216)) << 8;
4164 Value |= (op & UINT64_C(126976)) << 4;
4165 Value |= (op & UINT64_C(4088)) << 2;
4166 // op: Rdd32
4167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4168 op &= UINT64_C(31);
4169 Value |= op;
4170 break;
4171 }
4172 case Hexagon::S4_pstorerbnewf_abs:
4173 case Hexagon::S4_pstorerbnewfnew_abs:
4174 case Hexagon::S4_pstorerbnewt_abs:
4175 case Hexagon::S4_pstorerbnewtnew_abs:
4176 case Hexagon::S4_pstorerhnewf_abs:
4177 case Hexagon::S4_pstorerhnewfnew_abs:
4178 case Hexagon::S4_pstorerhnewt_abs:
4179 case Hexagon::S4_pstorerhnewtnew_abs:
4180 case Hexagon::S4_pstorerinewf_abs:
4181 case Hexagon::S4_pstorerinewfnew_abs:
4182 case Hexagon::S4_pstorerinewt_abs:
4183 case Hexagon::S4_pstorerinewtnew_abs: {
4184 // op: Ii
4185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4186 Value |= (op & UINT64_C(48)) << 12;
4187 Value |= (op & UINT64_C(15)) << 3;
4188 // op: Pv4
4189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4190 op &= UINT64_C(3);
4191 Value |= op;
4192 // op: Nt8
4193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4194 op &= UINT64_C(7);
4195 op <<= 8;
4196 Value |= op;
4197 break;
4198 }
4199 case Hexagon::S4_pstorerbf_abs:
4200 case Hexagon::S4_pstorerbfnew_abs:
4201 case Hexagon::S4_pstorerbt_abs:
4202 case Hexagon::S4_pstorerbtnew_abs:
4203 case Hexagon::S4_pstorerff_abs:
4204 case Hexagon::S4_pstorerffnew_abs:
4205 case Hexagon::S4_pstorerft_abs:
4206 case Hexagon::S4_pstorerftnew_abs:
4207 case Hexagon::S4_pstorerhf_abs:
4208 case Hexagon::S4_pstorerhfnew_abs:
4209 case Hexagon::S4_pstorerht_abs:
4210 case Hexagon::S4_pstorerhtnew_abs:
4211 case Hexagon::S4_pstorerif_abs:
4212 case Hexagon::S4_pstorerifnew_abs:
4213 case Hexagon::S4_pstorerit_abs:
4214 case Hexagon::S4_pstoreritnew_abs: {
4215 // op: Ii
4216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4217 Value |= (op & UINT64_C(48)) << 12;
4218 Value |= (op & UINT64_C(15)) << 3;
4219 // op: Pv4
4220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4221 op &= UINT64_C(3);
4222 Value |= op;
4223 // op: Rt32
4224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4225 op &= UINT64_C(31);
4226 op <<= 8;
4227 Value |= op;
4228 break;
4229 }
4230 case Hexagon::S4_pstorerdf_abs:
4231 case Hexagon::S4_pstorerdfnew_abs:
4232 case Hexagon::S4_pstorerdt_abs:
4233 case Hexagon::S4_pstorerdtnew_abs: {
4234 // op: Ii
4235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4236 Value |= (op & UINT64_C(48)) << 12;
4237 Value |= (op & UINT64_C(15)) << 3;
4238 // op: Pv4
4239 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4240 op &= UINT64_C(3);
4241 Value |= op;
4242 // op: Rtt32
4243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4244 op &= UINT64_C(31);
4245 op <<= 8;
4246 Value |= op;
4247 break;
4248 }
4249 case Hexagon::M4_mpyri_addi: {
4250 // op: Ii
4251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4252 Value |= (op & UINT64_C(48)) << 17;
4253 Value |= (op & UINT64_C(8)) << 10;
4254 Value |= (op & UINT64_C(7)) << 5;
4255 // op: II
4256 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4257 Value |= (op & UINT64_C(32)) << 18;
4258 Value |= (op & UINT64_C(31));
4259 // op: Rs32
4260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4261 op &= UINT64_C(31);
4262 op <<= 16;
4263 Value |= op;
4264 // op: Rd32
4265 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4266 op &= UINT64_C(31);
4267 op <<= 8;
4268 Value |= op;
4269 break;
4270 }
4271 case Hexagon::M4_mpyrr_addi: {
4272 // op: Ii
4273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4274 Value |= (op & UINT64_C(48)) << 17;
4275 Value |= (op & UINT64_C(8)) << 10;
4276 Value |= (op & UINT64_C(7)) << 5;
4277 // op: Rs32
4278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4279 op &= UINT64_C(31);
4280 op <<= 16;
4281 Value |= op;
4282 // op: Rt32
4283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4284 op &= UINT64_C(31);
4285 op <<= 8;
4286 Value |= op;
4287 // op: Rd32
4288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4289 op &= UINT64_C(31);
4290 Value |= op;
4291 break;
4292 }
4293 case Hexagon::L2_loadrbgp:
4294 case Hexagon::L2_loadrubgp:
4295 case Hexagon::PS_loadrbabs:
4296 case Hexagon::PS_loadrubabs: {
4297 // op: Ii
4298 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4299 Value |= (op & UINT64_C(49152)) << 11;
4300 Value |= (op & UINT64_C(15872)) << 7;
4301 Value |= (op & UINT64_C(511)) << 5;
4302 // op: Rd32
4303 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4304 op &= UINT64_C(31);
4305 Value |= op;
4306 break;
4307 }
4308 case Hexagon::A2_tfrsi: {
4309 // op: Ii
4310 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4311 Value |= (op & UINT64_C(49152)) << 8;
4312 Value |= (op & UINT64_C(15872)) << 7;
4313 Value |= (op & UINT64_C(511)) << 5;
4314 // op: Rd32
4315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4316 op &= UINT64_C(31);
4317 Value |= op;
4318 break;
4319 }
4320 case Hexagon::F2_sfimm_n:
4321 case Hexagon::F2_sfimm_p: {
4322 // op: Ii
4323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4324 Value |= (op & UINT64_C(512)) << 12;
4325 Value |= (op & UINT64_C(511)) << 5;
4326 // op: Rd32
4327 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4328 op &= UINT64_C(31);
4329 Value |= op;
4330 break;
4331 }
4332 case Hexagon::F2_dfimm_n:
4333 case Hexagon::F2_dfimm_p: {
4334 // op: Ii
4335 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4336 Value |= (op & UINT64_C(512)) << 12;
4337 Value |= (op & UINT64_C(511)) << 5;
4338 // op: Rdd32
4339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4340 op &= UINT64_C(31);
4341 Value |= op;
4342 break;
4343 }
4344 case Hexagon::A2_subri: {
4345 // op: Ii
4346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4347 Value |= (op & UINT64_C(512)) << 12;
4348 Value |= (op & UINT64_C(511)) << 5;
4349 // op: Rs32
4350 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4351 op &= UINT64_C(31);
4352 op <<= 16;
4353 Value |= op;
4354 // op: Rd32
4355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4356 op &= UINT64_C(31);
4357 Value |= op;
4358 break;
4359 }
4360 case Hexagon::S2_storerinew_io: {
4361 // op: Ii
4362 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4363 Value |= (op & UINT64_C(6144)) << 14;
4364 Value |= (op & UINT64_C(1024)) << 3;
4365 Value |= (op & UINT64_C(1020)) >> 2;
4366 // op: Rs32
4367 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4368 op &= UINT64_C(31);
4369 op <<= 16;
4370 Value |= op;
4371 // op: Nt8
4372 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4373 op &= UINT64_C(7);
4374 op <<= 8;
4375 Value |= op;
4376 break;
4377 }
4378 case Hexagon::S2_storeri_io: {
4379 // op: Ii
4380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4381 Value |= (op & UINT64_C(6144)) << 14;
4382 Value |= (op & UINT64_C(1024)) << 3;
4383 Value |= (op & UINT64_C(1020)) >> 2;
4384 // op: Rs32
4385 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4386 op &= UINT64_C(31);
4387 op <<= 16;
4388 Value |= op;
4389 // op: Rt32
4390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4391 op &= UINT64_C(31);
4392 op <<= 8;
4393 Value |= op;
4394 break;
4395 }
4396 case Hexagon::S4_lsli: {
4397 // op: Ii
4398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4399 Value |= (op & UINT64_C(62)) << 15;
4400 Value |= (op & UINT64_C(1)) << 5;
4401 // op: Rt32
4402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4403 op &= UINT64_C(31);
4404 op <<= 8;
4405 Value |= op;
4406 // op: Rd32
4407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4408 op &= UINT64_C(31);
4409 Value |= op;
4410 break;
4411 }
4412 case Hexagon::V6_vS32b_srls_ai:
4413 case Hexagon::V6_zLd_ai: {
4414 // op: Ii
4415 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4416 Value |= (op & UINT64_C(8)) << 10;
4417 Value |= (op & UINT64_C(7)) << 8;
4418 // op: Rt32
4419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4420 op &= UINT64_C(31);
4421 op <<= 16;
4422 Value |= op;
4423 break;
4424 }
4425 case Hexagon::V6_vS32b_new_ai:
4426 case Hexagon::V6_vS32b_nt_new_ai: {
4427 // op: Ii
4428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4429 Value |= (op & UINT64_C(8)) << 10;
4430 Value |= (op & UINT64_C(7)) << 8;
4431 // op: Rt32
4432 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4433 op &= UINT64_C(31);
4434 op <<= 16;
4435 Value |= op;
4436 // op: Os8
4437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4438 op &= UINT64_C(7);
4439 Value |= op;
4440 break;
4441 }
4442 case Hexagon::V6_vS32Ub_ai:
4443 case Hexagon::V6_vS32b_ai:
4444 case Hexagon::V6_vS32b_nt_ai: {
4445 // op: Ii
4446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4447 Value |= (op & UINT64_C(8)) << 10;
4448 Value |= (op & UINT64_C(7)) << 8;
4449 // op: Rt32
4450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4451 op &= UINT64_C(31);
4452 op <<= 16;
4453 Value |= op;
4454 // op: Vs32
4455 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4456 op &= UINT64_C(31);
4457 Value |= op;
4458 break;
4459 }
4460 case Hexagon::L2_loadrhgp:
4461 case Hexagon::L2_loadruhgp:
4462 case Hexagon::PS_loadrhabs:
4463 case Hexagon::PS_loadruhabs: {
4464 // op: Ii
4465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4466 Value |= (op & UINT64_C(98304)) << 10;
4467 Value |= (op & UINT64_C(31744)) << 6;
4468 Value |= (op & UINT64_C(1022)) << 4;
4469 // op: Rd32
4470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4471 op &= UINT64_C(31);
4472 Value |= op;
4473 break;
4474 }
4475 case Hexagon::J2_callf:
4476 case Hexagon::J2_callt:
4477 case Hexagon::J2_jumpf:
4478 case Hexagon::J2_jumpfnew:
4479 case Hexagon::J2_jumpfnewpt:
4480 case Hexagon::J2_jumpfpt:
4481 case Hexagon::J2_jumpt:
4482 case Hexagon::J2_jumptnew:
4483 case Hexagon::J2_jumptnewpt:
4484 case Hexagon::J2_jumptpt: {
4485 // op: Ii
4486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4487 Value |= (op & UINT64_C(98304)) << 7;
4488 Value |= (op & UINT64_C(31744)) << 6;
4489 Value |= (op & UINT64_C(512)) << 4;
4490 Value |= (op & UINT64_C(508)) >> 1;
4491 // op: Pu4
4492 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4493 op &= UINT64_C(3);
4494 op <<= 8;
4495 Value |= op;
4496 break;
4497 }
4498 case Hexagon::V6_vwhist128qm: {
4499 // op: Ii
4500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4501 op &= UINT64_C(1);
4502 op <<= 8;
4503 Value |= op;
4504 // op: Qv4
4505 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4506 op &= UINT64_C(3);
4507 op <<= 22;
4508 Value |= op;
4509 break;
4510 }
4511 case Hexagon::SL2_loadri_sp: {
4512 // op: Ii
4513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4514 op &= UINT64_C(124);
4515 op <<= 2;
4516 Value |= op;
4517 // op: Rd16
4518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4519 op &= UINT64_C(15);
4520 Value |= op;
4521 break;
4522 }
4523 case Hexagon::S4_storeirh_io: {
4524 // op: Ii
4525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4526 op &= UINT64_C(126);
4527 op <<= 6;
4528 Value |= op;
4529 // op: II
4530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4531 Value |= (op & UINT64_C(128)) << 6;
4532 Value |= (op & UINT64_C(127));
4533 // op: Rs32
4534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4535 op &= UINT64_C(31);
4536 op <<= 16;
4537 Value |= op;
4538 break;
4539 }
4540 case Hexagon::L4_iadd_memoph_io:
4541 case Hexagon::L4_iand_memoph_io:
4542 case Hexagon::L4_ior_memoph_io:
4543 case Hexagon::L4_isub_memoph_io: {
4544 // op: Ii
4545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4546 op &= UINT64_C(126);
4547 op <<= 6;
4548 Value |= op;
4549 // op: II
4550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4551 op &= UINT64_C(31);
4552 Value |= op;
4553 // op: Rs32
4554 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4555 op &= UINT64_C(31);
4556 op <<= 16;
4557 Value |= op;
4558 break;
4559 }
4560 case Hexagon::L4_add_memoph_io:
4561 case Hexagon::L4_and_memoph_io:
4562 case Hexagon::L4_or_memoph_io:
4563 case Hexagon::L4_sub_memoph_io: {
4564 // op: Ii
4565 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4566 op &= UINT64_C(126);
4567 op <<= 6;
4568 Value |= op;
4569 // op: Rs32
4570 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4571 op &= UINT64_C(31);
4572 op <<= 16;
4573 Value |= op;
4574 // op: Rt32
4575 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4576 op &= UINT64_C(31);
4577 Value |= op;
4578 break;
4579 }
4580 case Hexagon::SS2_storeh_io: {
4581 // op: Ii
4582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4583 op &= UINT64_C(14);
4584 op <<= 7;
4585 Value |= op;
4586 // op: Rs16
4587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4588 op &= UINT64_C(15);
4589 op <<= 4;
4590 Value |= op;
4591 // op: Rt16
4592 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4593 op &= UINT64_C(15);
4594 Value |= op;
4595 break;
4596 }
4597 case Hexagon::SS2_storebi0:
4598 case Hexagon::SS2_storebi1: {
4599 // op: Ii
4600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4601 op &= UINT64_C(15);
4602 Value |= op;
4603 // op: Rs16
4604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4605 op &= UINT64_C(15);
4606 op <<= 4;
4607 Value |= op;
4608 break;
4609 }
4610 case Hexagon::SS1_storeb_io: {
4611 // op: Ii
4612 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4613 op &= UINT64_C(15);
4614 op <<= 8;
4615 Value |= op;
4616 // op: Rs16
4617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4618 op &= UINT64_C(15);
4619 op <<= 4;
4620 Value |= op;
4621 // op: Rt16
4622 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4623 op &= UINT64_C(15);
4624 Value |= op;
4625 break;
4626 }
4627 case Hexagon::Y2_dcfetchbo: {
4628 // op: Ii
4629 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4630 op &= UINT64_C(16376);
4631 op >>= 3;
4632 Value |= op;
4633 // op: Rs32
4634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4635 op &= UINT64_C(31);
4636 op <<= 16;
4637 Value |= op;
4638 break;
4639 }
4640 case Hexagon::SL2_loadrd_sp: {
4641 // op: Ii
4642 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4643 op &= UINT64_C(248);
4644 Value |= op;
4645 // op: Rdd8
4646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4647 op &= UINT64_C(7);
4648 Value |= op;
4649 break;
4650 }
4651 case Hexagon::SA1_addsp: {
4652 // op: Ii
4653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4654 op &= UINT64_C(252);
4655 op <<= 2;
4656 Value |= op;
4657 // op: Rd16
4658 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4659 op &= UINT64_C(15);
4660 Value |= op;
4661 break;
4662 }
4663 case Hexagon::S4_storeiri_io: {
4664 // op: Ii
4665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4666 op &= UINT64_C(252);
4667 op <<= 5;
4668 Value |= op;
4669 // op: II
4670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4671 Value |= (op & UINT64_C(128)) << 6;
4672 Value |= (op & UINT64_C(127));
4673 // op: Rs32
4674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4675 op &= UINT64_C(31);
4676 op <<= 16;
4677 Value |= op;
4678 break;
4679 }
4680 case Hexagon::L4_iadd_memopw_io:
4681 case Hexagon::L4_iand_memopw_io:
4682 case Hexagon::L4_ior_memopw_io:
4683 case Hexagon::L4_isub_memopw_io: {
4684 // op: Ii
4685 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4686 op &= UINT64_C(252);
4687 op <<= 5;
4688 Value |= op;
4689 // op: II
4690 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4691 op &= UINT64_C(31);
4692 Value |= op;
4693 // op: Rs32
4694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4695 op &= UINT64_C(31);
4696 op <<= 16;
4697 Value |= op;
4698 break;
4699 }
4700 case Hexagon::L4_add_memopw_io:
4701 case Hexagon::L4_and_memopw_io:
4702 case Hexagon::L4_or_memopw_io:
4703 case Hexagon::L4_sub_memopw_io: {
4704 // op: Ii
4705 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4706 op &= UINT64_C(252);
4707 op <<= 5;
4708 Value |= op;
4709 // op: Rs32
4710 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4711 op &= UINT64_C(31);
4712 op <<= 16;
4713 Value |= op;
4714 // op: Rt32
4715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4716 op &= UINT64_C(31);
4717 Value |= op;
4718 break;
4719 }
4720 case Hexagon::A2_combineii: {
4721 // op: Ii
4722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4723 op &= UINT64_C(255);
4724 op <<= 5;
4725 Value |= op;
4726 // op: II
4727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4728 Value |= (op & UINT64_C(254)) << 15;
4729 Value |= (op & UINT64_C(1)) << 13;
4730 // op: Rdd32
4731 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4732 op &= UINT64_C(31);
4733 Value |= op;
4734 break;
4735 }
4736 case Hexagon::A4_combineii: {
4737 // op: Ii
4738 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4739 op &= UINT64_C(255);
4740 op <<= 5;
4741 Value |= op;
4742 // op: II
4743 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4744 Value |= (op & UINT64_C(62)) << 15;
4745 Value |= (op & UINT64_C(1)) << 13;
4746 // op: Rdd32
4747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4748 op &= UINT64_C(31);
4749 Value |= op;
4750 break;
4751 }
4752 case Hexagon::A4_combineir: {
4753 // op: Ii
4754 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4755 op &= UINT64_C(255);
4756 op <<= 5;
4757 Value |= op;
4758 // op: Rs32
4759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4760 op &= UINT64_C(31);
4761 op <<= 16;
4762 Value |= op;
4763 // op: Rdd32
4764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4765 op &= UINT64_C(31);
4766 Value |= op;
4767 break;
4768 }
4769 case Hexagon::SA1_cmpeqi: {
4770 // op: Ii
4771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4772 op &= UINT64_C(3);
4773 Value |= op;
4774 // op: Rs16
4775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4776 op &= UINT64_C(15);
4777 op <<= 4;
4778 Value |= op;
4779 break;
4780 }
4781 case Hexagon::SA1_combine0i:
4782 case Hexagon::SA1_combine1i:
4783 case Hexagon::SA1_combine2i:
4784 case Hexagon::SA1_combine3i: {
4785 // op: Ii
4786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4787 op &= UINT64_C(3);
4788 op <<= 5;
4789 Value |= op;
4790 // op: Rdd8
4791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4792 op &= UINT64_C(7);
4793 Value |= op;
4794 break;
4795 }
4796 case Hexagon::S2_mask: {
4797 // op: Ii
4798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4799 op &= UINT64_C(31);
4800 op <<= 8;
4801 Value |= op;
4802 // op: II
4803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4804 Value |= (op & UINT64_C(24)) << 18;
4805 Value |= (op & UINT64_C(7)) << 5;
4806 // op: Rd32
4807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4808 op &= UINT64_C(31);
4809 Value |= op;
4810 break;
4811 }
4812 case Hexagon::SS1_storew_io: {
4813 // op: Ii
4814 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4815 op &= UINT64_C(60);
4816 op <<= 6;
4817 Value |= op;
4818 // op: Rs16
4819 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4820 op &= UINT64_C(15);
4821 op <<= 4;
4822 Value |= op;
4823 // op: Rt16
4824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4825 op &= UINT64_C(15);
4826 Value |= op;
4827 break;
4828 }
4829 case Hexagon::SS2_storewi0:
4830 case Hexagon::SS2_storewi1: {
4831 // op: Ii
4832 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4833 op &= UINT64_C(60);
4834 op >>= 2;
4835 Value |= op;
4836 // op: Rs16
4837 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4838 op &= UINT64_C(15);
4839 op <<= 4;
4840 Value |= op;
4841 break;
4842 }
4843 case Hexagon::SA1_seti: {
4844 // op: Ii
4845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4846 op &= UINT64_C(63);
4847 op <<= 4;
4848 Value |= op;
4849 // op: Rd16
4850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4851 op &= UINT64_C(15);
4852 Value |= op;
4853 break;
4854 }
4855 case Hexagon::S4_storeirb_io: {
4856 // op: Ii
4857 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4858 op &= UINT64_C(63);
4859 op <<= 7;
4860 Value |= op;
4861 // op: II
4862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4863 Value |= (op & UINT64_C(128)) << 6;
4864 Value |= (op & UINT64_C(127));
4865 // op: Rs32
4866 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4867 op &= UINT64_C(31);
4868 op <<= 16;
4869 Value |= op;
4870 break;
4871 }
4872 case Hexagon::L4_iadd_memopb_io:
4873 case Hexagon::L4_iand_memopb_io:
4874 case Hexagon::L4_ior_memopb_io:
4875 case Hexagon::L4_isub_memopb_io: {
4876 // op: Ii
4877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4878 op &= UINT64_C(63);
4879 op <<= 7;
4880 Value |= op;
4881 // op: II
4882 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4883 op &= UINT64_C(31);
4884 Value |= op;
4885 // op: Rs32
4886 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4887 op &= UINT64_C(31);
4888 op <<= 16;
4889 Value |= op;
4890 break;
4891 }
4892 case Hexagon::C4_addipc: {
4893 // op: Ii
4894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4895 op &= UINT64_C(63);
4896 op <<= 7;
4897 Value |= op;
4898 // op: Rd32
4899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4900 op &= UINT64_C(31);
4901 Value |= op;
4902 break;
4903 }
4904 case Hexagon::L4_add_memopb_io:
4905 case Hexagon::L4_and_memopb_io:
4906 case Hexagon::L4_or_memopb_io:
4907 case Hexagon::L4_sub_memopb_io: {
4908 // op: Ii
4909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4910 op &= UINT64_C(63);
4911 op <<= 7;
4912 Value |= op;
4913 // op: Rs32
4914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4915 op &= UINT64_C(31);
4916 op <<= 16;
4917 Value |= op;
4918 // op: Rt32
4919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4920 op &= UINT64_C(31);
4921 Value |= op;
4922 break;
4923 }
4924 case Hexagon::L2_loadrd_io: {
4925 // op: Ii
4926 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4927 Value |= (op & UINT64_C(12288)) << 13;
4928 Value |= (op & UINT64_C(4088)) << 2;
4929 // op: Rs32
4930 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4931 op &= UINT64_C(31);
4932 op <<= 16;
4933 Value |= op;
4934 // op: Rdd32
4935 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4936 op &= UINT64_C(31);
4937 Value |= op;
4938 break;
4939 }
4940 case Hexagon::S2_pstorerinewf_io:
4941 case Hexagon::S2_pstorerinewt_io:
4942 case Hexagon::S4_pstorerinewfnew_io:
4943 case Hexagon::S4_pstorerinewtnew_io: {
4944 // op: Ii
4945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4946 Value |= (op & UINT64_C(128)) << 6;
4947 Value |= (op & UINT64_C(124)) << 1;
4948 // op: Pv4
4949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4950 op &= UINT64_C(3);
4951 Value |= op;
4952 // op: Rs32
4953 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4954 op &= UINT64_C(31);
4955 op <<= 16;
4956 Value |= op;
4957 // op: Nt8
4958 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4959 op &= UINT64_C(7);
4960 op <<= 8;
4961 Value |= op;
4962 break;
4963 }
4964 case Hexagon::S2_pstorerif_io:
4965 case Hexagon::S2_pstorerit_io:
4966 case Hexagon::S4_pstorerifnew_io:
4967 case Hexagon::S4_pstoreritnew_io: {
4968 // op: Ii
4969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4970 Value |= (op & UINT64_C(128)) << 6;
4971 Value |= (op & UINT64_C(124)) << 1;
4972 // op: Pv4
4973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
4974 op &= UINT64_C(3);
4975 Value |= op;
4976 // op: Rs32
4977 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
4978 op &= UINT64_C(31);
4979 op <<= 16;
4980 Value |= op;
4981 // op: Rt32
4982 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
4983 op &= UINT64_C(31);
4984 op <<= 8;
4985 Value |= op;
4986 break;
4987 }
4988 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
4989 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
4990 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
4991 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
4992 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
4993 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
4994 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
4995 case Hexagon::J4_cmpgtn1_t_jumpnv_t: {
4996 // op: Ii
4997 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
4998 Value |= (op & UINT64_C(1536)) << 11;
4999 Value |= (op & UINT64_C(508)) >> 1;
5000 // op: Ns8
5001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5002 op &= UINT64_C(7);
5003 op <<= 16;
5004 Value |= op;
5005 break;
5006 }
5007 case Hexagon::J4_cmpeq_f_jumpnv_nt:
5008 case Hexagon::J4_cmpeq_f_jumpnv_t:
5009 case Hexagon::J4_cmpeq_t_jumpnv_nt:
5010 case Hexagon::J4_cmpeq_t_jumpnv_t:
5011 case Hexagon::J4_cmpgt_f_jumpnv_nt:
5012 case Hexagon::J4_cmpgt_f_jumpnv_t:
5013 case Hexagon::J4_cmpgt_t_jumpnv_nt:
5014 case Hexagon::J4_cmpgt_t_jumpnv_t:
5015 case Hexagon::J4_cmpgtu_f_jumpnv_nt:
5016 case Hexagon::J4_cmpgtu_f_jumpnv_t:
5017 case Hexagon::J4_cmpgtu_t_jumpnv_nt:
5018 case Hexagon::J4_cmpgtu_t_jumpnv_t: {
5019 // op: Ii
5020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5021 Value |= (op & UINT64_C(1536)) << 11;
5022 Value |= (op & UINT64_C(508)) >> 1;
5023 // op: Ns8
5024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5025 op &= UINT64_C(7);
5026 op <<= 16;
5027 Value |= op;
5028 // op: Rt32
5029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5030 op &= UINT64_C(31);
5031 op <<= 8;
5032 Value |= op;
5033 break;
5034 }
5035 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
5036 case Hexagon::J4_cmpeqn1_fp0_jump_t:
5037 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
5038 case Hexagon::J4_cmpeqn1_fp1_jump_t:
5039 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
5040 case Hexagon::J4_cmpeqn1_tp0_jump_t:
5041 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
5042 case Hexagon::J4_cmpeqn1_tp1_jump_t:
5043 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
5044 case Hexagon::J4_cmpgtn1_fp0_jump_t:
5045 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
5046 case Hexagon::J4_cmpgtn1_fp1_jump_t:
5047 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
5048 case Hexagon::J4_cmpgtn1_tp0_jump_t:
5049 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
5050 case Hexagon::J4_cmpgtn1_tp1_jump_t: {
5051 // op: Ii
5052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5053 Value |= (op & UINT64_C(1536)) << 11;
5054 Value |= (op & UINT64_C(508)) >> 1;
5055 // op: Rs16
5056 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5057 op &= UINT64_C(15);
5058 op <<= 16;
5059 Value |= op;
5060 break;
5061 }
5062 case Hexagon::J4_cmpeq_fp0_jump_nt:
5063 case Hexagon::J4_cmpeq_fp0_jump_t:
5064 case Hexagon::J4_cmpeq_fp1_jump_nt:
5065 case Hexagon::J4_cmpeq_fp1_jump_t:
5066 case Hexagon::J4_cmpeq_tp0_jump_nt:
5067 case Hexagon::J4_cmpeq_tp0_jump_t:
5068 case Hexagon::J4_cmpeq_tp1_jump_nt:
5069 case Hexagon::J4_cmpeq_tp1_jump_t:
5070 case Hexagon::J4_cmpgt_fp0_jump_nt:
5071 case Hexagon::J4_cmpgt_fp0_jump_t:
5072 case Hexagon::J4_cmpgt_fp1_jump_nt:
5073 case Hexagon::J4_cmpgt_fp1_jump_t:
5074 case Hexagon::J4_cmpgt_tp0_jump_nt:
5075 case Hexagon::J4_cmpgt_tp0_jump_t:
5076 case Hexagon::J4_cmpgt_tp1_jump_nt:
5077 case Hexagon::J4_cmpgt_tp1_jump_t:
5078 case Hexagon::J4_cmpgtu_fp0_jump_nt:
5079 case Hexagon::J4_cmpgtu_fp0_jump_t:
5080 case Hexagon::J4_cmpgtu_fp1_jump_nt:
5081 case Hexagon::J4_cmpgtu_fp1_jump_t:
5082 case Hexagon::J4_cmpgtu_tp0_jump_nt:
5083 case Hexagon::J4_cmpgtu_tp0_jump_t:
5084 case Hexagon::J4_cmpgtu_tp1_jump_nt:
5085 case Hexagon::J4_cmpgtu_tp1_jump_t: {
5086 // op: Ii
5087 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5088 Value |= (op & UINT64_C(1536)) << 11;
5089 Value |= (op & UINT64_C(508)) >> 1;
5090 // op: Rs16
5091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5092 op &= UINT64_C(15);
5093 op <<= 16;
5094 Value |= op;
5095 // op: Rt16
5096 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5097 op &= UINT64_C(15);
5098 op <<= 8;
5099 Value |= op;
5100 break;
5101 }
5102 case Hexagon::J4_jumpsetr: {
5103 // op: Ii
5104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5105 Value |= (op & UINT64_C(1536)) << 11;
5106 Value |= (op & UINT64_C(508)) >> 1;
5107 // op: Rs16
5108 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5109 op &= UINT64_C(15);
5110 op <<= 16;
5111 Value |= op;
5112 // op: Rd16
5113 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5114 op &= UINT64_C(15);
5115 op <<= 8;
5116 Value |= op;
5117 break;
5118 }
5119 case Hexagon::J4_cmplt_f_jumpnv_nt:
5120 case Hexagon::J4_cmplt_f_jumpnv_t:
5121 case Hexagon::J4_cmplt_t_jumpnv_nt:
5122 case Hexagon::J4_cmplt_t_jumpnv_t:
5123 case Hexagon::J4_cmpltu_f_jumpnv_nt:
5124 case Hexagon::J4_cmpltu_f_jumpnv_t:
5125 case Hexagon::J4_cmpltu_t_jumpnv_nt:
5126 case Hexagon::J4_cmpltu_t_jumpnv_t: {
5127 // op: Ii
5128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5129 Value |= (op & UINT64_C(1536)) << 11;
5130 Value |= (op & UINT64_C(508)) >> 1;
5131 // op: Rt32
5132 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5133 op &= UINT64_C(31);
5134 op <<= 8;
5135 Value |= op;
5136 // op: Ns8
5137 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5138 op &= UINT64_C(7);
5139 op <<= 16;
5140 Value |= op;
5141 break;
5142 }
5143 case Hexagon::L2_loadrb_io:
5144 case Hexagon::L2_loadrub_io: {
5145 // op: Ii
5146 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5147 Value |= (op & UINT64_C(1536)) << 16;
5148 Value |= (op & UINT64_C(511)) << 5;
5149 // op: Rs32
5150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5151 op &= UINT64_C(31);
5152 op <<= 16;
5153 Value |= op;
5154 // op: Rd32
5155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5156 op &= UINT64_C(31);
5157 Value |= op;
5158 break;
5159 }
5160 case Hexagon::M4_mpyri_addr_u2: {
5161 // op: Ii
5162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5163 Value |= (op & UINT64_C(192)) << 15;
5164 Value |= (op & UINT64_C(32)) << 8;
5165 Value |= (op & UINT64_C(28)) << 3;
5166 // op: Ru32
5167 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5168 op &= UINT64_C(31);
5169 Value |= op;
5170 // op: Rs32
5171 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5172 op &= UINT64_C(31);
5173 op <<= 16;
5174 Value |= op;
5175 // op: Rd32
5176 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5177 op &= UINT64_C(31);
5178 op <<= 8;
5179 Value |= op;
5180 break;
5181 }
5182 case Hexagon::L4_loadbsw2_ur:
5183 case Hexagon::L4_loadbzw2_ur:
5184 case Hexagon::L4_loadrb_ur:
5185 case Hexagon::L4_loadrh_ur:
5186 case Hexagon::L4_loadri_ur:
5187 case Hexagon::L4_loadrub_ur:
5188 case Hexagon::L4_loadruh_ur: {
5189 // op: Ii
5190 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5191 Value |= (op & UINT64_C(2)) << 12;
5192 Value |= (op & UINT64_C(1)) << 7;
5193 // op: II
5194 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5195 Value |= (op & UINT64_C(60)) << 6;
5196 Value |= (op & UINT64_C(3)) << 5;
5197 // op: Rt32
5198 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5199 op &= UINT64_C(31);
5200 op <<= 16;
5201 Value |= op;
5202 // op: Rd32
5203 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5204 op &= UINT64_C(31);
5205 Value |= op;
5206 break;
5207 }
5208 case Hexagon::L4_loadbsw4_ur:
5209 case Hexagon::L4_loadbzw4_ur:
5210 case Hexagon::L4_loadrd_ur: {
5211 // op: Ii
5212 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5213 Value |= (op & UINT64_C(2)) << 12;
5214 Value |= (op & UINT64_C(1)) << 7;
5215 // op: II
5216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5217 Value |= (op & UINT64_C(60)) << 6;
5218 Value |= (op & UINT64_C(3)) << 5;
5219 // op: Rt32
5220 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5221 op &= UINT64_C(31);
5222 op <<= 16;
5223 Value |= op;
5224 // op: Rdd32
5225 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5226 op &= UINT64_C(31);
5227 Value |= op;
5228 break;
5229 }
5230 case Hexagon::S4_storerbnew_rr:
5231 case Hexagon::S4_storerhnew_rr:
5232 case Hexagon::S4_storerinew_rr: {
5233 // op: Ii
5234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5235 Value |= (op & UINT64_C(2)) << 12;
5236 Value |= (op & UINT64_C(1)) << 7;
5237 // op: Rs32
5238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5239 op &= UINT64_C(31);
5240 op <<= 16;
5241 Value |= op;
5242 // op: Ru32
5243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5244 op &= UINT64_C(31);
5245 op <<= 8;
5246 Value |= op;
5247 // op: Nt8
5248 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5249 op &= UINT64_C(7);
5250 Value |= op;
5251 break;
5252 }
5253 case Hexagon::S4_storerb_rr:
5254 case Hexagon::S4_storerf_rr:
5255 case Hexagon::S4_storerh_rr:
5256 case Hexagon::S4_storeri_rr: {
5257 // op: Ii
5258 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5259 Value |= (op & UINT64_C(2)) << 12;
5260 Value |= (op & UINT64_C(1)) << 7;
5261 // op: Rs32
5262 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5263 op &= UINT64_C(31);
5264 op <<= 16;
5265 Value |= op;
5266 // op: Ru32
5267 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5268 op &= UINT64_C(31);
5269 op <<= 8;
5270 Value |= op;
5271 // op: Rt32
5272 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5273 op &= UINT64_C(31);
5274 Value |= op;
5275 break;
5276 }
5277 case Hexagon::S4_storerd_rr: {
5278 // op: Ii
5279 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5280 Value |= (op & UINT64_C(2)) << 12;
5281 Value |= (op & UINT64_C(1)) << 7;
5282 // op: Rs32
5283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5284 op &= UINT64_C(31);
5285 op <<= 16;
5286 Value |= op;
5287 // op: Ru32
5288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5289 op &= UINT64_C(31);
5290 op <<= 8;
5291 Value |= op;
5292 // op: Rtt32
5293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5294 op &= UINT64_C(31);
5295 Value |= op;
5296 break;
5297 }
5298 case Hexagon::J2_trap1: {
5299 // op: Ii
5300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5301 Value |= (op & UINT64_C(248)) << 5;
5302 Value |= (op & UINT64_C(7)) << 2;
5303 // op: Rx32
5304 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5305 op &= UINT64_C(31);
5306 op <<= 16;
5307 Value |= op;
5308 break;
5309 }
5310 case Hexagon::S2_pstorerdf_io:
5311 case Hexagon::S2_pstorerdt_io:
5312 case Hexagon::S4_pstorerdfnew_io:
5313 case Hexagon::S4_pstorerdtnew_io: {
5314 // op: Ii
5315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5316 Value |= (op & UINT64_C(256)) << 5;
5317 Value |= (op & UINT64_C(248));
5318 // op: Pv4
5319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5320 op &= UINT64_C(3);
5321 Value |= op;
5322 // op: Rs32
5323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5324 op &= UINT64_C(31);
5325 op <<= 16;
5326 Value |= op;
5327 // op: Rtt32
5328 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5329 op &= UINT64_C(31);
5330 op <<= 8;
5331 Value |= op;
5332 break;
5333 }
5334 case Hexagon::L2_loadbsw2_io:
5335 case Hexagon::L2_loadbzw2_io:
5336 case Hexagon::L2_loadrh_io:
5337 case Hexagon::L2_loadruh_io: {
5338 // op: Ii
5339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5340 Value |= (op & UINT64_C(3072)) << 15;
5341 Value |= (op & UINT64_C(1022)) << 4;
5342 // op: Rs32
5343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5344 op &= UINT64_C(31);
5345 op <<= 16;
5346 Value |= op;
5347 // op: Rd32
5348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5349 op &= UINT64_C(31);
5350 Value |= op;
5351 break;
5352 }
5353 case Hexagon::S2_pstorerbnewf_io:
5354 case Hexagon::S2_pstorerbnewt_io:
5355 case Hexagon::S4_pstorerbnewfnew_io:
5356 case Hexagon::S4_pstorerbnewtnew_io: {
5357 // op: Ii
5358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5359 Value |= (op & UINT64_C(32)) << 8;
5360 Value |= (op & UINT64_C(31)) << 3;
5361 // op: Pv4
5362 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5363 op &= UINT64_C(3);
5364 Value |= op;
5365 // op: Rs32
5366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5367 op &= UINT64_C(31);
5368 op <<= 16;
5369 Value |= op;
5370 // op: Nt8
5371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5372 op &= UINT64_C(7);
5373 op <<= 8;
5374 Value |= op;
5375 break;
5376 }
5377 case Hexagon::S2_pstorerbf_io:
5378 case Hexagon::S2_pstorerbt_io:
5379 case Hexagon::S4_pstorerbfnew_io:
5380 case Hexagon::S4_pstorerbtnew_io: {
5381 // op: Ii
5382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5383 Value |= (op & UINT64_C(32)) << 8;
5384 Value |= (op & UINT64_C(31)) << 3;
5385 // op: Pv4
5386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5387 op &= UINT64_C(3);
5388 Value |= op;
5389 // op: Rs32
5390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5391 op &= UINT64_C(31);
5392 op <<= 16;
5393 Value |= op;
5394 // op: Rt32
5395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5396 op &= UINT64_C(31);
5397 op <<= 8;
5398 Value |= op;
5399 break;
5400 }
5401 case Hexagon::C2_cmoveif:
5402 case Hexagon::C2_cmoveit:
5403 case Hexagon::C2_cmovenewif:
5404 case Hexagon::C2_cmovenewit: {
5405 // op: Ii
5406 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5407 Value |= (op & UINT64_C(3840)) << 8;
5408 Value |= (op & UINT64_C(255)) << 5;
5409 // op: Pu4
5410 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5411 op &= UINT64_C(3);
5412 op <<= 21;
5413 Value |= op;
5414 // op: Rd32
5415 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5416 op &= UINT64_C(31);
5417 Value |= op;
5418 break;
5419 }
5420 case Hexagon::S4_subaddi: {
5421 // op: Ii
5422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5423 Value |= (op & UINT64_C(48)) << 17;
5424 Value |= (op & UINT64_C(8)) << 10;
5425 Value |= (op & UINT64_C(7)) << 5;
5426 // op: Rs32
5427 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5428 op &= UINT64_C(31);
5429 op <<= 16;
5430 Value |= op;
5431 // op: Ru32
5432 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5433 op &= UINT64_C(31);
5434 Value |= op;
5435 // op: Rd32
5436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5437 op &= UINT64_C(31);
5438 op <<= 8;
5439 Value |= op;
5440 break;
5441 }
5442 case Hexagon::A2_tfrih:
5443 case Hexagon::A2_tfril: {
5444 // op: Ii
5445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5446 Value |= (op & UINT64_C(49152)) << 8;
5447 Value |= (op & UINT64_C(16383));
5448 // op: Rx32
5449 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5450 op &= UINT64_C(31);
5451 op <<= 16;
5452 Value |= op;
5453 break;
5454 }
5455 case Hexagon::C2_cmpeqi:
5456 case Hexagon::C2_cmpgti:
5457 case Hexagon::C4_cmpltei:
5458 case Hexagon::C4_cmpneqi: {
5459 // op: Ii
5460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5461 Value |= (op & UINT64_C(512)) << 12;
5462 Value |= (op & UINT64_C(511)) << 5;
5463 // op: Rs32
5464 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5465 op &= UINT64_C(31);
5466 op <<= 16;
5467 Value |= op;
5468 // op: Pd4
5469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5470 op &= UINT64_C(3);
5471 Value |= op;
5472 break;
5473 }
5474 case Hexagon::A2_andir:
5475 case Hexagon::A2_orir: {
5476 // op: Ii
5477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5478 Value |= (op & UINT64_C(512)) << 12;
5479 Value |= (op & UINT64_C(511)) << 5;
5480 // op: Rs32
5481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5482 op &= UINT64_C(31);
5483 op <<= 16;
5484 Value |= op;
5485 // op: Rd32
5486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5487 op &= UINT64_C(31);
5488 Value |= op;
5489 break;
5490 }
5491 case Hexagon::L2_loadri_io: {
5492 // op: Ii
5493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5494 Value |= (op & UINT64_C(6144)) << 14;
5495 Value |= (op & UINT64_C(2044)) << 3;
5496 // op: Rs32
5497 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5498 op &= UINT64_C(31);
5499 op <<= 16;
5500 Value |= op;
5501 // op: Rd32
5502 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5503 op &= UINT64_C(31);
5504 Value |= op;
5505 break;
5506 }
5507 case Hexagon::L2_loadbsw4_io:
5508 case Hexagon::L2_loadbzw4_io: {
5509 // op: Ii
5510 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5511 Value |= (op & UINT64_C(6144)) << 14;
5512 Value |= (op & UINT64_C(2044)) << 3;
5513 // op: Rs32
5514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5515 op &= UINT64_C(31);
5516 op <<= 16;
5517 Value |= op;
5518 // op: Rdd32
5519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5520 op &= UINT64_C(31);
5521 Value |= op;
5522 break;
5523 }
5524 case Hexagon::L4_ploadrbf_abs:
5525 case Hexagon::L4_ploadrbfnew_abs:
5526 case Hexagon::L4_ploadrbt_abs:
5527 case Hexagon::L4_ploadrbtnew_abs:
5528 case Hexagon::L4_ploadrhf_abs:
5529 case Hexagon::L4_ploadrhfnew_abs:
5530 case Hexagon::L4_ploadrht_abs:
5531 case Hexagon::L4_ploadrhtnew_abs:
5532 case Hexagon::L4_ploadrif_abs:
5533 case Hexagon::L4_ploadrifnew_abs:
5534 case Hexagon::L4_ploadrit_abs:
5535 case Hexagon::L4_ploadritnew_abs:
5536 case Hexagon::L4_ploadrubf_abs:
5537 case Hexagon::L4_ploadrubfnew_abs:
5538 case Hexagon::L4_ploadrubt_abs:
5539 case Hexagon::L4_ploadrubtnew_abs:
5540 case Hexagon::L4_ploadruhf_abs:
5541 case Hexagon::L4_ploadruhfnew_abs:
5542 case Hexagon::L4_ploadruht_abs:
5543 case Hexagon::L4_ploadruhtnew_abs: {
5544 // op: Ii
5545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5546 Value |= (op & UINT64_C(62)) << 15;
5547 Value |= (op & UINT64_C(1)) << 8;
5548 // op: Pt4
5549 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5550 op &= UINT64_C(3);
5551 op <<= 9;
5552 Value |= op;
5553 // op: Rd32
5554 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5555 op &= UINT64_C(31);
5556 Value |= op;
5557 break;
5558 }
5559 case Hexagon::L4_ploadrdf_abs:
5560 case Hexagon::L4_ploadrdfnew_abs:
5561 case Hexagon::L4_ploadrdt_abs:
5562 case Hexagon::L4_ploadrdtnew_abs: {
5563 // op: Ii
5564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5565 Value |= (op & UINT64_C(62)) << 15;
5566 Value |= (op & UINT64_C(1)) << 8;
5567 // op: Pt4
5568 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5569 op &= UINT64_C(3);
5570 op <<= 9;
5571 Value |= op;
5572 // op: Rdd32
5573 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5574 op &= UINT64_C(31);
5575 Value |= op;
5576 break;
5577 }
5578 case Hexagon::S2_pstorerhnewf_io:
5579 case Hexagon::S2_pstorerhnewt_io:
5580 case Hexagon::S4_pstorerhnewfnew_io:
5581 case Hexagon::S4_pstorerhnewtnew_io: {
5582 // op: Ii
5583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5584 Value |= (op & UINT64_C(64)) << 7;
5585 Value |= (op & UINT64_C(62)) << 2;
5586 // op: Pv4
5587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5588 op &= UINT64_C(3);
5589 Value |= op;
5590 // op: Rs32
5591 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5592 op &= UINT64_C(31);
5593 op <<= 16;
5594 Value |= op;
5595 // op: Nt8
5596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5597 op &= UINT64_C(7);
5598 op <<= 8;
5599 Value |= op;
5600 break;
5601 }
5602 case Hexagon::S2_pstorerff_io:
5603 case Hexagon::S2_pstorerft_io:
5604 case Hexagon::S2_pstorerhf_io:
5605 case Hexagon::S2_pstorerht_io:
5606 case Hexagon::S4_pstorerffnew_io:
5607 case Hexagon::S4_pstorerftnew_io:
5608 case Hexagon::S4_pstorerhfnew_io:
5609 case Hexagon::S4_pstorerhtnew_io: {
5610 // op: Ii
5611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5612 Value |= (op & UINT64_C(64)) << 7;
5613 Value |= (op & UINT64_C(62)) << 2;
5614 // op: Pv4
5615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5616 op &= UINT64_C(3);
5617 Value |= op;
5618 // op: Rs32
5619 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5620 op &= UINT64_C(31);
5621 op <<= 16;
5622 Value |= op;
5623 // op: Rt32
5624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5625 op &= UINT64_C(31);
5626 op <<= 8;
5627 Value |= op;
5628 break;
5629 }
5630 case Hexagon::A2_addi: {
5631 // op: Ii
5632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5633 Value |= (op & UINT64_C(65024)) << 12;
5634 Value |= (op & UINT64_C(511)) << 5;
5635 // op: Rs32
5636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5637 op &= UINT64_C(31);
5638 op <<= 16;
5639 Value |= op;
5640 // op: Rd32
5641 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5642 op &= UINT64_C(31);
5643 Value |= op;
5644 break;
5645 }
5646 case Hexagon::V6_zLd_pred_ai: {
5647 // op: Ii
5648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5649 Value |= (op & UINT64_C(8)) << 10;
5650 Value |= (op & UINT64_C(7)) << 8;
5651 // op: Pv4
5652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5653 op &= UINT64_C(3);
5654 op <<= 11;
5655 Value |= op;
5656 // op: Rt32
5657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5658 op &= UINT64_C(31);
5659 op <<= 16;
5660 Value |= op;
5661 break;
5662 }
5663 case Hexagon::V6_vS32b_new_npred_ai:
5664 case Hexagon::V6_vS32b_new_pred_ai:
5665 case Hexagon::V6_vS32b_nt_new_npred_ai:
5666 case Hexagon::V6_vS32b_nt_new_pred_ai: {
5667 // op: Ii
5668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5669 Value |= (op & UINT64_C(8)) << 10;
5670 Value |= (op & UINT64_C(7)) << 8;
5671 // op: Pv4
5672 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5673 op &= UINT64_C(3);
5674 op <<= 11;
5675 Value |= op;
5676 // op: Rt32
5677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5678 op &= UINT64_C(31);
5679 op <<= 16;
5680 Value |= op;
5681 // op: Os8
5682 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5683 op &= UINT64_C(7);
5684 Value |= op;
5685 break;
5686 }
5687 case Hexagon::V6_vS32Ub_npred_ai:
5688 case Hexagon::V6_vS32Ub_pred_ai:
5689 case Hexagon::V6_vS32b_npred_ai:
5690 case Hexagon::V6_vS32b_nt_npred_ai:
5691 case Hexagon::V6_vS32b_nt_pred_ai:
5692 case Hexagon::V6_vS32b_pred_ai: {
5693 // op: Ii
5694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5695 Value |= (op & UINT64_C(8)) << 10;
5696 Value |= (op & UINT64_C(7)) << 8;
5697 // op: Pv4
5698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5699 op &= UINT64_C(3);
5700 op <<= 11;
5701 Value |= op;
5702 // op: Rt32
5703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5704 op &= UINT64_C(31);
5705 op <<= 16;
5706 Value |= op;
5707 // op: Vs32
5708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5709 op &= UINT64_C(31);
5710 Value |= op;
5711 break;
5712 }
5713 case Hexagon::V6_vS32b_nqpred_ai:
5714 case Hexagon::V6_vS32b_nt_nqpred_ai:
5715 case Hexagon::V6_vS32b_nt_qpred_ai:
5716 case Hexagon::V6_vS32b_qpred_ai: {
5717 // op: Ii
5718 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5719 Value |= (op & UINT64_C(8)) << 10;
5720 Value |= (op & UINT64_C(7)) << 8;
5721 // op: Qv4
5722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5723 op &= UINT64_C(3);
5724 op <<= 11;
5725 Value |= op;
5726 // op: Rt32
5727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5728 op &= UINT64_C(31);
5729 op <<= 16;
5730 Value |= op;
5731 // op: Vs32
5732 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5733 op &= UINT64_C(31);
5734 Value |= op;
5735 break;
5736 }
5737 case Hexagon::V6_vL32Ub_ai:
5738 case Hexagon::V6_vL32b_ai:
5739 case Hexagon::V6_vL32b_cur_ai:
5740 case Hexagon::V6_vL32b_nt_ai:
5741 case Hexagon::V6_vL32b_nt_cur_ai:
5742 case Hexagon::V6_vL32b_nt_tmp_ai:
5743 case Hexagon::V6_vL32b_tmp_ai: {
5744 // op: Ii
5745 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5746 Value |= (op & UINT64_C(8)) << 10;
5747 Value |= (op & UINT64_C(7)) << 8;
5748 // op: Rt32
5749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5750 op &= UINT64_C(31);
5751 op <<= 16;
5752 Value |= op;
5753 // op: Vd32
5754 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5755 op &= UINT64_C(31);
5756 Value |= op;
5757 break;
5758 }
5759 case Hexagon::S2_storerd_pci: {
5760 // op: Ii
5761 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5762 op &= UINT64_C(120);
5763 Value |= op;
5764 // op: Mu2
5765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5766 op &= UINT64_C(1);
5767 op <<= 13;
5768 Value |= op;
5769 // op: Rtt32
5770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
5771 op &= UINT64_C(31);
5772 op <<= 8;
5773 Value |= op;
5774 // op: Rx32
5775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5776 op &= UINT64_C(31);
5777 op <<= 16;
5778 Value |= op;
5779 break;
5780 }
5781 case Hexagon::S2_storerd_pi: {
5782 // op: Ii
5783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5784 op &= UINT64_C(120);
5785 Value |= op;
5786 // op: Rtt32
5787 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5788 op &= UINT64_C(31);
5789 op <<= 8;
5790 Value |= op;
5791 // op: Rx32
5792 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5793 op &= UINT64_C(31);
5794 op <<= 16;
5795 Value |= op;
5796 break;
5797 }
5798 case Hexagon::S4_storeirhf_io:
5799 case Hexagon::S4_storeirhfnew_io:
5800 case Hexagon::S4_storeirht_io:
5801 case Hexagon::S4_storeirhtnew_io: {
5802 // op: Ii
5803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5804 op &= UINT64_C(126);
5805 op <<= 6;
5806 Value |= op;
5807 // op: II
5808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5809 Value |= (op & UINT64_C(32)) << 8;
5810 Value |= (op & UINT64_C(31));
5811 // op: Pv4
5812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5813 op &= UINT64_C(3);
5814 op <<= 5;
5815 Value |= op;
5816 // op: Rs32
5817 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5818 op &= UINT64_C(31);
5819 op <<= 16;
5820 Value |= op;
5821 break;
5822 }
5823 case Hexagon::SA1_addi: {
5824 // op: Ii
5825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5826 op &= UINT64_C(127);
5827 op <<= 4;
5828 Value |= op;
5829 // op: Rx16
5830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5831 op &= UINT64_C(15);
5832 Value |= op;
5833 break;
5834 }
5835 case Hexagon::A4_cmpbgtui:
5836 case Hexagon::A4_cmphgtui: {
5837 // op: Ii
5838 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5839 op &= UINT64_C(127);
5840 op <<= 5;
5841 Value |= op;
5842 // op: Rs32
5843 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5844 op &= UINT64_C(31);
5845 op <<= 16;
5846 Value |= op;
5847 // op: Pd4
5848 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5849 op &= UINT64_C(3);
5850 Value |= op;
5851 break;
5852 }
5853 case Hexagon::A4_vcmpbgtui:
5854 case Hexagon::A4_vcmphgtui:
5855 case Hexagon::A4_vcmpwgtui: {
5856 // op: Ii
5857 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5858 op &= UINT64_C(127);
5859 op <<= 5;
5860 Value |= op;
5861 // op: Rss32
5862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5863 op &= UINT64_C(31);
5864 op <<= 16;
5865 Value |= op;
5866 // op: Pd4
5867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5868 op &= UINT64_C(3);
5869 Value |= op;
5870 break;
5871 }
5872 case Hexagon::SL2_loadrh_io:
5873 case Hexagon::SL2_loadruh_io: {
5874 // op: Ii
5875 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5876 op &= UINT64_C(14);
5877 op <<= 7;
5878 Value |= op;
5879 // op: Rs16
5880 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5881 op &= UINT64_C(15);
5882 op <<= 4;
5883 Value |= op;
5884 // op: Rd16
5885 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5886 op &= UINT64_C(15);
5887 Value |= op;
5888 break;
5889 }
5890 case Hexagon::S2_storerbnew_pci: {
5891 // op: Ii
5892 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5893 op &= UINT64_C(15);
5894 op <<= 3;
5895 Value |= op;
5896 // op: Mu2
5897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5898 op &= UINT64_C(1);
5899 op <<= 13;
5900 Value |= op;
5901 // op: Nt8
5902 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
5903 op &= UINT64_C(7);
5904 op <<= 8;
5905 Value |= op;
5906 // op: Rx32
5907 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5908 op &= UINT64_C(31);
5909 op <<= 16;
5910 Value |= op;
5911 break;
5912 }
5913 case Hexagon::S2_storerb_pci: {
5914 // op: Ii
5915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5916 op &= UINT64_C(15);
5917 op <<= 3;
5918 Value |= op;
5919 // op: Mu2
5920 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5921 op &= UINT64_C(1);
5922 op <<= 13;
5923 Value |= op;
5924 // op: Rt32
5925 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
5926 op &= UINT64_C(31);
5927 op <<= 8;
5928 Value |= op;
5929 // op: Rx32
5930 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5931 op &= UINT64_C(31);
5932 op <<= 16;
5933 Value |= op;
5934 break;
5935 }
5936 case Hexagon::S2_storerbnew_pi: {
5937 // op: Ii
5938 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5939 op &= UINT64_C(15);
5940 op <<= 3;
5941 Value |= op;
5942 // op: Nt8
5943 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5944 op &= UINT64_C(7);
5945 op <<= 8;
5946 Value |= op;
5947 // op: Rx32
5948 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5949 op &= UINT64_C(31);
5950 op <<= 16;
5951 Value |= op;
5952 break;
5953 }
5954 case Hexagon::S2_storerb_pi: {
5955 // op: Ii
5956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5957 op &= UINT64_C(15);
5958 op <<= 3;
5959 Value |= op;
5960 // op: Rt32
5961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
5962 op &= UINT64_C(31);
5963 op <<= 8;
5964 Value |= op;
5965 // op: Rx32
5966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5967 op &= UINT64_C(31);
5968 op <<= 16;
5969 Value |= op;
5970 break;
5971 }
5972 case Hexagon::SL1_loadrub_io: {
5973 // op: Ii
5974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5975 op &= UINT64_C(15);
5976 op <<= 8;
5977 Value |= op;
5978 // op: Rs16
5979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5980 op &= UINT64_C(15);
5981 op <<= 4;
5982 Value |= op;
5983 // op: Rd16
5984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
5985 op &= UINT64_C(15);
5986 Value |= op;
5987 break;
5988 }
5989 case Hexagon::S5_asrhub_rnd_sat:
5990 case Hexagon::S5_asrhub_sat: {
5991 // op: Ii
5992 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
5993 op &= UINT64_C(15);
5994 op <<= 8;
5995 Value |= op;
5996 // op: Rss32
5997 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
5998 op &= UINT64_C(31);
5999 op <<= 16;
6000 Value |= op;
6001 // op: Rd32
6002 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6003 op &= UINT64_C(31);
6004 Value |= op;
6005 break;
6006 }
6007 case Hexagon::S2_asl_i_vh:
6008 case Hexagon::S2_asr_i_vh:
6009 case Hexagon::S2_lsr_i_vh:
6010 case Hexagon::S5_vasrhrnd: {
6011 // op: Ii
6012 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6013 op &= UINT64_C(15);
6014 op <<= 8;
6015 Value |= op;
6016 // op: Rss32
6017 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6018 op &= UINT64_C(31);
6019 op <<= 16;
6020 Value |= op;
6021 // op: Rdd32
6022 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6023 op &= UINT64_C(31);
6024 Value |= op;
6025 break;
6026 }
6027 case Hexagon::S2_allocframe: {
6028 // op: Ii
6029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6030 op &= UINT64_C(16376);
6031 op >>= 3;
6032 Value |= op;
6033 // op: Rx32
6034 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6035 op &= UINT64_C(31);
6036 op <<= 16;
6037 Value |= op;
6038 break;
6039 }
6040 case Hexagon::S4_storeirif_io:
6041 case Hexagon::S4_storeirifnew_io:
6042 case Hexagon::S4_storeirit_io:
6043 case Hexagon::S4_storeiritnew_io: {
6044 // op: Ii
6045 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6046 op &= UINT64_C(252);
6047 op <<= 5;
6048 Value |= op;
6049 // op: II
6050 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6051 Value |= (op & UINT64_C(32)) << 8;
6052 Value |= (op & UINT64_C(31));
6053 // op: Pv4
6054 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6055 op &= UINT64_C(3);
6056 op <<= 5;
6057 Value |= op;
6058 // op: Rs32
6059 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6060 op &= UINT64_C(31);
6061 op <<= 16;
6062 Value |= op;
6063 break;
6064 }
6065 case Hexagon::C2_muxii: {
6066 // op: Ii
6067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6068 op &= UINT64_C(255);
6069 op <<= 5;
6070 Value |= op;
6071 // op: II
6072 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6073 Value |= (op & UINT64_C(254)) << 15;
6074 Value |= (op & UINT64_C(1)) << 13;
6075 // op: Pu4
6076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6077 op &= UINT64_C(3);
6078 op <<= 23;
6079 Value |= op;
6080 // op: Rd32
6081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6082 op &= UINT64_C(31);
6083 Value |= op;
6084 break;
6085 }
6086 case Hexagon::C2_muxri: {
6087 // op: Ii
6088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6089 op &= UINT64_C(255);
6090 op <<= 5;
6091 Value |= op;
6092 // op: Pu4
6093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6094 op &= UINT64_C(3);
6095 op <<= 21;
6096 Value |= op;
6097 // op: Rs32
6098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6099 op &= UINT64_C(31);
6100 op <<= 16;
6101 Value |= op;
6102 // op: Rd32
6103 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6104 op &= UINT64_C(31);
6105 Value |= op;
6106 break;
6107 }
6108 case Hexagon::A4_cmpbeqi:
6109 case Hexagon::A4_cmpbgti:
6110 case Hexagon::A4_cmpheqi:
6111 case Hexagon::A4_cmphgti: {
6112 // op: Ii
6113 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6114 op &= UINT64_C(255);
6115 op <<= 5;
6116 Value |= op;
6117 // op: Rs32
6118 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6119 op &= UINT64_C(31);
6120 op <<= 16;
6121 Value |= op;
6122 // op: Pd4
6123 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6124 op &= UINT64_C(3);
6125 Value |= op;
6126 break;
6127 }
6128 case Hexagon::A4_rcmpeqi:
6129 case Hexagon::A4_rcmpneqi:
6130 case Hexagon::M2_mpysin:
6131 case Hexagon::M2_mpysip: {
6132 // op: Ii
6133 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6134 op &= UINT64_C(255);
6135 op <<= 5;
6136 Value |= op;
6137 // op: Rs32
6138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6139 op &= UINT64_C(31);
6140 op <<= 16;
6141 Value |= op;
6142 // op: Rd32
6143 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6144 op &= UINT64_C(31);
6145 Value |= op;
6146 break;
6147 }
6148 case Hexagon::A4_combineri: {
6149 // op: Ii
6150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6151 op &= UINT64_C(255);
6152 op <<= 5;
6153 Value |= op;
6154 // op: Rs32
6155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6156 op &= UINT64_C(31);
6157 op <<= 16;
6158 Value |= op;
6159 // op: Rdd32
6160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6161 op &= UINT64_C(31);
6162 Value |= op;
6163 break;
6164 }
6165 case Hexagon::A4_vcmpbeqi:
6166 case Hexagon::A4_vcmpbgti:
6167 case Hexagon::A4_vcmpheqi:
6168 case Hexagon::A4_vcmphgti:
6169 case Hexagon::A4_vcmpweqi:
6170 case Hexagon::A4_vcmpwgti: {
6171 // op: Ii
6172 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6173 op &= UINT64_C(255);
6174 op <<= 5;
6175 Value |= op;
6176 // op: Rss32
6177 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6178 op &= UINT64_C(31);
6179 op <<= 16;
6180 Value |= op;
6181 // op: Pd4
6182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6183 op &= UINT64_C(3);
6184 Value |= op;
6185 break;
6186 }
6187 case Hexagon::S2_storerhnew_pci: {
6188 // op: Ii
6189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6190 op &= UINT64_C(30);
6191 op <<= 2;
6192 Value |= op;
6193 // op: Mu2
6194 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6195 op &= UINT64_C(1);
6196 op <<= 13;
6197 Value |= op;
6198 // op: Nt8
6199 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6200 op &= UINT64_C(7);
6201 op <<= 8;
6202 Value |= op;
6203 // op: Rx32
6204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6205 op &= UINT64_C(31);
6206 op <<= 16;
6207 Value |= op;
6208 break;
6209 }
6210 case Hexagon::S2_storerf_pci:
6211 case Hexagon::S2_storerh_pci: {
6212 // op: Ii
6213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6214 op &= UINT64_C(30);
6215 op <<= 2;
6216 Value |= op;
6217 // op: Mu2
6218 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6219 op &= UINT64_C(1);
6220 op <<= 13;
6221 Value |= op;
6222 // op: Rt32
6223 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6224 op &= UINT64_C(31);
6225 op <<= 8;
6226 Value |= op;
6227 // op: Rx32
6228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6229 op &= UINT64_C(31);
6230 op <<= 16;
6231 Value |= op;
6232 break;
6233 }
6234 case Hexagon::S2_storerhnew_pi: {
6235 // op: Ii
6236 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6237 op &= UINT64_C(30);
6238 op <<= 2;
6239 Value |= op;
6240 // op: Nt8
6241 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6242 op &= UINT64_C(7);
6243 op <<= 8;
6244 Value |= op;
6245 // op: Rx32
6246 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6247 op &= UINT64_C(31);
6248 op <<= 16;
6249 Value |= op;
6250 break;
6251 }
6252 case Hexagon::S2_storerf_pi:
6253 case Hexagon::S2_storerh_pi: {
6254 // op: Ii
6255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6256 op &= UINT64_C(30);
6257 op <<= 2;
6258 Value |= op;
6259 // op: Rt32
6260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6261 op &= UINT64_C(31);
6262 op <<= 8;
6263 Value |= op;
6264 // op: Rx32
6265 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6266 op &= UINT64_C(31);
6267 op <<= 16;
6268 Value |= op;
6269 break;
6270 }
6271 case Hexagon::F2_dfclass: {
6272 // op: Ii
6273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6274 op &= UINT64_C(31);
6275 op <<= 5;
6276 Value |= op;
6277 // op: Rss32
6278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6279 op &= UINT64_C(31);
6280 op <<= 16;
6281 Value |= op;
6282 // op: Pd4
6283 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6284 op &= UINT64_C(3);
6285 Value |= op;
6286 break;
6287 }
6288 case Hexagon::S2_extractu:
6289 case Hexagon::S4_extract: {
6290 // op: Ii
6291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6292 op &= UINT64_C(31);
6293 op <<= 8;
6294 Value |= op;
6295 // op: II
6296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6297 Value |= (op & UINT64_C(24)) << 18;
6298 Value |= (op & UINT64_C(7)) << 5;
6299 // op: Rs32
6300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6301 op &= UINT64_C(31);
6302 op <<= 16;
6303 Value |= op;
6304 // op: Rd32
6305 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6306 op &= UINT64_C(31);
6307 Value |= op;
6308 break;
6309 }
6310 case Hexagon::F2_sfclass:
6311 case Hexagon::S2_tstbit_i:
6312 case Hexagon::S4_ntstbit_i: {
6313 // op: Ii
6314 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6315 op &= UINT64_C(31);
6316 op <<= 8;
6317 Value |= op;
6318 // op: Rs32
6319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6320 op &= UINT64_C(31);
6321 op <<= 16;
6322 Value |= op;
6323 // op: Pd4
6324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6325 op &= UINT64_C(3);
6326 Value |= op;
6327 break;
6328 }
6329 case Hexagon::A4_cround_ri:
6330 case Hexagon::A4_round_ri:
6331 case Hexagon::A4_round_ri_sat:
6332 case Hexagon::A7_clip:
6333 case Hexagon::S2_asl_i_r:
6334 case Hexagon::S2_asl_i_r_sat:
6335 case Hexagon::S2_asr_i_r:
6336 case Hexagon::S2_asr_i_r_rnd:
6337 case Hexagon::S2_clrbit_i:
6338 case Hexagon::S2_lsr_i_r:
6339 case Hexagon::S2_setbit_i:
6340 case Hexagon::S2_togglebit_i:
6341 case Hexagon::S6_rol_i_r: {
6342 // op: Ii
6343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6344 op &= UINT64_C(31);
6345 op <<= 8;
6346 Value |= op;
6347 // op: Rs32
6348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6349 op &= UINT64_C(31);
6350 op <<= 16;
6351 Value |= op;
6352 // op: Rd32
6353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6354 op &= UINT64_C(31);
6355 Value |= op;
6356 break;
6357 }
6358 case Hexagon::A4_bitspliti: {
6359 // op: Ii
6360 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6361 op &= UINT64_C(31);
6362 op <<= 8;
6363 Value |= op;
6364 // op: Rs32
6365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6366 op &= UINT64_C(31);
6367 op <<= 16;
6368 Value |= op;
6369 // op: Rdd32
6370 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6371 op &= UINT64_C(31);
6372 Value |= op;
6373 break;
6374 }
6375 case Hexagon::S2_asr_i_svw_trun: {
6376 // op: Ii
6377 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6378 op &= UINT64_C(31);
6379 op <<= 8;
6380 Value |= op;
6381 // op: Rss32
6382 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6383 op &= UINT64_C(31);
6384 op <<= 16;
6385 Value |= op;
6386 // op: Rd32
6387 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6388 op &= UINT64_C(31);
6389 Value |= op;
6390 break;
6391 }
6392 case Hexagon::A7_vclip:
6393 case Hexagon::S2_asl_i_vw:
6394 case Hexagon::S2_asr_i_vw:
6395 case Hexagon::S2_lsr_i_vw: {
6396 // op: Ii
6397 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6398 op &= UINT64_C(31);
6399 op <<= 8;
6400 Value |= op;
6401 // op: Rss32
6402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6403 op &= UINT64_C(31);
6404 op <<= 16;
6405 Value |= op;
6406 // op: Rdd32
6407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6408 op &= UINT64_C(31);
6409 Value |= op;
6410 break;
6411 }
6412 case Hexagon::C2_cmpgtui:
6413 case Hexagon::C4_cmplteui: {
6414 // op: Ii
6415 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6416 op &= UINT64_C(511);
6417 op <<= 5;
6418 Value |= op;
6419 // op: Rs32
6420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6421 op &= UINT64_C(31);
6422 op <<= 16;
6423 Value |= op;
6424 // op: Pd4
6425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6426 op &= UINT64_C(3);
6427 Value |= op;
6428 break;
6429 }
6430 case Hexagon::S2_storerinew_pci: {
6431 // op: Ii
6432 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6433 op &= UINT64_C(60);
6434 op <<= 1;
6435 Value |= op;
6436 // op: Mu2
6437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6438 op &= UINT64_C(1);
6439 op <<= 13;
6440 Value |= op;
6441 // op: Nt8
6442 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6443 op &= UINT64_C(7);
6444 op <<= 8;
6445 Value |= op;
6446 // op: Rx32
6447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6448 op &= UINT64_C(31);
6449 op <<= 16;
6450 Value |= op;
6451 break;
6452 }
6453 case Hexagon::S2_storeri_pci: {
6454 // op: Ii
6455 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6456 op &= UINT64_C(60);
6457 op <<= 1;
6458 Value |= op;
6459 // op: Mu2
6460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6461 op &= UINT64_C(1);
6462 op <<= 13;
6463 Value |= op;
6464 // op: Rt32
6465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6466 op &= UINT64_C(31);
6467 op <<= 8;
6468 Value |= op;
6469 // op: Rx32
6470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6471 op &= UINT64_C(31);
6472 op <<= 16;
6473 Value |= op;
6474 break;
6475 }
6476 case Hexagon::S2_storerinew_pi: {
6477 // op: Ii
6478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6479 op &= UINT64_C(60);
6480 op <<= 1;
6481 Value |= op;
6482 // op: Nt8
6483 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6484 op &= UINT64_C(7);
6485 op <<= 8;
6486 Value |= op;
6487 // op: Rx32
6488 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6489 op &= UINT64_C(31);
6490 op <<= 16;
6491 Value |= op;
6492 break;
6493 }
6494 case Hexagon::S2_storeri_pi: {
6495 // op: Ii
6496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6497 op &= UINT64_C(60);
6498 op <<= 1;
6499 Value |= op;
6500 // op: Rt32
6501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6502 op &= UINT64_C(31);
6503 op <<= 8;
6504 Value |= op;
6505 // op: Rx32
6506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6507 op &= UINT64_C(31);
6508 op <<= 16;
6509 Value |= op;
6510 break;
6511 }
6512 case Hexagon::SL1_loadri_io: {
6513 // op: Ii
6514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6515 op &= UINT64_C(60);
6516 op <<= 6;
6517 Value |= op;
6518 // op: Rs16
6519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6520 op &= UINT64_C(15);
6521 op <<= 4;
6522 Value |= op;
6523 // op: Rd16
6524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6525 op &= UINT64_C(15);
6526 Value |= op;
6527 break;
6528 }
6529 case Hexagon::S4_storeirbf_io:
6530 case Hexagon::S4_storeirbfnew_io:
6531 case Hexagon::S4_storeirbt_io:
6532 case Hexagon::S4_storeirbtnew_io: {
6533 // op: Ii
6534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6535 op &= UINT64_C(63);
6536 op <<= 7;
6537 Value |= op;
6538 // op: II
6539 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6540 Value |= (op & UINT64_C(32)) << 8;
6541 Value |= (op & UINT64_C(31));
6542 // op: Pv4
6543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6544 op &= UINT64_C(3);
6545 op <<= 5;
6546 Value |= op;
6547 // op: Rs32
6548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6549 op &= UINT64_C(31);
6550 op <<= 16;
6551 Value |= op;
6552 break;
6553 }
6554 case Hexagon::S2_extractup:
6555 case Hexagon::S4_extractp: {
6556 // op: Ii
6557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6558 op &= UINT64_C(63);
6559 op <<= 8;
6560 Value |= op;
6561 // op: II
6562 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6563 Value |= (op & UINT64_C(56)) << 18;
6564 Value |= (op & UINT64_C(7)) << 5;
6565 // op: Rss32
6566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6567 op &= UINT64_C(31);
6568 op <<= 16;
6569 Value |= op;
6570 // op: Rdd32
6571 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6572 op &= UINT64_C(31);
6573 Value |= op;
6574 break;
6575 }
6576 case Hexagon::C2_bitsclri:
6577 case Hexagon::C4_nbitsclri: {
6578 // op: Ii
6579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6580 op &= UINT64_C(63);
6581 op <<= 8;
6582 Value |= op;
6583 // op: Rs32
6584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6585 op &= UINT64_C(31);
6586 op <<= 16;
6587 Value |= op;
6588 // op: Pd4
6589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6590 op &= UINT64_C(3);
6591 Value |= op;
6592 break;
6593 }
6594 case Hexagon::S4_clbaddi: {
6595 // op: Ii
6596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6597 op &= UINT64_C(63);
6598 op <<= 8;
6599 Value |= op;
6600 // op: Rs32
6601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6602 op &= UINT64_C(31);
6603 op <<= 16;
6604 Value |= op;
6605 // op: Rd32
6606 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6607 op &= UINT64_C(31);
6608 Value |= op;
6609 break;
6610 }
6611 case Hexagon::S4_clbpaddi: {
6612 // op: Ii
6613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6614 op &= UINT64_C(63);
6615 op <<= 8;
6616 Value |= op;
6617 // op: Rss32
6618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6619 op &= UINT64_C(31);
6620 op <<= 16;
6621 Value |= op;
6622 // op: Rd32
6623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6624 op &= UINT64_C(31);
6625 Value |= op;
6626 break;
6627 }
6628 case Hexagon::A7_croundd_ri:
6629 case Hexagon::S2_asl_i_p:
6630 case Hexagon::S2_asr_i_p:
6631 case Hexagon::S2_asr_i_p_rnd:
6632 case Hexagon::S2_lsr_i_p:
6633 case Hexagon::S6_rol_i_p: {
6634 // op: Ii
6635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6636 op &= UINT64_C(63);
6637 op <<= 8;
6638 Value |= op;
6639 // op: Rss32
6640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6641 op &= UINT64_C(31);
6642 op <<= 16;
6643 Value |= op;
6644 // op: Rdd32
6645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6646 op &= UINT64_C(31);
6647 Value |= op;
6648 break;
6649 }
6650 case Hexagon::V6_vS32b_new_pi:
6651 case Hexagon::V6_vS32b_nt_new_pi: {
6652 // op: Ii
6653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6654 op &= UINT64_C(7);
6655 op <<= 8;
6656 Value |= op;
6657 // op: Os8
6658 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6659 op &= UINT64_C(7);
6660 Value |= op;
6661 // op: Rx32
6662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6663 op &= UINT64_C(31);
6664 op <<= 16;
6665 Value |= op;
6666 break;
6667 }
6668 case Hexagon::SL2_loadrb_io: {
6669 // op: Ii
6670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6671 op &= UINT64_C(7);
6672 op <<= 8;
6673 Value |= op;
6674 // op: Rs16
6675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6676 op &= UINT64_C(15);
6677 op <<= 4;
6678 Value |= op;
6679 // op: Rd16
6680 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6681 op &= UINT64_C(15);
6682 Value |= op;
6683 break;
6684 }
6685 case Hexagon::V6_vS32b_srls_pi:
6686 case Hexagon::V6_zLd_pi: {
6687 // op: Ii
6688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6689 op &= UINT64_C(7);
6690 op <<= 8;
6691 Value |= op;
6692 // op: Rx32
6693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6694 op &= UINT64_C(31);
6695 op <<= 16;
6696 Value |= op;
6697 break;
6698 }
6699 case Hexagon::V6_vS32Ub_pi:
6700 case Hexagon::V6_vS32b_nt_pi:
6701 case Hexagon::V6_vS32b_pi: {
6702 // op: Ii
6703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6704 op &= UINT64_C(7);
6705 op <<= 8;
6706 Value |= op;
6707 // op: Vs32
6708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6709 op &= UINT64_C(31);
6710 Value |= op;
6711 // op: Rx32
6712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6713 op &= UINT64_C(31);
6714 op <<= 16;
6715 Value |= op;
6716 break;
6717 }
6718 case Hexagon::L2_loadalignb_io: {
6719 // op: Ii
6720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6721 Value |= (op & UINT64_C(1536)) << 16;
6722 Value |= (op & UINT64_C(511)) << 5;
6723 // op: Rs32
6724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6725 op &= UINT64_C(31);
6726 op <<= 16;
6727 Value |= op;
6728 // op: Ryy32
6729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6730 op &= UINT64_C(31);
6731 Value |= op;
6732 break;
6733 }
6734 case Hexagon::S4_vrcrotate: {
6735 // op: Ii
6736 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6737 Value |= (op & UINT64_C(2)) << 12;
6738 Value |= (op & UINT64_C(1)) << 5;
6739 // op: Rss32
6740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6741 op &= UINT64_C(31);
6742 op <<= 16;
6743 Value |= op;
6744 // op: Rt32
6745 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6746 op &= UINT64_C(31);
6747 op <<= 8;
6748 Value |= op;
6749 // op: Rdd32
6750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6751 op &= UINT64_C(31);
6752 Value |= op;
6753 break;
6754 }
6755 case Hexagon::L4_loadalignb_ur:
6756 case Hexagon::L4_loadalignh_ur: {
6757 // op: Ii
6758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6759 Value |= (op & UINT64_C(2)) << 12;
6760 Value |= (op & UINT64_C(1)) << 7;
6761 // op: II
6762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6763 Value |= (op & UINT64_C(60)) << 6;
6764 Value |= (op & UINT64_C(3)) << 5;
6765 // op: Rt32
6766 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6767 op &= UINT64_C(31);
6768 op <<= 16;
6769 Value |= op;
6770 // op: Ryy32
6771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6772 op &= UINT64_C(31);
6773 Value |= op;
6774 break;
6775 }
6776 case Hexagon::S4_pstorerbnewf_rr:
6777 case Hexagon::S4_pstorerbnewfnew_rr:
6778 case Hexagon::S4_pstorerbnewt_rr:
6779 case Hexagon::S4_pstorerbnewtnew_rr:
6780 case Hexagon::S4_pstorerhnewf_rr:
6781 case Hexagon::S4_pstorerhnewfnew_rr:
6782 case Hexagon::S4_pstorerhnewt_rr:
6783 case Hexagon::S4_pstorerhnewtnew_rr:
6784 case Hexagon::S4_pstorerinewf_rr:
6785 case Hexagon::S4_pstorerinewfnew_rr:
6786 case Hexagon::S4_pstorerinewt_rr:
6787 case Hexagon::S4_pstorerinewtnew_rr: {
6788 // op: Ii
6789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6790 Value |= (op & UINT64_C(2)) << 12;
6791 Value |= (op & UINT64_C(1)) << 7;
6792 // op: Pv4
6793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6794 op &= UINT64_C(3);
6795 op <<= 5;
6796 Value |= op;
6797 // op: Rs32
6798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6799 op &= UINT64_C(31);
6800 op <<= 16;
6801 Value |= op;
6802 // op: Ru32
6803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6804 op &= UINT64_C(31);
6805 op <<= 8;
6806 Value |= op;
6807 // op: Nt8
6808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6809 op &= UINT64_C(7);
6810 Value |= op;
6811 break;
6812 }
6813 case Hexagon::S4_pstorerbf_rr:
6814 case Hexagon::S4_pstorerbfnew_rr:
6815 case Hexagon::S4_pstorerbt_rr:
6816 case Hexagon::S4_pstorerbtnew_rr:
6817 case Hexagon::S4_pstorerff_rr:
6818 case Hexagon::S4_pstorerffnew_rr:
6819 case Hexagon::S4_pstorerft_rr:
6820 case Hexagon::S4_pstorerftnew_rr:
6821 case Hexagon::S4_pstorerhf_rr:
6822 case Hexagon::S4_pstorerhfnew_rr:
6823 case Hexagon::S4_pstorerht_rr:
6824 case Hexagon::S4_pstorerhtnew_rr:
6825 case Hexagon::S4_pstorerif_rr:
6826 case Hexagon::S4_pstorerifnew_rr:
6827 case Hexagon::S4_pstorerit_rr:
6828 case Hexagon::S4_pstoreritnew_rr: {
6829 // op: Ii
6830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6831 Value |= (op & UINT64_C(2)) << 12;
6832 Value |= (op & UINT64_C(1)) << 7;
6833 // op: Pv4
6834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6835 op &= UINT64_C(3);
6836 op <<= 5;
6837 Value |= op;
6838 // op: Rs32
6839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6840 op &= UINT64_C(31);
6841 op <<= 16;
6842 Value |= op;
6843 // op: Ru32
6844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6845 op &= UINT64_C(31);
6846 op <<= 8;
6847 Value |= op;
6848 // op: Rt32
6849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6850 op &= UINT64_C(31);
6851 Value |= op;
6852 break;
6853 }
6854 case Hexagon::S4_pstorerdf_rr:
6855 case Hexagon::S4_pstorerdfnew_rr:
6856 case Hexagon::S4_pstorerdt_rr:
6857 case Hexagon::S4_pstorerdtnew_rr: {
6858 // op: Ii
6859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6860 Value |= (op & UINT64_C(2)) << 12;
6861 Value |= (op & UINT64_C(1)) << 7;
6862 // op: Pv4
6863 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6864 op &= UINT64_C(3);
6865 op <<= 5;
6866 Value |= op;
6867 // op: Rs32
6868 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6869 op &= UINT64_C(31);
6870 op <<= 16;
6871 Value |= op;
6872 // op: Ru32
6873 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6874 op &= UINT64_C(31);
6875 op <<= 8;
6876 Value |= op;
6877 // op: Rtt32
6878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
6879 op &= UINT64_C(31);
6880 Value |= op;
6881 break;
6882 }
6883 case Hexagon::L4_loadrb_rr:
6884 case Hexagon::L4_loadrh_rr:
6885 case Hexagon::L4_loadri_rr:
6886 case Hexagon::L4_loadrub_rr:
6887 case Hexagon::L4_loadruh_rr: {
6888 // op: Ii
6889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6890 Value |= (op & UINT64_C(2)) << 12;
6891 Value |= (op & UINT64_C(1)) << 7;
6892 // op: Rs32
6893 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6894 op &= UINT64_C(31);
6895 op <<= 16;
6896 Value |= op;
6897 // op: Rt32
6898 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6899 op &= UINT64_C(31);
6900 op <<= 8;
6901 Value |= op;
6902 // op: Rd32
6903 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6904 op &= UINT64_C(31);
6905 Value |= op;
6906 break;
6907 }
6908 case Hexagon::L4_loadrd_rr: {
6909 // op: Ii
6910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6911 Value |= (op & UINT64_C(2)) << 12;
6912 Value |= (op & UINT64_C(1)) << 7;
6913 // op: Rs32
6914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6915 op &= UINT64_C(31);
6916 op <<= 16;
6917 Value |= op;
6918 // op: Rt32
6919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6920 op &= UINT64_C(31);
6921 op <<= 8;
6922 Value |= op;
6923 // op: Rdd32
6924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6925 op &= UINT64_C(31);
6926 Value |= op;
6927 break;
6928 }
6929 case Hexagon::L2_loadalignh_io: {
6930 // op: Ii
6931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6932 Value |= (op & UINT64_C(3072)) << 15;
6933 Value |= (op & UINT64_C(1022)) << 4;
6934 // op: Rs32
6935 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6936 op &= UINT64_C(31);
6937 op <<= 16;
6938 Value |= op;
6939 // op: Ryy32
6940 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6941 op &= UINT64_C(31);
6942 Value |= op;
6943 break;
6944 }
6945 case Hexagon::S4_addaddi: {
6946 // op: Ii
6947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6948 Value |= (op & UINT64_C(48)) << 17;
6949 Value |= (op & UINT64_C(8)) << 10;
6950 Value |= (op & UINT64_C(7)) << 5;
6951 // op: Rs32
6952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6953 op &= UINT64_C(31);
6954 op <<= 16;
6955 Value |= op;
6956 // op: Ru32
6957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6958 op &= UINT64_C(31);
6959 Value |= op;
6960 // op: Rd32
6961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6962 op &= UINT64_C(31);
6963 op <<= 8;
6964 Value |= op;
6965 break;
6966 }
6967 case Hexagon::M4_mpyri_addr: {
6968 // op: Ii
6969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6970 Value |= (op & UINT64_C(48)) << 17;
6971 Value |= (op & UINT64_C(8)) << 10;
6972 Value |= (op & UINT64_C(7)) << 5;
6973 // op: Ru32
6974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
6975 op &= UINT64_C(31);
6976 Value |= op;
6977 // op: Rs32
6978 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6979 op &= UINT64_C(31);
6980 op <<= 16;
6981 Value |= op;
6982 // op: Rd32
6983 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
6984 op &= UINT64_C(31);
6985 op <<= 8;
6986 Value |= op;
6987 break;
6988 }
6989 case Hexagon::S4_or_andi:
6990 case Hexagon::S4_or_ori: {
6991 // op: Ii
6992 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
6993 Value |= (op & UINT64_C(512)) << 12;
6994 Value |= (op & UINT64_C(511)) << 5;
6995 // op: Rs32
6996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
6997 op &= UINT64_C(31);
6998 op <<= 16;
6999 Value |= op;
7000 // op: Rx32
7001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7002 op &= UINT64_C(31);
7003 Value |= op;
7004 break;
7005 }
7006 case Hexagon::S4_or_andix: {
7007 // op: Ii
7008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7009 Value |= (op & UINT64_C(512)) << 12;
7010 Value |= (op & UINT64_C(511)) << 5;
7011 // op: Ru32
7012 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7013 op &= UINT64_C(31);
7014 Value |= op;
7015 // op: Rx32
7016 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7017 op &= UINT64_C(31);
7018 op <<= 16;
7019 Value |= op;
7020 break;
7021 }
7022 case Hexagon::V6_vL32b_cur_npred_ai:
7023 case Hexagon::V6_vL32b_cur_pred_ai:
7024 case Hexagon::V6_vL32b_npred_ai:
7025 case Hexagon::V6_vL32b_nt_cur_npred_ai:
7026 case Hexagon::V6_vL32b_nt_cur_pred_ai:
7027 case Hexagon::V6_vL32b_nt_npred_ai:
7028 case Hexagon::V6_vL32b_nt_pred_ai:
7029 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
7030 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
7031 case Hexagon::V6_vL32b_pred_ai:
7032 case Hexagon::V6_vL32b_tmp_npred_ai:
7033 case Hexagon::V6_vL32b_tmp_pred_ai: {
7034 // op: Ii
7035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7036 Value |= (op & UINT64_C(8)) << 10;
7037 Value |= (op & UINT64_C(7)) << 8;
7038 // op: Pv4
7039 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7040 op &= UINT64_C(3);
7041 op <<= 11;
7042 Value |= op;
7043 // op: Rt32
7044 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7045 op &= UINT64_C(31);
7046 op <<= 16;
7047 Value |= op;
7048 // op: Vd32
7049 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7050 op &= UINT64_C(31);
7051 Value |= op;
7052 break;
7053 }
7054 case Hexagon::S2_tableidxb:
7055 case Hexagon::S2_tableidxd:
7056 case Hexagon::S2_tableidxh:
7057 case Hexagon::S2_tableidxw: {
7058 // op: Ii
7059 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7060 Value |= (op & UINT64_C(8)) << 18;
7061 Value |= (op & UINT64_C(7)) << 5;
7062 // op: II
7063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7064 op &= UINT64_C(63);
7065 op <<= 8;
7066 Value |= op;
7067 // op: Rs32
7068 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7069 op &= UINT64_C(31);
7070 op <<= 16;
7071 Value |= op;
7072 // op: Rx32
7073 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7074 op &= UINT64_C(31);
7075 Value |= op;
7076 break;
7077 }
7078 case Hexagon::V6_vrmpybusi:
7079 case Hexagon::V6_vrmpyubi:
7080 case Hexagon::V6_vrsadubi: {
7081 // op: Ii
7082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7083 op &= UINT64_C(1);
7084 op <<= 5;
7085 Value |= op;
7086 // op: Vuu32
7087 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7088 op &= UINT64_C(31);
7089 op <<= 8;
7090 Value |= op;
7091 // op: Rt32
7092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7093 op &= UINT64_C(31);
7094 op <<= 16;
7095 Value |= op;
7096 // op: Vdd32
7097 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7098 op &= UINT64_C(31);
7099 Value |= op;
7100 break;
7101 }
7102 case Hexagon::S2_pstorerdf_pi:
7103 case Hexagon::S2_pstorerdfnew_pi:
7104 case Hexagon::S2_pstorerdt_pi:
7105 case Hexagon::S2_pstorerdtnew_pi: {
7106 // op: Ii
7107 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7108 op &= UINT64_C(120);
7109 Value |= op;
7110 // op: Pv4
7111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7112 op &= UINT64_C(3);
7113 Value |= op;
7114 // op: Rtt32
7115 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7116 op &= UINT64_C(31);
7117 op <<= 8;
7118 Value |= op;
7119 // op: Rx32
7120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7121 op &= UINT64_C(31);
7122 op <<= 16;
7123 Value |= op;
7124 break;
7125 }
7126 case Hexagon::L2_loadrd_pci: {
7127 // op: Ii
7128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7129 op &= UINT64_C(120);
7130 op <<= 2;
7131 Value |= op;
7132 // op: Mu2
7133 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7134 op &= UINT64_C(1);
7135 op <<= 13;
7136 Value |= op;
7137 // op: Rdd32
7138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7139 op &= UINT64_C(31);
7140 Value |= op;
7141 // op: Rx32
7142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7143 op &= UINT64_C(31);
7144 op <<= 16;
7145 Value |= op;
7146 break;
7147 }
7148 case Hexagon::L2_loadrd_pi: {
7149 // op: Ii
7150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7151 op &= UINT64_C(120);
7152 op <<= 2;
7153 Value |= op;
7154 // op: Rdd32
7155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7156 op &= UINT64_C(31);
7157 Value |= op;
7158 // op: Rx32
7159 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7160 op &= UINT64_C(31);
7161 op <<= 16;
7162 Value |= op;
7163 break;
7164 }
7165 case Hexagon::L2_ploadrhf_io:
7166 case Hexagon::L2_ploadrhfnew_io:
7167 case Hexagon::L2_ploadrht_io:
7168 case Hexagon::L2_ploadrhtnew_io:
7169 case Hexagon::L2_ploadruhf_io:
7170 case Hexagon::L2_ploadruhfnew_io:
7171 case Hexagon::L2_ploadruht_io:
7172 case Hexagon::L2_ploadruhtnew_io: {
7173 // op: Ii
7174 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7175 op &= UINT64_C(126);
7176 op <<= 4;
7177 Value |= op;
7178 // op: Pt4
7179 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7180 op &= UINT64_C(3);
7181 op <<= 11;
7182 Value |= op;
7183 // op: Rs32
7184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7185 op &= UINT64_C(31);
7186 op <<= 16;
7187 Value |= op;
7188 // op: Rd32
7189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7190 op &= UINT64_C(31);
7191 Value |= op;
7192 break;
7193 }
7194 case Hexagon::S2_pstorerbnewf_pi:
7195 case Hexagon::S2_pstorerbnewfnew_pi:
7196 case Hexagon::S2_pstorerbnewt_pi:
7197 case Hexagon::S2_pstorerbnewtnew_pi: {
7198 // op: Ii
7199 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7200 op &= UINT64_C(15);
7201 op <<= 3;
7202 Value |= op;
7203 // op: Pv4
7204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7205 op &= UINT64_C(3);
7206 Value |= op;
7207 // op: Nt8
7208 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7209 op &= UINT64_C(7);
7210 op <<= 8;
7211 Value |= op;
7212 // op: Rx32
7213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7214 op &= UINT64_C(31);
7215 op <<= 16;
7216 Value |= op;
7217 break;
7218 }
7219 case Hexagon::S2_pstorerbf_pi:
7220 case Hexagon::S2_pstorerbfnew_pi:
7221 case Hexagon::S2_pstorerbt_pi:
7222 case Hexagon::S2_pstorerbtnew_pi: {
7223 // op: Ii
7224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7225 op &= UINT64_C(15);
7226 op <<= 3;
7227 Value |= op;
7228 // op: Pv4
7229 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7230 op &= UINT64_C(3);
7231 Value |= op;
7232 // op: Rt32
7233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7234 op &= UINT64_C(31);
7235 op <<= 8;
7236 Value |= op;
7237 // op: Rx32
7238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7239 op &= UINT64_C(31);
7240 op <<= 16;
7241 Value |= op;
7242 break;
7243 }
7244 case Hexagon::L2_loadrb_pci:
7245 case Hexagon::L2_loadrub_pci: {
7246 // op: Ii
7247 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7248 op &= UINT64_C(15);
7249 op <<= 5;
7250 Value |= op;
7251 // op: Mu2
7252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7253 op &= UINT64_C(1);
7254 op <<= 13;
7255 Value |= op;
7256 // op: Rd32
7257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7258 op &= UINT64_C(31);
7259 Value |= op;
7260 // op: Rx32
7261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7262 op &= UINT64_C(31);
7263 op <<= 16;
7264 Value |= op;
7265 break;
7266 }
7267 case Hexagon::L2_loadrb_pi:
7268 case Hexagon::L2_loadrub_pi: {
7269 // op: Ii
7270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7271 op &= UINT64_C(15);
7272 op <<= 5;
7273 Value |= op;
7274 // op: Rd32
7275 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7276 op &= UINT64_C(31);
7277 Value |= op;
7278 // op: Rx32
7279 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7280 op &= UINT64_C(31);
7281 op <<= 16;
7282 Value |= op;
7283 break;
7284 }
7285 case Hexagon::L2_ploadrif_io:
7286 case Hexagon::L2_ploadrifnew_io:
7287 case Hexagon::L2_ploadrit_io:
7288 case Hexagon::L2_ploadritnew_io: {
7289 // op: Ii
7290 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7291 op &= UINT64_C(252);
7292 op <<= 3;
7293 Value |= op;
7294 // op: Pt4
7295 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7296 op &= UINT64_C(3);
7297 op <<= 11;
7298 Value |= op;
7299 // op: Rs32
7300 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7301 op &= UINT64_C(31);
7302 op <<= 16;
7303 Value |= op;
7304 // op: Rd32
7305 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7306 op &= UINT64_C(31);
7307 Value |= op;
7308 break;
7309 }
7310 case Hexagon::A2_paddif:
7311 case Hexagon::A2_paddifnew:
7312 case Hexagon::A2_paddit:
7313 case Hexagon::A2_padditnew:
7314 case Hexagon::C2_muxir: {
7315 // op: Ii
7316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7317 op &= UINT64_C(255);
7318 op <<= 5;
7319 Value |= op;
7320 // op: Pu4
7321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7322 op &= UINT64_C(3);
7323 op <<= 21;
7324 Value |= op;
7325 // op: Rs32
7326 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7327 op &= UINT64_C(31);
7328 op <<= 16;
7329 Value |= op;
7330 // op: Rd32
7331 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7332 op &= UINT64_C(31);
7333 Value |= op;
7334 break;
7335 }
7336 case Hexagon::M2_accii:
7337 case Hexagon::M2_macsin:
7338 case Hexagon::M2_macsip:
7339 case Hexagon::M2_naccii: {
7340 // op: Ii
7341 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7342 op &= UINT64_C(255);
7343 op <<= 5;
7344 Value |= op;
7345 // op: Rs32
7346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7347 op &= UINT64_C(31);
7348 op <<= 16;
7349 Value |= op;
7350 // op: Rx32
7351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7352 op &= UINT64_C(31);
7353 Value |= op;
7354 break;
7355 }
7356 case Hexagon::V6_v6mpyhubs10:
7357 case Hexagon::V6_v6mpyvubs10: {
7358 // op: Ii
7359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7360 op &= UINT64_C(3);
7361 op <<= 5;
7362 Value |= op;
7363 // op: Vuu32
7364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7365 op &= UINT64_C(31);
7366 op <<= 8;
7367 Value |= op;
7368 // op: Vvv32
7369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7370 op &= UINT64_C(31);
7371 op <<= 16;
7372 Value |= op;
7373 // op: Vdd32
7374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7375 op &= UINT64_C(31);
7376 Value |= op;
7377 break;
7378 }
7379 case Hexagon::S2_pstorerhnewf_pi:
7380 case Hexagon::S2_pstorerhnewfnew_pi:
7381 case Hexagon::S2_pstorerhnewt_pi:
7382 case Hexagon::S2_pstorerhnewtnew_pi: {
7383 // op: Ii
7384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7385 op &= UINT64_C(30);
7386 op <<= 2;
7387 Value |= op;
7388 // op: Pv4
7389 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7390 op &= UINT64_C(3);
7391 Value |= op;
7392 // op: Nt8
7393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7394 op &= UINT64_C(7);
7395 op <<= 8;
7396 Value |= op;
7397 // op: Rx32
7398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7399 op &= UINT64_C(31);
7400 op <<= 16;
7401 Value |= op;
7402 break;
7403 }
7404 case Hexagon::S2_pstorerff_pi:
7405 case Hexagon::S2_pstorerffnew_pi:
7406 case Hexagon::S2_pstorerft_pi:
7407 case Hexagon::S2_pstorerftnew_pi:
7408 case Hexagon::S2_pstorerhf_pi:
7409 case Hexagon::S2_pstorerhfnew_pi:
7410 case Hexagon::S2_pstorerht_pi:
7411 case Hexagon::S2_pstorerhtnew_pi: {
7412 // op: Ii
7413 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7414 op &= UINT64_C(30);
7415 op <<= 2;
7416 Value |= op;
7417 // op: Pv4
7418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7419 op &= UINT64_C(3);
7420 Value |= op;
7421 // op: Rt32
7422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7423 op &= UINT64_C(31);
7424 op <<= 8;
7425 Value |= op;
7426 // op: Rx32
7427 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7428 op &= UINT64_C(31);
7429 op <<= 16;
7430 Value |= op;
7431 break;
7432 }
7433 case Hexagon::L2_loadbsw2_pci:
7434 case Hexagon::L2_loadbzw2_pci:
7435 case Hexagon::L2_loadrh_pci:
7436 case Hexagon::L2_loadruh_pci: {
7437 // op: Ii
7438 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7439 op &= UINT64_C(30);
7440 op <<= 4;
7441 Value |= op;
7442 // op: Mu2
7443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7444 op &= UINT64_C(1);
7445 op <<= 13;
7446 Value |= op;
7447 // op: Rd32
7448 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7449 op &= UINT64_C(31);
7450 Value |= op;
7451 // op: Rx32
7452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7453 op &= UINT64_C(31);
7454 op <<= 16;
7455 Value |= op;
7456 break;
7457 }
7458 case Hexagon::L2_loadbsw2_pi:
7459 case Hexagon::L2_loadbzw2_pi:
7460 case Hexagon::L2_loadrh_pi:
7461 case Hexagon::L2_loadruh_pi: {
7462 // op: Ii
7463 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7464 op &= UINT64_C(30);
7465 op <<= 4;
7466 Value |= op;
7467 // op: Rd32
7468 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7469 op &= UINT64_C(31);
7470 Value |= op;
7471 // op: Rx32
7472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7473 op &= UINT64_C(31);
7474 op <<= 16;
7475 Value |= op;
7476 break;
7477 }
7478 case Hexagon::S2_insert: {
7479 // op: Ii
7480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7481 op &= UINT64_C(31);
7482 op <<= 8;
7483 Value |= op;
7484 // op: II
7485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7486 Value |= (op & UINT64_C(24)) << 18;
7487 Value |= (op & UINT64_C(7)) << 5;
7488 // op: Rs32
7489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7490 op &= UINT64_C(31);
7491 op <<= 16;
7492 Value |= op;
7493 // op: Rx32
7494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7495 op &= UINT64_C(31);
7496 Value |= op;
7497 break;
7498 }
7499 case Hexagon::S2_asl_i_r_acc:
7500 case Hexagon::S2_asl_i_r_and:
7501 case Hexagon::S2_asl_i_r_nac:
7502 case Hexagon::S2_asl_i_r_or:
7503 case Hexagon::S2_asl_i_r_xacc:
7504 case Hexagon::S2_asr_i_r_acc:
7505 case Hexagon::S2_asr_i_r_and:
7506 case Hexagon::S2_asr_i_r_nac:
7507 case Hexagon::S2_asr_i_r_or:
7508 case Hexagon::S2_lsr_i_r_acc:
7509 case Hexagon::S2_lsr_i_r_and:
7510 case Hexagon::S2_lsr_i_r_nac:
7511 case Hexagon::S2_lsr_i_r_or:
7512 case Hexagon::S2_lsr_i_r_xacc:
7513 case Hexagon::S6_rol_i_r_acc:
7514 case Hexagon::S6_rol_i_r_and:
7515 case Hexagon::S6_rol_i_r_nac:
7516 case Hexagon::S6_rol_i_r_or:
7517 case Hexagon::S6_rol_i_r_xacc: {
7518 // op: Ii
7519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7520 op &= UINT64_C(31);
7521 op <<= 8;
7522 Value |= op;
7523 // op: Rs32
7524 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7525 op &= UINT64_C(31);
7526 op <<= 16;
7527 Value |= op;
7528 // op: Rx32
7529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7530 op &= UINT64_C(31);
7531 Value |= op;
7532 break;
7533 }
7534 case Hexagon::L2_ploadrdf_io:
7535 case Hexagon::L2_ploadrdfnew_io:
7536 case Hexagon::L2_ploadrdt_io:
7537 case Hexagon::L2_ploadrdtnew_io: {
7538 // op: Ii
7539 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7540 op &= UINT64_C(504);
7541 op <<= 2;
7542 Value |= op;
7543 // op: Pt4
7544 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7545 op &= UINT64_C(3);
7546 op <<= 11;
7547 Value |= op;
7548 // op: Rs32
7549 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7550 op &= UINT64_C(31);
7551 op <<= 16;
7552 Value |= op;
7553 // op: Rdd32
7554 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7555 op &= UINT64_C(31);
7556 Value |= op;
7557 break;
7558 }
7559 case Hexagon::S2_pstorerinewf_pi:
7560 case Hexagon::S2_pstorerinewfnew_pi:
7561 case Hexagon::S2_pstorerinewt_pi:
7562 case Hexagon::S2_pstorerinewtnew_pi: {
7563 // op: Ii
7564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7565 op &= UINT64_C(60);
7566 op <<= 1;
7567 Value |= op;
7568 // op: Pv4
7569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7570 op &= UINT64_C(3);
7571 Value |= op;
7572 // op: Nt8
7573 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7574 op &= UINT64_C(7);
7575 op <<= 8;
7576 Value |= op;
7577 // op: Rx32
7578 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7579 op &= UINT64_C(31);
7580 op <<= 16;
7581 Value |= op;
7582 break;
7583 }
7584 case Hexagon::S2_pstorerif_pi:
7585 case Hexagon::S2_pstorerifnew_pi:
7586 case Hexagon::S2_pstorerit_pi:
7587 case Hexagon::S2_pstoreritnew_pi: {
7588 // op: Ii
7589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7590 op &= UINT64_C(60);
7591 op <<= 1;
7592 Value |= op;
7593 // op: Pv4
7594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7595 op &= UINT64_C(3);
7596 Value |= op;
7597 // op: Rt32
7598 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7599 op &= UINT64_C(31);
7600 op <<= 8;
7601 Value |= op;
7602 // op: Rx32
7603 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7604 op &= UINT64_C(31);
7605 op <<= 16;
7606 Value |= op;
7607 break;
7608 }
7609 case Hexagon::L2_loadri_pci: {
7610 // op: Ii
7611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7612 op &= UINT64_C(60);
7613 op <<= 3;
7614 Value |= op;
7615 // op: Mu2
7616 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7617 op &= UINT64_C(1);
7618 op <<= 13;
7619 Value |= op;
7620 // op: Rd32
7621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7622 op &= UINT64_C(31);
7623 Value |= op;
7624 // op: Rx32
7625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7626 op &= UINT64_C(31);
7627 op <<= 16;
7628 Value |= op;
7629 break;
7630 }
7631 case Hexagon::L2_loadbsw4_pci:
7632 case Hexagon::L2_loadbzw4_pci: {
7633 // op: Ii
7634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7635 op &= UINT64_C(60);
7636 op <<= 3;
7637 Value |= op;
7638 // op: Mu2
7639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7640 op &= UINT64_C(1);
7641 op <<= 13;
7642 Value |= op;
7643 // op: Rdd32
7644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7645 op &= UINT64_C(31);
7646 Value |= op;
7647 // op: Rx32
7648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7649 op &= UINT64_C(31);
7650 op <<= 16;
7651 Value |= op;
7652 break;
7653 }
7654 case Hexagon::L2_loadri_pi: {
7655 // op: Ii
7656 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7657 op &= UINT64_C(60);
7658 op <<= 3;
7659 Value |= op;
7660 // op: Rd32
7661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7662 op &= UINT64_C(31);
7663 Value |= op;
7664 // op: Rx32
7665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7666 op &= UINT64_C(31);
7667 op <<= 16;
7668 Value |= op;
7669 break;
7670 }
7671 case Hexagon::L2_loadbsw4_pi:
7672 case Hexagon::L2_loadbzw4_pi: {
7673 // op: Ii
7674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7675 op &= UINT64_C(60);
7676 op <<= 3;
7677 Value |= op;
7678 // op: Rdd32
7679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7680 op &= UINT64_C(31);
7681 Value |= op;
7682 // op: Rx32
7683 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7684 op &= UINT64_C(31);
7685 op <<= 16;
7686 Value |= op;
7687 break;
7688 }
7689 case Hexagon::L2_ploadrbf_io:
7690 case Hexagon::L2_ploadrbfnew_io:
7691 case Hexagon::L2_ploadrbt_io:
7692 case Hexagon::L2_ploadrbtnew_io:
7693 case Hexagon::L2_ploadrubf_io:
7694 case Hexagon::L2_ploadrubfnew_io:
7695 case Hexagon::L2_ploadrubt_io:
7696 case Hexagon::L2_ploadrubtnew_io: {
7697 // op: Ii
7698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7699 op &= UINT64_C(63);
7700 op <<= 5;
7701 Value |= op;
7702 // op: Pt4
7703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7704 op &= UINT64_C(3);
7705 op <<= 11;
7706 Value |= op;
7707 // op: Rs32
7708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7709 op &= UINT64_C(31);
7710 op <<= 16;
7711 Value |= op;
7712 // op: Rd32
7713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7714 op &= UINT64_C(31);
7715 Value |= op;
7716 break;
7717 }
7718 case Hexagon::S2_insertp: {
7719 // op: Ii
7720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7721 op &= UINT64_C(63);
7722 op <<= 8;
7723 Value |= op;
7724 // op: II
7725 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7726 Value |= (op & UINT64_C(56)) << 18;
7727 Value |= (op & UINT64_C(7)) << 5;
7728 // op: Rss32
7729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7730 op &= UINT64_C(31);
7731 op <<= 16;
7732 Value |= op;
7733 // op: Rxx32
7734 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7735 op &= UINT64_C(31);
7736 Value |= op;
7737 break;
7738 }
7739 case Hexagon::S2_asl_i_p_acc:
7740 case Hexagon::S2_asl_i_p_and:
7741 case Hexagon::S2_asl_i_p_nac:
7742 case Hexagon::S2_asl_i_p_or:
7743 case Hexagon::S2_asl_i_p_xacc:
7744 case Hexagon::S2_asr_i_p_acc:
7745 case Hexagon::S2_asr_i_p_and:
7746 case Hexagon::S2_asr_i_p_nac:
7747 case Hexagon::S2_asr_i_p_or:
7748 case Hexagon::S2_lsr_i_p_acc:
7749 case Hexagon::S2_lsr_i_p_and:
7750 case Hexagon::S2_lsr_i_p_nac:
7751 case Hexagon::S2_lsr_i_p_or:
7752 case Hexagon::S2_lsr_i_p_xacc:
7753 case Hexagon::S6_rol_i_p_acc:
7754 case Hexagon::S6_rol_i_p_and:
7755 case Hexagon::S6_rol_i_p_nac:
7756 case Hexagon::S6_rol_i_p_or:
7757 case Hexagon::S6_rol_i_p_xacc: {
7758 // op: Ii
7759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7760 op &= UINT64_C(63);
7761 op <<= 8;
7762 Value |= op;
7763 // op: Rss32
7764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7765 op &= UINT64_C(31);
7766 op <<= 16;
7767 Value |= op;
7768 // op: Rxx32
7769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7770 op &= UINT64_C(31);
7771 Value |= op;
7772 break;
7773 }
7774 case Hexagon::S2_vspliceib: {
7775 // op: Ii
7776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7777 op &= UINT64_C(7);
7778 op <<= 5;
7779 Value |= op;
7780 // op: Rss32
7781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7782 op &= UINT64_C(31);
7783 op <<= 16;
7784 Value |= op;
7785 // op: Rtt32
7786 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7787 op &= UINT64_C(31);
7788 op <<= 8;
7789 Value |= op;
7790 // op: Rdd32
7791 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7792 op &= UINT64_C(31);
7793 Value |= op;
7794 break;
7795 }
7796 case Hexagon::S2_addasl_rrri: {
7797 // op: Ii
7798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7799 op &= UINT64_C(7);
7800 op <<= 5;
7801 Value |= op;
7802 // op: Rt32
7803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7804 op &= UINT64_C(31);
7805 op <<= 8;
7806 Value |= op;
7807 // op: Rs32
7808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7809 op &= UINT64_C(31);
7810 op <<= 16;
7811 Value |= op;
7812 // op: Rd32
7813 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7814 op &= UINT64_C(31);
7815 Value |= op;
7816 break;
7817 }
7818 case Hexagon::S2_valignib: {
7819 // op: Ii
7820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7821 op &= UINT64_C(7);
7822 op <<= 5;
7823 Value |= op;
7824 // op: Rtt32
7825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7826 op &= UINT64_C(31);
7827 op <<= 8;
7828 Value |= op;
7829 // op: Rss32
7830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7831 op &= UINT64_C(31);
7832 op <<= 16;
7833 Value |= op;
7834 // op: Rdd32
7835 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7836 op &= UINT64_C(31);
7837 Value |= op;
7838 break;
7839 }
7840 case Hexagon::V6_valignbi:
7841 case Hexagon::V6_vlalignbi:
7842 case Hexagon::V6_vlutvvbi: {
7843 // op: Ii
7844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7845 op &= UINT64_C(7);
7846 op <<= 5;
7847 Value |= op;
7848 // op: Vu32
7849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7850 op &= UINT64_C(31);
7851 op <<= 8;
7852 Value |= op;
7853 // op: Vv32
7854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7855 op &= UINT64_C(31);
7856 op <<= 16;
7857 Value |= op;
7858 // op: Vd32
7859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7860 op &= UINT64_C(31);
7861 Value |= op;
7862 break;
7863 }
7864 case Hexagon::V6_vlutvwhi: {
7865 // op: Ii
7866 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7867 op &= UINT64_C(7);
7868 op <<= 5;
7869 Value |= op;
7870 // op: Vu32
7871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7872 op &= UINT64_C(31);
7873 op <<= 8;
7874 Value |= op;
7875 // op: Vv32
7876 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
7877 op &= UINT64_C(31);
7878 op <<= 16;
7879 Value |= op;
7880 // op: Vdd32
7881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7882 op &= UINT64_C(31);
7883 Value |= op;
7884 break;
7885 }
7886 case Hexagon::V6_vS32b_new_npred_pi:
7887 case Hexagon::V6_vS32b_new_pred_pi:
7888 case Hexagon::V6_vS32b_nt_new_npred_pi:
7889 case Hexagon::V6_vS32b_nt_new_pred_pi: {
7890 // op: Ii
7891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7892 op &= UINT64_C(7);
7893 op <<= 8;
7894 Value |= op;
7895 // op: Pv4
7896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7897 op &= UINT64_C(3);
7898 op <<= 11;
7899 Value |= op;
7900 // op: Os8
7901 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7902 op &= UINT64_C(7);
7903 Value |= op;
7904 // op: Rx32
7905 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7906 op &= UINT64_C(31);
7907 op <<= 16;
7908 Value |= op;
7909 break;
7910 }
7911 case Hexagon::V6_zLd_pred_pi: {
7912 // op: Ii
7913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7914 op &= UINT64_C(7);
7915 op <<= 8;
7916 Value |= op;
7917 // op: Pv4
7918 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7919 op &= UINT64_C(3);
7920 op <<= 11;
7921 Value |= op;
7922 // op: Rx32
7923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7924 op &= UINT64_C(31);
7925 op <<= 16;
7926 Value |= op;
7927 break;
7928 }
7929 case Hexagon::V6_vS32Ub_npred_pi:
7930 case Hexagon::V6_vS32Ub_pred_pi:
7931 case Hexagon::V6_vS32b_npred_pi:
7932 case Hexagon::V6_vS32b_nt_npred_pi:
7933 case Hexagon::V6_vS32b_nt_pred_pi:
7934 case Hexagon::V6_vS32b_pred_pi: {
7935 // op: Ii
7936 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7937 op &= UINT64_C(7);
7938 op <<= 8;
7939 Value |= op;
7940 // op: Pv4
7941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7942 op &= UINT64_C(3);
7943 op <<= 11;
7944 Value |= op;
7945 // op: Vs32
7946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7947 op &= UINT64_C(31);
7948 Value |= op;
7949 // op: Rx32
7950 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7951 op &= UINT64_C(31);
7952 op <<= 16;
7953 Value |= op;
7954 break;
7955 }
7956 case Hexagon::V6_vS32b_nqpred_pi:
7957 case Hexagon::V6_vS32b_nt_nqpred_pi:
7958 case Hexagon::V6_vS32b_nt_qpred_pi:
7959 case Hexagon::V6_vS32b_qpred_pi: {
7960 // op: Ii
7961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7962 op &= UINT64_C(7);
7963 op <<= 8;
7964 Value |= op;
7965 // op: Qv4
7966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7967 op &= UINT64_C(3);
7968 op <<= 11;
7969 Value |= op;
7970 // op: Vs32
7971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
7972 op &= UINT64_C(31);
7973 Value |= op;
7974 // op: Rx32
7975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7976 op &= UINT64_C(31);
7977 op <<= 16;
7978 Value |= op;
7979 break;
7980 }
7981 case Hexagon::V6_vL32Ub_pi:
7982 case Hexagon::V6_vL32b_cur_pi:
7983 case Hexagon::V6_vL32b_nt_cur_pi:
7984 case Hexagon::V6_vL32b_nt_pi:
7985 case Hexagon::V6_vL32b_nt_tmp_pi:
7986 case Hexagon::V6_vL32b_pi:
7987 case Hexagon::V6_vL32b_tmp_pi: {
7988 // op: Ii
7989 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
7990 op &= UINT64_C(7);
7991 op <<= 8;
7992 Value |= op;
7993 // op: Vd32
7994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
7995 op &= UINT64_C(31);
7996 Value |= op;
7997 // op: Rx32
7998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
7999 op &= UINT64_C(31);
8000 op <<= 16;
8001 Value |= op;
8002 break;
8003 }
8004 case Hexagon::S4_vrcrotate_acc: {
8005 // op: Ii
8006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8007 Value |= (op & UINT64_C(2)) << 12;
8008 Value |= (op & UINT64_C(1)) << 5;
8009 // op: Rss32
8010 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8011 op &= UINT64_C(31);
8012 op <<= 16;
8013 Value |= op;
8014 // op: Rt32
8015 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8016 op &= UINT64_C(31);
8017 op <<= 8;
8018 Value |= op;
8019 // op: Rxx32
8020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8021 op &= UINT64_C(31);
8022 Value |= op;
8023 break;
8024 }
8025 case Hexagon::L4_ploadrbf_rr:
8026 case Hexagon::L4_ploadrbfnew_rr:
8027 case Hexagon::L4_ploadrbt_rr:
8028 case Hexagon::L4_ploadrbtnew_rr:
8029 case Hexagon::L4_ploadrhf_rr:
8030 case Hexagon::L4_ploadrhfnew_rr:
8031 case Hexagon::L4_ploadrht_rr:
8032 case Hexagon::L4_ploadrhtnew_rr:
8033 case Hexagon::L4_ploadrif_rr:
8034 case Hexagon::L4_ploadrifnew_rr:
8035 case Hexagon::L4_ploadrit_rr:
8036 case Hexagon::L4_ploadritnew_rr:
8037 case Hexagon::L4_ploadrubf_rr:
8038 case Hexagon::L4_ploadrubfnew_rr:
8039 case Hexagon::L4_ploadrubt_rr:
8040 case Hexagon::L4_ploadrubtnew_rr:
8041 case Hexagon::L4_ploadruhf_rr:
8042 case Hexagon::L4_ploadruhfnew_rr:
8043 case Hexagon::L4_ploadruht_rr:
8044 case Hexagon::L4_ploadruhtnew_rr: {
8045 // op: Ii
8046 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8047 Value |= (op & UINT64_C(2)) << 12;
8048 Value |= (op & UINT64_C(1)) << 7;
8049 // op: Pv4
8050 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8051 op &= UINT64_C(3);
8052 op <<= 5;
8053 Value |= op;
8054 // op: Rs32
8055 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8056 op &= UINT64_C(31);
8057 op <<= 16;
8058 Value |= op;
8059 // op: Rt32
8060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8061 op &= UINT64_C(31);
8062 op <<= 8;
8063 Value |= op;
8064 // op: Rd32
8065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8066 op &= UINT64_C(31);
8067 Value |= op;
8068 break;
8069 }
8070 case Hexagon::L4_ploadrdf_rr:
8071 case Hexagon::L4_ploadrdfnew_rr:
8072 case Hexagon::L4_ploadrdt_rr:
8073 case Hexagon::L4_ploadrdtnew_rr: {
8074 // op: Ii
8075 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8076 Value |= (op & UINT64_C(2)) << 12;
8077 Value |= (op & UINT64_C(1)) << 7;
8078 // op: Pv4
8079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8080 op &= UINT64_C(3);
8081 op <<= 5;
8082 Value |= op;
8083 // op: Rs32
8084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8085 op &= UINT64_C(31);
8086 op <<= 16;
8087 Value |= op;
8088 // op: Rt32
8089 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8090 op &= UINT64_C(31);
8091 op <<= 8;
8092 Value |= op;
8093 // op: Rdd32
8094 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8095 op &= UINT64_C(31);
8096 Value |= op;
8097 break;
8098 }
8099 case Hexagon::V6_vrmpybusi_acc:
8100 case Hexagon::V6_vrmpyubi_acc:
8101 case Hexagon::V6_vrsadubi_acc: {
8102 // op: Ii
8103 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8104 op &= UINT64_C(1);
8105 op <<= 5;
8106 Value |= op;
8107 // op: Vuu32
8108 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8109 op &= UINT64_C(31);
8110 op <<= 8;
8111 Value |= op;
8112 // op: Rt32
8113 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8114 op &= UINT64_C(31);
8115 op <<= 16;
8116 Value |= op;
8117 // op: Vxx32
8118 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8119 op &= UINT64_C(31);
8120 Value |= op;
8121 break;
8122 }
8123 case Hexagon::L2_ploadrdf_pi:
8124 case Hexagon::L2_ploadrdfnew_pi:
8125 case Hexagon::L2_ploadrdt_pi:
8126 case Hexagon::L2_ploadrdtnew_pi: {
8127 // op: Ii
8128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8129 op &= UINT64_C(120);
8130 op <<= 2;
8131 Value |= op;
8132 // op: Pt4
8133 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8134 op &= UINT64_C(3);
8135 op <<= 9;
8136 Value |= op;
8137 // op: Rdd32
8138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8139 op &= UINT64_C(31);
8140 Value |= op;
8141 // op: Rx32
8142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8143 op &= UINT64_C(31);
8144 op <<= 16;
8145 Value |= op;
8146 break;
8147 }
8148 case Hexagon::L2_loadalignb_pci: {
8149 // op: Ii
8150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8151 op &= UINT64_C(15);
8152 op <<= 5;
8153 Value |= op;
8154 // op: Mu2
8155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
8156 op &= UINT64_C(1);
8157 op <<= 13;
8158 Value |= op;
8159 // op: Ryy32
8160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8161 op &= UINT64_C(31);
8162 Value |= op;
8163 // op: Rx32
8164 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8165 op &= UINT64_C(31);
8166 op <<= 16;
8167 Value |= op;
8168 break;
8169 }
8170 case Hexagon::L2_ploadrbf_pi:
8171 case Hexagon::L2_ploadrbfnew_pi:
8172 case Hexagon::L2_ploadrbt_pi:
8173 case Hexagon::L2_ploadrbtnew_pi:
8174 case Hexagon::L2_ploadrubf_pi:
8175 case Hexagon::L2_ploadrubfnew_pi:
8176 case Hexagon::L2_ploadrubt_pi:
8177 case Hexagon::L2_ploadrubtnew_pi: {
8178 // op: Ii
8179 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8180 op &= UINT64_C(15);
8181 op <<= 5;
8182 Value |= op;
8183 // op: Pt4
8184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8185 op &= UINT64_C(3);
8186 op <<= 9;
8187 Value |= op;
8188 // op: Rd32
8189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8190 op &= UINT64_C(31);
8191 Value |= op;
8192 // op: Rx32
8193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8194 op &= UINT64_C(31);
8195 op <<= 16;
8196 Value |= op;
8197 break;
8198 }
8199 case Hexagon::L2_loadalignb_pi: {
8200 // op: Ii
8201 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8202 op &= UINT64_C(15);
8203 op <<= 5;
8204 Value |= op;
8205 // op: Ryy32
8206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8207 op &= UINT64_C(31);
8208 Value |= op;
8209 // op: Rx32
8210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8211 op &= UINT64_C(31);
8212 op <<= 16;
8213 Value |= op;
8214 break;
8215 }
8216 case Hexagon::V6_v6mpyhubs10_vxx:
8217 case Hexagon::V6_v6mpyvubs10_vxx: {
8218 // op: Ii
8219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8220 op &= UINT64_C(3);
8221 op <<= 5;
8222 Value |= op;
8223 // op: Vuu32
8224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8225 op &= UINT64_C(31);
8226 op <<= 8;
8227 Value |= op;
8228 // op: Vvv32
8229 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8230 op &= UINT64_C(31);
8231 op <<= 16;
8232 Value |= op;
8233 // op: Vxx32
8234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8235 op &= UINT64_C(31);
8236 Value |= op;
8237 break;
8238 }
8239 case Hexagon::L2_loadalignh_pci: {
8240 // op: Ii
8241 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8242 op &= UINT64_C(30);
8243 op <<= 4;
8244 Value |= op;
8245 // op: Mu2
8246 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
8247 op &= UINT64_C(1);
8248 op <<= 13;
8249 Value |= op;
8250 // op: Ryy32
8251 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8252 op &= UINT64_C(31);
8253 Value |= op;
8254 // op: Rx32
8255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8256 op &= UINT64_C(31);
8257 op <<= 16;
8258 Value |= op;
8259 break;
8260 }
8261 case Hexagon::L2_ploadrhf_pi:
8262 case Hexagon::L2_ploadrhfnew_pi:
8263 case Hexagon::L2_ploadrht_pi:
8264 case Hexagon::L2_ploadrhtnew_pi:
8265 case Hexagon::L2_ploadruhf_pi:
8266 case Hexagon::L2_ploadruhfnew_pi:
8267 case Hexagon::L2_ploadruht_pi:
8268 case Hexagon::L2_ploadruhtnew_pi: {
8269 // op: Ii
8270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8271 op &= UINT64_C(30);
8272 op <<= 4;
8273 Value |= op;
8274 // op: Pt4
8275 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8276 op &= UINT64_C(3);
8277 op <<= 9;
8278 Value |= op;
8279 // op: Rd32
8280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8281 op &= UINT64_C(31);
8282 Value |= op;
8283 // op: Rx32
8284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8285 op &= UINT64_C(31);
8286 op <<= 16;
8287 Value |= op;
8288 break;
8289 }
8290 case Hexagon::L2_loadalignh_pi: {
8291 // op: Ii
8292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8293 op &= UINT64_C(30);
8294 op <<= 4;
8295 Value |= op;
8296 // op: Ryy32
8297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8298 op &= UINT64_C(31);
8299 Value |= op;
8300 // op: Rx32
8301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8302 op &= UINT64_C(31);
8303 op <<= 16;
8304 Value |= op;
8305 break;
8306 }
8307 case Hexagon::L2_ploadrif_pi:
8308 case Hexagon::L2_ploadrifnew_pi:
8309 case Hexagon::L2_ploadrit_pi:
8310 case Hexagon::L2_ploadritnew_pi: {
8311 // op: Ii
8312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8313 op &= UINT64_C(60);
8314 op <<= 3;
8315 Value |= op;
8316 // op: Pt4
8317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8318 op &= UINT64_C(3);
8319 op <<= 9;
8320 Value |= op;
8321 // op: Rd32
8322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8323 op &= UINT64_C(31);
8324 Value |= op;
8325 // op: Rx32
8326 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8327 op &= UINT64_C(31);
8328 op <<= 16;
8329 Value |= op;
8330 break;
8331 }
8332 case Hexagon::V6_vlutvvb_oracci: {
8333 // op: Ii
8334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8335 op &= UINT64_C(7);
8336 op <<= 5;
8337 Value |= op;
8338 // op: Vu32
8339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8340 op &= UINT64_C(31);
8341 op <<= 8;
8342 Value |= op;
8343 // op: Vv32
8344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8345 op &= UINT64_C(31);
8346 op <<= 16;
8347 Value |= op;
8348 // op: Vx32
8349 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8350 op &= UINT64_C(31);
8351 Value |= op;
8352 break;
8353 }
8354 case Hexagon::V6_vlutvwh_oracci: {
8355 // op: Ii
8356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8357 op &= UINT64_C(7);
8358 op <<= 5;
8359 Value |= op;
8360 // op: Vu32
8361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8362 op &= UINT64_C(31);
8363 op <<= 8;
8364 Value |= op;
8365 // op: Vv32
8366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8367 op &= UINT64_C(31);
8368 op <<= 16;
8369 Value |= op;
8370 // op: Vxx32
8371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8372 op &= UINT64_C(31);
8373 Value |= op;
8374 break;
8375 }
8376 case Hexagon::V6_vL32b_cur_npred_pi:
8377 case Hexagon::V6_vL32b_cur_pred_pi:
8378 case Hexagon::V6_vL32b_npred_pi:
8379 case Hexagon::V6_vL32b_nt_cur_npred_pi:
8380 case Hexagon::V6_vL32b_nt_cur_pred_pi:
8381 case Hexagon::V6_vL32b_nt_npred_pi:
8382 case Hexagon::V6_vL32b_nt_pred_pi:
8383 case Hexagon::V6_vL32b_nt_tmp_npred_pi:
8384 case Hexagon::V6_vL32b_nt_tmp_pred_pi:
8385 case Hexagon::V6_vL32b_pred_pi:
8386 case Hexagon::V6_vL32b_tmp_npred_pi:
8387 case Hexagon::V6_vL32b_tmp_pred_pi: {
8388 // op: Ii
8389 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8390 op &= UINT64_C(7);
8391 op <<= 8;
8392 Value |= op;
8393 // op: Pv4
8394 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8395 op &= UINT64_C(3);
8396 op <<= 11;
8397 Value |= op;
8398 // op: Vd32
8399 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8400 op &= UINT64_C(31);
8401 Value |= op;
8402 // op: Rx32
8403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8404 op &= UINT64_C(31);
8405 op <<= 16;
8406 Value |= op;
8407 break;
8408 }
8409 case Hexagon::S2_storerbnew_pbr:
8410 case Hexagon::S2_storerbnew_pcr:
8411 case Hexagon::S2_storerbnew_pr:
8412 case Hexagon::S2_storerhnew_pbr:
8413 case Hexagon::S2_storerhnew_pcr:
8414 case Hexagon::S2_storerhnew_pr:
8415 case Hexagon::S2_storerinew_pbr:
8416 case Hexagon::S2_storerinew_pcr:
8417 case Hexagon::S2_storerinew_pr: {
8418 // op: Mu2
8419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8420 op &= UINT64_C(1);
8421 op <<= 13;
8422 Value |= op;
8423 // op: Nt8
8424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8425 op &= UINT64_C(7);
8426 op <<= 8;
8427 Value |= op;
8428 // op: Rx32
8429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8430 op &= UINT64_C(31);
8431 op <<= 16;
8432 Value |= op;
8433 break;
8434 }
8435 case Hexagon::V6_vS32b_new_ppu:
8436 case Hexagon::V6_vS32b_nt_new_ppu: {
8437 // op: Mu2
8438 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8439 op &= UINT64_C(1);
8440 op <<= 13;
8441 Value |= op;
8442 // op: Os8
8443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8444 op &= UINT64_C(7);
8445 Value |= op;
8446 // op: Rx32
8447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8448 op &= UINT64_C(31);
8449 op <<= 16;
8450 Value |= op;
8451 break;
8452 }
8453 case Hexagon::S2_storerb_pbr:
8454 case Hexagon::S2_storerb_pcr:
8455 case Hexagon::S2_storerb_pr:
8456 case Hexagon::S2_storerf_pbr:
8457 case Hexagon::S2_storerf_pcr:
8458 case Hexagon::S2_storerf_pr:
8459 case Hexagon::S2_storerh_pbr:
8460 case Hexagon::S2_storerh_pcr:
8461 case Hexagon::S2_storerh_pr:
8462 case Hexagon::S2_storeri_pbr:
8463 case Hexagon::S2_storeri_pcr:
8464 case Hexagon::S2_storeri_pr: {
8465 // op: Mu2
8466 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8467 op &= UINT64_C(1);
8468 op <<= 13;
8469 Value |= op;
8470 // op: Rt32
8471 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8472 op &= UINT64_C(31);
8473 op <<= 8;
8474 Value |= op;
8475 // op: Rx32
8476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8477 op &= UINT64_C(31);
8478 op <<= 16;
8479 Value |= op;
8480 break;
8481 }
8482 case Hexagon::S2_storerd_pbr:
8483 case Hexagon::S2_storerd_pcr:
8484 case Hexagon::S2_storerd_pr: {
8485 // op: Mu2
8486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8487 op &= UINT64_C(1);
8488 op <<= 13;
8489 Value |= op;
8490 // op: Rtt32
8491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8492 op &= UINT64_C(31);
8493 op <<= 8;
8494 Value |= op;
8495 // op: Rx32
8496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8497 op &= UINT64_C(31);
8498 op <<= 16;
8499 Value |= op;
8500 break;
8501 }
8502 case Hexagon::V6_vS32b_srls_ppu:
8503 case Hexagon::V6_zLd_ppu: {
8504 // op: Mu2
8505 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8506 op &= UINT64_C(1);
8507 op <<= 13;
8508 Value |= op;
8509 // op: Rx32
8510 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8511 op &= UINT64_C(31);
8512 op <<= 16;
8513 Value |= op;
8514 break;
8515 }
8516 case Hexagon::V6_vS32Ub_ppu:
8517 case Hexagon::V6_vS32b_nt_ppu:
8518 case Hexagon::V6_vS32b_ppu: {
8519 // op: Mu2
8520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8521 op &= UINT64_C(1);
8522 op <<= 13;
8523 Value |= op;
8524 // op: Vs32
8525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8526 op &= UINT64_C(31);
8527 Value |= op;
8528 // op: Rx32
8529 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8530 op &= UINT64_C(31);
8531 op <<= 16;
8532 Value |= op;
8533 break;
8534 }
8535 case Hexagon::L2_loadbsw2_pbr:
8536 case Hexagon::L2_loadbsw2_pcr:
8537 case Hexagon::L2_loadbsw2_pr:
8538 case Hexagon::L2_loadbzw2_pbr:
8539 case Hexagon::L2_loadbzw2_pcr:
8540 case Hexagon::L2_loadbzw2_pr:
8541 case Hexagon::L2_loadrb_pbr:
8542 case Hexagon::L2_loadrb_pcr:
8543 case Hexagon::L2_loadrb_pr:
8544 case Hexagon::L2_loadrh_pbr:
8545 case Hexagon::L2_loadrh_pcr:
8546 case Hexagon::L2_loadrh_pr:
8547 case Hexagon::L2_loadri_pbr:
8548 case Hexagon::L2_loadri_pcr:
8549 case Hexagon::L2_loadri_pr:
8550 case Hexagon::L2_loadrub_pbr:
8551 case Hexagon::L2_loadrub_pcr:
8552 case Hexagon::L2_loadrub_pr:
8553 case Hexagon::L2_loadruh_pbr:
8554 case Hexagon::L2_loadruh_pcr:
8555 case Hexagon::L2_loadruh_pr: {
8556 // op: Mu2
8557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8558 op &= UINT64_C(1);
8559 op <<= 13;
8560 Value |= op;
8561 // op: Rd32
8562 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8563 op &= UINT64_C(31);
8564 Value |= op;
8565 // op: Rx32
8566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8567 op &= UINT64_C(31);
8568 op <<= 16;
8569 Value |= op;
8570 break;
8571 }
8572 case Hexagon::L2_loadbsw4_pbr:
8573 case Hexagon::L2_loadbsw4_pcr:
8574 case Hexagon::L2_loadbsw4_pr:
8575 case Hexagon::L2_loadbzw4_pbr:
8576 case Hexagon::L2_loadbzw4_pcr:
8577 case Hexagon::L2_loadbzw4_pr:
8578 case Hexagon::L2_loadrd_pbr:
8579 case Hexagon::L2_loadrd_pcr:
8580 case Hexagon::L2_loadrd_pr: {
8581 // op: Mu2
8582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8583 op &= UINT64_C(1);
8584 op <<= 13;
8585 Value |= op;
8586 // op: Rdd32
8587 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8588 op &= UINT64_C(31);
8589 Value |= op;
8590 // op: Rx32
8591 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8592 op &= UINT64_C(31);
8593 op <<= 16;
8594 Value |= op;
8595 break;
8596 }
8597 case Hexagon::V6_vL32Ub_ppu:
8598 case Hexagon::V6_vL32b_cur_ppu:
8599 case Hexagon::V6_vL32b_nt_cur_ppu:
8600 case Hexagon::V6_vL32b_nt_ppu:
8601 case Hexagon::V6_vL32b_nt_tmp_ppu:
8602 case Hexagon::V6_vL32b_ppu:
8603 case Hexagon::V6_vL32b_tmp_ppu: {
8604 // op: Mu2
8605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8606 op &= UINT64_C(1);
8607 op <<= 13;
8608 Value |= op;
8609 // op: Vd32
8610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8611 op &= UINT64_C(31);
8612 Value |= op;
8613 // op: Rx32
8614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8615 op &= UINT64_C(31);
8616 op <<= 16;
8617 Value |= op;
8618 break;
8619 }
8620 case Hexagon::L2_loadalignb_pbr:
8621 case Hexagon::L2_loadalignb_pcr:
8622 case Hexagon::L2_loadalignb_pr:
8623 case Hexagon::L2_loadalignh_pbr:
8624 case Hexagon::L2_loadalignh_pcr:
8625 case Hexagon::L2_loadalignh_pr: {
8626 // op: Mu2
8627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
8628 op &= UINT64_C(1);
8629 op <<= 13;
8630 Value |= op;
8631 // op: Ryy32
8632 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8633 op &= UINT64_C(31);
8634 Value |= op;
8635 // op: Rx32
8636 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8637 op &= UINT64_C(31);
8638 op <<= 16;
8639 Value |= op;
8640 break;
8641 }
8642 case Hexagon::C2_all8:
8643 case Hexagon::C2_any8:
8644 case Hexagon::C2_not: {
8645 // op: Ps4
8646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8647 op &= UINT64_C(3);
8648 op <<= 16;
8649 Value |= op;
8650 // op: Pd4
8651 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8652 op &= UINT64_C(3);
8653 Value |= op;
8654 break;
8655 }
8656 case Hexagon::C2_xor:
8657 case Hexagon::C4_fastcorner9:
8658 case Hexagon::C4_fastcorner9_not: {
8659 // op: Ps4
8660 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8661 op &= UINT64_C(3);
8662 op <<= 16;
8663 Value |= op;
8664 // op: Pt4
8665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8666 op &= UINT64_C(3);
8667 op <<= 8;
8668 Value |= op;
8669 // op: Pd4
8670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8671 op &= UINT64_C(3);
8672 Value |= op;
8673 break;
8674 }
8675 case Hexagon::C4_and_and:
8676 case Hexagon::C4_and_andn:
8677 case Hexagon::C4_and_or:
8678 case Hexagon::C4_and_orn:
8679 case Hexagon::C4_or_and:
8680 case Hexagon::C4_or_andn:
8681 case Hexagon::C4_or_or:
8682 case Hexagon::C4_or_orn: {
8683 // op: Ps4
8684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8685 op &= UINT64_C(3);
8686 op <<= 16;
8687 Value |= op;
8688 // op: Pt4
8689 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8690 op &= UINT64_C(3);
8691 op <<= 8;
8692 Value |= op;
8693 // op: Pu4
8694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8695 op &= UINT64_C(3);
8696 op <<= 6;
8697 Value |= op;
8698 // op: Pd4
8699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8700 op &= UINT64_C(3);
8701 Value |= op;
8702 break;
8703 }
8704 case Hexagon::C2_vitpack: {
8705 // op: Ps4
8706 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8707 op &= UINT64_C(3);
8708 op <<= 16;
8709 Value |= op;
8710 // op: Pt4
8711 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8712 op &= UINT64_C(3);
8713 op <<= 8;
8714 Value |= op;
8715 // op: Rd32
8716 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8717 op &= UINT64_C(31);
8718 Value |= op;
8719 break;
8720 }
8721 case Hexagon::C2_tfrpr: {
8722 // op: Ps4
8723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8724 op &= UINT64_C(3);
8725 op <<= 16;
8726 Value |= op;
8727 // op: Rd32
8728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8729 op &= UINT64_C(31);
8730 Value |= op;
8731 break;
8732 }
8733 case Hexagon::V6_vcmov:
8734 case Hexagon::V6_vncmov: {
8735 // op: Ps4
8736 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8737 op &= UINT64_C(3);
8738 op <<= 5;
8739 Value |= op;
8740 // op: Vu32
8741 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8742 op &= UINT64_C(31);
8743 op <<= 8;
8744 Value |= op;
8745 // op: Vd32
8746 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8747 op &= UINT64_C(31);
8748 Value |= op;
8749 break;
8750 }
8751 case Hexagon::V6_vccombine:
8752 case Hexagon::V6_vnccombine: {
8753 // op: Ps4
8754 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8755 op &= UINT64_C(3);
8756 op <<= 5;
8757 Value |= op;
8758 // op: Vu32
8759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8760 op &= UINT64_C(31);
8761 op <<= 8;
8762 Value |= op;
8763 // op: Vv32
8764 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8765 op &= UINT64_C(31);
8766 op <<= 16;
8767 Value |= op;
8768 // op: Vdd32
8769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8770 op &= UINT64_C(31);
8771 Value |= op;
8772 break;
8773 }
8774 case Hexagon::Y2_setimask:
8775 case Hexagon::Y2_setprio: {
8776 // op: Pt4
8777 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8778 op &= UINT64_C(3);
8779 op <<= 8;
8780 Value |= op;
8781 // op: Rs32
8782 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8783 op &= UINT64_C(31);
8784 op <<= 16;
8785 Value |= op;
8786 break;
8787 }
8788 case Hexagon::C2_and:
8789 case Hexagon::C2_andn:
8790 case Hexagon::C2_or:
8791 case Hexagon::C2_orn: {
8792 // op: Pt4
8793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8794 op &= UINT64_C(3);
8795 op <<= 8;
8796 Value |= op;
8797 // op: Ps4
8798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8799 op &= UINT64_C(3);
8800 op <<= 16;
8801 Value |= op;
8802 // op: Pd4
8803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8804 op &= UINT64_C(3);
8805 Value |= op;
8806 break;
8807 }
8808 case Hexagon::C2_mask: {
8809 // op: Pt4
8810 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8811 op &= UINT64_C(3);
8812 op <<= 8;
8813 Value |= op;
8814 // op: Rdd32
8815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8816 op &= UINT64_C(31);
8817 Value |= op;
8818 break;
8819 }
8820 case Hexagon::J2_callrf:
8821 case Hexagon::J2_callrt:
8822 case Hexagon::J2_jumprf:
8823 case Hexagon::J2_jumprfnew:
8824 case Hexagon::J2_jumprfnewpt:
8825 case Hexagon::J2_jumprfpt:
8826 case Hexagon::J2_jumprt:
8827 case Hexagon::J2_jumprtnew:
8828 case Hexagon::J2_jumprtnewpt:
8829 case Hexagon::J2_jumprtpt: {
8830 // op: Pu4
8831 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8832 op &= UINT64_C(3);
8833 op <<= 8;
8834 Value |= op;
8835 // op: Rs32
8836 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8837 op &= UINT64_C(31);
8838 op <<= 16;
8839 Value |= op;
8840 break;
8841 }
8842 case Hexagon::A2_paddf:
8843 case Hexagon::A2_paddfnew:
8844 case Hexagon::A2_paddt:
8845 case Hexagon::A2_paddtnew:
8846 case Hexagon::A2_pandf:
8847 case Hexagon::A2_pandfnew:
8848 case Hexagon::A2_pandt:
8849 case Hexagon::A2_pandtnew:
8850 case Hexagon::A2_porf:
8851 case Hexagon::A2_porfnew:
8852 case Hexagon::A2_port:
8853 case Hexagon::A2_portnew:
8854 case Hexagon::A2_pxorf:
8855 case Hexagon::A2_pxorfnew:
8856 case Hexagon::A2_pxort:
8857 case Hexagon::A2_pxortnew:
8858 case Hexagon::C2_mux: {
8859 // op: Pu4
8860 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8861 op &= UINT64_C(3);
8862 op <<= 5;
8863 Value |= op;
8864 // op: Rs32
8865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8866 op &= UINT64_C(31);
8867 op <<= 16;
8868 Value |= op;
8869 // op: Rt32
8870 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8871 op &= UINT64_C(31);
8872 op <<= 8;
8873 Value |= op;
8874 // op: Rd32
8875 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8876 op &= UINT64_C(31);
8877 Value |= op;
8878 break;
8879 }
8880 case Hexagon::C2_ccombinewf:
8881 case Hexagon::C2_ccombinewnewf:
8882 case Hexagon::C2_ccombinewnewt:
8883 case Hexagon::C2_ccombinewt: {
8884 // op: Pu4
8885 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8886 op &= UINT64_C(3);
8887 op <<= 5;
8888 Value |= op;
8889 // op: Rs32
8890 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8891 op &= UINT64_C(31);
8892 op <<= 16;
8893 Value |= op;
8894 // op: Rt32
8895 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8896 op &= UINT64_C(31);
8897 op <<= 8;
8898 Value |= op;
8899 // op: Rdd32
8900 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8901 op &= UINT64_C(31);
8902 Value |= op;
8903 break;
8904 }
8905 case Hexagon::C2_vmux: {
8906 // op: Pu4
8907 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8908 op &= UINT64_C(3);
8909 op <<= 5;
8910 Value |= op;
8911 // op: Rss32
8912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8913 op &= UINT64_C(31);
8914 op <<= 16;
8915 Value |= op;
8916 // op: Rtt32
8917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8918 op &= UINT64_C(31);
8919 op <<= 8;
8920 Value |= op;
8921 // op: Rdd32
8922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8923 op &= UINT64_C(31);
8924 Value |= op;
8925 break;
8926 }
8927 case Hexagon::A2_psubf:
8928 case Hexagon::A2_psubfnew:
8929 case Hexagon::A2_psubt:
8930 case Hexagon::A2_psubtnew: {
8931 // op: Pu4
8932 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8933 op &= UINT64_C(3);
8934 op <<= 5;
8935 Value |= op;
8936 // op: Rt32
8937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8938 op &= UINT64_C(31);
8939 op <<= 8;
8940 Value |= op;
8941 // op: Rs32
8942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8943 op &= UINT64_C(31);
8944 op <<= 16;
8945 Value |= op;
8946 // op: Rd32
8947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8948 op &= UINT64_C(31);
8949 Value |= op;
8950 break;
8951 }
8952 case Hexagon::A4_paslhf:
8953 case Hexagon::A4_paslhfnew:
8954 case Hexagon::A4_paslht:
8955 case Hexagon::A4_paslhtnew:
8956 case Hexagon::A4_pasrhf:
8957 case Hexagon::A4_pasrhfnew:
8958 case Hexagon::A4_pasrht:
8959 case Hexagon::A4_pasrhtnew:
8960 case Hexagon::A4_psxtbf:
8961 case Hexagon::A4_psxtbfnew:
8962 case Hexagon::A4_psxtbt:
8963 case Hexagon::A4_psxtbtnew:
8964 case Hexagon::A4_psxthf:
8965 case Hexagon::A4_psxthfnew:
8966 case Hexagon::A4_psxtht:
8967 case Hexagon::A4_psxthtnew:
8968 case Hexagon::A4_pzxtbf:
8969 case Hexagon::A4_pzxtbfnew:
8970 case Hexagon::A4_pzxtbt:
8971 case Hexagon::A4_pzxtbtnew:
8972 case Hexagon::A4_pzxthf:
8973 case Hexagon::A4_pzxthfnew:
8974 case Hexagon::A4_pzxtht:
8975 case Hexagon::A4_pzxthtnew: {
8976 // op: Pu4
8977 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8978 op &= UINT64_C(3);
8979 op <<= 8;
8980 Value |= op;
8981 // op: Rs32
8982 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8983 op &= UINT64_C(31);
8984 op <<= 16;
8985 Value |= op;
8986 // op: Rd32
8987 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8988 op &= UINT64_C(31);
8989 Value |= op;
8990 break;
8991 }
8992 case Hexagon::V6_vS32b_new_npred_ppu:
8993 case Hexagon::V6_vS32b_new_pred_ppu:
8994 case Hexagon::V6_vS32b_nt_new_npred_ppu:
8995 case Hexagon::V6_vS32b_nt_new_pred_ppu: {
8996 // op: Pv4
8997 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8998 op &= UINT64_C(3);
8999 op <<= 11;
9000 Value |= op;
9001 // op: Mu2
9002 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9003 op &= UINT64_C(1);
9004 op <<= 13;
9005 Value |= op;
9006 // op: Os8
9007 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9008 op &= UINT64_C(7);
9009 Value |= op;
9010 // op: Rx32
9011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9012 op &= UINT64_C(31);
9013 op <<= 16;
9014 Value |= op;
9015 break;
9016 }
9017 case Hexagon::V6_zLd_pred_ppu: {
9018 // op: Pv4
9019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9020 op &= UINT64_C(3);
9021 op <<= 11;
9022 Value |= op;
9023 // op: Mu2
9024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9025 op &= UINT64_C(1);
9026 op <<= 13;
9027 Value |= op;
9028 // op: Rx32
9029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9030 op &= UINT64_C(31);
9031 op <<= 16;
9032 Value |= op;
9033 break;
9034 }
9035 case Hexagon::V6_vS32Ub_npred_ppu:
9036 case Hexagon::V6_vS32Ub_pred_ppu:
9037 case Hexagon::V6_vS32b_npred_ppu:
9038 case Hexagon::V6_vS32b_nt_npred_ppu:
9039 case Hexagon::V6_vS32b_nt_pred_ppu:
9040 case Hexagon::V6_vS32b_pred_ppu: {
9041 // op: Pv4
9042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9043 op &= UINT64_C(3);
9044 op <<= 11;
9045 Value |= op;
9046 // op: Mu2
9047 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9048 op &= UINT64_C(1);
9049 op <<= 13;
9050 Value |= op;
9051 // op: Vs32
9052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9053 op &= UINT64_C(31);
9054 Value |= op;
9055 // op: Rx32
9056 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9057 op &= UINT64_C(31);
9058 op <<= 16;
9059 Value |= op;
9060 break;
9061 }
9062 case Hexagon::L4_return_f:
9063 case Hexagon::L4_return_fnew_pnt:
9064 case Hexagon::L4_return_fnew_pt:
9065 case Hexagon::L4_return_t:
9066 case Hexagon::L4_return_tnew_pnt:
9067 case Hexagon::L4_return_tnew_pt: {
9068 // op: Pv4
9069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9070 op &= UINT64_C(3);
9071 op <<= 8;
9072 Value |= op;
9073 // op: Rs32
9074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9075 op &= UINT64_C(31);
9076 op <<= 16;
9077 Value |= op;
9078 // op: Rdd32
9079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9080 op &= UINT64_C(31);
9081 Value |= op;
9082 break;
9083 }
9084 case Hexagon::V6_vL32b_cur_npred_ppu:
9085 case Hexagon::V6_vL32b_cur_pred_ppu:
9086 case Hexagon::V6_vL32b_npred_ppu:
9087 case Hexagon::V6_vL32b_nt_cur_npred_ppu:
9088 case Hexagon::V6_vL32b_nt_cur_pred_ppu:
9089 case Hexagon::V6_vL32b_nt_npred_ppu:
9090 case Hexagon::V6_vL32b_nt_pred_ppu:
9091 case Hexagon::V6_vL32b_nt_tmp_npred_ppu:
9092 case Hexagon::V6_vL32b_nt_tmp_pred_ppu:
9093 case Hexagon::V6_vL32b_pred_ppu:
9094 case Hexagon::V6_vL32b_tmp_npred_ppu:
9095 case Hexagon::V6_vL32b_tmp_pred_ppu: {
9096 // op: Pv4
9097 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9098 op &= UINT64_C(3);
9099 op <<= 11;
9100 Value |= op;
9101 // op: Mu2
9102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9103 op &= UINT64_C(1);
9104 op <<= 13;
9105 Value |= op;
9106 // op: Vd32
9107 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9108 op &= UINT64_C(31);
9109 Value |= op;
9110 // op: Rx32
9111 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9112 op &= UINT64_C(31);
9113 op <<= 16;
9114 Value |= op;
9115 break;
9116 }
9117 case Hexagon::V6_vgathermhq:
9118 case Hexagon::V6_vgathermwq: {
9119 // op: Qs4
9120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9121 op &= UINT64_C(3);
9122 op <<= 5;
9123 Value |= op;
9124 // op: Rt32
9125 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9126 op &= UINT64_C(31);
9127 op <<= 16;
9128 Value |= op;
9129 // op: Mu2
9130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9131 op &= UINT64_C(1);
9132 op <<= 13;
9133 Value |= op;
9134 // op: Vv32
9135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9136 op &= UINT64_C(31);
9137 Value |= op;
9138 break;
9139 }
9140 case Hexagon::V6_vscattermhq:
9141 case Hexagon::V6_vscattermwq: {
9142 // op: Qs4
9143 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9144 op &= UINT64_C(3);
9145 op <<= 5;
9146 Value |= op;
9147 // op: Rt32
9148 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9149 op &= UINT64_C(31);
9150 op <<= 16;
9151 Value |= op;
9152 // op: Mu2
9153 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9154 op &= UINT64_C(1);
9155 op <<= 13;
9156 Value |= op;
9157 // op: Vv32
9158 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9159 op &= UINT64_C(31);
9160 op <<= 8;
9161 Value |= op;
9162 // op: Vw32
9163 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9164 op &= UINT64_C(31);
9165 Value |= op;
9166 break;
9167 }
9168 case Hexagon::V6_vgathermhwq: {
9169 // op: Qs4
9170 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9171 op &= UINT64_C(3);
9172 op <<= 5;
9173 Value |= op;
9174 // op: Rt32
9175 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9176 op &= UINT64_C(31);
9177 op <<= 16;
9178 Value |= op;
9179 // op: Mu2
9180 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9181 op &= UINT64_C(1);
9182 op <<= 13;
9183 Value |= op;
9184 // op: Vvv32
9185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9186 op &= UINT64_C(31);
9187 Value |= op;
9188 break;
9189 }
9190 case Hexagon::V6_vscattermhwq: {
9191 // op: Qs4
9192 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9193 op &= UINT64_C(3);
9194 op <<= 5;
9195 Value |= op;
9196 // op: Rt32
9197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9198 op &= UINT64_C(31);
9199 op <<= 16;
9200 Value |= op;
9201 // op: Mu2
9202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9203 op &= UINT64_C(1);
9204 op <<= 13;
9205 Value |= op;
9206 // op: Vvv32
9207 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9208 op &= UINT64_C(31);
9209 op <<= 8;
9210 Value |= op;
9211 // op: Vw32
9212 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9213 op &= UINT64_C(31);
9214 Value |= op;
9215 break;
9216 }
9217 case Hexagon::V6_pred_not: {
9218 // op: Qs4
9219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9220 op &= UINT64_C(3);
9221 op <<= 8;
9222 Value |= op;
9223 // op: Qd4
9224 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9225 op &= UINT64_C(3);
9226 Value |= op;
9227 break;
9228 }
9229 case Hexagon::V6_pred_and:
9230 case Hexagon::V6_pred_and_n:
9231 case Hexagon::V6_pred_or:
9232 case Hexagon::V6_pred_or_n:
9233 case Hexagon::V6_pred_xor:
9234 case Hexagon::V6_shuffeqh:
9235 case Hexagon::V6_shuffeqw: {
9236 // op: Qs4
9237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9238 op &= UINT64_C(3);
9239 op <<= 8;
9240 Value |= op;
9241 // op: Qt4
9242 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9243 op &= UINT64_C(3);
9244 op <<= 22;
9245 Value |= op;
9246 // op: Qd4
9247 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9248 op &= UINT64_C(3);
9249 Value |= op;
9250 break;
9251 }
9252 case Hexagon::V6_vmux: {
9253 // op: Qt4
9254 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9255 op &= UINT64_C(3);
9256 op <<= 5;
9257 Value |= op;
9258 // op: Vu32
9259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9260 op &= UINT64_C(31);
9261 op <<= 8;
9262 Value |= op;
9263 // op: Vv32
9264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9265 op &= UINT64_C(31);
9266 op <<= 16;
9267 Value |= op;
9268 // op: Vd32
9269 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9270 op &= UINT64_C(31);
9271 Value |= op;
9272 break;
9273 }
9274 case Hexagon::V6_vswap: {
9275 // op: Qt4
9276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9277 op &= UINT64_C(3);
9278 op <<= 5;
9279 Value |= op;
9280 // op: Vu32
9281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9282 op &= UINT64_C(31);
9283 op <<= 8;
9284 Value |= op;
9285 // op: Vv32
9286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9287 op &= UINT64_C(31);
9288 op <<= 16;
9289 Value |= op;
9290 // op: Vdd32
9291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9292 op &= UINT64_C(31);
9293 Value |= op;
9294 break;
9295 }
9296 case Hexagon::V6_vandnqrt:
9297 case Hexagon::V6_vandqrt: {
9298 // op: Qu4
9299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9300 op &= UINT64_C(3);
9301 op <<= 8;
9302 Value |= op;
9303 // op: Rt32
9304 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9305 op &= UINT64_C(31);
9306 op <<= 16;
9307 Value |= op;
9308 // op: Vd32
9309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9310 op &= UINT64_C(31);
9311 Value |= op;
9312 break;
9313 }
9314 case Hexagon::V6_vandnqrt_acc:
9315 case Hexagon::V6_vandqrt_acc: {
9316 // op: Qu4
9317 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9318 op &= UINT64_C(3);
9319 op <<= 8;
9320 Value |= op;
9321 // op: Rt32
9322 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9323 op &= UINT64_C(31);
9324 op <<= 16;
9325 Value |= op;
9326 // op: Vx32
9327 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9328 op &= UINT64_C(31);
9329 Value |= op;
9330 break;
9331 }
9332 case Hexagon::V6_vhistq:
9333 case Hexagon::V6_vwhist128q:
9334 case Hexagon::V6_vwhist256q:
9335 case Hexagon::V6_vwhist256q_sat: {
9336 // op: Qv4
9337 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9338 op &= UINT64_C(3);
9339 op <<= 22;
9340 Value |= op;
9341 break;
9342 }
9343 case Hexagon::V6_vS32b_nqpred_ppu:
9344 case Hexagon::V6_vS32b_nt_nqpred_ppu:
9345 case Hexagon::V6_vS32b_nt_qpred_ppu:
9346 case Hexagon::V6_vS32b_qpred_ppu: {
9347 // op: Qv4
9348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9349 op &= UINT64_C(3);
9350 op <<= 11;
9351 Value |= op;
9352 // op: Mu2
9353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9354 op &= UINT64_C(1);
9355 op <<= 13;
9356 Value |= op;
9357 // op: Vs32
9358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9359 op &= UINT64_C(31);
9360 Value |= op;
9361 // op: Rx32
9362 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9363 op &= UINT64_C(31);
9364 op <<= 16;
9365 Value |= op;
9366 break;
9367 }
9368 case Hexagon::V6_vprefixqb:
9369 case Hexagon::V6_vprefixqh:
9370 case Hexagon::V6_vprefixqw: {
9371 // op: Qv4
9372 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9373 op &= UINT64_C(3);
9374 op <<= 22;
9375 Value |= op;
9376 // op: Vd32
9377 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9378 op &= UINT64_C(31);
9379 Value |= op;
9380 break;
9381 }
9382 case Hexagon::V6_vandvnqv:
9383 case Hexagon::V6_vandvqv: {
9384 // op: Qv4
9385 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9386 op &= UINT64_C(3);
9387 op <<= 22;
9388 Value |= op;
9389 // op: Vu32
9390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9391 op &= UINT64_C(31);
9392 op <<= 8;
9393 Value |= op;
9394 // op: Vd32
9395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9396 op &= UINT64_C(31);
9397 Value |= op;
9398 break;
9399 }
9400 case Hexagon::V6_vaddbnq:
9401 case Hexagon::V6_vaddbq:
9402 case Hexagon::V6_vaddhnq:
9403 case Hexagon::V6_vaddhq:
9404 case Hexagon::V6_vaddwnq:
9405 case Hexagon::V6_vaddwq:
9406 case Hexagon::V6_vsubbnq:
9407 case Hexagon::V6_vsubbq:
9408 case Hexagon::V6_vsubhnq:
9409 case Hexagon::V6_vsubhq:
9410 case Hexagon::V6_vsubwnq:
9411 case Hexagon::V6_vsubwq: {
9412 // op: Qv4
9413 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9414 op &= UINT64_C(3);
9415 op <<= 22;
9416 Value |= op;
9417 // op: Vu32
9418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9419 op &= UINT64_C(31);
9420 op <<= 8;
9421 Value |= op;
9422 // op: Vx32
9423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9424 op &= UINT64_C(31);
9425 Value |= op;
9426 break;
9427 }
9428 case Hexagon::SA1_clrf:
9429 case Hexagon::SA1_clrfnew:
9430 case Hexagon::SA1_clrt:
9431 case Hexagon::SA1_clrtnew:
9432 case Hexagon::SA1_setin1: {
9433 // op: Rd16
9434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9435 op &= UINT64_C(15);
9436 Value |= op;
9437 break;
9438 }
9439 case Hexagon::Y6_dmpause:
9440 case Hexagon::Y6_dmpoll:
9441 case Hexagon::Y6_dmwait: {
9442 // op: Rd32
9443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9444 op &= UINT64_C(31);
9445 Value |= op;
9446 break;
9447 }
9448 case Hexagon::PS_callr_nr: {
9449 // op: Rs
9450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9451 op &= UINT64_C(31);
9452 op <<= 16;
9453 Value |= op;
9454 break;
9455 }
9456 case Hexagon::SA1_and1:
9457 case Hexagon::SA1_dec:
9458 case Hexagon::SA1_inc:
9459 case Hexagon::SA1_sxtb:
9460 case Hexagon::SA1_sxth:
9461 case Hexagon::SA1_tfr:
9462 case Hexagon::SA1_zxtb:
9463 case Hexagon::SA1_zxth: {
9464 // op: Rs16
9465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9466 op &= UINT64_C(15);
9467 op <<= 4;
9468 Value |= op;
9469 // op: Rd16
9470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9471 op &= UINT64_C(15);
9472 Value |= op;
9473 break;
9474 }
9475 case Hexagon::SA1_combinerz:
9476 case Hexagon::SA1_combinezr: {
9477 // op: Rs16
9478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9479 op &= UINT64_C(15);
9480 op <<= 4;
9481 Value |= op;
9482 // op: Rdd8
9483 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9484 op &= UINT64_C(7);
9485 Value |= op;
9486 break;
9487 }
9488 case Hexagon::SA1_addrx: {
9489 // op: Rs16
9490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9491 op &= UINT64_C(15);
9492 op <<= 4;
9493 Value |= op;
9494 // op: Rx16
9495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9496 op &= UINT64_C(15);
9497 Value |= op;
9498 break;
9499 }
9500 case Hexagon::J2_callr:
9501 case Hexagon::J2_callrh:
9502 case Hexagon::J2_jumpr:
9503 case Hexagon::J2_jumprh:
9504 case Hexagon::J4_hintjumpr:
9505 case Hexagon::R6_release_at_vi:
9506 case Hexagon::R6_release_st_vi:
9507 case Hexagon::Y2_ciad:
9508 case Hexagon::Y2_cswi:
9509 case Hexagon::Y2_dccleana:
9510 case Hexagon::Y2_dccleanidx:
9511 case Hexagon::Y2_dccleaninva:
9512 case Hexagon::Y2_dccleaninvidx:
9513 case Hexagon::Y2_dcinva:
9514 case Hexagon::Y2_dcinvidx:
9515 case Hexagon::Y2_dczeroa:
9516 case Hexagon::Y2_iassignw:
9517 case Hexagon::Y2_icinva:
9518 case Hexagon::Y2_icinvidx:
9519 case Hexagon::Y2_l2cleaninvidx:
9520 case Hexagon::Y2_resume:
9521 case Hexagon::Y2_start:
9522 case Hexagon::Y2_stop:
9523 case Hexagon::Y2_swi:
9524 case Hexagon::Y2_wait:
9525 case Hexagon::Y4_nmi:
9526 case Hexagon::Y4_siad:
9527 case Hexagon::Y4_trace:
9528 case Hexagon::Y5_l2cleanidx:
9529 case Hexagon::Y5_l2invidx:
9530 case Hexagon::Y5_l2unlocka:
9531 case Hexagon::Y5_tlbasidi:
9532 case Hexagon::Y6_diag:
9533 case Hexagon::Y6_dmresume:
9534 case Hexagon::Y6_dmstart: {
9535 // op: Rs32
9536 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9537 op &= UINT64_C(31);
9538 op <<= 16;
9539 Value |= op;
9540 break;
9541 }
9542 case Hexagon::S2_storew_rl_at_vi:
9543 case Hexagon::S2_storew_rl_st_vi:
9544 case Hexagon::Y2_dctagw:
9545 case Hexagon::Y2_icdataw:
9546 case Hexagon::Y2_ictagw:
9547 case Hexagon::Y4_l2fetch:
9548 case Hexagon::Y4_l2tagw:
9549 case Hexagon::Y6_dmlink: {
9550 // op: Rs32
9551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9552 op &= UINT64_C(31);
9553 op <<= 16;
9554 Value |= op;
9555 // op: Rt32
9556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9557 op &= UINT64_C(31);
9558 op <<= 8;
9559 Value |= op;
9560 break;
9561 }
9562 case Hexagon::L6_memcpy: {
9563 // op: Rs32
9564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9565 op &= UINT64_C(31);
9566 op <<= 16;
9567 Value |= op;
9568 // op: Rt32
9569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9570 op &= UINT64_C(31);
9571 op <<= 8;
9572 Value |= op;
9573 // op: Mu2
9574 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9575 op &= UINT64_C(1);
9576 op <<= 13;
9577 Value |= op;
9578 break;
9579 }
9580 case Hexagon::S4_stored_rl_at_vi:
9581 case Hexagon::S4_stored_rl_st_vi:
9582 case Hexagon::Y5_l2fetch: {
9583 // op: Rs32
9584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9585 op &= UINT64_C(31);
9586 op <<= 16;
9587 Value |= op;
9588 // op: Rtt32
9589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9590 op &= UINT64_C(31);
9591 op <<= 8;
9592 Value |= op;
9593 break;
9594 }
9595 case Hexagon::A2_tfrrcr: {
9596 // op: Rs32
9597 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9598 op &= UINT64_C(31);
9599 op <<= 16;
9600 Value |= op;
9601 // op: Cd32
9602 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9603 op &= UINT64_C(31);
9604 Value |= op;
9605 break;
9606 }
9607 case Hexagon::G4_tfrgrcr: {
9608 // op: Rs32
9609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9610 op &= UINT64_C(31);
9611 op <<= 16;
9612 Value |= op;
9613 // op: Gd32
9614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9615 op &= UINT64_C(31);
9616 Value |= op;
9617 break;
9618 }
9619 case Hexagon::C2_tfrrp:
9620 case Hexagon::Y5_l2locka: {
9621 // op: Rs32
9622 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9623 op &= UINT64_C(31);
9624 op <<= 16;
9625 Value |= op;
9626 // op: Pd4
9627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9628 op &= UINT64_C(3);
9629 Value |= op;
9630 break;
9631 }
9632 case Hexagon::A2_abs:
9633 case Hexagon::A2_abssat:
9634 case Hexagon::A2_aslh:
9635 case Hexagon::A2_asrh:
9636 case Hexagon::A2_negsat:
9637 case Hexagon::A2_satb:
9638 case Hexagon::A2_sath:
9639 case Hexagon::A2_satub:
9640 case Hexagon::A2_satuh:
9641 case Hexagon::A2_swiz:
9642 case Hexagon::A2_sxtb:
9643 case Hexagon::A2_sxth:
9644 case Hexagon::A2_tfr:
9645 case Hexagon::A2_zxth:
9646 case Hexagon::F2_conv_sf2uw:
9647 case Hexagon::F2_conv_sf2uw_chop:
9648 case Hexagon::F2_conv_sf2w:
9649 case Hexagon::F2_conv_sf2w_chop:
9650 case Hexagon::F2_conv_uw2sf:
9651 case Hexagon::F2_conv_w2sf:
9652 case Hexagon::F2_sffixupr:
9653 case Hexagon::L2_loadw_aq:
9654 case Hexagon::L2_loadw_locked:
9655 case Hexagon::S2_brev:
9656 case Hexagon::S2_cl0:
9657 case Hexagon::S2_cl1:
9658 case Hexagon::S2_clb:
9659 case Hexagon::S2_clbnorm:
9660 case Hexagon::S2_ct0:
9661 case Hexagon::S2_ct1:
9662 case Hexagon::S2_svsathb:
9663 case Hexagon::S2_svsathub:
9664 case Hexagon::S2_vsplatrb:
9665 case Hexagon::Y2_dctagr:
9666 case Hexagon::Y2_getimask:
9667 case Hexagon::Y2_iassignr:
9668 case Hexagon::Y2_icdatar:
9669 case Hexagon::Y2_ictagr:
9670 case Hexagon::Y2_tlbp:
9671 case Hexagon::Y4_l2tagr: {
9672 // op: Rs32
9673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9674 op &= UINT64_C(31);
9675 op <<= 16;
9676 Value |= op;
9677 // op: Rd32
9678 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9679 op &= UINT64_C(31);
9680 Value |= op;
9681 break;
9682 }
9683 case Hexagon::A2_sxtw:
9684 case Hexagon::F2_conv_sf2d:
9685 case Hexagon::F2_conv_sf2d_chop:
9686 case Hexagon::F2_conv_sf2df:
9687 case Hexagon::F2_conv_sf2ud:
9688 case Hexagon::F2_conv_sf2ud_chop:
9689 case Hexagon::F2_conv_uw2df:
9690 case Hexagon::F2_conv_w2df:
9691 case Hexagon::L2_deallocframe:
9692 case Hexagon::L4_loadd_aq:
9693 case Hexagon::L4_loadd_locked:
9694 case Hexagon::L4_return:
9695 case Hexagon::S2_vsplatrh:
9696 case Hexagon::S2_vsxtbh:
9697 case Hexagon::S2_vsxthw:
9698 case Hexagon::S2_vzxtbh:
9699 case Hexagon::S2_vzxthw:
9700 case Hexagon::S6_vsplatrbp:
9701 case Hexagon::Y2_tlbr: {
9702 // op: Rs32
9703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9704 op &= UINT64_C(31);
9705 op <<= 16;
9706 Value |= op;
9707 // op: Rdd32
9708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9709 op &= UINT64_C(31);
9710 Value |= op;
9711 break;
9712 }
9713 case Hexagon::A4_cmpbeq:
9714 case Hexagon::A4_cmpbgt:
9715 case Hexagon::A4_cmpbgtu:
9716 case Hexagon::A4_cmpheq:
9717 case Hexagon::A4_cmphgt:
9718 case Hexagon::A4_cmphgtu:
9719 case Hexagon::C2_bitsclr:
9720 case Hexagon::C2_bitsset:
9721 case Hexagon::C2_cmpeq:
9722 case Hexagon::C2_cmpgt:
9723 case Hexagon::C2_cmpgtu:
9724 case Hexagon::C4_cmplte:
9725 case Hexagon::C4_cmplteu:
9726 case Hexagon::C4_cmpneq:
9727 case Hexagon::C4_nbitsclr:
9728 case Hexagon::C4_nbitsset:
9729 case Hexagon::F2_sfcmpeq:
9730 case Hexagon::F2_sfcmpge:
9731 case Hexagon::F2_sfcmpgt:
9732 case Hexagon::F2_sfcmpuo:
9733 case Hexagon::S2_storew_locked:
9734 case Hexagon::S2_tstbit_r:
9735 case Hexagon::S4_ntstbit_r: {
9736 // op: Rs32
9737 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9738 op &= UINT64_C(31);
9739 op <<= 16;
9740 Value |= op;
9741 // op: Rt32
9742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9743 op &= UINT64_C(31);
9744 op <<= 8;
9745 Value |= op;
9746 // op: Pd4
9747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9748 op &= UINT64_C(3);
9749 Value |= op;
9750 break;
9751 }
9752 case Hexagon::A2_add:
9753 case Hexagon::A2_addsat:
9754 case Hexagon::A2_and:
9755 case Hexagon::A2_max:
9756 case Hexagon::A2_maxu:
9757 case Hexagon::A2_or:
9758 case Hexagon::A2_svaddh:
9759 case Hexagon::A2_svaddhs:
9760 case Hexagon::A2_svadduhs:
9761 case Hexagon::A2_svavgh:
9762 case Hexagon::A2_svavghs:
9763 case Hexagon::A2_xor:
9764 case Hexagon::A4_cround_rr:
9765 case Hexagon::A4_modwrapu:
9766 case Hexagon::A4_rcmpeq:
9767 case Hexagon::A4_rcmpneq:
9768 case Hexagon::A4_round_rr:
9769 case Hexagon::A4_round_rr_sat:
9770 case Hexagon::F2_sfadd:
9771 case Hexagon::F2_sffixupd:
9772 case Hexagon::F2_sffixupn:
9773 case Hexagon::F2_sfmax:
9774 case Hexagon::F2_sfmin:
9775 case Hexagon::F2_sfmpy:
9776 case Hexagon::F2_sfsub:
9777 case Hexagon::L4_loadw_phys:
9778 case Hexagon::M2_cmpyrs_s0:
9779 case Hexagon::M2_cmpyrs_s1:
9780 case Hexagon::M2_cmpyrsc_s0:
9781 case Hexagon::M2_cmpyrsc_s1:
9782 case Hexagon::M2_dpmpyss_rnd_s0:
9783 case Hexagon::M2_hmmpyh_rs1:
9784 case Hexagon::M2_hmmpyh_s1:
9785 case Hexagon::M2_hmmpyl_rs1:
9786 case Hexagon::M2_hmmpyl_s1:
9787 case Hexagon::M2_mpy_hh_s0:
9788 case Hexagon::M2_mpy_hh_s1:
9789 case Hexagon::M2_mpy_hl_s0:
9790 case Hexagon::M2_mpy_hl_s1:
9791 case Hexagon::M2_mpy_lh_s0:
9792 case Hexagon::M2_mpy_lh_s1:
9793 case Hexagon::M2_mpy_ll_s0:
9794 case Hexagon::M2_mpy_ll_s1:
9795 case Hexagon::M2_mpy_rnd_hh_s0:
9796 case Hexagon::M2_mpy_rnd_hh_s1:
9797 case Hexagon::M2_mpy_rnd_hl_s0:
9798 case Hexagon::M2_mpy_rnd_hl_s1:
9799 case Hexagon::M2_mpy_rnd_lh_s0:
9800 case Hexagon::M2_mpy_rnd_lh_s1:
9801 case Hexagon::M2_mpy_rnd_ll_s0:
9802 case Hexagon::M2_mpy_rnd_ll_s1:
9803 case Hexagon::M2_mpy_sat_hh_s0:
9804 case Hexagon::M2_mpy_sat_hh_s1:
9805 case Hexagon::M2_mpy_sat_hl_s0:
9806 case Hexagon::M2_mpy_sat_hl_s1:
9807 case Hexagon::M2_mpy_sat_lh_s0:
9808 case Hexagon::M2_mpy_sat_lh_s1:
9809 case Hexagon::M2_mpy_sat_ll_s0:
9810 case Hexagon::M2_mpy_sat_ll_s1:
9811 case Hexagon::M2_mpy_sat_rnd_hh_s0:
9812 case Hexagon::M2_mpy_sat_rnd_hh_s1:
9813 case Hexagon::M2_mpy_sat_rnd_hl_s0:
9814 case Hexagon::M2_mpy_sat_rnd_hl_s1:
9815 case Hexagon::M2_mpy_sat_rnd_lh_s0:
9816 case Hexagon::M2_mpy_sat_rnd_lh_s1:
9817 case Hexagon::M2_mpy_sat_rnd_ll_s0:
9818 case Hexagon::M2_mpy_sat_rnd_ll_s1:
9819 case Hexagon::M2_mpy_up:
9820 case Hexagon::M2_mpy_up_s1:
9821 case Hexagon::M2_mpy_up_s1_sat:
9822 case Hexagon::M2_mpyi:
9823 case Hexagon::M2_mpysu_up:
9824 case Hexagon::M2_mpyu_hh_s0:
9825 case Hexagon::M2_mpyu_hh_s1:
9826 case Hexagon::M2_mpyu_hl_s0:
9827 case Hexagon::M2_mpyu_hl_s1:
9828 case Hexagon::M2_mpyu_lh_s0:
9829 case Hexagon::M2_mpyu_lh_s1:
9830 case Hexagon::M2_mpyu_ll_s0:
9831 case Hexagon::M2_mpyu_ll_s1:
9832 case Hexagon::M2_mpyu_up:
9833 case Hexagon::M2_vmpy2s_s0pack:
9834 case Hexagon::M2_vmpy2s_s1pack:
9835 case Hexagon::S2_asl_r_r:
9836 case Hexagon::S2_asl_r_r_sat:
9837 case Hexagon::S2_asr_r_r:
9838 case Hexagon::S2_asr_r_r_sat:
9839 case Hexagon::S2_clrbit_r:
9840 case Hexagon::S2_lsl_r_r:
9841 case Hexagon::S2_lsr_r_r:
9842 case Hexagon::S2_setbit_r:
9843 case Hexagon::S2_togglebit_r:
9844 case Hexagon::S4_parity:
9845 case Hexagon::dep_A2_addsat: {
9846 // op: Rs32
9847 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9848 op &= UINT64_C(31);
9849 op <<= 16;
9850 Value |= op;
9851 // op: Rt32
9852 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9853 op &= UINT64_C(31);
9854 op <<= 8;
9855 Value |= op;
9856 // op: Rd32
9857 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9858 op &= UINT64_C(31);
9859 Value |= op;
9860 break;
9861 }
9862 case Hexagon::A2_combinew:
9863 case Hexagon::A4_bitsplit:
9864 case Hexagon::M2_cmpyi_s0:
9865 case Hexagon::M2_cmpyr_s0:
9866 case Hexagon::M2_cmpys_s0:
9867 case Hexagon::M2_cmpys_s1:
9868 case Hexagon::M2_cmpysc_s0:
9869 case Hexagon::M2_cmpysc_s1:
9870 case Hexagon::M2_dpmpyss_s0:
9871 case Hexagon::M2_dpmpyuu_s0:
9872 case Hexagon::M2_mpyd_hh_s0:
9873 case Hexagon::M2_mpyd_hh_s1:
9874 case Hexagon::M2_mpyd_hl_s0:
9875 case Hexagon::M2_mpyd_hl_s1:
9876 case Hexagon::M2_mpyd_lh_s0:
9877 case Hexagon::M2_mpyd_lh_s1:
9878 case Hexagon::M2_mpyd_ll_s0:
9879 case Hexagon::M2_mpyd_ll_s1:
9880 case Hexagon::M2_mpyd_rnd_hh_s0:
9881 case Hexagon::M2_mpyd_rnd_hh_s1:
9882 case Hexagon::M2_mpyd_rnd_hl_s0:
9883 case Hexagon::M2_mpyd_rnd_hl_s1:
9884 case Hexagon::M2_mpyd_rnd_lh_s0:
9885 case Hexagon::M2_mpyd_rnd_lh_s1:
9886 case Hexagon::M2_mpyd_rnd_ll_s0:
9887 case Hexagon::M2_mpyd_rnd_ll_s1:
9888 case Hexagon::M2_mpyud_hh_s0:
9889 case Hexagon::M2_mpyud_hh_s1:
9890 case Hexagon::M2_mpyud_hl_s0:
9891 case Hexagon::M2_mpyud_hl_s1:
9892 case Hexagon::M2_mpyud_lh_s0:
9893 case Hexagon::M2_mpyud_lh_s1:
9894 case Hexagon::M2_mpyud_ll_s0:
9895 case Hexagon::M2_mpyud_ll_s1:
9896 case Hexagon::M2_vmpy2s_s0:
9897 case Hexagon::M2_vmpy2s_s1:
9898 case Hexagon::M2_vmpy2su_s0:
9899 case Hexagon::M2_vmpy2su_s1:
9900 case Hexagon::M4_pmpyw:
9901 case Hexagon::M4_vpmpyh:
9902 case Hexagon::M5_vmpybsu:
9903 case Hexagon::M5_vmpybuu:
9904 case Hexagon::S2_packhl:
9905 case Hexagon::dep_S2_packhl: {
9906 // op: Rs32
9907 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9908 op &= UINT64_C(31);
9909 op <<= 16;
9910 Value |= op;
9911 // op: Rt32
9912 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9913 op &= UINT64_C(31);
9914 op <<= 8;
9915 Value |= op;
9916 // op: Rdd32
9917 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9918 op &= UINT64_C(31);
9919 Value |= op;
9920 break;
9921 }
9922 case Hexagon::S4_stored_locked: {
9923 // op: Rs32
9924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9925 op &= UINT64_C(31);
9926 op <<= 16;
9927 Value |= op;
9928 // op: Rtt32
9929 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9930 op &= UINT64_C(31);
9931 op <<= 8;
9932 Value |= op;
9933 // op: Pd4
9934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9935 op &= UINT64_C(3);
9936 Value |= op;
9937 break;
9938 }
9939 case Hexagon::S2_extractu_rp:
9940 case Hexagon::S4_extract_rp: {
9941 // op: Rs32
9942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9943 op &= UINT64_C(31);
9944 op <<= 16;
9945 Value |= op;
9946 // op: Rtt32
9947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9948 op &= UINT64_C(31);
9949 op <<= 8;
9950 Value |= op;
9951 // op: Rd32
9952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9953 op &= UINT64_C(31);
9954 Value |= op;
9955 break;
9956 }
9957 case Hexagon::Y2_tfrsrcr: {
9958 // op: Rs32
9959 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9960 op &= UINT64_C(31);
9961 op <<= 16;
9962 Value |= op;
9963 // op: Sd128
9964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9965 op &= UINT64_C(127);
9966 Value |= op;
9967 break;
9968 }
9969 case Hexagon::F2_sfinvsqrta: {
9970 // op: Rs32
9971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9972 op &= UINT64_C(31);
9973 op <<= 16;
9974 Value |= op;
9975 // op: Rd32
9976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9977 op &= UINT64_C(31);
9978 Value |= op;
9979 // op: Pe4
9980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9981 op &= UINT64_C(3);
9982 op <<= 5;
9983 Value |= op;
9984 break;
9985 }
9986 case Hexagon::F2_sffma_sc: {
9987 // op: Rs32
9988 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9989 op &= UINT64_C(31);
9990 op <<= 16;
9991 Value |= op;
9992 // op: Rt32
9993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9994 op &= UINT64_C(31);
9995 op <<= 8;
9996 Value |= op;
9997 // op: Pu4
9998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9999 op &= UINT64_C(3);
10000 op <<= 5;
10001 Value |= op;
10002 // op: Rx32
10003 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10004 op &= UINT64_C(31);
10005 Value |= op;
10006 break;
10007 }
10008 case Hexagon::F2_sfrecipa: {
10009 // op: Rs32
10010 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10011 op &= UINT64_C(31);
10012 op <<= 16;
10013 Value |= op;
10014 // op: Rt32
10015 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10016 op &= UINT64_C(31);
10017 op <<= 8;
10018 Value |= op;
10019 // op: Rd32
10020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10021 op &= UINT64_C(31);
10022 Value |= op;
10023 // op: Pe4
10024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10025 op &= UINT64_C(3);
10026 op <<= 5;
10027 Value |= op;
10028 break;
10029 }
10030 case Hexagon::F2_sffma:
10031 case Hexagon::F2_sffma_lib:
10032 case Hexagon::F2_sffms:
10033 case Hexagon::F2_sffms_lib:
10034 case Hexagon::M2_acci:
10035 case Hexagon::M2_maci:
10036 case Hexagon::M2_mnaci:
10037 case Hexagon::M2_mpy_acc_hh_s0:
10038 case Hexagon::M2_mpy_acc_hh_s1:
10039 case Hexagon::M2_mpy_acc_hl_s0:
10040 case Hexagon::M2_mpy_acc_hl_s1:
10041 case Hexagon::M2_mpy_acc_lh_s0:
10042 case Hexagon::M2_mpy_acc_lh_s1:
10043 case Hexagon::M2_mpy_acc_ll_s0:
10044 case Hexagon::M2_mpy_acc_ll_s1:
10045 case Hexagon::M2_mpy_acc_sat_hh_s0:
10046 case Hexagon::M2_mpy_acc_sat_hh_s1:
10047 case Hexagon::M2_mpy_acc_sat_hl_s0:
10048 case Hexagon::M2_mpy_acc_sat_hl_s1:
10049 case Hexagon::M2_mpy_acc_sat_lh_s0:
10050 case Hexagon::M2_mpy_acc_sat_lh_s1:
10051 case Hexagon::M2_mpy_acc_sat_ll_s0:
10052 case Hexagon::M2_mpy_acc_sat_ll_s1:
10053 case Hexagon::M2_mpy_nac_hh_s0:
10054 case Hexagon::M2_mpy_nac_hh_s1:
10055 case Hexagon::M2_mpy_nac_hl_s0:
10056 case Hexagon::M2_mpy_nac_hl_s1:
10057 case Hexagon::M2_mpy_nac_lh_s0:
10058 case Hexagon::M2_mpy_nac_lh_s1:
10059 case Hexagon::M2_mpy_nac_ll_s0:
10060 case Hexagon::M2_mpy_nac_ll_s1:
10061 case Hexagon::M2_mpy_nac_sat_hh_s0:
10062 case Hexagon::M2_mpy_nac_sat_hh_s1:
10063 case Hexagon::M2_mpy_nac_sat_hl_s0:
10064 case Hexagon::M2_mpy_nac_sat_hl_s1:
10065 case Hexagon::M2_mpy_nac_sat_lh_s0:
10066 case Hexagon::M2_mpy_nac_sat_lh_s1:
10067 case Hexagon::M2_mpy_nac_sat_ll_s0:
10068 case Hexagon::M2_mpy_nac_sat_ll_s1:
10069 case Hexagon::M2_mpyu_acc_hh_s0:
10070 case Hexagon::M2_mpyu_acc_hh_s1:
10071 case Hexagon::M2_mpyu_acc_hl_s0:
10072 case Hexagon::M2_mpyu_acc_hl_s1:
10073 case Hexagon::M2_mpyu_acc_lh_s0:
10074 case Hexagon::M2_mpyu_acc_lh_s1:
10075 case Hexagon::M2_mpyu_acc_ll_s0:
10076 case Hexagon::M2_mpyu_acc_ll_s1:
10077 case Hexagon::M2_mpyu_nac_hh_s0:
10078 case Hexagon::M2_mpyu_nac_hh_s1:
10079 case Hexagon::M2_mpyu_nac_hl_s0:
10080 case Hexagon::M2_mpyu_nac_hl_s1:
10081 case Hexagon::M2_mpyu_nac_lh_s0:
10082 case Hexagon::M2_mpyu_nac_lh_s1:
10083 case Hexagon::M2_mpyu_nac_ll_s0:
10084 case Hexagon::M2_mpyu_nac_ll_s1:
10085 case Hexagon::M2_nacci:
10086 case Hexagon::M2_xor_xacc:
10087 case Hexagon::M4_and_and:
10088 case Hexagon::M4_and_andn:
10089 case Hexagon::M4_and_or:
10090 case Hexagon::M4_and_xor:
10091 case Hexagon::M4_mac_up_s1_sat:
10092 case Hexagon::M4_nac_up_s1_sat:
10093 case Hexagon::M4_or_and:
10094 case Hexagon::M4_or_andn:
10095 case Hexagon::M4_or_or:
10096 case Hexagon::M4_or_xor:
10097 case Hexagon::M4_xor_and:
10098 case Hexagon::M4_xor_andn:
10099 case Hexagon::M4_xor_or:
10100 case Hexagon::S2_asl_r_r_acc:
10101 case Hexagon::S2_asl_r_r_and:
10102 case Hexagon::S2_asl_r_r_nac:
10103 case Hexagon::S2_asl_r_r_or:
10104 case Hexagon::S2_asr_r_r_acc:
10105 case Hexagon::S2_asr_r_r_and:
10106 case Hexagon::S2_asr_r_r_nac:
10107 case Hexagon::S2_asr_r_r_or:
10108 case Hexagon::S2_lsl_r_r_acc:
10109 case Hexagon::S2_lsl_r_r_and:
10110 case Hexagon::S2_lsl_r_r_nac:
10111 case Hexagon::S2_lsl_r_r_or:
10112 case Hexagon::S2_lsr_r_r_acc:
10113 case Hexagon::S2_lsr_r_r_and:
10114 case Hexagon::S2_lsr_r_r_nac:
10115 case Hexagon::S2_lsr_r_r_or: {
10116 // op: Rs32
10117 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10118 op &= UINT64_C(31);
10119 op <<= 16;
10120 Value |= op;
10121 // op: Rt32
10122 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10123 op &= UINT64_C(31);
10124 op <<= 8;
10125 Value |= op;
10126 // op: Rx32
10127 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10128 op &= UINT64_C(31);
10129 Value |= op;
10130 break;
10131 }
10132 case Hexagon::M2_cmaci_s0:
10133 case Hexagon::M2_cmacr_s0:
10134 case Hexagon::M2_cmacs_s0:
10135 case Hexagon::M2_cmacs_s1:
10136 case Hexagon::M2_cmacsc_s0:
10137 case Hexagon::M2_cmacsc_s1:
10138 case Hexagon::M2_cnacs_s0:
10139 case Hexagon::M2_cnacs_s1:
10140 case Hexagon::M2_cnacsc_s0:
10141 case Hexagon::M2_cnacsc_s1:
10142 case Hexagon::M2_dpmpyss_acc_s0:
10143 case Hexagon::M2_dpmpyss_nac_s0:
10144 case Hexagon::M2_dpmpyuu_acc_s0:
10145 case Hexagon::M2_dpmpyuu_nac_s0:
10146 case Hexagon::M2_mpyd_acc_hh_s0:
10147 case Hexagon::M2_mpyd_acc_hh_s1:
10148 case Hexagon::M2_mpyd_acc_hl_s0:
10149 case Hexagon::M2_mpyd_acc_hl_s1:
10150 case Hexagon::M2_mpyd_acc_lh_s0:
10151 case Hexagon::M2_mpyd_acc_lh_s1:
10152 case Hexagon::M2_mpyd_acc_ll_s0:
10153 case Hexagon::M2_mpyd_acc_ll_s1:
10154 case Hexagon::M2_mpyd_nac_hh_s0:
10155 case Hexagon::M2_mpyd_nac_hh_s1:
10156 case Hexagon::M2_mpyd_nac_hl_s0:
10157 case Hexagon::M2_mpyd_nac_hl_s1:
10158 case Hexagon::M2_mpyd_nac_lh_s0:
10159 case Hexagon::M2_mpyd_nac_lh_s1:
10160 case Hexagon::M2_mpyd_nac_ll_s0:
10161 case Hexagon::M2_mpyd_nac_ll_s1:
10162 case Hexagon::M2_mpyud_acc_hh_s0:
10163 case Hexagon::M2_mpyud_acc_hh_s1:
10164 case Hexagon::M2_mpyud_acc_hl_s0:
10165 case Hexagon::M2_mpyud_acc_hl_s1:
10166 case Hexagon::M2_mpyud_acc_lh_s0:
10167 case Hexagon::M2_mpyud_acc_lh_s1:
10168 case Hexagon::M2_mpyud_acc_ll_s0:
10169 case Hexagon::M2_mpyud_acc_ll_s1:
10170 case Hexagon::M2_mpyud_nac_hh_s0:
10171 case Hexagon::M2_mpyud_nac_hh_s1:
10172 case Hexagon::M2_mpyud_nac_hl_s0:
10173 case Hexagon::M2_mpyud_nac_hl_s1:
10174 case Hexagon::M2_mpyud_nac_lh_s0:
10175 case Hexagon::M2_mpyud_nac_lh_s1:
10176 case Hexagon::M2_mpyud_nac_ll_s0:
10177 case Hexagon::M2_mpyud_nac_ll_s1:
10178 case Hexagon::M2_vmac2:
10179 case Hexagon::M2_vmac2s_s0:
10180 case Hexagon::M2_vmac2s_s1:
10181 case Hexagon::M2_vmac2su_s0:
10182 case Hexagon::M2_vmac2su_s1:
10183 case Hexagon::M4_pmpyw_acc:
10184 case Hexagon::M4_vpmpyh_acc:
10185 case Hexagon::M5_vmacbsu:
10186 case Hexagon::M5_vmacbuu: {
10187 // op: Rs32
10188 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10189 op &= UINT64_C(31);
10190 op <<= 16;
10191 Value |= op;
10192 // op: Rt32
10193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10194 op &= UINT64_C(31);
10195 op <<= 8;
10196 Value |= op;
10197 // op: Rxx32
10198 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10199 op &= UINT64_C(31);
10200 Value |= op;
10201 break;
10202 }
10203 case Hexagon::S2_insert_rp: {
10204 // op: Rs32
10205 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10206 op &= UINT64_C(31);
10207 op <<= 16;
10208 Value |= op;
10209 // op: Rtt32
10210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10211 op &= UINT64_C(31);
10212 op <<= 8;
10213 Value |= op;
10214 // op: Rx32
10215 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10216 op &= UINT64_C(31);
10217 Value |= op;
10218 break;
10219 }
10220 case Hexagon::Y2_tlbw: {
10221 // op: Rss32
10222 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10223 op &= UINT64_C(31);
10224 op <<= 16;
10225 Value |= op;
10226 // op: Rt32
10227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10228 op &= UINT64_C(31);
10229 op <<= 8;
10230 Value |= op;
10231 break;
10232 }
10233 case Hexagon::Y6_diag0:
10234 case Hexagon::Y6_diag1: {
10235 // op: Rss32
10236 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10237 op &= UINT64_C(31);
10238 op <<= 16;
10239 Value |= op;
10240 // op: Rtt32
10241 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10242 op &= UINT64_C(31);
10243 op <<= 8;
10244 Value |= op;
10245 break;
10246 }
10247 case Hexagon::A4_tfrpcp: {
10248 // op: Rss32
10249 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10250 op &= UINT64_C(31);
10251 op <<= 16;
10252 Value |= op;
10253 // op: Cdd32
10254 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10255 op &= UINT64_C(31);
10256 Value |= op;
10257 break;
10258 }
10259 case Hexagon::G4_tfrgpcp: {
10260 // op: Rss32
10261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10262 op &= UINT64_C(31);
10263 op <<= 16;
10264 Value |= op;
10265 // op: Gdd32
10266 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10267 op &= UINT64_C(31);
10268 Value |= op;
10269 break;
10270 }
10271 case Hexagon::A2_roundsat:
10272 case Hexagon::A2_sat:
10273 case Hexagon::F2_conv_d2sf:
10274 case Hexagon::F2_conv_df2sf:
10275 case Hexagon::F2_conv_df2uw:
10276 case Hexagon::F2_conv_df2uw_chop:
10277 case Hexagon::F2_conv_df2w:
10278 case Hexagon::F2_conv_df2w_chop:
10279 case Hexagon::F2_conv_ud2sf:
10280 case Hexagon::S2_cl0p:
10281 case Hexagon::S2_cl1p:
10282 case Hexagon::S2_clbp:
10283 case Hexagon::S2_ct0p:
10284 case Hexagon::S2_ct1p:
10285 case Hexagon::S2_vrndpackwh:
10286 case Hexagon::S2_vrndpackwhs:
10287 case Hexagon::S2_vsathb:
10288 case Hexagon::S2_vsathub:
10289 case Hexagon::S2_vsatwh:
10290 case Hexagon::S2_vsatwuh:
10291 case Hexagon::S2_vtrunehb:
10292 case Hexagon::S2_vtrunohb:
10293 case Hexagon::S4_clbpnorm:
10294 case Hexagon::S5_popcountp:
10295 case Hexagon::Y5_tlboc: {
10296 // op: Rss32
10297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10298 op &= UINT64_C(31);
10299 op <<= 16;
10300 Value |= op;
10301 // op: Rd32
10302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10303 op &= UINT64_C(31);
10304 Value |= op;
10305 break;
10306 }
10307 case Hexagon::A2_absp:
10308 case Hexagon::A2_negp:
10309 case Hexagon::A2_notp:
10310 case Hexagon::A2_vabsh:
10311 case Hexagon::A2_vabshsat:
10312 case Hexagon::A2_vabsw:
10313 case Hexagon::A2_vabswsat:
10314 case Hexagon::A2_vconj:
10315 case Hexagon::F2_conv_d2df:
10316 case Hexagon::F2_conv_df2d:
10317 case Hexagon::F2_conv_df2d_chop:
10318 case Hexagon::F2_conv_df2ud:
10319 case Hexagon::F2_conv_df2ud_chop:
10320 case Hexagon::F2_conv_ud2df:
10321 case Hexagon::S2_brevp:
10322 case Hexagon::S2_deinterleave:
10323 case Hexagon::S2_interleave:
10324 case Hexagon::S2_vsathb_nopack:
10325 case Hexagon::S2_vsathub_nopack:
10326 case Hexagon::S2_vsatwh_nopack:
10327 case Hexagon::S2_vsatwuh_nopack: {
10328 // op: Rss32
10329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10330 op &= UINT64_C(31);
10331 op <<= 16;
10332 Value |= op;
10333 // op: Rdd32
10334 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10335 op &= UINT64_C(31);
10336 Value |= op;
10337 break;
10338 }
10339 case Hexagon::A4_tlbmatch: {
10340 // op: Rss32
10341 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10342 op &= UINT64_C(31);
10343 op <<= 16;
10344 Value |= op;
10345 // op: Rt32
10346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10347 op &= UINT64_C(31);
10348 op <<= 8;
10349 Value |= op;
10350 // op: Pd4
10351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10352 op &= UINT64_C(3);
10353 Value |= op;
10354 break;
10355 }
10356 case Hexagon::M4_cmpyi_wh:
10357 case Hexagon::M4_cmpyi_whc:
10358 case Hexagon::M4_cmpyr_wh:
10359 case Hexagon::M4_cmpyr_whc:
10360 case Hexagon::S2_asr_r_svw_trun:
10361 case Hexagon::Y5_ctlbw: {
10362 // op: Rss32
10363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10364 op &= UINT64_C(31);
10365 op <<= 16;
10366 Value |= op;
10367 // op: Rt32
10368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10369 op &= UINT64_C(31);
10370 op <<= 8;
10371 Value |= op;
10372 // op: Rd32
10373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10374 op &= UINT64_C(31);
10375 Value |= op;
10376 break;
10377 }
10378 case Hexagon::A7_croundd_rr:
10379 case Hexagon::S2_asl_r_p:
10380 case Hexagon::S2_asl_r_vh:
10381 case Hexagon::S2_asl_r_vw:
10382 case Hexagon::S2_asr_r_p:
10383 case Hexagon::S2_asr_r_vh:
10384 case Hexagon::S2_asr_r_vw:
10385 case Hexagon::S2_lsl_r_p:
10386 case Hexagon::S2_lsl_r_vh:
10387 case Hexagon::S2_lsl_r_vw:
10388 case Hexagon::S2_lsr_r_p:
10389 case Hexagon::S2_lsr_r_vh:
10390 case Hexagon::S2_lsr_r_vw:
10391 case Hexagon::S2_vcnegh:
10392 case Hexagon::S2_vcrotate: {
10393 // op: Rss32
10394 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10395 op &= UINT64_C(31);
10396 op <<= 16;
10397 Value |= op;
10398 // op: Rt32
10399 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10400 op &= UINT64_C(31);
10401 op <<= 8;
10402 Value |= op;
10403 // op: Rdd32
10404 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10405 op &= UINT64_C(31);
10406 Value |= op;
10407 break;
10408 }
10409 case Hexagon::A2_vcmpbeq:
10410 case Hexagon::A2_vcmpbgtu:
10411 case Hexagon::A2_vcmpheq:
10412 case Hexagon::A2_vcmphgt:
10413 case Hexagon::A2_vcmphgtu:
10414 case Hexagon::A2_vcmpweq:
10415 case Hexagon::A2_vcmpwgt:
10416 case Hexagon::A2_vcmpwgtu:
10417 case Hexagon::A4_boundscheck_hi:
10418 case Hexagon::A4_boundscheck_lo:
10419 case Hexagon::A4_vcmpbeq_any:
10420 case Hexagon::A4_vcmpbgt:
10421 case Hexagon::A6_vcmpbeq_notany:
10422 case Hexagon::C2_cmpeqp:
10423 case Hexagon::C2_cmpgtp:
10424 case Hexagon::C2_cmpgtup:
10425 case Hexagon::F2_dfcmpeq:
10426 case Hexagon::F2_dfcmpge:
10427 case Hexagon::F2_dfcmpgt:
10428 case Hexagon::F2_dfcmpuo: {
10429 // op: Rss32
10430 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10431 op &= UINT64_C(31);
10432 op <<= 16;
10433 Value |= op;
10434 // op: Rtt32
10435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10436 op &= UINT64_C(31);
10437 op <<= 8;
10438 Value |= op;
10439 // op: Pd4
10440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10441 op &= UINT64_C(3);
10442 Value |= op;
10443 break;
10444 }
10445 case Hexagon::S2_vsplicerb: {
10446 // op: Rss32
10447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10448 op &= UINT64_C(31);
10449 op <<= 16;
10450 Value |= op;
10451 // op: Rtt32
10452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10453 op &= UINT64_C(31);
10454 op <<= 8;
10455 Value |= op;
10456 // op: Pu4
10457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10458 op &= UINT64_C(3);
10459 op <<= 5;
10460 Value |= op;
10461 // op: Rdd32
10462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10463 op &= UINT64_C(31);
10464 Value |= op;
10465 break;
10466 }
10467 case Hexagon::A5_vaddhubs:
10468 case Hexagon::M2_vdmpyrs_s0:
10469 case Hexagon::M2_vdmpyrs_s1:
10470 case Hexagon::M2_vraddh:
10471 case Hexagon::M2_vradduh:
10472 case Hexagon::M2_vrcmpys_s1rp_h:
10473 case Hexagon::M2_vrcmpys_s1rp_l:
10474 case Hexagon::M7_wcmpyiw:
10475 case Hexagon::M7_wcmpyiw_rnd:
10476 case Hexagon::M7_wcmpyiwc:
10477 case Hexagon::M7_wcmpyiwc_rnd:
10478 case Hexagon::M7_wcmpyrw:
10479 case Hexagon::M7_wcmpyrw_rnd:
10480 case Hexagon::M7_wcmpyrwc:
10481 case Hexagon::M7_wcmpyrwc_rnd:
10482 case Hexagon::S2_parityp: {
10483 // op: Rss32
10484 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10485 op &= UINT64_C(31);
10486 op <<= 16;
10487 Value |= op;
10488 // op: Rtt32
10489 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10490 op &= UINT64_C(31);
10491 op <<= 8;
10492 Value |= op;
10493 // op: Rd32
10494 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10495 op &= UINT64_C(31);
10496 Value |= op;
10497 break;
10498 }
10499 case Hexagon::A2_addp:
10500 case Hexagon::A2_addpsat:
10501 case Hexagon::A2_addsph:
10502 case Hexagon::A2_addspl:
10503 case Hexagon::A2_andp:
10504 case Hexagon::A2_maxp:
10505 case Hexagon::A2_maxup:
10506 case Hexagon::A2_orp:
10507 case Hexagon::A2_vaddh:
10508 case Hexagon::A2_vaddhs:
10509 case Hexagon::A2_vaddub:
10510 case Hexagon::A2_vaddubs:
10511 case Hexagon::A2_vadduhs:
10512 case Hexagon::A2_vaddw:
10513 case Hexagon::A2_vaddws:
10514 case Hexagon::A2_vavgh:
10515 case Hexagon::A2_vavghcr:
10516 case Hexagon::A2_vavghr:
10517 case Hexagon::A2_vavgub:
10518 case Hexagon::A2_vavgubr:
10519 case Hexagon::A2_vavguh:
10520 case Hexagon::A2_vavguhr:
10521 case Hexagon::A2_vavguw:
10522 case Hexagon::A2_vavguwr:
10523 case Hexagon::A2_vavgw:
10524 case Hexagon::A2_vavgwcr:
10525 case Hexagon::A2_vavgwr:
10526 case Hexagon::A2_vraddub:
10527 case Hexagon::A2_vrsadub:
10528 case Hexagon::A2_xorp:
10529 case Hexagon::F2_dfadd:
10530 case Hexagon::F2_dfmax:
10531 case Hexagon::F2_dfmin:
10532 case Hexagon::F2_dfmpyfix:
10533 case Hexagon::F2_dfmpyll:
10534 case Hexagon::F2_dfsub:
10535 case Hexagon::M2_mmpyh_rs0:
10536 case Hexagon::M2_mmpyh_rs1:
10537 case Hexagon::M2_mmpyh_s0:
10538 case Hexagon::M2_mmpyh_s1:
10539 case Hexagon::M2_mmpyl_rs0:
10540 case Hexagon::M2_mmpyl_rs1:
10541 case Hexagon::M2_mmpyl_s0:
10542 case Hexagon::M2_mmpyl_s1:
10543 case Hexagon::M2_mmpyuh_rs0:
10544 case Hexagon::M2_mmpyuh_rs1:
10545 case Hexagon::M2_mmpyuh_s0:
10546 case Hexagon::M2_mmpyuh_s1:
10547 case Hexagon::M2_mmpyul_rs0:
10548 case Hexagon::M2_mmpyul_rs1:
10549 case Hexagon::M2_mmpyul_s0:
10550 case Hexagon::M2_mmpyul_s1:
10551 case Hexagon::M2_vcmpy_s0_sat_i:
10552 case Hexagon::M2_vcmpy_s0_sat_r:
10553 case Hexagon::M2_vcmpy_s1_sat_i:
10554 case Hexagon::M2_vcmpy_s1_sat_r:
10555 case Hexagon::M2_vdmpys_s0:
10556 case Hexagon::M2_vdmpys_s1:
10557 case Hexagon::M2_vmpy2es_s0:
10558 case Hexagon::M2_vmpy2es_s1:
10559 case Hexagon::M2_vrcmpyi_s0:
10560 case Hexagon::M2_vrcmpyi_s0c:
10561 case Hexagon::M2_vrcmpyr_s0:
10562 case Hexagon::M2_vrcmpyr_s0c:
10563 case Hexagon::M2_vrcmpys_s1_h:
10564 case Hexagon::M2_vrcmpys_s1_l:
10565 case Hexagon::M2_vrmpy_s0:
10566 case Hexagon::M4_vrmpyeh_s0:
10567 case Hexagon::M4_vrmpyeh_s1:
10568 case Hexagon::M4_vrmpyoh_s0:
10569 case Hexagon::M4_vrmpyoh_s1:
10570 case Hexagon::M5_vdmpybsu:
10571 case Hexagon::M5_vrmpybsu:
10572 case Hexagon::M5_vrmpybuu:
10573 case Hexagon::M7_dcmpyiw:
10574 case Hexagon::M7_dcmpyiwc:
10575 case Hexagon::M7_dcmpyrw:
10576 case Hexagon::M7_dcmpyrwc:
10577 case Hexagon::S2_cabacdecbin:
10578 case Hexagon::S2_extractup_rp:
10579 case Hexagon::S2_lfsp:
10580 case Hexagon::S2_shuffeb:
10581 case Hexagon::S2_shuffeh:
10582 case Hexagon::S2_vtrunewh:
10583 case Hexagon::S2_vtrunowh:
10584 case Hexagon::S4_extractp_rp:
10585 case Hexagon::S4_vxaddsubh:
10586 case Hexagon::S4_vxaddsubhr:
10587 case Hexagon::S4_vxaddsubw:
10588 case Hexagon::S4_vxsubaddh:
10589 case Hexagon::S4_vxsubaddhr:
10590 case Hexagon::S4_vxsubaddw:
10591 case Hexagon::S6_vtrunehb_ppp:
10592 case Hexagon::S6_vtrunohb_ppp: {
10593 // op: Rss32
10594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10595 op &= UINT64_C(31);
10596 op <<= 16;
10597 Value |= op;
10598 // op: Rtt32
10599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10600 op &= UINT64_C(31);
10601 op <<= 8;
10602 Value |= op;
10603 // op: Rdd32
10604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10605 op &= UINT64_C(31);
10606 Value |= op;
10607 break;
10608 }
10609 case Hexagon::Y4_tfrspcp: {
10610 // op: Rss32
10611 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10612 op &= UINT64_C(31);
10613 op <<= 16;
10614 Value |= op;
10615 // op: Sdd128
10616 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10617 op &= UINT64_C(127);
10618 Value |= op;
10619 break;
10620 }
10621 case Hexagon::S2_asl_r_p_acc:
10622 case Hexagon::S2_asl_r_p_and:
10623 case Hexagon::S2_asl_r_p_nac:
10624 case Hexagon::S2_asl_r_p_or:
10625 case Hexagon::S2_asl_r_p_xor:
10626 case Hexagon::S2_asr_r_p_acc:
10627 case Hexagon::S2_asr_r_p_and:
10628 case Hexagon::S2_asr_r_p_nac:
10629 case Hexagon::S2_asr_r_p_or:
10630 case Hexagon::S2_asr_r_p_xor:
10631 case Hexagon::S2_lsl_r_p_acc:
10632 case Hexagon::S2_lsl_r_p_and:
10633 case Hexagon::S2_lsl_r_p_nac:
10634 case Hexagon::S2_lsl_r_p_or:
10635 case Hexagon::S2_lsl_r_p_xor:
10636 case Hexagon::S2_lsr_r_p_acc:
10637 case Hexagon::S2_lsr_r_p_and:
10638 case Hexagon::S2_lsr_r_p_nac:
10639 case Hexagon::S2_lsr_r_p_or:
10640 case Hexagon::S2_lsr_r_p_xor:
10641 case Hexagon::S2_vrcnegh: {
10642 // op: Rss32
10643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10644 op &= UINT64_C(31);
10645 op <<= 16;
10646 Value |= op;
10647 // op: Rt32
10648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10649 op &= UINT64_C(31);
10650 op <<= 8;
10651 Value |= op;
10652 // op: Rxx32
10653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10654 op &= UINT64_C(31);
10655 Value |= op;
10656 break;
10657 }
10658 case Hexagon::A4_addp_c:
10659 case Hexagon::A4_subp_c: {
10660 // op: Rss32
10661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10662 op &= UINT64_C(31);
10663 op <<= 16;
10664 Value |= op;
10665 // op: Rtt32
10666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10667 op &= UINT64_C(31);
10668 op <<= 8;
10669 Value |= op;
10670 // op: Rdd32
10671 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10672 op &= UINT64_C(31);
10673 Value |= op;
10674 // op: Px4
10675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10676 op &= UINT64_C(3);
10677 op <<= 5;
10678 Value |= op;
10679 break;
10680 }
10681 case Hexagon::A2_vraddub_acc:
10682 case Hexagon::A2_vrsadub_acc:
10683 case Hexagon::F2_dfmpyhh:
10684 case Hexagon::F2_dfmpylh:
10685 case Hexagon::M2_mmachs_rs0:
10686 case Hexagon::M2_mmachs_rs1:
10687 case Hexagon::M2_mmachs_s0:
10688 case Hexagon::M2_mmachs_s1:
10689 case Hexagon::M2_mmacls_rs0:
10690 case Hexagon::M2_mmacls_rs1:
10691 case Hexagon::M2_mmacls_s0:
10692 case Hexagon::M2_mmacls_s1:
10693 case Hexagon::M2_mmacuhs_rs0:
10694 case Hexagon::M2_mmacuhs_rs1:
10695 case Hexagon::M2_mmacuhs_s0:
10696 case Hexagon::M2_mmacuhs_s1:
10697 case Hexagon::M2_mmaculs_rs0:
10698 case Hexagon::M2_mmaculs_rs1:
10699 case Hexagon::M2_mmaculs_s0:
10700 case Hexagon::M2_mmaculs_s1:
10701 case Hexagon::M2_vcmac_s0_sat_i:
10702 case Hexagon::M2_vcmac_s0_sat_r:
10703 case Hexagon::M2_vdmacs_s0:
10704 case Hexagon::M2_vdmacs_s1:
10705 case Hexagon::M2_vmac2es:
10706 case Hexagon::M2_vmac2es_s0:
10707 case Hexagon::M2_vmac2es_s1:
10708 case Hexagon::M2_vrcmaci_s0:
10709 case Hexagon::M2_vrcmaci_s0c:
10710 case Hexagon::M2_vrcmacr_s0:
10711 case Hexagon::M2_vrcmacr_s0c:
10712 case Hexagon::M2_vrcmpys_acc_s1_h:
10713 case Hexagon::M2_vrcmpys_acc_s1_l:
10714 case Hexagon::M2_vrmac_s0:
10715 case Hexagon::M4_vrmpyeh_acc_s0:
10716 case Hexagon::M4_vrmpyeh_acc_s1:
10717 case Hexagon::M4_vrmpyoh_acc_s0:
10718 case Hexagon::M4_vrmpyoh_acc_s1:
10719 case Hexagon::M4_xor_xacc:
10720 case Hexagon::M5_vdmacbsu:
10721 case Hexagon::M5_vrmacbsu:
10722 case Hexagon::M5_vrmacbuu:
10723 case Hexagon::M7_dcmpyiw_acc:
10724 case Hexagon::M7_dcmpyiwc_acc:
10725 case Hexagon::M7_dcmpyrw_acc:
10726 case Hexagon::M7_dcmpyrwc_acc:
10727 case Hexagon::S2_insertp_rp: {
10728 // op: Rss32
10729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10730 op &= UINT64_C(31);
10731 op <<= 16;
10732 Value |= op;
10733 // op: Rtt32
10734 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10735 op &= UINT64_C(31);
10736 op <<= 8;
10737 Value |= op;
10738 // op: Rxx32
10739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10740 op &= UINT64_C(31);
10741 Value |= op;
10742 break;
10743 }
10744 case Hexagon::A4_vrmaxh:
10745 case Hexagon::A4_vrmaxuh:
10746 case Hexagon::A4_vrmaxuw:
10747 case Hexagon::A4_vrmaxw:
10748 case Hexagon::A4_vrminh:
10749 case Hexagon::A4_vrminuh:
10750 case Hexagon::A4_vrminuw:
10751 case Hexagon::A4_vrminw: {
10752 // op: Rss32
10753 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10754 op &= UINT64_C(31);
10755 op <<= 16;
10756 Value |= op;
10757 // op: Ru32
10758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10759 op &= UINT64_C(31);
10760 Value |= op;
10761 // op: Rxx32
10762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10763 op &= UINT64_C(31);
10764 op <<= 8;
10765 Value |= op;
10766 break;
10767 }
10768 case Hexagon::A5_ACS: {
10769 // op: Rss32
10770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10771 op &= UINT64_C(31);
10772 op <<= 16;
10773 Value |= op;
10774 // op: Rtt32
10775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
10776 op &= UINT64_C(31);
10777 op <<= 8;
10778 Value |= op;
10779 // op: Rxx32
10780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10781 op &= UINT64_C(31);
10782 Value |= op;
10783 // op: Pe4
10784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10785 op &= UINT64_C(3);
10786 op <<= 5;
10787 Value |= op;
10788 break;
10789 }
10790 case Hexagon::V6_vgathermh:
10791 case Hexagon::V6_vgathermw: {
10792 // op: Rt32
10793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10794 op &= UINT64_C(31);
10795 op <<= 16;
10796 Value |= op;
10797 // op: Mu2
10798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10799 op &= UINT64_C(1);
10800 op <<= 13;
10801 Value |= op;
10802 // op: Vv32
10803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10804 op &= UINT64_C(31);
10805 Value |= op;
10806 break;
10807 }
10808 case Hexagon::V6_vscattermh:
10809 case Hexagon::V6_vscattermh_add:
10810 case Hexagon::V6_vscattermw:
10811 case Hexagon::V6_vscattermw_add: {
10812 // op: Rt32
10813 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10814 op &= UINT64_C(31);
10815 op <<= 16;
10816 Value |= op;
10817 // op: Mu2
10818 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10819 op &= UINT64_C(1);
10820 op <<= 13;
10821 Value |= op;
10822 // op: Vv32
10823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10824 op &= UINT64_C(31);
10825 op <<= 8;
10826 Value |= op;
10827 // op: Vw32
10828 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10829 op &= UINT64_C(31);
10830 Value |= op;
10831 break;
10832 }
10833 case Hexagon::V6_vgathermhw: {
10834 // op: Rt32
10835 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10836 op &= UINT64_C(31);
10837 op <<= 16;
10838 Value |= op;
10839 // op: Mu2
10840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10841 op &= UINT64_C(1);
10842 op <<= 13;
10843 Value |= op;
10844 // op: Vvv32
10845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10846 op &= UINT64_C(31);
10847 Value |= op;
10848 break;
10849 }
10850 case Hexagon::V6_vscattermhw:
10851 case Hexagon::V6_vscattermhw_add: {
10852 // op: Rt32
10853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10854 op &= UINT64_C(31);
10855 op <<= 16;
10856 Value |= op;
10857 // op: Mu2
10858 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10859 op &= UINT64_C(1);
10860 op <<= 13;
10861 Value |= op;
10862 // op: Vvv32
10863 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10864 op &= UINT64_C(31);
10865 op <<= 8;
10866 Value |= op;
10867 // op: Vw32
10868 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10869 op &= UINT64_C(31);
10870 Value |= op;
10871 break;
10872 }
10873 case Hexagon::V6_pred_scalar2:
10874 case Hexagon::V6_pred_scalar2v2: {
10875 // op: Rt32
10876 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10877 op &= UINT64_C(31);
10878 op <<= 16;
10879 Value |= op;
10880 // op: Qd4
10881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10882 op &= UINT64_C(3);
10883 Value |= op;
10884 break;
10885 }
10886 case Hexagon::V6_lvsplatb:
10887 case Hexagon::V6_lvsplath:
10888 case Hexagon::V6_lvsplatw:
10889 case Hexagon::V6_zextract: {
10890 // op: Rt32
10891 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10892 op &= UINT64_C(31);
10893 op <<= 16;
10894 Value |= op;
10895 // op: Vd32
10896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10897 op &= UINT64_C(31);
10898 Value |= op;
10899 break;
10900 }
10901 case Hexagon::A2_addh_h16_hh:
10902 case Hexagon::A2_addh_h16_hl:
10903 case Hexagon::A2_addh_h16_lh:
10904 case Hexagon::A2_addh_h16_ll:
10905 case Hexagon::A2_addh_h16_sat_hh:
10906 case Hexagon::A2_addh_h16_sat_hl:
10907 case Hexagon::A2_addh_h16_sat_lh:
10908 case Hexagon::A2_addh_h16_sat_ll:
10909 case Hexagon::A2_addh_l16_hl:
10910 case Hexagon::A2_addh_l16_ll:
10911 case Hexagon::A2_addh_l16_sat_hl:
10912 case Hexagon::A2_addh_l16_sat_ll:
10913 case Hexagon::A2_combine_hh:
10914 case Hexagon::A2_combine_hl:
10915 case Hexagon::A2_combine_lh:
10916 case Hexagon::A2_combine_ll:
10917 case Hexagon::A2_min:
10918 case Hexagon::A2_minu:
10919 case Hexagon::A2_sub:
10920 case Hexagon::A2_subh_h16_hh:
10921 case Hexagon::A2_subh_h16_hl:
10922 case Hexagon::A2_subh_h16_lh:
10923 case Hexagon::A2_subh_h16_ll:
10924 case Hexagon::A2_subh_h16_sat_hh:
10925 case Hexagon::A2_subh_h16_sat_hl:
10926 case Hexagon::A2_subh_h16_sat_lh:
10927 case Hexagon::A2_subh_h16_sat_ll:
10928 case Hexagon::A2_subh_l16_hl:
10929 case Hexagon::A2_subh_l16_ll:
10930 case Hexagon::A2_subh_l16_sat_hl:
10931 case Hexagon::A2_subh_l16_sat_ll:
10932 case Hexagon::A2_subsat:
10933 case Hexagon::A2_svnavgh:
10934 case Hexagon::A2_svsubh:
10935 case Hexagon::A2_svsubhs:
10936 case Hexagon::A2_svsubuhs:
10937 case Hexagon::A4_andn:
10938 case Hexagon::A4_orn:
10939 case Hexagon::dep_A2_subsat: {
10940 // op: Rt32
10941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10942 op &= UINT64_C(31);
10943 op <<= 8;
10944 Value |= op;
10945 // op: Rs32
10946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10947 op &= UINT64_C(31);
10948 op <<= 16;
10949 Value |= op;
10950 // op: Rd32
10951 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10952 op &= UINT64_C(31);
10953 Value |= op;
10954 break;
10955 }
10956 case Hexagon::V6_vinsertwr: {
10957 // op: Rt32
10958 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10959 op &= UINT64_C(31);
10960 op <<= 16;
10961 Value |= op;
10962 // op: Vx32
10963 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10964 op &= UINT64_C(31);
10965 Value |= op;
10966 break;
10967 }
10968 case Hexagon::M2_subacc: {
10969 // op: Rt32
10970 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10971 op &= UINT64_C(31);
10972 op <<= 8;
10973 Value |= op;
10974 // op: Rs32
10975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10976 op &= UINT64_C(31);
10977 op <<= 16;
10978 Value |= op;
10979 // op: Rx32
10980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10981 op &= UINT64_C(31);
10982 Value |= op;
10983 break;
10984 }
10985 case Hexagon::V6_vdeal:
10986 case Hexagon::V6_vshuff: {
10987 // op: Rt32
10988 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
10989 op &= UINT64_C(31);
10990 op <<= 16;
10991 Value |= op;
10992 // op: Vy32
10993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10994 op &= UINT64_C(31);
10995 op <<= 8;
10996 Value |= op;
10997 // op: Vx32
10998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10999 op &= UINT64_C(31);
11000 Value |= op;
11001 break;
11002 }
11003 case Hexagon::Y6_l2gcleaninvpa:
11004 case Hexagon::Y6_l2gcleanpa: {
11005 // op: Rtt32
11006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11007 op &= UINT64_C(31);
11008 op <<= 8;
11009 Value |= op;
11010 break;
11011 }
11012 case Hexagon::S2_valignrb: {
11013 // op: Rtt32
11014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11015 op &= UINT64_C(31);
11016 op <<= 8;
11017 Value |= op;
11018 // op: Rss32
11019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11020 op &= UINT64_C(31);
11021 op <<= 16;
11022 Value |= op;
11023 // op: Pu4
11024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11025 op &= UINT64_C(3);
11026 op <<= 5;
11027 Value |= op;
11028 // op: Rdd32
11029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11030 op &= UINT64_C(31);
11031 Value |= op;
11032 break;
11033 }
11034 case Hexagon::A2_minp:
11035 case Hexagon::A2_minup:
11036 case Hexagon::A2_subp:
11037 case Hexagon::A2_vmaxb:
11038 case Hexagon::A2_vmaxh:
11039 case Hexagon::A2_vmaxub:
11040 case Hexagon::A2_vmaxuh:
11041 case Hexagon::A2_vmaxuw:
11042 case Hexagon::A2_vmaxw:
11043 case Hexagon::A2_vminb:
11044 case Hexagon::A2_vminh:
11045 case Hexagon::A2_vminub:
11046 case Hexagon::A2_vminuh:
11047 case Hexagon::A2_vminuw:
11048 case Hexagon::A2_vminw:
11049 case Hexagon::A2_vnavgh:
11050 case Hexagon::A2_vnavghcr:
11051 case Hexagon::A2_vnavghr:
11052 case Hexagon::A2_vnavgw:
11053 case Hexagon::A2_vnavgwcr:
11054 case Hexagon::A2_vnavgwr:
11055 case Hexagon::A2_vsubh:
11056 case Hexagon::A2_vsubhs:
11057 case Hexagon::A2_vsubub:
11058 case Hexagon::A2_vsububs:
11059 case Hexagon::A2_vsubuhs:
11060 case Hexagon::A2_vsubw:
11061 case Hexagon::A2_vsubws:
11062 case Hexagon::A4_andnp:
11063 case Hexagon::A4_ornp:
11064 case Hexagon::M2_vabsdiffh:
11065 case Hexagon::M2_vabsdiffw:
11066 case Hexagon::M6_vabsdiffb:
11067 case Hexagon::M6_vabsdiffub:
11068 case Hexagon::S2_shuffob:
11069 case Hexagon::S2_shuffoh: {
11070 // op: Rtt32
11071 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11072 op &= UINT64_C(31);
11073 op <<= 8;
11074 Value |= op;
11075 // op: Rss32
11076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11077 op &= UINT64_C(31);
11078 op <<= 16;
11079 Value |= op;
11080 // op: Rdd32
11081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11082 op &= UINT64_C(31);
11083 Value |= op;
11084 break;
11085 }
11086 case Hexagon::A6_vminub_RdP: {
11087 // op: Rtt32
11088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11089 op &= UINT64_C(31);
11090 op <<= 8;
11091 Value |= op;
11092 // op: Rss32
11093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11094 op &= UINT64_C(31);
11095 op <<= 16;
11096 Value |= op;
11097 // op: Rdd32
11098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11099 op &= UINT64_C(31);
11100 Value |= op;
11101 // op: Pe4
11102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11103 op &= UINT64_C(3);
11104 op <<= 5;
11105 Value |= op;
11106 break;
11107 }
11108 case Hexagon::M4_mpyrr_addr: {
11109 // op: Ru32
11110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11111 op &= UINT64_C(31);
11112 Value |= op;
11113 // op: Rs32
11114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11115 op &= UINT64_C(31);
11116 op <<= 16;
11117 Value |= op;
11118 // op: Ry32
11119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11120 op &= UINT64_C(31);
11121 op <<= 8;
11122 Value |= op;
11123 break;
11124 }
11125 case Hexagon::Y2_crswap0:
11126 case Hexagon::Y4_crswap1: {
11127 // op: Rx32
11128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11129 op &= UINT64_C(31);
11130 op <<= 16;
11131 Value |= op;
11132 break;
11133 }
11134 case Hexagon::Y4_crswap10: {
11135 // op: Rxx32
11136 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11137 op &= UINT64_C(31);
11138 op <<= 16;
11139 Value |= op;
11140 break;
11141 }
11142 case Hexagon::Y2_tfrscrr: {
11143 // op: Ss128
11144 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11145 op &= UINT64_C(127);
11146 op <<= 16;
11147 Value |= op;
11148 // op: Rd32
11149 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11150 op &= UINT64_C(31);
11151 Value |= op;
11152 break;
11153 }
11154 case Hexagon::Y4_tfrscpp: {
11155 // op: Sss128
11156 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11157 op &= UINT64_C(127);
11158 op <<= 16;
11159 Value |= op;
11160 // op: Rdd32
11161 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11162 op &= UINT64_C(31);
11163 Value |= op;
11164 break;
11165 }
11166 case Hexagon::V6_extractw: {
11167 // op: Vu32
11168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11169 op &= UINT64_C(31);
11170 op <<= 8;
11171 Value |= op;
11172 // op: Rs32
11173 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11174 op &= UINT64_C(31);
11175 op <<= 16;
11176 Value |= op;
11177 // op: Rd32
11178 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11179 op &= UINT64_C(31);
11180 Value |= op;
11181 break;
11182 }
11183 case Hexagon::V6_vandvrt: {
11184 // op: Vu32
11185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11186 op &= UINT64_C(31);
11187 op <<= 8;
11188 Value |= op;
11189 // op: Rt32
11190 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11191 op &= UINT64_C(31);
11192 op <<= 16;
11193 Value |= op;
11194 // op: Qd4
11195 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11196 op &= UINT64_C(3);
11197 Value |= op;
11198 break;
11199 }
11200 case Hexagon::V6_get_qfext:
11201 case Hexagon::V6_set_qfext:
11202 case Hexagon::V6_vaslh:
11203 case Hexagon::V6_vaslw:
11204 case Hexagon::V6_vasrh:
11205 case Hexagon::V6_vasrw:
11206 case Hexagon::V6_vdmpybus:
11207 case Hexagon::V6_vdmpyhb:
11208 case Hexagon::V6_vdmpyhsat:
11209 case Hexagon::V6_vdmpyhsusat:
11210 case Hexagon::V6_vlsrb:
11211 case Hexagon::V6_vlsrh:
11212 case Hexagon::V6_vlsrw:
11213 case Hexagon::V6_vmpy_rt_hf:
11214 case Hexagon::V6_vmpy_rt_qf16:
11215 case Hexagon::V6_vmpy_rt_sf:
11216 case Hexagon::V6_vmpyhsrs:
11217 case Hexagon::V6_vmpyhss:
11218 case Hexagon::V6_vmpyihb:
11219 case Hexagon::V6_vmpyiwb:
11220 case Hexagon::V6_vmpyiwh:
11221 case Hexagon::V6_vmpyiwub:
11222 case Hexagon::V6_vmpyuhe:
11223 case Hexagon::V6_vrmpybus:
11224 case Hexagon::V6_vrmpyub:
11225 case Hexagon::V6_vror: {
11226 // op: Vu32
11227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11228 op &= UINT64_C(31);
11229 op <<= 8;
11230 Value |= op;
11231 // op: Rt32
11232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11233 op &= UINT64_C(31);
11234 op <<= 16;
11235 Value |= op;
11236 // op: Vd32
11237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11238 op &= UINT64_C(31);
11239 Value |= op;
11240 break;
11241 }
11242 case Hexagon::V6_vmpybus:
11243 case Hexagon::V6_vmpyh:
11244 case Hexagon::V6_vmpyub:
11245 case Hexagon::V6_vmpyuh: {
11246 // op: Vu32
11247 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11248 op &= UINT64_C(31);
11249 op <<= 8;
11250 Value |= op;
11251 // op: Rt32
11252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11253 op &= UINT64_C(31);
11254 op <<= 16;
11255 Value |= op;
11256 // op: Vdd32
11257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11258 op &= UINT64_C(31);
11259 Value |= op;
11260 break;
11261 }
11262 case Hexagon::V6_vrmpyzbb_rt:
11263 case Hexagon::V6_vrmpyzbub_rt:
11264 case Hexagon::V6_vrmpyzcb_rt:
11265 case Hexagon::V6_vrmpyzcbs_rt:
11266 case Hexagon::V6_vrmpyznb_rt: {
11267 // op: Vu32
11268 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11269 op &= UINT64_C(31);
11270 op <<= 8;
11271 Value |= op;
11272 // op: Rt8
11273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11274 op &= UINT64_C(7);
11275 op <<= 16;
11276 Value |= op;
11277 // op: Vdddd32
11278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11279 op &= UINT64_C(31);
11280 Value |= op;
11281 break;
11282 }
11283 case Hexagon::V6_vlut4: {
11284 // op: Vu32
11285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11286 op &= UINT64_C(31);
11287 op <<= 8;
11288 Value |= op;
11289 // op: Rtt32
11290 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11291 op &= UINT64_C(31);
11292 op <<= 16;
11293 Value |= op;
11294 // op: Vd32
11295 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11296 op &= UINT64_C(31);
11297 Value |= op;
11298 break;
11299 }
11300 case Hexagon::V6_vrmpybub_rtt:
11301 case Hexagon::V6_vrmpyub_rtt: {
11302 // op: Vu32
11303 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11304 op &= UINT64_C(31);
11305 op <<= 8;
11306 Value |= op;
11307 // op: Rtt32
11308 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11309 op &= UINT64_C(31);
11310 op <<= 16;
11311 Value |= op;
11312 // op: Vdd32
11313 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11314 op &= UINT64_C(31);
11315 Value |= op;
11316 break;
11317 }
11318 case Hexagon::V6_vabs_f8:
11319 case Hexagon::V6_vabs_hf:
11320 case Hexagon::V6_vabs_sf:
11321 case Hexagon::V6_vabsb:
11322 case Hexagon::V6_vabsb_sat:
11323 case Hexagon::V6_vabsh:
11324 case Hexagon::V6_vabsh_sat:
11325 case Hexagon::V6_vabsw:
11326 case Hexagon::V6_vabsw_sat:
11327 case Hexagon::V6_vassign:
11328 case Hexagon::V6_vassign_fp:
11329 case Hexagon::V6_vassign_tmp:
11330 case Hexagon::V6_vcl0h:
11331 case Hexagon::V6_vcl0w:
11332 case Hexagon::V6_vconv_h_hf:
11333 case Hexagon::V6_vconv_hf_h:
11334 case Hexagon::V6_vconv_hf_qf16:
11335 case Hexagon::V6_vconv_sf_qf32:
11336 case Hexagon::V6_vconv_sf_w:
11337 case Hexagon::V6_vconv_w_sf:
11338 case Hexagon::V6_vcvt_h_hf:
11339 case Hexagon::V6_vcvt_hf_h:
11340 case Hexagon::V6_vcvt_hf_uh:
11341 case Hexagon::V6_vcvt_uh_hf:
11342 case Hexagon::V6_vdealb:
11343 case Hexagon::V6_vdealh:
11344 case Hexagon::V6_vfneg_f8:
11345 case Hexagon::V6_vfneg_hf:
11346 case Hexagon::V6_vfneg_sf:
11347 case Hexagon::V6_vnormamth:
11348 case Hexagon::V6_vnormamtw:
11349 case Hexagon::V6_vnot:
11350 case Hexagon::V6_vpopcounth:
11351 case Hexagon::V6_vshuffb:
11352 case Hexagon::V6_vshuffh: {
11353 // op: Vu32
11354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11355 op &= UINT64_C(31);
11356 op <<= 8;
11357 Value |= op;
11358 // op: Vd32
11359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11360 op &= UINT64_C(31);
11361 Value |= op;
11362 break;
11363 }
11364 case Hexagon::V6_vcvt2_hf_b:
11365 case Hexagon::V6_vcvt2_hf_ub:
11366 case Hexagon::V6_vcvt_hf_b:
11367 case Hexagon::V6_vcvt_hf_f8:
11368 case Hexagon::V6_vcvt_hf_ub:
11369 case Hexagon::V6_vcvt_sf_hf:
11370 case Hexagon::V6_vsb:
11371 case Hexagon::V6_vsh:
11372 case Hexagon::V6_vunpackb:
11373 case Hexagon::V6_vunpackh:
11374 case Hexagon::V6_vunpackub:
11375 case Hexagon::V6_vunpackuh:
11376 case Hexagon::V6_vzb:
11377 case Hexagon::V6_vzh: {
11378 // op: Vu32
11379 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11380 op &= UINT64_C(31);
11381 op <<= 8;
11382 Value |= op;
11383 // op: Vdd32
11384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11385 op &= UINT64_C(31);
11386 Value |= op;
11387 break;
11388 }
11389 case Hexagon::V6_veqb:
11390 case Hexagon::V6_veqh:
11391 case Hexagon::V6_veqw:
11392 case Hexagon::V6_vgtb:
11393 case Hexagon::V6_vgtbf:
11394 case Hexagon::V6_vgth:
11395 case Hexagon::V6_vgthf:
11396 case Hexagon::V6_vgtsf:
11397 case Hexagon::V6_vgtub:
11398 case Hexagon::V6_vgtuh:
11399 case Hexagon::V6_vgtuw:
11400 case Hexagon::V6_vgtw: {
11401 // op: Vu32
11402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11403 op &= UINT64_C(31);
11404 op <<= 8;
11405 Value |= op;
11406 // op: Vv32
11407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11408 op &= UINT64_C(31);
11409 op <<= 16;
11410 Value |= op;
11411 // op: Qd4
11412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11413 op &= UINT64_C(3);
11414 Value |= op;
11415 break;
11416 }
11417 case Hexagon::V6_vaddcarrysat: {
11418 // op: Vu32
11419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11420 op &= UINT64_C(31);
11421 op <<= 8;
11422 Value |= op;
11423 // op: Vv32
11424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11425 op &= UINT64_C(31);
11426 op <<= 16;
11427 Value |= op;
11428 // op: Qs4
11429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11430 op &= UINT64_C(3);
11431 op <<= 5;
11432 Value |= op;
11433 // op: Vd32
11434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11435 op &= UINT64_C(31);
11436 Value |= op;
11437 break;
11438 }
11439 case Hexagon::V6_vabsdiffh:
11440 case Hexagon::V6_vabsdiffub:
11441 case Hexagon::V6_vabsdiffuh:
11442 case Hexagon::V6_vabsdiffw:
11443 case Hexagon::V6_vadd_hf:
11444 case Hexagon::V6_vadd_hf_hf:
11445 case Hexagon::V6_vadd_qf16:
11446 case Hexagon::V6_vadd_qf16_mix:
11447 case Hexagon::V6_vadd_qf32:
11448 case Hexagon::V6_vadd_qf32_mix:
11449 case Hexagon::V6_vadd_sf:
11450 case Hexagon::V6_vadd_sf_sf:
11451 case Hexagon::V6_vaddb:
11452 case Hexagon::V6_vaddbsat:
11453 case Hexagon::V6_vaddclbh:
11454 case Hexagon::V6_vaddclbw:
11455 case Hexagon::V6_vaddh:
11456 case Hexagon::V6_vaddhsat:
11457 case Hexagon::V6_vaddubsat:
11458 case Hexagon::V6_vaddububb_sat:
11459 case Hexagon::V6_vadduhsat:
11460 case Hexagon::V6_vadduwsat:
11461 case Hexagon::V6_vaddw:
11462 case Hexagon::V6_vaddwsat:
11463 case Hexagon::V6_vand:
11464 case Hexagon::V6_vaslhv:
11465 case Hexagon::V6_vaslwv:
11466 case Hexagon::V6_vasrhv:
11467 case Hexagon::V6_vasrwv:
11468 case Hexagon::V6_vavgb:
11469 case Hexagon::V6_vavgbrnd:
11470 case Hexagon::V6_vavgh:
11471 case Hexagon::V6_vavghrnd:
11472 case Hexagon::V6_vavgub:
11473 case Hexagon::V6_vavgubrnd:
11474 case Hexagon::V6_vavguh:
11475 case Hexagon::V6_vavguhrnd:
11476 case Hexagon::V6_vavguw:
11477 case Hexagon::V6_vavguwrnd:
11478 case Hexagon::V6_vavgw:
11479 case Hexagon::V6_vavgwrnd:
11480 case Hexagon::V6_vcvt2_b_hf:
11481 case Hexagon::V6_vcvt2_ub_hf:
11482 case Hexagon::V6_vcvt_b_hf:
11483 case Hexagon::V6_vcvt_bf_sf:
11484 case Hexagon::V6_vcvt_f8_hf:
11485 case Hexagon::V6_vcvt_hf_sf:
11486 case Hexagon::V6_vcvt_ub_hf:
11487 case Hexagon::V6_vdealb4w:
11488 case Hexagon::V6_vdelta:
11489 case Hexagon::V6_vdmpy_sf_hf:
11490 case Hexagon::V6_vdmpyhvsat:
11491 case Hexagon::V6_vfmax_f8:
11492 case Hexagon::V6_vfmax_hf:
11493 case Hexagon::V6_vfmax_sf:
11494 case Hexagon::V6_vfmin_f8:
11495 case Hexagon::V6_vfmin_hf:
11496 case Hexagon::V6_vfmin_sf:
11497 case Hexagon::V6_vlsrhv:
11498 case Hexagon::V6_vlsrwv:
11499 case Hexagon::V6_vmax_bf:
11500 case Hexagon::V6_vmax_hf:
11501 case Hexagon::V6_vmax_sf:
11502 case Hexagon::V6_vmaxb:
11503 case Hexagon::V6_vmaxh:
11504 case Hexagon::V6_vmaxub:
11505 case Hexagon::V6_vmaxuh:
11506 case Hexagon::V6_vmaxw:
11507 case Hexagon::V6_vmerge_qf:
11508 case Hexagon::V6_vmin_bf:
11509 case Hexagon::V6_vmin_hf:
11510 case Hexagon::V6_vmin_sf:
11511 case Hexagon::V6_vminb:
11512 case Hexagon::V6_vminh:
11513 case Hexagon::V6_vminub:
11514 case Hexagon::V6_vminuh:
11515 case Hexagon::V6_vminw:
11516 case Hexagon::V6_vmpy_hf_hf:
11517 case Hexagon::V6_vmpy_qf16:
11518 case Hexagon::V6_vmpy_qf16_hf:
11519 case Hexagon::V6_vmpy_qf16_mix_hf:
11520 case Hexagon::V6_vmpy_qf32:
11521 case Hexagon::V6_vmpy_qf32_sf:
11522 case Hexagon::V6_vmpy_sf_sf:
11523 case Hexagon::V6_vmpyewuh:
11524 case Hexagon::V6_vmpyhvsrs:
11525 case Hexagon::V6_vmpyieoh:
11526 case Hexagon::V6_vmpyiewuh:
11527 case Hexagon::V6_vmpyih:
11528 case Hexagon::V6_vmpyiowh:
11529 case Hexagon::V6_vmpyowh:
11530 case Hexagon::V6_vmpyowh_rnd:
11531 case Hexagon::V6_vmpyuhvs:
11532 case Hexagon::V6_vnavgb:
11533 case Hexagon::V6_vnavgh:
11534 case Hexagon::V6_vnavgub:
11535 case Hexagon::V6_vnavgw:
11536 case Hexagon::V6_vor:
11537 case Hexagon::V6_vpackeb:
11538 case Hexagon::V6_vpackeh:
11539 case Hexagon::V6_vpackhb_sat:
11540 case Hexagon::V6_vpackhub_sat:
11541 case Hexagon::V6_vpackob:
11542 case Hexagon::V6_vpackoh:
11543 case Hexagon::V6_vpackwh_sat:
11544 case Hexagon::V6_vpackwuh_sat:
11545 case Hexagon::V6_vrdelta:
11546 case Hexagon::V6_vrmpybusv:
11547 case Hexagon::V6_vrmpybv:
11548 case Hexagon::V6_vrmpyubv:
11549 case Hexagon::V6_vrotr:
11550 case Hexagon::V6_vroundhb:
11551 case Hexagon::V6_vroundhub:
11552 case Hexagon::V6_vrounduhub:
11553 case Hexagon::V6_vrounduwuh:
11554 case Hexagon::V6_vroundwh:
11555 case Hexagon::V6_vroundwuh:
11556 case Hexagon::V6_vsatdw:
11557 case Hexagon::V6_vsathub:
11558 case Hexagon::V6_vsatuwuh:
11559 case Hexagon::V6_vsatwh:
11560 case Hexagon::V6_vshufeh:
11561 case Hexagon::V6_vshuffeb:
11562 case Hexagon::V6_vshuffob:
11563 case Hexagon::V6_vshufoh:
11564 case Hexagon::V6_vsub_hf:
11565 case Hexagon::V6_vsub_hf_hf:
11566 case Hexagon::V6_vsub_qf16:
11567 case Hexagon::V6_vsub_qf16_mix:
11568 case Hexagon::V6_vsub_qf32:
11569 case Hexagon::V6_vsub_qf32_mix:
11570 case Hexagon::V6_vsub_sf:
11571 case Hexagon::V6_vsub_sf_sf:
11572 case Hexagon::V6_vsubb:
11573 case Hexagon::V6_vsubbsat:
11574 case Hexagon::V6_vsubh:
11575 case Hexagon::V6_vsubhsat:
11576 case Hexagon::V6_vsububsat:
11577 case Hexagon::V6_vsubububb_sat:
11578 case Hexagon::V6_vsubuhsat:
11579 case Hexagon::V6_vsubuwsat:
11580 case Hexagon::V6_vsubw:
11581 case Hexagon::V6_vsubwsat:
11582 case Hexagon::V6_vxor: {
11583 // op: Vu32
11584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11585 op &= UINT64_C(31);
11586 op <<= 8;
11587 Value |= op;
11588 // op: Vv32
11589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11590 op &= UINT64_C(31);
11591 op <<= 16;
11592 Value |= op;
11593 // op: Vd32
11594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11595 op &= UINT64_C(31);
11596 Value |= op;
11597 break;
11598 }
11599 case Hexagon::V6_vadd_hf_f8:
11600 case Hexagon::V6_vadd_sf_bf:
11601 case Hexagon::V6_vadd_sf_hf:
11602 case Hexagon::V6_vaddhw:
11603 case Hexagon::V6_vaddubh:
11604 case Hexagon::V6_vadduhw:
11605 case Hexagon::V6_vcombine:
11606 case Hexagon::V6_vcombine_tmp:
11607 case Hexagon::V6_vmpy_hf_f8:
11608 case Hexagon::V6_vmpy_qf32_hf:
11609 case Hexagon::V6_vmpy_qf32_mix_hf:
11610 case Hexagon::V6_vmpy_qf32_qf16:
11611 case Hexagon::V6_vmpy_sf_bf:
11612 case Hexagon::V6_vmpy_sf_hf:
11613 case Hexagon::V6_vmpybusv:
11614 case Hexagon::V6_vmpybv:
11615 case Hexagon::V6_vmpyewuh_64:
11616 case Hexagon::V6_vmpyhus:
11617 case Hexagon::V6_vmpyhv:
11618 case Hexagon::V6_vmpyubv:
11619 case Hexagon::V6_vmpyuhv:
11620 case Hexagon::V6_vshufoeb:
11621 case Hexagon::V6_vshufoeh:
11622 case Hexagon::V6_vsub_hf_f8:
11623 case Hexagon::V6_vsub_sf_bf:
11624 case Hexagon::V6_vsub_sf_hf:
11625 case Hexagon::V6_vsubhw:
11626 case Hexagon::V6_vsububh:
11627 case Hexagon::V6_vsubuhw: {
11628 // op: Vu32
11629 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11630 op &= UINT64_C(31);
11631 op <<= 8;
11632 Value |= op;
11633 // op: Vv32
11634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11635 op &= UINT64_C(31);
11636 op <<= 16;
11637 Value |= op;
11638 // op: Vdd32
11639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11640 op &= UINT64_C(31);
11641 Value |= op;
11642 break;
11643 }
11644 case Hexagon::V6_valignb:
11645 case Hexagon::V6_vasrhbrndsat:
11646 case Hexagon::V6_vasrhbsat:
11647 case Hexagon::V6_vasrhubrndsat:
11648 case Hexagon::V6_vasrhubsat:
11649 case Hexagon::V6_vasruhubrndsat:
11650 case Hexagon::V6_vasruhubsat:
11651 case Hexagon::V6_vasruwuhrndsat:
11652 case Hexagon::V6_vasruwuhsat:
11653 case Hexagon::V6_vasrwh:
11654 case Hexagon::V6_vasrwhrndsat:
11655 case Hexagon::V6_vasrwhsat:
11656 case Hexagon::V6_vasrwuhrndsat:
11657 case Hexagon::V6_vasrwuhsat:
11658 case Hexagon::V6_vlalignb:
11659 case Hexagon::V6_vlutvvb:
11660 case Hexagon::V6_vlutvvb_nm: {
11661 // op: Vu32
11662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11663 op &= UINT64_C(31);
11664 op <<= 8;
11665 Value |= op;
11666 // op: Vv32
11667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11668 op &= UINT64_C(31);
11669 op <<= 19;
11670 Value |= op;
11671 // op: Rt8
11672 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11673 op &= UINT64_C(7);
11674 op <<= 16;
11675 Value |= op;
11676 // op: Vd32
11677 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11678 op &= UINT64_C(31);
11679 Value |= op;
11680 break;
11681 }
11682 case Hexagon::V6_vdealvdd:
11683 case Hexagon::V6_vlutvwh:
11684 case Hexagon::V6_vlutvwh_nm:
11685 case Hexagon::V6_vshuffvdd: {
11686 // op: Vu32
11687 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11688 op &= UINT64_C(31);
11689 op <<= 8;
11690 Value |= op;
11691 // op: Vv32
11692 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11693 op &= UINT64_C(31);
11694 op <<= 19;
11695 Value |= op;
11696 // op: Rt8
11697 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11698 op &= UINT64_C(7);
11699 op <<= 16;
11700 Value |= op;
11701 // op: Vdd32
11702 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11703 op &= UINT64_C(31);
11704 Value |= op;
11705 break;
11706 }
11707 case Hexagon::V6_vandvrt_acc: {
11708 // op: Vu32
11709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11710 op &= UINT64_C(31);
11711 op <<= 8;
11712 Value |= op;
11713 // op: Rt32
11714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11715 op &= UINT64_C(31);
11716 op <<= 16;
11717 Value |= op;
11718 // op: Qx4
11719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11720 op &= UINT64_C(3);
11721 Value |= op;
11722 break;
11723 }
11724 case Hexagon::V6_get_qfext_oracc:
11725 case Hexagon::V6_vaslh_acc:
11726 case Hexagon::V6_vaslw_acc:
11727 case Hexagon::V6_vasrh_acc:
11728 case Hexagon::V6_vasrw_acc:
11729 case Hexagon::V6_vdmpybus_acc:
11730 case Hexagon::V6_vdmpyhb_acc:
11731 case Hexagon::V6_vdmpyhsat_acc:
11732 case Hexagon::V6_vdmpyhsusat_acc:
11733 case Hexagon::V6_vmpyihb_acc:
11734 case Hexagon::V6_vmpyiwb_acc:
11735 case Hexagon::V6_vmpyiwh_acc:
11736 case Hexagon::V6_vmpyiwub_acc:
11737 case Hexagon::V6_vmpyuhe_acc:
11738 case Hexagon::V6_vrmpybus_acc:
11739 case Hexagon::V6_vrmpyub_acc: {
11740 // op: Vu32
11741 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11742 op &= UINT64_C(31);
11743 op <<= 8;
11744 Value |= op;
11745 // op: Rt32
11746 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11747 op &= UINT64_C(31);
11748 op <<= 16;
11749 Value |= op;
11750 // op: Vx32
11751 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11752 op &= UINT64_C(31);
11753 Value |= op;
11754 break;
11755 }
11756 case Hexagon::V6_vmpybus_acc:
11757 case Hexagon::V6_vmpyh_acc:
11758 case Hexagon::V6_vmpyhsat_acc:
11759 case Hexagon::V6_vmpyub_acc:
11760 case Hexagon::V6_vmpyuh_acc: {
11761 // op: Vu32
11762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11763 op &= UINT64_C(31);
11764 op <<= 8;
11765 Value |= op;
11766 // op: Rt32
11767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11768 op &= UINT64_C(31);
11769 op <<= 16;
11770 Value |= op;
11771 // op: Vxx32
11772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11773 op &= UINT64_C(31);
11774 Value |= op;
11775 break;
11776 }
11777 case Hexagon::V6_vrmpyzbb_rt_acc:
11778 case Hexagon::V6_vrmpyzbub_rt_acc:
11779 case Hexagon::V6_vrmpyzcb_rt_acc:
11780 case Hexagon::V6_vrmpyzcbs_rt_acc:
11781 case Hexagon::V6_vrmpyznb_rt_acc: {
11782 // op: Vu32
11783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11784 op &= UINT64_C(31);
11785 op <<= 8;
11786 Value |= op;
11787 // op: Rt8
11788 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11789 op &= UINT64_C(7);
11790 op <<= 16;
11791 Value |= op;
11792 // op: Vyyyy32
11793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11794 op &= UINT64_C(31);
11795 Value |= op;
11796 break;
11797 }
11798 case Hexagon::V6_vmpahhsat:
11799 case Hexagon::V6_vmpauhuhsat:
11800 case Hexagon::V6_vmpsuhuhsat: {
11801 // op: Vu32
11802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11803 op &= UINT64_C(31);
11804 op <<= 8;
11805 Value |= op;
11806 // op: Rtt32
11807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11808 op &= UINT64_C(31);
11809 op <<= 16;
11810 Value |= op;
11811 // op: Vx32
11812 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11813 op &= UINT64_C(31);
11814 Value |= op;
11815 break;
11816 }
11817 case Hexagon::V6_vrmpybub_rtt_acc:
11818 case Hexagon::V6_vrmpyub_rtt_acc: {
11819 // op: Vu32
11820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11821 op &= UINT64_C(31);
11822 op <<= 8;
11823 Value |= op;
11824 // op: Rtt32
11825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11826 op &= UINT64_C(31);
11827 op <<= 16;
11828 Value |= op;
11829 // op: Vxx32
11830 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11831 op &= UINT64_C(31);
11832 Value |= op;
11833 break;
11834 }
11835 case Hexagon::V6_vrmpyzbb_rx:
11836 case Hexagon::V6_vrmpyzbub_rx:
11837 case Hexagon::V6_vrmpyzcb_rx:
11838 case Hexagon::V6_vrmpyzcbs_rx:
11839 case Hexagon::V6_vrmpyznb_rx: {
11840 // op: Vu32
11841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11842 op &= UINT64_C(31);
11843 op <<= 8;
11844 Value |= op;
11845 // op: Vdddd32
11846 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11847 op &= UINT64_C(31);
11848 Value |= op;
11849 // op: Rx8
11850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11851 op &= UINT64_C(7);
11852 op <<= 16;
11853 Value |= op;
11854 break;
11855 }
11856 case Hexagon::V6_veqb_and:
11857 case Hexagon::V6_veqb_or:
11858 case Hexagon::V6_veqb_xor:
11859 case Hexagon::V6_veqh_and:
11860 case Hexagon::V6_veqh_or:
11861 case Hexagon::V6_veqh_xor:
11862 case Hexagon::V6_veqw_and:
11863 case Hexagon::V6_veqw_or:
11864 case Hexagon::V6_veqw_xor:
11865 case Hexagon::V6_vgtb_and:
11866 case Hexagon::V6_vgtb_or:
11867 case Hexagon::V6_vgtb_xor:
11868 case Hexagon::V6_vgtbf_and:
11869 case Hexagon::V6_vgtbf_or:
11870 case Hexagon::V6_vgtbf_xor:
11871 case Hexagon::V6_vgth_and:
11872 case Hexagon::V6_vgth_or:
11873 case Hexagon::V6_vgth_xor:
11874 case Hexagon::V6_vgthf_and:
11875 case Hexagon::V6_vgthf_or:
11876 case Hexagon::V6_vgthf_xor:
11877 case Hexagon::V6_vgtsf_and:
11878 case Hexagon::V6_vgtsf_or:
11879 case Hexagon::V6_vgtsf_xor:
11880 case Hexagon::V6_vgtub_and:
11881 case Hexagon::V6_vgtub_or:
11882 case Hexagon::V6_vgtub_xor:
11883 case Hexagon::V6_vgtuh_and:
11884 case Hexagon::V6_vgtuh_or:
11885 case Hexagon::V6_vgtuh_xor:
11886 case Hexagon::V6_vgtuw_and:
11887 case Hexagon::V6_vgtuw_or:
11888 case Hexagon::V6_vgtuw_xor:
11889 case Hexagon::V6_vgtw_and:
11890 case Hexagon::V6_vgtw_or:
11891 case Hexagon::V6_vgtw_xor: {
11892 // op: Vu32
11893 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11894 op &= UINT64_C(31);
11895 op <<= 8;
11896 Value |= op;
11897 // op: Vv32
11898 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11899 op &= UINT64_C(31);
11900 op <<= 16;
11901 Value |= op;
11902 // op: Qx4
11903 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11904 op &= UINT64_C(3);
11905 Value |= op;
11906 break;
11907 }
11908 case Hexagon::V6_vaddcarryo:
11909 case Hexagon::V6_vsubcarryo: {
11910 // op: Vu32
11911 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11912 op &= UINT64_C(31);
11913 op <<= 8;
11914 Value |= op;
11915 // op: Vv32
11916 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11917 op &= UINT64_C(31);
11918 op <<= 16;
11919 Value |= op;
11920 // op: Vd32
11921 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11922 op &= UINT64_C(31);
11923 Value |= op;
11924 // op: Qe4
11925 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11926 op &= UINT64_C(3);
11927 op <<= 5;
11928 Value |= op;
11929 break;
11930 }
11931 case Hexagon::V6_vaddcarry:
11932 case Hexagon::V6_vsubcarry: {
11933 // op: Vu32
11934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11935 op &= UINT64_C(31);
11936 op <<= 8;
11937 Value |= op;
11938 // op: Vv32
11939 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11940 op &= UINT64_C(31);
11941 op <<= 16;
11942 Value |= op;
11943 // op: Vd32
11944 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11945 op &= UINT64_C(31);
11946 Value |= op;
11947 // op: Qx4
11948 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11949 op &= UINT64_C(3);
11950 op <<= 5;
11951 Value |= op;
11952 break;
11953 }
11954 case Hexagon::V6_vdmpy_sf_hf_acc:
11955 case Hexagon::V6_vdmpyhvsat_acc:
11956 case Hexagon::V6_vmpy_hf_hf_acc:
11957 case Hexagon::V6_vmpyiewh_acc:
11958 case Hexagon::V6_vmpyiewuh_acc:
11959 case Hexagon::V6_vmpyih_acc:
11960 case Hexagon::V6_vmpyowh_rnd_sacc:
11961 case Hexagon::V6_vmpyowh_sacc:
11962 case Hexagon::V6_vrmpybusv_acc:
11963 case Hexagon::V6_vrmpybv_acc:
11964 case Hexagon::V6_vrmpyubv_acc: {
11965 // op: Vu32
11966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11967 op &= UINT64_C(31);
11968 op <<= 8;
11969 Value |= op;
11970 // op: Vv32
11971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11972 op &= UINT64_C(31);
11973 op <<= 16;
11974 Value |= op;
11975 // op: Vx32
11976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11977 op &= UINT64_C(31);
11978 Value |= op;
11979 break;
11980 }
11981 case Hexagon::V6_vaddhw_acc:
11982 case Hexagon::V6_vaddubh_acc:
11983 case Hexagon::V6_vadduhw_acc:
11984 case Hexagon::V6_vasr_into:
11985 case Hexagon::V6_vmpy_hf_f8_acc:
11986 case Hexagon::V6_vmpy_sf_bf_acc:
11987 case Hexagon::V6_vmpy_sf_hf_acc:
11988 case Hexagon::V6_vmpybusv_acc:
11989 case Hexagon::V6_vmpybv_acc:
11990 case Hexagon::V6_vmpyhus_acc:
11991 case Hexagon::V6_vmpyhv_acc:
11992 case Hexagon::V6_vmpyowh_64_acc:
11993 case Hexagon::V6_vmpyubv_acc:
11994 case Hexagon::V6_vmpyuhv_acc: {
11995 // op: Vu32
11996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11997 op &= UINT64_C(31);
11998 op <<= 8;
11999 Value |= op;
12000 // op: Vv32
12001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12002 op &= UINT64_C(31);
12003 op <<= 16;
12004 Value |= op;
12005 // op: Vxx32
12006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12007 op &= UINT64_C(31);
12008 Value |= op;
12009 break;
12010 }
12011 case Hexagon::V6_vlutvvb_oracc: {
12012 // op: Vu32
12013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12014 op &= UINT64_C(31);
12015 op <<= 8;
12016 Value |= op;
12017 // op: Vv32
12018 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12019 op &= UINT64_C(31);
12020 op <<= 19;
12021 Value |= op;
12022 // op: Rt8
12023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12024 op &= UINT64_C(7);
12025 op <<= 16;
12026 Value |= op;
12027 // op: Vx32
12028 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12029 op &= UINT64_C(31);
12030 Value |= op;
12031 break;
12032 }
12033 case Hexagon::V6_vlutvwh_oracc: {
12034 // op: Vu32
12035 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12036 op &= UINT64_C(31);
12037 op <<= 8;
12038 Value |= op;
12039 // op: Vv32
12040 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12041 op &= UINT64_C(31);
12042 op <<= 19;
12043 Value |= op;
12044 // op: Rt8
12045 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
12046 op &= UINT64_C(7);
12047 op <<= 16;
12048 Value |= op;
12049 // op: Vxx32
12050 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12051 op &= UINT64_C(31);
12052 Value |= op;
12053 break;
12054 }
12055 case Hexagon::V6_vunpackob:
12056 case Hexagon::V6_vunpackoh: {
12057 // op: Vu32
12058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12059 op &= UINT64_C(31);
12060 op <<= 8;
12061 Value |= op;
12062 // op: Vxx32
12063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12064 op &= UINT64_C(31);
12065 Value |= op;
12066 break;
12067 }
12068 case Hexagon::V6_vrmpyzbb_rx_acc:
12069 case Hexagon::V6_vrmpyzbub_rx_acc:
12070 case Hexagon::V6_vrmpyzcb_rx_acc:
12071 case Hexagon::V6_vrmpyzcbs_rx_acc:
12072 case Hexagon::V6_vrmpyznb_rx_acc: {
12073 // op: Vu32
12074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12075 op &= UINT64_C(31);
12076 op <<= 8;
12077 Value |= op;
12078 // op: Vyyyy32
12079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12080 op &= UINT64_C(31);
12081 Value |= op;
12082 // op: Rx8
12083 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12084 op &= UINT64_C(7);
12085 op <<= 16;
12086 Value |= op;
12087 break;
12088 }
12089 case Hexagon::V6_vdmpyhisat:
12090 case Hexagon::V6_vdmpyhsuisat: {
12091 // op: Vuu32
12092 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12093 op &= UINT64_C(31);
12094 op <<= 8;
12095 Value |= op;
12096 // op: Rt32
12097 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12098 op &= UINT64_C(31);
12099 op <<= 16;
12100 Value |= op;
12101 // op: Vd32
12102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12103 op &= UINT64_C(31);
12104 Value |= op;
12105 break;
12106 }
12107 case Hexagon::V6_vdmpybus_dv:
12108 case Hexagon::V6_vdmpyhb_dv:
12109 case Hexagon::V6_vdsaduh:
12110 case Hexagon::V6_vmpabus:
12111 case Hexagon::V6_vmpabuu:
12112 case Hexagon::V6_vmpahb:
12113 case Hexagon::V6_vmpauhb:
12114 case Hexagon::V6_vtmpyb:
12115 case Hexagon::V6_vtmpybus:
12116 case Hexagon::V6_vtmpyhb: {
12117 // op: Vuu32
12118 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12119 op &= UINT64_C(31);
12120 op <<= 8;
12121 Value |= op;
12122 // op: Rt32
12123 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12124 op &= UINT64_C(31);
12125 op <<= 16;
12126 Value |= op;
12127 // op: Vdd32
12128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12129 op &= UINT64_C(31);
12130 Value |= op;
12131 break;
12132 }
12133 case Hexagon::V6_vconv_hf_qf32: {
12134 // op: Vuu32
12135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12136 op &= UINT64_C(31);
12137 op <<= 8;
12138 Value |= op;
12139 // op: Vd32
12140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12141 op &= UINT64_C(31);
12142 Value |= op;
12143 break;
12144 }
12145 case Hexagon::V6_vasrvuhubrndsat:
12146 case Hexagon::V6_vasrvuhubsat:
12147 case Hexagon::V6_vasrvwuhrndsat:
12148 case Hexagon::V6_vasrvwuhsat: {
12149 // op: Vuu32
12150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12151 op &= UINT64_C(31);
12152 op <<= 8;
12153 Value |= op;
12154 // op: Vv32
12155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12156 op &= UINT64_C(31);
12157 op <<= 16;
12158 Value |= op;
12159 // op: Vd32
12160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12161 op &= UINT64_C(31);
12162 Value |= op;
12163 break;
12164 }
12165 case Hexagon::V6_vaddb_dv:
12166 case Hexagon::V6_vaddbsat_dv:
12167 case Hexagon::V6_vaddh_dv:
12168 case Hexagon::V6_vaddhsat_dv:
12169 case Hexagon::V6_vaddubsat_dv:
12170 case Hexagon::V6_vadduhsat_dv:
12171 case Hexagon::V6_vadduwsat_dv:
12172 case Hexagon::V6_vaddw_dv:
12173 case Hexagon::V6_vaddwsat_dv:
12174 case Hexagon::V6_vmpabusv:
12175 case Hexagon::V6_vmpabuuv:
12176 case Hexagon::V6_vsubb_dv:
12177 case Hexagon::V6_vsubbsat_dv:
12178 case Hexagon::V6_vsubh_dv:
12179 case Hexagon::V6_vsubhsat_dv:
12180 case Hexagon::V6_vsububsat_dv:
12181 case Hexagon::V6_vsubuhsat_dv:
12182 case Hexagon::V6_vsubuwsat_dv:
12183 case Hexagon::V6_vsubw_dv:
12184 case Hexagon::V6_vsubwsat_dv: {
12185 // op: Vuu32
12186 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12187 op &= UINT64_C(31);
12188 op <<= 8;
12189 Value |= op;
12190 // op: Vvv32
12191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12192 op &= UINT64_C(31);
12193 op <<= 16;
12194 Value |= op;
12195 // op: Vdd32
12196 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12197 op &= UINT64_C(31);
12198 Value |= op;
12199 break;
12200 }
12201 case Hexagon::V6_vdmpyhisat_acc:
12202 case Hexagon::V6_vdmpyhsuisat_acc: {
12203 // op: Vuu32
12204 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12205 op &= UINT64_C(31);
12206 op <<= 8;
12207 Value |= op;
12208 // op: Rt32
12209 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12210 op &= UINT64_C(31);
12211 op <<= 16;
12212 Value |= op;
12213 // op: Vx32
12214 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12215 op &= UINT64_C(31);
12216 Value |= op;
12217 break;
12218 }
12219 case Hexagon::V6_vdmpybus_dv_acc:
12220 case Hexagon::V6_vdmpyhb_dv_acc:
12221 case Hexagon::V6_vdsaduh_acc:
12222 case Hexagon::V6_vmpabus_acc:
12223 case Hexagon::V6_vmpabuu_acc:
12224 case Hexagon::V6_vmpahb_acc:
12225 case Hexagon::V6_vmpauhb_acc:
12226 case Hexagon::V6_vtmpyb_acc:
12227 case Hexagon::V6_vtmpybus_acc:
12228 case Hexagon::V6_vtmpyhb_acc: {
12229 // op: Vuu32
12230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12231 op &= UINT64_C(31);
12232 op <<= 8;
12233 Value |= op;
12234 // op: Rt32
12235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12236 op &= UINT64_C(31);
12237 op <<= 16;
12238 Value |= op;
12239 // op: Vxx32
12240 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12241 op &= UINT64_C(31);
12242 Value |= op;
12243 break;
12244 }
12245 case Hexagon::CALLProfile:
12246 case Hexagon::PS_call_stk:
12247 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
12248 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
12249 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
12250 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
12251 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
12252 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
12253 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
12254 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
12255 case Hexagon::SAVE_REGISTERS_CALL_V4:
12256 case Hexagon::SAVE_REGISTERS_CALL_V4STK:
12257 case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT:
12258 case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC:
12259 case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC:
12260 case Hexagon::SAVE_REGISTERS_CALL_V4_EXT:
12261 case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC:
12262 case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: {
12263 // op: dst
12264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12265 Value |= (op & UINT64_C(16744448)) << 1;
12266 Value |= (op & UINT64_C(32764)) >> 1;
12267 break;
12268 }
12269 case Hexagon::EH_RETURN_JMPR:
12270 case Hexagon::PS_jmpret: {
12271 // op: dst
12272 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12273 op &= UINT64_C(31);
12274 op <<= 16;
12275 Value |= op;
12276 break;
12277 }
12278 case Hexagon::HI:
12279 case Hexagon::LO: {
12280 // op: dst
12281 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12282 op &= UINT64_C(31);
12283 op <<= 16;
12284 Value |= op;
12285 // op: imm_value
12286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12287 Value |= (op & UINT64_C(49152)) << 8;
12288 Value |= (op & UINT64_C(16383));
12289 break;
12290 }
12291 case Hexagon::J2_loop0iext:
12292 case Hexagon::J2_loop1iext: {
12293 // op: offset
12294 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12295 Value |= (op & UINT64_C(496)) << 4;
12296 Value |= (op & UINT64_C(12)) << 1;
12297 // op: src2
12298 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12299 Value |= (op & UINT64_C(992)) << 11;
12300 Value |= (op & UINT64_C(28)) << 3;
12301 Value |= (op & UINT64_C(3));
12302 break;
12303 }
12304 case Hexagon::J2_loop0rext:
12305 case Hexagon::J2_loop1rext: {
12306 // op: offset
12307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12308 Value |= (op & UINT64_C(496)) << 4;
12309 Value |= (op & UINT64_C(12)) << 1;
12310 // op: src2
12311 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12312 op &= UINT64_C(31);
12313 op <<= 16;
12314 Value |= op;
12315 break;
12316 }
12317 case Hexagon::PS_jmpretf:
12318 case Hexagon::PS_jmpretfnew:
12319 case Hexagon::PS_jmpretfnewpt:
12320 case Hexagon::PS_jmprett:
12321 case Hexagon::PS_jmprettnew:
12322 case Hexagon::PS_jmprettnewpt: {
12323 // op: src
12324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12325 op &= UINT64_C(3);
12326 op <<= 8;
12327 Value |= op;
12328 // op: dst
12329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12330 op &= UINT64_C(31);
12331 op <<= 16;
12332 Value |= op;
12333 break;
12334 }
12335 default:
12336 std::string msg;
12337 raw_string_ostream Msg(msg);
12338 Msg << "Not supported instr: " << MI;
12339 report_fatal_error(reason: Msg.str().c_str());
12340 }
12341 return Value;
12342}
12343
12344#ifdef GET_OPERAND_BIT_OFFSET
12345#undef GET_OPERAND_BIT_OFFSET
12346
12347uint32_t HexagonMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
12348 unsigned OpNum,
12349 const MCSubtargetInfo &STI) const {
12350 switch (MI.getOpcode()) {
12351 case Hexagon::A2_nop:
12352 case Hexagon::CONST32:
12353 case Hexagon::CONST64:
12354 case Hexagon::DuplexIClass0:
12355 case Hexagon::DuplexIClass1:
12356 case Hexagon::DuplexIClass2:
12357 case Hexagon::DuplexIClass3:
12358 case Hexagon::DuplexIClass4:
12359 case Hexagon::DuplexIClass5:
12360 case Hexagon::DuplexIClass6:
12361 case Hexagon::DuplexIClass7:
12362 case Hexagon::DuplexIClass8:
12363 case Hexagon::DuplexIClass9:
12364 case Hexagon::DuplexIClassA:
12365 case Hexagon::DuplexIClassB:
12366 case Hexagon::DuplexIClassC:
12367 case Hexagon::DuplexIClassD:
12368 case Hexagon::DuplexIClassE:
12369 case Hexagon::DuplexIClassF:
12370 case Hexagon::J2_rte:
12371 case Hexagon::J2_unpause:
12372 case Hexagon::SL2_deallocframe:
12373 case Hexagon::SL2_jumpr31:
12374 case Hexagon::SL2_jumpr31_f:
12375 case Hexagon::SL2_jumpr31_fnew:
12376 case Hexagon::SL2_jumpr31_t:
12377 case Hexagon::SL2_jumpr31_tnew:
12378 case Hexagon::SL2_return:
12379 case Hexagon::SL2_return_f:
12380 case Hexagon::SL2_return_fnew:
12381 case Hexagon::SL2_return_t:
12382 case Hexagon::SL2_return_tnew:
12383 case Hexagon::TFRI64_V2_ext:
12384 case Hexagon::TFRI64_V4:
12385 case Hexagon::V6_vhist:
12386 case Hexagon::V6_vwhist128:
12387 case Hexagon::V6_vwhist256:
12388 case Hexagon::V6_vwhist256_sat:
12389 case Hexagon::Y2_barrier:
12390 case Hexagon::Y2_break:
12391 case Hexagon::Y2_dckill:
12392 case Hexagon::Y2_ickill:
12393 case Hexagon::Y2_isync:
12394 case Hexagon::Y2_k0lock:
12395 case Hexagon::Y2_k0unlock:
12396 case Hexagon::Y2_l2kill:
12397 case Hexagon::Y2_syncht:
12398 case Hexagon::Y2_tlblock:
12399 case Hexagon::Y2_tlbunlock:
12400 case Hexagon::Y5_l2gclean:
12401 case Hexagon::Y5_l2gcleaninv:
12402 case Hexagon::Y5_l2gunlock:
12403 case Hexagon::invalid_decode: {
12404 break;
12405 }
12406 case Hexagon::PS_storerbnewabs:
12407 case Hexagon::PS_storerhnewabs:
12408 case Hexagon::PS_storerinewabs:
12409 case Hexagon::S2_storerbnewgp:
12410 case Hexagon::S2_storerhnewgp:
12411 case Hexagon::S2_storerinewgp: {
12412 switch (OpNum) {
12413 case 0:
12414 // op: Ii
12415 return 0;
12416 case 1:
12417 // op: Nt8
12418 return 8;
12419 }
12420 break;
12421 }
12422 case Hexagon::PS_storerbabs:
12423 case Hexagon::PS_storerfabs:
12424 case Hexagon::PS_storerhabs:
12425 case Hexagon::PS_storeriabs:
12426 case Hexagon::S2_storerbgp:
12427 case Hexagon::S2_storerfgp:
12428 case Hexagon::S2_storerhgp:
12429 case Hexagon::S2_storerigp: {
12430 switch (OpNum) {
12431 case 0:
12432 // op: Ii
12433 return 0;
12434 case 1:
12435 // op: Rt32
12436 return 8;
12437 }
12438 break;
12439 }
12440 case Hexagon::PS_storerdabs:
12441 case Hexagon::S2_storerdgp: {
12442 switch (OpNum) {
12443 case 0:
12444 // op: Ii
12445 return 0;
12446 case 1:
12447 // op: Rtt32
12448 return 8;
12449 }
12450 break;
12451 }
12452 case Hexagon::A4_ext: {
12453 switch (OpNum) {
12454 case 0:
12455 // op: Ii
12456 return 0;
12457 }
12458 break;
12459 }
12460 case Hexagon::J2_call:
12461 case Hexagon::J2_jump: {
12462 switch (OpNum) {
12463 case 0:
12464 // op: Ii
12465 return 1;
12466 }
12467 break;
12468 }
12469 case Hexagon::J2_pause:
12470 case Hexagon::J2_trap0:
12471 case Hexagon::PS_trap1: {
12472 switch (OpNum) {
12473 case 0:
12474 // op: Ii
12475 return 2;
12476 }
12477 break;
12478 }
12479 case Hexagon::J2_loop0i:
12480 case Hexagon::J2_loop1i:
12481 case Hexagon::J2_ploop1si:
12482 case Hexagon::J2_ploop2si:
12483 case Hexagon::J2_ploop3si: {
12484 switch (OpNum) {
12485 case 0:
12486 // op: Ii
12487 return 3;
12488 case 1:
12489 // op: II
12490 return 0;
12491 }
12492 break;
12493 }
12494 case Hexagon::J2_loop0r:
12495 case Hexagon::J2_loop1r:
12496 case Hexagon::J2_ploop1sr:
12497 case Hexagon::J2_ploop2sr:
12498 case Hexagon::J2_ploop3sr: {
12499 switch (OpNum) {
12500 case 0:
12501 // op: Ii
12502 return 3;
12503 case 1:
12504 // op: Rs32
12505 return 16;
12506 }
12507 break;
12508 }
12509 case Hexagon::SS2_stored_sp: {
12510 switch (OpNum) {
12511 case 0:
12512 // op: Ii
12513 return 3;
12514 case 1:
12515 // op: Rtt8
12516 return 0;
12517 }
12518 break;
12519 }
12520 case Hexagon::SS2_storew_sp: {
12521 switch (OpNum) {
12522 case 0:
12523 // op: Ii
12524 return 4;
12525 case 1:
12526 // op: Rt16
12527 return 0;
12528 }
12529 break;
12530 }
12531 case Hexagon::SS2_allocframe: {
12532 switch (OpNum) {
12533 case 0:
12534 // op: Ii
12535 return 4;
12536 }
12537 break;
12538 }
12539 case Hexagon::V6_vwhist128m: {
12540 switch (OpNum) {
12541 case 0:
12542 // op: Ii
12543 return 8;
12544 }
12545 break;
12546 }
12547 case Hexagon::Y2_setimask:
12548 case Hexagon::Y2_setprio: {
12549 switch (OpNum) {
12550 case 0:
12551 // op: Pt4
12552 return 8;
12553 case 1:
12554 // op: Rs32
12555 return 16;
12556 }
12557 break;
12558 }
12559 case Hexagon::J2_callrf:
12560 case Hexagon::J2_callrt:
12561 case Hexagon::J2_jumprf:
12562 case Hexagon::J2_jumprfnew:
12563 case Hexagon::J2_jumprfnewpt:
12564 case Hexagon::J2_jumprfpt:
12565 case Hexagon::J2_jumprt:
12566 case Hexagon::J2_jumprtnew:
12567 case Hexagon::J2_jumprtnewpt:
12568 case Hexagon::J2_jumprtpt: {
12569 switch (OpNum) {
12570 case 0:
12571 // op: Pu4
12572 return 8;
12573 case 1:
12574 // op: Rs32
12575 return 16;
12576 }
12577 break;
12578 }
12579 case Hexagon::V6_vgathermhq:
12580 case Hexagon::V6_vgathermwq: {
12581 switch (OpNum) {
12582 case 0:
12583 // op: Qs4
12584 return 5;
12585 case 1:
12586 // op: Rt32
12587 return 16;
12588 case 2:
12589 // op: Mu2
12590 return 13;
12591 case 3:
12592 // op: Vv32
12593 return 0;
12594 }
12595 break;
12596 }
12597 case Hexagon::V6_vscattermhq:
12598 case Hexagon::V6_vscattermwq: {
12599 switch (OpNum) {
12600 case 0:
12601 // op: Qs4
12602 return 5;
12603 case 1:
12604 // op: Rt32
12605 return 16;
12606 case 2:
12607 // op: Mu2
12608 return 13;
12609 case 3:
12610 // op: Vv32
12611 return 8;
12612 case 4:
12613 // op: Vw32
12614 return 0;
12615 }
12616 break;
12617 }
12618 case Hexagon::V6_vgathermhwq: {
12619 switch (OpNum) {
12620 case 0:
12621 // op: Qs4
12622 return 5;
12623 case 1:
12624 // op: Rt32
12625 return 16;
12626 case 2:
12627 // op: Mu2
12628 return 13;
12629 case 3:
12630 // op: Vvv32
12631 return 0;
12632 }
12633 break;
12634 }
12635 case Hexagon::V6_vscattermhwq: {
12636 switch (OpNum) {
12637 case 0:
12638 // op: Qs4
12639 return 5;
12640 case 1:
12641 // op: Rt32
12642 return 16;
12643 case 2:
12644 // op: Mu2
12645 return 13;
12646 case 3:
12647 // op: Vvv32
12648 return 8;
12649 case 4:
12650 // op: Vw32
12651 return 0;
12652 }
12653 break;
12654 }
12655 case Hexagon::V6_vhistq:
12656 case Hexagon::V6_vwhist128q:
12657 case Hexagon::V6_vwhist256q:
12658 case Hexagon::V6_vwhist256q_sat: {
12659 switch (OpNum) {
12660 case 0:
12661 // op: Qv4
12662 return 22;
12663 }
12664 break;
12665 }
12666 case Hexagon::SA1_clrf:
12667 case Hexagon::SA1_clrfnew:
12668 case Hexagon::SA1_clrt:
12669 case Hexagon::SA1_clrtnew:
12670 case Hexagon::SA1_setin1: {
12671 switch (OpNum) {
12672 case 0:
12673 // op: Rd16
12674 return 0;
12675 }
12676 break;
12677 }
12678 case Hexagon::Y6_dmpause:
12679 case Hexagon::Y6_dmpoll:
12680 case Hexagon::Y6_dmwait: {
12681 switch (OpNum) {
12682 case 0:
12683 // op: Rd32
12684 return 0;
12685 }
12686 break;
12687 }
12688 case Hexagon::PS_callr_nr: {
12689 switch (OpNum) {
12690 case 0:
12691 // op: Rs
12692 return 16;
12693 }
12694 break;
12695 }
12696 case Hexagon::L6_memcpy: {
12697 switch (OpNum) {
12698 case 0:
12699 // op: Rs32
12700 return 16;
12701 case 1:
12702 // op: Rt32
12703 return 8;
12704 case 2:
12705 // op: Mu2
12706 return 13;
12707 }
12708 break;
12709 }
12710 case Hexagon::S2_storew_rl_at_vi:
12711 case Hexagon::S2_storew_rl_st_vi:
12712 case Hexagon::Y2_dctagw:
12713 case Hexagon::Y2_icdataw:
12714 case Hexagon::Y2_ictagw:
12715 case Hexagon::Y4_l2fetch:
12716 case Hexagon::Y4_l2tagw:
12717 case Hexagon::Y6_dmlink: {
12718 switch (OpNum) {
12719 case 0:
12720 // op: Rs32
12721 return 16;
12722 case 1:
12723 // op: Rt32
12724 return 8;
12725 }
12726 break;
12727 }
12728 case Hexagon::S4_stored_rl_at_vi:
12729 case Hexagon::S4_stored_rl_st_vi:
12730 case Hexagon::Y5_l2fetch: {
12731 switch (OpNum) {
12732 case 0:
12733 // op: Rs32
12734 return 16;
12735 case 1:
12736 // op: Rtt32
12737 return 8;
12738 }
12739 break;
12740 }
12741 case Hexagon::J2_callr:
12742 case Hexagon::J2_callrh:
12743 case Hexagon::J2_jumpr:
12744 case Hexagon::J2_jumprh:
12745 case Hexagon::J4_hintjumpr:
12746 case Hexagon::R6_release_at_vi:
12747 case Hexagon::R6_release_st_vi:
12748 case Hexagon::Y2_ciad:
12749 case Hexagon::Y2_cswi:
12750 case Hexagon::Y2_dccleana:
12751 case Hexagon::Y2_dccleanidx:
12752 case Hexagon::Y2_dccleaninva:
12753 case Hexagon::Y2_dccleaninvidx:
12754 case Hexagon::Y2_dcinva:
12755 case Hexagon::Y2_dcinvidx:
12756 case Hexagon::Y2_dczeroa:
12757 case Hexagon::Y2_iassignw:
12758 case Hexagon::Y2_icinva:
12759 case Hexagon::Y2_icinvidx:
12760 case Hexagon::Y2_l2cleaninvidx:
12761 case Hexagon::Y2_resume:
12762 case Hexagon::Y2_start:
12763 case Hexagon::Y2_stop:
12764 case Hexagon::Y2_swi:
12765 case Hexagon::Y2_wait:
12766 case Hexagon::Y4_nmi:
12767 case Hexagon::Y4_siad:
12768 case Hexagon::Y4_trace:
12769 case Hexagon::Y5_l2cleanidx:
12770 case Hexagon::Y5_l2invidx:
12771 case Hexagon::Y5_l2unlocka:
12772 case Hexagon::Y5_tlbasidi:
12773 case Hexagon::Y6_diag:
12774 case Hexagon::Y6_dmresume:
12775 case Hexagon::Y6_dmstart: {
12776 switch (OpNum) {
12777 case 0:
12778 // op: Rs32
12779 return 16;
12780 }
12781 break;
12782 }
12783 case Hexagon::Y2_tlbw: {
12784 switch (OpNum) {
12785 case 0:
12786 // op: Rss32
12787 return 16;
12788 case 1:
12789 // op: Rt32
12790 return 8;
12791 }
12792 break;
12793 }
12794 case Hexagon::Y6_diag0:
12795 case Hexagon::Y6_diag1: {
12796 switch (OpNum) {
12797 case 0:
12798 // op: Rss32
12799 return 16;
12800 case 1:
12801 // op: Rtt32
12802 return 8;
12803 }
12804 break;
12805 }
12806 case Hexagon::V6_vgathermh:
12807 case Hexagon::V6_vgathermw: {
12808 switch (OpNum) {
12809 case 0:
12810 // op: Rt32
12811 return 16;
12812 case 1:
12813 // op: Mu2
12814 return 13;
12815 case 2:
12816 // op: Vv32
12817 return 0;
12818 }
12819 break;
12820 }
12821 case Hexagon::V6_vscattermh:
12822 case Hexagon::V6_vscattermh_add:
12823 case Hexagon::V6_vscattermw:
12824 case Hexagon::V6_vscattermw_add: {
12825 switch (OpNum) {
12826 case 0:
12827 // op: Rt32
12828 return 16;
12829 case 1:
12830 // op: Mu2
12831 return 13;
12832 case 2:
12833 // op: Vv32
12834 return 8;
12835 case 3:
12836 // op: Vw32
12837 return 0;
12838 }
12839 break;
12840 }
12841 case Hexagon::V6_vgathermhw: {
12842 switch (OpNum) {
12843 case 0:
12844 // op: Rt32
12845 return 16;
12846 case 1:
12847 // op: Mu2
12848 return 13;
12849 case 2:
12850 // op: Vvv32
12851 return 0;
12852 }
12853 break;
12854 }
12855 case Hexagon::V6_vscattermhw:
12856 case Hexagon::V6_vscattermhw_add: {
12857 switch (OpNum) {
12858 case 0:
12859 // op: Rt32
12860 return 16;
12861 case 1:
12862 // op: Mu2
12863 return 13;
12864 case 2:
12865 // op: Vvv32
12866 return 8;
12867 case 3:
12868 // op: Vw32
12869 return 0;
12870 }
12871 break;
12872 }
12873 case Hexagon::Y6_l2gcleaninvpa:
12874 case Hexagon::Y6_l2gcleanpa: {
12875 switch (OpNum) {
12876 case 0:
12877 // op: Rtt32
12878 return 8;
12879 }
12880 break;
12881 }
12882 case Hexagon::Y2_crswap0:
12883 case Hexagon::Y4_crswap1: {
12884 switch (OpNum) {
12885 case 0:
12886 // op: Rx32
12887 return 16;
12888 }
12889 break;
12890 }
12891 case Hexagon::Y4_crswap10: {
12892 switch (OpNum) {
12893 case 0:
12894 // op: Rxx32
12895 return 16;
12896 }
12897 break;
12898 }
12899 case Hexagon::HI:
12900 case Hexagon::LO: {
12901 switch (OpNum) {
12902 case 0:
12903 // op: dst
12904 return 16;
12905 case 1:
12906 // op: imm_value
12907 return 0;
12908 }
12909 break;
12910 }
12911 case Hexagon::EH_RETURN_JMPR:
12912 case Hexagon::PS_jmpret: {
12913 switch (OpNum) {
12914 case 0:
12915 // op: dst
12916 return 16;
12917 }
12918 break;
12919 }
12920 case Hexagon::CALLProfile:
12921 case Hexagon::PS_call_stk:
12922 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
12923 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
12924 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
12925 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
12926 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
12927 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
12928 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
12929 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
12930 case Hexagon::SAVE_REGISTERS_CALL_V4:
12931 case Hexagon::SAVE_REGISTERS_CALL_V4STK:
12932 case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT:
12933 case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC:
12934 case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC:
12935 case Hexagon::SAVE_REGISTERS_CALL_V4_EXT:
12936 case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC:
12937 case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: {
12938 switch (OpNum) {
12939 case 0:
12940 // op: dst
12941 return 1;
12942 }
12943 break;
12944 }
12945 case Hexagon::J2_loop0iext:
12946 case Hexagon::J2_loop1iext: {
12947 switch (OpNum) {
12948 case 0:
12949 // op: offset
12950 return 3;
12951 case 1:
12952 // op: src2
12953 return 0;
12954 }
12955 break;
12956 }
12957 case Hexagon::J2_loop0rext:
12958 case Hexagon::J2_loop1rext: {
12959 switch (OpNum) {
12960 case 0:
12961 // op: offset
12962 return 3;
12963 case 1:
12964 // op: src2
12965 return 16;
12966 }
12967 break;
12968 }
12969 case Hexagon::PS_jmpretf:
12970 case Hexagon::PS_jmpretfnew:
12971 case Hexagon::PS_jmpretfnewpt:
12972 case Hexagon::PS_jmprett:
12973 case Hexagon::PS_jmprettnew:
12974 case Hexagon::PS_jmprettnewpt: {
12975 switch (OpNum) {
12976 case 0:
12977 // op: src
12978 return 8;
12979 case 1:
12980 // op: dst
12981 return 16;
12982 }
12983 break;
12984 }
12985 case Hexagon::A2_tfrcrr: {
12986 switch (OpNum) {
12987 case 1:
12988 // op: Cs32
12989 return 16;
12990 case 0:
12991 // op: Rd32
12992 return 0;
12993 }
12994 break;
12995 }
12996 case Hexagon::A4_tfrcpp: {
12997 switch (OpNum) {
12998 case 1:
12999 // op: Css32
13000 return 16;
13001 case 0:
13002 // op: Rdd32
13003 return 0;
13004 }
13005 break;
13006 }
13007 case Hexagon::G4_tfrgcrr: {
13008 switch (OpNum) {
13009 case 1:
13010 // op: Gs32
13011 return 16;
13012 case 0:
13013 // op: Rd32
13014 return 0;
13015 }
13016 break;
13017 }
13018 case Hexagon::G4_tfrgcpp: {
13019 switch (OpNum) {
13020 case 1:
13021 // op: Gss32
13022 return 16;
13023 case 0:
13024 // op: Rdd32
13025 return 0;
13026 }
13027 break;
13028 }
13029 case Hexagon::S4_storerbnew_ap:
13030 case Hexagon::S4_storerhnew_ap:
13031 case Hexagon::S4_storerinew_ap: {
13032 switch (OpNum) {
13033 case 1:
13034 // op: II
13035 return 0;
13036 case 2:
13037 // op: Nt8
13038 return 8;
13039 case 0:
13040 // op: Re32
13041 return 16;
13042 }
13043 break;
13044 }
13045 case Hexagon::S4_storerb_ap:
13046 case Hexagon::S4_storerf_ap:
13047 case Hexagon::S4_storerh_ap:
13048 case Hexagon::S4_storeri_ap: {
13049 switch (OpNum) {
13050 case 1:
13051 // op: II
13052 return 0;
13053 case 2:
13054 // op: Rt32
13055 return 8;
13056 case 0:
13057 // op: Re32
13058 return 16;
13059 }
13060 break;
13061 }
13062 case Hexagon::S4_storerd_ap: {
13063 switch (OpNum) {
13064 case 1:
13065 // op: II
13066 return 0;
13067 case 2:
13068 // op: Rtt32
13069 return 8;
13070 case 0:
13071 // op: Re32
13072 return 16;
13073 }
13074 break;
13075 }
13076 case Hexagon::J4_cmpeqi_f_jumpnv_nt:
13077 case Hexagon::J4_cmpeqi_f_jumpnv_t:
13078 case Hexagon::J4_cmpeqi_t_jumpnv_nt:
13079 case Hexagon::J4_cmpeqi_t_jumpnv_t:
13080 case Hexagon::J4_cmpgti_f_jumpnv_nt:
13081 case Hexagon::J4_cmpgti_f_jumpnv_t:
13082 case Hexagon::J4_cmpgti_t_jumpnv_nt:
13083 case Hexagon::J4_cmpgti_t_jumpnv_t:
13084 case Hexagon::J4_cmpgtui_f_jumpnv_nt:
13085 case Hexagon::J4_cmpgtui_f_jumpnv_t:
13086 case Hexagon::J4_cmpgtui_t_jumpnv_nt:
13087 case Hexagon::J4_cmpgtui_t_jumpnv_t: {
13088 switch (OpNum) {
13089 case 1:
13090 // op: II
13091 return 8;
13092 case 2:
13093 // op: Ii
13094 return 1;
13095 case 0:
13096 // op: Ns8
13097 return 16;
13098 }
13099 break;
13100 }
13101 case Hexagon::J4_jumpseti: {
13102 switch (OpNum) {
13103 case 1:
13104 // op: II
13105 return 8;
13106 case 2:
13107 // op: Ii
13108 return 1;
13109 case 0:
13110 // op: Rd16
13111 return 16;
13112 }
13113 break;
13114 }
13115 case Hexagon::J4_cmpeqi_fp0_jump_nt:
13116 case Hexagon::J4_cmpeqi_fp0_jump_t:
13117 case Hexagon::J4_cmpeqi_fp1_jump_nt:
13118 case Hexagon::J4_cmpeqi_fp1_jump_t:
13119 case Hexagon::J4_cmpeqi_tp0_jump_nt:
13120 case Hexagon::J4_cmpeqi_tp0_jump_t:
13121 case Hexagon::J4_cmpeqi_tp1_jump_nt:
13122 case Hexagon::J4_cmpeqi_tp1_jump_t:
13123 case Hexagon::J4_cmpgti_fp0_jump_nt:
13124 case Hexagon::J4_cmpgti_fp0_jump_t:
13125 case Hexagon::J4_cmpgti_fp1_jump_nt:
13126 case Hexagon::J4_cmpgti_fp1_jump_t:
13127 case Hexagon::J4_cmpgti_tp0_jump_nt:
13128 case Hexagon::J4_cmpgti_tp0_jump_t:
13129 case Hexagon::J4_cmpgti_tp1_jump_nt:
13130 case Hexagon::J4_cmpgti_tp1_jump_t:
13131 case Hexagon::J4_cmpgtui_fp0_jump_nt:
13132 case Hexagon::J4_cmpgtui_fp0_jump_t:
13133 case Hexagon::J4_cmpgtui_fp1_jump_nt:
13134 case Hexagon::J4_cmpgtui_fp1_jump_t:
13135 case Hexagon::J4_cmpgtui_tp0_jump_nt:
13136 case Hexagon::J4_cmpgtui_tp0_jump_t:
13137 case Hexagon::J4_cmpgtui_tp1_jump_nt:
13138 case Hexagon::J4_cmpgtui_tp1_jump_t: {
13139 switch (OpNum) {
13140 case 1:
13141 // op: II
13142 return 8;
13143 case 2:
13144 // op: Ii
13145 return 1;
13146 case 0:
13147 // op: Rs16
13148 return 16;
13149 }
13150 break;
13151 }
13152 case Hexagon::SA1_cmpeqi:
13153 case Hexagon::SS2_storebi0:
13154 case Hexagon::SS2_storebi1:
13155 case Hexagon::SS2_storewi0:
13156 case Hexagon::SS2_storewi1: {
13157 switch (OpNum) {
13158 case 1:
13159 // op: Ii
13160 return 0;
13161 case 0:
13162 // op: Rs16
13163 return 4;
13164 }
13165 break;
13166 }
13167 case Hexagon::S2_storerbnew_io:
13168 case Hexagon::S2_storerhnew_io:
13169 case Hexagon::S2_storerinew_io: {
13170 switch (OpNum) {
13171 case 1:
13172 // op: Ii
13173 return 0;
13174 case 0:
13175 // op: Rs32
13176 return 16;
13177 case 2:
13178 // op: Nt8
13179 return 8;
13180 }
13181 break;
13182 }
13183 case Hexagon::S2_storerb_io:
13184 case Hexagon::S2_storerf_io:
13185 case Hexagon::S2_storerh_io:
13186 case Hexagon::S2_storeri_io: {
13187 switch (OpNum) {
13188 case 1:
13189 // op: Ii
13190 return 0;
13191 case 0:
13192 // op: Rs32
13193 return 16;
13194 case 2:
13195 // op: Rt32
13196 return 8;
13197 }
13198 break;
13199 }
13200 case Hexagon::S2_storerd_io: {
13201 switch (OpNum) {
13202 case 1:
13203 // op: Ii
13204 return 0;
13205 case 0:
13206 // op: Rs32
13207 return 16;
13208 case 2:
13209 // op: Rtt32
13210 return 8;
13211 }
13212 break;
13213 }
13214 case Hexagon::Y2_dcfetchbo: {
13215 switch (OpNum) {
13216 case 1:
13217 // op: Ii
13218 return 0;
13219 case 0:
13220 // op: Rs32
13221 return 16;
13222 }
13223 break;
13224 }
13225 case Hexagon::J4_tstbit0_f_jumpnv_nt:
13226 case Hexagon::J4_tstbit0_f_jumpnv_t:
13227 case Hexagon::J4_tstbit0_t_jumpnv_nt:
13228 case Hexagon::J4_tstbit0_t_jumpnv_t: {
13229 switch (OpNum) {
13230 case 1:
13231 // op: Ii
13232 return 1;
13233 case 0:
13234 // op: Ns8
13235 return 16;
13236 }
13237 break;
13238 }
13239 case Hexagon::J2_callf:
13240 case Hexagon::J2_callt:
13241 case Hexagon::J2_jumpf:
13242 case Hexagon::J2_jumpfnew:
13243 case Hexagon::J2_jumpfnewpt:
13244 case Hexagon::J2_jumpfpt:
13245 case Hexagon::J2_jumpt:
13246 case Hexagon::J2_jumptnew:
13247 case Hexagon::J2_jumptnewpt:
13248 case Hexagon::J2_jumptpt: {
13249 switch (OpNum) {
13250 case 1:
13251 // op: Ii
13252 return 1;
13253 case 0:
13254 // op: Pu4
13255 return 8;
13256 }
13257 break;
13258 }
13259 case Hexagon::J4_tstbit0_fp0_jump_nt:
13260 case Hexagon::J4_tstbit0_fp0_jump_t:
13261 case Hexagon::J4_tstbit0_fp1_jump_nt:
13262 case Hexagon::J4_tstbit0_fp1_jump_t:
13263 case Hexagon::J4_tstbit0_tp0_jump_nt:
13264 case Hexagon::J4_tstbit0_tp0_jump_t:
13265 case Hexagon::J4_tstbit0_tp1_jump_nt:
13266 case Hexagon::J4_tstbit0_tp1_jump_t: {
13267 switch (OpNum) {
13268 case 1:
13269 // op: Ii
13270 return 1;
13271 case 0:
13272 // op: Rs16
13273 return 16;
13274 }
13275 break;
13276 }
13277 case Hexagon::J2_jumprgtez:
13278 case Hexagon::J2_jumprgtezpt:
13279 case Hexagon::J2_jumprltez:
13280 case Hexagon::J2_jumprltezpt:
13281 case Hexagon::J2_jumprnz:
13282 case Hexagon::J2_jumprnzpt:
13283 case Hexagon::J2_jumprz:
13284 case Hexagon::J2_jumprzpt: {
13285 switch (OpNum) {
13286 case 1:
13287 // op: Ii
13288 return 1;
13289 case 0:
13290 // op: Rs32
13291 return 16;
13292 }
13293 break;
13294 }
13295 case Hexagon::S4_pstorerbnewf_abs:
13296 case Hexagon::S4_pstorerbnewfnew_abs:
13297 case Hexagon::S4_pstorerbnewt_abs:
13298 case Hexagon::S4_pstorerbnewtnew_abs:
13299 case Hexagon::S4_pstorerhnewf_abs:
13300 case Hexagon::S4_pstorerhnewfnew_abs:
13301 case Hexagon::S4_pstorerhnewt_abs:
13302 case Hexagon::S4_pstorerhnewtnew_abs:
13303 case Hexagon::S4_pstorerinewf_abs:
13304 case Hexagon::S4_pstorerinewfnew_abs:
13305 case Hexagon::S4_pstorerinewt_abs:
13306 case Hexagon::S4_pstorerinewtnew_abs: {
13307 switch (OpNum) {
13308 case 1:
13309 // op: Ii
13310 return 3;
13311 case 0:
13312 // op: Pv4
13313 return 0;
13314 case 2:
13315 // op: Nt8
13316 return 8;
13317 }
13318 break;
13319 }
13320 case Hexagon::S4_pstorerbf_abs:
13321 case Hexagon::S4_pstorerbfnew_abs:
13322 case Hexagon::S4_pstorerbt_abs:
13323 case Hexagon::S4_pstorerbtnew_abs:
13324 case Hexagon::S4_pstorerff_abs:
13325 case Hexagon::S4_pstorerffnew_abs:
13326 case Hexagon::S4_pstorerft_abs:
13327 case Hexagon::S4_pstorerftnew_abs:
13328 case Hexagon::S4_pstorerhf_abs:
13329 case Hexagon::S4_pstorerhfnew_abs:
13330 case Hexagon::S4_pstorerht_abs:
13331 case Hexagon::S4_pstorerhtnew_abs:
13332 case Hexagon::S4_pstorerif_abs:
13333 case Hexagon::S4_pstorerifnew_abs:
13334 case Hexagon::S4_pstorerit_abs:
13335 case Hexagon::S4_pstoreritnew_abs: {
13336 switch (OpNum) {
13337 case 1:
13338 // op: Ii
13339 return 3;
13340 case 0:
13341 // op: Pv4
13342 return 0;
13343 case 2:
13344 // op: Rt32
13345 return 8;
13346 }
13347 break;
13348 }
13349 case Hexagon::S4_pstorerdf_abs:
13350 case Hexagon::S4_pstorerdfnew_abs:
13351 case Hexagon::S4_pstorerdt_abs:
13352 case Hexagon::S4_pstorerdtnew_abs: {
13353 switch (OpNum) {
13354 case 1:
13355 // op: Ii
13356 return 3;
13357 case 0:
13358 // op: Pv4
13359 return 0;
13360 case 2:
13361 // op: Rtt32
13362 return 8;
13363 }
13364 break;
13365 }
13366 case Hexagon::SL2_loadrd_sp: {
13367 switch (OpNum) {
13368 case 1:
13369 // op: Ii
13370 return 3;
13371 case 0:
13372 // op: Rdd8
13373 return 0;
13374 }
13375 break;
13376 }
13377 case Hexagon::S4_addi_asl_ri:
13378 case Hexagon::S4_addi_lsr_ri:
13379 case Hexagon::S4_andi_asl_ri:
13380 case Hexagon::S4_andi_lsr_ri:
13381 case Hexagon::S4_ori_asl_ri:
13382 case Hexagon::S4_ori_lsr_ri:
13383 case Hexagon::S4_subi_asl_ri:
13384 case Hexagon::S4_subi_lsr_ri: {
13385 switch (OpNum) {
13386 case 1:
13387 // op: Ii
13388 return 3;
13389 case 3:
13390 // op: II
13391 return 8;
13392 case 0:
13393 // op: Rx32
13394 return 16;
13395 }
13396 break;
13397 }
13398 case Hexagon::SA1_addsp:
13399 case Hexagon::SA1_seti:
13400 case Hexagon::SL2_loadri_sp: {
13401 switch (OpNum) {
13402 case 1:
13403 // op: Ii
13404 return 4;
13405 case 0:
13406 // op: Rd16
13407 return 0;
13408 }
13409 break;
13410 }
13411 case Hexagon::A2_tfrsi:
13412 case Hexagon::F2_sfimm_n:
13413 case Hexagon::F2_sfimm_p:
13414 case Hexagon::L2_loadrbgp:
13415 case Hexagon::L2_loadrhgp:
13416 case Hexagon::L2_loadrigp:
13417 case Hexagon::L2_loadrubgp:
13418 case Hexagon::L2_loadruhgp:
13419 case Hexagon::PS_loadrbabs:
13420 case Hexagon::PS_loadrhabs:
13421 case Hexagon::PS_loadriabs:
13422 case Hexagon::PS_loadrubabs:
13423 case Hexagon::PS_loadruhabs: {
13424 switch (OpNum) {
13425 case 1:
13426 // op: Ii
13427 return 5;
13428 case 0:
13429 // op: Rd32
13430 return 0;
13431 }
13432 break;
13433 }
13434 case Hexagon::F2_dfimm_n:
13435 case Hexagon::F2_dfimm_p:
13436 case Hexagon::L2_loadrdgp:
13437 case Hexagon::PS_loadrdabs: {
13438 switch (OpNum) {
13439 case 1:
13440 // op: Ii
13441 return 5;
13442 case 0:
13443 // op: Rdd32
13444 return 0;
13445 }
13446 break;
13447 }
13448 case Hexagon::SA1_combine0i:
13449 case Hexagon::SA1_combine1i:
13450 case Hexagon::SA1_combine2i:
13451 case Hexagon::SA1_combine3i: {
13452 switch (OpNum) {
13453 case 1:
13454 // op: Ii
13455 return 5;
13456 case 0:
13457 // op: Rdd8
13458 return 0;
13459 }
13460 break;
13461 }
13462 case Hexagon::A2_combineii:
13463 case Hexagon::A4_combineii: {
13464 switch (OpNum) {
13465 case 1:
13466 // op: Ii
13467 return 5;
13468 case 2:
13469 // op: II
13470 return 13;
13471 case 0:
13472 // op: Rdd32
13473 return 0;
13474 }
13475 break;
13476 }
13477 case Hexagon::A2_subri: {
13478 switch (OpNum) {
13479 case 1:
13480 // op: Ii
13481 return 5;
13482 case 2:
13483 // op: Rs32
13484 return 16;
13485 case 0:
13486 // op: Rd32
13487 return 0;
13488 }
13489 break;
13490 }
13491 case Hexagon::A4_combineir: {
13492 switch (OpNum) {
13493 case 1:
13494 // op: Ii
13495 return 5;
13496 case 2:
13497 // op: Rs32
13498 return 16;
13499 case 0:
13500 // op: Rdd32
13501 return 0;
13502 }
13503 break;
13504 }
13505 case Hexagon::M4_mpyrr_addi: {
13506 switch (OpNum) {
13507 case 1:
13508 // op: Ii
13509 return 5;
13510 case 2:
13511 // op: Rs32
13512 return 16;
13513 case 3:
13514 // op: Rt32
13515 return 8;
13516 case 0:
13517 // op: Rd32
13518 return 0;
13519 }
13520 break;
13521 }
13522 case Hexagon::S4_lsli: {
13523 switch (OpNum) {
13524 case 1:
13525 // op: Ii
13526 return 5;
13527 case 2:
13528 // op: Rt32
13529 return 8;
13530 case 0:
13531 // op: Rd32
13532 return 0;
13533 }
13534 break;
13535 }
13536 case Hexagon::M4_mpyri_addi: {
13537 switch (OpNum) {
13538 case 1:
13539 // op: Ii
13540 return 5;
13541 case 3:
13542 // op: II
13543 return 0;
13544 case 2:
13545 // op: Rs32
13546 return 16;
13547 case 0:
13548 // op: Rd32
13549 return 8;
13550 }
13551 break;
13552 }
13553 case Hexagon::S4_storerbnew_ur:
13554 case Hexagon::S4_storerhnew_ur:
13555 case Hexagon::S4_storerinew_ur: {
13556 switch (OpNum) {
13557 case 1:
13558 // op: Ii
13559 return 6;
13560 case 2:
13561 // op: II
13562 return 0;
13563 case 0:
13564 // op: Ru32
13565 return 16;
13566 case 3:
13567 // op: Nt8
13568 return 8;
13569 }
13570 break;
13571 }
13572 case Hexagon::S4_storerb_ur:
13573 case Hexagon::S4_storerf_ur:
13574 case Hexagon::S4_storerh_ur:
13575 case Hexagon::S4_storeri_ur: {
13576 switch (OpNum) {
13577 case 1:
13578 // op: Ii
13579 return 6;
13580 case 2:
13581 // op: II
13582 return 0;
13583 case 0:
13584 // op: Ru32
13585 return 16;
13586 case 3:
13587 // op: Rt32
13588 return 8;
13589 }
13590 break;
13591 }
13592 case Hexagon::S4_storerd_ur: {
13593 switch (OpNum) {
13594 case 1:
13595 // op: Ii
13596 return 6;
13597 case 2:
13598 // op: II
13599 return 0;
13600 case 0:
13601 // op: Ru32
13602 return 16;
13603 case 3:
13604 // op: Rtt32
13605 return 8;
13606 }
13607 break;
13608 }
13609 case Hexagon::C4_addipc: {
13610 switch (OpNum) {
13611 case 1:
13612 // op: Ii
13613 return 7;
13614 case 0:
13615 // op: Rd32
13616 return 0;
13617 }
13618 break;
13619 }
13620 case Hexagon::L4_add_memopb_io:
13621 case Hexagon::L4_add_memoph_io:
13622 case Hexagon::L4_add_memopw_io:
13623 case Hexagon::L4_and_memopb_io:
13624 case Hexagon::L4_and_memoph_io:
13625 case Hexagon::L4_and_memopw_io:
13626 case Hexagon::L4_or_memopb_io:
13627 case Hexagon::L4_or_memoph_io:
13628 case Hexagon::L4_or_memopw_io:
13629 case Hexagon::L4_sub_memopb_io:
13630 case Hexagon::L4_sub_memoph_io:
13631 case Hexagon::L4_sub_memopw_io: {
13632 switch (OpNum) {
13633 case 1:
13634 // op: Ii
13635 return 7;
13636 case 0:
13637 // op: Rs32
13638 return 16;
13639 case 2:
13640 // op: Rt32
13641 return 0;
13642 }
13643 break;
13644 }
13645 case Hexagon::L4_iadd_memopb_io:
13646 case Hexagon::L4_iadd_memoph_io:
13647 case Hexagon::L4_iadd_memopw_io:
13648 case Hexagon::L4_iand_memopb_io:
13649 case Hexagon::L4_iand_memoph_io:
13650 case Hexagon::L4_iand_memopw_io:
13651 case Hexagon::L4_ior_memopb_io:
13652 case Hexagon::L4_ior_memoph_io:
13653 case Hexagon::L4_ior_memopw_io:
13654 case Hexagon::L4_isub_memopb_io:
13655 case Hexagon::L4_isub_memoph_io:
13656 case Hexagon::L4_isub_memopw_io:
13657 case Hexagon::S4_storeirb_io:
13658 case Hexagon::S4_storeirh_io:
13659 case Hexagon::S4_storeiri_io: {
13660 switch (OpNum) {
13661 case 1:
13662 // op: Ii
13663 return 7;
13664 case 2:
13665 // op: II
13666 return 0;
13667 case 0:
13668 // op: Rs32
13669 return 16;
13670 }
13671 break;
13672 }
13673 case Hexagon::V6_vwhist128qm: {
13674 switch (OpNum) {
13675 case 1:
13676 // op: Ii
13677 return 8;
13678 case 0:
13679 // op: Qv4
13680 return 22;
13681 }
13682 break;
13683 }
13684 case Hexagon::SS1_storeb_io:
13685 case Hexagon::SS1_storew_io:
13686 case Hexagon::SS2_storeh_io: {
13687 switch (OpNum) {
13688 case 1:
13689 // op: Ii
13690 return 8;
13691 case 0:
13692 // op: Rs16
13693 return 4;
13694 case 2:
13695 // op: Rt16
13696 return 0;
13697 }
13698 break;
13699 }
13700 case Hexagon::V6_vS32b_new_ai:
13701 case Hexagon::V6_vS32b_nt_new_ai: {
13702 switch (OpNum) {
13703 case 1:
13704 // op: Ii
13705 return 8;
13706 case 0:
13707 // op: Rt32
13708 return 16;
13709 case 2:
13710 // op: Os8
13711 return 0;
13712 }
13713 break;
13714 }
13715 case Hexagon::V6_vS32Ub_ai:
13716 case Hexagon::V6_vS32b_ai:
13717 case Hexagon::V6_vS32b_nt_ai: {
13718 switch (OpNum) {
13719 case 1:
13720 // op: Ii
13721 return 8;
13722 case 0:
13723 // op: Rt32
13724 return 16;
13725 case 2:
13726 // op: Vs32
13727 return 0;
13728 }
13729 break;
13730 }
13731 case Hexagon::V6_vS32b_srls_ai:
13732 case Hexagon::V6_zLd_ai: {
13733 switch (OpNum) {
13734 case 1:
13735 // op: Ii
13736 return 8;
13737 case 0:
13738 // op: Rt32
13739 return 16;
13740 }
13741 break;
13742 }
13743 case Hexagon::S2_mask: {
13744 switch (OpNum) {
13745 case 1:
13746 // op: Ii
13747 return 8;
13748 case 2:
13749 // op: II
13750 return 5;
13751 case 0:
13752 // op: Rd32
13753 return 0;
13754 }
13755 break;
13756 }
13757 case Hexagon::C2_all8:
13758 case Hexagon::C2_any8:
13759 case Hexagon::C2_not: {
13760 switch (OpNum) {
13761 case 1:
13762 // op: Ps4
13763 return 16;
13764 case 0:
13765 // op: Pd4
13766 return 0;
13767 }
13768 break;
13769 }
13770 case Hexagon::C2_tfrpr: {
13771 switch (OpNum) {
13772 case 1:
13773 // op: Ps4
13774 return 16;
13775 case 0:
13776 // op: Rd32
13777 return 0;
13778 }
13779 break;
13780 }
13781 case Hexagon::C2_xor:
13782 case Hexagon::C4_fastcorner9:
13783 case Hexagon::C4_fastcorner9_not: {
13784 switch (OpNum) {
13785 case 1:
13786 // op: Ps4
13787 return 16;
13788 case 2:
13789 // op: Pt4
13790 return 8;
13791 case 0:
13792 // op: Pd4
13793 return 0;
13794 }
13795 break;
13796 }
13797 case Hexagon::C2_vitpack: {
13798 switch (OpNum) {
13799 case 1:
13800 // op: Ps4
13801 return 16;
13802 case 2:
13803 // op: Pt4
13804 return 8;
13805 case 0:
13806 // op: Rd32
13807 return 0;
13808 }
13809 break;
13810 }
13811 case Hexagon::C4_and_and:
13812 case Hexagon::C4_and_andn:
13813 case Hexagon::C4_and_or:
13814 case Hexagon::C4_and_orn:
13815 case Hexagon::C4_or_and:
13816 case Hexagon::C4_or_andn:
13817 case Hexagon::C4_or_or:
13818 case Hexagon::C4_or_orn: {
13819 switch (OpNum) {
13820 case 1:
13821 // op: Ps4
13822 return 16;
13823 case 2:
13824 // op: Pt4
13825 return 8;
13826 case 3:
13827 // op: Pu4
13828 return 6;
13829 case 0:
13830 // op: Pd4
13831 return 0;
13832 }
13833 break;
13834 }
13835 case Hexagon::V6_vcmov:
13836 case Hexagon::V6_vncmov: {
13837 switch (OpNum) {
13838 case 1:
13839 // op: Ps4
13840 return 5;
13841 case 2:
13842 // op: Vu32
13843 return 8;
13844 case 0:
13845 // op: Vd32
13846 return 0;
13847 }
13848 break;
13849 }
13850 case Hexagon::V6_vccombine:
13851 case Hexagon::V6_vnccombine: {
13852 switch (OpNum) {
13853 case 1:
13854 // op: Ps4
13855 return 5;
13856 case 2:
13857 // op: Vu32
13858 return 8;
13859 case 3:
13860 // op: Vv32
13861 return 16;
13862 case 0:
13863 // op: Vdd32
13864 return 0;
13865 }
13866 break;
13867 }
13868 case Hexagon::C2_mask: {
13869 switch (OpNum) {
13870 case 1:
13871 // op: Pt4
13872 return 8;
13873 case 0:
13874 // op: Rdd32
13875 return 0;
13876 }
13877 break;
13878 }
13879 case Hexagon::C2_and:
13880 case Hexagon::C2_andn:
13881 case Hexagon::C2_or:
13882 case Hexagon::C2_orn: {
13883 switch (OpNum) {
13884 case 1:
13885 // op: Pt4
13886 return 8;
13887 case 2:
13888 // op: Ps4
13889 return 16;
13890 case 0:
13891 // op: Pd4
13892 return 0;
13893 }
13894 break;
13895 }
13896 case Hexagon::A2_paddf:
13897 case Hexagon::A2_paddfnew:
13898 case Hexagon::A2_paddt:
13899 case Hexagon::A2_paddtnew:
13900 case Hexagon::A2_pandf:
13901 case Hexagon::A2_pandfnew:
13902 case Hexagon::A2_pandt:
13903 case Hexagon::A2_pandtnew:
13904 case Hexagon::A2_porf:
13905 case Hexagon::A2_porfnew:
13906 case Hexagon::A2_port:
13907 case Hexagon::A2_portnew:
13908 case Hexagon::A2_pxorf:
13909 case Hexagon::A2_pxorfnew:
13910 case Hexagon::A2_pxort:
13911 case Hexagon::A2_pxortnew:
13912 case Hexagon::C2_mux: {
13913 switch (OpNum) {
13914 case 1:
13915 // op: Pu4
13916 return 5;
13917 case 2:
13918 // op: Rs32
13919 return 16;
13920 case 3:
13921 // op: Rt32
13922 return 8;
13923 case 0:
13924 // op: Rd32
13925 return 0;
13926 }
13927 break;
13928 }
13929 case Hexagon::C2_ccombinewf:
13930 case Hexagon::C2_ccombinewnewf:
13931 case Hexagon::C2_ccombinewnewt:
13932 case Hexagon::C2_ccombinewt: {
13933 switch (OpNum) {
13934 case 1:
13935 // op: Pu4
13936 return 5;
13937 case 2:
13938 // op: Rs32
13939 return 16;
13940 case 3:
13941 // op: Rt32
13942 return 8;
13943 case 0:
13944 // op: Rdd32
13945 return 0;
13946 }
13947 break;
13948 }
13949 case Hexagon::C2_vmux: {
13950 switch (OpNum) {
13951 case 1:
13952 // op: Pu4
13953 return 5;
13954 case 2:
13955 // op: Rss32
13956 return 16;
13957 case 3:
13958 // op: Rtt32
13959 return 8;
13960 case 0:
13961 // op: Rdd32
13962 return 0;
13963 }
13964 break;
13965 }
13966 case Hexagon::A2_psubf:
13967 case Hexagon::A2_psubfnew:
13968 case Hexagon::A2_psubt:
13969 case Hexagon::A2_psubtnew: {
13970 switch (OpNum) {
13971 case 1:
13972 // op: Pu4
13973 return 5;
13974 case 2:
13975 // op: Rt32
13976 return 8;
13977 case 3:
13978 // op: Rs32
13979 return 16;
13980 case 0:
13981 // op: Rd32
13982 return 0;
13983 }
13984 break;
13985 }
13986 case Hexagon::A4_paslhf:
13987 case Hexagon::A4_paslhfnew:
13988 case Hexagon::A4_paslht:
13989 case Hexagon::A4_paslhtnew:
13990 case Hexagon::A4_pasrhf:
13991 case Hexagon::A4_pasrhfnew:
13992 case Hexagon::A4_pasrht:
13993 case Hexagon::A4_pasrhtnew:
13994 case Hexagon::A4_psxtbf:
13995 case Hexagon::A4_psxtbfnew:
13996 case Hexagon::A4_psxtbt:
13997 case Hexagon::A4_psxtbtnew:
13998 case Hexagon::A4_psxthf:
13999 case Hexagon::A4_psxthfnew:
14000 case Hexagon::A4_psxtht:
14001 case Hexagon::A4_psxthtnew:
14002 case Hexagon::A4_pzxtbf:
14003 case Hexagon::A4_pzxtbfnew:
14004 case Hexagon::A4_pzxtbt:
14005 case Hexagon::A4_pzxtbtnew:
14006 case Hexagon::A4_pzxthf:
14007 case Hexagon::A4_pzxthfnew:
14008 case Hexagon::A4_pzxtht:
14009 case Hexagon::A4_pzxthtnew: {
14010 switch (OpNum) {
14011 case 1:
14012 // op: Pu4
14013 return 8;
14014 case 2:
14015 // op: Rs32
14016 return 16;
14017 case 0:
14018 // op: Rd32
14019 return 0;
14020 }
14021 break;
14022 }
14023 case Hexagon::V6_zLd_pred_ppu: {
14024 switch (OpNum) {
14025 case 1:
14026 // op: Pv4
14027 return 11;
14028 case 3:
14029 // op: Mu2
14030 return 13;
14031 case 0:
14032 // op: Rx32
14033 return 16;
14034 }
14035 break;
14036 }
14037 case Hexagon::V6_vS32b_new_npred_ppu:
14038 case Hexagon::V6_vS32b_new_pred_ppu:
14039 case Hexagon::V6_vS32b_nt_new_npred_ppu:
14040 case Hexagon::V6_vS32b_nt_new_pred_ppu: {
14041 switch (OpNum) {
14042 case 1:
14043 // op: Pv4
14044 return 11;
14045 case 3:
14046 // op: Mu2
14047 return 13;
14048 case 4:
14049 // op: Os8
14050 return 0;
14051 case 0:
14052 // op: Rx32
14053 return 16;
14054 }
14055 break;
14056 }
14057 case Hexagon::V6_vS32Ub_npred_ppu:
14058 case Hexagon::V6_vS32Ub_pred_ppu:
14059 case Hexagon::V6_vS32b_npred_ppu:
14060 case Hexagon::V6_vS32b_nt_npred_ppu:
14061 case Hexagon::V6_vS32b_nt_pred_ppu:
14062 case Hexagon::V6_vS32b_pred_ppu: {
14063 switch (OpNum) {
14064 case 1:
14065 // op: Pv4
14066 return 11;
14067 case 3:
14068 // op: Mu2
14069 return 13;
14070 case 4:
14071 // op: Vs32
14072 return 0;
14073 case 0:
14074 // op: Rx32
14075 return 16;
14076 }
14077 break;
14078 }
14079 case Hexagon::L4_return_f:
14080 case Hexagon::L4_return_fnew_pnt:
14081 case Hexagon::L4_return_fnew_pt:
14082 case Hexagon::L4_return_t:
14083 case Hexagon::L4_return_tnew_pnt:
14084 case Hexagon::L4_return_tnew_pt: {
14085 switch (OpNum) {
14086 case 1:
14087 // op: Pv4
14088 return 8;
14089 case 2:
14090 // op: Rs32
14091 return 16;
14092 case 0:
14093 // op: Rdd32
14094 return 0;
14095 }
14096 break;
14097 }
14098 case Hexagon::V6_pred_not: {
14099 switch (OpNum) {
14100 case 1:
14101 // op: Qs4
14102 return 8;
14103 case 0:
14104 // op: Qd4
14105 return 0;
14106 }
14107 break;
14108 }
14109 case Hexagon::V6_pred_and:
14110 case Hexagon::V6_pred_and_n:
14111 case Hexagon::V6_pred_or:
14112 case Hexagon::V6_pred_or_n:
14113 case Hexagon::V6_pred_xor:
14114 case Hexagon::V6_shuffeqh:
14115 case Hexagon::V6_shuffeqw: {
14116 switch (OpNum) {
14117 case 1:
14118 // op: Qs4
14119 return 8;
14120 case 2:
14121 // op: Qt4
14122 return 22;
14123 case 0:
14124 // op: Qd4
14125 return 0;
14126 }
14127 break;
14128 }
14129 case Hexagon::V6_vmux: {
14130 switch (OpNum) {
14131 case 1:
14132 // op: Qt4
14133 return 5;
14134 case 2:
14135 // op: Vu32
14136 return 8;
14137 case 3:
14138 // op: Vv32
14139 return 16;
14140 case 0:
14141 // op: Vd32
14142 return 0;
14143 }
14144 break;
14145 }
14146 case Hexagon::V6_vswap: {
14147 switch (OpNum) {
14148 case 1:
14149 // op: Qt4
14150 return 5;
14151 case 2:
14152 // op: Vu32
14153 return 8;
14154 case 3:
14155 // op: Vv32
14156 return 16;
14157 case 0:
14158 // op: Vdd32
14159 return 0;
14160 }
14161 break;
14162 }
14163 case Hexagon::V6_vandnqrt:
14164 case Hexagon::V6_vandqrt: {
14165 switch (OpNum) {
14166 case 1:
14167 // op: Qu4
14168 return 8;
14169 case 2:
14170 // op: Rt32
14171 return 16;
14172 case 0:
14173 // op: Vd32
14174 return 0;
14175 }
14176 break;
14177 }
14178 case Hexagon::V6_vS32b_nqpred_ppu:
14179 case Hexagon::V6_vS32b_nt_nqpred_ppu:
14180 case Hexagon::V6_vS32b_nt_qpred_ppu:
14181 case Hexagon::V6_vS32b_qpred_ppu: {
14182 switch (OpNum) {
14183 case 1:
14184 // op: Qv4
14185 return 11;
14186 case 3:
14187 // op: Mu2
14188 return 13;
14189 case 4:
14190 // op: Vs32
14191 return 0;
14192 case 0:
14193 // op: Rx32
14194 return 16;
14195 }
14196 break;
14197 }
14198 case Hexagon::V6_vprefixqb:
14199 case Hexagon::V6_vprefixqh:
14200 case Hexagon::V6_vprefixqw: {
14201 switch (OpNum) {
14202 case 1:
14203 // op: Qv4
14204 return 22;
14205 case 0:
14206 // op: Vd32
14207 return 0;
14208 }
14209 break;
14210 }
14211 case Hexagon::V6_vandvnqv:
14212 case Hexagon::V6_vandvqv: {
14213 switch (OpNum) {
14214 case 1:
14215 // op: Qv4
14216 return 22;
14217 case 2:
14218 // op: Vu32
14219 return 8;
14220 case 0:
14221 // op: Vd32
14222 return 0;
14223 }
14224 break;
14225 }
14226 case Hexagon::V6_vaddbnq:
14227 case Hexagon::V6_vaddbq:
14228 case Hexagon::V6_vaddhnq:
14229 case Hexagon::V6_vaddhq:
14230 case Hexagon::V6_vaddwnq:
14231 case Hexagon::V6_vaddwq:
14232 case Hexagon::V6_vsubbnq:
14233 case Hexagon::V6_vsubbq:
14234 case Hexagon::V6_vsubhnq:
14235 case Hexagon::V6_vsubhq:
14236 case Hexagon::V6_vsubwnq:
14237 case Hexagon::V6_vsubwq: {
14238 switch (OpNum) {
14239 case 1:
14240 // op: Qv4
14241 return 22;
14242 case 3:
14243 // op: Vu32
14244 return 8;
14245 case 0:
14246 // op: Vx32
14247 return 0;
14248 }
14249 break;
14250 }
14251 case Hexagon::SA1_and1:
14252 case Hexagon::SA1_dec:
14253 case Hexagon::SA1_inc:
14254 case Hexagon::SA1_sxtb:
14255 case Hexagon::SA1_sxth:
14256 case Hexagon::SA1_tfr:
14257 case Hexagon::SA1_zxtb:
14258 case Hexagon::SA1_zxth: {
14259 switch (OpNum) {
14260 case 1:
14261 // op: Rs16
14262 return 4;
14263 case 0:
14264 // op: Rd16
14265 return 0;
14266 }
14267 break;
14268 }
14269 case Hexagon::SA1_combinerz:
14270 case Hexagon::SA1_combinezr: {
14271 switch (OpNum) {
14272 case 1:
14273 // op: Rs16
14274 return 4;
14275 case 0:
14276 // op: Rdd8
14277 return 0;
14278 }
14279 break;
14280 }
14281 case Hexagon::A2_tfrrcr: {
14282 switch (OpNum) {
14283 case 1:
14284 // op: Rs32
14285 return 16;
14286 case 0:
14287 // op: Cd32
14288 return 0;
14289 }
14290 break;
14291 }
14292 case Hexagon::G4_tfrgrcr: {
14293 switch (OpNum) {
14294 case 1:
14295 // op: Rs32
14296 return 16;
14297 case 0:
14298 // op: Gd32
14299 return 0;
14300 }
14301 break;
14302 }
14303 case Hexagon::C2_tfrrp:
14304 case Hexagon::Y5_l2locka: {
14305 switch (OpNum) {
14306 case 1:
14307 // op: Rs32
14308 return 16;
14309 case 0:
14310 // op: Pd4
14311 return 0;
14312 }
14313 break;
14314 }
14315 case Hexagon::A2_abs:
14316 case Hexagon::A2_abssat:
14317 case Hexagon::A2_aslh:
14318 case Hexagon::A2_asrh:
14319 case Hexagon::A2_negsat:
14320 case Hexagon::A2_satb:
14321 case Hexagon::A2_sath:
14322 case Hexagon::A2_satub:
14323 case Hexagon::A2_satuh:
14324 case Hexagon::A2_swiz:
14325 case Hexagon::A2_sxtb:
14326 case Hexagon::A2_sxth:
14327 case Hexagon::A2_tfr:
14328 case Hexagon::A2_zxth:
14329 case Hexagon::F2_conv_sf2uw:
14330 case Hexagon::F2_conv_sf2uw_chop:
14331 case Hexagon::F2_conv_sf2w:
14332 case Hexagon::F2_conv_sf2w_chop:
14333 case Hexagon::F2_conv_uw2sf:
14334 case Hexagon::F2_conv_w2sf:
14335 case Hexagon::F2_sffixupr:
14336 case Hexagon::L2_loadw_aq:
14337 case Hexagon::L2_loadw_locked:
14338 case Hexagon::S2_brev:
14339 case Hexagon::S2_cl0:
14340 case Hexagon::S2_cl1:
14341 case Hexagon::S2_clb:
14342 case Hexagon::S2_clbnorm:
14343 case Hexagon::S2_ct0:
14344 case Hexagon::S2_ct1:
14345 case Hexagon::S2_svsathb:
14346 case Hexagon::S2_svsathub:
14347 case Hexagon::S2_vsplatrb:
14348 case Hexagon::Y2_dctagr:
14349 case Hexagon::Y2_getimask:
14350 case Hexagon::Y2_iassignr:
14351 case Hexagon::Y2_icdatar:
14352 case Hexagon::Y2_ictagr:
14353 case Hexagon::Y2_tlbp:
14354 case Hexagon::Y4_l2tagr: {
14355 switch (OpNum) {
14356 case 1:
14357 // op: Rs32
14358 return 16;
14359 case 0:
14360 // op: Rd32
14361 return 0;
14362 }
14363 break;
14364 }
14365 case Hexagon::A2_sxtw:
14366 case Hexagon::F2_conv_sf2d:
14367 case Hexagon::F2_conv_sf2d_chop:
14368 case Hexagon::F2_conv_sf2df:
14369 case Hexagon::F2_conv_sf2ud:
14370 case Hexagon::F2_conv_sf2ud_chop:
14371 case Hexagon::F2_conv_uw2df:
14372 case Hexagon::F2_conv_w2df:
14373 case Hexagon::L2_deallocframe:
14374 case Hexagon::L4_loadd_aq:
14375 case Hexagon::L4_loadd_locked:
14376 case Hexagon::L4_return:
14377 case Hexagon::S2_vsplatrh:
14378 case Hexagon::S2_vsxtbh:
14379 case Hexagon::S2_vsxthw:
14380 case Hexagon::S2_vzxtbh:
14381 case Hexagon::S2_vzxthw:
14382 case Hexagon::S6_vsplatrbp:
14383 case Hexagon::Y2_tlbr: {
14384 switch (OpNum) {
14385 case 1:
14386 // op: Rs32
14387 return 16;
14388 case 0:
14389 // op: Rdd32
14390 return 0;
14391 }
14392 break;
14393 }
14394 case Hexagon::Y2_tfrsrcr: {
14395 switch (OpNum) {
14396 case 1:
14397 // op: Rs32
14398 return 16;
14399 case 0:
14400 // op: Sd128
14401 return 0;
14402 }
14403 break;
14404 }
14405 case Hexagon::A4_cmpbeq:
14406 case Hexagon::A4_cmpbgt:
14407 case Hexagon::A4_cmpbgtu:
14408 case Hexagon::A4_cmpheq:
14409 case Hexagon::A4_cmphgt:
14410 case Hexagon::A4_cmphgtu:
14411 case Hexagon::C2_bitsclr:
14412 case Hexagon::C2_bitsset:
14413 case Hexagon::C2_cmpeq:
14414 case Hexagon::C2_cmpgt:
14415 case Hexagon::C2_cmpgtu:
14416 case Hexagon::C4_cmplte:
14417 case Hexagon::C4_cmplteu:
14418 case Hexagon::C4_cmpneq:
14419 case Hexagon::C4_nbitsclr:
14420 case Hexagon::C4_nbitsset:
14421 case Hexagon::F2_sfcmpeq:
14422 case Hexagon::F2_sfcmpge:
14423 case Hexagon::F2_sfcmpgt:
14424 case Hexagon::F2_sfcmpuo:
14425 case Hexagon::S2_storew_locked:
14426 case Hexagon::S2_tstbit_r:
14427 case Hexagon::S4_ntstbit_r: {
14428 switch (OpNum) {
14429 case 1:
14430 // op: Rs32
14431 return 16;
14432 case 2:
14433 // op: Rt32
14434 return 8;
14435 case 0:
14436 // op: Pd4
14437 return 0;
14438 }
14439 break;
14440 }
14441 case Hexagon::A2_add:
14442 case Hexagon::A2_addsat:
14443 case Hexagon::A2_and:
14444 case Hexagon::A2_max:
14445 case Hexagon::A2_maxu:
14446 case Hexagon::A2_or:
14447 case Hexagon::A2_svaddh:
14448 case Hexagon::A2_svaddhs:
14449 case Hexagon::A2_svadduhs:
14450 case Hexagon::A2_svavgh:
14451 case Hexagon::A2_svavghs:
14452 case Hexagon::A2_xor:
14453 case Hexagon::A4_cround_rr:
14454 case Hexagon::A4_modwrapu:
14455 case Hexagon::A4_rcmpeq:
14456 case Hexagon::A4_rcmpneq:
14457 case Hexagon::A4_round_rr:
14458 case Hexagon::A4_round_rr_sat:
14459 case Hexagon::F2_sfadd:
14460 case Hexagon::F2_sffixupd:
14461 case Hexagon::F2_sffixupn:
14462 case Hexagon::F2_sfmax:
14463 case Hexagon::F2_sfmin:
14464 case Hexagon::F2_sfmpy:
14465 case Hexagon::F2_sfsub:
14466 case Hexagon::L4_loadw_phys:
14467 case Hexagon::M2_cmpyrs_s0:
14468 case Hexagon::M2_cmpyrs_s1:
14469 case Hexagon::M2_cmpyrsc_s0:
14470 case Hexagon::M2_cmpyrsc_s1:
14471 case Hexagon::M2_dpmpyss_rnd_s0:
14472 case Hexagon::M2_hmmpyh_rs1:
14473 case Hexagon::M2_hmmpyh_s1:
14474 case Hexagon::M2_hmmpyl_rs1:
14475 case Hexagon::M2_hmmpyl_s1:
14476 case Hexagon::M2_mpy_hh_s0:
14477 case Hexagon::M2_mpy_hh_s1:
14478 case Hexagon::M2_mpy_hl_s0:
14479 case Hexagon::M2_mpy_hl_s1:
14480 case Hexagon::M2_mpy_lh_s0:
14481 case Hexagon::M2_mpy_lh_s1:
14482 case Hexagon::M2_mpy_ll_s0:
14483 case Hexagon::M2_mpy_ll_s1:
14484 case Hexagon::M2_mpy_rnd_hh_s0:
14485 case Hexagon::M2_mpy_rnd_hh_s1:
14486 case Hexagon::M2_mpy_rnd_hl_s0:
14487 case Hexagon::M2_mpy_rnd_hl_s1:
14488 case Hexagon::M2_mpy_rnd_lh_s0:
14489 case Hexagon::M2_mpy_rnd_lh_s1:
14490 case Hexagon::M2_mpy_rnd_ll_s0:
14491 case Hexagon::M2_mpy_rnd_ll_s1:
14492 case Hexagon::M2_mpy_sat_hh_s0:
14493 case Hexagon::M2_mpy_sat_hh_s1:
14494 case Hexagon::M2_mpy_sat_hl_s0:
14495 case Hexagon::M2_mpy_sat_hl_s1:
14496 case Hexagon::M2_mpy_sat_lh_s0:
14497 case Hexagon::M2_mpy_sat_lh_s1:
14498 case Hexagon::M2_mpy_sat_ll_s0:
14499 case Hexagon::M2_mpy_sat_ll_s1:
14500 case Hexagon::M2_mpy_sat_rnd_hh_s0:
14501 case Hexagon::M2_mpy_sat_rnd_hh_s1:
14502 case Hexagon::M2_mpy_sat_rnd_hl_s0:
14503 case Hexagon::M2_mpy_sat_rnd_hl_s1:
14504 case Hexagon::M2_mpy_sat_rnd_lh_s0:
14505 case Hexagon::M2_mpy_sat_rnd_lh_s1:
14506 case Hexagon::M2_mpy_sat_rnd_ll_s0:
14507 case Hexagon::M2_mpy_sat_rnd_ll_s1:
14508 case Hexagon::M2_mpy_up:
14509 case Hexagon::M2_mpy_up_s1:
14510 case Hexagon::M2_mpy_up_s1_sat:
14511 case Hexagon::M2_mpyi:
14512 case Hexagon::M2_mpysu_up:
14513 case Hexagon::M2_mpyu_hh_s0:
14514 case Hexagon::M2_mpyu_hh_s1:
14515 case Hexagon::M2_mpyu_hl_s0:
14516 case Hexagon::M2_mpyu_hl_s1:
14517 case Hexagon::M2_mpyu_lh_s0:
14518 case Hexagon::M2_mpyu_lh_s1:
14519 case Hexagon::M2_mpyu_ll_s0:
14520 case Hexagon::M2_mpyu_ll_s1:
14521 case Hexagon::M2_mpyu_up:
14522 case Hexagon::M2_vmpy2s_s0pack:
14523 case Hexagon::M2_vmpy2s_s1pack:
14524 case Hexagon::S2_asl_r_r:
14525 case Hexagon::S2_asl_r_r_sat:
14526 case Hexagon::S2_asr_r_r:
14527 case Hexagon::S2_asr_r_r_sat:
14528 case Hexagon::S2_clrbit_r:
14529 case Hexagon::S2_lsl_r_r:
14530 case Hexagon::S2_lsr_r_r:
14531 case Hexagon::S2_setbit_r:
14532 case Hexagon::S2_togglebit_r:
14533 case Hexagon::S4_parity:
14534 case Hexagon::dep_A2_addsat: {
14535 switch (OpNum) {
14536 case 1:
14537 // op: Rs32
14538 return 16;
14539 case 2:
14540 // op: Rt32
14541 return 8;
14542 case 0:
14543 // op: Rd32
14544 return 0;
14545 }
14546 break;
14547 }
14548 case Hexagon::A2_combinew:
14549 case Hexagon::A4_bitsplit:
14550 case Hexagon::M2_cmpyi_s0:
14551 case Hexagon::M2_cmpyr_s0:
14552 case Hexagon::M2_cmpys_s0:
14553 case Hexagon::M2_cmpys_s1:
14554 case Hexagon::M2_cmpysc_s0:
14555 case Hexagon::M2_cmpysc_s1:
14556 case Hexagon::M2_dpmpyss_s0:
14557 case Hexagon::M2_dpmpyuu_s0:
14558 case Hexagon::M2_mpyd_hh_s0:
14559 case Hexagon::M2_mpyd_hh_s1:
14560 case Hexagon::M2_mpyd_hl_s0:
14561 case Hexagon::M2_mpyd_hl_s1:
14562 case Hexagon::M2_mpyd_lh_s0:
14563 case Hexagon::M2_mpyd_lh_s1:
14564 case Hexagon::M2_mpyd_ll_s0:
14565 case Hexagon::M2_mpyd_ll_s1:
14566 case Hexagon::M2_mpyd_rnd_hh_s0:
14567 case Hexagon::M2_mpyd_rnd_hh_s1:
14568 case Hexagon::M2_mpyd_rnd_hl_s0:
14569 case Hexagon::M2_mpyd_rnd_hl_s1:
14570 case Hexagon::M2_mpyd_rnd_lh_s0:
14571 case Hexagon::M2_mpyd_rnd_lh_s1:
14572 case Hexagon::M2_mpyd_rnd_ll_s0:
14573 case Hexagon::M2_mpyd_rnd_ll_s1:
14574 case Hexagon::M2_mpyud_hh_s0:
14575 case Hexagon::M2_mpyud_hh_s1:
14576 case Hexagon::M2_mpyud_hl_s0:
14577 case Hexagon::M2_mpyud_hl_s1:
14578 case Hexagon::M2_mpyud_lh_s0:
14579 case Hexagon::M2_mpyud_lh_s1:
14580 case Hexagon::M2_mpyud_ll_s0:
14581 case Hexagon::M2_mpyud_ll_s1:
14582 case Hexagon::M2_vmpy2s_s0:
14583 case Hexagon::M2_vmpy2s_s1:
14584 case Hexagon::M2_vmpy2su_s0:
14585 case Hexagon::M2_vmpy2su_s1:
14586 case Hexagon::M4_pmpyw:
14587 case Hexagon::M4_vpmpyh:
14588 case Hexagon::M5_vmpybsu:
14589 case Hexagon::M5_vmpybuu:
14590 case Hexagon::S2_packhl:
14591 case Hexagon::dep_S2_packhl: {
14592 switch (OpNum) {
14593 case 1:
14594 // op: Rs32
14595 return 16;
14596 case 2:
14597 // op: Rt32
14598 return 8;
14599 case 0:
14600 // op: Rdd32
14601 return 0;
14602 }
14603 break;
14604 }
14605 case Hexagon::S4_stored_locked: {
14606 switch (OpNum) {
14607 case 1:
14608 // op: Rs32
14609 return 16;
14610 case 2:
14611 // op: Rtt32
14612 return 8;
14613 case 0:
14614 // op: Pd4
14615 return 0;
14616 }
14617 break;
14618 }
14619 case Hexagon::S2_extractu_rp:
14620 case Hexagon::S4_extract_rp: {
14621 switch (OpNum) {
14622 case 1:
14623 // op: Rs32
14624 return 16;
14625 case 2:
14626 // op: Rtt32
14627 return 8;
14628 case 0:
14629 // op: Rd32
14630 return 0;
14631 }
14632 break;
14633 }
14634 case Hexagon::A4_tfrpcp: {
14635 switch (OpNum) {
14636 case 1:
14637 // op: Rss32
14638 return 16;
14639 case 0:
14640 // op: Cdd32
14641 return 0;
14642 }
14643 break;
14644 }
14645 case Hexagon::G4_tfrgpcp: {
14646 switch (OpNum) {
14647 case 1:
14648 // op: Rss32
14649 return 16;
14650 case 0:
14651 // op: Gdd32
14652 return 0;
14653 }
14654 break;
14655 }
14656 case Hexagon::A2_roundsat:
14657 case Hexagon::A2_sat:
14658 case Hexagon::F2_conv_d2sf:
14659 case Hexagon::F2_conv_df2sf:
14660 case Hexagon::F2_conv_df2uw:
14661 case Hexagon::F2_conv_df2uw_chop:
14662 case Hexagon::F2_conv_df2w:
14663 case Hexagon::F2_conv_df2w_chop:
14664 case Hexagon::F2_conv_ud2sf:
14665 case Hexagon::S2_cl0p:
14666 case Hexagon::S2_cl1p:
14667 case Hexagon::S2_clbp:
14668 case Hexagon::S2_ct0p:
14669 case Hexagon::S2_ct1p:
14670 case Hexagon::S2_vrndpackwh:
14671 case Hexagon::S2_vrndpackwhs:
14672 case Hexagon::S2_vsathb:
14673 case Hexagon::S2_vsathub:
14674 case Hexagon::S2_vsatwh:
14675 case Hexagon::S2_vsatwuh:
14676 case Hexagon::S2_vtrunehb:
14677 case Hexagon::S2_vtrunohb:
14678 case Hexagon::S4_clbpnorm:
14679 case Hexagon::S5_popcountp:
14680 case Hexagon::Y5_tlboc: {
14681 switch (OpNum) {
14682 case 1:
14683 // op: Rss32
14684 return 16;
14685 case 0:
14686 // op: Rd32
14687 return 0;
14688 }
14689 break;
14690 }
14691 case Hexagon::A2_absp:
14692 case Hexagon::A2_negp:
14693 case Hexagon::A2_notp:
14694 case Hexagon::A2_vabsh:
14695 case Hexagon::A2_vabshsat:
14696 case Hexagon::A2_vabsw:
14697 case Hexagon::A2_vabswsat:
14698 case Hexagon::A2_vconj:
14699 case Hexagon::F2_conv_d2df:
14700 case Hexagon::F2_conv_df2d:
14701 case Hexagon::F2_conv_df2d_chop:
14702 case Hexagon::F2_conv_df2ud:
14703 case Hexagon::F2_conv_df2ud_chop:
14704 case Hexagon::F2_conv_ud2df:
14705 case Hexagon::S2_brevp:
14706 case Hexagon::S2_deinterleave:
14707 case Hexagon::S2_interleave:
14708 case Hexagon::S2_vsathb_nopack:
14709 case Hexagon::S2_vsathub_nopack:
14710 case Hexagon::S2_vsatwh_nopack:
14711 case Hexagon::S2_vsatwuh_nopack: {
14712 switch (OpNum) {
14713 case 1:
14714 // op: Rss32
14715 return 16;
14716 case 0:
14717 // op: Rdd32
14718 return 0;
14719 }
14720 break;
14721 }
14722 case Hexagon::Y4_tfrspcp: {
14723 switch (OpNum) {
14724 case 1:
14725 // op: Rss32
14726 return 16;
14727 case 0:
14728 // op: Sdd128
14729 return 0;
14730 }
14731 break;
14732 }
14733 case Hexagon::A4_tlbmatch: {
14734 switch (OpNum) {
14735 case 1:
14736 // op: Rss32
14737 return 16;
14738 case 2:
14739 // op: Rt32
14740 return 8;
14741 case 0:
14742 // op: Pd4
14743 return 0;
14744 }
14745 break;
14746 }
14747 case Hexagon::M4_cmpyi_wh:
14748 case Hexagon::M4_cmpyi_whc:
14749 case Hexagon::M4_cmpyr_wh:
14750 case Hexagon::M4_cmpyr_whc:
14751 case Hexagon::S2_asr_r_svw_trun:
14752 case Hexagon::Y5_ctlbw: {
14753 switch (OpNum) {
14754 case 1:
14755 // op: Rss32
14756 return 16;
14757 case 2:
14758 // op: Rt32
14759 return 8;
14760 case 0:
14761 // op: Rd32
14762 return 0;
14763 }
14764 break;
14765 }
14766 case Hexagon::A7_croundd_rr:
14767 case Hexagon::S2_asl_r_p:
14768 case Hexagon::S2_asl_r_vh:
14769 case Hexagon::S2_asl_r_vw:
14770 case Hexagon::S2_asr_r_p:
14771 case Hexagon::S2_asr_r_vh:
14772 case Hexagon::S2_asr_r_vw:
14773 case Hexagon::S2_lsl_r_p:
14774 case Hexagon::S2_lsl_r_vh:
14775 case Hexagon::S2_lsl_r_vw:
14776 case Hexagon::S2_lsr_r_p:
14777 case Hexagon::S2_lsr_r_vh:
14778 case Hexagon::S2_lsr_r_vw:
14779 case Hexagon::S2_vcnegh:
14780 case Hexagon::S2_vcrotate: {
14781 switch (OpNum) {
14782 case 1:
14783 // op: Rss32
14784 return 16;
14785 case 2:
14786 // op: Rt32
14787 return 8;
14788 case 0:
14789 // op: Rdd32
14790 return 0;
14791 }
14792 break;
14793 }
14794 case Hexagon::A2_vcmpbeq:
14795 case Hexagon::A2_vcmpbgtu:
14796 case Hexagon::A2_vcmpheq:
14797 case Hexagon::A2_vcmphgt:
14798 case Hexagon::A2_vcmphgtu:
14799 case Hexagon::A2_vcmpweq:
14800 case Hexagon::A2_vcmpwgt:
14801 case Hexagon::A2_vcmpwgtu:
14802 case Hexagon::A4_boundscheck_hi:
14803 case Hexagon::A4_boundscheck_lo:
14804 case Hexagon::A4_vcmpbeq_any:
14805 case Hexagon::A4_vcmpbgt:
14806 case Hexagon::A6_vcmpbeq_notany:
14807 case Hexagon::C2_cmpeqp:
14808 case Hexagon::C2_cmpgtp:
14809 case Hexagon::C2_cmpgtup:
14810 case Hexagon::F2_dfcmpeq:
14811 case Hexagon::F2_dfcmpge:
14812 case Hexagon::F2_dfcmpgt:
14813 case Hexagon::F2_dfcmpuo: {
14814 switch (OpNum) {
14815 case 1:
14816 // op: Rss32
14817 return 16;
14818 case 2:
14819 // op: Rtt32
14820 return 8;
14821 case 0:
14822 // op: Pd4
14823 return 0;
14824 }
14825 break;
14826 }
14827 case Hexagon::A5_vaddhubs:
14828 case Hexagon::M2_vdmpyrs_s0:
14829 case Hexagon::M2_vdmpyrs_s1:
14830 case Hexagon::M2_vraddh:
14831 case Hexagon::M2_vradduh:
14832 case Hexagon::M2_vrcmpys_s1rp_h:
14833 case Hexagon::M2_vrcmpys_s1rp_l:
14834 case Hexagon::M7_wcmpyiw:
14835 case Hexagon::M7_wcmpyiw_rnd:
14836 case Hexagon::M7_wcmpyiwc:
14837 case Hexagon::M7_wcmpyiwc_rnd:
14838 case Hexagon::M7_wcmpyrw:
14839 case Hexagon::M7_wcmpyrw_rnd:
14840 case Hexagon::M7_wcmpyrwc:
14841 case Hexagon::M7_wcmpyrwc_rnd:
14842 case Hexagon::S2_parityp: {
14843 switch (OpNum) {
14844 case 1:
14845 // op: Rss32
14846 return 16;
14847 case 2:
14848 // op: Rtt32
14849 return 8;
14850 case 0:
14851 // op: Rd32
14852 return 0;
14853 }
14854 break;
14855 }
14856 case Hexagon::A2_addp:
14857 case Hexagon::A2_addpsat:
14858 case Hexagon::A2_addsph:
14859 case Hexagon::A2_addspl:
14860 case Hexagon::A2_andp:
14861 case Hexagon::A2_maxp:
14862 case Hexagon::A2_maxup:
14863 case Hexagon::A2_orp:
14864 case Hexagon::A2_vaddh:
14865 case Hexagon::A2_vaddhs:
14866 case Hexagon::A2_vaddub:
14867 case Hexagon::A2_vaddubs:
14868 case Hexagon::A2_vadduhs:
14869 case Hexagon::A2_vaddw:
14870 case Hexagon::A2_vaddws:
14871 case Hexagon::A2_vavgh:
14872 case Hexagon::A2_vavghcr:
14873 case Hexagon::A2_vavghr:
14874 case Hexagon::A2_vavgub:
14875 case Hexagon::A2_vavgubr:
14876 case Hexagon::A2_vavguh:
14877 case Hexagon::A2_vavguhr:
14878 case Hexagon::A2_vavguw:
14879 case Hexagon::A2_vavguwr:
14880 case Hexagon::A2_vavgw:
14881 case Hexagon::A2_vavgwcr:
14882 case Hexagon::A2_vavgwr:
14883 case Hexagon::A2_vraddub:
14884 case Hexagon::A2_vrsadub:
14885 case Hexagon::A2_xorp:
14886 case Hexagon::F2_dfadd:
14887 case Hexagon::F2_dfmax:
14888 case Hexagon::F2_dfmin:
14889 case Hexagon::F2_dfmpyfix:
14890 case Hexagon::F2_dfmpyll:
14891 case Hexagon::F2_dfsub:
14892 case Hexagon::M2_mmpyh_rs0:
14893 case Hexagon::M2_mmpyh_rs1:
14894 case Hexagon::M2_mmpyh_s0:
14895 case Hexagon::M2_mmpyh_s1:
14896 case Hexagon::M2_mmpyl_rs0:
14897 case Hexagon::M2_mmpyl_rs1:
14898 case Hexagon::M2_mmpyl_s0:
14899 case Hexagon::M2_mmpyl_s1:
14900 case Hexagon::M2_mmpyuh_rs0:
14901 case Hexagon::M2_mmpyuh_rs1:
14902 case Hexagon::M2_mmpyuh_s0:
14903 case Hexagon::M2_mmpyuh_s1:
14904 case Hexagon::M2_mmpyul_rs0:
14905 case Hexagon::M2_mmpyul_rs1:
14906 case Hexagon::M2_mmpyul_s0:
14907 case Hexagon::M2_mmpyul_s1:
14908 case Hexagon::M2_vcmpy_s0_sat_i:
14909 case Hexagon::M2_vcmpy_s0_sat_r:
14910 case Hexagon::M2_vcmpy_s1_sat_i:
14911 case Hexagon::M2_vcmpy_s1_sat_r:
14912 case Hexagon::M2_vdmpys_s0:
14913 case Hexagon::M2_vdmpys_s1:
14914 case Hexagon::M2_vmpy2es_s0:
14915 case Hexagon::M2_vmpy2es_s1:
14916 case Hexagon::M2_vrcmpyi_s0:
14917 case Hexagon::M2_vrcmpyi_s0c:
14918 case Hexagon::M2_vrcmpyr_s0:
14919 case Hexagon::M2_vrcmpyr_s0c:
14920 case Hexagon::M2_vrcmpys_s1_h:
14921 case Hexagon::M2_vrcmpys_s1_l:
14922 case Hexagon::M2_vrmpy_s0:
14923 case Hexagon::M4_vrmpyeh_s0:
14924 case Hexagon::M4_vrmpyeh_s1:
14925 case Hexagon::M4_vrmpyoh_s0:
14926 case Hexagon::M4_vrmpyoh_s1:
14927 case Hexagon::M5_vdmpybsu:
14928 case Hexagon::M5_vrmpybsu:
14929 case Hexagon::M5_vrmpybuu:
14930 case Hexagon::M7_dcmpyiw:
14931 case Hexagon::M7_dcmpyiwc:
14932 case Hexagon::M7_dcmpyrw:
14933 case Hexagon::M7_dcmpyrwc:
14934 case Hexagon::S2_cabacdecbin:
14935 case Hexagon::S2_extractup_rp:
14936 case Hexagon::S2_lfsp:
14937 case Hexagon::S2_shuffeb:
14938 case Hexagon::S2_shuffeh:
14939 case Hexagon::S2_vtrunewh:
14940 case Hexagon::S2_vtrunowh:
14941 case Hexagon::S4_extractp_rp:
14942 case Hexagon::S4_vxaddsubh:
14943 case Hexagon::S4_vxaddsubhr:
14944 case Hexagon::S4_vxaddsubw:
14945 case Hexagon::S4_vxsubaddh:
14946 case Hexagon::S4_vxsubaddhr:
14947 case Hexagon::S4_vxsubaddw:
14948 case Hexagon::S6_vtrunehb_ppp:
14949 case Hexagon::S6_vtrunohb_ppp: {
14950 switch (OpNum) {
14951 case 1:
14952 // op: Rss32
14953 return 16;
14954 case 2:
14955 // op: Rtt32
14956 return 8;
14957 case 0:
14958 // op: Rdd32
14959 return 0;
14960 }
14961 break;
14962 }
14963 case Hexagon::S2_vsplicerb: {
14964 switch (OpNum) {
14965 case 1:
14966 // op: Rss32
14967 return 16;
14968 case 2:
14969 // op: Rtt32
14970 return 8;
14971 case 3:
14972 // op: Pu4
14973 return 5;
14974 case 0:
14975 // op: Rdd32
14976 return 0;
14977 }
14978 break;
14979 }
14980 case Hexagon::V6_pred_scalar2:
14981 case Hexagon::V6_pred_scalar2v2: {
14982 switch (OpNum) {
14983 case 1:
14984 // op: Rt32
14985 return 16;
14986 case 0:
14987 // op: Qd4
14988 return 0;
14989 }
14990 break;
14991 }
14992 case Hexagon::V6_lvsplatb:
14993 case Hexagon::V6_lvsplath:
14994 case Hexagon::V6_lvsplatw:
14995 case Hexagon::V6_zextract: {
14996 switch (OpNum) {
14997 case 1:
14998 // op: Rt32
14999 return 16;
15000 case 0:
15001 // op: Vd32
15002 return 0;
15003 }
15004 break;
15005 }
15006 case Hexagon::A2_addh_h16_hh:
15007 case Hexagon::A2_addh_h16_hl:
15008 case Hexagon::A2_addh_h16_lh:
15009 case Hexagon::A2_addh_h16_ll:
15010 case Hexagon::A2_addh_h16_sat_hh:
15011 case Hexagon::A2_addh_h16_sat_hl:
15012 case Hexagon::A2_addh_h16_sat_lh:
15013 case Hexagon::A2_addh_h16_sat_ll:
15014 case Hexagon::A2_addh_l16_hl:
15015 case Hexagon::A2_addh_l16_ll:
15016 case Hexagon::A2_addh_l16_sat_hl:
15017 case Hexagon::A2_addh_l16_sat_ll:
15018 case Hexagon::A2_combine_hh:
15019 case Hexagon::A2_combine_hl:
15020 case Hexagon::A2_combine_lh:
15021 case Hexagon::A2_combine_ll:
15022 case Hexagon::A2_min:
15023 case Hexagon::A2_minu:
15024 case Hexagon::A2_sub:
15025 case Hexagon::A2_subh_h16_hh:
15026 case Hexagon::A2_subh_h16_hl:
15027 case Hexagon::A2_subh_h16_lh:
15028 case Hexagon::A2_subh_h16_ll:
15029 case Hexagon::A2_subh_h16_sat_hh:
15030 case Hexagon::A2_subh_h16_sat_hl:
15031 case Hexagon::A2_subh_h16_sat_lh:
15032 case Hexagon::A2_subh_h16_sat_ll:
15033 case Hexagon::A2_subh_l16_hl:
15034 case Hexagon::A2_subh_l16_ll:
15035 case Hexagon::A2_subh_l16_sat_hl:
15036 case Hexagon::A2_subh_l16_sat_ll:
15037 case Hexagon::A2_subsat:
15038 case Hexagon::A2_svnavgh:
15039 case Hexagon::A2_svsubh:
15040 case Hexagon::A2_svsubhs:
15041 case Hexagon::A2_svsubuhs:
15042 case Hexagon::A4_andn:
15043 case Hexagon::A4_orn:
15044 case Hexagon::dep_A2_subsat: {
15045 switch (OpNum) {
15046 case 1:
15047 // op: Rt32
15048 return 8;
15049 case 2:
15050 // op: Rs32
15051 return 16;
15052 case 0:
15053 // op: Rd32
15054 return 0;
15055 }
15056 break;
15057 }
15058 case Hexagon::A2_minp:
15059 case Hexagon::A2_minup:
15060 case Hexagon::A2_subp:
15061 case Hexagon::A2_vmaxb:
15062 case Hexagon::A2_vmaxh:
15063 case Hexagon::A2_vmaxub:
15064 case Hexagon::A2_vmaxuh:
15065 case Hexagon::A2_vmaxuw:
15066 case Hexagon::A2_vmaxw:
15067 case Hexagon::A2_vminb:
15068 case Hexagon::A2_vminh:
15069 case Hexagon::A2_vminub:
15070 case Hexagon::A2_vminuh:
15071 case Hexagon::A2_vminuw:
15072 case Hexagon::A2_vminw:
15073 case Hexagon::A2_vnavgh:
15074 case Hexagon::A2_vnavghcr:
15075 case Hexagon::A2_vnavghr:
15076 case Hexagon::A2_vnavgw:
15077 case Hexagon::A2_vnavgwcr:
15078 case Hexagon::A2_vnavgwr:
15079 case Hexagon::A2_vsubh:
15080 case Hexagon::A2_vsubhs:
15081 case Hexagon::A2_vsubub:
15082 case Hexagon::A2_vsububs:
15083 case Hexagon::A2_vsubuhs:
15084 case Hexagon::A2_vsubw:
15085 case Hexagon::A2_vsubws:
15086 case Hexagon::A4_andnp:
15087 case Hexagon::A4_ornp:
15088 case Hexagon::M2_vabsdiffh:
15089 case Hexagon::M2_vabsdiffw:
15090 case Hexagon::M6_vabsdiffb:
15091 case Hexagon::M6_vabsdiffub:
15092 case Hexagon::S2_shuffob:
15093 case Hexagon::S2_shuffoh: {
15094 switch (OpNum) {
15095 case 1:
15096 // op: Rtt32
15097 return 8;
15098 case 2:
15099 // op: Rss32
15100 return 16;
15101 case 0:
15102 // op: Rdd32
15103 return 0;
15104 }
15105 break;
15106 }
15107 case Hexagon::S2_valignrb: {
15108 switch (OpNum) {
15109 case 1:
15110 // op: Rtt32
15111 return 8;
15112 case 2:
15113 // op: Rss32
15114 return 16;
15115 case 3:
15116 // op: Pu4
15117 return 5;
15118 case 0:
15119 // op: Rdd32
15120 return 0;
15121 }
15122 break;
15123 }
15124 case Hexagon::M4_mpyrr_addr: {
15125 switch (OpNum) {
15126 case 1:
15127 // op: Ru32
15128 return 0;
15129 case 3:
15130 // op: Rs32
15131 return 16;
15132 case 0:
15133 // op: Ry32
15134 return 8;
15135 }
15136 break;
15137 }
15138 case Hexagon::Y2_tfrscrr: {
15139 switch (OpNum) {
15140 case 1:
15141 // op: Ss128
15142 return 16;
15143 case 0:
15144 // op: Rd32
15145 return 0;
15146 }
15147 break;
15148 }
15149 case Hexagon::Y4_tfrscpp: {
15150 switch (OpNum) {
15151 case 1:
15152 // op: Sss128
15153 return 16;
15154 case 0:
15155 // op: Rdd32
15156 return 0;
15157 }
15158 break;
15159 }
15160 case Hexagon::V6_vabs_f8:
15161 case Hexagon::V6_vabs_hf:
15162 case Hexagon::V6_vabs_sf:
15163 case Hexagon::V6_vabsb:
15164 case Hexagon::V6_vabsb_sat:
15165 case Hexagon::V6_vabsh:
15166 case Hexagon::V6_vabsh_sat:
15167 case Hexagon::V6_vabsw:
15168 case Hexagon::V6_vabsw_sat:
15169 case Hexagon::V6_vassign:
15170 case Hexagon::V6_vassign_fp:
15171 case Hexagon::V6_vassign_tmp:
15172 case Hexagon::V6_vcl0h:
15173 case Hexagon::V6_vcl0w:
15174 case Hexagon::V6_vconv_h_hf:
15175 case Hexagon::V6_vconv_hf_h:
15176 case Hexagon::V6_vconv_hf_qf16:
15177 case Hexagon::V6_vconv_sf_qf32:
15178 case Hexagon::V6_vconv_sf_w:
15179 case Hexagon::V6_vconv_w_sf:
15180 case Hexagon::V6_vcvt_h_hf:
15181 case Hexagon::V6_vcvt_hf_h:
15182 case Hexagon::V6_vcvt_hf_uh:
15183 case Hexagon::V6_vcvt_uh_hf:
15184 case Hexagon::V6_vdealb:
15185 case Hexagon::V6_vdealh:
15186 case Hexagon::V6_vfneg_f8:
15187 case Hexagon::V6_vfneg_hf:
15188 case Hexagon::V6_vfneg_sf:
15189 case Hexagon::V6_vnormamth:
15190 case Hexagon::V6_vnormamtw:
15191 case Hexagon::V6_vnot:
15192 case Hexagon::V6_vpopcounth:
15193 case Hexagon::V6_vshuffb:
15194 case Hexagon::V6_vshuffh: {
15195 switch (OpNum) {
15196 case 1:
15197 // op: Vu32
15198 return 8;
15199 case 0:
15200 // op: Vd32
15201 return 0;
15202 }
15203 break;
15204 }
15205 case Hexagon::V6_vcvt2_hf_b:
15206 case Hexagon::V6_vcvt2_hf_ub:
15207 case Hexagon::V6_vcvt_hf_b:
15208 case Hexagon::V6_vcvt_hf_f8:
15209 case Hexagon::V6_vcvt_hf_ub:
15210 case Hexagon::V6_vcvt_sf_hf:
15211 case Hexagon::V6_vsb:
15212 case Hexagon::V6_vsh:
15213 case Hexagon::V6_vunpackb:
15214 case Hexagon::V6_vunpackh:
15215 case Hexagon::V6_vunpackub:
15216 case Hexagon::V6_vunpackuh:
15217 case Hexagon::V6_vzb:
15218 case Hexagon::V6_vzh: {
15219 switch (OpNum) {
15220 case 1:
15221 // op: Vu32
15222 return 8;
15223 case 0:
15224 // op: Vdd32
15225 return 0;
15226 }
15227 break;
15228 }
15229 case Hexagon::V6_extractw: {
15230 switch (OpNum) {
15231 case 1:
15232 // op: Vu32
15233 return 8;
15234 case 2:
15235 // op: Rs32
15236 return 16;
15237 case 0:
15238 // op: Rd32
15239 return 0;
15240 }
15241 break;
15242 }
15243 case Hexagon::V6_vandvrt: {
15244 switch (OpNum) {
15245 case 1:
15246 // op: Vu32
15247 return 8;
15248 case 2:
15249 // op: Rt32
15250 return 16;
15251 case 0:
15252 // op: Qd4
15253 return 0;
15254 }
15255 break;
15256 }
15257 case Hexagon::V6_get_qfext:
15258 case Hexagon::V6_set_qfext:
15259 case Hexagon::V6_vaslh:
15260 case Hexagon::V6_vaslw:
15261 case Hexagon::V6_vasrh:
15262 case Hexagon::V6_vasrw:
15263 case Hexagon::V6_vdmpybus:
15264 case Hexagon::V6_vdmpyhb:
15265 case Hexagon::V6_vdmpyhsat:
15266 case Hexagon::V6_vdmpyhsusat:
15267 case Hexagon::V6_vlsrb:
15268 case Hexagon::V6_vlsrh:
15269 case Hexagon::V6_vlsrw:
15270 case Hexagon::V6_vmpy_rt_hf:
15271 case Hexagon::V6_vmpy_rt_qf16:
15272 case Hexagon::V6_vmpy_rt_sf:
15273 case Hexagon::V6_vmpyhsrs:
15274 case Hexagon::V6_vmpyhss:
15275 case Hexagon::V6_vmpyihb:
15276 case Hexagon::V6_vmpyiwb:
15277 case Hexagon::V6_vmpyiwh:
15278 case Hexagon::V6_vmpyiwub:
15279 case Hexagon::V6_vmpyuhe:
15280 case Hexagon::V6_vrmpybus:
15281 case Hexagon::V6_vrmpyub:
15282 case Hexagon::V6_vror: {
15283 switch (OpNum) {
15284 case 1:
15285 // op: Vu32
15286 return 8;
15287 case 2:
15288 // op: Rt32
15289 return 16;
15290 case 0:
15291 // op: Vd32
15292 return 0;
15293 }
15294 break;
15295 }
15296 case Hexagon::V6_vmpybus:
15297 case Hexagon::V6_vmpyh:
15298 case Hexagon::V6_vmpyub:
15299 case Hexagon::V6_vmpyuh: {
15300 switch (OpNum) {
15301 case 1:
15302 // op: Vu32
15303 return 8;
15304 case 2:
15305 // op: Rt32
15306 return 16;
15307 case 0:
15308 // op: Vdd32
15309 return 0;
15310 }
15311 break;
15312 }
15313 case Hexagon::V6_vrmpyzbb_rt:
15314 case Hexagon::V6_vrmpyzbub_rt:
15315 case Hexagon::V6_vrmpyzcb_rt:
15316 case Hexagon::V6_vrmpyzcbs_rt:
15317 case Hexagon::V6_vrmpyznb_rt: {
15318 switch (OpNum) {
15319 case 1:
15320 // op: Vu32
15321 return 8;
15322 case 2:
15323 // op: Rt8
15324 return 16;
15325 case 0:
15326 // op: Vdddd32
15327 return 0;
15328 }
15329 break;
15330 }
15331 case Hexagon::V6_vlut4: {
15332 switch (OpNum) {
15333 case 1:
15334 // op: Vu32
15335 return 8;
15336 case 2:
15337 // op: Rtt32
15338 return 16;
15339 case 0:
15340 // op: Vd32
15341 return 0;
15342 }
15343 break;
15344 }
15345 case Hexagon::V6_vrmpybub_rtt:
15346 case Hexagon::V6_vrmpyub_rtt: {
15347 switch (OpNum) {
15348 case 1:
15349 // op: Vu32
15350 return 8;
15351 case 2:
15352 // op: Rtt32
15353 return 16;
15354 case 0:
15355 // op: Vdd32
15356 return 0;
15357 }
15358 break;
15359 }
15360 case Hexagon::V6_veqb:
15361 case Hexagon::V6_veqh:
15362 case Hexagon::V6_veqw:
15363 case Hexagon::V6_vgtb:
15364 case Hexagon::V6_vgtbf:
15365 case Hexagon::V6_vgth:
15366 case Hexagon::V6_vgthf:
15367 case Hexagon::V6_vgtsf:
15368 case Hexagon::V6_vgtub:
15369 case Hexagon::V6_vgtuh:
15370 case Hexagon::V6_vgtuw:
15371 case Hexagon::V6_vgtw: {
15372 switch (OpNum) {
15373 case 1:
15374 // op: Vu32
15375 return 8;
15376 case 2:
15377 // op: Vv32
15378 return 16;
15379 case 0:
15380 // op: Qd4
15381 return 0;
15382 }
15383 break;
15384 }
15385 case Hexagon::V6_vabsdiffh:
15386 case Hexagon::V6_vabsdiffub:
15387 case Hexagon::V6_vabsdiffuh:
15388 case Hexagon::V6_vabsdiffw:
15389 case Hexagon::V6_vadd_hf:
15390 case Hexagon::V6_vadd_hf_hf:
15391 case Hexagon::V6_vadd_qf16:
15392 case Hexagon::V6_vadd_qf16_mix:
15393 case Hexagon::V6_vadd_qf32:
15394 case Hexagon::V6_vadd_qf32_mix:
15395 case Hexagon::V6_vadd_sf:
15396 case Hexagon::V6_vadd_sf_sf:
15397 case Hexagon::V6_vaddb:
15398 case Hexagon::V6_vaddbsat:
15399 case Hexagon::V6_vaddclbh:
15400 case Hexagon::V6_vaddclbw:
15401 case Hexagon::V6_vaddh:
15402 case Hexagon::V6_vaddhsat:
15403 case Hexagon::V6_vaddubsat:
15404 case Hexagon::V6_vaddububb_sat:
15405 case Hexagon::V6_vadduhsat:
15406 case Hexagon::V6_vadduwsat:
15407 case Hexagon::V6_vaddw:
15408 case Hexagon::V6_vaddwsat:
15409 case Hexagon::V6_vand:
15410 case Hexagon::V6_vaslhv:
15411 case Hexagon::V6_vaslwv:
15412 case Hexagon::V6_vasrhv:
15413 case Hexagon::V6_vasrwv:
15414 case Hexagon::V6_vavgb:
15415 case Hexagon::V6_vavgbrnd:
15416 case Hexagon::V6_vavgh:
15417 case Hexagon::V6_vavghrnd:
15418 case Hexagon::V6_vavgub:
15419 case Hexagon::V6_vavgubrnd:
15420 case Hexagon::V6_vavguh:
15421 case Hexagon::V6_vavguhrnd:
15422 case Hexagon::V6_vavguw:
15423 case Hexagon::V6_vavguwrnd:
15424 case Hexagon::V6_vavgw:
15425 case Hexagon::V6_vavgwrnd:
15426 case Hexagon::V6_vcvt2_b_hf:
15427 case Hexagon::V6_vcvt2_ub_hf:
15428 case Hexagon::V6_vcvt_b_hf:
15429 case Hexagon::V6_vcvt_bf_sf:
15430 case Hexagon::V6_vcvt_f8_hf:
15431 case Hexagon::V6_vcvt_hf_sf:
15432 case Hexagon::V6_vcvt_ub_hf:
15433 case Hexagon::V6_vdealb4w:
15434 case Hexagon::V6_vdelta:
15435 case Hexagon::V6_vdmpy_sf_hf:
15436 case Hexagon::V6_vdmpyhvsat:
15437 case Hexagon::V6_vfmax_f8:
15438 case Hexagon::V6_vfmax_hf:
15439 case Hexagon::V6_vfmax_sf:
15440 case Hexagon::V6_vfmin_f8:
15441 case Hexagon::V6_vfmin_hf:
15442 case Hexagon::V6_vfmin_sf:
15443 case Hexagon::V6_vlsrhv:
15444 case Hexagon::V6_vlsrwv:
15445 case Hexagon::V6_vmax_bf:
15446 case Hexagon::V6_vmax_hf:
15447 case Hexagon::V6_vmax_sf:
15448 case Hexagon::V6_vmaxb:
15449 case Hexagon::V6_vmaxh:
15450 case Hexagon::V6_vmaxub:
15451 case Hexagon::V6_vmaxuh:
15452 case Hexagon::V6_vmaxw:
15453 case Hexagon::V6_vmerge_qf:
15454 case Hexagon::V6_vmin_bf:
15455 case Hexagon::V6_vmin_hf:
15456 case Hexagon::V6_vmin_sf:
15457 case Hexagon::V6_vminb:
15458 case Hexagon::V6_vminh:
15459 case Hexagon::V6_vminub:
15460 case Hexagon::V6_vminuh:
15461 case Hexagon::V6_vminw:
15462 case Hexagon::V6_vmpy_hf_hf:
15463 case Hexagon::V6_vmpy_qf16:
15464 case Hexagon::V6_vmpy_qf16_hf:
15465 case Hexagon::V6_vmpy_qf16_mix_hf:
15466 case Hexagon::V6_vmpy_qf32:
15467 case Hexagon::V6_vmpy_qf32_sf:
15468 case Hexagon::V6_vmpy_sf_sf:
15469 case Hexagon::V6_vmpyewuh:
15470 case Hexagon::V6_vmpyhvsrs:
15471 case Hexagon::V6_vmpyieoh:
15472 case Hexagon::V6_vmpyiewuh:
15473 case Hexagon::V6_vmpyih:
15474 case Hexagon::V6_vmpyiowh:
15475 case Hexagon::V6_vmpyowh:
15476 case Hexagon::V6_vmpyowh_rnd:
15477 case Hexagon::V6_vmpyuhvs:
15478 case Hexagon::V6_vnavgb:
15479 case Hexagon::V6_vnavgh:
15480 case Hexagon::V6_vnavgub:
15481 case Hexagon::V6_vnavgw:
15482 case Hexagon::V6_vor:
15483 case Hexagon::V6_vpackeb:
15484 case Hexagon::V6_vpackeh:
15485 case Hexagon::V6_vpackhb_sat:
15486 case Hexagon::V6_vpackhub_sat:
15487 case Hexagon::V6_vpackob:
15488 case Hexagon::V6_vpackoh:
15489 case Hexagon::V6_vpackwh_sat:
15490 case Hexagon::V6_vpackwuh_sat:
15491 case Hexagon::V6_vrdelta:
15492 case Hexagon::V6_vrmpybusv:
15493 case Hexagon::V6_vrmpybv:
15494 case Hexagon::V6_vrmpyubv:
15495 case Hexagon::V6_vrotr:
15496 case Hexagon::V6_vroundhb:
15497 case Hexagon::V6_vroundhub:
15498 case Hexagon::V6_vrounduhub:
15499 case Hexagon::V6_vrounduwuh:
15500 case Hexagon::V6_vroundwh:
15501 case Hexagon::V6_vroundwuh:
15502 case Hexagon::V6_vsatdw:
15503 case Hexagon::V6_vsathub:
15504 case Hexagon::V6_vsatuwuh:
15505 case Hexagon::V6_vsatwh:
15506 case Hexagon::V6_vshufeh:
15507 case Hexagon::V6_vshuffeb:
15508 case Hexagon::V6_vshuffob:
15509 case Hexagon::V6_vshufoh:
15510 case Hexagon::V6_vsub_hf:
15511 case Hexagon::V6_vsub_hf_hf:
15512 case Hexagon::V6_vsub_qf16:
15513 case Hexagon::V6_vsub_qf16_mix:
15514 case Hexagon::V6_vsub_qf32:
15515 case Hexagon::V6_vsub_qf32_mix:
15516 case Hexagon::V6_vsub_sf:
15517 case Hexagon::V6_vsub_sf_sf:
15518 case Hexagon::V6_vsubb:
15519 case Hexagon::V6_vsubbsat:
15520 case Hexagon::V6_vsubh:
15521 case Hexagon::V6_vsubhsat:
15522 case Hexagon::V6_vsububsat:
15523 case Hexagon::V6_vsubububb_sat:
15524 case Hexagon::V6_vsubuhsat:
15525 case Hexagon::V6_vsubuwsat:
15526 case Hexagon::V6_vsubw:
15527 case Hexagon::V6_vsubwsat:
15528 case Hexagon::V6_vxor: {
15529 switch (OpNum) {
15530 case 1:
15531 // op: Vu32
15532 return 8;
15533 case 2:
15534 // op: Vv32
15535 return 16;
15536 case 0:
15537 // op: Vd32
15538 return 0;
15539 }
15540 break;
15541 }
15542 case Hexagon::V6_vadd_hf_f8:
15543 case Hexagon::V6_vadd_sf_bf:
15544 case Hexagon::V6_vadd_sf_hf:
15545 case Hexagon::V6_vaddhw:
15546 case Hexagon::V6_vaddubh:
15547 case Hexagon::V6_vadduhw:
15548 case Hexagon::V6_vcombine:
15549 case Hexagon::V6_vcombine_tmp:
15550 case Hexagon::V6_vmpy_hf_f8:
15551 case Hexagon::V6_vmpy_qf32_hf:
15552 case Hexagon::V6_vmpy_qf32_mix_hf:
15553 case Hexagon::V6_vmpy_qf32_qf16:
15554 case Hexagon::V6_vmpy_sf_bf:
15555 case Hexagon::V6_vmpy_sf_hf:
15556 case Hexagon::V6_vmpybusv:
15557 case Hexagon::V6_vmpybv:
15558 case Hexagon::V6_vmpyewuh_64:
15559 case Hexagon::V6_vmpyhus:
15560 case Hexagon::V6_vmpyhv:
15561 case Hexagon::V6_vmpyubv:
15562 case Hexagon::V6_vmpyuhv:
15563 case Hexagon::V6_vshufoeb:
15564 case Hexagon::V6_vshufoeh:
15565 case Hexagon::V6_vsub_hf_f8:
15566 case Hexagon::V6_vsub_sf_bf:
15567 case Hexagon::V6_vsub_sf_hf:
15568 case Hexagon::V6_vsubhw:
15569 case Hexagon::V6_vsububh:
15570 case Hexagon::V6_vsubuhw: {
15571 switch (OpNum) {
15572 case 1:
15573 // op: Vu32
15574 return 8;
15575 case 2:
15576 // op: Vv32
15577 return 16;
15578 case 0:
15579 // op: Vdd32
15580 return 0;
15581 }
15582 break;
15583 }
15584 case Hexagon::V6_vaddcarrysat: {
15585 switch (OpNum) {
15586 case 1:
15587 // op: Vu32
15588 return 8;
15589 case 2:
15590 // op: Vv32
15591 return 16;
15592 case 3:
15593 // op: Qs4
15594 return 5;
15595 case 0:
15596 // op: Vd32
15597 return 0;
15598 }
15599 break;
15600 }
15601 case Hexagon::V6_valignb:
15602 case Hexagon::V6_vasrhbrndsat:
15603 case Hexagon::V6_vasrhbsat:
15604 case Hexagon::V6_vasrhubrndsat:
15605 case Hexagon::V6_vasrhubsat:
15606 case Hexagon::V6_vasruhubrndsat:
15607 case Hexagon::V6_vasruhubsat:
15608 case Hexagon::V6_vasruwuhrndsat:
15609 case Hexagon::V6_vasruwuhsat:
15610 case Hexagon::V6_vasrwh:
15611 case Hexagon::V6_vasrwhrndsat:
15612 case Hexagon::V6_vasrwhsat:
15613 case Hexagon::V6_vasrwuhrndsat:
15614 case Hexagon::V6_vasrwuhsat:
15615 case Hexagon::V6_vlalignb:
15616 case Hexagon::V6_vlutvvb:
15617 case Hexagon::V6_vlutvvb_nm: {
15618 switch (OpNum) {
15619 case 1:
15620 // op: Vu32
15621 return 8;
15622 case 2:
15623 // op: Vv32
15624 return 19;
15625 case 3:
15626 // op: Rt8
15627 return 16;
15628 case 0:
15629 // op: Vd32
15630 return 0;
15631 }
15632 break;
15633 }
15634 case Hexagon::V6_vdealvdd:
15635 case Hexagon::V6_vlutvwh:
15636 case Hexagon::V6_vlutvwh_nm:
15637 case Hexagon::V6_vshuffvdd: {
15638 switch (OpNum) {
15639 case 1:
15640 // op: Vu32
15641 return 8;
15642 case 2:
15643 // op: Vv32
15644 return 19;
15645 case 3:
15646 // op: Rt8
15647 return 16;
15648 case 0:
15649 // op: Vdd32
15650 return 0;
15651 }
15652 break;
15653 }
15654 case Hexagon::V6_vconv_hf_qf32: {
15655 switch (OpNum) {
15656 case 1:
15657 // op: Vuu32
15658 return 8;
15659 case 0:
15660 // op: Vd32
15661 return 0;
15662 }
15663 break;
15664 }
15665 case Hexagon::V6_vdmpyhisat:
15666 case Hexagon::V6_vdmpyhsuisat: {
15667 switch (OpNum) {
15668 case 1:
15669 // op: Vuu32
15670 return 8;
15671 case 2:
15672 // op: Rt32
15673 return 16;
15674 case 0:
15675 // op: Vd32
15676 return 0;
15677 }
15678 break;
15679 }
15680 case Hexagon::V6_vdmpybus_dv:
15681 case Hexagon::V6_vdmpyhb_dv:
15682 case Hexagon::V6_vdsaduh:
15683 case Hexagon::V6_vmpabus:
15684 case Hexagon::V6_vmpabuu:
15685 case Hexagon::V6_vmpahb:
15686 case Hexagon::V6_vmpauhb:
15687 case Hexagon::V6_vtmpyb:
15688 case Hexagon::V6_vtmpybus:
15689 case Hexagon::V6_vtmpyhb: {
15690 switch (OpNum) {
15691 case 1:
15692 // op: Vuu32
15693 return 8;
15694 case 2:
15695 // op: Rt32
15696 return 16;
15697 case 0:
15698 // op: Vdd32
15699 return 0;
15700 }
15701 break;
15702 }
15703 case Hexagon::V6_vasrvuhubrndsat:
15704 case Hexagon::V6_vasrvuhubsat:
15705 case Hexagon::V6_vasrvwuhrndsat:
15706 case Hexagon::V6_vasrvwuhsat: {
15707 switch (OpNum) {
15708 case 1:
15709 // op: Vuu32
15710 return 8;
15711 case 2:
15712 // op: Vv32
15713 return 16;
15714 case 0:
15715 // op: Vd32
15716 return 0;
15717 }
15718 break;
15719 }
15720 case Hexagon::V6_vaddb_dv:
15721 case Hexagon::V6_vaddbsat_dv:
15722 case Hexagon::V6_vaddh_dv:
15723 case Hexagon::V6_vaddhsat_dv:
15724 case Hexagon::V6_vaddubsat_dv:
15725 case Hexagon::V6_vadduhsat_dv:
15726 case Hexagon::V6_vadduwsat_dv:
15727 case Hexagon::V6_vaddw_dv:
15728 case Hexagon::V6_vaddwsat_dv:
15729 case Hexagon::V6_vmpabusv:
15730 case Hexagon::V6_vmpabuuv:
15731 case Hexagon::V6_vsubb_dv:
15732 case Hexagon::V6_vsubbsat_dv:
15733 case Hexagon::V6_vsubh_dv:
15734 case Hexagon::V6_vsubhsat_dv:
15735 case Hexagon::V6_vsububsat_dv:
15736 case Hexagon::V6_vsubuhsat_dv:
15737 case Hexagon::V6_vsubuwsat_dv:
15738 case Hexagon::V6_vsubw_dv:
15739 case Hexagon::V6_vsubwsat_dv: {
15740 switch (OpNum) {
15741 case 1:
15742 // op: Vuu32
15743 return 8;
15744 case 2:
15745 // op: Vvv32
15746 return 16;
15747 case 0:
15748 // op: Vdd32
15749 return 0;
15750 }
15751 break;
15752 }
15753 case Hexagon::L4_loadbsw2_ap:
15754 case Hexagon::L4_loadbzw2_ap:
15755 case Hexagon::L4_loadrb_ap:
15756 case Hexagon::L4_loadrh_ap:
15757 case Hexagon::L4_loadri_ap:
15758 case Hexagon::L4_loadrub_ap:
15759 case Hexagon::L4_loadruh_ap: {
15760 switch (OpNum) {
15761 case 2:
15762 // op: II
15763 return 5;
15764 case 0:
15765 // op: Rd32
15766 return 0;
15767 case 1:
15768 // op: Re32
15769 return 16;
15770 }
15771 break;
15772 }
15773 case Hexagon::L4_loadbsw4_ap:
15774 case Hexagon::L4_loadbzw4_ap:
15775 case Hexagon::L4_loadrd_ap: {
15776 switch (OpNum) {
15777 case 2:
15778 // op: II
15779 return 5;
15780 case 0:
15781 // op: Rdd32
15782 return 0;
15783 case 1:
15784 // op: Re32
15785 return 16;
15786 }
15787 break;
15788 }
15789 case Hexagon::A2_tfrih:
15790 case Hexagon::A2_tfril:
15791 case Hexagon::S2_allocframe: {
15792 switch (OpNum) {
15793 case 2:
15794 // op: Ii
15795 return 0;
15796 case 0:
15797 // op: Rx32
15798 return 16;
15799 }
15800 break;
15801 }
15802 case Hexagon::J4_cmpeq_f_jumpnv_nt:
15803 case Hexagon::J4_cmpeq_f_jumpnv_t:
15804 case Hexagon::J4_cmpeq_t_jumpnv_nt:
15805 case Hexagon::J4_cmpeq_t_jumpnv_t:
15806 case Hexagon::J4_cmpgt_f_jumpnv_nt:
15807 case Hexagon::J4_cmpgt_f_jumpnv_t:
15808 case Hexagon::J4_cmpgt_t_jumpnv_nt:
15809 case Hexagon::J4_cmpgt_t_jumpnv_t:
15810 case Hexagon::J4_cmpgtu_f_jumpnv_nt:
15811 case Hexagon::J4_cmpgtu_f_jumpnv_t:
15812 case Hexagon::J4_cmpgtu_t_jumpnv_nt:
15813 case Hexagon::J4_cmpgtu_t_jumpnv_t: {
15814 switch (OpNum) {
15815 case 2:
15816 // op: Ii
15817 return 1;
15818 case 0:
15819 // op: Ns8
15820 return 16;
15821 case 1:
15822 // op: Rt32
15823 return 8;
15824 }
15825 break;
15826 }
15827 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
15828 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
15829 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
15830 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
15831 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
15832 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
15833 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
15834 case Hexagon::J4_cmpgtn1_t_jumpnv_t: {
15835 switch (OpNum) {
15836 case 2:
15837 // op: Ii
15838 return 1;
15839 case 0:
15840 // op: Ns8
15841 return 16;
15842 }
15843 break;
15844 }
15845 case Hexagon::J4_cmpeq_fp0_jump_nt:
15846 case Hexagon::J4_cmpeq_fp0_jump_t:
15847 case Hexagon::J4_cmpeq_fp1_jump_nt:
15848 case Hexagon::J4_cmpeq_fp1_jump_t:
15849 case Hexagon::J4_cmpeq_tp0_jump_nt:
15850 case Hexagon::J4_cmpeq_tp0_jump_t:
15851 case Hexagon::J4_cmpeq_tp1_jump_nt:
15852 case Hexagon::J4_cmpeq_tp1_jump_t:
15853 case Hexagon::J4_cmpgt_fp0_jump_nt:
15854 case Hexagon::J4_cmpgt_fp0_jump_t:
15855 case Hexagon::J4_cmpgt_fp1_jump_nt:
15856 case Hexagon::J4_cmpgt_fp1_jump_t:
15857 case Hexagon::J4_cmpgt_tp0_jump_nt:
15858 case Hexagon::J4_cmpgt_tp0_jump_t:
15859 case Hexagon::J4_cmpgt_tp1_jump_nt:
15860 case Hexagon::J4_cmpgt_tp1_jump_t:
15861 case Hexagon::J4_cmpgtu_fp0_jump_nt:
15862 case Hexagon::J4_cmpgtu_fp0_jump_t:
15863 case Hexagon::J4_cmpgtu_fp1_jump_nt:
15864 case Hexagon::J4_cmpgtu_fp1_jump_t:
15865 case Hexagon::J4_cmpgtu_tp0_jump_nt:
15866 case Hexagon::J4_cmpgtu_tp0_jump_t:
15867 case Hexagon::J4_cmpgtu_tp1_jump_nt:
15868 case Hexagon::J4_cmpgtu_tp1_jump_t: {
15869 switch (OpNum) {
15870 case 2:
15871 // op: Ii
15872 return 1;
15873 case 0:
15874 // op: Rs16
15875 return 16;
15876 case 1:
15877 // op: Rt16
15878 return 8;
15879 }
15880 break;
15881 }
15882 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
15883 case Hexagon::J4_cmpeqn1_fp0_jump_t:
15884 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
15885 case Hexagon::J4_cmpeqn1_fp1_jump_t:
15886 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
15887 case Hexagon::J4_cmpeqn1_tp0_jump_t:
15888 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
15889 case Hexagon::J4_cmpeqn1_tp1_jump_t:
15890 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
15891 case Hexagon::J4_cmpgtn1_fp0_jump_t:
15892 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
15893 case Hexagon::J4_cmpgtn1_fp1_jump_t:
15894 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
15895 case Hexagon::J4_cmpgtn1_tp0_jump_t:
15896 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
15897 case Hexagon::J4_cmpgtn1_tp1_jump_t: {
15898 switch (OpNum) {
15899 case 2:
15900 // op: Ii
15901 return 1;
15902 case 0:
15903 // op: Rs16
15904 return 16;
15905 }
15906 break;
15907 }
15908 case Hexagon::J4_cmplt_f_jumpnv_nt:
15909 case Hexagon::J4_cmplt_f_jumpnv_t:
15910 case Hexagon::J4_cmplt_t_jumpnv_nt:
15911 case Hexagon::J4_cmplt_t_jumpnv_t:
15912 case Hexagon::J4_cmpltu_f_jumpnv_nt:
15913 case Hexagon::J4_cmpltu_f_jumpnv_t:
15914 case Hexagon::J4_cmpltu_t_jumpnv_nt:
15915 case Hexagon::J4_cmpltu_t_jumpnv_t: {
15916 switch (OpNum) {
15917 case 2:
15918 // op: Ii
15919 return 1;
15920 case 0:
15921 // op: Rt32
15922 return 8;
15923 case 1:
15924 // op: Ns8
15925 return 16;
15926 }
15927 break;
15928 }
15929 case Hexagon::J4_jumpsetr: {
15930 switch (OpNum) {
15931 case 2:
15932 // op: Ii
15933 return 1;
15934 case 1:
15935 // op: Rs16
15936 return 16;
15937 case 0:
15938 // op: Rd16
15939 return 8;
15940 }
15941 break;
15942 }
15943 case Hexagon::J2_trap1: {
15944 switch (OpNum) {
15945 case 2:
15946 // op: Ii
15947 return 2;
15948 case 0:
15949 // op: Rx32
15950 return 16;
15951 }
15952 break;
15953 }
15954 case Hexagon::S2_pstorerbnewf_io:
15955 case Hexagon::S2_pstorerbnewt_io:
15956 case Hexagon::S2_pstorerhnewf_io:
15957 case Hexagon::S2_pstorerhnewt_io:
15958 case Hexagon::S2_pstorerinewf_io:
15959 case Hexagon::S2_pstorerinewt_io:
15960 case Hexagon::S4_pstorerbnewfnew_io:
15961 case Hexagon::S4_pstorerbnewtnew_io:
15962 case Hexagon::S4_pstorerhnewfnew_io:
15963 case Hexagon::S4_pstorerhnewtnew_io:
15964 case Hexagon::S4_pstorerinewfnew_io:
15965 case Hexagon::S4_pstorerinewtnew_io: {
15966 switch (OpNum) {
15967 case 2:
15968 // op: Ii
15969 return 3;
15970 case 0:
15971 // op: Pv4
15972 return 0;
15973 case 1:
15974 // op: Rs32
15975 return 16;
15976 case 3:
15977 // op: Nt8
15978 return 8;
15979 }
15980 break;
15981 }
15982 case Hexagon::S2_pstorerbf_io:
15983 case Hexagon::S2_pstorerbt_io:
15984 case Hexagon::S2_pstorerff_io:
15985 case Hexagon::S2_pstorerft_io:
15986 case Hexagon::S2_pstorerhf_io:
15987 case Hexagon::S2_pstorerht_io:
15988 case Hexagon::S2_pstorerif_io:
15989 case Hexagon::S2_pstorerit_io:
15990 case Hexagon::S4_pstorerbfnew_io:
15991 case Hexagon::S4_pstorerbtnew_io:
15992 case Hexagon::S4_pstorerffnew_io:
15993 case Hexagon::S4_pstorerftnew_io:
15994 case Hexagon::S4_pstorerhfnew_io:
15995 case Hexagon::S4_pstorerhtnew_io:
15996 case Hexagon::S4_pstorerifnew_io:
15997 case Hexagon::S4_pstoreritnew_io: {
15998 switch (OpNum) {
15999 case 2:
16000 // op: Ii
16001 return 3;
16002 case 0:
16003 // op: Pv4
16004 return 0;
16005 case 1:
16006 // op: Rs32
16007 return 16;
16008 case 3:
16009 // op: Rt32
16010 return 8;
16011 }
16012 break;
16013 }
16014 case Hexagon::S2_pstorerdf_io:
16015 case Hexagon::S2_pstorerdt_io:
16016 case Hexagon::S4_pstorerdfnew_io:
16017 case Hexagon::S4_pstorerdtnew_io: {
16018 switch (OpNum) {
16019 case 2:
16020 // op: Ii
16021 return 3;
16022 case 0:
16023 // op: Pv4
16024 return 0;
16025 case 1:
16026 // op: Rs32
16027 return 16;
16028 case 3:
16029 // op: Rtt32
16030 return 8;
16031 }
16032 break;
16033 }
16034 case Hexagon::S2_storerbnew_pci:
16035 case Hexagon::S2_storerhnew_pci:
16036 case Hexagon::S2_storerinew_pci: {
16037 switch (OpNum) {
16038 case 2:
16039 // op: Ii
16040 return 3;
16041 case 3:
16042 // op: Mu2
16043 return 13;
16044 case 4:
16045 // op: Nt8
16046 return 8;
16047 case 0:
16048 // op: Rx32
16049 return 16;
16050 }
16051 break;
16052 }
16053 case Hexagon::S2_storerb_pci:
16054 case Hexagon::S2_storerf_pci:
16055 case Hexagon::S2_storerh_pci:
16056 case Hexagon::S2_storeri_pci: {
16057 switch (OpNum) {
16058 case 2:
16059 // op: Ii
16060 return 3;
16061 case 3:
16062 // op: Mu2
16063 return 13;
16064 case 4:
16065 // op: Rt32
16066 return 8;
16067 case 0:
16068 // op: Rx32
16069 return 16;
16070 }
16071 break;
16072 }
16073 case Hexagon::S2_storerd_pci: {
16074 switch (OpNum) {
16075 case 2:
16076 // op: Ii
16077 return 3;
16078 case 3:
16079 // op: Mu2
16080 return 13;
16081 case 4:
16082 // op: Rtt32
16083 return 8;
16084 case 0:
16085 // op: Rx32
16086 return 16;
16087 }
16088 break;
16089 }
16090 case Hexagon::S2_storerbnew_pi:
16091 case Hexagon::S2_storerhnew_pi:
16092 case Hexagon::S2_storerinew_pi: {
16093 switch (OpNum) {
16094 case 2:
16095 // op: Ii
16096 return 3;
16097 case 3:
16098 // op: Nt8
16099 return 8;
16100 case 0:
16101 // op: Rx32
16102 return 16;
16103 }
16104 break;
16105 }
16106 case Hexagon::S2_storerb_pi:
16107 case Hexagon::S2_storerf_pi:
16108 case Hexagon::S2_storerh_pi:
16109 case Hexagon::S2_storeri_pi: {
16110 switch (OpNum) {
16111 case 2:
16112 // op: Ii
16113 return 3;
16114 case 3:
16115 // op: Rt32
16116 return 8;
16117 case 0:
16118 // op: Rx32
16119 return 16;
16120 }
16121 break;
16122 }
16123 case Hexagon::S2_storerd_pi: {
16124 switch (OpNum) {
16125 case 2:
16126 // op: Ii
16127 return 3;
16128 case 3:
16129 // op: Rtt32
16130 return 8;
16131 case 0:
16132 // op: Rx32
16133 return 16;
16134 }
16135 break;
16136 }
16137 case Hexagon::SA1_addi: {
16138 switch (OpNum) {
16139 case 2:
16140 // op: Ii
16141 return 4;
16142 case 0:
16143 // op: Rx16
16144 return 0;
16145 }
16146 break;
16147 }
16148 case Hexagon::C2_cmoveif:
16149 case Hexagon::C2_cmoveit:
16150 case Hexagon::C2_cmovenewif:
16151 case Hexagon::C2_cmovenewit: {
16152 switch (OpNum) {
16153 case 2:
16154 // op: Ii
16155 return 5;
16156 case 1:
16157 // op: Pu4
16158 return 21;
16159 case 0:
16160 // op: Rd32
16161 return 0;
16162 }
16163 break;
16164 }
16165 case Hexagon::C2_muxri: {
16166 switch (OpNum) {
16167 case 2:
16168 // op: Ii
16169 return 5;
16170 case 1:
16171 // op: Pu4
16172 return 21;
16173 case 3:
16174 // op: Rs32
16175 return 16;
16176 case 0:
16177 // op: Rd32
16178 return 0;
16179 }
16180 break;
16181 }
16182 case Hexagon::A4_cmpbeqi:
16183 case Hexagon::A4_cmpbgti:
16184 case Hexagon::A4_cmpbgtui:
16185 case Hexagon::A4_cmpheqi:
16186 case Hexagon::A4_cmphgti:
16187 case Hexagon::A4_cmphgtui:
16188 case Hexagon::C2_cmpeqi:
16189 case Hexagon::C2_cmpgti:
16190 case Hexagon::C2_cmpgtui:
16191 case Hexagon::C4_cmpltei:
16192 case Hexagon::C4_cmplteui:
16193 case Hexagon::C4_cmpneqi: {
16194 switch (OpNum) {
16195 case 2:
16196 // op: Ii
16197 return 5;
16198 case 1:
16199 // op: Rs32
16200 return 16;
16201 case 0:
16202 // op: Pd4
16203 return 0;
16204 }
16205 break;
16206 }
16207 case Hexagon::A2_addi:
16208 case Hexagon::A2_andir:
16209 case Hexagon::A2_orir:
16210 case Hexagon::A4_rcmpeqi:
16211 case Hexagon::A4_rcmpneqi:
16212 case Hexagon::L2_loadbsw2_io:
16213 case Hexagon::L2_loadbzw2_io:
16214 case Hexagon::L2_loadrb_io:
16215 case Hexagon::L2_loadrh_io:
16216 case Hexagon::L2_loadri_io:
16217 case Hexagon::L2_loadrub_io:
16218 case Hexagon::L2_loadruh_io:
16219 case Hexagon::M2_mpysin:
16220 case Hexagon::M2_mpysip: {
16221 switch (OpNum) {
16222 case 2:
16223 // op: Ii
16224 return 5;
16225 case 1:
16226 // op: Rs32
16227 return 16;
16228 case 0:
16229 // op: Rd32
16230 return 0;
16231 }
16232 break;
16233 }
16234 case Hexagon::A4_combineri:
16235 case Hexagon::L2_loadbsw4_io:
16236 case Hexagon::L2_loadbzw4_io:
16237 case Hexagon::L2_loadrd_io: {
16238 switch (OpNum) {
16239 case 2:
16240 // op: Ii
16241 return 5;
16242 case 1:
16243 // op: Rs32
16244 return 16;
16245 case 0:
16246 // op: Rdd32
16247 return 0;
16248 }
16249 break;
16250 }
16251 case Hexagon::S4_subaddi: {
16252 switch (OpNum) {
16253 case 2:
16254 // op: Ii
16255 return 5;
16256 case 1:
16257 // op: Rs32
16258 return 16;
16259 case 3:
16260 // op: Ru32
16261 return 0;
16262 case 0:
16263 // op: Rd32
16264 return 8;
16265 }
16266 break;
16267 }
16268 case Hexagon::A4_vcmpbeqi:
16269 case Hexagon::A4_vcmpbgti:
16270 case Hexagon::A4_vcmpbgtui:
16271 case Hexagon::A4_vcmpheqi:
16272 case Hexagon::A4_vcmphgti:
16273 case Hexagon::A4_vcmphgtui:
16274 case Hexagon::A4_vcmpweqi:
16275 case Hexagon::A4_vcmpwgti:
16276 case Hexagon::A4_vcmpwgtui:
16277 case Hexagon::F2_dfclass: {
16278 switch (OpNum) {
16279 case 2:
16280 // op: Ii
16281 return 5;
16282 case 1:
16283 // op: Rss32
16284 return 16;
16285 case 0:
16286 // op: Pd4
16287 return 0;
16288 }
16289 break;
16290 }
16291 case Hexagon::M4_mpyri_addr_u2: {
16292 switch (OpNum) {
16293 case 2:
16294 // op: Ii
16295 return 5;
16296 case 1:
16297 // op: Ru32
16298 return 0;
16299 case 3:
16300 // op: Rs32
16301 return 16;
16302 case 0:
16303 // op: Rd32
16304 return 8;
16305 }
16306 break;
16307 }
16308 case Hexagon::C2_muxii: {
16309 switch (OpNum) {
16310 case 2:
16311 // op: Ii
16312 return 5;
16313 case 3:
16314 // op: II
16315 return 13;
16316 case 1:
16317 // op: Pu4
16318 return 23;
16319 case 0:
16320 // op: Rd32
16321 return 0;
16322 }
16323 break;
16324 }
16325 case Hexagon::S4_storerbnew_rr:
16326 case Hexagon::S4_storerhnew_rr:
16327 case Hexagon::S4_storerinew_rr: {
16328 switch (OpNum) {
16329 case 2:
16330 // op: Ii
16331 return 7;
16332 case 0:
16333 // op: Rs32
16334 return 16;
16335 case 1:
16336 // op: Ru32
16337 return 8;
16338 case 3:
16339 // op: Nt8
16340 return 0;
16341 }
16342 break;
16343 }
16344 case Hexagon::S4_storerb_rr:
16345 case Hexagon::S4_storerf_rr:
16346 case Hexagon::S4_storerh_rr:
16347 case Hexagon::S4_storeri_rr: {
16348 switch (OpNum) {
16349 case 2:
16350 // op: Ii
16351 return 7;
16352 case 0:
16353 // op: Rs32
16354 return 16;
16355 case 1:
16356 // op: Ru32
16357 return 8;
16358 case 3:
16359 // op: Rt32
16360 return 0;
16361 }
16362 break;
16363 }
16364 case Hexagon::S4_storerd_rr: {
16365 switch (OpNum) {
16366 case 2:
16367 // op: Ii
16368 return 7;
16369 case 0:
16370 // op: Rs32
16371 return 16;
16372 case 1:
16373 // op: Ru32
16374 return 8;
16375 case 3:
16376 // op: Rtt32
16377 return 0;
16378 }
16379 break;
16380 }
16381 case Hexagon::S4_storeirbf_io:
16382 case Hexagon::S4_storeirbfnew_io:
16383 case Hexagon::S4_storeirbt_io:
16384 case Hexagon::S4_storeirbtnew_io:
16385 case Hexagon::S4_storeirhf_io:
16386 case Hexagon::S4_storeirhfnew_io:
16387 case Hexagon::S4_storeirht_io:
16388 case Hexagon::S4_storeirhtnew_io:
16389 case Hexagon::S4_storeirif_io:
16390 case Hexagon::S4_storeirifnew_io:
16391 case Hexagon::S4_storeirit_io:
16392 case Hexagon::S4_storeiritnew_io: {
16393 switch (OpNum) {
16394 case 2:
16395 // op: Ii
16396 return 7;
16397 case 3:
16398 // op: II
16399 return 0;
16400 case 0:
16401 // op: Pv4
16402 return 5;
16403 case 1:
16404 // op: Rs32
16405 return 16;
16406 }
16407 break;
16408 }
16409 case Hexagon::L4_loadbsw2_ur:
16410 case Hexagon::L4_loadbzw2_ur:
16411 case Hexagon::L4_loadrb_ur:
16412 case Hexagon::L4_loadrh_ur:
16413 case Hexagon::L4_loadri_ur:
16414 case Hexagon::L4_loadrub_ur:
16415 case Hexagon::L4_loadruh_ur: {
16416 switch (OpNum) {
16417 case 2:
16418 // op: Ii
16419 return 7;
16420 case 3:
16421 // op: II
16422 return 5;
16423 case 1:
16424 // op: Rt32
16425 return 16;
16426 case 0:
16427 // op: Rd32
16428 return 0;
16429 }
16430 break;
16431 }
16432 case Hexagon::L4_loadbsw4_ur:
16433 case Hexagon::L4_loadbzw4_ur:
16434 case Hexagon::L4_loadrd_ur: {
16435 switch (OpNum) {
16436 case 2:
16437 // op: Ii
16438 return 7;
16439 case 3:
16440 // op: II
16441 return 5;
16442 case 1:
16443 // op: Rt32
16444 return 16;
16445 case 0:
16446 // op: Rdd32
16447 return 0;
16448 }
16449 break;
16450 }
16451 case Hexagon::V6_vS32b_new_npred_ai:
16452 case Hexagon::V6_vS32b_new_pred_ai:
16453 case Hexagon::V6_vS32b_nt_new_npred_ai:
16454 case Hexagon::V6_vS32b_nt_new_pred_ai: {
16455 switch (OpNum) {
16456 case 2:
16457 // op: Ii
16458 return 8;
16459 case 0:
16460 // op: Pv4
16461 return 11;
16462 case 1:
16463 // op: Rt32
16464 return 16;
16465 case 3:
16466 // op: Os8
16467 return 0;
16468 }
16469 break;
16470 }
16471 case Hexagon::V6_vS32Ub_npred_ai:
16472 case Hexagon::V6_vS32Ub_pred_ai:
16473 case Hexagon::V6_vS32b_npred_ai:
16474 case Hexagon::V6_vS32b_nt_npred_ai:
16475 case Hexagon::V6_vS32b_nt_pred_ai:
16476 case Hexagon::V6_vS32b_pred_ai: {
16477 switch (OpNum) {
16478 case 2:
16479 // op: Ii
16480 return 8;
16481 case 0:
16482 // op: Pv4
16483 return 11;
16484 case 1:
16485 // op: Rt32
16486 return 16;
16487 case 3:
16488 // op: Vs32
16489 return 0;
16490 }
16491 break;
16492 }
16493 case Hexagon::V6_zLd_pred_ai: {
16494 switch (OpNum) {
16495 case 2:
16496 // op: Ii
16497 return 8;
16498 case 0:
16499 // op: Pv4
16500 return 11;
16501 case 1:
16502 // op: Rt32
16503 return 16;
16504 }
16505 break;
16506 }
16507 case Hexagon::V6_vS32b_nqpred_ai:
16508 case Hexagon::V6_vS32b_nt_nqpred_ai:
16509 case Hexagon::V6_vS32b_nt_qpred_ai:
16510 case Hexagon::V6_vS32b_qpred_ai: {
16511 switch (OpNum) {
16512 case 2:
16513 // op: Ii
16514 return 8;
16515 case 0:
16516 // op: Qv4
16517 return 11;
16518 case 1:
16519 // op: Rt32
16520 return 16;
16521 case 3:
16522 // op: Vs32
16523 return 0;
16524 }
16525 break;
16526 }
16527 case Hexagon::V6_vS32b_srls_pi:
16528 case Hexagon::V6_zLd_pi: {
16529 switch (OpNum) {
16530 case 2:
16531 // op: Ii
16532 return 8;
16533 case 0:
16534 // op: Rx32
16535 return 16;
16536 }
16537 break;
16538 }
16539 case Hexagon::L4_ploadrbf_abs:
16540 case Hexagon::L4_ploadrbfnew_abs:
16541 case Hexagon::L4_ploadrbt_abs:
16542 case Hexagon::L4_ploadrbtnew_abs:
16543 case Hexagon::L4_ploadrhf_abs:
16544 case Hexagon::L4_ploadrhfnew_abs:
16545 case Hexagon::L4_ploadrht_abs:
16546 case Hexagon::L4_ploadrhtnew_abs:
16547 case Hexagon::L4_ploadrif_abs:
16548 case Hexagon::L4_ploadrifnew_abs:
16549 case Hexagon::L4_ploadrit_abs:
16550 case Hexagon::L4_ploadritnew_abs:
16551 case Hexagon::L4_ploadrubf_abs:
16552 case Hexagon::L4_ploadrubfnew_abs:
16553 case Hexagon::L4_ploadrubt_abs:
16554 case Hexagon::L4_ploadrubtnew_abs:
16555 case Hexagon::L4_ploadruhf_abs:
16556 case Hexagon::L4_ploadruhfnew_abs:
16557 case Hexagon::L4_ploadruht_abs:
16558 case Hexagon::L4_ploadruhtnew_abs: {
16559 switch (OpNum) {
16560 case 2:
16561 // op: Ii
16562 return 8;
16563 case 1:
16564 // op: Pt4
16565 return 9;
16566 case 0:
16567 // op: Rd32
16568 return 0;
16569 }
16570 break;
16571 }
16572 case Hexagon::L4_ploadrdf_abs:
16573 case Hexagon::L4_ploadrdfnew_abs:
16574 case Hexagon::L4_ploadrdt_abs:
16575 case Hexagon::L4_ploadrdtnew_abs: {
16576 switch (OpNum) {
16577 case 2:
16578 // op: Ii
16579 return 8;
16580 case 1:
16581 // op: Pt4
16582 return 9;
16583 case 0:
16584 // op: Rdd32
16585 return 0;
16586 }
16587 break;
16588 }
16589 case Hexagon::SL1_loadri_io:
16590 case Hexagon::SL1_loadrub_io:
16591 case Hexagon::SL2_loadrb_io:
16592 case Hexagon::SL2_loadrh_io:
16593 case Hexagon::SL2_loadruh_io: {
16594 switch (OpNum) {
16595 case 2:
16596 // op: Ii
16597 return 8;
16598 case 1:
16599 // op: Rs16
16600 return 4;
16601 case 0:
16602 // op: Rd16
16603 return 0;
16604 }
16605 break;
16606 }
16607 case Hexagon::C2_bitsclri:
16608 case Hexagon::C4_nbitsclri:
16609 case Hexagon::F2_sfclass:
16610 case Hexagon::S2_tstbit_i:
16611 case Hexagon::S4_ntstbit_i: {
16612 switch (OpNum) {
16613 case 2:
16614 // op: Ii
16615 return 8;
16616 case 1:
16617 // op: Rs32
16618 return 16;
16619 case 0:
16620 // op: Pd4
16621 return 0;
16622 }
16623 break;
16624 }
16625 case Hexagon::A4_cround_ri:
16626 case Hexagon::A4_round_ri:
16627 case Hexagon::A4_round_ri_sat:
16628 case Hexagon::A7_clip:
16629 case Hexagon::S2_asl_i_r:
16630 case Hexagon::S2_asl_i_r_sat:
16631 case Hexagon::S2_asr_i_r:
16632 case Hexagon::S2_asr_i_r_rnd:
16633 case Hexagon::S2_clrbit_i:
16634 case Hexagon::S2_lsr_i_r:
16635 case Hexagon::S2_setbit_i:
16636 case Hexagon::S2_togglebit_i:
16637 case Hexagon::S4_clbaddi:
16638 case Hexagon::S6_rol_i_r: {
16639 switch (OpNum) {
16640 case 2:
16641 // op: Ii
16642 return 8;
16643 case 1:
16644 // op: Rs32
16645 return 16;
16646 case 0:
16647 // op: Rd32
16648 return 0;
16649 }
16650 break;
16651 }
16652 case Hexagon::A4_bitspliti: {
16653 switch (OpNum) {
16654 case 2:
16655 // op: Ii
16656 return 8;
16657 case 1:
16658 // op: Rs32
16659 return 16;
16660 case 0:
16661 // op: Rdd32
16662 return 0;
16663 }
16664 break;
16665 }
16666 case Hexagon::S2_asr_i_svw_trun:
16667 case Hexagon::S4_clbpaddi:
16668 case Hexagon::S5_asrhub_rnd_sat:
16669 case Hexagon::S5_asrhub_sat: {
16670 switch (OpNum) {
16671 case 2:
16672 // op: Ii
16673 return 8;
16674 case 1:
16675 // op: Rss32
16676 return 16;
16677 case 0:
16678 // op: Rd32
16679 return 0;
16680 }
16681 break;
16682 }
16683 case Hexagon::A7_croundd_ri:
16684 case Hexagon::A7_vclip:
16685 case Hexagon::S2_asl_i_p:
16686 case Hexagon::S2_asl_i_vh:
16687 case Hexagon::S2_asl_i_vw:
16688 case Hexagon::S2_asr_i_p:
16689 case Hexagon::S2_asr_i_p_rnd:
16690 case Hexagon::S2_asr_i_vh:
16691 case Hexagon::S2_asr_i_vw:
16692 case Hexagon::S2_lsr_i_p:
16693 case Hexagon::S2_lsr_i_vh:
16694 case Hexagon::S2_lsr_i_vw:
16695 case Hexagon::S5_vasrhrnd:
16696 case Hexagon::S6_rol_i_p: {
16697 switch (OpNum) {
16698 case 2:
16699 // op: Ii
16700 return 8;
16701 case 1:
16702 // op: Rss32
16703 return 16;
16704 case 0:
16705 // op: Rdd32
16706 return 0;
16707 }
16708 break;
16709 }
16710 case Hexagon::V6_vL32Ub_ai:
16711 case Hexagon::V6_vL32b_ai:
16712 case Hexagon::V6_vL32b_cur_ai:
16713 case Hexagon::V6_vL32b_nt_ai:
16714 case Hexagon::V6_vL32b_nt_cur_ai:
16715 case Hexagon::V6_vL32b_nt_tmp_ai:
16716 case Hexagon::V6_vL32b_tmp_ai: {
16717 switch (OpNum) {
16718 case 2:
16719 // op: Ii
16720 return 8;
16721 case 1:
16722 // op: Rt32
16723 return 16;
16724 case 0:
16725 // op: Vd32
16726 return 0;
16727 }
16728 break;
16729 }
16730 case Hexagon::S2_extractu:
16731 case Hexagon::S4_extract: {
16732 switch (OpNum) {
16733 case 2:
16734 // op: Ii
16735 return 8;
16736 case 3:
16737 // op: II
16738 return 5;
16739 case 1:
16740 // op: Rs32
16741 return 16;
16742 case 0:
16743 // op: Rd32
16744 return 0;
16745 }
16746 break;
16747 }
16748 case Hexagon::S2_extractup:
16749 case Hexagon::S4_extractp: {
16750 switch (OpNum) {
16751 case 2:
16752 // op: Ii
16753 return 8;
16754 case 3:
16755 // op: II
16756 return 5;
16757 case 1:
16758 // op: Rss32
16759 return 16;
16760 case 0:
16761 // op: Rdd32
16762 return 0;
16763 }
16764 break;
16765 }
16766 case Hexagon::V6_vS32b_new_pi:
16767 case Hexagon::V6_vS32b_nt_new_pi: {
16768 switch (OpNum) {
16769 case 2:
16770 // op: Ii
16771 return 8;
16772 case 3:
16773 // op: Os8
16774 return 0;
16775 case 0:
16776 // op: Rx32
16777 return 16;
16778 }
16779 break;
16780 }
16781 case Hexagon::V6_vS32Ub_pi:
16782 case Hexagon::V6_vS32b_nt_pi:
16783 case Hexagon::V6_vS32b_pi: {
16784 switch (OpNum) {
16785 case 2:
16786 // op: Ii
16787 return 8;
16788 case 3:
16789 // op: Vs32
16790 return 0;
16791 case 0:
16792 // op: Rx32
16793 return 16;
16794 }
16795 break;
16796 }
16797 case Hexagon::V6_vS32b_srls_ppu:
16798 case Hexagon::V6_zLd_ppu: {
16799 switch (OpNum) {
16800 case 2:
16801 // op: Mu2
16802 return 13;
16803 case 0:
16804 // op: Rx32
16805 return 16;
16806 }
16807 break;
16808 }
16809 case Hexagon::S2_storerbnew_pbr:
16810 case Hexagon::S2_storerbnew_pcr:
16811 case Hexagon::S2_storerbnew_pr:
16812 case Hexagon::S2_storerhnew_pbr:
16813 case Hexagon::S2_storerhnew_pcr:
16814 case Hexagon::S2_storerhnew_pr:
16815 case Hexagon::S2_storerinew_pbr:
16816 case Hexagon::S2_storerinew_pcr:
16817 case Hexagon::S2_storerinew_pr: {
16818 switch (OpNum) {
16819 case 2:
16820 // op: Mu2
16821 return 13;
16822 case 3:
16823 // op: Nt8
16824 return 8;
16825 case 0:
16826 // op: Rx32
16827 return 16;
16828 }
16829 break;
16830 }
16831 case Hexagon::V6_vS32b_new_ppu:
16832 case Hexagon::V6_vS32b_nt_new_ppu: {
16833 switch (OpNum) {
16834 case 2:
16835 // op: Mu2
16836 return 13;
16837 case 3:
16838 // op: Os8
16839 return 0;
16840 case 0:
16841 // op: Rx32
16842 return 16;
16843 }
16844 break;
16845 }
16846 case Hexagon::S2_storerb_pbr:
16847 case Hexagon::S2_storerb_pcr:
16848 case Hexagon::S2_storerb_pr:
16849 case Hexagon::S2_storerf_pbr:
16850 case Hexagon::S2_storerf_pcr:
16851 case Hexagon::S2_storerf_pr:
16852 case Hexagon::S2_storerh_pbr:
16853 case Hexagon::S2_storerh_pcr:
16854 case Hexagon::S2_storerh_pr:
16855 case Hexagon::S2_storeri_pbr:
16856 case Hexagon::S2_storeri_pcr:
16857 case Hexagon::S2_storeri_pr: {
16858 switch (OpNum) {
16859 case 2:
16860 // op: Mu2
16861 return 13;
16862 case 3:
16863 // op: Rt32
16864 return 8;
16865 case 0:
16866 // op: Rx32
16867 return 16;
16868 }
16869 break;
16870 }
16871 case Hexagon::S2_storerd_pbr:
16872 case Hexagon::S2_storerd_pcr:
16873 case Hexagon::S2_storerd_pr: {
16874 switch (OpNum) {
16875 case 2:
16876 // op: Mu2
16877 return 13;
16878 case 3:
16879 // op: Rtt32
16880 return 8;
16881 case 0:
16882 // op: Rx32
16883 return 16;
16884 }
16885 break;
16886 }
16887 case Hexagon::V6_vS32Ub_ppu:
16888 case Hexagon::V6_vS32b_nt_ppu:
16889 case Hexagon::V6_vS32b_ppu: {
16890 switch (OpNum) {
16891 case 2:
16892 // op: Mu2
16893 return 13;
16894 case 3:
16895 // op: Vs32
16896 return 0;
16897 case 0:
16898 // op: Rx32
16899 return 16;
16900 }
16901 break;
16902 }
16903 case Hexagon::V6_vL32b_cur_npred_ppu:
16904 case Hexagon::V6_vL32b_cur_pred_ppu:
16905 case Hexagon::V6_vL32b_npred_ppu:
16906 case Hexagon::V6_vL32b_nt_cur_npred_ppu:
16907 case Hexagon::V6_vL32b_nt_cur_pred_ppu:
16908 case Hexagon::V6_vL32b_nt_npred_ppu:
16909 case Hexagon::V6_vL32b_nt_pred_ppu:
16910 case Hexagon::V6_vL32b_nt_tmp_npred_ppu:
16911 case Hexagon::V6_vL32b_nt_tmp_pred_ppu:
16912 case Hexagon::V6_vL32b_pred_ppu:
16913 case Hexagon::V6_vL32b_tmp_npred_ppu:
16914 case Hexagon::V6_vL32b_tmp_pred_ppu: {
16915 switch (OpNum) {
16916 case 2:
16917 // op: Pv4
16918 return 11;
16919 case 4:
16920 // op: Mu2
16921 return 13;
16922 case 0:
16923 // op: Vd32
16924 return 0;
16925 case 1:
16926 // op: Rx32
16927 return 16;
16928 }
16929 break;
16930 }
16931 case Hexagon::V6_vandnqrt_acc:
16932 case Hexagon::V6_vandqrt_acc: {
16933 switch (OpNum) {
16934 case 2:
16935 // op: Qu4
16936 return 8;
16937 case 3:
16938 // op: Rt32
16939 return 16;
16940 case 0:
16941 // op: Vx32
16942 return 0;
16943 }
16944 break;
16945 }
16946 case Hexagon::SA1_addrx: {
16947 switch (OpNum) {
16948 case 2:
16949 // op: Rs16
16950 return 4;
16951 case 0:
16952 // op: Rx16
16953 return 0;
16954 }
16955 break;
16956 }
16957 case Hexagon::F2_sfinvsqrta: {
16958 switch (OpNum) {
16959 case 2:
16960 // op: Rs32
16961 return 16;
16962 case 0:
16963 // op: Rd32
16964 return 0;
16965 case 1:
16966 // op: Pe4
16967 return 5;
16968 }
16969 break;
16970 }
16971 case Hexagon::F2_sfrecipa: {
16972 switch (OpNum) {
16973 case 2:
16974 // op: Rs32
16975 return 16;
16976 case 3:
16977 // op: Rt32
16978 return 8;
16979 case 0:
16980 // op: Rd32
16981 return 0;
16982 case 1:
16983 // op: Pe4
16984 return 5;
16985 }
16986 break;
16987 }
16988 case Hexagon::F2_sffma:
16989 case Hexagon::F2_sffma_lib:
16990 case Hexagon::F2_sffms:
16991 case Hexagon::F2_sffms_lib:
16992 case Hexagon::M2_acci:
16993 case Hexagon::M2_maci:
16994 case Hexagon::M2_mnaci:
16995 case Hexagon::M2_mpy_acc_hh_s0:
16996 case Hexagon::M2_mpy_acc_hh_s1:
16997 case Hexagon::M2_mpy_acc_hl_s0:
16998 case Hexagon::M2_mpy_acc_hl_s1:
16999 case Hexagon::M2_mpy_acc_lh_s0:
17000 case Hexagon::M2_mpy_acc_lh_s1:
17001 case Hexagon::M2_mpy_acc_ll_s0:
17002 case Hexagon::M2_mpy_acc_ll_s1:
17003 case Hexagon::M2_mpy_acc_sat_hh_s0:
17004 case Hexagon::M2_mpy_acc_sat_hh_s1:
17005 case Hexagon::M2_mpy_acc_sat_hl_s0:
17006 case Hexagon::M2_mpy_acc_sat_hl_s1:
17007 case Hexagon::M2_mpy_acc_sat_lh_s0:
17008 case Hexagon::M2_mpy_acc_sat_lh_s1:
17009 case Hexagon::M2_mpy_acc_sat_ll_s0:
17010 case Hexagon::M2_mpy_acc_sat_ll_s1:
17011 case Hexagon::M2_mpy_nac_hh_s0:
17012 case Hexagon::M2_mpy_nac_hh_s1:
17013 case Hexagon::M2_mpy_nac_hl_s0:
17014 case Hexagon::M2_mpy_nac_hl_s1:
17015 case Hexagon::M2_mpy_nac_lh_s0:
17016 case Hexagon::M2_mpy_nac_lh_s1:
17017 case Hexagon::M2_mpy_nac_ll_s0:
17018 case Hexagon::M2_mpy_nac_ll_s1:
17019 case Hexagon::M2_mpy_nac_sat_hh_s0:
17020 case Hexagon::M2_mpy_nac_sat_hh_s1:
17021 case Hexagon::M2_mpy_nac_sat_hl_s0:
17022 case Hexagon::M2_mpy_nac_sat_hl_s1:
17023 case Hexagon::M2_mpy_nac_sat_lh_s0:
17024 case Hexagon::M2_mpy_nac_sat_lh_s1:
17025 case Hexagon::M2_mpy_nac_sat_ll_s0:
17026 case Hexagon::M2_mpy_nac_sat_ll_s1:
17027 case Hexagon::M2_mpyu_acc_hh_s0:
17028 case Hexagon::M2_mpyu_acc_hh_s1:
17029 case Hexagon::M2_mpyu_acc_hl_s0:
17030 case Hexagon::M2_mpyu_acc_hl_s1:
17031 case Hexagon::M2_mpyu_acc_lh_s0:
17032 case Hexagon::M2_mpyu_acc_lh_s1:
17033 case Hexagon::M2_mpyu_acc_ll_s0:
17034 case Hexagon::M2_mpyu_acc_ll_s1:
17035 case Hexagon::M2_mpyu_nac_hh_s0:
17036 case Hexagon::M2_mpyu_nac_hh_s1:
17037 case Hexagon::M2_mpyu_nac_hl_s0:
17038 case Hexagon::M2_mpyu_nac_hl_s1:
17039 case Hexagon::M2_mpyu_nac_lh_s0:
17040 case Hexagon::M2_mpyu_nac_lh_s1:
17041 case Hexagon::M2_mpyu_nac_ll_s0:
17042 case Hexagon::M2_mpyu_nac_ll_s1:
17043 case Hexagon::M2_nacci:
17044 case Hexagon::M2_xor_xacc:
17045 case Hexagon::M4_and_and:
17046 case Hexagon::M4_and_andn:
17047 case Hexagon::M4_and_or:
17048 case Hexagon::M4_and_xor:
17049 case Hexagon::M4_mac_up_s1_sat:
17050 case Hexagon::M4_nac_up_s1_sat:
17051 case Hexagon::M4_or_and:
17052 case Hexagon::M4_or_andn:
17053 case Hexagon::M4_or_or:
17054 case Hexagon::M4_or_xor:
17055 case Hexagon::M4_xor_and:
17056 case Hexagon::M4_xor_andn:
17057 case Hexagon::M4_xor_or:
17058 case Hexagon::S2_asl_r_r_acc:
17059 case Hexagon::S2_asl_r_r_and:
17060 case Hexagon::S2_asl_r_r_nac:
17061 case Hexagon::S2_asl_r_r_or:
17062 case Hexagon::S2_asr_r_r_acc:
17063 case Hexagon::S2_asr_r_r_and:
17064 case Hexagon::S2_asr_r_r_nac:
17065 case Hexagon::S2_asr_r_r_or:
17066 case Hexagon::S2_lsl_r_r_acc:
17067 case Hexagon::S2_lsl_r_r_and:
17068 case Hexagon::S2_lsl_r_r_nac:
17069 case Hexagon::S2_lsl_r_r_or:
17070 case Hexagon::S2_lsr_r_r_acc:
17071 case Hexagon::S2_lsr_r_r_and:
17072 case Hexagon::S2_lsr_r_r_nac:
17073 case Hexagon::S2_lsr_r_r_or: {
17074 switch (OpNum) {
17075 case 2:
17076 // op: Rs32
17077 return 16;
17078 case 3:
17079 // op: Rt32
17080 return 8;
17081 case 0:
17082 // op: Rx32
17083 return 0;
17084 }
17085 break;
17086 }
17087 case Hexagon::M2_cmaci_s0:
17088 case Hexagon::M2_cmacr_s0:
17089 case Hexagon::M2_cmacs_s0:
17090 case Hexagon::M2_cmacs_s1:
17091 case Hexagon::M2_cmacsc_s0:
17092 case Hexagon::M2_cmacsc_s1:
17093 case Hexagon::M2_cnacs_s0:
17094 case Hexagon::M2_cnacs_s1:
17095 case Hexagon::M2_cnacsc_s0:
17096 case Hexagon::M2_cnacsc_s1:
17097 case Hexagon::M2_dpmpyss_acc_s0:
17098 case Hexagon::M2_dpmpyss_nac_s0:
17099 case Hexagon::M2_dpmpyuu_acc_s0:
17100 case Hexagon::M2_dpmpyuu_nac_s0:
17101 case Hexagon::M2_mpyd_acc_hh_s0:
17102 case Hexagon::M2_mpyd_acc_hh_s1:
17103 case Hexagon::M2_mpyd_acc_hl_s0:
17104 case Hexagon::M2_mpyd_acc_hl_s1:
17105 case Hexagon::M2_mpyd_acc_lh_s0:
17106 case Hexagon::M2_mpyd_acc_lh_s1:
17107 case Hexagon::M2_mpyd_acc_ll_s0:
17108 case Hexagon::M2_mpyd_acc_ll_s1:
17109 case Hexagon::M2_mpyd_nac_hh_s0:
17110 case Hexagon::M2_mpyd_nac_hh_s1:
17111 case Hexagon::M2_mpyd_nac_hl_s0:
17112 case Hexagon::M2_mpyd_nac_hl_s1:
17113 case Hexagon::M2_mpyd_nac_lh_s0:
17114 case Hexagon::M2_mpyd_nac_lh_s1:
17115 case Hexagon::M2_mpyd_nac_ll_s0:
17116 case Hexagon::M2_mpyd_nac_ll_s1:
17117 case Hexagon::M2_mpyud_acc_hh_s0:
17118 case Hexagon::M2_mpyud_acc_hh_s1:
17119 case Hexagon::M2_mpyud_acc_hl_s0:
17120 case Hexagon::M2_mpyud_acc_hl_s1:
17121 case Hexagon::M2_mpyud_acc_lh_s0:
17122 case Hexagon::M2_mpyud_acc_lh_s1:
17123 case Hexagon::M2_mpyud_acc_ll_s0:
17124 case Hexagon::M2_mpyud_acc_ll_s1:
17125 case Hexagon::M2_mpyud_nac_hh_s0:
17126 case Hexagon::M2_mpyud_nac_hh_s1:
17127 case Hexagon::M2_mpyud_nac_hl_s0:
17128 case Hexagon::M2_mpyud_nac_hl_s1:
17129 case Hexagon::M2_mpyud_nac_lh_s0:
17130 case Hexagon::M2_mpyud_nac_lh_s1:
17131 case Hexagon::M2_mpyud_nac_ll_s0:
17132 case Hexagon::M2_mpyud_nac_ll_s1:
17133 case Hexagon::M2_vmac2:
17134 case Hexagon::M2_vmac2s_s0:
17135 case Hexagon::M2_vmac2s_s1:
17136 case Hexagon::M2_vmac2su_s0:
17137 case Hexagon::M2_vmac2su_s1:
17138 case Hexagon::M4_pmpyw_acc:
17139 case Hexagon::M4_vpmpyh_acc:
17140 case Hexagon::M5_vmacbsu:
17141 case Hexagon::M5_vmacbuu: {
17142 switch (OpNum) {
17143 case 2:
17144 // op: Rs32
17145 return 16;
17146 case 3:
17147 // op: Rt32
17148 return 8;
17149 case 0:
17150 // op: Rxx32
17151 return 0;
17152 }
17153 break;
17154 }
17155 case Hexagon::F2_sffma_sc: {
17156 switch (OpNum) {
17157 case 2:
17158 // op: Rs32
17159 return 16;
17160 case 3:
17161 // op: Rt32
17162 return 8;
17163 case 4:
17164 // op: Pu4
17165 return 5;
17166 case 0:
17167 // op: Rx32
17168 return 0;
17169 }
17170 break;
17171 }
17172 case Hexagon::S2_insert_rp: {
17173 switch (OpNum) {
17174 case 2:
17175 // op: Rs32
17176 return 16;
17177 case 3:
17178 // op: Rtt32
17179 return 8;
17180 case 0:
17181 // op: Rx32
17182 return 0;
17183 }
17184 break;
17185 }
17186 case Hexagon::S2_asl_r_p_acc:
17187 case Hexagon::S2_asl_r_p_and:
17188 case Hexagon::S2_asl_r_p_nac:
17189 case Hexagon::S2_asl_r_p_or:
17190 case Hexagon::S2_asl_r_p_xor:
17191 case Hexagon::S2_asr_r_p_acc:
17192 case Hexagon::S2_asr_r_p_and:
17193 case Hexagon::S2_asr_r_p_nac:
17194 case Hexagon::S2_asr_r_p_or:
17195 case Hexagon::S2_asr_r_p_xor:
17196 case Hexagon::S2_lsl_r_p_acc:
17197 case Hexagon::S2_lsl_r_p_and:
17198 case Hexagon::S2_lsl_r_p_nac:
17199 case Hexagon::S2_lsl_r_p_or:
17200 case Hexagon::S2_lsl_r_p_xor:
17201 case Hexagon::S2_lsr_r_p_acc:
17202 case Hexagon::S2_lsr_r_p_and:
17203 case Hexagon::S2_lsr_r_p_nac:
17204 case Hexagon::S2_lsr_r_p_or:
17205 case Hexagon::S2_lsr_r_p_xor:
17206 case Hexagon::S2_vrcnegh: {
17207 switch (OpNum) {
17208 case 2:
17209 // op: Rss32
17210 return 16;
17211 case 3:
17212 // op: Rt32
17213 return 8;
17214 case 0:
17215 // op: Rxx32
17216 return 0;
17217 }
17218 break;
17219 }
17220 case Hexagon::A4_addp_c:
17221 case Hexagon::A4_subp_c: {
17222 switch (OpNum) {
17223 case 2:
17224 // op: Rss32
17225 return 16;
17226 case 3:
17227 // op: Rtt32
17228 return 8;
17229 case 0:
17230 // op: Rdd32
17231 return 0;
17232 case 1:
17233 // op: Px4
17234 return 5;
17235 }
17236 break;
17237 }
17238 case Hexagon::A2_vraddub_acc:
17239 case Hexagon::A2_vrsadub_acc:
17240 case Hexagon::F2_dfmpyhh:
17241 case Hexagon::F2_dfmpylh:
17242 case Hexagon::M2_mmachs_rs0:
17243 case Hexagon::M2_mmachs_rs1:
17244 case Hexagon::M2_mmachs_s0:
17245 case Hexagon::M2_mmachs_s1:
17246 case Hexagon::M2_mmacls_rs0:
17247 case Hexagon::M2_mmacls_rs1:
17248 case Hexagon::M2_mmacls_s0:
17249 case Hexagon::M2_mmacls_s1:
17250 case Hexagon::M2_mmacuhs_rs0:
17251 case Hexagon::M2_mmacuhs_rs1:
17252 case Hexagon::M2_mmacuhs_s0:
17253 case Hexagon::M2_mmacuhs_s1:
17254 case Hexagon::M2_mmaculs_rs0:
17255 case Hexagon::M2_mmaculs_rs1:
17256 case Hexagon::M2_mmaculs_s0:
17257 case Hexagon::M2_mmaculs_s1:
17258 case Hexagon::M2_vcmac_s0_sat_i:
17259 case Hexagon::M2_vcmac_s0_sat_r:
17260 case Hexagon::M2_vdmacs_s0:
17261 case Hexagon::M2_vdmacs_s1:
17262 case Hexagon::M2_vmac2es:
17263 case Hexagon::M2_vmac2es_s0:
17264 case Hexagon::M2_vmac2es_s1:
17265 case Hexagon::M2_vrcmaci_s0:
17266 case Hexagon::M2_vrcmaci_s0c:
17267 case Hexagon::M2_vrcmacr_s0:
17268 case Hexagon::M2_vrcmacr_s0c:
17269 case Hexagon::M2_vrcmpys_acc_s1_h:
17270 case Hexagon::M2_vrcmpys_acc_s1_l:
17271 case Hexagon::M2_vrmac_s0:
17272 case Hexagon::M4_vrmpyeh_acc_s0:
17273 case Hexagon::M4_vrmpyeh_acc_s1:
17274 case Hexagon::M4_vrmpyoh_acc_s0:
17275 case Hexagon::M4_vrmpyoh_acc_s1:
17276 case Hexagon::M4_xor_xacc:
17277 case Hexagon::M5_vdmacbsu:
17278 case Hexagon::M5_vrmacbsu:
17279 case Hexagon::M5_vrmacbuu:
17280 case Hexagon::M7_dcmpyiw_acc:
17281 case Hexagon::M7_dcmpyiwc_acc:
17282 case Hexagon::M7_dcmpyrw_acc:
17283 case Hexagon::M7_dcmpyrwc_acc:
17284 case Hexagon::S2_insertp_rp: {
17285 switch (OpNum) {
17286 case 2:
17287 // op: Rss32
17288 return 16;
17289 case 3:
17290 // op: Rtt32
17291 return 8;
17292 case 0:
17293 // op: Rxx32
17294 return 0;
17295 }
17296 break;
17297 }
17298 case Hexagon::A4_vrmaxh:
17299 case Hexagon::A4_vrmaxuh:
17300 case Hexagon::A4_vrmaxuw:
17301 case Hexagon::A4_vrmaxw:
17302 case Hexagon::A4_vrminh:
17303 case Hexagon::A4_vrminuh:
17304 case Hexagon::A4_vrminuw:
17305 case Hexagon::A4_vrminw: {
17306 switch (OpNum) {
17307 case 2:
17308 // op: Rss32
17309 return 16;
17310 case 3:
17311 // op: Ru32
17312 return 0;
17313 case 0:
17314 // op: Rxx32
17315 return 8;
17316 }
17317 break;
17318 }
17319 case Hexagon::V6_vinsertwr: {
17320 switch (OpNum) {
17321 case 2:
17322 // op: Rt32
17323 return 16;
17324 case 0:
17325 // op: Vx32
17326 return 0;
17327 }
17328 break;
17329 }
17330 case Hexagon::M2_subacc: {
17331 switch (OpNum) {
17332 case 2:
17333 // op: Rt32
17334 return 8;
17335 case 3:
17336 // op: Rs32
17337 return 16;
17338 case 0:
17339 // op: Rx32
17340 return 0;
17341 }
17342 break;
17343 }
17344 case Hexagon::A6_vminub_RdP: {
17345 switch (OpNum) {
17346 case 2:
17347 // op: Rtt32
17348 return 8;
17349 case 3:
17350 // op: Rss32
17351 return 16;
17352 case 0:
17353 // op: Rdd32
17354 return 0;
17355 case 1:
17356 // op: Pe4
17357 return 5;
17358 }
17359 break;
17360 }
17361 case Hexagon::V6_vrmpyzbb_rx:
17362 case Hexagon::V6_vrmpyzbub_rx:
17363 case Hexagon::V6_vrmpyzcb_rx:
17364 case Hexagon::V6_vrmpyzcbs_rx:
17365 case Hexagon::V6_vrmpyznb_rx: {
17366 switch (OpNum) {
17367 case 2:
17368 // op: Vu32
17369 return 8;
17370 case 0:
17371 // op: Vdddd32
17372 return 0;
17373 case 1:
17374 // op: Rx8
17375 return 16;
17376 }
17377 break;
17378 }
17379 case Hexagon::V6_vunpackob:
17380 case Hexagon::V6_vunpackoh: {
17381 switch (OpNum) {
17382 case 2:
17383 // op: Vu32
17384 return 8;
17385 case 0:
17386 // op: Vxx32
17387 return 0;
17388 }
17389 break;
17390 }
17391 case Hexagon::V6_vandvrt_acc: {
17392 switch (OpNum) {
17393 case 2:
17394 // op: Vu32
17395 return 8;
17396 case 3:
17397 // op: Rt32
17398 return 16;
17399 case 0:
17400 // op: Qx4
17401 return 0;
17402 }
17403 break;
17404 }
17405 case Hexagon::V6_get_qfext_oracc:
17406 case Hexagon::V6_vaslh_acc:
17407 case Hexagon::V6_vaslw_acc:
17408 case Hexagon::V6_vasrh_acc:
17409 case Hexagon::V6_vasrw_acc:
17410 case Hexagon::V6_vdmpybus_acc:
17411 case Hexagon::V6_vdmpyhb_acc:
17412 case Hexagon::V6_vdmpyhsat_acc:
17413 case Hexagon::V6_vdmpyhsusat_acc:
17414 case Hexagon::V6_vmpyihb_acc:
17415 case Hexagon::V6_vmpyiwb_acc:
17416 case Hexagon::V6_vmpyiwh_acc:
17417 case Hexagon::V6_vmpyiwub_acc:
17418 case Hexagon::V6_vmpyuhe_acc:
17419 case Hexagon::V6_vrmpybus_acc:
17420 case Hexagon::V6_vrmpyub_acc: {
17421 switch (OpNum) {
17422 case 2:
17423 // op: Vu32
17424 return 8;
17425 case 3:
17426 // op: Rt32
17427 return 16;
17428 case 0:
17429 // op: Vx32
17430 return 0;
17431 }
17432 break;
17433 }
17434 case Hexagon::V6_vmpybus_acc:
17435 case Hexagon::V6_vmpyh_acc:
17436 case Hexagon::V6_vmpyhsat_acc:
17437 case Hexagon::V6_vmpyub_acc:
17438 case Hexagon::V6_vmpyuh_acc: {
17439 switch (OpNum) {
17440 case 2:
17441 // op: Vu32
17442 return 8;
17443 case 3:
17444 // op: Rt32
17445 return 16;
17446 case 0:
17447 // op: Vxx32
17448 return 0;
17449 }
17450 break;
17451 }
17452 case Hexagon::V6_vrmpyzbb_rt_acc:
17453 case Hexagon::V6_vrmpyzbub_rt_acc:
17454 case Hexagon::V6_vrmpyzcb_rt_acc:
17455 case Hexagon::V6_vrmpyzcbs_rt_acc:
17456 case Hexagon::V6_vrmpyznb_rt_acc: {
17457 switch (OpNum) {
17458 case 2:
17459 // op: Vu32
17460 return 8;
17461 case 3:
17462 // op: Rt8
17463 return 16;
17464 case 0:
17465 // op: Vyyyy32
17466 return 0;
17467 }
17468 break;
17469 }
17470 case Hexagon::V6_vmpahhsat:
17471 case Hexagon::V6_vmpauhuhsat:
17472 case Hexagon::V6_vmpsuhuhsat: {
17473 switch (OpNum) {
17474 case 2:
17475 // op: Vu32
17476 return 8;
17477 case 3:
17478 // op: Rtt32
17479 return 16;
17480 case 0:
17481 // op: Vx32
17482 return 0;
17483 }
17484 break;
17485 }
17486 case Hexagon::V6_vrmpybub_rtt_acc:
17487 case Hexagon::V6_vrmpyub_rtt_acc: {
17488 switch (OpNum) {
17489 case 2:
17490 // op: Vu32
17491 return 8;
17492 case 3:
17493 // op: Rtt32
17494 return 16;
17495 case 0:
17496 // op: Vxx32
17497 return 0;
17498 }
17499 break;
17500 }
17501 case Hexagon::V6_veqb_and:
17502 case Hexagon::V6_veqb_or:
17503 case Hexagon::V6_veqb_xor:
17504 case Hexagon::V6_veqh_and:
17505 case Hexagon::V6_veqh_or:
17506 case Hexagon::V6_veqh_xor:
17507 case Hexagon::V6_veqw_and:
17508 case Hexagon::V6_veqw_or:
17509 case Hexagon::V6_veqw_xor:
17510 case Hexagon::V6_vgtb_and:
17511 case Hexagon::V6_vgtb_or:
17512 case Hexagon::V6_vgtb_xor:
17513 case Hexagon::V6_vgtbf_and:
17514 case Hexagon::V6_vgtbf_or:
17515 case Hexagon::V6_vgtbf_xor:
17516 case Hexagon::V6_vgth_and:
17517 case Hexagon::V6_vgth_or:
17518 case Hexagon::V6_vgth_xor:
17519 case Hexagon::V6_vgthf_and:
17520 case Hexagon::V6_vgthf_or:
17521 case Hexagon::V6_vgthf_xor:
17522 case Hexagon::V6_vgtsf_and:
17523 case Hexagon::V6_vgtsf_or:
17524 case Hexagon::V6_vgtsf_xor:
17525 case Hexagon::V6_vgtub_and:
17526 case Hexagon::V6_vgtub_or:
17527 case Hexagon::V6_vgtub_xor:
17528 case Hexagon::V6_vgtuh_and:
17529 case Hexagon::V6_vgtuh_or:
17530 case Hexagon::V6_vgtuh_xor:
17531 case Hexagon::V6_vgtuw_and:
17532 case Hexagon::V6_vgtuw_or:
17533 case Hexagon::V6_vgtuw_xor:
17534 case Hexagon::V6_vgtw_and:
17535 case Hexagon::V6_vgtw_or:
17536 case Hexagon::V6_vgtw_xor: {
17537 switch (OpNum) {
17538 case 2:
17539 // op: Vu32
17540 return 8;
17541 case 3:
17542 // op: Vv32
17543 return 16;
17544 case 0:
17545 // op: Qx4
17546 return 0;
17547 }
17548 break;
17549 }
17550 case Hexagon::V6_vaddcarryo:
17551 case Hexagon::V6_vsubcarryo: {
17552 switch (OpNum) {
17553 case 2:
17554 // op: Vu32
17555 return 8;
17556 case 3:
17557 // op: Vv32
17558 return 16;
17559 case 0:
17560 // op: Vd32
17561 return 0;
17562 case 1:
17563 // op: Qe4
17564 return 5;
17565 }
17566 break;
17567 }
17568 case Hexagon::V6_vaddcarry:
17569 case Hexagon::V6_vsubcarry: {
17570 switch (OpNum) {
17571 case 2:
17572 // op: Vu32
17573 return 8;
17574 case 3:
17575 // op: Vv32
17576 return 16;
17577 case 0:
17578 // op: Vd32
17579 return 0;
17580 case 1:
17581 // op: Qx4
17582 return 5;
17583 }
17584 break;
17585 }
17586 case Hexagon::V6_vdmpy_sf_hf_acc:
17587 case Hexagon::V6_vdmpyhvsat_acc:
17588 case Hexagon::V6_vmpy_hf_hf_acc:
17589 case Hexagon::V6_vmpyiewh_acc:
17590 case Hexagon::V6_vmpyiewuh_acc:
17591 case Hexagon::V6_vmpyih_acc:
17592 case Hexagon::V6_vmpyowh_rnd_sacc:
17593 case Hexagon::V6_vmpyowh_sacc:
17594 case Hexagon::V6_vrmpybusv_acc:
17595 case Hexagon::V6_vrmpybv_acc:
17596 case Hexagon::V6_vrmpyubv_acc: {
17597 switch (OpNum) {
17598 case 2:
17599 // op: Vu32
17600 return 8;
17601 case 3:
17602 // op: Vv32
17603 return 16;
17604 case 0:
17605 // op: Vx32
17606 return 0;
17607 }
17608 break;
17609 }
17610 case Hexagon::V6_vaddhw_acc:
17611 case Hexagon::V6_vaddubh_acc:
17612 case Hexagon::V6_vadduhw_acc:
17613 case Hexagon::V6_vasr_into:
17614 case Hexagon::V6_vmpy_hf_f8_acc:
17615 case Hexagon::V6_vmpy_sf_bf_acc:
17616 case Hexagon::V6_vmpy_sf_hf_acc:
17617 case Hexagon::V6_vmpybusv_acc:
17618 case Hexagon::V6_vmpybv_acc:
17619 case Hexagon::V6_vmpyhus_acc:
17620 case Hexagon::V6_vmpyhv_acc:
17621 case Hexagon::V6_vmpyowh_64_acc:
17622 case Hexagon::V6_vmpyubv_acc:
17623 case Hexagon::V6_vmpyuhv_acc: {
17624 switch (OpNum) {
17625 case 2:
17626 // op: Vu32
17627 return 8;
17628 case 3:
17629 // op: Vv32
17630 return 16;
17631 case 0:
17632 // op: Vxx32
17633 return 0;
17634 }
17635 break;
17636 }
17637 case Hexagon::V6_vlutvvb_oracc: {
17638 switch (OpNum) {
17639 case 2:
17640 // op: Vu32
17641 return 8;
17642 case 3:
17643 // op: Vv32
17644 return 19;
17645 case 4:
17646 // op: Rt8
17647 return 16;
17648 case 0:
17649 // op: Vx32
17650 return 0;
17651 }
17652 break;
17653 }
17654 case Hexagon::V6_vlutvwh_oracc: {
17655 switch (OpNum) {
17656 case 2:
17657 // op: Vu32
17658 return 8;
17659 case 3:
17660 // op: Vv32
17661 return 19;
17662 case 4:
17663 // op: Rt8
17664 return 16;
17665 case 0:
17666 // op: Vxx32
17667 return 0;
17668 }
17669 break;
17670 }
17671 case Hexagon::V6_vdmpyhisat_acc:
17672 case Hexagon::V6_vdmpyhsuisat_acc: {
17673 switch (OpNum) {
17674 case 2:
17675 // op: Vuu32
17676 return 8;
17677 case 3:
17678 // op: Rt32
17679 return 16;
17680 case 0:
17681 // op: Vx32
17682 return 0;
17683 }
17684 break;
17685 }
17686 case Hexagon::V6_vdmpybus_dv_acc:
17687 case Hexagon::V6_vdmpyhb_dv_acc:
17688 case Hexagon::V6_vdsaduh_acc:
17689 case Hexagon::V6_vmpabus_acc:
17690 case Hexagon::V6_vmpabuu_acc:
17691 case Hexagon::V6_vmpahb_acc:
17692 case Hexagon::V6_vmpauhb_acc:
17693 case Hexagon::V6_vtmpyb_acc:
17694 case Hexagon::V6_vtmpybus_acc:
17695 case Hexagon::V6_vtmpyhb_acc: {
17696 switch (OpNum) {
17697 case 2:
17698 // op: Vuu32
17699 return 8;
17700 case 3:
17701 // op: Rt32
17702 return 16;
17703 case 0:
17704 // op: Vxx32
17705 return 0;
17706 }
17707 break;
17708 }
17709 case Hexagon::L4_loadalignb_ap:
17710 case Hexagon::L4_loadalignh_ap: {
17711 switch (OpNum) {
17712 case 3:
17713 // op: II
17714 return 5;
17715 case 0:
17716 // op: Ryy32
17717 return 0;
17718 case 1:
17719 // op: Re32
17720 return 16;
17721 }
17722 break;
17723 }
17724 case Hexagon::S2_pstorerbnewf_pi:
17725 case Hexagon::S2_pstorerbnewfnew_pi:
17726 case Hexagon::S2_pstorerbnewt_pi:
17727 case Hexagon::S2_pstorerbnewtnew_pi:
17728 case Hexagon::S2_pstorerhnewf_pi:
17729 case Hexagon::S2_pstorerhnewfnew_pi:
17730 case Hexagon::S2_pstorerhnewt_pi:
17731 case Hexagon::S2_pstorerhnewtnew_pi:
17732 case Hexagon::S2_pstorerinewf_pi:
17733 case Hexagon::S2_pstorerinewfnew_pi:
17734 case Hexagon::S2_pstorerinewt_pi:
17735 case Hexagon::S2_pstorerinewtnew_pi: {
17736 switch (OpNum) {
17737 case 3:
17738 // op: Ii
17739 return 3;
17740 case 1:
17741 // op: Pv4
17742 return 0;
17743 case 4:
17744 // op: Nt8
17745 return 8;
17746 case 0:
17747 // op: Rx32
17748 return 16;
17749 }
17750 break;
17751 }
17752 case Hexagon::S2_pstorerbf_pi:
17753 case Hexagon::S2_pstorerbfnew_pi:
17754 case Hexagon::S2_pstorerbt_pi:
17755 case Hexagon::S2_pstorerbtnew_pi:
17756 case Hexagon::S2_pstorerff_pi:
17757 case Hexagon::S2_pstorerffnew_pi:
17758 case Hexagon::S2_pstorerft_pi:
17759 case Hexagon::S2_pstorerftnew_pi:
17760 case Hexagon::S2_pstorerhf_pi:
17761 case Hexagon::S2_pstorerhfnew_pi:
17762 case Hexagon::S2_pstorerht_pi:
17763 case Hexagon::S2_pstorerhtnew_pi:
17764 case Hexagon::S2_pstorerif_pi:
17765 case Hexagon::S2_pstorerifnew_pi:
17766 case Hexagon::S2_pstorerit_pi:
17767 case Hexagon::S2_pstoreritnew_pi: {
17768 switch (OpNum) {
17769 case 3:
17770 // op: Ii
17771 return 3;
17772 case 1:
17773 // op: Pv4
17774 return 0;
17775 case 4:
17776 // op: Rt32
17777 return 8;
17778 case 0:
17779 // op: Rx32
17780 return 16;
17781 }
17782 break;
17783 }
17784 case Hexagon::S2_pstorerdf_pi:
17785 case Hexagon::S2_pstorerdfnew_pi:
17786 case Hexagon::S2_pstorerdt_pi:
17787 case Hexagon::S2_pstorerdtnew_pi: {
17788 switch (OpNum) {
17789 case 3:
17790 // op: Ii
17791 return 3;
17792 case 1:
17793 // op: Pv4
17794 return 0;
17795 case 4:
17796 // op: Rtt32
17797 return 8;
17798 case 0:
17799 // op: Rx32
17800 return 16;
17801 }
17802 break;
17803 }
17804 case Hexagon::L2_loadbsw2_pi:
17805 case Hexagon::L2_loadbzw2_pi:
17806 case Hexagon::L2_loadrb_pi:
17807 case Hexagon::L2_loadrh_pi:
17808 case Hexagon::L2_loadri_pi:
17809 case Hexagon::L2_loadrub_pi:
17810 case Hexagon::L2_loadruh_pi: {
17811 switch (OpNum) {
17812 case 3:
17813 // op: Ii
17814 return 5;
17815 case 0:
17816 // op: Rd32
17817 return 0;
17818 case 1:
17819 // op: Rx32
17820 return 16;
17821 }
17822 break;
17823 }
17824 case Hexagon::L2_loadbsw4_pi:
17825 case Hexagon::L2_loadbzw4_pi:
17826 case Hexagon::L2_loadrd_pi: {
17827 switch (OpNum) {
17828 case 3:
17829 // op: Ii
17830 return 5;
17831 case 0:
17832 // op: Rdd32
17833 return 0;
17834 case 1:
17835 // op: Rx32
17836 return 16;
17837 }
17838 break;
17839 }
17840 case Hexagon::L2_ploadrbf_io:
17841 case Hexagon::L2_ploadrbfnew_io:
17842 case Hexagon::L2_ploadrbt_io:
17843 case Hexagon::L2_ploadrbtnew_io:
17844 case Hexagon::L2_ploadrhf_io:
17845 case Hexagon::L2_ploadrhfnew_io:
17846 case Hexagon::L2_ploadrht_io:
17847 case Hexagon::L2_ploadrhtnew_io:
17848 case Hexagon::L2_ploadrif_io:
17849 case Hexagon::L2_ploadrifnew_io:
17850 case Hexagon::L2_ploadrit_io:
17851 case Hexagon::L2_ploadritnew_io:
17852 case Hexagon::L2_ploadrubf_io:
17853 case Hexagon::L2_ploadrubfnew_io:
17854 case Hexagon::L2_ploadrubt_io:
17855 case Hexagon::L2_ploadrubtnew_io:
17856 case Hexagon::L2_ploadruhf_io:
17857 case Hexagon::L2_ploadruhfnew_io:
17858 case Hexagon::L2_ploadruht_io:
17859 case Hexagon::L2_ploadruhtnew_io: {
17860 switch (OpNum) {
17861 case 3:
17862 // op: Ii
17863 return 5;
17864 case 1:
17865 // op: Pt4
17866 return 11;
17867 case 2:
17868 // op: Rs32
17869 return 16;
17870 case 0:
17871 // op: Rd32
17872 return 0;
17873 }
17874 break;
17875 }
17876 case Hexagon::L2_ploadrdf_io:
17877 case Hexagon::L2_ploadrdfnew_io:
17878 case Hexagon::L2_ploadrdt_io:
17879 case Hexagon::L2_ploadrdtnew_io: {
17880 switch (OpNum) {
17881 case 3:
17882 // op: Ii
17883 return 5;
17884 case 1:
17885 // op: Pt4
17886 return 11;
17887 case 2:
17888 // op: Rs32
17889 return 16;
17890 case 0:
17891 // op: Rdd32
17892 return 0;
17893 }
17894 break;
17895 }
17896 case Hexagon::A2_paddif:
17897 case Hexagon::A2_paddifnew:
17898 case Hexagon::A2_paddit:
17899 case Hexagon::A2_padditnew:
17900 case Hexagon::C2_muxir: {
17901 switch (OpNum) {
17902 case 3:
17903 // op: Ii
17904 return 5;
17905 case 1:
17906 // op: Pu4
17907 return 21;
17908 case 2:
17909 // op: Rs32
17910 return 16;
17911 case 0:
17912 // op: Rd32
17913 return 0;
17914 }
17915 break;
17916 }
17917 case Hexagon::S4_addaddi: {
17918 switch (OpNum) {
17919 case 3:
17920 // op: Ii
17921 return 5;
17922 case 1:
17923 // op: Rs32
17924 return 16;
17925 case 2:
17926 // op: Ru32
17927 return 0;
17928 case 0:
17929 // op: Rd32
17930 return 8;
17931 }
17932 break;
17933 }
17934 case Hexagon::S4_vrcrotate: {
17935 switch (OpNum) {
17936 case 3:
17937 // op: Ii
17938 return 5;
17939 case 1:
17940 // op: Rss32
17941 return 16;
17942 case 2:
17943 // op: Rt32
17944 return 8;
17945 case 0:
17946 // op: Rdd32
17947 return 0;
17948 }
17949 break;
17950 }
17951 case Hexagon::S2_vspliceib: {
17952 switch (OpNum) {
17953 case 3:
17954 // op: Ii
17955 return 5;
17956 case 1:
17957 // op: Rss32
17958 return 16;
17959 case 2:
17960 // op: Rtt32
17961 return 8;
17962 case 0:
17963 // op: Rdd32
17964 return 0;
17965 }
17966 break;
17967 }
17968 case Hexagon::S2_addasl_rrri: {
17969 switch (OpNum) {
17970 case 3:
17971 // op: Ii
17972 return 5;
17973 case 1:
17974 // op: Rt32
17975 return 8;
17976 case 2:
17977 // op: Rs32
17978 return 16;
17979 case 0:
17980 // op: Rd32
17981 return 0;
17982 }
17983 break;
17984 }
17985 case Hexagon::S2_valignib: {
17986 switch (OpNum) {
17987 case 3:
17988 // op: Ii
17989 return 5;
17990 case 1:
17991 // op: Rtt32
17992 return 8;
17993 case 2:
17994 // op: Rss32
17995 return 16;
17996 case 0:
17997 // op: Rdd32
17998 return 0;
17999 }
18000 break;
18001 }
18002 case Hexagon::S4_or_andix: {
18003 switch (OpNum) {
18004 case 3:
18005 // op: Ii
18006 return 5;
18007 case 1:
18008 // op: Ru32
18009 return 0;
18010 case 0:
18011 // op: Rx32
18012 return 16;
18013 }
18014 break;
18015 }
18016 case Hexagon::M4_mpyri_addr: {
18017 switch (OpNum) {
18018 case 3:
18019 // op: Ii
18020 return 5;
18021 case 1:
18022 // op: Ru32
18023 return 0;
18024 case 2:
18025 // op: Rs32
18026 return 16;
18027 case 0:
18028 // op: Rd32
18029 return 8;
18030 }
18031 break;
18032 }
18033 case Hexagon::V6_valignbi:
18034 case Hexagon::V6_vlalignbi:
18035 case Hexagon::V6_vlutvvbi: {
18036 switch (OpNum) {
18037 case 3:
18038 // op: Ii
18039 return 5;
18040 case 1:
18041 // op: Vu32
18042 return 8;
18043 case 2:
18044 // op: Vv32
18045 return 16;
18046 case 0:
18047 // op: Vd32
18048 return 0;
18049 }
18050 break;
18051 }
18052 case Hexagon::V6_vlutvwhi: {
18053 switch (OpNum) {
18054 case 3:
18055 // op: Ii
18056 return 5;
18057 case 1:
18058 // op: Vu32
18059 return 8;
18060 case 2:
18061 // op: Vv32
18062 return 16;
18063 case 0:
18064 // op: Vdd32
18065 return 0;
18066 }
18067 break;
18068 }
18069 case Hexagon::V6_vrmpybusi:
18070 case Hexagon::V6_vrmpyubi:
18071 case Hexagon::V6_vrsadubi: {
18072 switch (OpNum) {
18073 case 3:
18074 // op: Ii
18075 return 5;
18076 case 1:
18077 // op: Vuu32
18078 return 8;
18079 case 2:
18080 // op: Rt32
18081 return 16;
18082 case 0:
18083 // op: Vdd32
18084 return 0;
18085 }
18086 break;
18087 }
18088 case Hexagon::V6_v6mpyhubs10:
18089 case Hexagon::V6_v6mpyvubs10: {
18090 switch (OpNum) {
18091 case 3:
18092 // op: Ii
18093 return 5;
18094 case 1:
18095 // op: Vuu32
18096 return 8;
18097 case 2:
18098 // op: Vvv32
18099 return 16;
18100 case 0:
18101 // op: Vdd32
18102 return 0;
18103 }
18104 break;
18105 }
18106 case Hexagon::M2_accii:
18107 case Hexagon::M2_macsin:
18108 case Hexagon::M2_macsip:
18109 case Hexagon::M2_naccii:
18110 case Hexagon::S4_or_andi:
18111 case Hexagon::S4_or_ori: {
18112 switch (OpNum) {
18113 case 3:
18114 // op: Ii
18115 return 5;
18116 case 2:
18117 // op: Rs32
18118 return 16;
18119 case 0:
18120 // op: Rx32
18121 return 0;
18122 }
18123 break;
18124 }
18125 case Hexagon::L2_loadalignb_io:
18126 case Hexagon::L2_loadalignh_io: {
18127 switch (OpNum) {
18128 case 3:
18129 // op: Ii
18130 return 5;
18131 case 2:
18132 // op: Rs32
18133 return 16;
18134 case 0:
18135 // op: Ryy32
18136 return 0;
18137 }
18138 break;
18139 }
18140 case Hexagon::S2_tableidxb:
18141 case Hexagon::S2_tableidxd:
18142 case Hexagon::S2_tableidxh:
18143 case Hexagon::S2_tableidxw: {
18144 switch (OpNum) {
18145 case 3:
18146 // op: Ii
18147 return 5;
18148 case 4:
18149 // op: II
18150 return 8;
18151 case 2:
18152 // op: Rs32
18153 return 16;
18154 case 0:
18155 // op: Rx32
18156 return 0;
18157 }
18158 break;
18159 }
18160 case Hexagon::L2_loadbsw2_pci:
18161 case Hexagon::L2_loadbzw2_pci:
18162 case Hexagon::L2_loadrb_pci:
18163 case Hexagon::L2_loadrh_pci:
18164 case Hexagon::L2_loadri_pci:
18165 case Hexagon::L2_loadrub_pci:
18166 case Hexagon::L2_loadruh_pci: {
18167 switch (OpNum) {
18168 case 3:
18169 // op: Ii
18170 return 5;
18171 case 4:
18172 // op: Mu2
18173 return 13;
18174 case 0:
18175 // op: Rd32
18176 return 0;
18177 case 1:
18178 // op: Rx32
18179 return 16;
18180 }
18181 break;
18182 }
18183 case Hexagon::L2_loadbsw4_pci:
18184 case Hexagon::L2_loadbzw4_pci:
18185 case Hexagon::L2_loadrd_pci: {
18186 switch (OpNum) {
18187 case 3:
18188 // op: Ii
18189 return 5;
18190 case 4:
18191 // op: Mu2
18192 return 13;
18193 case 0:
18194 // op: Rdd32
18195 return 0;
18196 case 1:
18197 // op: Rx32
18198 return 16;
18199 }
18200 break;
18201 }
18202 case Hexagon::S4_pstorerbnewf_rr:
18203 case Hexagon::S4_pstorerbnewfnew_rr:
18204 case Hexagon::S4_pstorerbnewt_rr:
18205 case Hexagon::S4_pstorerbnewtnew_rr:
18206 case Hexagon::S4_pstorerhnewf_rr:
18207 case Hexagon::S4_pstorerhnewfnew_rr:
18208 case Hexagon::S4_pstorerhnewt_rr:
18209 case Hexagon::S4_pstorerhnewtnew_rr:
18210 case Hexagon::S4_pstorerinewf_rr:
18211 case Hexagon::S4_pstorerinewfnew_rr:
18212 case Hexagon::S4_pstorerinewt_rr:
18213 case Hexagon::S4_pstorerinewtnew_rr: {
18214 switch (OpNum) {
18215 case 3:
18216 // op: Ii
18217 return 7;
18218 case 0:
18219 // op: Pv4
18220 return 5;
18221 case 1:
18222 // op: Rs32
18223 return 16;
18224 case 2:
18225 // op: Ru32
18226 return 8;
18227 case 4:
18228 // op: Nt8
18229 return 0;
18230 }
18231 break;
18232 }
18233 case Hexagon::S4_pstorerbf_rr:
18234 case Hexagon::S4_pstorerbfnew_rr:
18235 case Hexagon::S4_pstorerbt_rr:
18236 case Hexagon::S4_pstorerbtnew_rr:
18237 case Hexagon::S4_pstorerff_rr:
18238 case Hexagon::S4_pstorerffnew_rr:
18239 case Hexagon::S4_pstorerft_rr:
18240 case Hexagon::S4_pstorerftnew_rr:
18241 case Hexagon::S4_pstorerhf_rr:
18242 case Hexagon::S4_pstorerhfnew_rr:
18243 case Hexagon::S4_pstorerht_rr:
18244 case Hexagon::S4_pstorerhtnew_rr:
18245 case Hexagon::S4_pstorerif_rr:
18246 case Hexagon::S4_pstorerifnew_rr:
18247 case Hexagon::S4_pstorerit_rr:
18248 case Hexagon::S4_pstoreritnew_rr: {
18249 switch (OpNum) {
18250 case 3:
18251 // op: Ii
18252 return 7;
18253 case 0:
18254 // op: Pv4
18255 return 5;
18256 case 1:
18257 // op: Rs32
18258 return 16;
18259 case 2:
18260 // op: Ru32
18261 return 8;
18262 case 4:
18263 // op: Rt32
18264 return 0;
18265 }
18266 break;
18267 }
18268 case Hexagon::S4_pstorerdf_rr:
18269 case Hexagon::S4_pstorerdfnew_rr:
18270 case Hexagon::S4_pstorerdt_rr:
18271 case Hexagon::S4_pstorerdtnew_rr: {
18272 switch (OpNum) {
18273 case 3:
18274 // op: Ii
18275 return 7;
18276 case 0:
18277 // op: Pv4
18278 return 5;
18279 case 1:
18280 // op: Rs32
18281 return 16;
18282 case 2:
18283 // op: Ru32
18284 return 8;
18285 case 4:
18286 // op: Rtt32
18287 return 0;
18288 }
18289 break;
18290 }
18291 case Hexagon::L4_loadrb_rr:
18292 case Hexagon::L4_loadrh_rr:
18293 case Hexagon::L4_loadri_rr:
18294 case Hexagon::L4_loadrub_rr:
18295 case Hexagon::L4_loadruh_rr: {
18296 switch (OpNum) {
18297 case 3:
18298 // op: Ii
18299 return 7;
18300 case 1:
18301 // op: Rs32
18302 return 16;
18303 case 2:
18304 // op: Rt32
18305 return 8;
18306 case 0:
18307 // op: Rd32
18308 return 0;
18309 }
18310 break;
18311 }
18312 case Hexagon::L4_loadrd_rr: {
18313 switch (OpNum) {
18314 case 3:
18315 // op: Ii
18316 return 7;
18317 case 1:
18318 // op: Rs32
18319 return 16;
18320 case 2:
18321 // op: Rt32
18322 return 8;
18323 case 0:
18324 // op: Rdd32
18325 return 0;
18326 }
18327 break;
18328 }
18329 case Hexagon::L4_loadalignb_ur:
18330 case Hexagon::L4_loadalignh_ur: {
18331 switch (OpNum) {
18332 case 3:
18333 // op: Ii
18334 return 7;
18335 case 4:
18336 // op: II
18337 return 5;
18338 case 2:
18339 // op: Rt32
18340 return 16;
18341 case 0:
18342 // op: Ryy32
18343 return 0;
18344 }
18345 break;
18346 }
18347 case Hexagon::V6_vL32Ub_pi:
18348 case Hexagon::V6_vL32b_cur_pi:
18349 case Hexagon::V6_vL32b_nt_cur_pi:
18350 case Hexagon::V6_vL32b_nt_pi:
18351 case Hexagon::V6_vL32b_nt_tmp_pi:
18352 case Hexagon::V6_vL32b_pi:
18353 case Hexagon::V6_vL32b_tmp_pi: {
18354 switch (OpNum) {
18355 case 3:
18356 // op: Ii
18357 return 8;
18358 case 0:
18359 // op: Vd32
18360 return 0;
18361 case 1:
18362 // op: Rx32
18363 return 16;
18364 }
18365 break;
18366 }
18367 case Hexagon::V6_zLd_pred_pi: {
18368 switch (OpNum) {
18369 case 3:
18370 // op: Ii
18371 return 8;
18372 case 1:
18373 // op: Pv4
18374 return 11;
18375 case 0:
18376 // op: Rx32
18377 return 16;
18378 }
18379 break;
18380 }
18381 case Hexagon::V6_vL32b_cur_npred_ai:
18382 case Hexagon::V6_vL32b_cur_pred_ai:
18383 case Hexagon::V6_vL32b_npred_ai:
18384 case Hexagon::V6_vL32b_nt_cur_npred_ai:
18385 case Hexagon::V6_vL32b_nt_cur_pred_ai:
18386 case Hexagon::V6_vL32b_nt_npred_ai:
18387 case Hexagon::V6_vL32b_nt_pred_ai:
18388 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
18389 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
18390 case Hexagon::V6_vL32b_pred_ai:
18391 case Hexagon::V6_vL32b_tmp_npred_ai:
18392 case Hexagon::V6_vL32b_tmp_pred_ai: {
18393 switch (OpNum) {
18394 case 3:
18395 // op: Ii
18396 return 8;
18397 case 1:
18398 // op: Pv4
18399 return 11;
18400 case 2:
18401 // op: Rt32
18402 return 16;
18403 case 0:
18404 // op: Vd32
18405 return 0;
18406 }
18407 break;
18408 }
18409 case Hexagon::V6_vS32b_new_npred_pi:
18410 case Hexagon::V6_vS32b_new_pred_pi:
18411 case Hexagon::V6_vS32b_nt_new_npred_pi:
18412 case Hexagon::V6_vS32b_nt_new_pred_pi: {
18413 switch (OpNum) {
18414 case 3:
18415 // op: Ii
18416 return 8;
18417 case 1:
18418 // op: Pv4
18419 return 11;
18420 case 4:
18421 // op: Os8
18422 return 0;
18423 case 0:
18424 // op: Rx32
18425 return 16;
18426 }
18427 break;
18428 }
18429 case Hexagon::V6_vS32Ub_npred_pi:
18430 case Hexagon::V6_vS32Ub_pred_pi:
18431 case Hexagon::V6_vS32b_npred_pi:
18432 case Hexagon::V6_vS32b_nt_npred_pi:
18433 case Hexagon::V6_vS32b_nt_pred_pi:
18434 case Hexagon::V6_vS32b_pred_pi: {
18435 switch (OpNum) {
18436 case 3:
18437 // op: Ii
18438 return 8;
18439 case 1:
18440 // op: Pv4
18441 return 11;
18442 case 4:
18443 // op: Vs32
18444 return 0;
18445 case 0:
18446 // op: Rx32
18447 return 16;
18448 }
18449 break;
18450 }
18451 case Hexagon::V6_vS32b_nqpred_pi:
18452 case Hexagon::V6_vS32b_nt_nqpred_pi:
18453 case Hexagon::V6_vS32b_nt_qpred_pi:
18454 case Hexagon::V6_vS32b_qpred_pi: {
18455 switch (OpNum) {
18456 case 3:
18457 // op: Ii
18458 return 8;
18459 case 1:
18460 // op: Qv4
18461 return 11;
18462 case 4:
18463 // op: Vs32
18464 return 0;
18465 case 0:
18466 // op: Rx32
18467 return 16;
18468 }
18469 break;
18470 }
18471 case Hexagon::S2_asl_i_r_acc:
18472 case Hexagon::S2_asl_i_r_and:
18473 case Hexagon::S2_asl_i_r_nac:
18474 case Hexagon::S2_asl_i_r_or:
18475 case Hexagon::S2_asl_i_r_xacc:
18476 case Hexagon::S2_asr_i_r_acc:
18477 case Hexagon::S2_asr_i_r_and:
18478 case Hexagon::S2_asr_i_r_nac:
18479 case Hexagon::S2_asr_i_r_or:
18480 case Hexagon::S2_lsr_i_r_acc:
18481 case Hexagon::S2_lsr_i_r_and:
18482 case Hexagon::S2_lsr_i_r_nac:
18483 case Hexagon::S2_lsr_i_r_or:
18484 case Hexagon::S2_lsr_i_r_xacc:
18485 case Hexagon::S6_rol_i_r_acc:
18486 case Hexagon::S6_rol_i_r_and:
18487 case Hexagon::S6_rol_i_r_nac:
18488 case Hexagon::S6_rol_i_r_or:
18489 case Hexagon::S6_rol_i_r_xacc: {
18490 switch (OpNum) {
18491 case 3:
18492 // op: Ii
18493 return 8;
18494 case 2:
18495 // op: Rs32
18496 return 16;
18497 case 0:
18498 // op: Rx32
18499 return 0;
18500 }
18501 break;
18502 }
18503 case Hexagon::S2_asl_i_p_acc:
18504 case Hexagon::S2_asl_i_p_and:
18505 case Hexagon::S2_asl_i_p_nac:
18506 case Hexagon::S2_asl_i_p_or:
18507 case Hexagon::S2_asl_i_p_xacc:
18508 case Hexagon::S2_asr_i_p_acc:
18509 case Hexagon::S2_asr_i_p_and:
18510 case Hexagon::S2_asr_i_p_nac:
18511 case Hexagon::S2_asr_i_p_or:
18512 case Hexagon::S2_lsr_i_p_acc:
18513 case Hexagon::S2_lsr_i_p_and:
18514 case Hexagon::S2_lsr_i_p_nac:
18515 case Hexagon::S2_lsr_i_p_or:
18516 case Hexagon::S2_lsr_i_p_xacc:
18517 case Hexagon::S6_rol_i_p_acc:
18518 case Hexagon::S6_rol_i_p_and:
18519 case Hexagon::S6_rol_i_p_nac:
18520 case Hexagon::S6_rol_i_p_or:
18521 case Hexagon::S6_rol_i_p_xacc: {
18522 switch (OpNum) {
18523 case 3:
18524 // op: Ii
18525 return 8;
18526 case 2:
18527 // op: Rss32
18528 return 16;
18529 case 0:
18530 // op: Rxx32
18531 return 0;
18532 }
18533 break;
18534 }
18535 case Hexagon::S2_insert: {
18536 switch (OpNum) {
18537 case 3:
18538 // op: Ii
18539 return 8;
18540 case 4:
18541 // op: II
18542 return 5;
18543 case 2:
18544 // op: Rs32
18545 return 16;
18546 case 0:
18547 // op: Rx32
18548 return 0;
18549 }
18550 break;
18551 }
18552 case Hexagon::S2_insertp: {
18553 switch (OpNum) {
18554 case 3:
18555 // op: Ii
18556 return 8;
18557 case 4:
18558 // op: II
18559 return 5;
18560 case 2:
18561 // op: Rss32
18562 return 16;
18563 case 0:
18564 // op: Rxx32
18565 return 0;
18566 }
18567 break;
18568 }
18569 case Hexagon::L2_loadbsw2_pbr:
18570 case Hexagon::L2_loadbsw2_pcr:
18571 case Hexagon::L2_loadbsw2_pr:
18572 case Hexagon::L2_loadbzw2_pbr:
18573 case Hexagon::L2_loadbzw2_pcr:
18574 case Hexagon::L2_loadbzw2_pr:
18575 case Hexagon::L2_loadrb_pbr:
18576 case Hexagon::L2_loadrb_pcr:
18577 case Hexagon::L2_loadrb_pr:
18578 case Hexagon::L2_loadrh_pbr:
18579 case Hexagon::L2_loadrh_pcr:
18580 case Hexagon::L2_loadrh_pr:
18581 case Hexagon::L2_loadri_pbr:
18582 case Hexagon::L2_loadri_pcr:
18583 case Hexagon::L2_loadri_pr:
18584 case Hexagon::L2_loadrub_pbr:
18585 case Hexagon::L2_loadrub_pcr:
18586 case Hexagon::L2_loadrub_pr:
18587 case Hexagon::L2_loadruh_pbr:
18588 case Hexagon::L2_loadruh_pcr:
18589 case Hexagon::L2_loadruh_pr: {
18590 switch (OpNum) {
18591 case 3:
18592 // op: Mu2
18593 return 13;
18594 case 0:
18595 // op: Rd32
18596 return 0;
18597 case 1:
18598 // op: Rx32
18599 return 16;
18600 }
18601 break;
18602 }
18603 case Hexagon::L2_loadbsw4_pbr:
18604 case Hexagon::L2_loadbsw4_pcr:
18605 case Hexagon::L2_loadbsw4_pr:
18606 case Hexagon::L2_loadbzw4_pbr:
18607 case Hexagon::L2_loadbzw4_pcr:
18608 case Hexagon::L2_loadbzw4_pr:
18609 case Hexagon::L2_loadrd_pbr:
18610 case Hexagon::L2_loadrd_pcr:
18611 case Hexagon::L2_loadrd_pr: {
18612 switch (OpNum) {
18613 case 3:
18614 // op: Mu2
18615 return 13;
18616 case 0:
18617 // op: Rdd32
18618 return 0;
18619 case 1:
18620 // op: Rx32
18621 return 16;
18622 }
18623 break;
18624 }
18625 case Hexagon::V6_vL32Ub_ppu:
18626 case Hexagon::V6_vL32b_cur_ppu:
18627 case Hexagon::V6_vL32b_nt_cur_ppu:
18628 case Hexagon::V6_vL32b_nt_ppu:
18629 case Hexagon::V6_vL32b_nt_tmp_ppu:
18630 case Hexagon::V6_vL32b_ppu:
18631 case Hexagon::V6_vL32b_tmp_ppu: {
18632 switch (OpNum) {
18633 case 3:
18634 // op: Mu2
18635 return 13;
18636 case 0:
18637 // op: Vd32
18638 return 0;
18639 case 1:
18640 // op: Rx32
18641 return 16;
18642 }
18643 break;
18644 }
18645 case Hexagon::A5_ACS: {
18646 switch (OpNum) {
18647 case 3:
18648 // op: Rss32
18649 return 16;
18650 case 4:
18651 // op: Rtt32
18652 return 8;
18653 case 0:
18654 // op: Rxx32
18655 return 0;
18656 case 1:
18657 // op: Pe4
18658 return 5;
18659 }
18660 break;
18661 }
18662 case Hexagon::V6_vrmpyzbb_rx_acc:
18663 case Hexagon::V6_vrmpyzbub_rx_acc:
18664 case Hexagon::V6_vrmpyzcb_rx_acc:
18665 case Hexagon::V6_vrmpyzcbs_rx_acc:
18666 case Hexagon::V6_vrmpyznb_rx_acc: {
18667 switch (OpNum) {
18668 case 3:
18669 // op: Vu32
18670 return 8;
18671 case 0:
18672 // op: Vyyyy32
18673 return 0;
18674 case 1:
18675 // op: Rx8
18676 return 16;
18677 }
18678 break;
18679 }
18680 case Hexagon::L2_loadalignb_pi:
18681 case Hexagon::L2_loadalignh_pi: {
18682 switch (OpNum) {
18683 case 4:
18684 // op: Ii
18685 return 5;
18686 case 0:
18687 // op: Ryy32
18688 return 0;
18689 case 1:
18690 // op: Rx32
18691 return 16;
18692 }
18693 break;
18694 }
18695 case Hexagon::L2_ploadrbf_pi:
18696 case Hexagon::L2_ploadrbfnew_pi:
18697 case Hexagon::L2_ploadrbt_pi:
18698 case Hexagon::L2_ploadrbtnew_pi:
18699 case Hexagon::L2_ploadrhf_pi:
18700 case Hexagon::L2_ploadrhfnew_pi:
18701 case Hexagon::L2_ploadrht_pi:
18702 case Hexagon::L2_ploadrhtnew_pi:
18703 case Hexagon::L2_ploadrif_pi:
18704 case Hexagon::L2_ploadrifnew_pi:
18705 case Hexagon::L2_ploadrit_pi:
18706 case Hexagon::L2_ploadritnew_pi:
18707 case Hexagon::L2_ploadrubf_pi:
18708 case Hexagon::L2_ploadrubfnew_pi:
18709 case Hexagon::L2_ploadrubt_pi:
18710 case Hexagon::L2_ploadrubtnew_pi:
18711 case Hexagon::L2_ploadruhf_pi:
18712 case Hexagon::L2_ploadruhfnew_pi:
18713 case Hexagon::L2_ploadruht_pi:
18714 case Hexagon::L2_ploadruhtnew_pi: {
18715 switch (OpNum) {
18716 case 4:
18717 // op: Ii
18718 return 5;
18719 case 2:
18720 // op: Pt4
18721 return 9;
18722 case 0:
18723 // op: Rd32
18724 return 0;
18725 case 1:
18726 // op: Rx32
18727 return 16;
18728 }
18729 break;
18730 }
18731 case Hexagon::L2_ploadrdf_pi:
18732 case Hexagon::L2_ploadrdfnew_pi:
18733 case Hexagon::L2_ploadrdt_pi:
18734 case Hexagon::L2_ploadrdtnew_pi: {
18735 switch (OpNum) {
18736 case 4:
18737 // op: Ii
18738 return 5;
18739 case 2:
18740 // op: Pt4
18741 return 9;
18742 case 0:
18743 // op: Rdd32
18744 return 0;
18745 case 1:
18746 // op: Rx32
18747 return 16;
18748 }
18749 break;
18750 }
18751 case Hexagon::S4_vrcrotate_acc: {
18752 switch (OpNum) {
18753 case 4:
18754 // op: Ii
18755 return 5;
18756 case 2:
18757 // op: Rss32
18758 return 16;
18759 case 3:
18760 // op: Rt32
18761 return 8;
18762 case 0:
18763 // op: Rxx32
18764 return 0;
18765 }
18766 break;
18767 }
18768 case Hexagon::V6_vlutvvb_oracci: {
18769 switch (OpNum) {
18770 case 4:
18771 // op: Ii
18772 return 5;
18773 case 2:
18774 // op: Vu32
18775 return 8;
18776 case 3:
18777 // op: Vv32
18778 return 16;
18779 case 0:
18780 // op: Vx32
18781 return 0;
18782 }
18783 break;
18784 }
18785 case Hexagon::V6_vlutvwh_oracci: {
18786 switch (OpNum) {
18787 case 4:
18788 // op: Ii
18789 return 5;
18790 case 2:
18791 // op: Vu32
18792 return 8;
18793 case 3:
18794 // op: Vv32
18795 return 16;
18796 case 0:
18797 // op: Vxx32
18798 return 0;
18799 }
18800 break;
18801 }
18802 case Hexagon::V6_vrmpybusi_acc:
18803 case Hexagon::V6_vrmpyubi_acc:
18804 case Hexagon::V6_vrsadubi_acc: {
18805 switch (OpNum) {
18806 case 4:
18807 // op: Ii
18808 return 5;
18809 case 2:
18810 // op: Vuu32
18811 return 8;
18812 case 3:
18813 // op: Rt32
18814 return 16;
18815 case 0:
18816 // op: Vxx32
18817 return 0;
18818 }
18819 break;
18820 }
18821 case Hexagon::V6_v6mpyhubs10_vxx:
18822 case Hexagon::V6_v6mpyvubs10_vxx: {
18823 switch (OpNum) {
18824 case 4:
18825 // op: Ii
18826 return 5;
18827 case 2:
18828 // op: Vuu32
18829 return 8;
18830 case 3:
18831 // op: Vvv32
18832 return 16;
18833 case 0:
18834 // op: Vxx32
18835 return 0;
18836 }
18837 break;
18838 }
18839 case Hexagon::L2_loadalignb_pci:
18840 case Hexagon::L2_loadalignh_pci: {
18841 switch (OpNum) {
18842 case 4:
18843 // op: Ii
18844 return 5;
18845 case 5:
18846 // op: Mu2
18847 return 13;
18848 case 0:
18849 // op: Ryy32
18850 return 0;
18851 case 1:
18852 // op: Rx32
18853 return 16;
18854 }
18855 break;
18856 }
18857 case Hexagon::L4_ploadrbf_rr:
18858 case Hexagon::L4_ploadrbfnew_rr:
18859 case Hexagon::L4_ploadrbt_rr:
18860 case Hexagon::L4_ploadrbtnew_rr:
18861 case Hexagon::L4_ploadrhf_rr:
18862 case Hexagon::L4_ploadrhfnew_rr:
18863 case Hexagon::L4_ploadrht_rr:
18864 case Hexagon::L4_ploadrhtnew_rr:
18865 case Hexagon::L4_ploadrif_rr:
18866 case Hexagon::L4_ploadrifnew_rr:
18867 case Hexagon::L4_ploadrit_rr:
18868 case Hexagon::L4_ploadritnew_rr:
18869 case Hexagon::L4_ploadrubf_rr:
18870 case Hexagon::L4_ploadrubfnew_rr:
18871 case Hexagon::L4_ploadrubt_rr:
18872 case Hexagon::L4_ploadrubtnew_rr:
18873 case Hexagon::L4_ploadruhf_rr:
18874 case Hexagon::L4_ploadruhfnew_rr:
18875 case Hexagon::L4_ploadruht_rr:
18876 case Hexagon::L4_ploadruhtnew_rr: {
18877 switch (OpNum) {
18878 case 4:
18879 // op: Ii
18880 return 7;
18881 case 1:
18882 // op: Pv4
18883 return 5;
18884 case 2:
18885 // op: Rs32
18886 return 16;
18887 case 3:
18888 // op: Rt32
18889 return 8;
18890 case 0:
18891 // op: Rd32
18892 return 0;
18893 }
18894 break;
18895 }
18896 case Hexagon::L4_ploadrdf_rr:
18897 case Hexagon::L4_ploadrdfnew_rr:
18898 case Hexagon::L4_ploadrdt_rr:
18899 case Hexagon::L4_ploadrdtnew_rr: {
18900 switch (OpNum) {
18901 case 4:
18902 // op: Ii
18903 return 7;
18904 case 1:
18905 // op: Pv4
18906 return 5;
18907 case 2:
18908 // op: Rs32
18909 return 16;
18910 case 3:
18911 // op: Rt32
18912 return 8;
18913 case 0:
18914 // op: Rdd32
18915 return 0;
18916 }
18917 break;
18918 }
18919 case Hexagon::V6_vL32b_cur_npred_pi:
18920 case Hexagon::V6_vL32b_cur_pred_pi:
18921 case Hexagon::V6_vL32b_npred_pi:
18922 case Hexagon::V6_vL32b_nt_cur_npred_pi:
18923 case Hexagon::V6_vL32b_nt_cur_pred_pi:
18924 case Hexagon::V6_vL32b_nt_npred_pi:
18925 case Hexagon::V6_vL32b_nt_pred_pi:
18926 case Hexagon::V6_vL32b_nt_tmp_npred_pi:
18927 case Hexagon::V6_vL32b_nt_tmp_pred_pi:
18928 case Hexagon::V6_vL32b_pred_pi:
18929 case Hexagon::V6_vL32b_tmp_npred_pi:
18930 case Hexagon::V6_vL32b_tmp_pred_pi: {
18931 switch (OpNum) {
18932 case 4:
18933 // op: Ii
18934 return 8;
18935 case 2:
18936 // op: Pv4
18937 return 11;
18938 case 0:
18939 // op: Vd32
18940 return 0;
18941 case 1:
18942 // op: Rx32
18943 return 16;
18944 }
18945 break;
18946 }
18947 case Hexagon::L2_loadalignb_pbr:
18948 case Hexagon::L2_loadalignb_pcr:
18949 case Hexagon::L2_loadalignb_pr:
18950 case Hexagon::L2_loadalignh_pbr:
18951 case Hexagon::L2_loadalignh_pcr:
18952 case Hexagon::L2_loadalignh_pr: {
18953 switch (OpNum) {
18954 case 4:
18955 // op: Mu2
18956 return 13;
18957 case 0:
18958 // op: Ryy32
18959 return 0;
18960 case 1:
18961 // op: Rx32
18962 return 16;
18963 }
18964 break;
18965 }
18966 case Hexagon::V6_vdeal:
18967 case Hexagon::V6_vshuff: {
18968 switch (OpNum) {
18969 case 4:
18970 // op: Rt32
18971 return 16;
18972 case 0:
18973 // op: Vy32
18974 return 8;
18975 case 1:
18976 // op: Vx32
18977 return 0;
18978 }
18979 break;
18980 }
18981 }
18982 std::string msg;
18983 raw_string_ostream Msg(msg);
18984 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
18985 report_fatal_error(Msg.str().c_str());
18986}
18987
18988#endif // GET_OPERAND_BIT_OFFSET
18989
18990