1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_immZExt5(int64_t Imm) {
12return Imm == (Imm & 0x1f);
13}
14static bool Predicate_immZExt6(int64_t Imm) {
15return Imm == (Imm & 0x3f);
16}
17static bool Predicate_immSExt6(int64_t Imm) {
18return isInt<6>(x: Imm);
19}
20static bool Predicate_immZExt4Ptr(int64_t Imm) {
21return isUInt<4>(x: Imm);
22}
23static bool Predicate_immZExt3Ptr(int64_t Imm) {
24return isUInt<3>(x: Imm);
25}
26static bool Predicate_immZExt2Ptr(int64_t Imm) {
27return isUInt<2>(x: Imm);
28}
29static bool Predicate_immZExt1Ptr(int64_t Imm) {
30return isUInt<1>(x: Imm);
31}
32static bool Predicate_immZExt4(int64_t Imm) {
33return isUInt<4>(x: Imm);
34}
35static bool Predicate_immSExtAddiur2(int64_t Imm) {
36return Imm == 1 || Imm == -1 ||
37 ((Imm % 4 == 0) &&
38 Imm < 28 && Imm > 0);
39}
40static bool Predicate_immSExtAddius5(int64_t Imm) {
41return Imm >= -8 && Imm <= 7;
42}
43static bool Predicate_immZExtAndi16(int64_t Imm) {
44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
47}
48static bool Predicate_immZExt2Shift(int64_t Imm) {
49return Imm >= 1 && Imm <= 8;
50}
51
52
53// FastEmit functions for ISD::BITCAST.
54
55Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
56 if (RetVT.SimpleTy != MVT::f32)
57 return Register();
58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
59 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MMR6, RC: &Mips::FGR32RegClass, Op0);
60 }
61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
62 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MM, RC: &Mips::FGR32RegClass, Op0);
63 }
64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
65 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1, RC: &Mips::FGR32RegClass, Op0);
66 }
67 return Register();
68}
69
70Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
71 if (RetVT.SimpleTy != MVT::f64)
72 return Register();
73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
74 return fastEmitInst_r(MachineInstOpcode: Mips::DMTC1, RC: &Mips::FGR64RegClass, Op0);
75 }
76 return Register();
77}
78
79Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
80 if (RetVT.SimpleTy != MVT::i32)
81 return Register();
82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
83 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MMR6, RC: &Mips::GPR32RegClass, Op0);
84 }
85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
86 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MM, RC: &Mips::GPR32RegClass, Op0);
87 }
88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
89 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1, RC: &Mips::GPR32RegClass, Op0);
90 }
91 return Register();
92}
93
94Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
95 if (RetVT.SimpleTy != MVT::i64)
96 return Register();
97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
98 return fastEmitInst_r(MachineInstOpcode: Mips::DMFC1, RC: &Mips::GPR64RegClass, Op0);
99 }
100 return Register();
101}
102
103Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
104 switch (VT.SimpleTy) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
109 default: return Register();
110 }
111}
112
113// FastEmit functions for ISD::BRIND.
114
115Register fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, Register Op0) {
116 if (RetVT.SimpleTy != MVT::isVoid)
117 return Register();
118 if ((Subtarget->inMips16Mode())) {
119 return fastEmitInst_r(MachineInstOpcode: Mips::JrcRx16, RC: &Mips::CPU16RegsRegClass, Op0);
120 }
121 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
122 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MMR6, RC: &Mips::GPR32RegClass, Op0);
123 }
124 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
125 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MM, RC: &Mips::GPR32RegClass, Op0);
126 }
127 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
128 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranchR6, RC: &Mips::GPR32RegClass, Op0);
129 }
130 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
131 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranchR6, RC: &Mips::GPR32RegClass, Op0);
132 }
133 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
134 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch, RC: &Mips::GPR32RegClass, Op0);
135 }
136 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
137 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch, RC: &Mips::GPR32RegClass, Op0);
138 }
139 return Register();
140}
141
142Register fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, Register Op0) {
143 if (RetVT.SimpleTy != MVT::isVoid)
144 return Register();
145 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
146 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranch64R6, RC: &Mips::GPR64RegClass, Op0);
147 }
148 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
149 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64R6, RC: &Mips::GPR64RegClass, Op0);
150 }
151 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
152 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch64, RC: &Mips::GPR64RegClass, Op0);
153 }
154 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
155 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64, RC: &Mips::GPR64RegClass, Op0);
156 }
157 return Register();
158}
159
160Register fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, Register Op0) {
161 switch (VT.SimpleTy) {
162 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0);
163 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0);
164 default: return Register();
165 }
166}
167
168// FastEmit functions for ISD::CTLZ.
169
170Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
171 if (RetVT.SimpleTy != MVT::i32)
172 return Register();
173 if ((Subtarget->inMicroMipsMode())) {
174 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_MM, RC: &Mips::GPR32RegClass, Op0);
175 }
176 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
177 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_R6, RC: &Mips::GPR32RegClass, Op0);
178 }
179 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
180 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ, RC: &Mips::GPR32RegClass, Op0);
181 }
182 return Register();
183}
184
185Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
186 if (RetVT.SimpleTy != MVT::i64)
187 return Register();
188 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
189 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ_R6, RC: &Mips::GPR64RegClass, Op0);
190 }
191 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
192 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ, RC: &Mips::GPR64RegClass, Op0);
193 }
194 return Register();
195}
196
197Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
198 if (RetVT.SimpleTy != MVT::v16i8)
199 return Register();
200 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
201 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_B, RC: &Mips::MSA128BRegClass, Op0);
202 }
203 return Register();
204}
205
206Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
207 if (RetVT.SimpleTy != MVT::v8i16)
208 return Register();
209 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
210 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_H, RC: &Mips::MSA128HRegClass, Op0);
211 }
212 return Register();
213}
214
215Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
216 if (RetVT.SimpleTy != MVT::v4i32)
217 return Register();
218 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
219 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_W, RC: &Mips::MSA128WRegClass, Op0);
220 }
221 return Register();
222}
223
224Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
225 if (RetVT.SimpleTy != MVT::v2i64)
226 return Register();
227 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
228 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_D, RC: &Mips::MSA128DRegClass, Op0);
229 }
230 return Register();
231}
232
233Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
234 switch (VT.SimpleTy) {
235 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
236 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
237 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
238 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
239 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
240 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
241 default: return Register();
242 }
243}
244
245// FastEmit functions for ISD::CTPOP.
246
247Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
248 if (RetVT.SimpleTy != MVT::i32)
249 return Register();
250 if ((Subtarget->hasCnMips())) {
251 return fastEmitInst_r(MachineInstOpcode: Mips::POP, RC: &Mips::GPR32RegClass, Op0);
252 }
253 return Register();
254}
255
256Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
257 if (RetVT.SimpleTy != MVT::i64)
258 return Register();
259 if ((Subtarget->hasCnMips())) {
260 return fastEmitInst_r(MachineInstOpcode: Mips::DPOP, RC: &Mips::GPR64RegClass, Op0);
261 }
262 return Register();
263}
264
265Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
266 if (RetVT.SimpleTy != MVT::v16i8)
267 return Register();
268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
269 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_B, RC: &Mips::MSA128BRegClass, Op0);
270 }
271 return Register();
272}
273
274Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
275 if (RetVT.SimpleTy != MVT::v8i16)
276 return Register();
277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
278 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_H, RC: &Mips::MSA128HRegClass, Op0);
279 }
280 return Register();
281}
282
283Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
284 if (RetVT.SimpleTy != MVT::v4i32)
285 return Register();
286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
287 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_W, RC: &Mips::MSA128WRegClass, Op0);
288 }
289 return Register();
290}
291
292Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
293 if (RetVT.SimpleTy != MVT::v2i64)
294 return Register();
295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
296 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_D, RC: &Mips::MSA128DRegClass, Op0);
297 }
298 return Register();
299}
300
301Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
302 switch (VT.SimpleTy) {
303 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
304 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
305 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
306 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
307 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
308 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FABS.
314
315Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return Register();
318 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
319 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S_MM, RC: &Mips::FGR32RegClass, Op0);
320 }
321 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
322 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S, RC: &Mips::FGR32RegClass, Op0);
323 }
324 return Register();
325}
326
327Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::f64)
329 return Register();
330 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
331 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64_MM, RC: &Mips::FGR64RegClass, Op0);
332 }
333 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
334 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
335 }
336 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
337 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64, RC: &Mips::FGR64RegClass, Op0);
338 }
339 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
340 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32, RC: &Mips::AFGR64RegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
346 if (RetVT.SimpleTy != MVT::v4f32)
347 return Register();
348 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
349 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_W, RC: &Mips::MSA128WRegClass, Op0);
350 }
351 return Register();
352}
353
354Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
355 if (RetVT.SimpleTy != MVT::v2f64)
356 return Register();
357 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
358 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D, RC: &Mips::MSA128DRegClass, Op0);
359 }
360 return Register();
361}
362
363Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
364 switch (VT.SimpleTy) {
365 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
366 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
367 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
368 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
369 default: return Register();
370 }
371}
372
373// FastEmit functions for ISD::FEXP2.
374
375Register fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, Register Op0) {
376 if (RetVT.SimpleTy != MVT::v4f32)
377 return Register();
378 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
379 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_W_1_PSEUDO, RC: &Mips::MSA128WRegClass, Op0);
380 }
381 return Register();
382}
383
384Register fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, Register Op0) {
385 if (RetVT.SimpleTy != MVT::v2f64)
386 return Register();
387 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
388 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_D_1_PSEUDO, RC: &Mips::MSA128DRegClass, Op0);
389 }
390 return Register();
391}
392
393Register fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, Register Op0) {
394 switch (VT.SimpleTy) {
395 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0);
396 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0);
397 default: return Register();
398 }
399}
400
401// FastEmit functions for ISD::FLOG2.
402
403Register fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, Register Op0) {
404 if (RetVT.SimpleTy != MVT::v4f32)
405 return Register();
406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
407 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_W, RC: &Mips::MSA128WRegClass, Op0);
408 }
409 return Register();
410}
411
412Register fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, Register Op0) {
413 if (RetVT.SimpleTy != MVT::v2f64)
414 return Register();
415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
416 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_D, RC: &Mips::MSA128DRegClass, Op0);
417 }
418 return Register();
419}
420
421Register fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, Register Op0) {
422 switch (VT.SimpleTy) {
423 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0);
424 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0);
425 default: return Register();
426 }
427}
428
429// FastEmit functions for ISD::FNEG.
430
431Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
432 if (RetVT.SimpleTy != MVT::f32)
433 return Register();
434 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
435 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
436 }
437 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
438 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MM, RC: &Mips::FGR32RegClass, Op0);
439 }
440 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
441 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S, RC: &Mips::FGR32RegClass, Op0);
442 }
443 return Register();
444}
445
446Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
447 if (RetVT.SimpleTy != MVT::f64)
448 return Register();
449 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
450 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64_MM, RC: &Mips::FGR64RegClass, Op0);
451 }
452 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
453 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
454 }
455 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
456 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64, RC: &Mips::FGR64RegClass, Op0);
457 }
458 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
459 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32, RC: &Mips::AFGR64RegClass, Op0);
460 }
461 return Register();
462}
463
464Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
465 switch (VT.SimpleTy) {
466 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
467 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
468 default: return Register();
469 }
470}
471
472// FastEmit functions for ISD::FP_EXTEND.
473
474Register fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Register Op0) {
475 if ((Subtarget->hasMSA())) {
476 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_W_PSEUDO, RC: &Mips::FGR32RegClass, Op0);
477 }
478 return Register();
479}
480
481Register fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Register Op0) {
482 if ((Subtarget->hasMSA())) {
483 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_D_PSEUDO, RC: &Mips::FGR64RegClass, Op0);
484 }
485 return Register();
486}
487
488Register fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, Register Op0) {
489switch (RetVT.SimpleTy) {
490 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0);
491 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0);
492 default: return Register();
493}
494}
495
496Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
497 if (RetVT.SimpleTy != MVT::f64)
498 return Register();
499 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
500 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S_MM, RC: &Mips::AFGR64RegClass, Op0);
501 }
502 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
503 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S_MM, RC: &Mips::FGR64RegClass, Op0);
504 }
505 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
506 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
507 }
508 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
509 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
510 }
511 return Register();
512}
513
514Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
515 switch (VT.SimpleTy) {
516 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0);
517 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
518 default: return Register();
519 }
520}
521
522// FastEmit functions for ISD::FP_ROUND.
523
524Register fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, Register Op0) {
525 if (RetVT.SimpleTy != MVT::f16)
526 return Register();
527 if ((Subtarget->hasMSA())) {
528 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_W_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
529 }
530 return Register();
531}
532
533Register fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Register Op0) {
534 if ((Subtarget->hasMSA())) {
535 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_D_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
536 }
537 return Register();
538}
539
540Register fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Register Op0) {
541 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
542 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32_MM, RC: &Mips::FGR32RegClass, Op0);
543 }
544 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
545 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64_MM, RC: &Mips::FGR32RegClass, Op0);
546 }
547 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
548 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
549 }
550 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
551 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
552 }
553 return Register();
554}
555
556Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
557switch (RetVT.SimpleTy) {
558 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0);
559 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0);
560 default: return Register();
561}
562}
563
564Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
565 switch (VT.SimpleTy) {
566 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0);
567 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
568 default: return Register();
569 }
570}
571
572// FastEmit functions for ISD::FP_TO_SINT.
573
574Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
575 if (RetVT.SimpleTy != MVT::v4i32)
576 return Register();
577 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
578 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_W, RC: &Mips::MSA128WRegClass, Op0);
579 }
580 return Register();
581}
582
583Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
584 if (RetVT.SimpleTy != MVT::v2i64)
585 return Register();
586 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
587 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_D, RC: &Mips::MSA128DRegClass, Op0);
588 }
589 return Register();
590}
591
592Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
593 switch (VT.SimpleTy) {
594 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
595 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
596 default: return Register();
597 }
598}
599
600// FastEmit functions for ISD::FP_TO_UINT.
601
602Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
603 if (RetVT.SimpleTy != MVT::v4i32)
604 return Register();
605 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
606 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_W, RC: &Mips::MSA128WRegClass, Op0);
607 }
608 return Register();
609}
610
611Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
612 if (RetVT.SimpleTy != MVT::v2i64)
613 return Register();
614 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
615 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_D, RC: &Mips::MSA128DRegClass, Op0);
616 }
617 return Register();
618}
619
620Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
621 switch (VT.SimpleTy) {
622 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
623 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
624 default: return Register();
625 }
626}
627
628// FastEmit functions for ISD::FRINT.
629
630Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
631 if (RetVT.SimpleTy != MVT::v4f32)
632 return Register();
633 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
634 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_W, RC: &Mips::MSA128WRegClass, Op0);
635 }
636 return Register();
637}
638
639Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
640 if (RetVT.SimpleTy != MVT::v2f64)
641 return Register();
642 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
643 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_D, RC: &Mips::MSA128DRegClass, Op0);
644 }
645 return Register();
646}
647
648Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
649 switch (VT.SimpleTy) {
650 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
651 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
652 default: return Register();
653 }
654}
655
656// FastEmit functions for ISD::FSQRT.
657
658Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
659 if (RetVT.SimpleTy != MVT::f32)
660 return Register();
661 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
662 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S_MM, RC: &Mips::FGR32RegClass, Op0);
663 }
664 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
665 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
666 }
667 return Register();
668}
669
670Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
671 if (RetVT.SimpleTy != MVT::f64)
672 return Register();
673 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
674 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64_MM, RC: &Mips::FGR64RegClass, Op0);
675 }
676 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
677 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
678 }
679 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
680 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
681 }
682 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
683 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
684 }
685 return Register();
686}
687
688Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
689 if (RetVT.SimpleTy != MVT::v4f32)
690 return Register();
691 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
692 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_W, RC: &Mips::MSA128WRegClass, Op0);
693 }
694 return Register();
695}
696
697Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
698 if (RetVT.SimpleTy != MVT::v2f64)
699 return Register();
700 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
701 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D, RC: &Mips::MSA128DRegClass, Op0);
702 }
703 return Register();
704}
705
706Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
707 switch (VT.SimpleTy) {
708 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
709 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
710 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
711 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
712 default: return Register();
713 }
714}
715
716// FastEmit functions for ISD::SIGN_EXTEND.
717
718Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
719 if (RetVT.SimpleTy != MVT::i64)
720 return Register();
721 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
722 return fastEmitInst_r(MachineInstOpcode: Mips::SLL64_32, RC: &Mips::GPR64RegClass, Op0);
723 }
724 return Register();
725}
726
727Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
728 switch (VT.SimpleTy) {
729 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
730 default: return Register();
731 }
732}
733
734// FastEmit functions for ISD::SINT_TO_FP.
735
736Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
737 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
738}
739
740Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
741 if ((Subtarget->isFP64bit())) {
742 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
743 }
744 if ((!Subtarget->isFP64bit())) {
745 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
746 }
747 return Register();
748}
749
750Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
751switch (RetVT.SimpleTy) {
752 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
753 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
754 default: return Register();
755}
756}
757
758Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
759 if (RetVT.SimpleTy != MVT::f64)
760 return Register();
761 if ((Subtarget->isFP64bit())) {
762 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
763 }
764 return Register();
765}
766
767Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
768 if (RetVT.SimpleTy != MVT::v4f32)
769 return Register();
770 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
771 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_W, RC: &Mips::MSA128WRegClass, Op0);
772 }
773 return Register();
774}
775
776Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
777 if (RetVT.SimpleTy != MVT::v2f64)
778 return Register();
779 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
780 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_D, RC: &Mips::MSA128DRegClass, Op0);
781 }
782 return Register();
783}
784
785Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
786 switch (VT.SimpleTy) {
787 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
788 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
789 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
790 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
791 default: return Register();
792 }
793}
794
795// FastEmit functions for ISD::UINT_TO_FP.
796
797Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
798 if (RetVT.SimpleTy != MVT::v4f32)
799 return Register();
800 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
801 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_W, RC: &Mips::MSA128WRegClass, Op0);
802 }
803 return Register();
804}
805
806Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
807 if (RetVT.SimpleTy != MVT::v2f64)
808 return Register();
809 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
810 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_D, RC: &Mips::MSA128DRegClass, Op0);
811 }
812 return Register();
813}
814
815Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
816 switch (VT.SimpleTy) {
817 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
818 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
819 default: return Register();
820 }
821}
822
823// FastEmit functions for MipsISD::JmpLink.
824
825Register fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, Register Op0) {
826 if (RetVT.SimpleTy != MVT::isVoid)
827 return Register();
828 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
829 return fastEmitInst_r(MachineInstOpcode: Mips::JALR16_MM, RC: &Mips::GPR32RegClass, Op0);
830 }
831 if ((Subtarget->inMips16Mode())) {
832 return fastEmitInst_r(MachineInstOpcode: Mips::JumpLinkReg16, RC: &Mips::CPU16RegsRegClass, Op0);
833 }
834 if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
835 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHBPseudo, RC: &Mips::GPR32RegClass, Op0);
836 }
837 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
838 return fastEmitInst_r(MachineInstOpcode: Mips::JALRPseudo, RC: &Mips::GPR32RegClass, Op0);
839 }
840 return Register();
841}
842
843Register fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, Register Op0) {
844 if (RetVT.SimpleTy != MVT::isVoid)
845 return Register();
846 if ((Subtarget->isABI_N64()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
847 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHB64Pseudo, RC: &Mips::GPR64RegClass, Op0);
848 }
849 if ((Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
850 return fastEmitInst_r(MachineInstOpcode: Mips::JALR64Pseudo, RC: &Mips::GPR64RegClass, Op0);
851 }
852 return Register();
853}
854
855Register fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, Register Op0) {
856 switch (VT.SimpleTy) {
857 case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0);
858 case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0);
859 default: return Register();
860 }
861}
862
863// FastEmit functions for MipsISD::MFHI.
864
865Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Register Op0) {
866 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
867 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
868 }
869 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
870 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI_MM, RC: &Mips::GPR32RegClass, Op0);
871 }
872 if ((Subtarget->hasDSP())) {
873 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP, RC: &Mips::GPR32RegClass, Op0);
874 }
875 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
876 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI, RC: &Mips::GPR32RegClass, Op0);
877 }
878 return Register();
879}
880
881Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Register Op0) {
882 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
883 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI64, RC: &Mips::GPR64RegClass, Op0);
884 }
885 return Register();
886}
887
888Register fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, Register Op0) {
889switch (RetVT.SimpleTy) {
890 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0);
891 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0);
892 default: return Register();
893}
894}
895
896Register fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, Register Op0) {
897 switch (VT.SimpleTy) {
898 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0);
899 default: return Register();
900 }
901}
902
903// FastEmit functions for MipsISD::MFLO.
904
905Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Register Op0) {
906 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
907 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
908 }
909 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
910 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO_MM, RC: &Mips::GPR32RegClass, Op0);
911 }
912 if ((Subtarget->hasDSP())) {
913 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP, RC: &Mips::GPR32RegClass, Op0);
914 }
915 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
916 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO, RC: &Mips::GPR32RegClass, Op0);
917 }
918 return Register();
919}
920
921Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Register Op0) {
922 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
923 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO64, RC: &Mips::GPR64RegClass, Op0);
924 }
925 return Register();
926}
927
928Register fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, Register Op0) {
929switch (RetVT.SimpleTy) {
930 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0);
931 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0);
932 default: return Register();
933}
934}
935
936Register fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, Register Op0) {
937 switch (VT.SimpleTy) {
938 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0);
939 default: return Register();
940 }
941}
942
943// FastEmit functions for MipsISD::MTC1_D64.
944
945Register fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, Register Op0) {
946 if (RetVT.SimpleTy != MVT::f64)
947 return Register();
948 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
949 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64_MM, RC: &Mips::FGR64RegClass, Op0);
950 }
951 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
952 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64, RC: &Mips::FGR64RegClass, Op0);
953 }
954 return Register();
955}
956
957Register fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, Register Op0) {
958 switch (VT.SimpleTy) {
959 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0);
960 default: return Register();
961 }
962}
963
964// FastEmit functions for MipsISD::TailCall.
965
966Register fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, Register Op0) {
967 if (RetVT.SimpleTy != MVT::isVoid)
968 return Register();
969 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
970 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MMR6, RC: &Mips::GPR32RegClass, Op0);
971 }
972 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
973 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MM, RC: &Mips::GPR32RegClass, Op0);
974 }
975 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
976 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHBR6REG, RC: &Mips::GPR32RegClass, Op0);
977 }
978 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
979 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLR6REG, RC: &Mips::GPR32RegClass, Op0);
980 }
981 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
982 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB, RC: &Mips::GPR32RegClass, Op0);
983 }
984 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
985 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG, RC: &Mips::GPR32RegClass, Op0);
986 }
987 return Register();
988}
989
990Register fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, Register Op0) {
991 if (RetVT.SimpleTy != MVT::isVoid)
992 return Register();
993 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
994 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHB64R6REG, RC: &Mips::GPR64RegClass, Op0);
995 }
996 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
997 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALL64R6REG, RC: &Mips::GPR64RegClass, Op0);
998 }
999 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1000 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB64, RC: &Mips::GPR64RegClass, Op0);
1001 }
1002 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1003 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG64, RC: &Mips::GPR64RegClass, Op0);
1004 }
1005 return Register();
1006}
1007
1008Register fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, Register Op0) {
1009 switch (VT.SimpleTy) {
1010 case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0);
1011 case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0);
1012 default: return Register();
1013 }
1014}
1015
1016// FastEmit functions for MipsISD::TruncIntFP.
1017
1018Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Register Op0) {
1019 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1020 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
1021 }
1022 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1023 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MM, RC: &Mips::FGR32RegClass, Op0);
1024 }
1025 if ((Subtarget->hasStandardEncoding())) {
1026 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S, RC: &Mips::FGR32RegClass, Op0);
1027 }
1028 return Register();
1029}
1030
1031Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Register Op0) {
1032 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1033 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_S, RC: &Mips::FGR64RegClass, Op0);
1034 }
1035 return Register();
1036}
1037
1038Register fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, Register Op0) {
1039switch (RetVT.SimpleTy) {
1040 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0);
1041 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0);
1042 default: return Register();
1043}
1044}
1045
1046Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Register Op0) {
1047 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1048 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D_MMR6, RC: &Mips::FGR32RegClass, Op0);
1049 }
1050 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1051 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_D64_MM, RC: &Mips::FGR32RegClass, Op0);
1052 }
1053 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1054 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_MM, RC: &Mips::FGR32RegClass, Op0);
1055 }
1056 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1057 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D64, RC: &Mips::FGR32RegClass, Op0);
1058 }
1059 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1060 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D32, RC: &Mips::FGR32RegClass, Op0);
1061 }
1062 return Register();
1063}
1064
1065Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Register Op0) {
1066 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1067 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_D64, RC: &Mips::FGR64RegClass, Op0);
1068 }
1069 return Register();
1070}
1071
1072Register fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, Register Op0) {
1073switch (RetVT.SimpleTy) {
1074 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0);
1075 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0);
1076 default: return Register();
1077}
1078}
1079
1080Register fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, Register Op0) {
1081 switch (VT.SimpleTy) {
1082 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0);
1083 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0);
1084 default: return Register();
1085 }
1086}
1087
1088// FastEmit functions for MipsISD::VALL_NONZERO.
1089
1090Register fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1091 if (RetVT.SimpleTy != MVT::i32)
1092 return Register();
1093 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1094}
1095
1096Register fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1097 if (RetVT.SimpleTy != MVT::i32)
1098 return Register();
1099 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1100}
1101
1102Register fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1103 if (RetVT.SimpleTy != MVT::i32)
1104 return Register();
1105 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1106}
1107
1108Register fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1109 if (RetVT.SimpleTy != MVT::i32)
1110 return Register();
1111 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1112}
1113
1114Register fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1115 switch (VT.SimpleTy) {
1116 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0);
1117 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0);
1118 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0);
1119 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0);
1120 default: return Register();
1121 }
1122}
1123
1124// FastEmit functions for MipsISD::VALL_ZERO.
1125
1126Register fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1127 if (RetVT.SimpleTy != MVT::i32)
1128 return Register();
1129 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1130}
1131
1132Register fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1133 if (RetVT.SimpleTy != MVT::i32)
1134 return Register();
1135 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1136}
1137
1138Register fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1139 if (RetVT.SimpleTy != MVT::i32)
1140 return Register();
1141 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1142}
1143
1144Register fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1145 if (RetVT.SimpleTy != MVT::i32)
1146 return Register();
1147 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1148}
1149
1150Register fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1151 switch (VT.SimpleTy) {
1152 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0);
1153 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0);
1154 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0);
1155 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0);
1156 default: return Register();
1157 }
1158}
1159
1160// FastEmit functions for MipsISD::VANY_NONZERO.
1161
1162Register fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1163 if (RetVT.SimpleTy != MVT::i32)
1164 return Register();
1165 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1166}
1167
1168Register fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1169 switch (VT.SimpleTy) {
1170 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0);
1171 default: return Register();
1172 }
1173}
1174
1175// FastEmit functions for MipsISD::VANY_ZERO.
1176
1177Register fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1178 if (RetVT.SimpleTy != MVT::i32)
1179 return Register();
1180 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1181}
1182
1183Register fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1184 switch (VT.SimpleTy) {
1185 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0);
1186 default: return Register();
1187 }
1188}
1189
1190// Top-level FastEmit function.
1191
1192Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1193 switch (Opcode) {
1194 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1195 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0);
1196 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1197 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1198 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1199 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0);
1200 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0);
1201 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1202 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1203 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1204 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1205 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1206 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1207 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1208 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1209 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1210 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1211 case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0);
1212 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0);
1213 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0);
1214 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0);
1215 case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0);
1216 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0);
1217 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0);
1218 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0);
1219 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0);
1220 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0);
1221 default: return Register();
1222 }
1223}
1224
1225// FastEmit functions for ISD::ADD.
1226
1227Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1228 if (RetVT.SimpleTy != MVT::i32)
1229 return Register();
1230 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1231 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
1232 }
1233 if ((Subtarget->inMips16Mode())) {
1234 return fastEmitInst_rr(MachineInstOpcode: Mips::AdduRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1235 }
1236 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1237 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1238 }
1239 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1240 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1241 }
1242 return Register();
1243}
1244
1245Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1246 if (RetVT.SimpleTy != MVT::i64)
1247 return Register();
1248 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1249 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1250 }
1251 return Register();
1252}
1253
1254Register fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
1255 if (RetVT.SimpleTy != MVT::v4i8)
1256 return Register();
1257 if ((Subtarget->hasDSP())) {
1258 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
1259 }
1260 return Register();
1261}
1262
1263Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1264 if (RetVT.SimpleTy != MVT::v16i8)
1265 return Register();
1266 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1267 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1268 }
1269 return Register();
1270}
1271
1272Register fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1273 if (RetVT.SimpleTy != MVT::v2i16)
1274 return Register();
1275 if ((Subtarget->hasDSP())) {
1276 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1277 }
1278 return Register();
1279}
1280
1281Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1282 if (RetVT.SimpleTy != MVT::v8i16)
1283 return Register();
1284 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1285 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1286 }
1287 return Register();
1288}
1289
1290Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1291 if (RetVT.SimpleTy != MVT::v4i32)
1292 return Register();
1293 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1294 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1295 }
1296 return Register();
1297}
1298
1299Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1300 if (RetVT.SimpleTy != MVT::v2i64)
1301 return Register();
1302 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1303 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1304 }
1305 return Register();
1306}
1307
1308Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1309 switch (VT.SimpleTy) {
1310 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1311 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1312 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op1);
1313 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1314 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op1);
1315 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1316 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1317 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1318 default: return Register();
1319 }
1320}
1321
1322// FastEmit functions for ISD::ADDC.
1323
1324Register fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1325 if (RetVT.SimpleTy != MVT::i32)
1326 return Register();
1327 if ((Subtarget->hasDSP())) {
1328 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDSC, RC: &Mips::GPR32RegClass, Op0, Op1);
1329 }
1330 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1331 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1332 }
1333 return Register();
1334}
1335
1336Register fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1337 if (RetVT.SimpleTy != MVT::i64)
1338 return Register();
1339 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1340 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1341 }
1342 return Register();
1343}
1344
1345Register fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1346 switch (VT.SimpleTy) {
1347 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
1348 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
1349 default: return Register();
1350 }
1351}
1352
1353// FastEmit functions for ISD::ADDE.
1354
1355Register fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1356 if (RetVT.SimpleTy != MVT::i32)
1357 return Register();
1358 if ((Subtarget->hasDSP())) {
1359 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDWC, RC: &Mips::GPR32RegClass, Op0, Op1);
1360 }
1361 return Register();
1362}
1363
1364Register fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1365 switch (VT.SimpleTy) {
1366 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
1367 default: return Register();
1368 }
1369}
1370
1371// FastEmit functions for ISD::AND.
1372
1373Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1374 if (RetVT.SimpleTy != MVT::i32)
1375 return Register();
1376 if ((Subtarget->inMips16Mode())) {
1377 return fastEmitInst_rr(MachineInstOpcode: Mips::AndRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1378 }
1379 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1380 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1381 }
1382 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1383 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1384 }
1385 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1386 return fastEmitInst_rr(MachineInstOpcode: Mips::AND, RC: &Mips::GPR32RegClass, Op0, Op1);
1387 }
1388 return Register();
1389}
1390
1391Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1392 if (RetVT.SimpleTy != MVT::i64)
1393 return Register();
1394 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1395 return fastEmitInst_rr(MachineInstOpcode: Mips::AND64, RC: &Mips::GPR64RegClass, Op0, Op1);
1396 }
1397 return Register();
1398}
1399
1400Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1401 if (RetVT.SimpleTy != MVT::v16i8)
1402 return Register();
1403 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1404 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1405 }
1406 return Register();
1407}
1408
1409Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1410 if (RetVT.SimpleTy != MVT::v8i16)
1411 return Register();
1412 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1413 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1414 }
1415 return Register();
1416}
1417
1418Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1419 if (RetVT.SimpleTy != MVT::v4i32)
1420 return Register();
1421 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1422 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1423 }
1424 return Register();
1425}
1426
1427Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1428 if (RetVT.SimpleTy != MVT::v2i64)
1429 return Register();
1430 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1431 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1432 }
1433 return Register();
1434}
1435
1436Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1437 switch (VT.SimpleTy) {
1438 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1439 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1440 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1441 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1442 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1443 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1444 default: return Register();
1445 }
1446}
1447
1448// FastEmit functions for ISD::FADD.
1449
1450Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1451 if (RetVT.SimpleTy != MVT::f32)
1452 return Register();
1453 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1454 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1455 }
1456 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1457 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1458 }
1459 return Register();
1460}
1461
1462Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1463 if (RetVT.SimpleTy != MVT::f64)
1464 return Register();
1465 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1466 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1467 }
1468 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1469 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1470 }
1471 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1472 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1473 }
1474 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1475 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1476 }
1477 return Register();
1478}
1479
1480Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1481 if (RetVT.SimpleTy != MVT::v4f32)
1482 return Register();
1483 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1484 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1485 }
1486 return Register();
1487}
1488
1489Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1490 if (RetVT.SimpleTy != MVT::v2f64)
1491 return Register();
1492 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1493 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1494 }
1495 return Register();
1496}
1497
1498Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1499 switch (VT.SimpleTy) {
1500 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1501 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1502 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1503 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1504 default: return Register();
1505 }
1506}
1507
1508// FastEmit functions for ISD::FDIV.
1509
1510Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1511 if (RetVT.SimpleTy != MVT::f32)
1512 return Register();
1513 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1514 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1515 }
1516 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1517 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1518 }
1519 return Register();
1520}
1521
1522Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1523 if (RetVT.SimpleTy != MVT::f64)
1524 return Register();
1525 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1526 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1527 }
1528 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1529 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1530 }
1531 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1532 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1533 }
1534 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1535 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1536 }
1537 return Register();
1538}
1539
1540Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1541 if (RetVT.SimpleTy != MVT::v4f32)
1542 return Register();
1543 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1544 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1545 }
1546 return Register();
1547}
1548
1549Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1550 if (RetVT.SimpleTy != MVT::v2f64)
1551 return Register();
1552 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1553 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1554 }
1555 return Register();
1556}
1557
1558Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1559 switch (VT.SimpleTy) {
1560 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1561 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1562 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1563 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1564 default: return Register();
1565 }
1566}
1567
1568// FastEmit functions for ISD::FMAXNUM.
1569
1570Register fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1571 if (RetVT.SimpleTy != MVT::f32)
1572 return Register();
1573 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1574 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1575 }
1576 return Register();
1577}
1578
1579Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1580 if (RetVT.SimpleTy != MVT::f64)
1581 return Register();
1582 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1583 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1584 }
1585 return Register();
1586}
1587
1588Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1589 switch (VT.SimpleTy) {
1590 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1);
1591 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
1592 default: return Register();
1593 }
1594}
1595
1596// FastEmit functions for ISD::FMAXNUM_IEEE.
1597
1598Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1599 if (RetVT.SimpleTy != MVT::f32)
1600 return Register();
1601 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1602 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1603 }
1604 return Register();
1605}
1606
1607Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1608 if (RetVT.SimpleTy != MVT::f64)
1609 return Register();
1610 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1611 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1612 }
1613 return Register();
1614}
1615
1616Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1617 switch (VT.SimpleTy) {
1618 case MVT::f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1619 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1620 default: return Register();
1621 }
1622}
1623
1624// FastEmit functions for ISD::FMINNUM.
1625
1626Register fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1627 if (RetVT.SimpleTy != MVT::f32)
1628 return Register();
1629 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1630 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1631 }
1632 return Register();
1633}
1634
1635Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1636 if (RetVT.SimpleTy != MVT::f64)
1637 return Register();
1638 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1639 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1640 }
1641 return Register();
1642}
1643
1644Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1645 switch (VT.SimpleTy) {
1646 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1);
1647 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
1648 default: return Register();
1649 }
1650}
1651
1652// FastEmit functions for ISD::FMINNUM_IEEE.
1653
1654Register fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1655 if (RetVT.SimpleTy != MVT::f32)
1656 return Register();
1657 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1658 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1659 }
1660 return Register();
1661}
1662
1663Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1664 if (RetVT.SimpleTy != MVT::f64)
1665 return Register();
1666 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1667 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1668 }
1669 return Register();
1670}
1671
1672Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1673 switch (VT.SimpleTy) {
1674 case MVT::f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1675 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1676 default: return Register();
1677 }
1678}
1679
1680// FastEmit functions for ISD::FMUL.
1681
1682Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1683 if (RetVT.SimpleTy != MVT::f32)
1684 return Register();
1685 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1686 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1687 }
1688 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1689 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1690 }
1691 return Register();
1692}
1693
1694Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1695 if (RetVT.SimpleTy != MVT::f64)
1696 return Register();
1697 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1698 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1699 }
1700 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1701 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1702 }
1703 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1704 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1705 }
1706 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1707 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1708 }
1709 return Register();
1710}
1711
1712Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1713 if (RetVT.SimpleTy != MVT::v4f32)
1714 return Register();
1715 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1716 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1717 }
1718 return Register();
1719}
1720
1721Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1722 if (RetVT.SimpleTy != MVT::v2f64)
1723 return Register();
1724 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1725 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1726 }
1727 return Register();
1728}
1729
1730Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1731 switch (VT.SimpleTy) {
1732 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1733 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1734 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1735 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1736 default: return Register();
1737 }
1738}
1739
1740// FastEmit functions for ISD::FSUB.
1741
1742Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1743 if (RetVT.SimpleTy != MVT::f32)
1744 return Register();
1745 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1746 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1747 }
1748 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1749 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1750 }
1751 return Register();
1752}
1753
1754Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1755 if (RetVT.SimpleTy != MVT::f64)
1756 return Register();
1757 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1758 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1759 }
1760 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1761 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1762 }
1763 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1764 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1765 }
1766 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1767 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1768 }
1769 return Register();
1770}
1771
1772Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1773 if (RetVT.SimpleTy != MVT::v4f32)
1774 return Register();
1775 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1776 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1777 }
1778 return Register();
1779}
1780
1781Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1782 if (RetVT.SimpleTy != MVT::v2f64)
1783 return Register();
1784 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1785 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1786 }
1787 return Register();
1788}
1789
1790Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1791 switch (VT.SimpleTy) {
1792 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1793 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1794 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1795 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1796 default: return Register();
1797 }
1798}
1799
1800// FastEmit functions for ISD::MUL.
1801
1802Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1803 if (RetVT.SimpleTy != MVT::i32)
1804 return Register();
1805 if ((Subtarget->inMips16Mode())) {
1806 return fastEmitInst_rr(MachineInstOpcode: Mips::MultRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1807 }
1808 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1809 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1810 }
1811 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1812 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1813 }
1814 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1815 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_R6, RC: &Mips::GPR32RegClass, Op0, Op1);
1816 }
1817 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1818 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL, RC: &Mips::GPR32RegClass, Op0, Op1);
1819 }
1820 return Register();
1821}
1822
1823Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1824 if (RetVT.SimpleTy != MVT::i64)
1825 return Register();
1826 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1827 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL_R6, RC: &Mips::GPR64RegClass, Op0, Op1);
1828 }
1829 if ((Subtarget->hasCnMips())) {
1830 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL, RC: &Mips::GPR64RegClass, Op0, Op1);
1831 }
1832 return Register();
1833}
1834
1835Register fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1836 if (RetVT.SimpleTy != MVT::v16i8)
1837 return Register();
1838 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1839 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1840 }
1841 return Register();
1842}
1843
1844Register fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1845 if (RetVT.SimpleTy != MVT::v2i16)
1846 return Register();
1847 if ((Subtarget->hasDSPR2())) {
1848 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1849 }
1850 return Register();
1851}
1852
1853Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1854 if (RetVT.SimpleTy != MVT::v8i16)
1855 return Register();
1856 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1857 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1858 }
1859 return Register();
1860}
1861
1862Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1863 if (RetVT.SimpleTy != MVT::v4i32)
1864 return Register();
1865 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1866 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1867 }
1868 return Register();
1869}
1870
1871Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1872 if (RetVT.SimpleTy != MVT::v2i64)
1873 return Register();
1874 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1875 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1876 }
1877 return Register();
1878}
1879
1880Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1881 switch (VT.SimpleTy) {
1882 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1883 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1884 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1);
1885 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op1);
1886 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1887 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1888 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1889 default: return Register();
1890 }
1891}
1892
1893// FastEmit functions for ISD::MULHS.
1894
1895Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1896 if (RetVT.SimpleTy != MVT::i32)
1897 return Register();
1898 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1899 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1900 }
1901 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1902 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH, RC: &Mips::GPR32RegClass, Op0, Op1);
1903 }
1904 return Register();
1905}
1906
1907Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1908 if (RetVT.SimpleTy != MVT::i64)
1909 return Register();
1910 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1911 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUH, RC: &Mips::GPR64RegClass, Op0, Op1);
1912 }
1913 return Register();
1914}
1915
1916Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1917 switch (VT.SimpleTy) {
1918 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
1919 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
1920 default: return Register();
1921 }
1922}
1923
1924// FastEmit functions for ISD::MULHU.
1925
1926Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1927 if (RetVT.SimpleTy != MVT::i32)
1928 return Register();
1929 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1930 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1931 }
1932 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1933 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU, RC: &Mips::GPR32RegClass, Op0, Op1);
1934 }
1935 return Register();
1936}
1937
1938Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1939 if (RetVT.SimpleTy != MVT::i64)
1940 return Register();
1941 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1942 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUHU, RC: &Mips::GPR64RegClass, Op0, Op1);
1943 }
1944 return Register();
1945}
1946
1947Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1948 switch (VT.SimpleTy) {
1949 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
1950 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
1951 default: return Register();
1952 }
1953}
1954
1955// FastEmit functions for ISD::OR.
1956
1957Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1958 if (RetVT.SimpleTy != MVT::i32)
1959 return Register();
1960 if ((Subtarget->inMips16Mode())) {
1961 return fastEmitInst_rr(MachineInstOpcode: Mips::OrRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1962 }
1963 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1964 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1965 }
1966 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1967 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1968 }
1969 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1970 return fastEmitInst_rr(MachineInstOpcode: Mips::OR, RC: &Mips::GPR32RegClass, Op0, Op1);
1971 }
1972 return Register();
1973}
1974
1975Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1976 if (RetVT.SimpleTy != MVT::i64)
1977 return Register();
1978 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1979 return fastEmitInst_rr(MachineInstOpcode: Mips::OR64, RC: &Mips::GPR64RegClass, Op0, Op1);
1980 }
1981 return Register();
1982}
1983
1984Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1985 if (RetVT.SimpleTy != MVT::v16i8)
1986 return Register();
1987 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1988 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1989 }
1990 return Register();
1991}
1992
1993Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1994 if (RetVT.SimpleTy != MVT::v8i16)
1995 return Register();
1996 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1997 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1998 }
1999 return Register();
2000}
2001
2002Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2003 if (RetVT.SimpleTy != MVT::v4i32)
2004 return Register();
2005 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2006 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
2007 }
2008 return Register();
2009}
2010
2011Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2012 if (RetVT.SimpleTy != MVT::v2i64)
2013 return Register();
2014 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2015 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
2016 }
2017 return Register();
2018}
2019
2020Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2021 switch (VT.SimpleTy) {
2022 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2023 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2024 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2025 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2026 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2027 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2028 default: return Register();
2029 }
2030}
2031
2032// FastEmit functions for ISD::ROTR.
2033
2034Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2035 if (RetVT.SimpleTy != MVT::i32)
2036 return Register();
2037 if ((Subtarget->inMicroMipsMode())) {
2038 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2039 }
2040 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2041 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV, RC: &Mips::GPR32RegClass, Op0, Op1);
2042 }
2043 return Register();
2044}
2045
2046Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2047 switch (VT.SimpleTy) {
2048 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2049 default: return Register();
2050 }
2051}
2052
2053// FastEmit functions for ISD::SDIV.
2054
2055Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2056 if (RetVT.SimpleTy != MVT::i32)
2057 return Register();
2058 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2059 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2060 }
2061 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2062 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV, RC: &Mips::GPR32RegClass, Op0, Op1);
2063 }
2064 return Register();
2065}
2066
2067Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2068 if (RetVT.SimpleTy != MVT::i64)
2069 return Register();
2070 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2071 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIV, RC: &Mips::GPR64RegClass, Op0, Op1);
2072 }
2073 return Register();
2074}
2075
2076Register fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2077 if (RetVT.SimpleTy != MVT::v16i8)
2078 return Register();
2079 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2080 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2081 }
2082 return Register();
2083}
2084
2085Register fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2086 if (RetVT.SimpleTy != MVT::v8i16)
2087 return Register();
2088 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2089 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2090 }
2091 return Register();
2092}
2093
2094Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2095 if (RetVT.SimpleTy != MVT::v4i32)
2096 return Register();
2097 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2098 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2099 }
2100 return Register();
2101}
2102
2103Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2104 if (RetVT.SimpleTy != MVT::v2i64)
2105 return Register();
2106 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2107 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2108 }
2109 return Register();
2110}
2111
2112Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2113 switch (VT.SimpleTy) {
2114 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2115 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2116 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2117 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2118 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2119 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2120 default: return Register();
2121 }
2122}
2123
2124// FastEmit functions for ISD::SHL.
2125
2126Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2127 if (RetVT.SimpleTy != MVT::i32)
2128 return Register();
2129 if ((Subtarget->inMicroMipsMode())) {
2130 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2131 }
2132 if ((Subtarget->inMips16Mode())) {
2133 return fastEmitInst_rr(MachineInstOpcode: Mips::SllvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2134 }
2135 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2136 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2137 }
2138 return Register();
2139}
2140
2141Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2142 if (RetVT.SimpleTy != MVT::v16i8)
2143 return Register();
2144 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2145 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2146 }
2147 return Register();
2148}
2149
2150Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2151 if (RetVT.SimpleTy != MVT::v8i16)
2152 return Register();
2153 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2154 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2155 }
2156 return Register();
2157}
2158
2159Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2160 if (RetVT.SimpleTy != MVT::v4i32)
2161 return Register();
2162 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2163 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2164 }
2165 return Register();
2166}
2167
2168Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2169 if (RetVT.SimpleTy != MVT::v2i64)
2170 return Register();
2171 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2172 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2173 }
2174 return Register();
2175}
2176
2177Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2178 switch (VT.SimpleTy) {
2179 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2180 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
2181 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
2182 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
2183 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
2184 default: return Register();
2185 }
2186}
2187
2188// FastEmit functions for ISD::SMAX.
2189
2190Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2191 if (RetVT.SimpleTy != MVT::v16i8)
2192 return Register();
2193 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2194 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2195 }
2196 return Register();
2197}
2198
2199Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2200 if (RetVT.SimpleTy != MVT::v8i16)
2201 return Register();
2202 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2203 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2204 }
2205 return Register();
2206}
2207
2208Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2209 if (RetVT.SimpleTy != MVT::v4i32)
2210 return Register();
2211 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2212 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2213 }
2214 return Register();
2215}
2216
2217Register fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2218 if (RetVT.SimpleTy != MVT::v2i64)
2219 return Register();
2220 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2221 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2222 }
2223 return Register();
2224}
2225
2226Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2227 switch (VT.SimpleTy) {
2228 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2229 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2230 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2231 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2232 default: return Register();
2233 }
2234}
2235
2236// FastEmit functions for ISD::SMIN.
2237
2238Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2239 if (RetVT.SimpleTy != MVT::v16i8)
2240 return Register();
2241 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2242 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2243 }
2244 return Register();
2245}
2246
2247Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2248 if (RetVT.SimpleTy != MVT::v8i16)
2249 return Register();
2250 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2251 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2252 }
2253 return Register();
2254}
2255
2256Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2257 if (RetVT.SimpleTy != MVT::v4i32)
2258 return Register();
2259 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2260 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2261 }
2262 return Register();
2263}
2264
2265Register fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2266 if (RetVT.SimpleTy != MVT::v2i64)
2267 return Register();
2268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2269 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2270 }
2271 return Register();
2272}
2273
2274Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2275 switch (VT.SimpleTy) {
2276 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2277 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2278 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2279 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2280 default: return Register();
2281 }
2282}
2283
2284// FastEmit functions for ISD::SRA.
2285
2286Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2287 if (RetVT.SimpleTy != MVT::i32)
2288 return Register();
2289 if ((Subtarget->inMicroMipsMode())) {
2290 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2291 }
2292 if ((Subtarget->inMips16Mode())) {
2293 return fastEmitInst_rr(MachineInstOpcode: Mips::SravRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2294 }
2295 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2296 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV, RC: &Mips::GPR32RegClass, Op0, Op1);
2297 }
2298 return Register();
2299}
2300
2301Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2302 if (RetVT.SimpleTy != MVT::v16i8)
2303 return Register();
2304 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2305 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2306 }
2307 return Register();
2308}
2309
2310Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2311 if (RetVT.SimpleTy != MVT::v8i16)
2312 return Register();
2313 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2314 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2315 }
2316 return Register();
2317}
2318
2319Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2320 if (RetVT.SimpleTy != MVT::v4i32)
2321 return Register();
2322 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2323 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2324 }
2325 return Register();
2326}
2327
2328Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2329 if (RetVT.SimpleTy != MVT::v2i64)
2330 return Register();
2331 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2332 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2333 }
2334 return Register();
2335}
2336
2337Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2338 switch (VT.SimpleTy) {
2339 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2340 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
2341 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
2342 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
2343 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
2344 default: return Register();
2345 }
2346}
2347
2348// FastEmit functions for ISD::SREM.
2349
2350Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2351 if (RetVT.SimpleTy != MVT::i32)
2352 return Register();
2353 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2354 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2355 }
2356 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2357 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD, RC: &Mips::GPR32RegClass, Op0, Op1);
2358 }
2359 return Register();
2360}
2361
2362Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2363 if (RetVT.SimpleTy != MVT::i64)
2364 return Register();
2365 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2366 return fastEmitInst_rr(MachineInstOpcode: Mips::DMOD, RC: &Mips::GPR64RegClass, Op0, Op1);
2367 }
2368 return Register();
2369}
2370
2371Register fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2372 if (RetVT.SimpleTy != MVT::v16i8)
2373 return Register();
2374 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2375 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2376 }
2377 return Register();
2378}
2379
2380Register fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2381 if (RetVT.SimpleTy != MVT::v8i16)
2382 return Register();
2383 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2384 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2385 }
2386 return Register();
2387}
2388
2389Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2390 if (RetVT.SimpleTy != MVT::v4i32)
2391 return Register();
2392 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2393 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2394 }
2395 return Register();
2396}
2397
2398Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2399 if (RetVT.SimpleTy != MVT::v2i64)
2400 return Register();
2401 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2402 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2403 }
2404 return Register();
2405}
2406
2407Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2408 switch (VT.SimpleTy) {
2409 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2410 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2411 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2412 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2413 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2414 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2415 default: return Register();
2416 }
2417}
2418
2419// FastEmit functions for ISD::SRL.
2420
2421Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2422 if (RetVT.SimpleTy != MVT::i32)
2423 return Register();
2424 if ((Subtarget->inMicroMipsMode())) {
2425 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2426 }
2427 if ((Subtarget->inMips16Mode())) {
2428 return fastEmitInst_rr(MachineInstOpcode: Mips::SrlvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2429 }
2430 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2431 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2432 }
2433 return Register();
2434}
2435
2436Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2437 if (RetVT.SimpleTy != MVT::v16i8)
2438 return Register();
2439 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2440 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2441 }
2442 return Register();
2443}
2444
2445Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2446 if (RetVT.SimpleTy != MVT::v8i16)
2447 return Register();
2448 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2449 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2450 }
2451 return Register();
2452}
2453
2454Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2455 if (RetVT.SimpleTy != MVT::v4i32)
2456 return Register();
2457 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2458 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2459 }
2460 return Register();
2461}
2462
2463Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2464 if (RetVT.SimpleTy != MVT::v2i64)
2465 return Register();
2466 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2467 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2468 }
2469 return Register();
2470}
2471
2472Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2473 switch (VT.SimpleTy) {
2474 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2475 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
2476 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
2477 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
2478 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
2479 default: return Register();
2480 }
2481}
2482
2483// FastEmit functions for ISD::SUB.
2484
2485Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2486 if (RetVT.SimpleTy != MVT::i32)
2487 return Register();
2488 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2489 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
2490 }
2491 if ((Subtarget->inMips16Mode())) {
2492 return fastEmitInst_rr(MachineInstOpcode: Mips::SubuRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2493 }
2494 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2495 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2496 }
2497 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2498 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2499 }
2500 return Register();
2501}
2502
2503Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2504 if (RetVT.SimpleTy != MVT::i64)
2505 return Register();
2506 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2507 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2508 }
2509 return Register();
2510}
2511
2512Register fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
2513 if (RetVT.SimpleTy != MVT::v4i8)
2514 return Register();
2515 if ((Subtarget->hasDSP())) {
2516 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
2517 }
2518 return Register();
2519}
2520
2521Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2522 if (RetVT.SimpleTy != MVT::v16i8)
2523 return Register();
2524 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2525 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2526 }
2527 return Register();
2528}
2529
2530Register fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
2531 if (RetVT.SimpleTy != MVT::v2i16)
2532 return Register();
2533 if ((Subtarget->hasDSP())) {
2534 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
2535 }
2536 return Register();
2537}
2538
2539Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2540 if (RetVT.SimpleTy != MVT::v8i16)
2541 return Register();
2542 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2543 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2544 }
2545 return Register();
2546}
2547
2548Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2549 if (RetVT.SimpleTy != MVT::v4i32)
2550 return Register();
2551 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2552 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2553 }
2554 return Register();
2555}
2556
2557Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2558 if (RetVT.SimpleTy != MVT::v2i64)
2559 return Register();
2560 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2561 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2562 }
2563 return Register();
2564}
2565
2566Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2567 switch (VT.SimpleTy) {
2568 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2569 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2570 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op1);
2571 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2572 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op1);
2573 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2574 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2575 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2576 default: return Register();
2577 }
2578}
2579
2580// FastEmit functions for ISD::SUBC.
2581
2582Register fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2583 if (RetVT.SimpleTy != MVT::i32)
2584 return Register();
2585 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2586 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2587 }
2588 if ((Subtarget->inMicroMipsMode())) {
2589 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2590 }
2591 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2592 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2593 }
2594 return Register();
2595}
2596
2597Register fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2598 if (RetVT.SimpleTy != MVT::i64)
2599 return Register();
2600 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2601 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2602 }
2603 return Register();
2604}
2605
2606Register fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2607 switch (VT.SimpleTy) {
2608 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
2609 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
2610 default: return Register();
2611 }
2612}
2613
2614// FastEmit functions for ISD::UDIV.
2615
2616Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2617 if (RetVT.SimpleTy != MVT::i32)
2618 return Register();
2619 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2620 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2621 }
2622 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2623 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU, RC: &Mips::GPR32RegClass, Op0, Op1);
2624 }
2625 return Register();
2626}
2627
2628Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2629 if (RetVT.SimpleTy != MVT::i64)
2630 return Register();
2631 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2632 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIVU, RC: &Mips::GPR64RegClass, Op0, Op1);
2633 }
2634 return Register();
2635}
2636
2637Register fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2638 if (RetVT.SimpleTy != MVT::v16i8)
2639 return Register();
2640 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2641 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2642 }
2643 return Register();
2644}
2645
2646Register fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2647 if (RetVT.SimpleTy != MVT::v8i16)
2648 return Register();
2649 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2650 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2651 }
2652 return Register();
2653}
2654
2655Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2656 if (RetVT.SimpleTy != MVT::v4i32)
2657 return Register();
2658 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2659 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2660 }
2661 return Register();
2662}
2663
2664Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2665 if (RetVT.SimpleTy != MVT::v2i64)
2666 return Register();
2667 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2668 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2669 }
2670 return Register();
2671}
2672
2673Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2674 switch (VT.SimpleTy) {
2675 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2676 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2677 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2678 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2679 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2680 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2681 default: return Register();
2682 }
2683}
2684
2685// FastEmit functions for ISD::UMAX.
2686
2687Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2688 if (RetVT.SimpleTy != MVT::v16i8)
2689 return Register();
2690 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2691 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2692 }
2693 return Register();
2694}
2695
2696Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2697 if (RetVT.SimpleTy != MVT::v8i16)
2698 return Register();
2699 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2700 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2701 }
2702 return Register();
2703}
2704
2705Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2706 if (RetVT.SimpleTy != MVT::v4i32)
2707 return Register();
2708 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2709 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2710 }
2711 return Register();
2712}
2713
2714Register fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2715 if (RetVT.SimpleTy != MVT::v2i64)
2716 return Register();
2717 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2718 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2719 }
2720 return Register();
2721}
2722
2723Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2724 switch (VT.SimpleTy) {
2725 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2726 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2727 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2728 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2729 default: return Register();
2730 }
2731}
2732
2733// FastEmit functions for ISD::UMIN.
2734
2735Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2736 if (RetVT.SimpleTy != MVT::v16i8)
2737 return Register();
2738 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2739 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2740 }
2741 return Register();
2742}
2743
2744Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2745 if (RetVT.SimpleTy != MVT::v8i16)
2746 return Register();
2747 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2748 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2749 }
2750 return Register();
2751}
2752
2753Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2754 if (RetVT.SimpleTy != MVT::v4i32)
2755 return Register();
2756 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2757 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2758 }
2759 return Register();
2760}
2761
2762Register fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2763 if (RetVT.SimpleTy != MVT::v2i64)
2764 return Register();
2765 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2766 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2767 }
2768 return Register();
2769}
2770
2771Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2772 switch (VT.SimpleTy) {
2773 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2774 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2775 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2776 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2777 default: return Register();
2778 }
2779}
2780
2781// FastEmit functions for ISD::UREM.
2782
2783Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2784 if (RetVT.SimpleTy != MVT::i32)
2785 return Register();
2786 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2787 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2788 }
2789 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2790 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU, RC: &Mips::GPR32RegClass, Op0, Op1);
2791 }
2792 return Register();
2793}
2794
2795Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2796 if (RetVT.SimpleTy != MVT::i64)
2797 return Register();
2798 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2799 return fastEmitInst_rr(MachineInstOpcode: Mips::DMODU, RC: &Mips::GPR64RegClass, Op0, Op1);
2800 }
2801 return Register();
2802}
2803
2804Register fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2805 if (RetVT.SimpleTy != MVT::v16i8)
2806 return Register();
2807 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2808 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2809 }
2810 return Register();
2811}
2812
2813Register fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2814 if (RetVT.SimpleTy != MVT::v8i16)
2815 return Register();
2816 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2817 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2818 }
2819 return Register();
2820}
2821
2822Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2823 if (RetVT.SimpleTy != MVT::v4i32)
2824 return Register();
2825 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2826 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2827 }
2828 return Register();
2829}
2830
2831Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2832 if (RetVT.SimpleTy != MVT::v2i64)
2833 return Register();
2834 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2835 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2836 }
2837 return Register();
2838}
2839
2840Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2841 switch (VT.SimpleTy) {
2842 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2843 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2844 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2845 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2846 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2847 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2848 default: return Register();
2849 }
2850}
2851
2852// FastEmit functions for ISD::XOR.
2853
2854Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2855 if (RetVT.SimpleTy != MVT::i32)
2856 return Register();
2857 if ((Subtarget->inMips16Mode())) {
2858 return fastEmitInst_rr(MachineInstOpcode: Mips::XorRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2859 }
2860 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2861 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2862 }
2863 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2864 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2865 }
2866 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2867 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR, RC: &Mips::GPR32RegClass, Op0, Op1);
2868 }
2869 return Register();
2870}
2871
2872Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2873 if (RetVT.SimpleTy != MVT::i64)
2874 return Register();
2875 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2876 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR64, RC: &Mips::GPR64RegClass, Op0, Op1);
2877 }
2878 return Register();
2879}
2880
2881Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2882 if (RetVT.SimpleTy != MVT::v16i8)
2883 return Register();
2884 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2885 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
2886 }
2887 return Register();
2888}
2889
2890Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2891 if (RetVT.SimpleTy != MVT::v8i16)
2892 return Register();
2893 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2894 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
2895 }
2896 return Register();
2897}
2898
2899Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2900 if (RetVT.SimpleTy != MVT::v4i32)
2901 return Register();
2902 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2903 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
2904 }
2905 return Register();
2906}
2907
2908Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2909 if (RetVT.SimpleTy != MVT::v2i64)
2910 return Register();
2911 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2912 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
2913 }
2914 return Register();
2915}
2916
2917Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2918 switch (VT.SimpleTy) {
2919 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2920 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2921 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2922 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2923 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2924 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2925 default: return Register();
2926 }
2927}
2928
2929// FastEmit functions for MipsISD::BuildPairF64.
2930
2931Register fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2932 if (RetVT.SimpleTy != MVT::f64)
2933 return Register();
2934 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
2935 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_64, RC: &Mips::FGR64RegClass, Op0, Op1);
2936 }
2937 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
2938 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64, RC: &Mips::AFGR64RegClass, Op0, Op1);
2939 }
2940 return Register();
2941}
2942
2943Register fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2944 switch (VT.SimpleTy) {
2945 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op1);
2946 default: return Register();
2947 }
2948}
2949
2950// FastEmit functions for MipsISD::DivRem.
2951
2952Register fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2953 if (RetVT.SimpleTy != MVT::Untyped)
2954 return Register();
2955 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2956 return fastEmitInst_rr(MachineInstOpcode: Mips::SDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
2957 }
2958 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2959 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoSDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
2960 }
2961 return Register();
2962}
2963
2964Register fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2965 if (RetVT.SimpleTy != MVT::Untyped)
2966 return Register();
2967 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2968 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDSDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
2969 }
2970 return Register();
2971}
2972
2973Register fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2974 switch (VT.SimpleTy) {
2975 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op1);
2976 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op1);
2977 default: return Register();
2978 }
2979}
2980
2981// FastEmit functions for MipsISD::DivRem16.
2982
2983Register fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2984 if (RetVT.SimpleTy != MVT::isVoid)
2985 return Register();
2986 if ((Subtarget->inMips16Mode())) {
2987 return fastEmitInst_rr(MachineInstOpcode: Mips::DivRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2988 }
2989 return Register();
2990}
2991
2992Register fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2993 switch (VT.SimpleTy) {
2994 case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op1);
2995 default: return Register();
2996 }
2997}
2998
2999// FastEmit functions for MipsISD::DivRemU.
3000
3001Register fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3002 if (RetVT.SimpleTy != MVT::Untyped)
3003 return Register();
3004 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3005 return fastEmitInst_rr(MachineInstOpcode: Mips::UDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3006 }
3007 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3008 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoUDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3009 }
3010 return Register();
3011}
3012
3013Register fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3014 if (RetVT.SimpleTy != MVT::Untyped)
3015 return Register();
3016 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3017 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDUDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3018 }
3019 return Register();
3020}
3021
3022Register fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3023 switch (VT.SimpleTy) {
3024 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op1);
3025 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op1);
3026 default: return Register();
3027 }
3028}
3029
3030// FastEmit functions for MipsISD::DivRemU16.
3031
3032Register fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3033 if (RetVT.SimpleTy != MVT::isVoid)
3034 return Register();
3035 if ((Subtarget->inMips16Mode())) {
3036 return fastEmitInst_rr(MachineInstOpcode: Mips::DivuRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3037 }
3038 return Register();
3039}
3040
3041Register fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3042 switch (VT.SimpleTy) {
3043 case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op1);
3044 default: return Register();
3045 }
3046}
3047
3048// FastEmit functions for MipsISD::EH_RETURN.
3049
3050Register fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3051 if (RetVT.SimpleTy != MVT::isVoid)
3052 return Register();
3053 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return32, RC: &Mips::GPR32RegClass, Op0, Op1);
3054}
3055
3056Register fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3057 if (RetVT.SimpleTy != MVT::isVoid)
3058 return Register();
3059 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return64, RC: &Mips::GPR64RegClass, Op0, Op1);
3060}
3061
3062Register fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3063 switch (VT.SimpleTy) {
3064 case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op1);
3065 case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op1);
3066 default: return Register();
3067 }
3068}
3069
3070// FastEmit functions for MipsISD::ILVEV.
3071
3072Register fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3073 if (RetVT.SimpleTy != MVT::v16i8)
3074 return Register();
3075 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3076 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3077 }
3078 return Register();
3079}
3080
3081Register fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3082 if (RetVT.SimpleTy != MVT::v8i16)
3083 return Register();
3084 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3085 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3086 }
3087 return Register();
3088}
3089
3090Register fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3091 if (RetVT.SimpleTy != MVT::v4i32)
3092 return Register();
3093 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3094 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3095 }
3096 return Register();
3097}
3098
3099Register fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3100 if (RetVT.SimpleTy != MVT::v2i64)
3101 return Register();
3102 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3103 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3104 }
3105 return Register();
3106}
3107
3108Register fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3109 switch (VT.SimpleTy) {
3110 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3111 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3112 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3113 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3114 default: return Register();
3115 }
3116}
3117
3118// FastEmit functions for MipsISD::ILVL.
3119
3120Register fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3121 if (RetVT.SimpleTy != MVT::v16i8)
3122 return Register();
3123 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3124 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3125 }
3126 return Register();
3127}
3128
3129Register fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3130 if (RetVT.SimpleTy != MVT::v8i16)
3131 return Register();
3132 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3133 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3134 }
3135 return Register();
3136}
3137
3138Register fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3139 if (RetVT.SimpleTy != MVT::v4i32)
3140 return Register();
3141 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3142 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3143 }
3144 return Register();
3145}
3146
3147Register fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3148 if (RetVT.SimpleTy != MVT::v2i64)
3149 return Register();
3150 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3151 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3152 }
3153 return Register();
3154}
3155
3156Register fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3157 switch (VT.SimpleTy) {
3158 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op1);
3159 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op1);
3160 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op1);
3161 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op1);
3162 default: return Register();
3163 }
3164}
3165
3166// FastEmit functions for MipsISD::ILVOD.
3167
3168Register fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3169 if (RetVT.SimpleTy != MVT::v16i8)
3170 return Register();
3171 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3172 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3173 }
3174 return Register();
3175}
3176
3177Register fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3178 if (RetVT.SimpleTy != MVT::v8i16)
3179 return Register();
3180 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3181 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3182 }
3183 return Register();
3184}
3185
3186Register fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3187 if (RetVT.SimpleTy != MVT::v4i32)
3188 return Register();
3189 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3190 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3191 }
3192 return Register();
3193}
3194
3195Register fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3196 if (RetVT.SimpleTy != MVT::v2i64)
3197 return Register();
3198 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3199 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3200 }
3201 return Register();
3202}
3203
3204Register fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3205 switch (VT.SimpleTy) {
3206 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3207 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3208 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3209 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3210 default: return Register();
3211 }
3212}
3213
3214// FastEmit functions for MipsISD::ILVR.
3215
3216Register fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3217 if (RetVT.SimpleTy != MVT::v16i8)
3218 return Register();
3219 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3220 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3221 }
3222 return Register();
3223}
3224
3225Register fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3226 if (RetVT.SimpleTy != MVT::v8i16)
3227 return Register();
3228 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3229 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3230 }
3231 return Register();
3232}
3233
3234Register fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3235 if (RetVT.SimpleTy != MVT::v4i32)
3236 return Register();
3237 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3238 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3239 }
3240 return Register();
3241}
3242
3243Register fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3244 if (RetVT.SimpleTy != MVT::v2i64)
3245 return Register();
3246 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3247 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3248 }
3249 return Register();
3250}
3251
3252Register fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3253 switch (VT.SimpleTy) {
3254 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op1);
3255 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op1);
3256 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op1);
3257 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op1);
3258 default: return Register();
3259 }
3260}
3261
3262// FastEmit functions for MipsISD::MTLOHI.
3263
3264Register fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3265 if (RetVT.SimpleTy != MVT::Untyped)
3266 return Register();
3267 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3268 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3269 }
3270 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) {
3271 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3272 }
3273 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3274 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI, RC: &Mips::ACC64RegClass, Op0, Op1);
3275 }
3276 return Register();
3277}
3278
3279Register fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3280 if (RetVT.SimpleTy != MVT::Untyped)
3281 return Register();
3282 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3283 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI64, RC: &Mips::ACC128RegClass, Op0, Op1);
3284 }
3285 return Register();
3286}
3287
3288Register fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3289 switch (VT.SimpleTy) {
3290 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op1);
3291 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op1);
3292 default: return Register();
3293 }
3294}
3295
3296// FastEmit functions for MipsISD::Mult.
3297
3298Register fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3299 if (RetVT.SimpleTy != MVT::Untyped)
3300 return Register();
3301 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3302 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3303 }
3304 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3305 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3306 }
3307 if ((Subtarget->hasDSP())) {
3308 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3309 }
3310 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3311 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT, RC: &Mips::ACC64RegClass, Op0, Op1);
3312 }
3313 return Register();
3314}
3315
3316Register fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3317 if (RetVT.SimpleTy != MVT::Untyped)
3318 return Register();
3319 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3320 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULT, RC: &Mips::ACC128RegClass, Op0, Op1);
3321 }
3322 return Register();
3323}
3324
3325Register fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3326 switch (VT.SimpleTy) {
3327 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op1);
3328 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op1);
3329 default: return Register();
3330 }
3331}
3332
3333// FastEmit functions for MipsISD::Multu.
3334
3335Register fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3336 if (RetVT.SimpleTy != MVT::Untyped)
3337 return Register();
3338 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3339 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3340 }
3341 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3342 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3343 }
3344 if ((Subtarget->hasDSP())) {
3345 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3346 }
3347 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3348 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu, RC: &Mips::ACC64RegClass, Op0, Op1);
3349 }
3350 return Register();
3351}
3352
3353Register fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3354 if (RetVT.SimpleTy != MVT::Untyped)
3355 return Register();
3356 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3357 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULTu, RC: &Mips::ACC128RegClass, Op0, Op1);
3358 }
3359 return Register();
3360}
3361
3362Register fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3363 switch (VT.SimpleTy) {
3364 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op1);
3365 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op1);
3366 default: return Register();
3367 }
3368}
3369
3370// FastEmit functions for MipsISD::PCKEV.
3371
3372Register fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3373 if (RetVT.SimpleTy != MVT::v16i8)
3374 return Register();
3375 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3376 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3377 }
3378 return Register();
3379}
3380
3381Register fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3382 if (RetVT.SimpleTy != MVT::v8i16)
3383 return Register();
3384 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3385 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3386 }
3387 return Register();
3388}
3389
3390Register fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3391 if (RetVT.SimpleTy != MVT::v4i32)
3392 return Register();
3393 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3394 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3395 }
3396 return Register();
3397}
3398
3399Register fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3400 if (RetVT.SimpleTy != MVT::v2i64)
3401 return Register();
3402 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3403 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3404 }
3405 return Register();
3406}
3407
3408Register fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3409 switch (VT.SimpleTy) {
3410 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3411 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3412 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3413 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3414 default: return Register();
3415 }
3416}
3417
3418// FastEmit functions for MipsISD::PCKOD.
3419
3420Register fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3421 if (RetVT.SimpleTy != MVT::v16i8)
3422 return Register();
3423 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3424 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3425 }
3426 return Register();
3427}
3428
3429Register fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3430 if (RetVT.SimpleTy != MVT::v8i16)
3431 return Register();
3432 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3433 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3434 }
3435 return Register();
3436}
3437
3438Register fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3439 if (RetVT.SimpleTy != MVT::v4i32)
3440 return Register();
3441 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3442 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3443 }
3444 return Register();
3445}
3446
3447Register fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3448 if (RetVT.SimpleTy != MVT::v2i64)
3449 return Register();
3450 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3451 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3452 }
3453 return Register();
3454}
3455
3456Register fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3457 switch (VT.SimpleTy) {
3458 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3459 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3460 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3461 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3462 default: return Register();
3463 }
3464}
3465
3466// FastEmit functions for MipsISD::VNOR.
3467
3468Register fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3469 if (RetVT.SimpleTy != MVT::v16i8)
3470 return Register();
3471 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3472 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3473 }
3474 return Register();
3475}
3476
3477Register fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3478 if (RetVT.SimpleTy != MVT::v8i16)
3479 return Register();
3480 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3481 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3482 }
3483 return Register();
3484}
3485
3486Register fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3487 if (RetVT.SimpleTy != MVT::v4i32)
3488 return Register();
3489 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3490 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3491 }
3492 return Register();
3493}
3494
3495Register fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3496 if (RetVT.SimpleTy != MVT::v2i64)
3497 return Register();
3498 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3499 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3500 }
3501 return Register();
3502}
3503
3504Register fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3505 switch (VT.SimpleTy) {
3506 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3507 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3508 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3509 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3510 default: return Register();
3511 }
3512}
3513
3514// Top-level FastEmit function.
3515
3516Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
3517 switch (Opcode) {
3518 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
3519 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
3520 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
3521 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
3522 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
3523 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
3524 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
3525 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3526 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
3527 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3528 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
3529 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
3530 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
3531 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
3532 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
3533 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
3534 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
3535 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
3536 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
3537 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
3538 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
3539 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
3540 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
3541 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
3542 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
3543 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
3544 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
3545 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
3546 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
3547 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
3548 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
3549 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op1);
3550 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op1);
3551 case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op1);
3552 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op1);
3553 case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op1);
3554 case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op1);
3555 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op1);
3556 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op1);
3557 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op1);
3558 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op1);
3559 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op1);
3560 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op1);
3561 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op1);
3562 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op1);
3563 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op1);
3564 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op1);
3565 default: return Register();
3566 }
3567}
3568
3569// FastEmit functions for MipsISD::ExtractElementF64.
3570
3571Register fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3572 if (RetVT.SimpleTy != MVT::i32)
3573 return Register();
3574 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3575 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64_64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3576 }
3577 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3578 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3579 }
3580 return Register();
3581}
3582
3583Register fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3584 switch (VT.SimpleTy) {
3585 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, imm1);
3586 default: return Register();
3587 }
3588}
3589
3590// FastEmit functions for MipsISD::SHLL_DSP.
3591
3592Register fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3593 if (RetVT.SimpleTy != MVT::v4i8)
3594 return Register();
3595 if ((Subtarget->hasDSP())) {
3596 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3597 }
3598 return Register();
3599}
3600
3601Register fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3602 if (RetVT.SimpleTy != MVT::v2i16)
3603 return Register();
3604 if ((Subtarget->hasDSP())) {
3605 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3606 }
3607 return Register();
3608}
3609
3610Register fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3611 switch (VT.SimpleTy) {
3612 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3613 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3614 default: return Register();
3615 }
3616}
3617
3618// FastEmit functions for MipsISD::SHRA_DSP.
3619
3620Register fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3621 if (RetVT.SimpleTy != MVT::v4i8)
3622 return Register();
3623 if ((Subtarget->hasDSPR2())) {
3624 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3625 }
3626 return Register();
3627}
3628
3629Register fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3630 if (RetVT.SimpleTy != MVT::v2i16)
3631 return Register();
3632 if ((Subtarget->hasDSP())) {
3633 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3634 }
3635 return Register();
3636}
3637
3638Register fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3639 switch (VT.SimpleTy) {
3640 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3641 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3642 default: return Register();
3643 }
3644}
3645
3646// FastEmit functions for MipsISD::SHRL_DSP.
3647
3648Register fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3649 if (RetVT.SimpleTy != MVT::v4i8)
3650 return Register();
3651 if ((Subtarget->hasDSP())) {
3652 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3653 }
3654 return Register();
3655}
3656
3657Register fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3658 if (RetVT.SimpleTy != MVT::v2i16)
3659 return Register();
3660 if ((Subtarget->hasDSPR2())) {
3661 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3662 }
3663 return Register();
3664}
3665
3666Register fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3667 switch (VT.SimpleTy) {
3668 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3669 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3670 default: return Register();
3671 }
3672}
3673
3674// Top-level FastEmit function.
3675
3676Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
3677 if (VT == MVT::i32 && Predicate_immZExt5(Imm: imm1))
3678 if (Register Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, imm1))
3679 return Reg;
3680
3681 if (VT == MVT::i32 && Predicate_immZExt6(Imm: imm1))
3682 if (Register Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, imm1))
3683 return Reg;
3684
3685 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(Imm: imm1))
3686 if (Register Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, imm1))
3687 return Reg;
3688
3689 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(Imm: imm1))
3690 if (Register Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, imm1))
3691 return Reg;
3692
3693 if (VT == MVT::i32 && Predicate_immZExt4(Imm: imm1))
3694 if (Register Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, imm1))
3695 return Reg;
3696
3697 if (VT == MVT::i32 && Predicate_immSExtAddiur2(Imm: imm1))
3698 if (Register Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, imm1))
3699 return Reg;
3700
3701 if (VT == MVT::i32 && Predicate_immSExtAddius5(Imm: imm1))
3702 if (Register Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, imm1))
3703 return Reg;
3704
3705 if (VT == MVT::i32 && Predicate_immZExtAndi16(Imm: imm1))
3706 if (Register Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, imm1))
3707 return Reg;
3708
3709 if (VT == MVT::i32 && Predicate_immZExt2Shift(Imm: imm1))
3710 if (Register Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, imm1))
3711 return Reg;
3712
3713 switch (Opcode) {
3714 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, imm1);
3715 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, imm1);
3716 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, imm1);
3717 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, imm1);
3718 default: return Register();
3719 }
3720}
3721
3722// FastEmit functions for ISD::ROTR.
3723
3724Register fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3725 if (RetVT.SimpleTy != MVT::i32)
3726 return Register();
3727 if ((Subtarget->inMicroMipsMode())) {
3728 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3729 }
3730 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3731 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3732 }
3733 return Register();
3734}
3735
3736Register fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3737 switch (VT.SimpleTy) {
3738 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3739 default: return Register();
3740 }
3741}
3742
3743// FastEmit functions for ISD::SHL.
3744
3745Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3746 if (RetVT.SimpleTy != MVT::i32)
3747 return Register();
3748 if ((Subtarget->inMicroMipsMode())) {
3749 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3750 }
3751 if ((Subtarget->inMips16Mode())) {
3752 return fastEmitInst_ri(MachineInstOpcode: Mips::SllX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3753 }
3754 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3755 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3756 }
3757 return Register();
3758}
3759
3760Register fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3761 switch (VT.SimpleTy) {
3762 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3763 default: return Register();
3764 }
3765}
3766
3767// FastEmit functions for ISD::SRA.
3768
3769Register fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3770 if (RetVT.SimpleTy != MVT::i32)
3771 return Register();
3772 if ((Subtarget->inMicroMipsMode())) {
3773 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3774 }
3775 if ((Subtarget->inMips16Mode())) {
3776 return fastEmitInst_ri(MachineInstOpcode: Mips::SraX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3777 }
3778 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3779 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3780 }
3781 return Register();
3782}
3783
3784Register fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3785 switch (VT.SimpleTy) {
3786 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3787 default: return Register();
3788 }
3789}
3790
3791// FastEmit functions for ISD::SRL.
3792
3793Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3794 if (RetVT.SimpleTy != MVT::i32)
3795 return Register();
3796 if ((Subtarget->inMicroMipsMode())) {
3797 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3798 }
3799 if ((Subtarget->inMips16Mode())) {
3800 return fastEmitInst_ri(MachineInstOpcode: Mips::SrlX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3801 }
3802 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3803 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3804 }
3805 return Register();
3806}
3807
3808Register fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3809 switch (VT.SimpleTy) {
3810 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3811 default: return Register();
3812 }
3813}
3814
3815// Top-level FastEmit function.
3816
3817Register fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3818 switch (Opcode) {
3819 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3820 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3821 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3822 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3823 default: return Register();
3824 }
3825}
3826
3827// FastEmit functions for ISD::ROTR.
3828
3829Register fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3830 if (RetVT.SimpleTy != MVT::i64)
3831 return Register();
3832 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3833 return fastEmitInst_ri(MachineInstOpcode: Mips::DROTR, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3834 }
3835 return Register();
3836}
3837
3838Register fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3839 switch (VT.SimpleTy) {
3840 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3841 default: return Register();
3842 }
3843}
3844
3845// FastEmit functions for ISD::SHL.
3846
3847Register fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3848 if (RetVT.SimpleTy != MVT::i64)
3849 return Register();
3850 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3851 return fastEmitInst_ri(MachineInstOpcode: Mips::DSLL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3852 }
3853 return Register();
3854}
3855
3856Register fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3857 switch (VT.SimpleTy) {
3858 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3859 default: return Register();
3860 }
3861}
3862
3863// FastEmit functions for ISD::SRA.
3864
3865Register fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3866 if (RetVT.SimpleTy != MVT::i64)
3867 return Register();
3868 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3869 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRA, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3870 }
3871 return Register();
3872}
3873
3874Register fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3875 switch (VT.SimpleTy) {
3876 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3877 default: return Register();
3878 }
3879}
3880
3881// FastEmit functions for ISD::SRL.
3882
3883Register fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3884 if (RetVT.SimpleTy != MVT::i64)
3885 return Register();
3886 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3887 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3888 }
3889 return Register();
3890}
3891
3892Register fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3893 switch (VT.SimpleTy) {
3894 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3895 default: return Register();
3896 }
3897}
3898
3899// Top-level FastEmit function.
3900
3901Register fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3902 switch (Opcode) {
3903 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3904 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3905 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3906 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3907 default: return Register();
3908 }
3909}
3910
3911// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3912
3913Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
3914 if (RetVT.SimpleTy != MVT::f32)
3915 return Register();
3916 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3917 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FW_PSEUDO, RC: &Mips::FGR32RegClass, Op0, Imm: imm1);
3918 }
3919 return Register();
3920}
3921
3922Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3923 switch (VT.SimpleTy) {
3924 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, imm1);
3925 default: return Register();
3926 }
3927}
3928
3929// Top-level FastEmit function.
3930
3931Register fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3932 switch (Opcode) {
3933 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, imm1);
3934 default: return Register();
3935 }
3936}
3937
3938// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3939
3940Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
3941 if (RetVT.SimpleTy != MVT::f64)
3942 return Register();
3943 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3944 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FD_PSEUDO, RC: &Mips::FGR64RegClass, Op0, Imm: imm1);
3945 }
3946 return Register();
3947}
3948
3949Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3950 switch (VT.SimpleTy) {
3951 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, imm1);
3952 default: return Register();
3953 }
3954}
3955
3956// Top-level FastEmit function.
3957
3958Register fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3959 switch (Opcode) {
3960 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, imm1);
3961 default: return Register();
3962 }
3963}
3964
3965// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3966
3967Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, Register Op0, uint64_t imm1) {
3968 if (RetVT.SimpleTy != MVT::i32)
3969 return Register();
3970 if ((Subtarget->hasMSA())) {
3971 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_S_W, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3972 }
3973 return Register();
3974}
3975
3976Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3977 switch (VT.SimpleTy) {
3978 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, imm1);
3979 default: return Register();
3980 }
3981}
3982
3983// Top-level FastEmit function.
3984
3985Register fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3986 switch (Opcode) {
3987 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, imm1);
3988 default: return Register();
3989 }
3990}
3991
3992// FastEmit functions for ISD::ADD.
3993
3994Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, Register Op0, uint64_t imm1) {
3995 if (RetVT.SimpleTy != MVT::i32)
3996 return Register();
3997 if ((Subtarget->inMicroMipsMode())) {
3998 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUR2_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
3999 }
4000 return Register();
4001}
4002
4003Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4004 switch (VT.SimpleTy) {
4005 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, imm1);
4006 default: return Register();
4007 }
4008}
4009
4010// Top-level FastEmit function.
4011
4012Register fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4013 switch (Opcode) {
4014 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, imm1);
4015 default: return Register();
4016 }
4017}
4018
4019// FastEmit functions for ISD::ADD.
4020
4021Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, Register Op0, uint64_t imm1) {
4022 if (RetVT.SimpleTy != MVT::i32)
4023 return Register();
4024 if ((Subtarget->inMicroMipsMode())) {
4025 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUS5_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4026 }
4027 return Register();
4028}
4029
4030Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4031 switch (VT.SimpleTy) {
4032 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, imm1);
4033 default: return Register();
4034 }
4035}
4036
4037// Top-level FastEmit function.
4038
4039Register fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4040 switch (Opcode) {
4041 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, imm1);
4042 default: return Register();
4043 }
4044}
4045
4046// FastEmit functions for ISD::AND.
4047
4048Register fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, Register Op0, uint64_t imm1) {
4049 if (RetVT.SimpleTy != MVT::i32)
4050 return Register();
4051 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
4052 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4053 }
4054 if ((Subtarget->inMicroMipsMode())) {
4055 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4056 }
4057 return Register();
4058}
4059
4060Register fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4061 switch (VT.SimpleTy) {
4062 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, imm1);
4063 default: return Register();
4064 }
4065}
4066
4067// Top-level FastEmit function.
4068
4069Register fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4070 switch (Opcode) {
4071 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, imm1);
4072 default: return Register();
4073 }
4074}
4075
4076// FastEmit functions for ISD::SHL.
4077
4078Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4079 if (RetVT.SimpleTy != MVT::i32)
4080 return Register();
4081 if ((Subtarget->inMicroMipsMode())) {
4082 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4083 }
4084 return Register();
4085}
4086
4087Register fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4088 switch (VT.SimpleTy) {
4089 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4090 default: return Register();
4091 }
4092}
4093
4094// FastEmit functions for ISD::SRL.
4095
4096Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4097 if (RetVT.SimpleTy != MVT::i32)
4098 return Register();
4099 if ((Subtarget->inMicroMipsMode())) {
4100 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4101 }
4102 return Register();
4103}
4104
4105Register fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4106 switch (VT.SimpleTy) {
4107 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4108 default: return Register();
4109 }
4110}
4111
4112// Top-level FastEmit function.
4113
4114Register fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4115 switch (Opcode) {
4116 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4117 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4118 default: return Register();
4119 }
4120}
4121
4122// FastEmit functions for ISD::Constant.
4123
4124Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4125 if (RetVT.SimpleTy != MVT::i32)
4126 return Register();
4127 if ((Subtarget->inMips16Mode())) {
4128 return fastEmitInst_i(MachineInstOpcode: Mips::LwConstant32, RC: &Mips::CPU16RegsRegClass, Imm: imm0);
4129 }
4130 return Register();
4131}
4132
4133Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4134 switch (VT.SimpleTy) {
4135 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4136 default: return Register();
4137 }
4138}
4139
4140// Top-level FastEmit function.
4141
4142Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4143 switch (Opcode) {
4144 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4145 default: return Register();
4146 }
4147}
4148
4149