1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the PPC target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_imm32SExt16(int64_t Imm) {
12
13 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
14 // sign extended field. Used by instructions like 'addi'.
15 return (int32_t)Imm == (short)Imm;
16
17}
18static bool Predicate_imm64SExt16(int64_t Imm) {
19
20 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
21 // sign extended field. Used by instructions like 'addi'.
22 return (int64_t)Imm == (short)Imm;
23
24}
25static bool Predicate_immSExt5NonZero(int64_t Imm) {
26 return Imm && isInt<5>(x: Imm);
27}
28static bool Predicate_i32immNonAllOneNonZero(int64_t Imm) {
29 return Imm && (Imm != -1);
30}
31
32
33// FastEmit functions for ISD::READCYCLECOUNTER.
34
35Register fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
36 if (RetVT.SimpleTy != MVT::i64)
37 return Register();
38 return fastEmitInst_(MachineInstOpcode: PPC::MFTB8, RC: &PPC::G8RCRegClass);
39}
40
41Register fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
42 switch (VT.SimpleTy) {
43 case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
44 default: return Register();
45 }
46}
47
48// FastEmit functions for PPCISD::GET_TPOINTER.
49
50Register fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(MVT RetVT) {
51 if (RetVT.SimpleTy != MVT::i32)
52 return Register();
53 return fastEmitInst_(MachineInstOpcode: PPC::GETtlsTpointer32AIX, RC: &PPC::GPRCRegClass);
54}
55
56Register fastEmit_PPCISD_GET_TPOINTER_(MVT VT, MVT RetVT) {
57 switch (VT.SimpleTy) {
58 case MVT::i32: return fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(RetVT);
59 default: return Register();
60 }
61}
62
63// FastEmit functions for PPCISD::MFFS.
64
65Register fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
66 if (RetVT.SimpleTy != MVT::f64)
67 return Register();
68 if ((Subtarget->hasFPU())) {
69 return fastEmitInst_(MachineInstOpcode: PPC::MFFS, RC: &PPC::F8RCRegClass);
70 }
71 return Register();
72}
73
74Register fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
75 switch (VT.SimpleTy) {
76 case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
77 default: return Register();
78 }
79}
80
81// FastEmit functions for PPCISD::PPC32_GOT.
82
83Register fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
84 if (RetVT.SimpleTy != MVT::i32)
85 return Register();
86 return fastEmitInst_(MachineInstOpcode: PPC::PPC32GOT, RC: &PPC::GPRCRegClass);
87}
88
89Register fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
90 switch (VT.SimpleTy) {
91 case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
92 default: return Register();
93 }
94}
95
96// Top-level FastEmit function.
97
98Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
99 switch (Opcode) {
100 case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
101 case PPCISD::GET_TPOINTER: return fastEmit_PPCISD_GET_TPOINTER_(VT, RetVT);
102 case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
103 case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
104 default: return Register();
105 }
106}
107
108// FastEmit functions for ISD::ANY_EXTEND.
109
110Register fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
111 if ((Subtarget->isISA3_1())) {
112 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
113 }
114 return Register();
115}
116
117Register fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
118 if ((Subtarget->isISA3_1())) {
119 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC8, RC: &PPC::G8RCRegClass, Op0);
120 }
121 return Register();
122}
123
124Register fastEmit_ISD_ANY_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
125switch (RetVT.SimpleTy) {
126 case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Op0);
127 case MVT::i64: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Op0);
128 default: return Register();
129}
130}
131
132Register fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
133 switch (VT.SimpleTy) {
134 case MVT::i1: return fastEmit_ISD_ANY_EXTEND_MVT_i1_r(RetVT, Op0);
135 default: return Register();
136 }
137}
138
139// FastEmit functions for ISD::BITCAST.
140
141Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
142 if (RetVT.SimpleTy != MVT::f64)
143 return Register();
144 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
145 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRD, RC: &PPC::VSFRCRegClass, Op0);
146 }
147 return Register();
148}
149
150Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
151 if (RetVT.SimpleTy != MVT::i64)
152 return Register();
153 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
154 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRD, RC: &PPC::G8RCRegClass, Op0);
155 }
156 return Register();
157}
158
159Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
160 switch (VT.SimpleTy) {
161 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
162 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
163 default: return Register();
164 }
165}
166
167// FastEmit functions for ISD::BSWAP.
168
169Register fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::i32)
171 return Register();
172 if ((Subtarget->isISA3_1())) {
173 return fastEmitInst_r(MachineInstOpcode: PPC::BRW, RC: &PPC::GPRCRegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, Register Op0) {
179 if (RetVT.SimpleTy != MVT::i64)
180 return Register();
181 if ((Subtarget->isISA3_1())) {
182 return fastEmitInst_r(MachineInstOpcode: PPC::BRD, RC: &PPC::G8RCRegClass, Op0);
183 }
184 return Register();
185}
186
187Register fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, Register Op0) {
188 if (RetVT.SimpleTy != MVT::v4i32)
189 return Register();
190 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
191 return fastEmitInst_r(MachineInstOpcode: PPC::XXBRW, RC: &PPC::VSRCRegClass, Op0);
192 }
193 return Register();
194}
195
196Register fastEmit_ISD_BSWAP_MVT_v2i64_r(MVT RetVT, Register Op0) {
197 if (RetVT.SimpleTy != MVT::v2i64)
198 return Register();
199 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
200 return fastEmitInst_r(MachineInstOpcode: PPC::XXBRD, RC: &PPC::VSRCRegClass, Op0);
201 }
202 return Register();
203}
204
205Register fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, Register Op0) {
206 switch (VT.SimpleTy) {
207 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0);
208 case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0);
209 case MVT::v4i32: return fastEmit_ISD_BSWAP_MVT_v4i32_r(RetVT, Op0);
210 case MVT::v2i64: return fastEmit_ISD_BSWAP_MVT_v2i64_r(RetVT, Op0);
211 default: return Register();
212 }
213}
214
215// FastEmit functions for ISD::CTLZ.
216
217Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
218 if (RetVT.SimpleTy != MVT::i32)
219 return Register();
220 return fastEmitInst_r(MachineInstOpcode: PPC::CNTLZW, RC: &PPC::GPRCRegClass, Op0);
221}
222
223Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
224 if (RetVT.SimpleTy != MVT::i64)
225 return Register();
226 return fastEmitInst_r(MachineInstOpcode: PPC::CNTLZD, RC: &PPC::G8RCRegClass, Op0);
227}
228
229Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
230 if (RetVT.SimpleTy != MVT::v16i8)
231 return Register();
232 if ((Subtarget->hasP8Altivec())) {
233 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZB, RC: &PPC::VRRCRegClass, Op0);
234 }
235 return Register();
236}
237
238Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
239 if (RetVT.SimpleTy != MVT::v8i16)
240 return Register();
241 if ((Subtarget->hasP8Altivec())) {
242 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZH, RC: &PPC::VRRCRegClass, Op0);
243 }
244 return Register();
245}
246
247Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
248 if (RetVT.SimpleTy != MVT::v4i32)
249 return Register();
250 if ((Subtarget->hasP8Altivec())) {
251 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZW, RC: &PPC::VRRCRegClass, Op0);
252 }
253 return Register();
254}
255
256Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
257 if (RetVT.SimpleTy != MVT::v2i64)
258 return Register();
259 if ((Subtarget->hasP8Altivec())) {
260 return fastEmitInst_r(MachineInstOpcode: PPC::VCLZD, RC: &PPC::VRRCRegClass, Op0);
261 }
262 return Register();
263}
264
265Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
266 switch (VT.SimpleTy) {
267 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
268 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
269 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
270 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
271 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
272 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
273 default: return Register();
274 }
275}
276
277// FastEmit functions for ISD::CTPOP.
278
279Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
280 if (RetVT.SimpleTy != MVT::i32)
281 return Register();
282 return fastEmitInst_r(MachineInstOpcode: PPC::POPCNTW, RC: &PPC::GPRCRegClass, Op0);
283}
284
285Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
286 if (RetVT.SimpleTy != MVT::i64)
287 return Register();
288 return fastEmitInst_r(MachineInstOpcode: PPC::POPCNTD, RC: &PPC::G8RCRegClass, Op0);
289}
290
291Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
292 if (RetVT.SimpleTy != MVT::v16i8)
293 return Register();
294 if ((Subtarget->hasP8Altivec())) {
295 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTB, RC: &PPC::VRRCRegClass, Op0);
296 }
297 return Register();
298}
299
300Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
301 if (RetVT.SimpleTy != MVT::v8i16)
302 return Register();
303 if ((Subtarget->hasP8Altivec())) {
304 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTH, RC: &PPC::VRRCRegClass, Op0);
305 }
306 return Register();
307}
308
309Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
310 if (RetVT.SimpleTy != MVT::v4i32)
311 return Register();
312 if ((Subtarget->hasP8Altivec())) {
313 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTW, RC: &PPC::VRRCRegClass, Op0);
314 }
315 return Register();
316}
317
318Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
319 if (RetVT.SimpleTy != MVT::v2i64)
320 return Register();
321 if ((Subtarget->hasP8Altivec())) {
322 return fastEmitInst_r(MachineInstOpcode: PPC::VPOPCNTD, RC: &PPC::VRRCRegClass, Op0);
323 }
324 return Register();
325}
326
327Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
328 switch (VT.SimpleTy) {
329 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
330 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
331 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
332 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
333 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
334 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
335 default: return Register();
336 }
337}
338
339// FastEmit functions for ISD::CTTZ.
340
341Register fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, Register Op0) {
342 if (RetVT.SimpleTy != MVT::i32)
343 return Register();
344 if ((Subtarget->isISA3_0())) {
345 return fastEmitInst_r(MachineInstOpcode: PPC::CNTTZW, RC: &PPC::GPRCRegClass, Op0);
346 }
347 return Register();
348}
349
350Register fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, Register Op0) {
351 if (RetVT.SimpleTy != MVT::i64)
352 return Register();
353 if ((Subtarget->isISA3_0())) {
354 return fastEmitInst_r(MachineInstOpcode: PPC::CNTTZD, RC: &PPC::G8RCRegClass, Op0);
355 }
356 return Register();
357}
358
359Register fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
360 if (RetVT.SimpleTy != MVT::v16i8)
361 return Register();
362 if ((Subtarget->hasP9Altivec())) {
363 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZB, RC: &PPC::VRRCRegClass, Op0);
364 }
365 return Register();
366}
367
368Register fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
369 if (RetVT.SimpleTy != MVT::v8i16)
370 return Register();
371 if ((Subtarget->hasP9Altivec())) {
372 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZH, RC: &PPC::VRRCRegClass, Op0);
373 }
374 return Register();
375}
376
377Register fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
378 if (RetVT.SimpleTy != MVT::v4i32)
379 return Register();
380 if ((Subtarget->hasP9Altivec())) {
381 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZW, RC: &PPC::VRRCRegClass, Op0);
382 }
383 return Register();
384}
385
386Register fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
387 if (RetVT.SimpleTy != MVT::v2i64)
388 return Register();
389 if ((Subtarget->hasP9Altivec())) {
390 return fastEmitInst_r(MachineInstOpcode: PPC::VCTZD, RC: &PPC::VRRCRegClass, Op0);
391 }
392 return Register();
393}
394
395Register fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, Register Op0) {
396 switch (VT.SimpleTy) {
397 case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0);
398 case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0);
399 case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0);
400 case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0);
401 case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0);
402 case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0);
403 default: return Register();
404 }
405}
406
407// FastEmit functions for ISD::FABS.
408
409Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
410 if (RetVT.SimpleTy != MVT::f32)
411 return Register();
412 if ((Subtarget->hasSPE())) {
413 return fastEmitInst_r(MachineInstOpcode: PPC::EFSABS, RC: &PPC::GPRCRegClass, Op0);
414 }
415 if ((Subtarget->hasFPU())) {
416 return fastEmitInst_r(MachineInstOpcode: PPC::FABSS, RC: &PPC::F4RCRegClass, Op0);
417 }
418 return Register();
419}
420
421Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
422 if (RetVT.SimpleTy != MVT::f64)
423 return Register();
424 if ((Subtarget->hasVSX())) {
425 return fastEmitInst_r(MachineInstOpcode: PPC::XSABSDP, RC: &PPC::VSFRCRegClass, Op0);
426 }
427 if ((Subtarget->hasSPE())) {
428 return fastEmitInst_r(MachineInstOpcode: PPC::EFDABS, RC: &PPC::SPERCRegClass, Op0);
429 }
430 if ((Subtarget->hasFPU())) {
431 return fastEmitInst_r(MachineInstOpcode: PPC::FABSD, RC: &PPC::F8RCRegClass, Op0);
432 }
433 return Register();
434}
435
436Register fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, Register Op0) {
437 if (RetVT.SimpleTy != MVT::f128)
438 return Register();
439 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
440 return fastEmitInst_r(MachineInstOpcode: PPC::XSABSQP, RC: &PPC::VRRCRegClass, Op0);
441 }
442 return Register();
443}
444
445Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
446 if (RetVT.SimpleTy != MVT::v4f32)
447 return Register();
448 if ((Subtarget->hasVSX())) {
449 return fastEmitInst_r(MachineInstOpcode: PPC::XVABSSP, RC: &PPC::VSRCRegClass, Op0);
450 }
451 return Register();
452}
453
454Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
455 if (RetVT.SimpleTy != MVT::v2f64)
456 return Register();
457 if ((Subtarget->hasVSX())) {
458 return fastEmitInst_r(MachineInstOpcode: PPC::XVABSDP, RC: &PPC::VSRCRegClass, Op0);
459 }
460 return Register();
461}
462
463Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
464 switch (VT.SimpleTy) {
465 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
466 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
467 case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0);
468 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
469 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
470 default: return Register();
471 }
472}
473
474// FastEmit functions for ISD::FCEIL.
475
476Register fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
477 if (RetVT.SimpleTy != MVT::f32)
478 return Register();
479 if ((Subtarget->hasFPU())) {
480 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPS, RC: &PPC::F4RCRegClass, Op0);
481 }
482 return Register();
483}
484
485Register fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
486 if (RetVT.SimpleTy != MVT::f64)
487 return Register();
488 if ((Subtarget->hasVSX())) {
489 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIP, RC: &PPC::VSFRCRegClass, Op0);
490 }
491 if ((Subtarget->hasFPU())) {
492 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPD, RC: &PPC::F8RCRegClass, Op0);
493 }
494 return Register();
495}
496
497Register fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
498 if (RetVT.SimpleTy != MVT::v4f32)
499 return Register();
500 if ((Subtarget->hasVSX())) {
501 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIP, RC: &PPC::VSRCRegClass, Op0);
502 }
503 if ((Subtarget->hasAltivec())) {
504 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIP, RC: &PPC::VRRCRegClass, Op0);
505 }
506 return Register();
507}
508
509Register fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
510 if (RetVT.SimpleTy != MVT::v2f64)
511 return Register();
512 if ((Subtarget->hasVSX())) {
513 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIP, RC: &PPC::VSRCRegClass, Op0);
514 }
515 return Register();
516}
517
518Register fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
519 switch (VT.SimpleTy) {
520 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0);
521 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0);
522 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0);
523 case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0);
524 default: return Register();
525 }
526}
527
528// FastEmit functions for ISD::FFLOOR.
529
530Register fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
531 if (RetVT.SimpleTy != MVT::f32)
532 return Register();
533 if ((Subtarget->hasFPU())) {
534 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMS, RC: &PPC::F4RCRegClass, Op0);
535 }
536 return Register();
537}
538
539Register fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
540 if (RetVT.SimpleTy != MVT::f64)
541 return Register();
542 if ((Subtarget->hasVSX())) {
543 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIM, RC: &PPC::VSFRCRegClass, Op0);
544 }
545 if ((Subtarget->hasFPU())) {
546 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMD, RC: &PPC::F8RCRegClass, Op0);
547 }
548 return Register();
549}
550
551Register fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
552 if (RetVT.SimpleTy != MVT::v4f32)
553 return Register();
554 if ((Subtarget->hasVSX())) {
555 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIM, RC: &PPC::VSRCRegClass, Op0);
556 }
557 if ((Subtarget->hasAltivec())) {
558 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIM, RC: &PPC::VRRCRegClass, Op0);
559 }
560 return Register();
561}
562
563Register fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
564 if (RetVT.SimpleTy != MVT::v2f64)
565 return Register();
566 if ((Subtarget->hasVSX())) {
567 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIM, RC: &PPC::VSRCRegClass, Op0);
568 }
569 return Register();
570}
571
572Register fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
573 switch (VT.SimpleTy) {
574 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0);
575 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0);
576 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0);
577 case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0);
578 default: return Register();
579 }
580}
581
582// FastEmit functions for ISD::FNEARBYINT.
583
584Register fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, Register Op0) {
585 if (RetVT.SimpleTy != MVT::f64)
586 return Register();
587 if ((Subtarget->hasVSX())) {
588 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
589 }
590 return Register();
591}
592
593Register fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
594 if (RetVT.SimpleTy != MVT::v4f32)
595 return Register();
596 if ((Subtarget->hasVSX())) {
597 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
598 }
599 if ((Subtarget->hasAltivec())) {
600 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIN, RC: &PPC::VRRCRegClass, Op0);
601 }
602 return Register();
603}
604
605Register fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
606 if (RetVT.SimpleTy != MVT::v2f64)
607 return Register();
608 if ((Subtarget->hasVSX())) {
609 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
610 }
611 return Register();
612}
613
614Register fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, Register Op0) {
615 switch (VT.SimpleTy) {
616 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0);
617 case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0);
618 case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0);
619 default: return Register();
620 }
621}
622
623// FastEmit functions for ISD::FNEG.
624
625Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
626 if (RetVT.SimpleTy != MVT::f32)
627 return Register();
628 if ((Subtarget->hasSPE())) {
629 return fastEmitInst_r(MachineInstOpcode: PPC::EFSNEG, RC: &PPC::GPRCRegClass, Op0);
630 }
631 if ((Subtarget->hasFPU())) {
632 return fastEmitInst_r(MachineInstOpcode: PPC::FNEGS, RC: &PPC::F4RCRegClass, Op0);
633 }
634 return Register();
635}
636
637Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
638 if (RetVT.SimpleTy != MVT::f64)
639 return Register();
640 if ((Subtarget->hasVSX())) {
641 return fastEmitInst_r(MachineInstOpcode: PPC::XSNEGDP, RC: &PPC::VSFRCRegClass, Op0);
642 }
643 if ((Subtarget->hasSPE())) {
644 return fastEmitInst_r(MachineInstOpcode: PPC::EFDNEG, RC: &PPC::SPERCRegClass, Op0);
645 }
646 if ((Subtarget->hasFPU())) {
647 return fastEmitInst_r(MachineInstOpcode: PPC::FNEGD, RC: &PPC::F8RCRegClass, Op0);
648 }
649 return Register();
650}
651
652Register fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, Register Op0) {
653 if (RetVT.SimpleTy != MVT::f128)
654 return Register();
655 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
656 return fastEmitInst_r(MachineInstOpcode: PPC::XSNEGQP, RC: &PPC::VRRCRegClass, Op0);
657 }
658 return Register();
659}
660
661Register fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, Register Op0) {
662 if (RetVT.SimpleTy != MVT::v4f32)
663 return Register();
664 if ((Subtarget->hasVSX())) {
665 return fastEmitInst_r(MachineInstOpcode: PPC::XVNEGSP, RC: &PPC::VSRCRegClass, Op0);
666 }
667 return Register();
668}
669
670Register fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, Register Op0) {
671 if (RetVT.SimpleTy != MVT::v2f64)
672 return Register();
673 if ((Subtarget->hasVSX())) {
674 return fastEmitInst_r(MachineInstOpcode: PPC::XVNEGDP, RC: &PPC::VSRCRegClass, Op0);
675 }
676 return Register();
677}
678
679Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
680 switch (VT.SimpleTy) {
681 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
682 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
683 case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0);
684 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0);
685 case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0);
686 default: return Register();
687 }
688}
689
690// FastEmit functions for ISD::FP_EXTEND.
691
692Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
693 if (RetVT.SimpleTy != MVT::f64)
694 return Register();
695 if ((Subtarget->hasSPE())) {
696 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFS, RC: &PPC::SPERCRegClass, Op0);
697 }
698 return Register();
699}
700
701Register fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, Register Op0) {
702 if (RetVT.SimpleTy != MVT::f128)
703 return Register();
704 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
705 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPQP, RC: &PPC::VRRCRegClass, Op0);
706 }
707 return Register();
708}
709
710Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
711 switch (VT.SimpleTy) {
712 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
713 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0);
714 default: return Register();
715 }
716}
717
718// FastEmit functions for ISD::FP_ROUND.
719
720Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
721 if (RetVT.SimpleTy != MVT::f32)
722 return Register();
723 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
724 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSP, RC: &PPC::VSSRCRegClass, Op0);
725 }
726 if ((Subtarget->hasSPE())) {
727 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFD, RC: &PPC::GPRCRegClass, Op0);
728 }
729 if ((Subtarget->hasFPU())) {
730 return fastEmitInst_r(MachineInstOpcode: PPC::FRSP, RC: &PPC::F4RCRegClass, Op0);
731 }
732 return Register();
733}
734
735Register fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, Register Op0) {
736 if (RetVT.SimpleTy != MVT::f64)
737 return Register();
738 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
739 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPDP, RC: &PPC::VFRCRegClass, Op0);
740 }
741 return Register();
742}
743
744Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
745 switch (VT.SimpleTy) {
746 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
747 case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0);
748 default: return Register();
749 }
750}
751
752// FastEmit functions for ISD::FP_TO_SINT.
753
754Register fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
755 if (RetVT.SimpleTy != MVT::i32)
756 return Register();
757 if ((Subtarget->hasSPE())) {
758 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTSIZ, RC: &PPC::GPRCRegClass, Op0);
759 }
760 return Register();
761}
762
763Register fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
764 if (RetVT.SimpleTy != MVT::i32)
765 return Register();
766 if ((Subtarget->hasSPE())) {
767 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTSIZ, RC: &PPC::GPRCRegClass, Op0);
768 }
769 return Register();
770}
771
772Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
773 if (RetVT.SimpleTy != MVT::v4i32)
774 return Register();
775 if ((Subtarget->hasVSX())) {
776 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPSXWS, RC: &PPC::VSRCRegClass, Op0);
777 }
778 if ((Subtarget->hasAltivec())) {
779 return fastEmitInst_r(MachineInstOpcode: PPC::VCTSXS_0, RC: &PPC::VRRCRegClass, Op0);
780 }
781 return Register();
782}
783
784Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
785 if (RetVT.SimpleTy != MVT::v2i64)
786 return Register();
787 if ((Subtarget->hasVSX())) {
788 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPSXDS, RC: &PPC::VSRCRegClass, Op0);
789 }
790 return Register();
791}
792
793Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
794 switch (VT.SimpleTy) {
795 case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
796 case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
797 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
798 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
799 default: return Register();
800 }
801}
802
803// FastEmit functions for ISD::FP_TO_UINT.
804
805Register fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
806 if (RetVT.SimpleTy != MVT::i32)
807 return Register();
808 if ((Subtarget->hasSPE())) {
809 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTUIZ, RC: &PPC::GPRCRegClass, Op0);
810 }
811 return Register();
812}
813
814Register fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
815 if (RetVT.SimpleTy != MVT::i32)
816 return Register();
817 if ((Subtarget->hasSPE())) {
818 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTUIZ, RC: &PPC::GPRCRegClass, Op0);
819 }
820 return Register();
821}
822
823Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
824 if (RetVT.SimpleTy != MVT::v4i32)
825 return Register();
826 if ((Subtarget->hasVSX())) {
827 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPUXWS, RC: &PPC::VSRCRegClass, Op0);
828 }
829 if ((Subtarget->hasAltivec())) {
830 return fastEmitInst_r(MachineInstOpcode: PPC::VCTUXS_0, RC: &PPC::VRRCRegClass, Op0);
831 }
832 return Register();
833}
834
835Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
836 if (RetVT.SimpleTy != MVT::v2i64)
837 return Register();
838 if ((Subtarget->hasVSX())) {
839 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPUXDS, RC: &PPC::VSRCRegClass, Op0);
840 }
841 return Register();
842}
843
844Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
845 switch (VT.SimpleTy) {
846 case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
847 case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
848 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
849 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
850 default: return Register();
851 }
852}
853
854// FastEmit functions for ISD::FRINT.
855
856Register fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
857 if (RetVT.SimpleTy != MVT::f64)
858 return Register();
859 if ((Subtarget->hasVSX())) {
860 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
861 }
862 return Register();
863}
864
865Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
866 if (RetVT.SimpleTy != MVT::v4f32)
867 return Register();
868 if ((Subtarget->hasVSX())) {
869 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
870 }
871 return Register();
872}
873
874Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
875 if (RetVT.SimpleTy != MVT::v2f64)
876 return Register();
877 if ((Subtarget->hasVSX())) {
878 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
879 }
880 return Register();
881}
882
883Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
884 switch (VT.SimpleTy) {
885 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
886 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
887 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
888 default: return Register();
889 }
890}
891
892// FastEmit functions for ISD::FROUND.
893
894Register fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, Register Op0) {
895 if (RetVT.SimpleTy != MVT::f32)
896 return Register();
897 if ((Subtarget->hasFPU())) {
898 return fastEmitInst_r(MachineInstOpcode: PPC::FRINS, RC: &PPC::F4RCRegClass, Op0);
899 }
900 return Register();
901}
902
903Register fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, Register Op0) {
904 if (RetVT.SimpleTy != MVT::f64)
905 return Register();
906 if ((Subtarget->hasVSX())) {
907 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPI, RC: &PPC::VSFRCRegClass, Op0);
908 }
909 if ((Subtarget->hasFPU())) {
910 return fastEmitInst_r(MachineInstOpcode: PPC::FRIND, RC: &PPC::F8RCRegClass, Op0);
911 }
912 return Register();
913}
914
915Register fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, Register Op0) {
916 if (RetVT.SimpleTy != MVT::v4f32)
917 return Register();
918 if ((Subtarget->hasVSX())) {
919 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPI, RC: &PPC::VSRCRegClass, Op0);
920 }
921 return Register();
922}
923
924Register fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, Register Op0) {
925 if (RetVT.SimpleTy != MVT::v2f64)
926 return Register();
927 if ((Subtarget->hasVSX())) {
928 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPI, RC: &PPC::VSRCRegClass, Op0);
929 }
930 return Register();
931}
932
933Register fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, Register Op0) {
934 switch (VT.SimpleTy) {
935 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0);
936 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0);
937 case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0);
938 case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0);
939 default: return Register();
940 }
941}
942
943// FastEmit functions for ISD::FSQRT.
944
945Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
946 if (RetVT.SimpleTy != MVT::f32)
947 return Register();
948 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
949 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTSP, RC: &PPC::VSSRCRegClass, Op0);
950 }
951 if ((Subtarget->hasFPU())) {
952 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRTS, RC: &PPC::F4RCRegClass, Op0);
953 }
954 return Register();
955}
956
957Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
958 if (RetVT.SimpleTy != MVT::f64)
959 return Register();
960 if ((Subtarget->hasVSX())) {
961 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
962 }
963 if ((Subtarget->hasFPU())) {
964 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
965 }
966 return Register();
967}
968
969Register fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, Register Op0) {
970 if (RetVT.SimpleTy != MVT::f128)
971 return Register();
972 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
973 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTQP, RC: &PPC::VRRCRegClass, Op0);
974 }
975 return Register();
976}
977
978Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
979 if (RetVT.SimpleTy != MVT::v4f32)
980 return Register();
981 if ((Subtarget->hasVSX())) {
982 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
983 }
984 return Register();
985}
986
987Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
988 if (RetVT.SimpleTy != MVT::v2f64)
989 return Register();
990 if ((Subtarget->hasVSX())) {
991 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
992 }
993 return Register();
994}
995
996Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
997 switch (VT.SimpleTy) {
998 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
999 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
1000 case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0);
1001 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
1002 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
1003 default: return Register();
1004 }
1005}
1006
1007// FastEmit functions for ISD::FTRUNC.
1008
1009Register fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
1010 if (RetVT.SimpleTy != MVT::f32)
1011 return Register();
1012 if ((Subtarget->hasFPU())) {
1013 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZS, RC: &PPC::F4RCRegClass, Op0);
1014 }
1015 return Register();
1016}
1017
1018Register fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
1019 if (RetVT.SimpleTy != MVT::f64)
1020 return Register();
1021 if ((Subtarget->hasVSX())) {
1022 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIZ, RC: &PPC::VSFRCRegClass, Op0);
1023 }
1024 if ((Subtarget->hasFPU())) {
1025 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZD, RC: &PPC::F8RCRegClass, Op0);
1026 }
1027 return Register();
1028}
1029
1030Register fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
1031 if (RetVT.SimpleTy != MVT::v4f32)
1032 return Register();
1033 if ((Subtarget->hasVSX())) {
1034 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIZ, RC: &PPC::VSRCRegClass, Op0);
1035 }
1036 if ((Subtarget->hasAltivec())) {
1037 return fastEmitInst_r(MachineInstOpcode: PPC::VRFIZ, RC: &PPC::VRRCRegClass, Op0);
1038 }
1039 return Register();
1040}
1041
1042Register fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
1043 if (RetVT.SimpleTy != MVT::v2f64)
1044 return Register();
1045 if ((Subtarget->hasVSX())) {
1046 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIZ, RC: &PPC::VSRCRegClass, Op0);
1047 }
1048 return Register();
1049}
1050
1051Register fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
1052 switch (VT.SimpleTy) {
1053 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0);
1054 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0);
1055 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0);
1056 case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0);
1057 default: return Register();
1058 }
1059}
1060
1061// FastEmit functions for ISD::SCALAR_TO_VECTOR.
1062
1063Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, Register Op0) {
1064 if (RetVT.SimpleTy != MVT::v4i32)
1065 return Register();
1066 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1067 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWS, RC: &PPC::VSRCRegClass, Op0);
1068 }
1069 return Register();
1070}
1071
1072Register fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, Register Op0) {
1073 if (RetVT.SimpleTy != MVT::v4f32)
1074 return Register();
1075 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) {
1076 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
1077 }
1078 return Register();
1079}
1080
1081Register fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, Register Op0) {
1082 switch (VT.SimpleTy) {
1083 case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
1084 case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
1085 default: return Register();
1086 }
1087}
1088
1089// FastEmit functions for ISD::SIGN_EXTEND.
1090
1091Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
1092 if ((Subtarget->isISA3_1())) {
1093 return fastEmitInst_r(MachineInstOpcode: PPC::SETNBC, RC: &PPC::GPRCRegClass, Op0);
1094 }
1095 return Register();
1096}
1097
1098Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
1099 if ((Subtarget->isISA3_1())) {
1100 return fastEmitInst_r(MachineInstOpcode: PPC::SETNBC8, RC: &PPC::G8RCRegClass, Op0);
1101 }
1102 return Register();
1103}
1104
1105Register fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
1106switch (RetVT.SimpleTy) {
1107 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Op0);
1108 case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Op0);
1109 default: return Register();
1110}
1111}
1112
1113Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
1114 if (RetVT.SimpleTy != MVT::i64)
1115 return Register();
1116 return fastEmitInst_r(MachineInstOpcode: PPC::EXTSW_32_64, RC: &PPC::G8RCRegClass, Op0);
1117}
1118
1119Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1120 switch (VT.SimpleTy) {
1121 case MVT::i1: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(RetVT, Op0);
1122 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
1123 default: return Register();
1124 }
1125}
1126
1127// FastEmit functions for ISD::SINT_TO_FP.
1128
1129Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1130 if ((Subtarget->hasSPE())) {
1131 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFSI, RC: &PPC::GPRCRegClass, Op0);
1132 }
1133 return Register();
1134}
1135
1136Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1137 if ((Subtarget->hasSPE())) {
1138 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFSI, RC: &PPC::SPERCRegClass, Op0);
1139 }
1140 return Register();
1141}
1142
1143Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1144switch (RetVT.SimpleTy) {
1145 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1146 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1147 default: return Register();
1148}
1149}
1150
1151Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1152 if (RetVT.SimpleTy != MVT::v4f32)
1153 return Register();
1154 if ((Subtarget->hasVSX())) {
1155 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXWSP, RC: &PPC::VSRCRegClass, Op0);
1156 }
1157 if ((Subtarget->hasAltivec())) {
1158 return fastEmitInst_r(MachineInstOpcode: PPC::VCFSX_0, RC: &PPC::VRRCRegClass, Op0);
1159 }
1160 return Register();
1161}
1162
1163Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1164 if (RetVT.SimpleTy != MVT::v2f64)
1165 return Register();
1166 if ((Subtarget->hasVSX())) {
1167 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXDDP, RC: &PPC::VSRCRegClass, Op0);
1168 }
1169 return Register();
1170}
1171
1172Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1173 switch (VT.SimpleTy) {
1174 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
1175 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1176 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1177 default: return Register();
1178 }
1179}
1180
1181// FastEmit functions for ISD::STRICT_FCEIL.
1182
1183Register fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(MVT RetVT, Register Op0) {
1184 if (RetVT.SimpleTy != MVT::f32)
1185 return Register();
1186 if ((Subtarget->hasFPU())) {
1187 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPS, RC: &PPC::F4RCRegClass, Op0);
1188 }
1189 return Register();
1190}
1191
1192Register fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(MVT RetVT, Register Op0) {
1193 if (RetVT.SimpleTy != MVT::f64)
1194 return Register();
1195 if ((Subtarget->hasVSX())) {
1196 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIP, RC: &PPC::VSFRCRegClass, Op0);
1197 }
1198 if ((Subtarget->hasFPU())) {
1199 return fastEmitInst_r(MachineInstOpcode: PPC::FRIPD, RC: &PPC::F8RCRegClass, Op0);
1200 }
1201 return Register();
1202}
1203
1204Register fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(MVT RetVT, Register Op0) {
1205 if (RetVT.SimpleTy != MVT::v4f32)
1206 return Register();
1207 if ((Subtarget->hasVSX())) {
1208 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIP, RC: &PPC::VSRCRegClass, Op0);
1209 }
1210 return Register();
1211}
1212
1213Register fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(MVT RetVT, Register Op0) {
1214 if (RetVT.SimpleTy != MVT::v2f64)
1215 return Register();
1216 if ((Subtarget->hasVSX())) {
1217 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIP, RC: &PPC::VSRCRegClass, Op0);
1218 }
1219 return Register();
1220}
1221
1222Register fastEmit_ISD_STRICT_FCEIL_r(MVT VT, MVT RetVT, Register Op0) {
1223 switch (VT.SimpleTy) {
1224 case MVT::f32: return fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(RetVT, Op0);
1225 case MVT::f64: return fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(RetVT, Op0);
1226 case MVT::v4f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(RetVT, Op0);
1227 case MVT::v2f64: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(RetVT, Op0);
1228 default: return Register();
1229 }
1230}
1231
1232// FastEmit functions for ISD::STRICT_FFLOOR.
1233
1234Register fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(MVT RetVT, Register Op0) {
1235 if (RetVT.SimpleTy != MVT::f32)
1236 return Register();
1237 if ((Subtarget->hasFPU())) {
1238 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMS, RC: &PPC::F4RCRegClass, Op0);
1239 }
1240 return Register();
1241}
1242
1243Register fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(MVT RetVT, Register Op0) {
1244 if (RetVT.SimpleTy != MVT::f64)
1245 return Register();
1246 if ((Subtarget->hasVSX())) {
1247 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIM, RC: &PPC::VSFRCRegClass, Op0);
1248 }
1249 if ((Subtarget->hasFPU())) {
1250 return fastEmitInst_r(MachineInstOpcode: PPC::FRIMD, RC: &PPC::F8RCRegClass, Op0);
1251 }
1252 return Register();
1253}
1254
1255Register fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(MVT RetVT, Register Op0) {
1256 if (RetVT.SimpleTy != MVT::v4f32)
1257 return Register();
1258 if ((Subtarget->hasVSX())) {
1259 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIM, RC: &PPC::VSRCRegClass, Op0);
1260 }
1261 return Register();
1262}
1263
1264Register fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(MVT RetVT, Register Op0) {
1265 if (RetVT.SimpleTy != MVT::v2f64)
1266 return Register();
1267 if ((Subtarget->hasVSX())) {
1268 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIM, RC: &PPC::VSRCRegClass, Op0);
1269 }
1270 return Register();
1271}
1272
1273Register fastEmit_ISD_STRICT_FFLOOR_r(MVT VT, MVT RetVT, Register Op0) {
1274 switch (VT.SimpleTy) {
1275 case MVT::f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(RetVT, Op0);
1276 case MVT::f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(RetVT, Op0);
1277 case MVT::v4f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(RetVT, Op0);
1278 case MVT::v2f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(RetVT, Op0);
1279 default: return Register();
1280 }
1281}
1282
1283// FastEmit functions for ISD::STRICT_FP_EXTEND.
1284
1285Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
1286 if (RetVT.SimpleTy != MVT::f64)
1287 return Register();
1288 if ((Subtarget->hasSPE())) {
1289 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFS, RC: &PPC::SPERCRegClass, Op0);
1290 }
1291 return Register();
1292}
1293
1294Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(MVT RetVT, Register Op0) {
1295 if (RetVT.SimpleTy != MVT::f128)
1296 return Register();
1297 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1298 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPQP, RC: &PPC::VRRCRegClass, Op0);
1299 }
1300 return Register();
1301}
1302
1303Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1304 switch (VT.SimpleTy) {
1305 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
1306 case MVT::f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(RetVT, Op0);
1307 default: return Register();
1308 }
1309}
1310
1311// FastEmit functions for ISD::STRICT_FP_ROUND.
1312
1313Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
1314 if (RetVT.SimpleTy != MVT::f32)
1315 return Register();
1316 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1317 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSP, RC: &PPC::VSSRCRegClass, Op0);
1318 }
1319 if ((Subtarget->hasSPE())) {
1320 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFD, RC: &PPC::GPRCRegClass, Op0);
1321 }
1322 if ((Subtarget->hasFPU())) {
1323 return fastEmitInst_r(MachineInstOpcode: PPC::FRSP, RC: &PPC::F4RCRegClass, Op0);
1324 }
1325 return Register();
1326}
1327
1328Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(MVT RetVT, Register Op0) {
1329 if (RetVT.SimpleTy != MVT::f64)
1330 return Register();
1331 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1332 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPDP, RC: &PPC::VFRCRegClass, Op0);
1333 }
1334 return Register();
1335}
1336
1337Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
1338 switch (VT.SimpleTy) {
1339 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
1340 case MVT::f128: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(RetVT, Op0);
1341 default: return Register();
1342 }
1343}
1344
1345// FastEmit functions for ISD::STRICT_FP_TO_SINT.
1346
1347Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, Register Op0) {
1348 if (RetVT.SimpleTy != MVT::i32)
1349 return Register();
1350 if ((Subtarget->hasSPE())) {
1351 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTSIZ, RC: &PPC::GPRCRegClass, Op0);
1352 }
1353 return Register();
1354}
1355
1356Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, Register Op0) {
1357 if (RetVT.SimpleTy != MVT::i32)
1358 return Register();
1359 if ((Subtarget->hasSPE())) {
1360 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTSIZ, RC: &PPC::GPRCRegClass, Op0);
1361 }
1362 return Register();
1363}
1364
1365Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1366 if (RetVT.SimpleTy != MVT::v4i32)
1367 return Register();
1368 if ((Subtarget->hasVSX())) {
1369 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPSXWS, RC: &PPC::VSRCRegClass, Op0);
1370 }
1371 return Register();
1372}
1373
1374Register fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1375 if (RetVT.SimpleTy != MVT::v2i64)
1376 return Register();
1377 if ((Subtarget->hasVSX())) {
1378 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPSXDS, RC: &PPC::VSRCRegClass, Op0);
1379 }
1380 return Register();
1381}
1382
1383Register fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
1384 switch (VT.SimpleTy) {
1385 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
1386 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
1387 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
1388 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
1389 default: return Register();
1390 }
1391}
1392
1393// FastEmit functions for ISD::STRICT_FP_TO_UINT.
1394
1395Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, Register Op0) {
1396 if (RetVT.SimpleTy != MVT::i32)
1397 return Register();
1398 if ((Subtarget->hasSPE())) {
1399 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCTUIZ, RC: &PPC::GPRCRegClass, Op0);
1400 }
1401 return Register();
1402}
1403
1404Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, Register Op0) {
1405 if (RetVT.SimpleTy != MVT::i32)
1406 return Register();
1407 if ((Subtarget->hasSPE())) {
1408 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCTUIZ, RC: &PPC::GPRCRegClass, Op0);
1409 }
1410 return Register();
1411}
1412
1413Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1414 if (RetVT.SimpleTy != MVT::v4i32)
1415 return Register();
1416 if ((Subtarget->hasVSX())) {
1417 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSPUXWS, RC: &PPC::VSRCRegClass, Op0);
1418 }
1419 return Register();
1420}
1421
1422Register fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1423 if (RetVT.SimpleTy != MVT::v2i64)
1424 return Register();
1425 if ((Subtarget->hasVSX())) {
1426 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVDPUXDS, RC: &PPC::VSRCRegClass, Op0);
1427 }
1428 return Register();
1429}
1430
1431Register fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
1432 switch (VT.SimpleTy) {
1433 case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0);
1434 case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0);
1435 case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
1436 case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
1437 default: return Register();
1438 }
1439}
1440
1441// FastEmit functions for ISD::STRICT_FRINT.
1442
1443Register fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
1444 if (RetVT.SimpleTy != MVT::f64)
1445 return Register();
1446 if ((Subtarget->hasVSX())) {
1447 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIC, RC: &PPC::VSFRCRegClass, Op0);
1448 }
1449 return Register();
1450}
1451
1452Register fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1453 if (RetVT.SimpleTy != MVT::v4f32)
1454 return Register();
1455 if ((Subtarget->hasVSX())) {
1456 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIC, RC: &PPC::VSRCRegClass, Op0);
1457 }
1458 return Register();
1459}
1460
1461Register fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1462 if (RetVT.SimpleTy != MVT::v2f64)
1463 return Register();
1464 if ((Subtarget->hasVSX())) {
1465 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIC, RC: &PPC::VSRCRegClass, Op0);
1466 }
1467 return Register();
1468}
1469
1470Register fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
1471 switch (VT.SimpleTy) {
1472 case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0);
1473 case MVT::v4f32: return fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(RetVT, Op0);
1474 case MVT::v2f64: return fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(RetVT, Op0);
1475 default: return Register();
1476 }
1477}
1478
1479// FastEmit functions for ISD::STRICT_FROUND.
1480
1481Register fastEmit_ISD_STRICT_FROUND_MVT_f32_r(MVT RetVT, Register Op0) {
1482 if (RetVT.SimpleTy != MVT::f32)
1483 return Register();
1484 if ((Subtarget->hasFPU())) {
1485 return fastEmitInst_r(MachineInstOpcode: PPC::FRINS, RC: &PPC::F4RCRegClass, Op0);
1486 }
1487 return Register();
1488}
1489
1490Register fastEmit_ISD_STRICT_FROUND_MVT_f64_r(MVT RetVT, Register Op0) {
1491 if (RetVT.SimpleTy != MVT::f64)
1492 return Register();
1493 if ((Subtarget->hasVSX())) {
1494 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPI, RC: &PPC::VSFRCRegClass, Op0);
1495 }
1496 if ((Subtarget->hasFPU())) {
1497 return fastEmitInst_r(MachineInstOpcode: PPC::FRIND, RC: &PPC::F8RCRegClass, Op0);
1498 }
1499 return Register();
1500}
1501
1502Register fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(MVT RetVT, Register Op0) {
1503 if (RetVT.SimpleTy != MVT::v4f32)
1504 return Register();
1505 if ((Subtarget->hasVSX())) {
1506 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPI, RC: &PPC::VSRCRegClass, Op0);
1507 }
1508 return Register();
1509}
1510
1511Register fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(MVT RetVT, Register Op0) {
1512 if (RetVT.SimpleTy != MVT::v2f64)
1513 return Register();
1514 if ((Subtarget->hasVSX())) {
1515 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPI, RC: &PPC::VSRCRegClass, Op0);
1516 }
1517 return Register();
1518}
1519
1520Register fastEmit_ISD_STRICT_FROUND_r(MVT VT, MVT RetVT, Register Op0) {
1521 switch (VT.SimpleTy) {
1522 case MVT::f32: return fastEmit_ISD_STRICT_FROUND_MVT_f32_r(RetVT, Op0);
1523 case MVT::f64: return fastEmit_ISD_STRICT_FROUND_MVT_f64_r(RetVT, Op0);
1524 case MVT::v4f32: return fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(RetVT, Op0);
1525 case MVT::v2f64: return fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(RetVT, Op0);
1526 default: return Register();
1527 }
1528}
1529
1530// FastEmit functions for ISD::STRICT_FSQRT.
1531
1532Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
1533 if (RetVT.SimpleTy != MVT::f32)
1534 return Register();
1535 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1536 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTSP, RC: &PPC::VSSRCRegClass, Op0);
1537 }
1538 if ((Subtarget->hasFPU())) {
1539 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRTS, RC: &PPC::F4RCRegClass, Op0);
1540 }
1541 return Register();
1542}
1543
1544Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
1545 if (RetVT.SimpleTy != MVT::f64)
1546 return Register();
1547 if ((Subtarget->hasVSX())) {
1548 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
1549 }
1550 if ((Subtarget->hasFPU())) {
1551 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
1552 }
1553 return Register();
1554}
1555
1556Register fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(MVT RetVT, Register Op0) {
1557 if (RetVT.SimpleTy != MVT::f128)
1558 return Register();
1559 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1560 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTQP, RC: &PPC::VRRCRegClass, Op0);
1561 }
1562 return Register();
1563}
1564
1565Register fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
1566 if (RetVT.SimpleTy != MVT::v4f32)
1567 return Register();
1568 if ((Subtarget->hasVSX())) {
1569 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
1570 }
1571 return Register();
1572}
1573
1574Register fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
1575 if (RetVT.SimpleTy != MVT::v2f64)
1576 return Register();
1577 if ((Subtarget->hasVSX())) {
1578 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
1579 }
1580 return Register();
1581}
1582
1583Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
1584 switch (VT.SimpleTy) {
1585 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
1586 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
1587 case MVT::f128: return fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(RetVT, Op0);
1588 case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0);
1589 case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0);
1590 default: return Register();
1591 }
1592}
1593
1594// FastEmit functions for ISD::STRICT_FTRUNC.
1595
1596Register fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(MVT RetVT, Register Op0) {
1597 if (RetVT.SimpleTy != MVT::f32)
1598 return Register();
1599 if ((Subtarget->hasFPU())) {
1600 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZS, RC: &PPC::F4RCRegClass, Op0);
1601 }
1602 return Register();
1603}
1604
1605Register fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(MVT RetVT, Register Op0) {
1606 if (RetVT.SimpleTy != MVT::f64)
1607 return Register();
1608 if ((Subtarget->hasVSX())) {
1609 return fastEmitInst_r(MachineInstOpcode: PPC::XSRDPIZ, RC: &PPC::VSFRCRegClass, Op0);
1610 }
1611 if ((Subtarget->hasFPU())) {
1612 return fastEmitInst_r(MachineInstOpcode: PPC::FRIZD, RC: &PPC::F8RCRegClass, Op0);
1613 }
1614 return Register();
1615}
1616
1617Register fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(MVT RetVT, Register Op0) {
1618 if (RetVT.SimpleTy != MVT::v4f32)
1619 return Register();
1620 if ((Subtarget->hasVSX())) {
1621 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSPIZ, RC: &PPC::VSRCRegClass, Op0);
1622 }
1623 return Register();
1624}
1625
1626Register fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(MVT RetVT, Register Op0) {
1627 if (RetVT.SimpleTy != MVT::v2f64)
1628 return Register();
1629 if ((Subtarget->hasVSX())) {
1630 return fastEmitInst_r(MachineInstOpcode: PPC::XVRDPIZ, RC: &PPC::VSRCRegClass, Op0);
1631 }
1632 return Register();
1633}
1634
1635Register fastEmit_ISD_STRICT_FTRUNC_r(MVT VT, MVT RetVT, Register Op0) {
1636 switch (VT.SimpleTy) {
1637 case MVT::f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(RetVT, Op0);
1638 case MVT::f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(RetVT, Op0);
1639 case MVT::v4f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(RetVT, Op0);
1640 case MVT::v2f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(RetVT, Op0);
1641 default: return Register();
1642 }
1643}
1644
1645// FastEmit functions for ISD::STRICT_SINT_TO_FP.
1646
1647Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1648 if ((Subtarget->hasSPE())) {
1649 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFSI, RC: &PPC::GPRCRegClass, Op0);
1650 }
1651 return Register();
1652}
1653
1654Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1655 if ((Subtarget->hasSPE())) {
1656 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFSI, RC: &PPC::SPERCRegClass, Op0);
1657 }
1658 return Register();
1659}
1660
1661Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1662switch (RetVT.SimpleTy) {
1663 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1664 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1665 default: return Register();
1666}
1667}
1668
1669Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1670 if (RetVT.SimpleTy != MVT::v4f32)
1671 return Register();
1672 if ((Subtarget->hasVSX())) {
1673 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXWSP, RC: &PPC::VSRCRegClass, Op0);
1674 }
1675 return Register();
1676}
1677
1678Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1679 if (RetVT.SimpleTy != MVT::v2f64)
1680 return Register();
1681 if ((Subtarget->hasVSX())) {
1682 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVSXDDP, RC: &PPC::VSRCRegClass, Op0);
1683 }
1684 return Register();
1685}
1686
1687Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1688 switch (VT.SimpleTy) {
1689 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
1690 case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1691 case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1692 default: return Register();
1693 }
1694}
1695
1696// FastEmit functions for ISD::STRICT_UINT_TO_FP.
1697
1698Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1699 if ((Subtarget->hasSPE())) {
1700 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFUI, RC: &PPC::GPRCRegClass, Op0);
1701 }
1702 return Register();
1703}
1704
1705Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1706 if ((Subtarget->hasSPE())) {
1707 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFUI, RC: &PPC::SPERCRegClass, Op0);
1708 }
1709 return Register();
1710}
1711
1712Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1713switch (RetVT.SimpleTy) {
1714 case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1715 case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1716 default: return Register();
1717}
1718}
1719
1720Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1721 if (RetVT.SimpleTy != MVT::v4f32)
1722 return Register();
1723 if ((Subtarget->hasVSX())) {
1724 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXWSP, RC: &PPC::VSRCRegClass, Op0);
1725 }
1726 return Register();
1727}
1728
1729Register fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1730 if (RetVT.SimpleTy != MVT::v2f64)
1731 return Register();
1732 if ((Subtarget->hasVSX())) {
1733 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXDDP, RC: &PPC::VSRCRegClass, Op0);
1734 }
1735 return Register();
1736}
1737
1738Register fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1739 switch (VT.SimpleTy) {
1740 case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1741 case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1742 case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1743 default: return Register();
1744 }
1745}
1746
1747// FastEmit functions for ISD::TRUNCATE.
1748
1749Register fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, Register Op0) {
1750 if (RetVT.SimpleTy != MVT::i1)
1751 return Register();
1752 return fastEmitInst_r(MachineInstOpcode: PPC::ANDI_rec_1_GT_BIT, RC: &PPC::CRBITRCRegClass, Op0);
1753}
1754
1755Register fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, Register Op0) {
1756 if (RetVT.SimpleTy != MVT::i1)
1757 return Register();
1758 return fastEmitInst_r(MachineInstOpcode: PPC::ANDI_rec_1_GT_BIT8, RC: &PPC::CRBITRCRegClass, Op0);
1759}
1760
1761Register fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, Register Op0) {
1762 switch (VT.SimpleTy) {
1763 case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0);
1764 case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
1765 default: return Register();
1766 }
1767}
1768
1769// FastEmit functions for ISD::UINT_TO_FP.
1770
1771Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
1772 if ((Subtarget->hasSPE())) {
1773 return fastEmitInst_r(MachineInstOpcode: PPC::EFSCFUI, RC: &PPC::GPRCRegClass, Op0);
1774 }
1775 return Register();
1776}
1777
1778Register fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
1779 if ((Subtarget->hasSPE())) {
1780 return fastEmitInst_r(MachineInstOpcode: PPC::EFDCFUI, RC: &PPC::SPERCRegClass, Op0);
1781 }
1782 return Register();
1783}
1784
1785Register fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
1786switch (RetVT.SimpleTy) {
1787 case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
1788 case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
1789 default: return Register();
1790}
1791}
1792
1793Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
1794 if (RetVT.SimpleTy != MVT::v4f32)
1795 return Register();
1796 if ((Subtarget->hasVSX())) {
1797 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXWSP, RC: &PPC::VSRCRegClass, Op0);
1798 }
1799 if ((Subtarget->hasAltivec())) {
1800 return fastEmitInst_r(MachineInstOpcode: PPC::VCFUX_0, RC: &PPC::VRRCRegClass, Op0);
1801 }
1802 return Register();
1803}
1804
1805Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
1806 if (RetVT.SimpleTy != MVT::v2f64)
1807 return Register();
1808 if ((Subtarget->hasVSX())) {
1809 return fastEmitInst_r(MachineInstOpcode: PPC::XVCVUXDDP, RC: &PPC::VSRCRegClass, Op0);
1810 }
1811 return Register();
1812}
1813
1814Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
1815 switch (VT.SimpleTy) {
1816 case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0);
1817 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
1818 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
1819 default: return Register();
1820 }
1821}
1822
1823// FastEmit functions for ISD::ZERO_EXTEND.
1824
1825Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Register Op0) {
1826 if ((Subtarget->isISA3_1())) {
1827 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
1828 }
1829 return Register();
1830}
1831
1832Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Register Op0) {
1833 if ((Subtarget->isISA3_1())) {
1834 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC8, RC: &PPC::G8RCRegClass, Op0);
1835 }
1836 return Register();
1837}
1838
1839Register fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(MVT RetVT, Register Op0) {
1840switch (RetVT.SimpleTy) {
1841 case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Op0);
1842 case MVT::i64: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Op0);
1843 default: return Register();
1844}
1845}
1846
1847Register fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
1848 switch (VT.SimpleTy) {
1849 case MVT::i1: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(RetVT, Op0);
1850 default: return Register();
1851 }
1852}
1853
1854// FastEmit functions for PPCISD::FCFID.
1855
1856Register fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, Register Op0) {
1857 if (RetVT.SimpleTy != MVT::f64)
1858 return Register();
1859 if ((Subtarget->hasVSX())) {
1860 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDDP, RC: &PPC::VSFRCRegClass, Op0);
1861 }
1862 return fastEmitInst_r(MachineInstOpcode: PPC::FCFID, RC: &PPC::F8RCRegClass, Op0);
1863}
1864
1865Register fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, Register Op0) {
1866 switch (VT.SimpleTy) {
1867 case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0);
1868 default: return Register();
1869 }
1870}
1871
1872// FastEmit functions for PPCISD::FCFIDS.
1873
1874Register fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, Register Op0) {
1875 if (RetVT.SimpleTy != MVT::f32)
1876 return Register();
1877 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1878 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDSP, RC: &PPC::VSSRCRegClass, Op0);
1879 }
1880 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDS, RC: &PPC::F4RCRegClass, Op0);
1881}
1882
1883Register fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, Register Op0) {
1884 switch (VT.SimpleTy) {
1885 case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0);
1886 default: return Register();
1887 }
1888}
1889
1890// FastEmit functions for PPCISD::FCFIDU.
1891
1892Register fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, Register Op0) {
1893 if (RetVT.SimpleTy != MVT::f64)
1894 return Register();
1895 if ((Subtarget->hasVSX())) {
1896 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDDP, RC: &PPC::VSFRCRegClass, Op0);
1897 }
1898 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDU, RC: &PPC::F8RCRegClass, Op0);
1899}
1900
1901Register fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, Register Op0) {
1902 switch (VT.SimpleTy) {
1903 case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0);
1904 default: return Register();
1905 }
1906}
1907
1908// FastEmit functions for PPCISD::FCFIDUS.
1909
1910Register fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, Register Op0) {
1911 if (RetVT.SimpleTy != MVT::f32)
1912 return Register();
1913 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
1914 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDSP, RC: &PPC::VSSRCRegClass, Op0);
1915 }
1916 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDUS, RC: &PPC::F4RCRegClass, Op0);
1917}
1918
1919Register fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, Register Op0) {
1920 switch (VT.SimpleTy) {
1921 case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0);
1922 default: return Register();
1923 }
1924}
1925
1926// FastEmit functions for PPCISD::FCTIDUZ.
1927
1928Register fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, Register Op0) {
1929 if (RetVT.SimpleTy != MVT::f32)
1930 return Register();
1931 if ((Subtarget->hasVSX())) {
1932 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDSs, RC: &PPC::VSSRCRegClass, Op0);
1933 }
1934 return Register();
1935}
1936
1937Register fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, Register Op0) {
1938 if (RetVT.SimpleTy != MVT::f64)
1939 return Register();
1940 if ((Subtarget->hasVSX())) {
1941 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDS, RC: &PPC::VSFRCRegClass, Op0);
1942 }
1943 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDUZ, RC: &PPC::F8RCRegClass, Op0);
1944}
1945
1946Register fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(MVT RetVT, Register Op0) {
1947 if (RetVT.SimpleTy != MVT::f128)
1948 return Register();
1949 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1950 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUDZ, RC: &PPC::VRRCRegClass, Op0);
1951 }
1952 return Register();
1953}
1954
1955Register fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, Register Op0) {
1956 switch (VT.SimpleTy) {
1957 case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0);
1958 case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0);
1959 case MVT::f128: return fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(RetVT, Op0);
1960 default: return Register();
1961 }
1962}
1963
1964// FastEmit functions for PPCISD::FCTIDZ.
1965
1966Register fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, Register Op0) {
1967 if (RetVT.SimpleTy != MVT::f32)
1968 return Register();
1969 if ((Subtarget->hasVSX())) {
1970 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDSs, RC: &PPC::VSSRCRegClass, Op0);
1971 }
1972 return Register();
1973}
1974
1975Register fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, Register Op0) {
1976 if (RetVT.SimpleTy != MVT::f64)
1977 return Register();
1978 if ((Subtarget->hasVSX())) {
1979 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDS, RC: &PPC::VSFRCRegClass, Op0);
1980 }
1981 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDZ, RC: &PPC::F8RCRegClass, Op0);
1982}
1983
1984Register fastEmit_PPCISD_FCTIDZ_MVT_f128_r(MVT RetVT, Register Op0) {
1985 if (RetVT.SimpleTy != MVT::f128)
1986 return Register();
1987 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
1988 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSDZ, RC: &PPC::VRRCRegClass, Op0);
1989 }
1990 return Register();
1991}
1992
1993Register fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, Register Op0) {
1994 switch (VT.SimpleTy) {
1995 case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0);
1996 case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0);
1997 case MVT::f128: return fastEmit_PPCISD_FCTIDZ_MVT_f128_r(RetVT, Op0);
1998 default: return Register();
1999 }
2000}
2001
2002// FastEmit functions for PPCISD::FCTIWUZ.
2003
2004Register fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2005 if (RetVT.SimpleTy != MVT::f32)
2006 return Register();
2007 if ((Subtarget->hasVSX())) {
2008 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWSs, RC: &PPC::VSSRCRegClass, Op0);
2009 }
2010 return Register();
2011}
2012
2013Register fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2014 if (RetVT.SimpleTy != MVT::f64)
2015 return Register();
2016 if ((Subtarget->hasVSX())) {
2017 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWS, RC: &PPC::VSFRCRegClass, Op0);
2018 }
2019 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWUZ, RC: &PPC::F8RCRegClass, Op0);
2020}
2021
2022Register fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2023 if (RetVT.SimpleTy != MVT::f128)
2024 return Register();
2025 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2026 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUWZ, RC: &PPC::VRRCRegClass, Op0);
2027 }
2028 return Register();
2029}
2030
2031Register fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, Register Op0) {
2032 switch (VT.SimpleTy) {
2033 case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0);
2034 case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0);
2035 case MVT::f128: return fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(RetVT, Op0);
2036 default: return Register();
2037 }
2038}
2039
2040// FastEmit functions for PPCISD::FCTIWZ.
2041
2042Register fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, Register Op0) {
2043 if (RetVT.SimpleTy != MVT::f32)
2044 return Register();
2045 if ((Subtarget->hasVSX())) {
2046 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWSs, RC: &PPC::VSSRCRegClass, Op0);
2047 }
2048 return Register();
2049}
2050
2051Register fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, Register Op0) {
2052 if (RetVT.SimpleTy != MVT::f64)
2053 return Register();
2054 if ((Subtarget->hasVSX())) {
2055 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWS, RC: &PPC::VSFRCRegClass, Op0);
2056 }
2057 if ((Subtarget->hasFPU())) {
2058 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWZ, RC: &PPC::F8RCRegClass, Op0);
2059 }
2060 return Register();
2061}
2062
2063Register fastEmit_PPCISD_FCTIWZ_MVT_f128_r(MVT RetVT, Register Op0) {
2064 if (RetVT.SimpleTy != MVT::f128)
2065 return Register();
2066 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2067 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSWZ, RC: &PPC::VRRCRegClass, Op0);
2068 }
2069 return Register();
2070}
2071
2072Register fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, Register Op0) {
2073 switch (VT.SimpleTy) {
2074 case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0);
2075 case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0);
2076 case MVT::f128: return fastEmit_PPCISD_FCTIWZ_MVT_f128_r(RetVT, Op0);
2077 default: return Register();
2078 }
2079}
2080
2081// FastEmit functions for PPCISD::FRE.
2082
2083Register fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, Register Op0) {
2084 if (RetVT.SimpleTy != MVT::f32)
2085 return Register();
2086 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2087 return fastEmitInst_r(MachineInstOpcode: PPC::XSRESP, RC: &PPC::VSSRCRegClass, Op0);
2088 }
2089 if ((Subtarget->hasFPU())) {
2090 return fastEmitInst_r(MachineInstOpcode: PPC::FRES, RC: &PPC::F4RCRegClass, Op0);
2091 }
2092 return Register();
2093}
2094
2095Register fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, Register Op0) {
2096 if (RetVT.SimpleTy != MVT::f64)
2097 return Register();
2098 if ((Subtarget->hasVSX())) {
2099 return fastEmitInst_r(MachineInstOpcode: PPC::XSREDP, RC: &PPC::VSFRCRegClass, Op0);
2100 }
2101 if ((Subtarget->hasFPU())) {
2102 return fastEmitInst_r(MachineInstOpcode: PPC::FRE, RC: &PPC::F8RCRegClass, Op0);
2103 }
2104 return Register();
2105}
2106
2107Register fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, Register Op0) {
2108 if (RetVT.SimpleTy != MVT::v4f32)
2109 return Register();
2110 if ((Subtarget->hasVSX())) {
2111 return fastEmitInst_r(MachineInstOpcode: PPC::XVRESP, RC: &PPC::VSRCRegClass, Op0);
2112 }
2113 if ((Subtarget->hasAltivec())) {
2114 return fastEmitInst_r(MachineInstOpcode: PPC::VREFP, RC: &PPC::VRRCRegClass, Op0);
2115 }
2116 return Register();
2117}
2118
2119Register fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, Register Op0) {
2120 if (RetVT.SimpleTy != MVT::v2f64)
2121 return Register();
2122 if ((Subtarget->hasVSX())) {
2123 return fastEmitInst_r(MachineInstOpcode: PPC::XVREDP, RC: &PPC::VSRCRegClass, Op0);
2124 }
2125 return Register();
2126}
2127
2128Register fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, Register Op0) {
2129 switch (VT.SimpleTy) {
2130 case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0);
2131 case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0);
2132 case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0);
2133 case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0);
2134 default: return Register();
2135 }
2136}
2137
2138// FastEmit functions for PPCISD::FRSQRTE.
2139
2140Register fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, Register Op0) {
2141 if (RetVT.SimpleTy != MVT::f32)
2142 return Register();
2143 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2144 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSQRTESP, RC: &PPC::VSSRCRegClass, Op0);
2145 }
2146 if ((Subtarget->hasFPU())) {
2147 return fastEmitInst_r(MachineInstOpcode: PPC::FRSQRTES, RC: &PPC::F4RCRegClass, Op0);
2148 }
2149 return Register();
2150}
2151
2152Register fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, Register Op0) {
2153 if (RetVT.SimpleTy != MVT::f64)
2154 return Register();
2155 if ((Subtarget->hasVSX())) {
2156 return fastEmitInst_r(MachineInstOpcode: PPC::XSRSQRTEDP, RC: &PPC::VSFRCRegClass, Op0);
2157 }
2158 if ((Subtarget->hasFPU())) {
2159 return fastEmitInst_r(MachineInstOpcode: PPC::FRSQRTE, RC: &PPC::F8RCRegClass, Op0);
2160 }
2161 return Register();
2162}
2163
2164Register fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, Register Op0) {
2165 if (RetVT.SimpleTy != MVT::v4f32)
2166 return Register();
2167 if ((Subtarget->hasVSX())) {
2168 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSQRTESP, RC: &PPC::VSRCRegClass, Op0);
2169 }
2170 if ((Subtarget->hasAltivec())) {
2171 return fastEmitInst_r(MachineInstOpcode: PPC::VRSQRTEFP, RC: &PPC::VRRCRegClass, Op0);
2172 }
2173 return Register();
2174}
2175
2176Register fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, Register Op0) {
2177 if (RetVT.SimpleTy != MVT::v2f64)
2178 return Register();
2179 if ((Subtarget->hasVSX())) {
2180 return fastEmitInst_r(MachineInstOpcode: PPC::XVRSQRTEDP, RC: &PPC::VSRCRegClass, Op0);
2181 }
2182 return Register();
2183}
2184
2185Register fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, Register Op0) {
2186 switch (VT.SimpleTy) {
2187 case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0);
2188 case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0);
2189 case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0);
2190 case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0);
2191 default: return Register();
2192 }
2193}
2194
2195// FastEmit functions for PPCISD::FSQRT.
2196
2197Register fastEmit_PPCISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
2198 if (RetVT.SimpleTy != MVT::f64)
2199 return Register();
2200 if ((Subtarget->hasVSX())) {
2201 return fastEmitInst_r(MachineInstOpcode: PPC::XSSQRTDP, RC: &PPC::VSFRCRegClass, Op0);
2202 }
2203 return fastEmitInst_r(MachineInstOpcode: PPC::FSQRT, RC: &PPC::F8RCRegClass, Op0);
2204}
2205
2206Register fastEmit_PPCISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
2207 if (RetVT.SimpleTy != MVT::v4f32)
2208 return Register();
2209 if ((Subtarget->hasVSX())) {
2210 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTSP, RC: &PPC::VSRCRegClass, Op0);
2211 }
2212 return Register();
2213}
2214
2215Register fastEmit_PPCISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
2216 if (RetVT.SimpleTy != MVT::v2f64)
2217 return Register();
2218 if ((Subtarget->hasVSX())) {
2219 return fastEmitInst_r(MachineInstOpcode: PPC::XVSQRTDP, RC: &PPC::VSRCRegClass, Op0);
2220 }
2221 return Register();
2222}
2223
2224Register fastEmit_PPCISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
2225 switch (VT.SimpleTy) {
2226 case MVT::f64: return fastEmit_PPCISD_FSQRT_MVT_f64_r(RetVT, Op0);
2227 case MVT::v4f32: return fastEmit_PPCISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
2228 case MVT::v2f64: return fastEmit_PPCISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
2229 default: return Register();
2230 }
2231}
2232
2233// FastEmit functions for PPCISD::FTSQRT.
2234
2235Register fastEmit_PPCISD_FTSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
2236 if (RetVT.SimpleTy != MVT::i32)
2237 return Register();
2238 if ((Subtarget->hasVSX())) {
2239 return fastEmitInst_r(MachineInstOpcode: PPC::XSTSQRTDP, RC: &PPC::CRRCRegClass, Op0);
2240 }
2241 if ((Subtarget->hasFPU())) {
2242 return fastEmitInst_r(MachineInstOpcode: PPC::FTSQRT, RC: &PPC::CRRCRegClass, Op0);
2243 }
2244 return Register();
2245}
2246
2247Register fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
2248 if (RetVT.SimpleTy != MVT::i32)
2249 return Register();
2250 if ((Subtarget->hasVSX())) {
2251 return fastEmitInst_r(MachineInstOpcode: PPC::XVTSQRTSP, RC: &PPC::CRRCRegClass, Op0);
2252 }
2253 return Register();
2254}
2255
2256Register fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
2257 if (RetVT.SimpleTy != MVT::i32)
2258 return Register();
2259 if ((Subtarget->hasVSX())) {
2260 return fastEmitInst_r(MachineInstOpcode: PPC::XVTSQRTDP, RC: &PPC::CRRCRegClass, Op0);
2261 }
2262 return Register();
2263}
2264
2265Register fastEmit_PPCISD_FTSQRT_r(MVT VT, MVT RetVT, Register Op0) {
2266 switch (VT.SimpleTy) {
2267 case MVT::f64: return fastEmit_PPCISD_FTSQRT_MVT_f64_r(RetVT, Op0);
2268 case MVT::v4f32: return fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(RetVT, Op0);
2269 case MVT::v2f64: return fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(RetVT, Op0);
2270 default: return Register();
2271 }
2272}
2273
2274// FastEmit functions for PPCISD::GET_TLS_MOD_AIX.
2275
2276Register fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i32_r(MVT RetVT, Register Op0) {
2277 if (RetVT.SimpleTy != MVT::i32)
2278 return Register();
2279 return fastEmitInst_r(MachineInstOpcode: PPC::GETtlsMOD32AIX, RC: &PPC::GPRCRegClass, Op0);
2280}
2281
2282Register fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i64_r(MVT RetVT, Register Op0) {
2283 if (RetVT.SimpleTy != MVT::i64)
2284 return Register();
2285 return fastEmitInst_r(MachineInstOpcode: PPC::GETtlsMOD64AIX, RC: &PPC::G8RCRegClass, Op0);
2286}
2287
2288Register fastEmit_PPCISD_GET_TLS_MOD_AIX_r(MVT VT, MVT RetVT, Register Op0) {
2289 switch (VT.SimpleTy) {
2290 case MVT::i32: return fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i32_r(RetVT, Op0);
2291 case MVT::i64: return fastEmit_PPCISD_GET_TLS_MOD_AIX_MVT_i64_r(RetVT, Op0);
2292 default: return Register();
2293 }
2294}
2295
2296// FastEmit functions for PPCISD::MFVSR.
2297
2298Register fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Register Op0) {
2299 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2300 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRWZ, RC: &PPC::GPRCRegClass, Op0);
2301 }
2302 return Register();
2303}
2304
2305Register fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Register Op0) {
2306 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2307 return fastEmitInst_r(MachineInstOpcode: PPC::MFVSRD, RC: &PPC::G8RCRegClass, Op0);
2308 }
2309 return Register();
2310}
2311
2312Register fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, Register Op0) {
2313switch (RetVT.SimpleTy) {
2314 case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0);
2315 case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0);
2316 default: return Register();
2317}
2318}
2319
2320Register fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, Register Op0) {
2321 switch (VT.SimpleTy) {
2322 case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0);
2323 default: return Register();
2324 }
2325}
2326
2327// FastEmit functions for PPCISD::MTCTR.
2328
2329Register fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, Register Op0) {
2330 if (RetVT.SimpleTy != MVT::isVoid)
2331 return Register();
2332 return fastEmitInst_r(MachineInstOpcode: PPC::MTCTR, RC: &PPC::GPRCRegClass, Op0);
2333}
2334
2335Register fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, Register Op0) {
2336 if (RetVT.SimpleTy != MVT::isVoid)
2337 return Register();
2338 return fastEmitInst_r(MachineInstOpcode: PPC::MTCTR8, RC: &PPC::G8RCRegClass, Op0);
2339}
2340
2341Register fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, Register Op0) {
2342 switch (VT.SimpleTy) {
2343 case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0);
2344 case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0);
2345 default: return Register();
2346 }
2347}
2348
2349// FastEmit functions for PPCISD::MTVSRA.
2350
2351Register fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, Register Op0) {
2352 if (RetVT.SimpleTy != MVT::f64)
2353 return Register();
2354 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2355 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWA, RC: &PPC::VSFRCRegClass, Op0);
2356 }
2357 return Register();
2358}
2359
2360Register fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, Register Op0) {
2361 if (RetVT.SimpleTy != MVT::f64)
2362 return Register();
2363 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2364 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRD, RC: &PPC::VSFRCRegClass, Op0);
2365 }
2366 return Register();
2367}
2368
2369Register fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, Register Op0) {
2370 switch (VT.SimpleTy) {
2371 case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0);
2372 case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0);
2373 default: return Register();
2374 }
2375}
2376
2377// FastEmit functions for PPCISD::MTVSRZ.
2378
2379Register fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, Register Op0) {
2380 if (RetVT.SimpleTy != MVT::f64)
2381 return Register();
2382 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) {
2383 return fastEmitInst_r(MachineInstOpcode: PPC::MTVSRWZ, RC: &PPC::VSFRCRegClass, Op0);
2384 }
2385 return Register();
2386}
2387
2388Register fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, Register Op0) {
2389 switch (VT.SimpleTy) {
2390 case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0);
2391 default: return Register();
2392 }
2393}
2394
2395// FastEmit functions for PPCISD::SCALAR_TO_VECTOR_PERMUTED.
2396
2397Register fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(MVT RetVT, Register Op0) {
2398 if (RetVT.SimpleTy != MVT::v4f32)
2399 return Register();
2400 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (Subtarget->isLittleEndian())) {
2401 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
2402 }
2403 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) {
2404 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSPN, RC: &PPC::VSRCRegClass, Op0);
2405 }
2406 return Register();
2407}
2408
2409Register fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(MVT VT, MVT RetVT, Register Op0) {
2410 switch (VT.SimpleTy) {
2411 case MVT::f32: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(RetVT, Op0);
2412 default: return Register();
2413 }
2414}
2415
2416// FastEmit functions for PPCISD::SETBC.
2417
2418Register fastEmit_PPCISD_SETBC_MVT_i1_r(MVT RetVT, Register Op0) {
2419 if (RetVT.SimpleTy != MVT::i32)
2420 return Register();
2421 if ((Subtarget->isISA3_1())) {
2422 return fastEmitInst_r(MachineInstOpcode: PPC::SETBC, RC: &PPC::GPRCRegClass, Op0);
2423 }
2424 return Register();
2425}
2426
2427Register fastEmit_PPCISD_SETBC_r(MVT VT, MVT RetVT, Register Op0) {
2428 switch (VT.SimpleTy) {
2429 case MVT::i1: return fastEmit_PPCISD_SETBC_MVT_i1_r(RetVT, Op0);
2430 default: return Register();
2431 }
2432}
2433
2434// FastEmit functions for PPCISD::SETBCR.
2435
2436Register fastEmit_PPCISD_SETBCR_MVT_i1_r(MVT RetVT, Register Op0) {
2437 if (RetVT.SimpleTy != MVT::i32)
2438 return Register();
2439 if ((Subtarget->isISA3_1())) {
2440 return fastEmitInst_r(MachineInstOpcode: PPC::SETBCR, RC: &PPC::GPRCRegClass, Op0);
2441 }
2442 return Register();
2443}
2444
2445Register fastEmit_PPCISD_SETBCR_r(MVT VT, MVT RetVT, Register Op0) {
2446 switch (VT.SimpleTy) {
2447 case MVT::i1: return fastEmit_PPCISD_SETBCR_MVT_i1_r(RetVT, Op0);
2448 default: return Register();
2449 }
2450}
2451
2452// FastEmit functions for PPCISD::STRICT_FCFID.
2453
2454Register fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(MVT RetVT, Register Op0) {
2455 if (RetVT.SimpleTy != MVT::f64)
2456 return Register();
2457 if ((Subtarget->hasVSX())) {
2458 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDDP, RC: &PPC::VSFRCRegClass, Op0);
2459 }
2460 return fastEmitInst_r(MachineInstOpcode: PPC::FCFID, RC: &PPC::F8RCRegClass, Op0);
2461}
2462
2463Register fastEmit_PPCISD_STRICT_FCFID_r(MVT VT, MVT RetVT, Register Op0) {
2464 switch (VT.SimpleTy) {
2465 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(RetVT, Op0);
2466 default: return Register();
2467 }
2468}
2469
2470// FastEmit functions for PPCISD::STRICT_FCFIDS.
2471
2472Register fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(MVT RetVT, Register Op0) {
2473 if (RetVT.SimpleTy != MVT::f32)
2474 return Register();
2475 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2476 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVSXDSP, RC: &PPC::VSSRCRegClass, Op0);
2477 }
2478 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDS, RC: &PPC::F4RCRegClass, Op0);
2479}
2480
2481Register fastEmit_PPCISD_STRICT_FCFIDS_r(MVT VT, MVT RetVT, Register Op0) {
2482 switch (VT.SimpleTy) {
2483 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(RetVT, Op0);
2484 default: return Register();
2485 }
2486}
2487
2488// FastEmit functions for PPCISD::STRICT_FCFIDU.
2489
2490Register fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(MVT RetVT, Register Op0) {
2491 if (RetVT.SimpleTy != MVT::f64)
2492 return Register();
2493 if ((Subtarget->hasVSX())) {
2494 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDDP, RC: &PPC::VSFRCRegClass, Op0);
2495 }
2496 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDU, RC: &PPC::F8RCRegClass, Op0);
2497}
2498
2499Register fastEmit_PPCISD_STRICT_FCFIDU_r(MVT VT, MVT RetVT, Register Op0) {
2500 switch (VT.SimpleTy) {
2501 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(RetVT, Op0);
2502 default: return Register();
2503 }
2504}
2505
2506// FastEmit functions for PPCISD::STRICT_FCFIDUS.
2507
2508Register fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(MVT RetVT, Register Op0) {
2509 if (RetVT.SimpleTy != MVT::f32)
2510 return Register();
2511 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2512 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVUXDSP, RC: &PPC::VSSRCRegClass, Op0);
2513 }
2514 return fastEmitInst_r(MachineInstOpcode: PPC::FCFIDUS, RC: &PPC::F4RCRegClass, Op0);
2515}
2516
2517Register fastEmit_PPCISD_STRICT_FCFIDUS_r(MVT VT, MVT RetVT, Register Op0) {
2518 switch (VT.SimpleTy) {
2519 case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(RetVT, Op0);
2520 default: return Register();
2521 }
2522}
2523
2524// FastEmit functions for PPCISD::STRICT_FCTIDUZ.
2525
2526Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2527 if (RetVT.SimpleTy != MVT::f32)
2528 return Register();
2529 if ((Subtarget->hasVSX())) {
2530 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDSs, RC: &PPC::VSSRCRegClass, Op0);
2531 }
2532 return Register();
2533}
2534
2535Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2536 if (RetVT.SimpleTy != MVT::f64)
2537 return Register();
2538 if ((Subtarget->hasVSX())) {
2539 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXDS, RC: &PPC::VSFRCRegClass, Op0);
2540 }
2541 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDUZ, RC: &PPC::F8RCRegClass, Op0);
2542}
2543
2544Register fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2545 if (RetVT.SimpleTy != MVT::f128)
2546 return Register();
2547 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2548 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUDZ, RC: &PPC::VRRCRegClass, Op0);
2549 }
2550 return Register();
2551}
2552
2553Register fastEmit_PPCISD_STRICT_FCTIDUZ_r(MVT VT, MVT RetVT, Register Op0) {
2554 switch (VT.SimpleTy) {
2555 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(RetVT, Op0);
2556 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(RetVT, Op0);
2557 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(RetVT, Op0);
2558 default: return Register();
2559 }
2560}
2561
2562// FastEmit functions for PPCISD::STRICT_FCTIDZ.
2563
2564Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(MVT RetVT, Register Op0) {
2565 if (RetVT.SimpleTy != MVT::f32)
2566 return Register();
2567 if ((Subtarget->hasVSX())) {
2568 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDSs, RC: &PPC::VSSRCRegClass, Op0);
2569 }
2570 return Register();
2571}
2572
2573Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(MVT RetVT, Register Op0) {
2574 if (RetVT.SimpleTy != MVT::f64)
2575 return Register();
2576 if ((Subtarget->hasVSX())) {
2577 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXDS, RC: &PPC::VSFRCRegClass, Op0);
2578 }
2579 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIDZ, RC: &PPC::F8RCRegClass, Op0);
2580}
2581
2582Register fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(MVT RetVT, Register Op0) {
2583 if (RetVT.SimpleTy != MVT::f128)
2584 return Register();
2585 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2586 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSDZ, RC: &PPC::VRRCRegClass, Op0);
2587 }
2588 return Register();
2589}
2590
2591Register fastEmit_PPCISD_STRICT_FCTIDZ_r(MVT VT, MVT RetVT, Register Op0) {
2592 switch (VT.SimpleTy) {
2593 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(RetVT, Op0);
2594 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(RetVT, Op0);
2595 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(RetVT, Op0);
2596 default: return Register();
2597 }
2598}
2599
2600// FastEmit functions for PPCISD::STRICT_FCTIWUZ.
2601
2602Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(MVT RetVT, Register Op0) {
2603 if (RetVT.SimpleTy != MVT::f32)
2604 return Register();
2605 if ((Subtarget->hasVSX())) {
2606 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWSs, RC: &PPC::VSSRCRegClass, Op0);
2607 }
2608 return Register();
2609}
2610
2611Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(MVT RetVT, Register Op0) {
2612 if (RetVT.SimpleTy != MVT::f64)
2613 return Register();
2614 if ((Subtarget->hasVSX())) {
2615 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPUXWS, RC: &PPC::VSFRCRegClass, Op0);
2616 }
2617 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWUZ, RC: &PPC::F8RCRegClass, Op0);
2618}
2619
2620Register fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(MVT RetVT, Register Op0) {
2621 if (RetVT.SimpleTy != MVT::f128)
2622 return Register();
2623 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2624 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPUWZ, RC: &PPC::VRRCRegClass, Op0);
2625 }
2626 return Register();
2627}
2628
2629Register fastEmit_PPCISD_STRICT_FCTIWUZ_r(MVT VT, MVT RetVT, Register Op0) {
2630 switch (VT.SimpleTy) {
2631 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(RetVT, Op0);
2632 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(RetVT, Op0);
2633 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(RetVT, Op0);
2634 default: return Register();
2635 }
2636}
2637
2638// FastEmit functions for PPCISD::STRICT_FCTIWZ.
2639
2640Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(MVT RetVT, Register Op0) {
2641 if (RetVT.SimpleTy != MVT::f32)
2642 return Register();
2643 if ((Subtarget->hasVSX())) {
2644 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWSs, RC: &PPC::VSSRCRegClass, Op0);
2645 }
2646 return Register();
2647}
2648
2649Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(MVT RetVT, Register Op0) {
2650 if (RetVT.SimpleTy != MVT::f64)
2651 return Register();
2652 if ((Subtarget->hasVSX())) {
2653 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVDPSXWS, RC: &PPC::VSFRCRegClass, Op0);
2654 }
2655 if ((Subtarget->hasFPU())) {
2656 return fastEmitInst_r(MachineInstOpcode: PPC::FCTIWZ, RC: &PPC::F8RCRegClass, Op0);
2657 }
2658 return Register();
2659}
2660
2661Register fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(MVT RetVT, Register Op0) {
2662 if (RetVT.SimpleTy != MVT::f128)
2663 return Register();
2664 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
2665 return fastEmitInst_r(MachineInstOpcode: PPC::XSCVQPSWZ, RC: &PPC::VRRCRegClass, Op0);
2666 }
2667 return Register();
2668}
2669
2670Register fastEmit_PPCISD_STRICT_FCTIWZ_r(MVT VT, MVT RetVT, Register Op0) {
2671 switch (VT.SimpleTy) {
2672 case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(RetVT, Op0);
2673 case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(RetVT, Op0);
2674 case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(RetVT, Op0);
2675 default: return Register();
2676 }
2677}
2678
2679// FastEmit functions for PPCISD::TLSLD_AIX.
2680
2681Register fastEmit_PPCISD_TLSLD_AIX_MVT_i32_r(MVT RetVT, Register Op0) {
2682 if (RetVT.SimpleTy != MVT::i32)
2683 return Register();
2684 return fastEmitInst_r(MachineInstOpcode: PPC::TLSLDAIX, RC: &PPC::GPRCRegClass, Op0);
2685}
2686
2687Register fastEmit_PPCISD_TLSLD_AIX_MVT_i64_r(MVT RetVT, Register Op0) {
2688 if (RetVT.SimpleTy != MVT::i64)
2689 return Register();
2690 return fastEmitInst_r(MachineInstOpcode: PPC::TLSLDAIX8, RC: &PPC::G8RCRegClass, Op0);
2691}
2692
2693Register fastEmit_PPCISD_TLSLD_AIX_r(MVT VT, MVT RetVT, Register Op0) {
2694 switch (VT.SimpleTy) {
2695 case MVT::i32: return fastEmit_PPCISD_TLSLD_AIX_MVT_i32_r(RetVT, Op0);
2696 case MVT::i64: return fastEmit_PPCISD_TLSLD_AIX_MVT_i64_r(RetVT, Op0);
2697 default: return Register();
2698 }
2699}
2700
2701// FastEmit functions for PPCISD::XXMFACC.
2702
2703Register fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(MVT RetVT, Register Op0) {
2704 if (RetVT.SimpleTy != MVT::v512i1)
2705 return Register();
2706 if ((!Subtarget->isISAFuture()) && (Subtarget->hasMMA())) {
2707 return fastEmitInst_r(MachineInstOpcode: PPC::XXMFACC, RC: &PPC::ACCRCRegClass, Op0);
2708 }
2709 return Register();
2710}
2711
2712Register fastEmit_PPCISD_XXMFACC_r(MVT VT, MVT RetVT, Register Op0) {
2713 switch (VT.SimpleTy) {
2714 case MVT::v512i1: return fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(RetVT, Op0);
2715 default: return Register();
2716 }
2717}
2718
2719// FastEmit functions for PPCISD::XXSPLTI_SP_TO_DP.
2720
2721Register fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(MVT RetVT, Register Op0) {
2722 if (RetVT.SimpleTy != MVT::v2f64)
2723 return Register();
2724 if ((Subtarget->hasPrefixInstrs())) {
2725 return fastEmitInst_r(MachineInstOpcode: PPC::XXSPLTIDP, RC: &PPC::VSRCRegClass, Op0);
2726 }
2727 return Register();
2728}
2729
2730Register fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(MVT VT, MVT RetVT, Register Op0) {
2731 switch (VT.SimpleTy) {
2732 case MVT::i32: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(RetVT, Op0);
2733 default: return Register();
2734 }
2735}
2736
2737// Top-level FastEmit function.
2738
2739Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
2740 switch (Opcode) {
2741 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
2742 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
2743 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0);
2744 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
2745 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
2746 case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0);
2747 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
2748 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0);
2749 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0);
2750 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0);
2751 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
2752 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
2753 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
2754 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
2755 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
2756 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
2757 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0);
2758 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
2759 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0);
2760 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
2761 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
2762 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
2763 case ISD::STRICT_FCEIL: return fastEmit_ISD_STRICT_FCEIL_r(VT, RetVT, Op0);
2764 case ISD::STRICT_FFLOOR: return fastEmit_ISD_STRICT_FFLOOR_r(VT, RetVT, Op0);
2765 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
2766 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
2767 case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0);
2768 case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0);
2769 case ISD::STRICT_FRINT: return fastEmit_ISD_STRICT_FRINT_r(VT, RetVT, Op0);
2770 case ISD::STRICT_FROUND: return fastEmit_ISD_STRICT_FROUND_r(VT, RetVT, Op0);
2771 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
2772 case ISD::STRICT_FTRUNC: return fastEmit_ISD_STRICT_FTRUNC_r(VT, RetVT, Op0);
2773 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
2774 case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0);
2775 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
2776 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
2777 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
2778 case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0);
2779 case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0);
2780 case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0);
2781 case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0);
2782 case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0);
2783 case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0);
2784 case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0);
2785 case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0);
2786 case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0);
2787 case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0);
2788 case PPCISD::FSQRT: return fastEmit_PPCISD_FSQRT_r(VT, RetVT, Op0);
2789 case PPCISD::FTSQRT: return fastEmit_PPCISD_FTSQRT_r(VT, RetVT, Op0);
2790 case PPCISD::GET_TLS_MOD_AIX: return fastEmit_PPCISD_GET_TLS_MOD_AIX_r(VT, RetVT, Op0);
2791 case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0);
2792 case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0);
2793 case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0);
2794 case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0);
2795 case PPCISD::SCALAR_TO_VECTOR_PERMUTED: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(VT, RetVT, Op0);
2796 case PPCISD::SETBC: return fastEmit_PPCISD_SETBC_r(VT, RetVT, Op0);
2797 case PPCISD::SETBCR: return fastEmit_PPCISD_SETBCR_r(VT, RetVT, Op0);
2798 case PPCISD::STRICT_FCFID: return fastEmit_PPCISD_STRICT_FCFID_r(VT, RetVT, Op0);
2799 case PPCISD::STRICT_FCFIDS: return fastEmit_PPCISD_STRICT_FCFIDS_r(VT, RetVT, Op0);
2800 case PPCISD::STRICT_FCFIDU: return fastEmit_PPCISD_STRICT_FCFIDU_r(VT, RetVT, Op0);
2801 case PPCISD::STRICT_FCFIDUS: return fastEmit_PPCISD_STRICT_FCFIDUS_r(VT, RetVT, Op0);
2802 case PPCISD::STRICT_FCTIDUZ: return fastEmit_PPCISD_STRICT_FCTIDUZ_r(VT, RetVT, Op0);
2803 case PPCISD::STRICT_FCTIDZ: return fastEmit_PPCISD_STRICT_FCTIDZ_r(VT, RetVT, Op0);
2804 case PPCISD::STRICT_FCTIWUZ: return fastEmit_PPCISD_STRICT_FCTIWUZ_r(VT, RetVT, Op0);
2805 case PPCISD::STRICT_FCTIWZ: return fastEmit_PPCISD_STRICT_FCTIWZ_r(VT, RetVT, Op0);
2806 case PPCISD::TLSLD_AIX: return fastEmit_PPCISD_TLSLD_AIX_r(VT, RetVT, Op0);
2807 case PPCISD::XXMFACC: return fastEmit_PPCISD_XXMFACC_r(VT, RetVT, Op0);
2808 case PPCISD::XXSPLTI_SP_TO_DP: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(VT, RetVT, Op0);
2809 default: return Register();
2810 }
2811}
2812
2813// FastEmit functions for ISD::ABDU.
2814
2815Register fastEmit_ISD_ABDU_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2816 if (RetVT.SimpleTy != MVT::v16i8)
2817 return Register();
2818 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2819 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUB, RC: &PPC::VRRCRegClass, Op0, Op1);
2820 }
2821 return Register();
2822}
2823
2824Register fastEmit_ISD_ABDU_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2825 if (RetVT.SimpleTy != MVT::v8i16)
2826 return Register();
2827 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2828 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUH, RC: &PPC::VRRCRegClass, Op0, Op1);
2829 }
2830 return Register();
2831}
2832
2833Register fastEmit_ISD_ABDU_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2834 if (RetVT.SimpleTy != MVT::v4i32)
2835 return Register();
2836 if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) {
2837 return fastEmitInst_rr(MachineInstOpcode: PPC::VABSDUW, RC: &PPC::VRRCRegClass, Op0, Op1);
2838 }
2839 return Register();
2840}
2841
2842Register fastEmit_ISD_ABDU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2843 switch (VT.SimpleTy) {
2844 case MVT::v16i8: return fastEmit_ISD_ABDU_MVT_v16i8_rr(RetVT, Op0, Op1);
2845 case MVT::v8i16: return fastEmit_ISD_ABDU_MVT_v8i16_rr(RetVT, Op0, Op1);
2846 case MVT::v4i32: return fastEmit_ISD_ABDU_MVT_v4i32_rr(RetVT, Op0, Op1);
2847 default: return Register();
2848 }
2849}
2850
2851// FastEmit functions for ISD::ADD.
2852
2853Register fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
2854 if (RetVT.SimpleTy != MVT::i1)
2855 return Register();
2856 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
2857}
2858
2859Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2860 if (RetVT.SimpleTy != MVT::i32)
2861 return Register();
2862 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD4, RC: &PPC::GPRCRegClass, Op0, Op1);
2863}
2864
2865Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2866 if (RetVT.SimpleTy != MVT::i64)
2867 return Register();
2868 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD8, RC: &PPC::G8RCRegClass, Op0, Op1);
2869}
2870
2871Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2872 if (RetVT.SimpleTy != MVT::v16i8)
2873 return Register();
2874 if ((Subtarget->hasAltivec())) {
2875 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUBM, RC: &PPC::VRRCRegClass, Op0, Op1);
2876 }
2877 return Register();
2878}
2879
2880Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2881 if (RetVT.SimpleTy != MVT::v8i16)
2882 return Register();
2883 if ((Subtarget->hasAltivec())) {
2884 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUHM, RC: &PPC::VRRCRegClass, Op0, Op1);
2885 }
2886 return Register();
2887}
2888
2889Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2890 if (RetVT.SimpleTy != MVT::v4i32)
2891 return Register();
2892 if ((Subtarget->hasAltivec())) {
2893 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
2894 }
2895 return Register();
2896}
2897
2898Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2899 if (RetVT.SimpleTy != MVT::v2i64)
2900 return Register();
2901 if ((Subtarget->hasP8Altivec())) {
2902 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUDM, RC: &PPC::VRRCRegClass, Op0, Op1);
2903 }
2904 return Register();
2905}
2906
2907Register fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
2908 if (RetVT.SimpleTy != MVT::v1i128)
2909 return Register();
2910 if ((Subtarget->hasP8Altivec())) {
2911 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUQM, RC: &PPC::VRRCRegClass, Op0, Op1);
2912 }
2913 return Register();
2914}
2915
2916Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2917 switch (VT.SimpleTy) {
2918 case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op1);
2919 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
2920 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
2921 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
2922 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
2923 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
2924 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
2925 case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op1);
2926 default: return Register();
2927 }
2928}
2929
2930// FastEmit functions for ISD::AND.
2931
2932Register fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
2933 if (RetVT.SimpleTy != MVT::i1)
2934 return Register();
2935 return fastEmitInst_rr(MachineInstOpcode: PPC::CRAND, RC: &PPC::CRBITRCRegClass, Op0, Op1);
2936}
2937
2938Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2939 if (RetVT.SimpleTy != MVT::i32)
2940 return Register();
2941 return fastEmitInst_rr(MachineInstOpcode: PPC::AND, RC: &PPC::GPRCRegClass, Op0, Op1);
2942}
2943
2944Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2945 if (RetVT.SimpleTy != MVT::i64)
2946 return Register();
2947 return fastEmitInst_rr(MachineInstOpcode: PPC::AND8, RC: &PPC::G8RCRegClass, Op0, Op1);
2948}
2949
2950Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2951 if (RetVT.SimpleTy != MVT::v4i32)
2952 return Register();
2953 if ((Subtarget->hasVSX())) {
2954 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLAND, RC: &PPC::VSRCRegClass, Op0, Op1);
2955 }
2956 if ((Subtarget->hasAltivec())) {
2957 return fastEmitInst_rr(MachineInstOpcode: PPC::VAND, RC: &PPC::VRRCRegClass, Op0, Op1);
2958 }
2959 return Register();
2960}
2961
2962Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2963 switch (VT.SimpleTy) {
2964 case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op1);
2965 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
2966 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
2967 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
2968 default: return Register();
2969 }
2970}
2971
2972// FastEmit functions for ISD::BUILD_VECTOR.
2973
2974Register fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2975 if (RetVT.SimpleTy != MVT::v2i64)
2976 return Register();
2977 if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian()) && (Subtarget->isISA3_0()) && (Subtarget->isPPC64())) {
2978 return fastEmitInst_rr(MachineInstOpcode: PPC::MTVSRDD, RC: &PPC::VSRCRegClass, Op0, Op1);
2979 }
2980 return Register();
2981}
2982
2983Register fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2984 switch (VT.SimpleTy) {
2985 case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op1);
2986 default: return Register();
2987 }
2988}
2989
2990// FastEmit functions for ISD::FADD.
2991
2992Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2993 if (RetVT.SimpleTy != MVT::f32)
2994 return Register();
2995 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
2996 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
2997 }
2998 if ((Subtarget->hasSPE())) {
2999 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSADD, RC: &PPC::GPRCRegClass, Op0, Op1);
3000 }
3001 if ((Subtarget->hasFPU())) {
3002 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDS, RC: &PPC::F4RCRegClass, Op0, Op1);
3003 }
3004 return Register();
3005}
3006
3007Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3008 if (RetVT.SimpleTy != MVT::f64)
3009 return Register();
3010 if ((Subtarget->hasVSX())) {
3011 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3012 }
3013 if ((Subtarget->hasSPE())) {
3014 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDADD, RC: &PPC::SPERCRegClass, Op0, Op1);
3015 }
3016 if ((Subtarget->hasFPU())) {
3017 return fastEmitInst_rr(MachineInstOpcode: PPC::FADD, RC: &PPC::F8RCRegClass, Op0, Op1);
3018 }
3019 return Register();
3020}
3021
3022Register fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3023 if (RetVT.SimpleTy != MVT::f128)
3024 return Register();
3025 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3026 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3027 }
3028 return Register();
3029}
3030
3031Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3032 if (RetVT.SimpleTy != MVT::v4f32)
3033 return Register();
3034 if ((Subtarget->hasVSX())) {
3035 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3036 }
3037 if ((Subtarget->hasAltivec())) {
3038 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDFP, RC: &PPC::VRRCRegClass, Op0, Op1);
3039 }
3040 return Register();
3041}
3042
3043Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3044 if (RetVT.SimpleTy != MVT::v2f64)
3045 return Register();
3046 if ((Subtarget->hasVSX())) {
3047 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3048 }
3049 return Register();
3050}
3051
3052Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3053 switch (VT.SimpleTy) {
3054 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
3055 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
3056 case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op1);
3057 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
3058 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
3059 default: return Register();
3060 }
3061}
3062
3063// FastEmit functions for ISD::FDIV.
3064
3065Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3066 if (RetVT.SimpleTy != MVT::f32)
3067 return Register();
3068 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3069 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3070 }
3071 if ((Subtarget->hasSPE())) {
3072 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSDIV, RC: &PPC::GPRCRegClass, Op0, Op1);
3073 }
3074 if ((Subtarget->hasFPU())) {
3075 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIVS, RC: &PPC::F4RCRegClass, Op0, Op1);
3076 }
3077 return Register();
3078}
3079
3080Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3081 if (RetVT.SimpleTy != MVT::f64)
3082 return Register();
3083 if ((Subtarget->hasVSX())) {
3084 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3085 }
3086 if ((Subtarget->hasSPE())) {
3087 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDDIV, RC: &PPC::SPERCRegClass, Op0, Op1);
3088 }
3089 if ((Subtarget->hasFPU())) {
3090 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIV, RC: &PPC::F8RCRegClass, Op0, Op1);
3091 }
3092 return Register();
3093}
3094
3095Register fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3096 if (RetVT.SimpleTy != MVT::f128)
3097 return Register();
3098 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3099 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3100 }
3101 return Register();
3102}
3103
3104Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3105 if (RetVT.SimpleTy != MVT::v4f32)
3106 return Register();
3107 if ((Subtarget->hasVSX())) {
3108 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3109 }
3110 return Register();
3111}
3112
3113Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3114 if (RetVT.SimpleTy != MVT::v2f64)
3115 return Register();
3116 if ((Subtarget->hasVSX())) {
3117 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3118 }
3119 return Register();
3120}
3121
3122Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3123 switch (VT.SimpleTy) {
3124 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
3125 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
3126 case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op1);
3127 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
3128 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
3129 default: return Register();
3130 }
3131}
3132
3133// FastEmit functions for ISD::FMAXNUM.
3134
3135Register fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3136 if (RetVT.SimpleTy != MVT::v4f32)
3137 return Register();
3138 if ((Subtarget->hasVSX())) {
3139 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3140 }
3141 return Register();
3142}
3143
3144Register fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3145 if (RetVT.SimpleTy != MVT::v2f64)
3146 return Register();
3147 if ((Subtarget->hasVSX())) {
3148 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3149 }
3150 return Register();
3151}
3152
3153Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3154 switch (VT.SimpleTy) {
3155 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
3156 case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
3157 default: return Register();
3158 }
3159}
3160
3161// FastEmit functions for ISD::FMAXNUM_IEEE.
3162
3163Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3164 if (RetVT.SimpleTy != MVT::f64)
3165 return Register();
3166 if ((Subtarget->hasVSX())) {
3167 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3168 }
3169 return Register();
3170}
3171
3172Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3173 switch (VT.SimpleTy) {
3174 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
3175 default: return Register();
3176 }
3177}
3178
3179// FastEmit functions for ISD::FMINNUM.
3180
3181Register fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3182 if (RetVT.SimpleTy != MVT::v4f32)
3183 return Register();
3184 if ((Subtarget->hasVSX())) {
3185 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3186 }
3187 return Register();
3188}
3189
3190Register fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3191 if (RetVT.SimpleTy != MVT::v2f64)
3192 return Register();
3193 if ((Subtarget->hasVSX())) {
3194 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3195 }
3196 return Register();
3197}
3198
3199Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3200 switch (VT.SimpleTy) {
3201 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
3202 case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
3203 default: return Register();
3204 }
3205}
3206
3207// FastEmit functions for ISD::FMINNUM_IEEE.
3208
3209Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3210 if (RetVT.SimpleTy != MVT::f64)
3211 return Register();
3212 if ((Subtarget->hasVSX())) {
3213 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3214 }
3215 return Register();
3216}
3217
3218Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3219 switch (VT.SimpleTy) {
3220 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
3221 default: return Register();
3222 }
3223}
3224
3225// FastEmit functions for ISD::FMUL.
3226
3227Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3228 if (RetVT.SimpleTy != MVT::f32)
3229 return Register();
3230 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3231 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3232 }
3233 if ((Subtarget->hasSPE())) {
3234 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSMUL, RC: &PPC::GPRCRegClass, Op0, Op1);
3235 }
3236 if ((Subtarget->hasFPU())) {
3237 return fastEmitInst_rr(MachineInstOpcode: PPC::FMULS, RC: &PPC::F4RCRegClass, Op0, Op1);
3238 }
3239 return Register();
3240}
3241
3242Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3243 if (RetVT.SimpleTy != MVT::f64)
3244 return Register();
3245 if ((Subtarget->hasVSX())) {
3246 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3247 }
3248 if ((Subtarget->hasSPE())) {
3249 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDMUL, RC: &PPC::SPERCRegClass, Op0, Op1);
3250 }
3251 if ((Subtarget->hasFPU())) {
3252 return fastEmitInst_rr(MachineInstOpcode: PPC::FMUL, RC: &PPC::F8RCRegClass, Op0, Op1);
3253 }
3254 return Register();
3255}
3256
3257Register fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3258 if (RetVT.SimpleTy != MVT::f128)
3259 return Register();
3260 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3261 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3262 }
3263 return Register();
3264}
3265
3266Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3267 if (RetVT.SimpleTy != MVT::v4f32)
3268 return Register();
3269 if ((Subtarget->hasVSX())) {
3270 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3271 }
3272 return Register();
3273}
3274
3275Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3276 if (RetVT.SimpleTy != MVT::v2f64)
3277 return Register();
3278 if ((Subtarget->hasVSX())) {
3279 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3280 }
3281 return Register();
3282}
3283
3284Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3285 switch (VT.SimpleTy) {
3286 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
3287 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
3288 case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op1);
3289 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
3290 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
3291 default: return Register();
3292 }
3293}
3294
3295// FastEmit functions for ISD::FSUB.
3296
3297Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3298 if (RetVT.SimpleTy != MVT::f32)
3299 return Register();
3300 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
3301 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
3302 }
3303 if ((Subtarget->hasSPE())) {
3304 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSSUB, RC: &PPC::GPRCRegClass, Op0, Op1);
3305 }
3306 if ((Subtarget->hasFPU())) {
3307 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUBS, RC: &PPC::F4RCRegClass, Op0, Op1);
3308 }
3309 return Register();
3310}
3311
3312Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
3313 if (RetVT.SimpleTy != MVT::f64)
3314 return Register();
3315 if ((Subtarget->hasVSX())) {
3316 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
3317 }
3318 if ((Subtarget->hasSPE())) {
3319 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDSUB, RC: &PPC::SPERCRegClass, Op0, Op1);
3320 }
3321 if ((Subtarget->hasFPU())) {
3322 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUB, RC: &PPC::F8RCRegClass, Op0, Op1);
3323 }
3324 return Register();
3325}
3326
3327Register fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
3328 if (RetVT.SimpleTy != MVT::f128)
3329 return Register();
3330 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
3331 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBQP, RC: &PPC::VRRCRegClass, Op0, Op1);
3332 }
3333 return Register();
3334}
3335
3336Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
3337 if (RetVT.SimpleTy != MVT::v4f32)
3338 return Register();
3339 if ((Subtarget->hasVSX())) {
3340 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBSP, RC: &PPC::VSRCRegClass, Op0, Op1);
3341 }
3342 if ((Subtarget->hasAltivec())) {
3343 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBFP, RC: &PPC::VRRCRegClass, Op0, Op1);
3344 }
3345 return Register();
3346}
3347
3348Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
3349 if (RetVT.SimpleTy != MVT::v2f64)
3350 return Register();
3351 if ((Subtarget->hasVSX())) {
3352 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBDP, RC: &PPC::VSRCRegClass, Op0, Op1);
3353 }
3354 return Register();
3355}
3356
3357Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3358 switch (VT.SimpleTy) {
3359 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
3360 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
3361 case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op1);
3362 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
3363 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
3364 default: return Register();
3365 }
3366}
3367
3368// FastEmit functions for ISD::MUL.
3369
3370Register fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
3371 if (RetVT.SimpleTy != MVT::i1)
3372 return Register();
3373 return fastEmitInst_rr(MachineInstOpcode: PPC::CRAND, RC: &PPC::CRBITRCRegClass, Op0, Op1);
3374}
3375
3376Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3377 if (RetVT.SimpleTy != MVT::i32)
3378 return Register();
3379 return fastEmitInst_rr(MachineInstOpcode: PPC::MULLW, RC: &PPC::GPRCRegClass, Op0, Op1);
3380}
3381
3382Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3383 if (RetVT.SimpleTy != MVT::i64)
3384 return Register();
3385 return fastEmitInst_rr(MachineInstOpcode: PPC::MULLD, RC: &PPC::G8RCRegClass, Op0, Op1);
3386}
3387
3388Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3389 if (RetVT.SimpleTy != MVT::v4i32)
3390 return Register();
3391 if ((Subtarget->hasP8Altivec())) {
3392 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
3393 }
3394 return Register();
3395}
3396
3397Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3398 if (RetVT.SimpleTy != MVT::v2i64)
3399 return Register();
3400 if ((Subtarget->isISA3_1())) {
3401 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3402 }
3403 return Register();
3404}
3405
3406Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3407 switch (VT.SimpleTy) {
3408 case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op1);
3409 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
3410 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
3411 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
3412 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
3413 default: return Register();
3414 }
3415}
3416
3417// FastEmit functions for ISD::MULHS.
3418
3419Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3420 if (RetVT.SimpleTy != MVT::i32)
3421 return Register();
3422 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHW, RC: &PPC::GPRCRegClass, Op0, Op1);
3423}
3424
3425Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3426 if (RetVT.SimpleTy != MVT::i64)
3427 return Register();
3428 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHD, RC: &PPC::G8RCRegClass, Op0, Op1);
3429}
3430
3431Register fastEmit_ISD_MULHS_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3432 if (RetVT.SimpleTy != MVT::v4i32)
3433 return Register();
3434 if ((Subtarget->isISA3_1())) {
3435 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3436 }
3437 return Register();
3438}
3439
3440Register fastEmit_ISD_MULHS_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3441 if (RetVT.SimpleTy != MVT::v2i64)
3442 return Register();
3443 if ((Subtarget->isISA3_1())) {
3444 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3445 }
3446 return Register();
3447}
3448
3449Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3450 switch (VT.SimpleTy) {
3451 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
3452 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
3453 case MVT::v4i32: return fastEmit_ISD_MULHS_MVT_v4i32_rr(RetVT, Op0, Op1);
3454 case MVT::v2i64: return fastEmit_ISD_MULHS_MVT_v2i64_rr(RetVT, Op0, Op1);
3455 default: return Register();
3456 }
3457}
3458
3459// FastEmit functions for ISD::MULHU.
3460
3461Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3462 if (RetVT.SimpleTy != MVT::i32)
3463 return Register();
3464 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHWU, RC: &PPC::GPRCRegClass, Op0, Op1);
3465}
3466
3467Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3468 if (RetVT.SimpleTy != MVT::i64)
3469 return Register();
3470 return fastEmitInst_rr(MachineInstOpcode: PPC::MULHDU, RC: &PPC::G8RCRegClass, Op0, Op1);
3471}
3472
3473Register fastEmit_ISD_MULHU_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3474 if (RetVT.SimpleTy != MVT::v4i32)
3475 return Register();
3476 if ((Subtarget->isISA3_1())) {
3477 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHUW, RC: &PPC::VRRCRegClass, Op0, Op1);
3478 }
3479 return Register();
3480}
3481
3482Register fastEmit_ISD_MULHU_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3483 if (RetVT.SimpleTy != MVT::v2i64)
3484 return Register();
3485 if ((Subtarget->isISA3_1())) {
3486 return fastEmitInst_rr(MachineInstOpcode: PPC::VMULHUD, RC: &PPC::VRRCRegClass, Op0, Op1);
3487 }
3488 return Register();
3489}
3490
3491Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3492 switch (VT.SimpleTy) {
3493 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
3494 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
3495 case MVT::v4i32: return fastEmit_ISD_MULHU_MVT_v4i32_rr(RetVT, Op0, Op1);
3496 case MVT::v2i64: return fastEmit_ISD_MULHU_MVT_v2i64_rr(RetVT, Op0, Op1);
3497 default: return Register();
3498 }
3499}
3500
3501// FastEmit functions for ISD::OR.
3502
3503Register fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
3504 if (RetVT.SimpleTy != MVT::i1)
3505 return Register();
3506 return fastEmitInst_rr(MachineInstOpcode: PPC::CROR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
3507}
3508
3509Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3510 if (RetVT.SimpleTy != MVT::i32)
3511 return Register();
3512 return fastEmitInst_rr(MachineInstOpcode: PPC::OR, RC: &PPC::GPRCRegClass, Op0, Op1);
3513}
3514
3515Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3516 if (RetVT.SimpleTy != MVT::i64)
3517 return Register();
3518 return fastEmitInst_rr(MachineInstOpcode: PPC::OR8, RC: &PPC::G8RCRegClass, Op0, Op1);
3519}
3520
3521Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3522 if (RetVT.SimpleTy != MVT::v4i32)
3523 return Register();
3524 if ((Subtarget->hasVSX())) {
3525 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLOR, RC: &PPC::VSRCRegClass, Op0, Op1);
3526 }
3527 if ((Subtarget->hasAltivec())) {
3528 return fastEmitInst_rr(MachineInstOpcode: PPC::VOR, RC: &PPC::VRRCRegClass, Op0, Op1);
3529 }
3530 return Register();
3531}
3532
3533Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3534 switch (VT.SimpleTy) {
3535 case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op1);
3536 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
3537 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
3538 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
3539 default: return Register();
3540 }
3541}
3542
3543// FastEmit functions for ISD::ROTL.
3544
3545Register fastEmit_ISD_ROTL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3546 if (RetVT.SimpleTy != MVT::v16i8)
3547 return Register();
3548 if ((Subtarget->hasAltivec())) {
3549 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLB, RC: &PPC::VRRCRegClass, Op0, Op1);
3550 }
3551 return Register();
3552}
3553
3554Register fastEmit_ISD_ROTL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3555 if (RetVT.SimpleTy != MVT::v8i16)
3556 return Register();
3557 if ((Subtarget->hasAltivec())) {
3558 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLH, RC: &PPC::VRRCRegClass, Op0, Op1);
3559 }
3560 return Register();
3561}
3562
3563Register fastEmit_ISD_ROTL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3564 if (RetVT.SimpleTy != MVT::v4i32)
3565 return Register();
3566 if ((Subtarget->hasAltivec())) {
3567 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLW, RC: &PPC::VRRCRegClass, Op0, Op1);
3568 }
3569 return Register();
3570}
3571
3572Register fastEmit_ISD_ROTL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3573 if (RetVT.SimpleTy != MVT::v2i64)
3574 return Register();
3575 if ((Subtarget->hasP8Altivec())) {
3576 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3577 }
3578 return Register();
3579}
3580
3581Register fastEmit_ISD_ROTL_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
3582 if (RetVT.SimpleTy != MVT::v1i128)
3583 return Register();
3584 if ((Subtarget->isISA3_1())) {
3585 return fastEmitInst_rr(MachineInstOpcode: PPC::VRLQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3586 }
3587 return Register();
3588}
3589
3590Register fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3591 switch (VT.SimpleTy) {
3592 case MVT::v16i8: return fastEmit_ISD_ROTL_MVT_v16i8_rr(RetVT, Op0, Op1);
3593 case MVT::v8i16: return fastEmit_ISD_ROTL_MVT_v8i16_rr(RetVT, Op0, Op1);
3594 case MVT::v4i32: return fastEmit_ISD_ROTL_MVT_v4i32_rr(RetVT, Op0, Op1);
3595 case MVT::v2i64: return fastEmit_ISD_ROTL_MVT_v2i64_rr(RetVT, Op0, Op1);
3596 case MVT::v1i128: return fastEmit_ISD_ROTL_MVT_v1i128_rr(RetVT, Op0, Op1);
3597 default: return Register();
3598 }
3599}
3600
3601// FastEmit functions for ISD::SADDSAT.
3602
3603Register fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3604 if (RetVT.SimpleTy != MVT::v16i8)
3605 return Register();
3606 if ((Subtarget->hasAltivec())) {
3607 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSBS, RC: &PPC::VRRCRegClass, Op0, Op1);
3608 }
3609 return Register();
3610}
3611
3612Register fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3613 if (RetVT.SimpleTy != MVT::v8i16)
3614 return Register();
3615 if ((Subtarget->hasAltivec())) {
3616 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSHS, RC: &PPC::VRRCRegClass, Op0, Op1);
3617 }
3618 return Register();
3619}
3620
3621Register fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3622 if (RetVT.SimpleTy != MVT::v4i32)
3623 return Register();
3624 if ((Subtarget->hasAltivec())) {
3625 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDSWS, RC: &PPC::VRRCRegClass, Op0, Op1);
3626 }
3627 return Register();
3628}
3629
3630Register fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3631 switch (VT.SimpleTy) {
3632 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
3633 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
3634 case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
3635 default: return Register();
3636 }
3637}
3638
3639// FastEmit functions for ISD::SDIV.
3640
3641Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3642 if (RetVT.SimpleTy != MVT::i32)
3643 return Register();
3644 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVW, RC: &PPC::GPRCRegClass, Op0, Op1);
3645}
3646
3647Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3648 if (RetVT.SimpleTy != MVT::i64)
3649 return Register();
3650 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVD, RC: &PPC::G8RCRegClass, Op0, Op1);
3651}
3652
3653Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3654 if (RetVT.SimpleTy != MVT::v4i32)
3655 return Register();
3656 if ((Subtarget->isISA3_1())) {
3657 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3658 }
3659 return Register();
3660}
3661
3662Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3663 if (RetVT.SimpleTy != MVT::v2i64)
3664 return Register();
3665 if ((Subtarget->isISA3_1())) {
3666 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3667 }
3668 return Register();
3669}
3670
3671Register fastEmit_ISD_SDIV_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
3672 if (RetVT.SimpleTy != MVT::v1i128)
3673 return Register();
3674 if ((Subtarget->isISA3_1())) {
3675 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVSQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3676 }
3677 return Register();
3678}
3679
3680Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3681 switch (VT.SimpleTy) {
3682 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
3683 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
3684 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
3685 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
3686 case MVT::v1i128: return fastEmit_ISD_SDIV_MVT_v1i128_rr(RetVT, Op0, Op1);
3687 default: return Register();
3688 }
3689}
3690
3691// FastEmit functions for ISD::SHL.
3692
3693Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3694 if (RetVT.SimpleTy != MVT::i32)
3695 return Register();
3696 return fastEmitInst_rr(MachineInstOpcode: PPC::SLW, RC: &PPC::GPRCRegClass, Op0, Op1);
3697}
3698
3699Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3700 if (RetVT.SimpleTy != MVT::v16i8)
3701 return Register();
3702 if ((Subtarget->hasAltivec())) {
3703 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLB, RC: &PPC::VRRCRegClass, Op0, Op1);
3704 }
3705 return Register();
3706}
3707
3708Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3709 if (RetVT.SimpleTy != MVT::v8i16)
3710 return Register();
3711 if ((Subtarget->hasAltivec())) {
3712 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLH, RC: &PPC::VRRCRegClass, Op0, Op1);
3713 }
3714 return Register();
3715}
3716
3717Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3718 if (RetVT.SimpleTy != MVT::v4i32)
3719 return Register();
3720 if ((Subtarget->hasAltivec())) {
3721 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLW, RC: &PPC::VRRCRegClass, Op0, Op1);
3722 }
3723 return Register();
3724}
3725
3726Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3727 if (RetVT.SimpleTy != MVT::v2i64)
3728 return Register();
3729 if ((Subtarget->hasP8Altivec())) {
3730 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLD, RC: &PPC::VRRCRegClass, Op0, Op1);
3731 }
3732 return Register();
3733}
3734
3735Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3736 switch (VT.SimpleTy) {
3737 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
3738 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
3739 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
3740 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
3741 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
3742 default: return Register();
3743 }
3744}
3745
3746// FastEmit functions for ISD::SMAX.
3747
3748Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3749 if (RetVT.SimpleTy != MVT::v16i8)
3750 return Register();
3751 if ((Subtarget->hasAltivec())) {
3752 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSB, RC: &PPC::VRRCRegClass, Op0, Op1);
3753 }
3754 return Register();
3755}
3756
3757Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3758 if (RetVT.SimpleTy != MVT::v8i16)
3759 return Register();
3760 if ((Subtarget->hasAltivec())) {
3761 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3762 }
3763 return Register();
3764}
3765
3766Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3767 if (RetVT.SimpleTy != MVT::v4i32)
3768 return Register();
3769 if ((Subtarget->hasAltivec())) {
3770 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3771 }
3772 return Register();
3773}
3774
3775Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3776 switch (VT.SimpleTy) {
3777 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
3778 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
3779 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
3780 default: return Register();
3781 }
3782}
3783
3784// FastEmit functions for ISD::SMIN.
3785
3786Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3787 if (RetVT.SimpleTy != MVT::v16i8)
3788 return Register();
3789 if ((Subtarget->hasAltivec())) {
3790 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSB, RC: &PPC::VRRCRegClass, Op0, Op1);
3791 }
3792 return Register();
3793}
3794
3795Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3796 if (RetVT.SimpleTy != MVT::v8i16)
3797 return Register();
3798 if ((Subtarget->hasAltivec())) {
3799 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSH, RC: &PPC::VRRCRegClass, Op0, Op1);
3800 }
3801 return Register();
3802}
3803
3804Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3805 if (RetVT.SimpleTy != MVT::v4i32)
3806 return Register();
3807 if ((Subtarget->hasAltivec())) {
3808 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3809 }
3810 return Register();
3811}
3812
3813Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3814 switch (VT.SimpleTy) {
3815 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
3816 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
3817 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
3818 default: return Register();
3819 }
3820}
3821
3822// FastEmit functions for ISD::SRA.
3823
3824Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3825 if (RetVT.SimpleTy != MVT::i32)
3826 return Register();
3827 return fastEmitInst_rr(MachineInstOpcode: PPC::SRAW, RC: &PPC::GPRCRegClass, Op0, Op1);
3828}
3829
3830Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3831 if (RetVT.SimpleTy != MVT::v16i8)
3832 return Register();
3833 if ((Subtarget->hasAltivec())) {
3834 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAB, RC: &PPC::VRRCRegClass, Op0, Op1);
3835 }
3836 return Register();
3837}
3838
3839Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3840 if (RetVT.SimpleTy != MVT::v8i16)
3841 return Register();
3842 if ((Subtarget->hasAltivec())) {
3843 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAH, RC: &PPC::VRRCRegClass, Op0, Op1);
3844 }
3845 return Register();
3846}
3847
3848Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3849 if (RetVT.SimpleTy != MVT::v4i32)
3850 return Register();
3851 if ((Subtarget->hasAltivec())) {
3852 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAW, RC: &PPC::VRRCRegClass, Op0, Op1);
3853 }
3854 return Register();
3855}
3856
3857Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3858 if (RetVT.SimpleTy != MVT::v2i64)
3859 return Register();
3860 if ((Subtarget->hasP8Altivec())) {
3861 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAD, RC: &PPC::VRRCRegClass, Op0, Op1);
3862 }
3863 return Register();
3864}
3865
3866Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3867 switch (VT.SimpleTy) {
3868 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
3869 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
3870 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
3871 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
3872 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
3873 default: return Register();
3874 }
3875}
3876
3877// FastEmit functions for ISD::SREM.
3878
3879Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3880 if (RetVT.SimpleTy != MVT::i32)
3881 return Register();
3882 if ((Subtarget->isISA3_0())) {
3883 return fastEmitInst_rr(MachineInstOpcode: PPC::MODSW, RC: &PPC::GPRCRegClass, Op0, Op1);
3884 }
3885 return Register();
3886}
3887
3888Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3889 if (RetVT.SimpleTy != MVT::i64)
3890 return Register();
3891 if ((Subtarget->isISA3_0())) {
3892 return fastEmitInst_rr(MachineInstOpcode: PPC::MODSD, RC: &PPC::G8RCRegClass, Op0, Op1);
3893 }
3894 return Register();
3895}
3896
3897Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3898 if (RetVT.SimpleTy != MVT::v4i32)
3899 return Register();
3900 if ((Subtarget->isISA3_1())) {
3901 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSW, RC: &PPC::VRRCRegClass, Op0, Op1);
3902 }
3903 return Register();
3904}
3905
3906Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3907 if (RetVT.SimpleTy != MVT::v2i64)
3908 return Register();
3909 if ((Subtarget->isISA3_1())) {
3910 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSD, RC: &PPC::VRRCRegClass, Op0, Op1);
3911 }
3912 return Register();
3913}
3914
3915Register fastEmit_ISD_SREM_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
3916 if (RetVT.SimpleTy != MVT::v1i128)
3917 return Register();
3918 if ((Subtarget->isISA3_1())) {
3919 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODSQ, RC: &PPC::VRRCRegClass, Op0, Op1);
3920 }
3921 return Register();
3922}
3923
3924Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3925 switch (VT.SimpleTy) {
3926 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
3927 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
3928 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
3929 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
3930 case MVT::v1i128: return fastEmit_ISD_SREM_MVT_v1i128_rr(RetVT, Op0, Op1);
3931 default: return Register();
3932 }
3933}
3934
3935// FastEmit functions for ISD::SRL.
3936
3937Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3938 if (RetVT.SimpleTy != MVT::i32)
3939 return Register();
3940 return fastEmitInst_rr(MachineInstOpcode: PPC::SRW, RC: &PPC::GPRCRegClass, Op0, Op1);
3941}
3942
3943Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3944 if (RetVT.SimpleTy != MVT::v16i8)
3945 return Register();
3946 if ((Subtarget->hasAltivec())) {
3947 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRB, RC: &PPC::VRRCRegClass, Op0, Op1);
3948 }
3949 return Register();
3950}
3951
3952Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3953 if (RetVT.SimpleTy != MVT::v8i16)
3954 return Register();
3955 if ((Subtarget->hasAltivec())) {
3956 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRH, RC: &PPC::VRRCRegClass, Op0, Op1);
3957 }
3958 return Register();
3959}
3960
3961Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3962 if (RetVT.SimpleTy != MVT::v4i32)
3963 return Register();
3964 if ((Subtarget->hasAltivec())) {
3965 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRW, RC: &PPC::VRRCRegClass, Op0, Op1);
3966 }
3967 return Register();
3968}
3969
3970Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3971 if (RetVT.SimpleTy != MVT::v2i64)
3972 return Register();
3973 if ((Subtarget->hasP8Altivec())) {
3974 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRD, RC: &PPC::VRRCRegClass, Op0, Op1);
3975 }
3976 return Register();
3977}
3978
3979Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3980 switch (VT.SimpleTy) {
3981 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
3982 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
3983 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
3984 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
3985 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
3986 default: return Register();
3987 }
3988}
3989
3990// FastEmit functions for ISD::SSUBSAT.
3991
3992Register fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3993 if (RetVT.SimpleTy != MVT::v16i8)
3994 return Register();
3995 if ((Subtarget->hasAltivec())) {
3996 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSBS, RC: &PPC::VRRCRegClass, Op0, Op1);
3997 }
3998 return Register();
3999}
4000
4001Register fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4002 if (RetVT.SimpleTy != MVT::v8i16)
4003 return Register();
4004 if ((Subtarget->hasAltivec())) {
4005 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4006 }
4007 return Register();
4008}
4009
4010Register fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4011 if (RetVT.SimpleTy != MVT::v4i32)
4012 return Register();
4013 if ((Subtarget->hasAltivec())) {
4014 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBSWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4015 }
4016 return Register();
4017}
4018
4019Register fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4020 switch (VT.SimpleTy) {
4021 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4022 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4023 case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4024 default: return Register();
4025 }
4026}
4027
4028// FastEmit functions for ISD::STRICT_FADD.
4029
4030Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4031 if (RetVT.SimpleTy != MVT::f32)
4032 return Register();
4033 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4034 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4035 }
4036 if ((Subtarget->hasSPE())) {
4037 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSADD, RC: &PPC::GPRCRegClass, Op0, Op1);
4038 }
4039 if ((Subtarget->hasFPU())) {
4040 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDS, RC: &PPC::F4RCRegClass, Op0, Op1);
4041 }
4042 return Register();
4043}
4044
4045Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4046 if (RetVT.SimpleTy != MVT::f64)
4047 return Register();
4048 if ((Subtarget->hasVSX())) {
4049 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4050 }
4051 if ((Subtarget->hasSPE())) {
4052 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDADD, RC: &PPC::SPERCRegClass, Op0, Op1);
4053 }
4054 if ((Subtarget->hasFPU())) {
4055 return fastEmitInst_rr(MachineInstOpcode: PPC::FADD, RC: &PPC::F8RCRegClass, Op0, Op1);
4056 }
4057 return Register();
4058}
4059
4060Register fastEmit_ISD_STRICT_FADD_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4061 if (RetVT.SimpleTy != MVT::f128)
4062 return Register();
4063 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4064 return fastEmitInst_rr(MachineInstOpcode: PPC::XSADDQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4065 }
4066 return Register();
4067}
4068
4069Register fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4070 if (RetVT.SimpleTy != MVT::v4f32)
4071 return Register();
4072 if ((Subtarget->hasVSX())) {
4073 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4074 }
4075 return Register();
4076}
4077
4078Register fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4079 if (RetVT.SimpleTy != MVT::v2f64)
4080 return Register();
4081 if ((Subtarget->hasVSX())) {
4082 return fastEmitInst_rr(MachineInstOpcode: PPC::XVADDDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4083 }
4084 return Register();
4085}
4086
4087Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4088 switch (VT.SimpleTy) {
4089 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
4090 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
4091 case MVT::f128: return fastEmit_ISD_STRICT_FADD_MVT_f128_rr(RetVT, Op0, Op1);
4092 case MVT::v4f32: return fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
4093 case MVT::v2f64: return fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
4094 default: return Register();
4095 }
4096}
4097
4098// FastEmit functions for ISD::STRICT_FDIV.
4099
4100Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4101 if (RetVT.SimpleTy != MVT::f32)
4102 return Register();
4103 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4104 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4105 }
4106 if ((Subtarget->hasSPE())) {
4107 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSDIV, RC: &PPC::GPRCRegClass, Op0, Op1);
4108 }
4109 if ((Subtarget->hasFPU())) {
4110 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIVS, RC: &PPC::F4RCRegClass, Op0, Op1);
4111 }
4112 return Register();
4113}
4114
4115Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4116 if (RetVT.SimpleTy != MVT::f64)
4117 return Register();
4118 if ((Subtarget->hasVSX())) {
4119 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4120 }
4121 if ((Subtarget->hasSPE())) {
4122 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDDIV, RC: &PPC::SPERCRegClass, Op0, Op1);
4123 }
4124 if ((Subtarget->hasFPU())) {
4125 return fastEmitInst_rr(MachineInstOpcode: PPC::FDIV, RC: &PPC::F8RCRegClass, Op0, Op1);
4126 }
4127 return Register();
4128}
4129
4130Register fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4131 if (RetVT.SimpleTy != MVT::f128)
4132 return Register();
4133 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4134 return fastEmitInst_rr(MachineInstOpcode: PPC::XSDIVQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4135 }
4136 return Register();
4137}
4138
4139Register fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4140 if (RetVT.SimpleTy != MVT::v4f32)
4141 return Register();
4142 if ((Subtarget->hasVSX())) {
4143 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4144 }
4145 return Register();
4146}
4147
4148Register fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4149 if (RetVT.SimpleTy != MVT::v2f64)
4150 return Register();
4151 if ((Subtarget->hasVSX())) {
4152 return fastEmitInst_rr(MachineInstOpcode: PPC::XVDIVDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4153 }
4154 return Register();
4155}
4156
4157Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4158 switch (VT.SimpleTy) {
4159 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
4160 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
4161 case MVT::f128: return fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(RetVT, Op0, Op1);
4162 case MVT::v4f32: return fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
4163 case MVT::v2f64: return fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
4164 default: return Register();
4165 }
4166}
4167
4168// FastEmit functions for ISD::STRICT_FMAXNUM.
4169
4170Register fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4171 if (RetVT.SimpleTy != MVT::v4f32)
4172 return Register();
4173 if ((Subtarget->hasVSX())) {
4174 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4175 }
4176 return Register();
4177}
4178
4179Register fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4180 if (RetVT.SimpleTy != MVT::v2f64)
4181 return Register();
4182 if ((Subtarget->hasVSX())) {
4183 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMAXDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4184 }
4185 return Register();
4186}
4187
4188Register fastEmit_ISD_STRICT_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4189 switch (VT.SimpleTy) {
4190 case MVT::v4f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
4191 case MVT::v2f64: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
4192 default: return Register();
4193 }
4194}
4195
4196// FastEmit functions for ISD::STRICT_FMINNUM.
4197
4198Register fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4199 if (RetVT.SimpleTy != MVT::v4f32)
4200 return Register();
4201 if ((Subtarget->hasVSX())) {
4202 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4203 }
4204 return Register();
4205}
4206
4207Register fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4208 if (RetVT.SimpleTy != MVT::v2f64)
4209 return Register();
4210 if ((Subtarget->hasVSX())) {
4211 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMINDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4212 }
4213 return Register();
4214}
4215
4216Register fastEmit_ISD_STRICT_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4217 switch (VT.SimpleTy) {
4218 case MVT::v4f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1);
4219 case MVT::v2f64: return fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1);
4220 default: return Register();
4221 }
4222}
4223
4224// FastEmit functions for ISD::STRICT_FMUL.
4225
4226Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4227 if (RetVT.SimpleTy != MVT::f32)
4228 return Register();
4229 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4230 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4231 }
4232 if ((Subtarget->hasSPE())) {
4233 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSMUL, RC: &PPC::GPRCRegClass, Op0, Op1);
4234 }
4235 if ((Subtarget->hasFPU())) {
4236 return fastEmitInst_rr(MachineInstOpcode: PPC::FMULS, RC: &PPC::F4RCRegClass, Op0, Op1);
4237 }
4238 return Register();
4239}
4240
4241Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4242 if (RetVT.SimpleTy != MVT::f64)
4243 return Register();
4244 if ((Subtarget->hasVSX())) {
4245 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4246 }
4247 if ((Subtarget->hasSPE())) {
4248 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDMUL, RC: &PPC::SPERCRegClass, Op0, Op1);
4249 }
4250 if ((Subtarget->hasFPU())) {
4251 return fastEmitInst_rr(MachineInstOpcode: PPC::FMUL, RC: &PPC::F8RCRegClass, Op0, Op1);
4252 }
4253 return Register();
4254}
4255
4256Register fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4257 if (RetVT.SimpleTy != MVT::f128)
4258 return Register();
4259 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4260 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMULQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4261 }
4262 return Register();
4263}
4264
4265Register fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4266 if (RetVT.SimpleTy != MVT::v4f32)
4267 return Register();
4268 if ((Subtarget->hasVSX())) {
4269 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4270 }
4271 return Register();
4272}
4273
4274Register fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4275 if (RetVT.SimpleTy != MVT::v2f64)
4276 return Register();
4277 if ((Subtarget->hasVSX())) {
4278 return fastEmitInst_rr(MachineInstOpcode: PPC::XVMULDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4279 }
4280 return Register();
4281}
4282
4283Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4284 switch (VT.SimpleTy) {
4285 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
4286 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
4287 case MVT::f128: return fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(RetVT, Op0, Op1);
4288 case MVT::v4f32: return fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
4289 case MVT::v2f64: return fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
4290 default: return Register();
4291 }
4292}
4293
4294// FastEmit functions for ISD::STRICT_FSUB.
4295
4296Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
4297 if (RetVT.SimpleTy != MVT::f32)
4298 return Register();
4299 if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) {
4300 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBSP, RC: &PPC::VSSRCRegClass, Op0, Op1);
4301 }
4302 if ((Subtarget->hasSPE())) {
4303 return fastEmitInst_rr(MachineInstOpcode: PPC::EFSSUB, RC: &PPC::GPRCRegClass, Op0, Op1);
4304 }
4305 if ((Subtarget->hasFPU())) {
4306 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUBS, RC: &PPC::F4RCRegClass, Op0, Op1);
4307 }
4308 return Register();
4309}
4310
4311Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4312 if (RetVT.SimpleTy != MVT::f64)
4313 return Register();
4314 if ((Subtarget->hasVSX())) {
4315 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
4316 }
4317 if ((Subtarget->hasSPE())) {
4318 return fastEmitInst_rr(MachineInstOpcode: PPC::EFDSUB, RC: &PPC::SPERCRegClass, Op0, Op1);
4319 }
4320 if ((Subtarget->hasFPU())) {
4321 return fastEmitInst_rr(MachineInstOpcode: PPC::FSUB, RC: &PPC::F8RCRegClass, Op0, Op1);
4322 }
4323 return Register();
4324}
4325
4326Register fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
4327 if (RetVT.SimpleTy != MVT::f128)
4328 return Register();
4329 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
4330 return fastEmitInst_rr(MachineInstOpcode: PPC::XSSUBQP, RC: &PPC::VRRCRegClass, Op0, Op1);
4331 }
4332 return Register();
4333}
4334
4335Register fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
4336 if (RetVT.SimpleTy != MVT::v4f32)
4337 return Register();
4338 if ((Subtarget->hasVSX())) {
4339 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBSP, RC: &PPC::VSRCRegClass, Op0, Op1);
4340 }
4341 return Register();
4342}
4343
4344Register fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
4345 if (RetVT.SimpleTy != MVT::v2f64)
4346 return Register();
4347 if ((Subtarget->hasVSX())) {
4348 return fastEmitInst_rr(MachineInstOpcode: PPC::XVSUBDP, RC: &PPC::VSRCRegClass, Op0, Op1);
4349 }
4350 return Register();
4351}
4352
4353Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4354 switch (VT.SimpleTy) {
4355 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
4356 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
4357 case MVT::f128: return fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(RetVT, Op0, Op1);
4358 case MVT::v4f32: return fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
4359 case MVT::v2f64: return fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
4360 default: return Register();
4361 }
4362}
4363
4364// FastEmit functions for ISD::SUB.
4365
4366Register fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
4367 if (RetVT.SimpleTy != MVT::i1)
4368 return Register();
4369 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
4370}
4371
4372Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4373 if (RetVT.SimpleTy != MVT::v16i8)
4374 return Register();
4375 if ((Subtarget->hasAltivec())) {
4376 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUBM, RC: &PPC::VRRCRegClass, Op0, Op1);
4377 }
4378 return Register();
4379}
4380
4381Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4382 if (RetVT.SimpleTy != MVT::v8i16)
4383 return Register();
4384 if ((Subtarget->hasAltivec())) {
4385 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUHM, RC: &PPC::VRRCRegClass, Op0, Op1);
4386 }
4387 return Register();
4388}
4389
4390Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4391 if (RetVT.SimpleTy != MVT::v4i32)
4392 return Register();
4393 if ((Subtarget->hasAltivec())) {
4394 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUWM, RC: &PPC::VRRCRegClass, Op0, Op1);
4395 }
4396 return Register();
4397}
4398
4399Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4400 if (RetVT.SimpleTy != MVT::v2i64)
4401 return Register();
4402 if ((Subtarget->hasP8Altivec())) {
4403 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUDM, RC: &PPC::VRRCRegClass, Op0, Op1);
4404 }
4405 return Register();
4406}
4407
4408Register fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4409 if (RetVT.SimpleTy != MVT::v1i128)
4410 return Register();
4411 if ((Subtarget->hasP8Altivec())) {
4412 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUQM, RC: &PPC::VRRCRegClass, Op0, Op1);
4413 }
4414 return Register();
4415}
4416
4417Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4418 switch (VT.SimpleTy) {
4419 case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op1);
4420 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
4421 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
4422 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
4423 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
4424 case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op1);
4425 default: return Register();
4426 }
4427}
4428
4429// FastEmit functions for ISD::UADDSAT.
4430
4431Register fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4432 if (RetVT.SimpleTy != MVT::v16i8)
4433 return Register();
4434 if ((Subtarget->hasAltivec())) {
4435 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4436 }
4437 return Register();
4438}
4439
4440Register fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4441 if (RetVT.SimpleTy != MVT::v8i16)
4442 return Register();
4443 if ((Subtarget->hasAltivec())) {
4444 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4445 }
4446 return Register();
4447}
4448
4449Register fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4450 if (RetVT.SimpleTy != MVT::v4i32)
4451 return Register();
4452 if ((Subtarget->hasAltivec())) {
4453 return fastEmitInst_rr(MachineInstOpcode: PPC::VADDUWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4454 }
4455 return Register();
4456}
4457
4458Register fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4459 switch (VT.SimpleTy) {
4460 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4461 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4462 case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4463 default: return Register();
4464 }
4465}
4466
4467// FastEmit functions for ISD::UDIV.
4468
4469Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4470 if (RetVT.SimpleTy != MVT::i32)
4471 return Register();
4472 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVWU, RC: &PPC::GPRCRegClass, Op0, Op1);
4473}
4474
4475Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4476 if (RetVT.SimpleTy != MVT::i64)
4477 return Register();
4478 return fastEmitInst_rr(MachineInstOpcode: PPC::DIVDU, RC: &PPC::G8RCRegClass, Op0, Op1);
4479}
4480
4481Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4482 if (RetVT.SimpleTy != MVT::v4i32)
4483 return Register();
4484 if ((Subtarget->isISA3_1())) {
4485 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4486 }
4487 return Register();
4488}
4489
4490Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4491 if (RetVT.SimpleTy != MVT::v2i64)
4492 return Register();
4493 if ((Subtarget->isISA3_1())) {
4494 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUD, RC: &PPC::VRRCRegClass, Op0, Op1);
4495 }
4496 return Register();
4497}
4498
4499Register fastEmit_ISD_UDIV_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4500 if (RetVT.SimpleTy != MVT::v1i128)
4501 return Register();
4502 if ((Subtarget->isISA3_1())) {
4503 return fastEmitInst_rr(MachineInstOpcode: PPC::VDIVUQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4504 }
4505 return Register();
4506}
4507
4508Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4509 switch (VT.SimpleTy) {
4510 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
4511 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
4512 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
4513 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
4514 case MVT::v1i128: return fastEmit_ISD_UDIV_MVT_v1i128_rr(RetVT, Op0, Op1);
4515 default: return Register();
4516 }
4517}
4518
4519// FastEmit functions for ISD::UMAX.
4520
4521Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4522 if (RetVT.SimpleTy != MVT::v16i8)
4523 return Register();
4524 if ((Subtarget->hasAltivec())) {
4525 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUB, RC: &PPC::VRRCRegClass, Op0, Op1);
4526 }
4527 return Register();
4528}
4529
4530Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4531 if (RetVT.SimpleTy != MVT::v8i16)
4532 return Register();
4533 if ((Subtarget->hasAltivec())) {
4534 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUH, RC: &PPC::VRRCRegClass, Op0, Op1);
4535 }
4536 return Register();
4537}
4538
4539Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4540 if (RetVT.SimpleTy != MVT::v4i32)
4541 return Register();
4542 if ((Subtarget->hasAltivec())) {
4543 return fastEmitInst_rr(MachineInstOpcode: PPC::VMAXUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4544 }
4545 return Register();
4546}
4547
4548Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4549 switch (VT.SimpleTy) {
4550 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
4551 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
4552 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
4553 default: return Register();
4554 }
4555}
4556
4557// FastEmit functions for ISD::UMIN.
4558
4559Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4560 if (RetVT.SimpleTy != MVT::v16i8)
4561 return Register();
4562 if ((Subtarget->hasAltivec())) {
4563 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUB, RC: &PPC::VRRCRegClass, Op0, Op1);
4564 }
4565 return Register();
4566}
4567
4568Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4569 if (RetVT.SimpleTy != MVT::v8i16)
4570 return Register();
4571 if ((Subtarget->hasAltivec())) {
4572 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUH, RC: &PPC::VRRCRegClass, Op0, Op1);
4573 }
4574 return Register();
4575}
4576
4577Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4578 if (RetVT.SimpleTy != MVT::v4i32)
4579 return Register();
4580 if ((Subtarget->hasAltivec())) {
4581 return fastEmitInst_rr(MachineInstOpcode: PPC::VMINUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4582 }
4583 return Register();
4584}
4585
4586Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4587 switch (VT.SimpleTy) {
4588 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
4589 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
4590 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
4591 default: return Register();
4592 }
4593}
4594
4595// FastEmit functions for ISD::UREM.
4596
4597Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4598 if (RetVT.SimpleTy != MVT::i32)
4599 return Register();
4600 if ((Subtarget->isISA3_0())) {
4601 return fastEmitInst_rr(MachineInstOpcode: PPC::MODUW, RC: &PPC::GPRCRegClass, Op0, Op1);
4602 }
4603 return Register();
4604}
4605
4606Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4607 if (RetVT.SimpleTy != MVT::i64)
4608 return Register();
4609 if ((Subtarget->isISA3_0())) {
4610 return fastEmitInst_rr(MachineInstOpcode: PPC::MODUD, RC: &PPC::G8RCRegClass, Op0, Op1);
4611 }
4612 return Register();
4613}
4614
4615Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4616 if (RetVT.SimpleTy != MVT::v4i32)
4617 return Register();
4618 if ((Subtarget->isISA3_1())) {
4619 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUW, RC: &PPC::VRRCRegClass, Op0, Op1);
4620 }
4621 return Register();
4622}
4623
4624Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4625 if (RetVT.SimpleTy != MVT::v2i64)
4626 return Register();
4627 if ((Subtarget->isISA3_1())) {
4628 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUD, RC: &PPC::VRRCRegClass, Op0, Op1);
4629 }
4630 return Register();
4631}
4632
4633Register fastEmit_ISD_UREM_MVT_v1i128_rr(MVT RetVT, Register Op0, Register Op1) {
4634 if (RetVT.SimpleTy != MVT::v1i128)
4635 return Register();
4636 if ((Subtarget->isISA3_1())) {
4637 return fastEmitInst_rr(MachineInstOpcode: PPC::VMODUQ, RC: &PPC::VRRCRegClass, Op0, Op1);
4638 }
4639 return Register();
4640}
4641
4642Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4643 switch (VT.SimpleTy) {
4644 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
4645 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
4646 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
4647 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
4648 case MVT::v1i128: return fastEmit_ISD_UREM_MVT_v1i128_rr(RetVT, Op0, Op1);
4649 default: return Register();
4650 }
4651}
4652
4653// FastEmit functions for ISD::USUBSAT.
4654
4655Register fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4656 if (RetVT.SimpleTy != MVT::v16i8)
4657 return Register();
4658 if ((Subtarget->hasAltivec())) {
4659 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUBS, RC: &PPC::VRRCRegClass, Op0, Op1);
4660 }
4661 return Register();
4662}
4663
4664Register fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4665 if (RetVT.SimpleTy != MVT::v8i16)
4666 return Register();
4667 if ((Subtarget->hasAltivec())) {
4668 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUHS, RC: &PPC::VRRCRegClass, Op0, Op1);
4669 }
4670 return Register();
4671}
4672
4673Register fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4674 if (RetVT.SimpleTy != MVT::v4i32)
4675 return Register();
4676 if ((Subtarget->hasAltivec())) {
4677 return fastEmitInst_rr(MachineInstOpcode: PPC::VSUBUWS, RC: &PPC::VRRCRegClass, Op0, Op1);
4678 }
4679 return Register();
4680}
4681
4682Register fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4683 switch (VT.SimpleTy) {
4684 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1);
4685 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1);
4686 case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1);
4687 default: return Register();
4688 }
4689}
4690
4691// FastEmit functions for ISD::XOR.
4692
4693Register fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, Register Op0, Register Op1) {
4694 if (RetVT.SimpleTy != MVT::i1)
4695 return Register();
4696 return fastEmitInst_rr(MachineInstOpcode: PPC::CRXOR, RC: &PPC::CRBITRCRegClass, Op0, Op1);
4697}
4698
4699Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4700 if (RetVT.SimpleTy != MVT::i32)
4701 return Register();
4702 return fastEmitInst_rr(MachineInstOpcode: PPC::XOR, RC: &PPC::GPRCRegClass, Op0, Op1);
4703}
4704
4705Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4706 if (RetVT.SimpleTy != MVT::i64)
4707 return Register();
4708 return fastEmitInst_rr(MachineInstOpcode: PPC::XOR8, RC: &PPC::G8RCRegClass, Op0, Op1);
4709}
4710
4711Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4712 if (RetVT.SimpleTy != MVT::v4i32)
4713 return Register();
4714 if ((Subtarget->hasVSX())) {
4715 return fastEmitInst_rr(MachineInstOpcode: PPC::XXLXOR, RC: &PPC::VSRCRegClass, Op0, Op1);
4716 }
4717 if ((Subtarget->hasAltivec())) {
4718 return fastEmitInst_rr(MachineInstOpcode: PPC::VXOR, RC: &PPC::VRRCRegClass, Op0, Op1);
4719 }
4720 return Register();
4721}
4722
4723Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4724 switch (VT.SimpleTy) {
4725 case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op1);
4726 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
4727 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
4728 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
4729 default: return Register();
4730 }
4731}
4732
4733// FastEmit functions for PPCISD::ADD_TLS.
4734
4735Register fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4736 if (RetVT.SimpleTy != MVT::i32)
4737 return Register();
4738 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD4TLS, RC: &PPC::GPRCRegClass, Op0, Op1);
4739}
4740
4741Register fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4742 if (RetVT.SimpleTy != MVT::i64)
4743 return Register();
4744 return fastEmitInst_rr(MachineInstOpcode: PPC::ADD8TLS, RC: &PPC::G8RCRegClass, Op0, Op1);
4745}
4746
4747Register fastEmit_PPCISD_ADD_TLS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4748 switch (VT.SimpleTy) {
4749 case MVT::i32: return fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(RetVT, Op0, Op1);
4750 case MVT::i64: return fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(RetVT, Op0, Op1);
4751 default: return Register();
4752 }
4753}
4754
4755// FastEmit functions for PPCISD::CMPB.
4756
4757Register fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4758 if (RetVT.SimpleTy != MVT::i32)
4759 return Register();
4760 return fastEmitInst_rr(MachineInstOpcode: PPC::CMPB, RC: &PPC::GPRCRegClass, Op0, Op1);
4761}
4762
4763Register fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4764 if (RetVT.SimpleTy != MVT::i64)
4765 return Register();
4766 return fastEmitInst_rr(MachineInstOpcode: PPC::CMPB8, RC: &PPC::G8RCRegClass, Op0, Op1);
4767}
4768
4769Register fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4770 switch (VT.SimpleTy) {
4771 case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op1);
4772 case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op1);
4773 default: return Register();
4774 }
4775}
4776
4777// FastEmit functions for PPCISD::FADDRTZ.
4778
4779Register fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4780 if (RetVT.SimpleTy != MVT::f64)
4781 return Register();
4782 if ((Subtarget->hasFPU())) {
4783 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDrtz, RC: &PPC::F8RCRegClass, Op0, Op1);
4784 }
4785 return Register();
4786}
4787
4788Register fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4789 switch (VT.SimpleTy) {
4790 case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1);
4791 default: return Register();
4792 }
4793}
4794
4795// FastEmit functions for PPCISD::GET_TLS_ADDR.
4796
4797Register fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4798 if (RetVT.SimpleTy != MVT::i32)
4799 return Register();
4800 return fastEmitInst_rr(MachineInstOpcode: PPC::GETtlsADDR32AIX, RC: &PPC::GPRCRegClass, Op0, Op1);
4801}
4802
4803Register fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
4804 if (RetVT.SimpleTy != MVT::i64)
4805 return Register();
4806 return fastEmitInst_rr(MachineInstOpcode: PPC::GETtlsADDR64AIX, RC: &PPC::G8RCRegClass, Op0, Op1);
4807}
4808
4809Register fastEmit_PPCISD_GET_TLS_ADDR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4810 switch (VT.SimpleTy) {
4811 case MVT::i32: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(RetVT, Op0, Op1);
4812 case MVT::i64: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(RetVT, Op0, Op1);
4813 default: return Register();
4814 }
4815}
4816
4817// FastEmit functions for PPCISD::SHL.
4818
4819Register fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4820 if (RetVT.SimpleTy != MVT::i32)
4821 return Register();
4822 return fastEmitInst_rr(MachineInstOpcode: PPC::SLW, RC: &PPC::GPRCRegClass, Op0, Op1);
4823}
4824
4825Register fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4826 if (RetVT.SimpleTy != MVT::v16i8)
4827 return Register();
4828 if ((Subtarget->hasAltivec())) {
4829 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLB, RC: &PPC::VRRCRegClass, Op0, Op1);
4830 }
4831 return Register();
4832}
4833
4834Register fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4835 if (RetVT.SimpleTy != MVT::v8i16)
4836 return Register();
4837 if ((Subtarget->hasAltivec())) {
4838 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLH, RC: &PPC::VRRCRegClass, Op0, Op1);
4839 }
4840 return Register();
4841}
4842
4843Register fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4844 if (RetVT.SimpleTy != MVT::v4i32)
4845 return Register();
4846 if ((Subtarget->hasAltivec())) {
4847 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLW, RC: &PPC::VRRCRegClass, Op0, Op1);
4848 }
4849 return Register();
4850}
4851
4852Register fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4853 if (RetVT.SimpleTy != MVT::v2i64)
4854 return Register();
4855 if ((Subtarget->hasP8Altivec())) {
4856 return fastEmitInst_rr(MachineInstOpcode: PPC::VSLD, RC: &PPC::VRRCRegClass, Op0, Op1);
4857 }
4858 return Register();
4859}
4860
4861Register fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4862 switch (VT.SimpleTy) {
4863 case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
4864 case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
4865 case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
4866 case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
4867 case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
4868 default: return Register();
4869 }
4870}
4871
4872// FastEmit functions for PPCISD::SRA.
4873
4874Register fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4875 if (RetVT.SimpleTy != MVT::i32)
4876 return Register();
4877 return fastEmitInst_rr(MachineInstOpcode: PPC::SRAW, RC: &PPC::GPRCRegClass, Op0, Op1);
4878}
4879
4880Register fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4881 if (RetVT.SimpleTy != MVT::v16i8)
4882 return Register();
4883 if ((Subtarget->hasAltivec())) {
4884 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAB, RC: &PPC::VRRCRegClass, Op0, Op1);
4885 }
4886 return Register();
4887}
4888
4889Register fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4890 if (RetVT.SimpleTy != MVT::v8i16)
4891 return Register();
4892 if ((Subtarget->hasAltivec())) {
4893 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAH, RC: &PPC::VRRCRegClass, Op0, Op1);
4894 }
4895 return Register();
4896}
4897
4898Register fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4899 if (RetVT.SimpleTy != MVT::v4i32)
4900 return Register();
4901 if ((Subtarget->hasAltivec())) {
4902 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAW, RC: &PPC::VRRCRegClass, Op0, Op1);
4903 }
4904 return Register();
4905}
4906
4907Register fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4908 if (RetVT.SimpleTy != MVT::v2i64)
4909 return Register();
4910 if ((Subtarget->hasP8Altivec())) {
4911 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRAD, RC: &PPC::VRRCRegClass, Op0, Op1);
4912 }
4913 return Register();
4914}
4915
4916Register fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4917 switch (VT.SimpleTy) {
4918 case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
4919 case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
4920 case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
4921 case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
4922 case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
4923 default: return Register();
4924 }
4925}
4926
4927// FastEmit functions for PPCISD::SRL.
4928
4929Register fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
4930 if (RetVT.SimpleTy != MVT::i32)
4931 return Register();
4932 return fastEmitInst_rr(MachineInstOpcode: PPC::SRW, RC: &PPC::GPRCRegClass, Op0, Op1);
4933}
4934
4935Register fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
4936 if (RetVT.SimpleTy != MVT::v16i8)
4937 return Register();
4938 if ((Subtarget->hasAltivec())) {
4939 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRB, RC: &PPC::VRRCRegClass, Op0, Op1);
4940 }
4941 return Register();
4942}
4943
4944Register fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
4945 if (RetVT.SimpleTy != MVT::v8i16)
4946 return Register();
4947 if ((Subtarget->hasAltivec())) {
4948 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRH, RC: &PPC::VRRCRegClass, Op0, Op1);
4949 }
4950 return Register();
4951}
4952
4953Register fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
4954 if (RetVT.SimpleTy != MVT::v4i32)
4955 return Register();
4956 if ((Subtarget->hasAltivec())) {
4957 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRW, RC: &PPC::VRRCRegClass, Op0, Op1);
4958 }
4959 return Register();
4960}
4961
4962Register fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
4963 if (RetVT.SimpleTy != MVT::v2i64)
4964 return Register();
4965 if ((Subtarget->hasP8Altivec())) {
4966 return fastEmitInst_rr(MachineInstOpcode: PPC::VSRD, RC: &PPC::VRRCRegClass, Op0, Op1);
4967 }
4968 return Register();
4969}
4970
4971Register fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4972 switch (VT.SimpleTy) {
4973 case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
4974 case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
4975 case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
4976 case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
4977 case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
4978 default: return Register();
4979 }
4980}
4981
4982// FastEmit functions for PPCISD::STRICT_FADDRTZ.
4983
4984Register fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
4985 if (RetVT.SimpleTy != MVT::f64)
4986 return Register();
4987 if ((Subtarget->hasFPU())) {
4988 return fastEmitInst_rr(MachineInstOpcode: PPC::FADDrtz, RC: &PPC::F8RCRegClass, Op0, Op1);
4989 }
4990 return Register();
4991}
4992
4993Register fastEmit_PPCISD_STRICT_FADDRTZ_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
4994 switch (VT.SimpleTy) {
4995 case MVT::f64: return fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1);
4996 default: return Register();
4997 }
4998}
4999
5000// FastEmit functions for PPCISD::TLSGD_AIX.
5001
5002Register fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
5003 if (RetVT.SimpleTy != MVT::i32)
5004 return Register();
5005 return fastEmitInst_rr(MachineInstOpcode: PPC::TLSGDAIX, RC: &PPC::GPRCRegClass, Op0, Op1);
5006}
5007
5008Register fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
5009 if (RetVT.SimpleTy != MVT::i64)
5010 return Register();
5011 return fastEmitInst_rr(MachineInstOpcode: PPC::TLSGDAIX8, RC: &PPC::G8RCRegClass, Op0, Op1);
5012}
5013
5014Register fastEmit_PPCISD_TLSGD_AIX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5015 switch (VT.SimpleTy) {
5016 case MVT::i32: return fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(RetVT, Op0, Op1);
5017 case MVT::i64: return fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(RetVT, Op0, Op1);
5018 default: return Register();
5019 }
5020}
5021
5022// FastEmit functions for PPCISD::XSMAXC.
5023
5024Register fastEmit_PPCISD_XSMAXC_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
5025 if (RetVT.SimpleTy != MVT::f64)
5026 return Register();
5027 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
5028 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXCDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
5029 }
5030 return Register();
5031}
5032
5033Register fastEmit_PPCISD_XSMAXC_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
5034 if (RetVT.SimpleTy != MVT::f128)
5035 return Register();
5036 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) {
5037 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMAXCQP, RC: &PPC::VRRCRegClass, Op0, Op1);
5038 }
5039 return Register();
5040}
5041
5042Register fastEmit_PPCISD_XSMAXC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5043 switch (VT.SimpleTy) {
5044 case MVT::f64: return fastEmit_PPCISD_XSMAXC_MVT_f64_rr(RetVT, Op0, Op1);
5045 case MVT::f128: return fastEmit_PPCISD_XSMAXC_MVT_f128_rr(RetVT, Op0, Op1);
5046 default: return Register();
5047 }
5048}
5049
5050// FastEmit functions for PPCISD::XSMINC.
5051
5052Register fastEmit_PPCISD_XSMINC_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
5053 if (RetVT.SimpleTy != MVT::f64)
5054 return Register();
5055 if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) {
5056 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINCDP, RC: &PPC::VSFRCRegClass, Op0, Op1);
5057 }
5058 return Register();
5059}
5060
5061Register fastEmit_PPCISD_XSMINC_MVT_f128_rr(MVT RetVT, Register Op0, Register Op1) {
5062 if (RetVT.SimpleTy != MVT::f128)
5063 return Register();
5064 if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) {
5065 return fastEmitInst_rr(MachineInstOpcode: PPC::XSMINCQP, RC: &PPC::VRRCRegClass, Op0, Op1);
5066 }
5067 return Register();
5068}
5069
5070Register fastEmit_PPCISD_XSMINC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
5071 switch (VT.SimpleTy) {
5072 case MVT::f64: return fastEmit_PPCISD_XSMINC_MVT_f64_rr(RetVT, Op0, Op1);
5073 case MVT::f128: return fastEmit_PPCISD_XSMINC_MVT_f128_rr(RetVT, Op0, Op1);
5074 default: return Register();
5075 }
5076}
5077
5078// Top-level FastEmit function.
5079
5080Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
5081 switch (Opcode) {
5082 case ISD::ABDU: return fastEmit_ISD_ABDU_rr(VT, RetVT, Op0, Op1);
5083 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
5084 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
5085 case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op1);
5086 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
5087 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
5088 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
5089 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
5090 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
5091 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
5092 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
5093 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
5094 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
5095 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
5096 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
5097 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
5098 case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1);
5099 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1);
5100 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
5101 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
5102 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
5103 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
5104 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
5105 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
5106 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
5107 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1);
5108 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
5109 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
5110 case ISD::STRICT_FMAXNUM: return fastEmit_ISD_STRICT_FMAXNUM_rr(VT, RetVT, Op0, Op1);
5111 case ISD::STRICT_FMINNUM: return fastEmit_ISD_STRICT_FMINNUM_rr(VT, RetVT, Op0, Op1);
5112 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
5113 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
5114 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
5115 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1);
5116 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
5117 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
5118 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
5119 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
5120 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1);
5121 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
5122 case PPCISD::ADD_TLS: return fastEmit_PPCISD_ADD_TLS_rr(VT, RetVT, Op0, Op1);
5123 case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op1);
5124 case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op1);
5125 case PPCISD::GET_TLS_ADDR: return fastEmit_PPCISD_GET_TLS_ADDR_rr(VT, RetVT, Op0, Op1);
5126 case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op1);
5127 case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op1);
5128 case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op1);
5129 case PPCISD::STRICT_FADDRTZ: return fastEmit_PPCISD_STRICT_FADDRTZ_rr(VT, RetVT, Op0, Op1);
5130 case PPCISD::TLSGD_AIX: return fastEmit_PPCISD_TLSGD_AIX_rr(VT, RetVT, Op0, Op1);
5131 case PPCISD::XSMAXC: return fastEmit_PPCISD_XSMAXC_rr(VT, RetVT, Op0, Op1);
5132 case PPCISD::XSMINC: return fastEmit_PPCISD_XSMINC_rr(VT, RetVT, Op0, Op1);
5133 default: return Register();
5134 }
5135}
5136
5137// FastEmit functions for ISD::SRA.
5138
5139Register fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5140 if (RetVT.SimpleTy != MVT::i32)
5141 return Register();
5142 return fastEmitInst_ri(MachineInstOpcode: PPC::SRAWI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5143}
5144
5145Register fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5146 if (RetVT.SimpleTy != MVT::i64)
5147 return Register();
5148 return fastEmitInst_ri(MachineInstOpcode: PPC::SRADI, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5149}
5150
5151Register fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5152 switch (VT.SimpleTy) {
5153 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, imm1);
5154 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, imm1);
5155 default: return Register();
5156 }
5157}
5158
5159// FastEmit functions for PPCISD::EXTSWSLI.
5160
5161Register fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5162 if (RetVT.SimpleTy != MVT::i64)
5163 return Register();
5164 if ((Subtarget->isISA3_0())) {
5165 return fastEmitInst_ri(MachineInstOpcode: PPC::EXTSWSLI_32_64, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5166 }
5167 return Register();
5168}
5169
5170Register fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5171 switch (VT.SimpleTy) {
5172 case MVT::i32: return fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(RetVT, Op0, imm1);
5173 default: return Register();
5174 }
5175}
5176
5177// FastEmit functions for PPCISD::TC_RETURN.
5178
5179Register fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5180 if (RetVT.SimpleTy != MVT::isVoid)
5181 return Register();
5182 return fastEmitInst_ri(MachineInstOpcode: PPC::TCRETURNri, RC: &PPC::CTRRCRegClass, Op0, Imm: imm1);
5183}
5184
5185Register fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
5186 if (RetVT.SimpleTy != MVT::isVoid)
5187 return Register();
5188 return fastEmitInst_ri(MachineInstOpcode: PPC::TCRETURNri8, RC: &PPC::CTRRC8RegClass, Op0, Imm: imm1);
5189}
5190
5191Register fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5192 switch (VT.SimpleTy) {
5193 case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, imm1);
5194 case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, imm1);
5195 default: return Register();
5196 }
5197}
5198
5199// Top-level FastEmit function.
5200
5201Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
5202 if (VT == MVT::i32 && Predicate_imm32SExt16(Imm: imm1))
5203 if (Register Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, imm1))
5204 return Reg;
5205
5206 if (VT == MVT::i64 && Predicate_imm64SExt16(Imm: imm1))
5207 if (Register Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, imm1))
5208 return Reg;
5209
5210 switch (Opcode) {
5211 case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, imm1);
5212 case PPCISD::EXTSWSLI: return fastEmit_PPCISD_EXTSWSLI_ri(VT, RetVT, Op0, imm1);
5213 case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, imm1);
5214 default: return Register();
5215 }
5216}
5217
5218// FastEmit functions for ISD::ADD.
5219
5220Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5221 if (RetVT.SimpleTy != MVT::i32)
5222 return Register();
5223 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5224}
5225
5226Register fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5227 switch (VT.SimpleTy) {
5228 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5229 default: return Register();
5230 }
5231}
5232
5233// FastEmit functions for ISD::MUL.
5234
5235Register fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5236 if (RetVT.SimpleTy != MVT::i32)
5237 return Register();
5238 return fastEmitInst_ri(MachineInstOpcode: PPC::MULLI, RC: &PPC::GPRCRegClass, Op0, Imm: imm1);
5239}
5240
5241Register fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5242 switch (VT.SimpleTy) {
5243 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5244 default: return Register();
5245 }
5246}
5247
5248// FastEmit functions for PPCISD::XXSPLT.
5249
5250Register fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5251 if (RetVT.SimpleTy != MVT::v4i32)
5252 return Register();
5253 if ((Subtarget->hasVSX())) {
5254 return fastEmitInst_ri(MachineInstOpcode: PPC::XXSPLTW, RC: &PPC::VSRCRegClass, Op0, Imm: imm1);
5255 }
5256 return Register();
5257}
5258
5259Register fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5260 switch (VT.SimpleTy) {
5261 case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1);
5262 default: return Register();
5263 }
5264}
5265
5266// Top-level FastEmit function.
5267
5268Register fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
5269 switch (Opcode) {
5270 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5271 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5272 case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1);
5273 default: return Register();
5274 }
5275}
5276
5277// FastEmit functions for ISD::ADD.
5278
5279Register fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5280 if (RetVT.SimpleTy != MVT::i64)
5281 return Register();
5282 return fastEmitInst_ri(MachineInstOpcode: PPC::ADDI8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5283}
5284
5285Register fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5286 switch (VT.SimpleTy) {
5287 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5288 default: return Register();
5289 }
5290}
5291
5292// FastEmit functions for ISD::MUL.
5293
5294Register fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, Register Op0, uint64_t imm1) {
5295 if (RetVT.SimpleTy != MVT::i64)
5296 return Register();
5297 return fastEmitInst_ri(MachineInstOpcode: PPC::MULLI8, RC: &PPC::G8RCRegClass, Op0, Imm: imm1);
5298}
5299
5300Register fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
5301 switch (VT.SimpleTy) {
5302 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1);
5303 default: return Register();
5304 }
5305}
5306
5307// Top-level FastEmit function.
5308
5309Register fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
5310 switch (Opcode) {
5311 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5312 case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1);
5313 default: return Register();
5314 }
5315}
5316
5317