1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t RISCVMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(0),
443 UINT64_C(0),
444 UINT64_C(0),
445 UINT64_C(0),
446 UINT64_C(0),
447 UINT64_C(0),
448 UINT64_C(0),
449 UINT64_C(0),
450 UINT64_C(0),
451 UINT64_C(0),
452 UINT64_C(0),
453 UINT64_C(0),
454 UINT64_C(0),
455 UINT64_C(0),
456 UINT64_C(0),
457 UINT64_C(0),
458 UINT64_C(0),
459 UINT64_C(0),
460 UINT64_C(0),
461 UINT64_C(0),
462 UINT64_C(0),
463 UINT64_C(0),
464 UINT64_C(0),
465 UINT64_C(0),
466 UINT64_C(0),
467 UINT64_C(0),
468 UINT64_C(0),
469 UINT64_C(0),
470 UINT64_C(0),
471 UINT64_C(0),
472 UINT64_C(0),
473 UINT64_C(0),
474 UINT64_C(0),
475 UINT64_C(0),
476 UINT64_C(0),
477 UINT64_C(0),
478 UINT64_C(0),
479 UINT64_C(0),
480 UINT64_C(0),
481 UINT64_C(0),
482 UINT64_C(0),
483 UINT64_C(0),
484 UINT64_C(0),
485 UINT64_C(0),
486 UINT64_C(0),
487 UINT64_C(0),
488 UINT64_C(0),
489 UINT64_C(0),
490 UINT64_C(0),
491 UINT64_C(0),
492 UINT64_C(0),
493 UINT64_C(0),
494 UINT64_C(0),
495 UINT64_C(0),
496 UINT64_C(0),
497 UINT64_C(0),
498 UINT64_C(0),
499 UINT64_C(0),
500 UINT64_C(0),
501 UINT64_C(0),
502 UINT64_C(0),
503 UINT64_C(0),
504 UINT64_C(0),
505 UINT64_C(0),
506 UINT64_C(0),
507 UINT64_C(0),
508 UINT64_C(0),
509 UINT64_C(0),
510 UINT64_C(0),
511 UINT64_C(0),
512 UINT64_C(0),
513 UINT64_C(0),
514 UINT64_C(0),
515 UINT64_C(0),
516 UINT64_C(0),
517 UINT64_C(0),
518 UINT64_C(0),
519 UINT64_C(0),
520 UINT64_C(0),
521 UINT64_C(0),
522 UINT64_C(0),
523 UINT64_C(0),
524 UINT64_C(0),
525 UINT64_C(0),
526 UINT64_C(0),
527 UINT64_C(0),
528 UINT64_C(0),
529 UINT64_C(0),
530 UINT64_C(0),
531 UINT64_C(0),
532 UINT64_C(0),
533 UINT64_C(0),
534 UINT64_C(0),
535 UINT64_C(0),
536 UINT64_C(0),
537 UINT64_C(0),
538 UINT64_C(0),
539 UINT64_C(0),
540 UINT64_C(0),
541 UINT64_C(0),
542 UINT64_C(0),
543 UINT64_C(0),
544 UINT64_C(0),
545 UINT64_C(0),
546 UINT64_C(0),
547 UINT64_C(0),
548 UINT64_C(0),
549 UINT64_C(0),
550 UINT64_C(0),
551 UINT64_C(0),
552 UINT64_C(0),
553 UINT64_C(0),
554 UINT64_C(0),
555 UINT64_C(0),
556 UINT64_C(0),
557 UINT64_C(0),
558 UINT64_C(0),
559 UINT64_C(0),
560 UINT64_C(0),
561 UINT64_C(0),
562 UINT64_C(0),
563 UINT64_C(0),
564 UINT64_C(0),
565 UINT64_C(0),
566 UINT64_C(0),
567 UINT64_C(0),
568 UINT64_C(0),
569 UINT64_C(0),
570 UINT64_C(0),
571 UINT64_C(0),
572 UINT64_C(0),
573 UINT64_C(0),
574 UINT64_C(0),
575 UINT64_C(0),
576 UINT64_C(0),
577 UINT64_C(0),
578 UINT64_C(0),
579 UINT64_C(0),
580 UINT64_C(0),
581 UINT64_C(0),
582 UINT64_C(0),
583 UINT64_C(0),
584 UINT64_C(0),
585 UINT64_C(0),
586 UINT64_C(0),
587 UINT64_C(0),
588 UINT64_C(0),
589 UINT64_C(0),
590 UINT64_C(0),
591 UINT64_C(0),
592 UINT64_C(0),
593 UINT64_C(0),
594 UINT64_C(0),
595 UINT64_C(0),
596 UINT64_C(0),
597 UINT64_C(0),
598 UINT64_C(0),
599 UINT64_C(0),
600 UINT64_C(0),
601 UINT64_C(0),
602 UINT64_C(0),
603 UINT64_C(0),
604 UINT64_C(0),
605 UINT64_C(0),
606 UINT64_C(0),
607 UINT64_C(0),
608 UINT64_C(0),
609 UINT64_C(0),
610 UINT64_C(0),
611 UINT64_C(0),
612 UINT64_C(0),
613 UINT64_C(0),
614 UINT64_C(0),
615 UINT64_C(0),
616 UINT64_C(0),
617 UINT64_C(0),
618 UINT64_C(0),
619 UINT64_C(0),
620 UINT64_C(0),
621 UINT64_C(0),
622 UINT64_C(0),
623 UINT64_C(0),
624 UINT64_C(0),
625 UINT64_C(0),
626 UINT64_C(0),
627 UINT64_C(0),
628 UINT64_C(0),
629 UINT64_C(0),
630 UINT64_C(0),
631 UINT64_C(0),
632 UINT64_C(0),
633 UINT64_C(0),
634 UINT64_C(0),
635 UINT64_C(0),
636 UINT64_C(0),
637 UINT64_C(0),
638 UINT64_C(0),
639 UINT64_C(0),
640 UINT64_C(0),
641 UINT64_C(0),
642 UINT64_C(0),
643 UINT64_C(0),
644 UINT64_C(0),
645 UINT64_C(0),
646 UINT64_C(0),
647 UINT64_C(0),
648 UINT64_C(0),
649 UINT64_C(0),
650 UINT64_C(0),
651 UINT64_C(0),
652 UINT64_C(0),
653 UINT64_C(0),
654 UINT64_C(0),
655 UINT64_C(0),
656 UINT64_C(0),
657 UINT64_C(0),
658 UINT64_C(0),
659 UINT64_C(0),
660 UINT64_C(0),
661 UINT64_C(0),
662 UINT64_C(0),
663 UINT64_C(0),
664 UINT64_C(0),
665 UINT64_C(0),
666 UINT64_C(0),
667 UINT64_C(0),
668 UINT64_C(0),
669 UINT64_C(0),
670 UINT64_C(0),
671 UINT64_C(0),
672 UINT64_C(0),
673 UINT64_C(0),
674 UINT64_C(0),
675 UINT64_C(0),
676 UINT64_C(0),
677 UINT64_C(0),
678 UINT64_C(0),
679 UINT64_C(0),
680 UINT64_C(0),
681 UINT64_C(0),
682 UINT64_C(0),
683 UINT64_C(0),
684 UINT64_C(0),
685 UINT64_C(0),
686 UINT64_C(0),
687 UINT64_C(0),
688 UINT64_C(0),
689 UINT64_C(0),
690 UINT64_C(0),
691 UINT64_C(0),
692 UINT64_C(0),
693 UINT64_C(0),
694 UINT64_C(0),
695 UINT64_C(0),
696 UINT64_C(0),
697 UINT64_C(0),
698 UINT64_C(0),
699 UINT64_C(0),
700 UINT64_C(0),
701 UINT64_C(0),
702 UINT64_C(0),
703 UINT64_C(0),
704 UINT64_C(0),
705 UINT64_C(0),
706 UINT64_C(0),
707 UINT64_C(0),
708 UINT64_C(0),
709 UINT64_C(0),
710 UINT64_C(0),
711 UINT64_C(0),
712 UINT64_C(0),
713 UINT64_C(0),
714 UINT64_C(0),
715 UINT64_C(0),
716 UINT64_C(0),
717 UINT64_C(0),
718 UINT64_C(0),
719 UINT64_C(0),
720 UINT64_C(0),
721 UINT64_C(0),
722 UINT64_C(0),
723 UINT64_C(0),
724 UINT64_C(0),
725 UINT64_C(0),
726 UINT64_C(0),
727 UINT64_C(0),
728 UINT64_C(0),
729 UINT64_C(0),
730 UINT64_C(0),
731 UINT64_C(0),
732 UINT64_C(0),
733 UINT64_C(0),
734 UINT64_C(0),
735 UINT64_C(0),
736 UINT64_C(0),
737 UINT64_C(0),
738 UINT64_C(0),
739 UINT64_C(0),
740 UINT64_C(0),
741 UINT64_C(0),
742 UINT64_C(0),
743 UINT64_C(0),
744 UINT64_C(0),
745 UINT64_C(0),
746 UINT64_C(0),
747 UINT64_C(0),
748 UINT64_C(0),
749 UINT64_C(0),
750 UINT64_C(0),
751 UINT64_C(0),
752 UINT64_C(0),
753 UINT64_C(0),
754 UINT64_C(0),
755 UINT64_C(0),
756 UINT64_C(0),
757 UINT64_C(0),
758 UINT64_C(0),
759 UINT64_C(0),
760 UINT64_C(0),
761 UINT64_C(0),
762 UINT64_C(0),
763 UINT64_C(0),
764 UINT64_C(0),
765 UINT64_C(0),
766 UINT64_C(0),
767 UINT64_C(0),
768 UINT64_C(0),
769 UINT64_C(0),
770 UINT64_C(0),
771 UINT64_C(0),
772 UINT64_C(0),
773 UINT64_C(0),
774 UINT64_C(0),
775 UINT64_C(0),
776 UINT64_C(0),
777 UINT64_C(0),
778 UINT64_C(0),
779 UINT64_C(0),
780 UINT64_C(0),
781 UINT64_C(0),
782 UINT64_C(0),
783 UINT64_C(0),
784 UINT64_C(0),
785 UINT64_C(0),
786 UINT64_C(0),
787 UINT64_C(0),
788 UINT64_C(0),
789 UINT64_C(0),
790 UINT64_C(0),
791 UINT64_C(0),
792 UINT64_C(0),
793 UINT64_C(0),
794 UINT64_C(0),
795 UINT64_C(0),
796 UINT64_C(0),
797 UINT64_C(0),
798 UINT64_C(0),
799 UINT64_C(0),
800 UINT64_C(0),
801 UINT64_C(0),
802 UINT64_C(0),
803 UINT64_C(0),
804 UINT64_C(0),
805 UINT64_C(0),
806 UINT64_C(0),
807 UINT64_C(0),
808 UINT64_C(0),
809 UINT64_C(0),
810 UINT64_C(0),
811 UINT64_C(0),
812 UINT64_C(0),
813 UINT64_C(0),
814 UINT64_C(0),
815 UINT64_C(0),
816 UINT64_C(0),
817 UINT64_C(0),
818 UINT64_C(0),
819 UINT64_C(0),
820 UINT64_C(0),
821 UINT64_C(0),
822 UINT64_C(0),
823 UINT64_C(0),
824 UINT64_C(0),
825 UINT64_C(0),
826 UINT64_C(0),
827 UINT64_C(0),
828 UINT64_C(0),
829 UINT64_C(0),
830 UINT64_C(0),
831 UINT64_C(0),
832 UINT64_C(0),
833 UINT64_C(0),
834 UINT64_C(0),
835 UINT64_C(0),
836 UINT64_C(0),
837 UINT64_C(0),
838 UINT64_C(0),
839 UINT64_C(0),
840 UINT64_C(0),
841 UINT64_C(0),
842 UINT64_C(0),
843 UINT64_C(0),
844 UINT64_C(0),
845 UINT64_C(0),
846 UINT64_C(0),
847 UINT64_C(0),
848 UINT64_C(0),
849 UINT64_C(0),
850 UINT64_C(0),
851 UINT64_C(0),
852 UINT64_C(0),
853 UINT64_C(0),
854 UINT64_C(0),
855 UINT64_C(0),
856 UINT64_C(0),
857 UINT64_C(0),
858 UINT64_C(0),
859 UINT64_C(0),
860 UINT64_C(0),
861 UINT64_C(0),
862 UINT64_C(0),
863 UINT64_C(0),
864 UINT64_C(0),
865 UINT64_C(0),
866 UINT64_C(0),
867 UINT64_C(0),
868 UINT64_C(0),
869 UINT64_C(0),
870 UINT64_C(0),
871 UINT64_C(0),
872 UINT64_C(0),
873 UINT64_C(0),
874 UINT64_C(0),
875 UINT64_C(0),
876 UINT64_C(0),
877 UINT64_C(0),
878 UINT64_C(0),
879 UINT64_C(0),
880 UINT64_C(0),
881 UINT64_C(0),
882 UINT64_C(0),
883 UINT64_C(0),
884 UINT64_C(0),
885 UINT64_C(0),
886 UINT64_C(0),
887 UINT64_C(0),
888 UINT64_C(0),
889 UINT64_C(0),
890 UINT64_C(0),
891 UINT64_C(0),
892 UINT64_C(0),
893 UINT64_C(0),
894 UINT64_C(0),
895 UINT64_C(0),
896 UINT64_C(0),
897 UINT64_C(0),
898 UINT64_C(0),
899 UINT64_C(0),
900 UINT64_C(0),
901 UINT64_C(0),
902 UINT64_C(0),
903 UINT64_C(0),
904 UINT64_C(0),
905 UINT64_C(0),
906 UINT64_C(0),
907 UINT64_C(0),
908 UINT64_C(0),
909 UINT64_C(0),
910 UINT64_C(0),
911 UINT64_C(0),
912 UINT64_C(0),
913 UINT64_C(0),
914 UINT64_C(0),
915 UINT64_C(0),
916 UINT64_C(0),
917 UINT64_C(0),
918 UINT64_C(0),
919 UINT64_C(0),
920 UINT64_C(0),
921 UINT64_C(0),
922 UINT64_C(0),
923 UINT64_C(0),
924 UINT64_C(0),
925 UINT64_C(0),
926 UINT64_C(0),
927 UINT64_C(0),
928 UINT64_C(0),
929 UINT64_C(0),
930 UINT64_C(0),
931 UINT64_C(0),
932 UINT64_C(0),
933 UINT64_C(0),
934 UINT64_C(0),
935 UINT64_C(0),
936 UINT64_C(0),
937 UINT64_C(0),
938 UINT64_C(0),
939 UINT64_C(0),
940 UINT64_C(0),
941 UINT64_C(0),
942 UINT64_C(0),
943 UINT64_C(0),
944 UINT64_C(0),
945 UINT64_C(0),
946 UINT64_C(0),
947 UINT64_C(0),
948 UINT64_C(0),
949 UINT64_C(0),
950 UINT64_C(0),
951 UINT64_C(0),
952 UINT64_C(0),
953 UINT64_C(0),
954 UINT64_C(0),
955 UINT64_C(0),
956 UINT64_C(0),
957 UINT64_C(0),
958 UINT64_C(0),
959 UINT64_C(0),
960 UINT64_C(0),
961 UINT64_C(0),
962 UINT64_C(0),
963 UINT64_C(0),
964 UINT64_C(0),
965 UINT64_C(0),
966 UINT64_C(0),
967 UINT64_C(0),
968 UINT64_C(0),
969 UINT64_C(0),
970 UINT64_C(0),
971 UINT64_C(0),
972 UINT64_C(0),
973 UINT64_C(0),
974 UINT64_C(0),
975 UINT64_C(0),
976 UINT64_C(0),
977 UINT64_C(0),
978 UINT64_C(0),
979 UINT64_C(0),
980 UINT64_C(0),
981 UINT64_C(0),
982 UINT64_C(0),
983 UINT64_C(0),
984 UINT64_C(0),
985 UINT64_C(0),
986 UINT64_C(0),
987 UINT64_C(0),
988 UINT64_C(0),
989 UINT64_C(0),
990 UINT64_C(0),
991 UINT64_C(0),
992 UINT64_C(0),
993 UINT64_C(0),
994 UINT64_C(0),
995 UINT64_C(0),
996 UINT64_C(0),
997 UINT64_C(0),
998 UINT64_C(0),
999 UINT64_C(0),
1000 UINT64_C(0),
1001 UINT64_C(0),
1002 UINT64_C(0),
1003 UINT64_C(0),
1004 UINT64_C(0),
1005 UINT64_C(0),
1006 UINT64_C(0),
1007 UINT64_C(0),
1008 UINT64_C(0),
1009 UINT64_C(0),
1010 UINT64_C(0),
1011 UINT64_C(0),
1012 UINT64_C(0),
1013 UINT64_C(0),
1014 UINT64_C(0),
1015 UINT64_C(0),
1016 UINT64_C(0),
1017 UINT64_C(0),
1018 UINT64_C(0),
1019 UINT64_C(0),
1020 UINT64_C(0),
1021 UINT64_C(0),
1022 UINT64_C(0),
1023 UINT64_C(0),
1024 UINT64_C(0),
1025 UINT64_C(0),
1026 UINT64_C(0),
1027 UINT64_C(0),
1028 UINT64_C(0),
1029 UINT64_C(0),
1030 UINT64_C(0),
1031 UINT64_C(0),
1032 UINT64_C(0),
1033 UINT64_C(0),
1034 UINT64_C(0),
1035 UINT64_C(0),
1036 UINT64_C(0),
1037 UINT64_C(0),
1038 UINT64_C(0),
1039 UINT64_C(0),
1040 UINT64_C(0),
1041 UINT64_C(0),
1042 UINT64_C(0),
1043 UINT64_C(0),
1044 UINT64_C(0),
1045 UINT64_C(0),
1046 UINT64_C(0),
1047 UINT64_C(0),
1048 UINT64_C(0),
1049 UINT64_C(0),
1050 UINT64_C(0),
1051 UINT64_C(0),
1052 UINT64_C(0),
1053 UINT64_C(0),
1054 UINT64_C(0),
1055 UINT64_C(0),
1056 UINT64_C(0),
1057 UINT64_C(0),
1058 UINT64_C(0),
1059 UINT64_C(0),
1060 UINT64_C(0),
1061 UINT64_C(0),
1062 UINT64_C(0),
1063 UINT64_C(0),
1064 UINT64_C(0),
1065 UINT64_C(0),
1066 UINT64_C(0),
1067 UINT64_C(0),
1068 UINT64_C(0),
1069 UINT64_C(0),
1070 UINT64_C(0),
1071 UINT64_C(0),
1072 UINT64_C(0),
1073 UINT64_C(0),
1074 UINT64_C(0),
1075 UINT64_C(0),
1076 UINT64_C(0),
1077 UINT64_C(0),
1078 UINT64_C(0),
1079 UINT64_C(0),
1080 UINT64_C(0),
1081 UINT64_C(0),
1082 UINT64_C(0),
1083 UINT64_C(0),
1084 UINT64_C(0),
1085 UINT64_C(0),
1086 UINT64_C(0),
1087 UINT64_C(0),
1088 UINT64_C(0),
1089 UINT64_C(0),
1090 UINT64_C(0),
1091 UINT64_C(0),
1092 UINT64_C(0),
1093 UINT64_C(0),
1094 UINT64_C(0),
1095 UINT64_C(0),
1096 UINT64_C(0),
1097 UINT64_C(0),
1098 UINT64_C(0),
1099 UINT64_C(0),
1100 UINT64_C(0),
1101 UINT64_C(0),
1102 UINT64_C(0),
1103 UINT64_C(0),
1104 UINT64_C(0),
1105 UINT64_C(0),
1106 UINT64_C(0),
1107 UINT64_C(0),
1108 UINT64_C(0),
1109 UINT64_C(0),
1110 UINT64_C(0),
1111 UINT64_C(0),
1112 UINT64_C(0),
1113 UINT64_C(0),
1114 UINT64_C(0),
1115 UINT64_C(0),
1116 UINT64_C(0),
1117 UINT64_C(0),
1118 UINT64_C(0),
1119 UINT64_C(0),
1120 UINT64_C(0),
1121 UINT64_C(0),
1122 UINT64_C(0),
1123 UINT64_C(0),
1124 UINT64_C(0),
1125 UINT64_C(0),
1126 UINT64_C(0),
1127 UINT64_C(0),
1128 UINT64_C(0),
1129 UINT64_C(0),
1130 UINT64_C(0),
1131 UINT64_C(0),
1132 UINT64_C(0),
1133 UINT64_C(0),
1134 UINT64_C(0),
1135 UINT64_C(0),
1136 UINT64_C(0),
1137 UINT64_C(0),
1138 UINT64_C(0),
1139 UINT64_C(0),
1140 UINT64_C(0),
1141 UINT64_C(0),
1142 UINT64_C(0),
1143 UINT64_C(0),
1144 UINT64_C(0),
1145 UINT64_C(0),
1146 UINT64_C(0),
1147 UINT64_C(0),
1148 UINT64_C(0),
1149 UINT64_C(0),
1150 UINT64_C(0),
1151 UINT64_C(0),
1152 UINT64_C(0),
1153 UINT64_C(0),
1154 UINT64_C(0),
1155 UINT64_C(0),
1156 UINT64_C(0),
1157 UINT64_C(0),
1158 UINT64_C(0),
1159 UINT64_C(0),
1160 UINT64_C(0),
1161 UINT64_C(0),
1162 UINT64_C(0),
1163 UINT64_C(0),
1164 UINT64_C(0),
1165 UINT64_C(0),
1166 UINT64_C(0),
1167 UINT64_C(0),
1168 UINT64_C(0),
1169 UINT64_C(0),
1170 UINT64_C(0),
1171 UINT64_C(0),
1172 UINT64_C(0),
1173 UINT64_C(0),
1174 UINT64_C(0),
1175 UINT64_C(0),
1176 UINT64_C(0),
1177 UINT64_C(0),
1178 UINT64_C(0),
1179 UINT64_C(0),
1180 UINT64_C(0),
1181 UINT64_C(0),
1182 UINT64_C(0),
1183 UINT64_C(0),
1184 UINT64_C(0),
1185 UINT64_C(0),
1186 UINT64_C(0),
1187 UINT64_C(0),
1188 UINT64_C(0),
1189 UINT64_C(0),
1190 UINT64_C(0),
1191 UINT64_C(0),
1192 UINT64_C(0),
1193 UINT64_C(0),
1194 UINT64_C(0),
1195 UINT64_C(0),
1196 UINT64_C(0),
1197 UINT64_C(0),
1198 UINT64_C(0),
1199 UINT64_C(0),
1200 UINT64_C(0),
1201 UINT64_C(0),
1202 UINT64_C(0),
1203 UINT64_C(0),
1204 UINT64_C(0),
1205 UINT64_C(0),
1206 UINT64_C(0),
1207 UINT64_C(0),
1208 UINT64_C(0),
1209 UINT64_C(0),
1210 UINT64_C(0),
1211 UINT64_C(0),
1212 UINT64_C(0),
1213 UINT64_C(0),
1214 UINT64_C(0),
1215 UINT64_C(0),
1216 UINT64_C(0),
1217 UINT64_C(0),
1218 UINT64_C(0),
1219 UINT64_C(0),
1220 UINT64_C(0),
1221 UINT64_C(0),
1222 UINT64_C(0),
1223 UINT64_C(0),
1224 UINT64_C(0),
1225 UINT64_C(0),
1226 UINT64_C(0),
1227 UINT64_C(0),
1228 UINT64_C(0),
1229 UINT64_C(0),
1230 UINT64_C(0),
1231 UINT64_C(0),
1232 UINT64_C(0),
1233 UINT64_C(0),
1234 UINT64_C(0),
1235 UINT64_C(0),
1236 UINT64_C(0),
1237 UINT64_C(0),
1238 UINT64_C(0),
1239 UINT64_C(0),
1240 UINT64_C(0),
1241 UINT64_C(0),
1242 UINT64_C(0),
1243 UINT64_C(0),
1244 UINT64_C(0),
1245 UINT64_C(0),
1246 UINT64_C(0),
1247 UINT64_C(0),
1248 UINT64_C(0),
1249 UINT64_C(0),
1250 UINT64_C(0),
1251 UINT64_C(0),
1252 UINT64_C(0),
1253 UINT64_C(0),
1254 UINT64_C(0),
1255 UINT64_C(0),
1256 UINT64_C(0),
1257 UINT64_C(0),
1258 UINT64_C(0),
1259 UINT64_C(0),
1260 UINT64_C(0),
1261 UINT64_C(0),
1262 UINT64_C(0),
1263 UINT64_C(0),
1264 UINT64_C(0),
1265 UINT64_C(0),
1266 UINT64_C(0),
1267 UINT64_C(0),
1268 UINT64_C(0),
1269 UINT64_C(0),
1270 UINT64_C(0),
1271 UINT64_C(0),
1272 UINT64_C(0),
1273 UINT64_C(0),
1274 UINT64_C(0),
1275 UINT64_C(0),
1276 UINT64_C(0),
1277 UINT64_C(0),
1278 UINT64_C(0),
1279 UINT64_C(0),
1280 UINT64_C(0),
1281 UINT64_C(0),
1282 UINT64_C(0),
1283 UINT64_C(0),
1284 UINT64_C(0),
1285 UINT64_C(0),
1286 UINT64_C(0),
1287 UINT64_C(0),
1288 UINT64_C(0),
1289 UINT64_C(0),
1290 UINT64_C(0),
1291 UINT64_C(0),
1292 UINT64_C(0),
1293 UINT64_C(0),
1294 UINT64_C(0),
1295 UINT64_C(0),
1296 UINT64_C(0),
1297 UINT64_C(0),
1298 UINT64_C(0),
1299 UINT64_C(0),
1300 UINT64_C(0),
1301 UINT64_C(0),
1302 UINT64_C(0),
1303 UINT64_C(0),
1304 UINT64_C(0),
1305 UINT64_C(0),
1306 UINT64_C(0),
1307 UINT64_C(0),
1308 UINT64_C(0),
1309 UINT64_C(0),
1310 UINT64_C(0),
1311 UINT64_C(0),
1312 UINT64_C(0),
1313 UINT64_C(0),
1314 UINT64_C(0),
1315 UINT64_C(0),
1316 UINT64_C(0),
1317 UINT64_C(0),
1318 UINT64_C(0),
1319 UINT64_C(0),
1320 UINT64_C(0),
1321 UINT64_C(0),
1322 UINT64_C(0),
1323 UINT64_C(0),
1324 UINT64_C(0),
1325 UINT64_C(0),
1326 UINT64_C(0),
1327 UINT64_C(0),
1328 UINT64_C(0),
1329 UINT64_C(0),
1330 UINT64_C(0),
1331 UINT64_C(0),
1332 UINT64_C(0),
1333 UINT64_C(0),
1334 UINT64_C(0),
1335 UINT64_C(0),
1336 UINT64_C(0),
1337 UINT64_C(0),
1338 UINT64_C(0),
1339 UINT64_C(0),
1340 UINT64_C(0),
1341 UINT64_C(0),
1342 UINT64_C(0),
1343 UINT64_C(0),
1344 UINT64_C(0),
1345 UINT64_C(0),
1346 UINT64_C(0),
1347 UINT64_C(0),
1348 UINT64_C(0),
1349 UINT64_C(0),
1350 UINT64_C(0),
1351 UINT64_C(0),
1352 UINT64_C(0),
1353 UINT64_C(0),
1354 UINT64_C(0),
1355 UINT64_C(0),
1356 UINT64_C(0),
1357 UINT64_C(0),
1358 UINT64_C(0),
1359 UINT64_C(0),
1360 UINT64_C(0),
1361 UINT64_C(0),
1362 UINT64_C(0),
1363 UINT64_C(0),
1364 UINT64_C(0),
1365 UINT64_C(0),
1366 UINT64_C(0),
1367 UINT64_C(0),
1368 UINT64_C(0),
1369 UINT64_C(0),
1370 UINT64_C(0),
1371 UINT64_C(0),
1372 UINT64_C(0),
1373 UINT64_C(0),
1374 UINT64_C(0),
1375 UINT64_C(0),
1376 UINT64_C(0),
1377 UINT64_C(0),
1378 UINT64_C(0),
1379 UINT64_C(0),
1380 UINT64_C(0),
1381 UINT64_C(0),
1382 UINT64_C(0),
1383 UINT64_C(0),
1384 UINT64_C(0),
1385 UINT64_C(0),
1386 UINT64_C(0),
1387 UINT64_C(0),
1388 UINT64_C(0),
1389 UINT64_C(0),
1390 UINT64_C(0),
1391 UINT64_C(0),
1392 UINT64_C(0),
1393 UINT64_C(0),
1394 UINT64_C(0),
1395 UINT64_C(0),
1396 UINT64_C(0),
1397 UINT64_C(0),
1398 UINT64_C(0),
1399 UINT64_C(0),
1400 UINT64_C(0),
1401 UINT64_C(0),
1402 UINT64_C(0),
1403 UINT64_C(0),
1404 UINT64_C(0),
1405 UINT64_C(0),
1406 UINT64_C(0),
1407 UINT64_C(0),
1408 UINT64_C(0),
1409 UINT64_C(0),
1410 UINT64_C(0),
1411 UINT64_C(0),
1412 UINT64_C(0),
1413 UINT64_C(0),
1414 UINT64_C(0),
1415 UINT64_C(0),
1416 UINT64_C(0),
1417 UINT64_C(0),
1418 UINT64_C(0),
1419 UINT64_C(0),
1420 UINT64_C(0),
1421 UINT64_C(0),
1422 UINT64_C(0),
1423 UINT64_C(0),
1424 UINT64_C(0),
1425 UINT64_C(0),
1426 UINT64_C(0),
1427 UINT64_C(0),
1428 UINT64_C(0),
1429 UINT64_C(0),
1430 UINT64_C(0),
1431 UINT64_C(0),
1432 UINT64_C(0),
1433 UINT64_C(0),
1434 UINT64_C(0),
1435 UINT64_C(0),
1436 UINT64_C(0),
1437 UINT64_C(0),
1438 UINT64_C(0),
1439 UINT64_C(0),
1440 UINT64_C(0),
1441 UINT64_C(0),
1442 UINT64_C(0),
1443 UINT64_C(0),
1444 UINT64_C(0),
1445 UINT64_C(0),
1446 UINT64_C(0),
1447 UINT64_C(0),
1448 UINT64_C(0),
1449 UINT64_C(0),
1450 UINT64_C(0),
1451 UINT64_C(0),
1452 UINT64_C(0),
1453 UINT64_C(0),
1454 UINT64_C(0),
1455 UINT64_C(0),
1456 UINT64_C(0),
1457 UINT64_C(0),
1458 UINT64_C(0),
1459 UINT64_C(0),
1460 UINT64_C(0),
1461 UINT64_C(0),
1462 UINT64_C(0),
1463 UINT64_C(0),
1464 UINT64_C(0),
1465 UINT64_C(0),
1466 UINT64_C(0),
1467 UINT64_C(0),
1468 UINT64_C(0),
1469 UINT64_C(0),
1470 UINT64_C(0),
1471 UINT64_C(0),
1472 UINT64_C(0),
1473 UINT64_C(0),
1474 UINT64_C(0),
1475 UINT64_C(0),
1476 UINT64_C(0),
1477 UINT64_C(0),
1478 UINT64_C(0),
1479 UINT64_C(0),
1480 UINT64_C(0),
1481 UINT64_C(0),
1482 UINT64_C(0),
1483 UINT64_C(0),
1484 UINT64_C(0),
1485 UINT64_C(0),
1486 UINT64_C(0),
1487 UINT64_C(0),
1488 UINT64_C(0),
1489 UINT64_C(0),
1490 UINT64_C(0),
1491 UINT64_C(0),
1492 UINT64_C(0),
1493 UINT64_C(0),
1494 UINT64_C(0),
1495 UINT64_C(0),
1496 UINT64_C(0),
1497 UINT64_C(0),
1498 UINT64_C(0),
1499 UINT64_C(0),
1500 UINT64_C(0),
1501 UINT64_C(0),
1502 UINT64_C(0),
1503 UINT64_C(0),
1504 UINT64_C(0),
1505 UINT64_C(0),
1506 UINT64_C(0),
1507 UINT64_C(0),
1508 UINT64_C(0),
1509 UINT64_C(0),
1510 UINT64_C(0),
1511 UINT64_C(0),
1512 UINT64_C(0),
1513 UINT64_C(0),
1514 UINT64_C(0),
1515 UINT64_C(0),
1516 UINT64_C(0),
1517 UINT64_C(0),
1518 UINT64_C(0),
1519 UINT64_C(0),
1520 UINT64_C(0),
1521 UINT64_C(0),
1522 UINT64_C(0),
1523 UINT64_C(0),
1524 UINT64_C(0),
1525 UINT64_C(0),
1526 UINT64_C(0),
1527 UINT64_C(0),
1528 UINT64_C(0),
1529 UINT64_C(0),
1530 UINT64_C(0),
1531 UINT64_C(0),
1532 UINT64_C(0),
1533 UINT64_C(0),
1534 UINT64_C(0),
1535 UINT64_C(0),
1536 UINT64_C(0),
1537 UINT64_C(0),
1538 UINT64_C(0),
1539 UINT64_C(0),
1540 UINT64_C(0),
1541 UINT64_C(0),
1542 UINT64_C(0),
1543 UINT64_C(0),
1544 UINT64_C(0),
1545 UINT64_C(0),
1546 UINT64_C(0),
1547 UINT64_C(0),
1548 UINT64_C(0),
1549 UINT64_C(0),
1550 UINT64_C(0),
1551 UINT64_C(0),
1552 UINT64_C(0),
1553 UINT64_C(0),
1554 UINT64_C(0),
1555 UINT64_C(0),
1556 UINT64_C(0),
1557 UINT64_C(0),
1558 UINT64_C(0),
1559 UINT64_C(0),
1560 UINT64_C(0),
1561 UINT64_C(0),
1562 UINT64_C(0),
1563 UINT64_C(0),
1564 UINT64_C(0),
1565 UINT64_C(0),
1566 UINT64_C(0),
1567 UINT64_C(0),
1568 UINT64_C(0),
1569 UINT64_C(0),
1570 UINT64_C(0),
1571 UINT64_C(0),
1572 UINT64_C(0),
1573 UINT64_C(0),
1574 UINT64_C(0),
1575 UINT64_C(0),
1576 UINT64_C(0),
1577 UINT64_C(0),
1578 UINT64_C(0),
1579 UINT64_C(0),
1580 UINT64_C(0),
1581 UINT64_C(0),
1582 UINT64_C(0),
1583 UINT64_C(0),
1584 UINT64_C(0),
1585 UINT64_C(0),
1586 UINT64_C(0),
1587 UINT64_C(0),
1588 UINT64_C(0),
1589 UINT64_C(0),
1590 UINT64_C(0),
1591 UINT64_C(0),
1592 UINT64_C(0),
1593 UINT64_C(0),
1594 UINT64_C(0),
1595 UINT64_C(0),
1596 UINT64_C(0),
1597 UINT64_C(0),
1598 UINT64_C(0),
1599 UINT64_C(0),
1600 UINT64_C(0),
1601 UINT64_C(0),
1602 UINT64_C(0),
1603 UINT64_C(0),
1604 UINT64_C(0),
1605 UINT64_C(0),
1606 UINT64_C(0),
1607 UINT64_C(0),
1608 UINT64_C(0),
1609 UINT64_C(0),
1610 UINT64_C(0),
1611 UINT64_C(0),
1612 UINT64_C(0),
1613 UINT64_C(0),
1614 UINT64_C(0),
1615 UINT64_C(0),
1616 UINT64_C(0),
1617 UINT64_C(0),
1618 UINT64_C(0),
1619 UINT64_C(0),
1620 UINT64_C(0),
1621 UINT64_C(0),
1622 UINT64_C(0),
1623 UINT64_C(0),
1624 UINT64_C(0),
1625 UINT64_C(0),
1626 UINT64_C(0),
1627 UINT64_C(0),
1628 UINT64_C(0),
1629 UINT64_C(0),
1630 UINT64_C(0),
1631 UINT64_C(0),
1632 UINT64_C(0),
1633 UINT64_C(0),
1634 UINT64_C(0),
1635 UINT64_C(0),
1636 UINT64_C(0),
1637 UINT64_C(0),
1638 UINT64_C(0),
1639 UINT64_C(0),
1640 UINT64_C(0),
1641 UINT64_C(0),
1642 UINT64_C(0),
1643 UINT64_C(0),
1644 UINT64_C(0),
1645 UINT64_C(0),
1646 UINT64_C(0),
1647 UINT64_C(0),
1648 UINT64_C(0),
1649 UINT64_C(0),
1650 UINT64_C(0),
1651 UINT64_C(0),
1652 UINT64_C(0),
1653 UINT64_C(0),
1654 UINT64_C(0),
1655 UINT64_C(0),
1656 UINT64_C(0),
1657 UINT64_C(0),
1658 UINT64_C(0),
1659 UINT64_C(0),
1660 UINT64_C(0),
1661 UINT64_C(0),
1662 UINT64_C(0),
1663 UINT64_C(0),
1664 UINT64_C(0),
1665 UINT64_C(0),
1666 UINT64_C(0),
1667 UINT64_C(0),
1668 UINT64_C(0),
1669 UINT64_C(0),
1670 UINT64_C(0),
1671 UINT64_C(0),
1672 UINT64_C(0),
1673 UINT64_C(0),
1674 UINT64_C(0),
1675 UINT64_C(0),
1676 UINT64_C(0),
1677 UINT64_C(0),
1678 UINT64_C(0),
1679 UINT64_C(0),
1680 UINT64_C(0),
1681 UINT64_C(0),
1682 UINT64_C(0),
1683 UINT64_C(0),
1684 UINT64_C(0),
1685 UINT64_C(0),
1686 UINT64_C(0),
1687 UINT64_C(0),
1688 UINT64_C(0),
1689 UINT64_C(0),
1690 UINT64_C(0),
1691 UINT64_C(0),
1692 UINT64_C(0),
1693 UINT64_C(0),
1694 UINT64_C(0),
1695 UINT64_C(0),
1696 UINT64_C(0),
1697 UINT64_C(0),
1698 UINT64_C(0),
1699 UINT64_C(0),
1700 UINT64_C(0),
1701 UINT64_C(0),
1702 UINT64_C(0),
1703 UINT64_C(0),
1704 UINT64_C(0),
1705 UINT64_C(0),
1706 UINT64_C(0),
1707 UINT64_C(0),
1708 UINT64_C(0),
1709 UINT64_C(0),
1710 UINT64_C(0),
1711 UINT64_C(0),
1712 UINT64_C(0),
1713 UINT64_C(0),
1714 UINT64_C(0),
1715 UINT64_C(0),
1716 UINT64_C(0),
1717 UINT64_C(0),
1718 UINT64_C(0),
1719 UINT64_C(0),
1720 UINT64_C(0),
1721 UINT64_C(0),
1722 UINT64_C(0),
1723 UINT64_C(0),
1724 UINT64_C(0),
1725 UINT64_C(0),
1726 UINT64_C(0),
1727 UINT64_C(0),
1728 UINT64_C(0),
1729 UINT64_C(0),
1730 UINT64_C(0),
1731 UINT64_C(0),
1732 UINT64_C(0),
1733 UINT64_C(0),
1734 UINT64_C(0),
1735 UINT64_C(0),
1736 UINT64_C(0),
1737 UINT64_C(0),
1738 UINT64_C(0),
1739 UINT64_C(0),
1740 UINT64_C(0),
1741 UINT64_C(0),
1742 UINT64_C(0),
1743 UINT64_C(0),
1744 UINT64_C(0),
1745 UINT64_C(0),
1746 UINT64_C(0),
1747 UINT64_C(0),
1748 UINT64_C(0),
1749 UINT64_C(0),
1750 UINT64_C(0),
1751 UINT64_C(0),
1752 UINT64_C(0),
1753 UINT64_C(0),
1754 UINT64_C(0),
1755 UINT64_C(0),
1756 UINT64_C(0),
1757 UINT64_C(0),
1758 UINT64_C(0),
1759 UINT64_C(0),
1760 UINT64_C(0),
1761 UINT64_C(0),
1762 UINT64_C(0),
1763 UINT64_C(0),
1764 UINT64_C(0),
1765 UINT64_C(0),
1766 UINT64_C(0),
1767 UINT64_C(0),
1768 UINT64_C(0),
1769 UINT64_C(0),
1770 UINT64_C(0),
1771 UINT64_C(0),
1772 UINT64_C(0),
1773 UINT64_C(0),
1774 UINT64_C(0),
1775 UINT64_C(0),
1776 UINT64_C(0),
1777 UINT64_C(0),
1778 UINT64_C(0),
1779 UINT64_C(0),
1780 UINT64_C(0),
1781 UINT64_C(0),
1782 UINT64_C(0),
1783 UINT64_C(0),
1784 UINT64_C(0),
1785 UINT64_C(0),
1786 UINT64_C(0),
1787 UINT64_C(0),
1788 UINT64_C(0),
1789 UINT64_C(0),
1790 UINT64_C(0),
1791 UINT64_C(0),
1792 UINT64_C(0),
1793 UINT64_C(0),
1794 UINT64_C(0),
1795 UINT64_C(0),
1796 UINT64_C(0),
1797 UINT64_C(0),
1798 UINT64_C(0),
1799 UINT64_C(0),
1800 UINT64_C(0),
1801 UINT64_C(0),
1802 UINT64_C(0),
1803 UINT64_C(0),
1804 UINT64_C(0),
1805 UINT64_C(0),
1806 UINT64_C(0),
1807 UINT64_C(0),
1808 UINT64_C(0),
1809 UINT64_C(0),
1810 UINT64_C(0),
1811 UINT64_C(0),
1812 UINT64_C(0),
1813 UINT64_C(0),
1814 UINT64_C(0),
1815 UINT64_C(0),
1816 UINT64_C(0),
1817 UINT64_C(0),
1818 UINT64_C(0),
1819 UINT64_C(0),
1820 UINT64_C(0),
1821 UINT64_C(0),
1822 UINT64_C(0),
1823 UINT64_C(0),
1824 UINT64_C(0),
1825 UINT64_C(0),
1826 UINT64_C(0),
1827 UINT64_C(0),
1828 UINT64_C(0),
1829 UINT64_C(0),
1830 UINT64_C(0),
1831 UINT64_C(0),
1832 UINT64_C(0),
1833 UINT64_C(0),
1834 UINT64_C(0),
1835 UINT64_C(0),
1836 UINT64_C(0),
1837 UINT64_C(0),
1838 UINT64_C(0),
1839 UINT64_C(0),
1840 UINT64_C(0),
1841 UINT64_C(0),
1842 UINT64_C(0),
1843 UINT64_C(0),
1844 UINT64_C(0),
1845 UINT64_C(0),
1846 UINT64_C(0),
1847 UINT64_C(0),
1848 UINT64_C(0),
1849 UINT64_C(0),
1850 UINT64_C(0),
1851 UINT64_C(0),
1852 UINT64_C(0),
1853 UINT64_C(0),
1854 UINT64_C(0),
1855 UINT64_C(0),
1856 UINT64_C(0),
1857 UINT64_C(0),
1858 UINT64_C(0),
1859 UINT64_C(0),
1860 UINT64_C(0),
1861 UINT64_C(0),
1862 UINT64_C(0),
1863 UINT64_C(0),
1864 UINT64_C(0),
1865 UINT64_C(0),
1866 UINT64_C(0),
1867 UINT64_C(0),
1868 UINT64_C(0),
1869 UINT64_C(0),
1870 UINT64_C(0),
1871 UINT64_C(0),
1872 UINT64_C(0),
1873 UINT64_C(0),
1874 UINT64_C(0),
1875 UINT64_C(0),
1876 UINT64_C(0),
1877 UINT64_C(0),
1878 UINT64_C(0),
1879 UINT64_C(0),
1880 UINT64_C(0),
1881 UINT64_C(0),
1882 UINT64_C(0),
1883 UINT64_C(0),
1884 UINT64_C(0),
1885 UINT64_C(0),
1886 UINT64_C(0),
1887 UINT64_C(0),
1888 UINT64_C(0),
1889 UINT64_C(0),
1890 UINT64_C(0),
1891 UINT64_C(0),
1892 UINT64_C(0),
1893 UINT64_C(0),
1894 UINT64_C(0),
1895 UINT64_C(0),
1896 UINT64_C(0),
1897 UINT64_C(0),
1898 UINT64_C(0),
1899 UINT64_C(0),
1900 UINT64_C(0),
1901 UINT64_C(0),
1902 UINT64_C(0),
1903 UINT64_C(0),
1904 UINT64_C(0),
1905 UINT64_C(0),
1906 UINT64_C(0),
1907 UINT64_C(0),
1908 UINT64_C(0),
1909 UINT64_C(0),
1910 UINT64_C(0),
1911 UINT64_C(0),
1912 UINT64_C(0),
1913 UINT64_C(0),
1914 UINT64_C(0),
1915 UINT64_C(0),
1916 UINT64_C(0),
1917 UINT64_C(0),
1918 UINT64_C(0),
1919 UINT64_C(0),
1920 UINT64_C(0),
1921 UINT64_C(0),
1922 UINT64_C(0),
1923 UINT64_C(0),
1924 UINT64_C(0),
1925 UINT64_C(0),
1926 UINT64_C(0),
1927 UINT64_C(0),
1928 UINT64_C(0),
1929 UINT64_C(0),
1930 UINT64_C(0),
1931 UINT64_C(0),
1932 UINT64_C(0),
1933 UINT64_C(0),
1934 UINT64_C(0),
1935 UINT64_C(0),
1936 UINT64_C(0),
1937 UINT64_C(0),
1938 UINT64_C(0),
1939 UINT64_C(0),
1940 UINT64_C(0),
1941 UINT64_C(0),
1942 UINT64_C(0),
1943 UINT64_C(0),
1944 UINT64_C(0),
1945 UINT64_C(0),
1946 UINT64_C(0),
1947 UINT64_C(0),
1948 UINT64_C(0),
1949 UINT64_C(0),
1950 UINT64_C(0),
1951 UINT64_C(0),
1952 UINT64_C(0),
1953 UINT64_C(0),
1954 UINT64_C(0),
1955 UINT64_C(0),
1956 UINT64_C(0),
1957 UINT64_C(0),
1958 UINT64_C(0),
1959 UINT64_C(0),
1960 UINT64_C(0),
1961 UINT64_C(0),
1962 UINT64_C(0),
1963 UINT64_C(0),
1964 UINT64_C(0),
1965 UINT64_C(0),
1966 UINT64_C(0),
1967 UINT64_C(0),
1968 UINT64_C(0),
1969 UINT64_C(0),
1970 UINT64_C(0),
1971 UINT64_C(0),
1972 UINT64_C(0),
1973 UINT64_C(0),
1974 UINT64_C(0),
1975 UINT64_C(0),
1976 UINT64_C(0),
1977 UINT64_C(0),
1978 UINT64_C(0),
1979 UINT64_C(0),
1980 UINT64_C(0),
1981 UINT64_C(0),
1982 UINT64_C(0),
1983 UINT64_C(0),
1984 UINT64_C(0),
1985 UINT64_C(0),
1986 UINT64_C(0),
1987 UINT64_C(0),
1988 UINT64_C(0),
1989 UINT64_C(0),
1990 UINT64_C(0),
1991 UINT64_C(0),
1992 UINT64_C(0),
1993 UINT64_C(0),
1994 UINT64_C(0),
1995 UINT64_C(0),
1996 UINT64_C(0),
1997 UINT64_C(0),
1998 UINT64_C(0),
1999 UINT64_C(0),
2000 UINT64_C(0),
2001 UINT64_C(0),
2002 UINT64_C(0),
2003 UINT64_C(0),
2004 UINT64_C(0),
2005 UINT64_C(0),
2006 UINT64_C(0),
2007 UINT64_C(0),
2008 UINT64_C(0),
2009 UINT64_C(0),
2010 UINT64_C(0),
2011 UINT64_C(0),
2012 UINT64_C(0),
2013 UINT64_C(0),
2014 UINT64_C(0),
2015 UINT64_C(0),
2016 UINT64_C(0),
2017 UINT64_C(0),
2018 UINT64_C(0),
2019 UINT64_C(0),
2020 UINT64_C(0),
2021 UINT64_C(0),
2022 UINT64_C(0),
2023 UINT64_C(0),
2024 UINT64_C(0),
2025 UINT64_C(0),
2026 UINT64_C(0),
2027 UINT64_C(0),
2028 UINT64_C(0),
2029 UINT64_C(0),
2030 UINT64_C(0),
2031 UINT64_C(0),
2032 UINT64_C(0),
2033 UINT64_C(0),
2034 UINT64_C(0),
2035 UINT64_C(0),
2036 UINT64_C(0),
2037 UINT64_C(0),
2038 UINT64_C(0),
2039 UINT64_C(0),
2040 UINT64_C(0),
2041 UINT64_C(0),
2042 UINT64_C(0),
2043 UINT64_C(0),
2044 UINT64_C(0),
2045 UINT64_C(0),
2046 UINT64_C(0),
2047 UINT64_C(0),
2048 UINT64_C(0),
2049 UINT64_C(0),
2050 UINT64_C(0),
2051 UINT64_C(0),
2052 UINT64_C(0),
2053 UINT64_C(0),
2054 UINT64_C(0),
2055 UINT64_C(0),
2056 UINT64_C(0),
2057 UINT64_C(0),
2058 UINT64_C(0),
2059 UINT64_C(0),
2060 UINT64_C(0),
2061 UINT64_C(0),
2062 UINT64_C(0),
2063 UINT64_C(0),
2064 UINT64_C(0),
2065 UINT64_C(0),
2066 UINT64_C(0),
2067 UINT64_C(0),
2068 UINT64_C(0),
2069 UINT64_C(0),
2070 UINT64_C(0),
2071 UINT64_C(0),
2072 UINT64_C(0),
2073 UINT64_C(0),
2074 UINT64_C(0),
2075 UINT64_C(0),
2076 UINT64_C(0),
2077 UINT64_C(0),
2078 UINT64_C(0),
2079 UINT64_C(0),
2080 UINT64_C(0),
2081 UINT64_C(0),
2082 UINT64_C(0),
2083 UINT64_C(0),
2084 UINT64_C(0),
2085 UINT64_C(0),
2086 UINT64_C(0),
2087 UINT64_C(0),
2088 UINT64_C(0),
2089 UINT64_C(0),
2090 UINT64_C(0),
2091 UINT64_C(0),
2092 UINT64_C(0),
2093 UINT64_C(0),
2094 UINT64_C(0),
2095 UINT64_C(0),
2096 UINT64_C(0),
2097 UINT64_C(0),
2098 UINT64_C(0),
2099 UINT64_C(0),
2100 UINT64_C(0),
2101 UINT64_C(0),
2102 UINT64_C(0),
2103 UINT64_C(0),
2104 UINT64_C(0),
2105 UINT64_C(0),
2106 UINT64_C(0),
2107 UINT64_C(0),
2108 UINT64_C(0),
2109 UINT64_C(0),
2110 UINT64_C(0),
2111 UINT64_C(0),
2112 UINT64_C(0),
2113 UINT64_C(0),
2114 UINT64_C(0),
2115 UINT64_C(0),
2116 UINT64_C(0),
2117 UINT64_C(0),
2118 UINT64_C(0),
2119 UINT64_C(0),
2120 UINT64_C(0),
2121 UINT64_C(0),
2122 UINT64_C(0),
2123 UINT64_C(0),
2124 UINT64_C(0),
2125 UINT64_C(0),
2126 UINT64_C(0),
2127 UINT64_C(0),
2128 UINT64_C(0),
2129 UINT64_C(0),
2130 UINT64_C(0),
2131 UINT64_C(0),
2132 UINT64_C(0),
2133 UINT64_C(0),
2134 UINT64_C(0),
2135 UINT64_C(0),
2136 UINT64_C(0),
2137 UINT64_C(0),
2138 UINT64_C(0),
2139 UINT64_C(0),
2140 UINT64_C(0),
2141 UINT64_C(0),
2142 UINT64_C(0),
2143 UINT64_C(0),
2144 UINT64_C(0),
2145 UINT64_C(0),
2146 UINT64_C(0),
2147 UINT64_C(0),
2148 UINT64_C(0),
2149 UINT64_C(0),
2150 UINT64_C(0),
2151 UINT64_C(0),
2152 UINT64_C(0),
2153 UINT64_C(0),
2154 UINT64_C(0),
2155 UINT64_C(0),
2156 UINT64_C(0),
2157 UINT64_C(0),
2158 UINT64_C(0),
2159 UINT64_C(0),
2160 UINT64_C(0),
2161 UINT64_C(0),
2162 UINT64_C(0),
2163 UINT64_C(0),
2164 UINT64_C(0),
2165 UINT64_C(0),
2166 UINT64_C(0),
2167 UINT64_C(0),
2168 UINT64_C(0),
2169 UINT64_C(0),
2170 UINT64_C(0),
2171 UINT64_C(0),
2172 UINT64_C(0),
2173 UINT64_C(0),
2174 UINT64_C(0),
2175 UINT64_C(0),
2176 UINT64_C(0),
2177 UINT64_C(0),
2178 UINT64_C(0),
2179 UINT64_C(0),
2180 UINT64_C(0),
2181 UINT64_C(0),
2182 UINT64_C(0),
2183 UINT64_C(0),
2184 UINT64_C(0),
2185 UINT64_C(0),
2186 UINT64_C(0),
2187 UINT64_C(0),
2188 UINT64_C(0),
2189 UINT64_C(0),
2190 UINT64_C(0),
2191 UINT64_C(0),
2192 UINT64_C(0),
2193 UINT64_C(0),
2194 UINT64_C(0),
2195 UINT64_C(0),
2196 UINT64_C(0),
2197 UINT64_C(0),
2198 UINT64_C(0),
2199 UINT64_C(0),
2200 UINT64_C(0),
2201 UINT64_C(0),
2202 UINT64_C(0),
2203 UINT64_C(0),
2204 UINT64_C(0),
2205 UINT64_C(0),
2206 UINT64_C(0),
2207 UINT64_C(0),
2208 UINT64_C(0),
2209 UINT64_C(0),
2210 UINT64_C(0),
2211 UINT64_C(0),
2212 UINT64_C(0),
2213 UINT64_C(0),
2214 UINT64_C(0),
2215 UINT64_C(0),
2216 UINT64_C(0),
2217 UINT64_C(0),
2218 UINT64_C(0),
2219 UINT64_C(0),
2220 UINT64_C(0),
2221 UINT64_C(0),
2222 UINT64_C(0),
2223 UINT64_C(0),
2224 UINT64_C(0),
2225 UINT64_C(0),
2226 UINT64_C(0),
2227 UINT64_C(0),
2228 UINT64_C(0),
2229 UINT64_C(0),
2230 UINT64_C(0),
2231 UINT64_C(0),
2232 UINT64_C(0),
2233 UINT64_C(0),
2234 UINT64_C(0),
2235 UINT64_C(0),
2236 UINT64_C(0),
2237 UINT64_C(0),
2238 UINT64_C(0),
2239 UINT64_C(0),
2240 UINT64_C(0),
2241 UINT64_C(0),
2242 UINT64_C(0),
2243 UINT64_C(0),
2244 UINT64_C(0),
2245 UINT64_C(0),
2246 UINT64_C(0),
2247 UINT64_C(0),
2248 UINT64_C(0),
2249 UINT64_C(0),
2250 UINT64_C(0),
2251 UINT64_C(0),
2252 UINT64_C(0),
2253 UINT64_C(0),
2254 UINT64_C(0),
2255 UINT64_C(0),
2256 UINT64_C(0),
2257 UINT64_C(0),
2258 UINT64_C(0),
2259 UINT64_C(0),
2260 UINT64_C(0),
2261 UINT64_C(0),
2262 UINT64_C(0),
2263 UINT64_C(0),
2264 UINT64_C(0),
2265 UINT64_C(0),
2266 UINT64_C(0),
2267 UINT64_C(0),
2268 UINT64_C(0),
2269 UINT64_C(0),
2270 UINT64_C(0),
2271 UINT64_C(0),
2272 UINT64_C(0),
2273 UINT64_C(0),
2274 UINT64_C(0),
2275 UINT64_C(0),
2276 UINT64_C(0),
2277 UINT64_C(0),
2278 UINT64_C(0),
2279 UINT64_C(0),
2280 UINT64_C(0),
2281 UINT64_C(0),
2282 UINT64_C(0),
2283 UINT64_C(0),
2284 UINT64_C(0),
2285 UINT64_C(0),
2286 UINT64_C(0),
2287 UINT64_C(0),
2288 UINT64_C(0),
2289 UINT64_C(0),
2290 UINT64_C(0),
2291 UINT64_C(0),
2292 UINT64_C(0),
2293 UINT64_C(0),
2294 UINT64_C(0),
2295 UINT64_C(0),
2296 UINT64_C(0),
2297 UINT64_C(0),
2298 UINT64_C(0),
2299 UINT64_C(0),
2300 UINT64_C(0),
2301 UINT64_C(0),
2302 UINT64_C(0),
2303 UINT64_C(0),
2304 UINT64_C(0),
2305 UINT64_C(0),
2306 UINT64_C(0),
2307 UINT64_C(0),
2308 UINT64_C(0),
2309 UINT64_C(0),
2310 UINT64_C(0),
2311 UINT64_C(0),
2312 UINT64_C(0),
2313 UINT64_C(0),
2314 UINT64_C(0),
2315 UINT64_C(0),
2316 UINT64_C(0),
2317 UINT64_C(0),
2318 UINT64_C(0),
2319 UINT64_C(0),
2320 UINT64_C(0),
2321 UINT64_C(0),
2322 UINT64_C(0),
2323 UINT64_C(0),
2324 UINT64_C(0),
2325 UINT64_C(0),
2326 UINT64_C(0),
2327 UINT64_C(0),
2328 UINT64_C(0),
2329 UINT64_C(0),
2330 UINT64_C(0),
2331 UINT64_C(0),
2332 UINT64_C(0),
2333 UINT64_C(0),
2334 UINT64_C(0),
2335 UINT64_C(0),
2336 UINT64_C(0),
2337 UINT64_C(0),
2338 UINT64_C(0),
2339 UINT64_C(0),
2340 UINT64_C(0),
2341 UINT64_C(0),
2342 UINT64_C(0),
2343 UINT64_C(0),
2344 UINT64_C(0),
2345 UINT64_C(0),
2346 UINT64_C(0),
2347 UINT64_C(0),
2348 UINT64_C(0),
2349 UINT64_C(0),
2350 UINT64_C(0),
2351 UINT64_C(0),
2352 UINT64_C(0),
2353 UINT64_C(0),
2354 UINT64_C(0),
2355 UINT64_C(0),
2356 UINT64_C(0),
2357 UINT64_C(0),
2358 UINT64_C(0),
2359 UINT64_C(0),
2360 UINT64_C(0),
2361 UINT64_C(0),
2362 UINT64_C(0),
2363 UINT64_C(0),
2364 UINT64_C(0),
2365 UINT64_C(0),
2366 UINT64_C(0),
2367 UINT64_C(0),
2368 UINT64_C(0),
2369 UINT64_C(0),
2370 UINT64_C(0),
2371 UINT64_C(0),
2372 UINT64_C(0),
2373 UINT64_C(0),
2374 UINT64_C(0),
2375 UINT64_C(0),
2376 UINT64_C(0),
2377 UINT64_C(0),
2378 UINT64_C(0),
2379 UINT64_C(0),
2380 UINT64_C(0),
2381 UINT64_C(0),
2382 UINT64_C(0),
2383 UINT64_C(0),
2384 UINT64_C(0),
2385 UINT64_C(0),
2386 UINT64_C(0),
2387 UINT64_C(0),
2388 UINT64_C(0),
2389 UINT64_C(0),
2390 UINT64_C(0),
2391 UINT64_C(0),
2392 UINT64_C(0),
2393 UINT64_C(0),
2394 UINT64_C(0),
2395 UINT64_C(0),
2396 UINT64_C(0),
2397 UINT64_C(0),
2398 UINT64_C(0),
2399 UINT64_C(0),
2400 UINT64_C(0),
2401 UINT64_C(0),
2402 UINT64_C(0),
2403 UINT64_C(0),
2404 UINT64_C(0),
2405 UINT64_C(0),
2406 UINT64_C(0),
2407 UINT64_C(0),
2408 UINT64_C(0),
2409 UINT64_C(0),
2410 UINT64_C(0),
2411 UINT64_C(0),
2412 UINT64_C(0),
2413 UINT64_C(0),
2414 UINT64_C(0),
2415 UINT64_C(0),
2416 UINT64_C(0),
2417 UINT64_C(0),
2418 UINT64_C(0),
2419 UINT64_C(0),
2420 UINT64_C(0),
2421 UINT64_C(0),
2422 UINT64_C(0),
2423 UINT64_C(0),
2424 UINT64_C(0),
2425 UINT64_C(0),
2426 UINT64_C(0),
2427 UINT64_C(0),
2428 UINT64_C(0),
2429 UINT64_C(0),
2430 UINT64_C(0),
2431 UINT64_C(0),
2432 UINT64_C(0),
2433 UINT64_C(0),
2434 UINT64_C(0),
2435 UINT64_C(0),
2436 UINT64_C(0),
2437 UINT64_C(0),
2438 UINT64_C(0),
2439 UINT64_C(0),
2440 UINT64_C(0),
2441 UINT64_C(0),
2442 UINT64_C(0),
2443 UINT64_C(0),
2444 UINT64_C(0),
2445 UINT64_C(0),
2446 UINT64_C(0),
2447 UINT64_C(0),
2448 UINT64_C(0),
2449 UINT64_C(0),
2450 UINT64_C(0),
2451 UINT64_C(0),
2452 UINT64_C(0),
2453 UINT64_C(0),
2454 UINT64_C(0),
2455 UINT64_C(0),
2456 UINT64_C(0),
2457 UINT64_C(0),
2458 UINT64_C(0),
2459 UINT64_C(0),
2460 UINT64_C(0),
2461 UINT64_C(0),
2462 UINT64_C(0),
2463 UINT64_C(0),
2464 UINT64_C(0),
2465 UINT64_C(0),
2466 UINT64_C(0),
2467 UINT64_C(0),
2468 UINT64_C(0),
2469 UINT64_C(0),
2470 UINT64_C(0),
2471 UINT64_C(0),
2472 UINT64_C(0),
2473 UINT64_C(0),
2474 UINT64_C(0),
2475 UINT64_C(0),
2476 UINT64_C(0),
2477 UINT64_C(0),
2478 UINT64_C(0),
2479 UINT64_C(0),
2480 UINT64_C(0),
2481 UINT64_C(0),
2482 UINT64_C(0),
2483 UINT64_C(0),
2484 UINT64_C(0),
2485 UINT64_C(0),
2486 UINT64_C(0),
2487 UINT64_C(0),
2488 UINT64_C(0),
2489 UINT64_C(0),
2490 UINT64_C(0),
2491 UINT64_C(0),
2492 UINT64_C(0),
2493 UINT64_C(0),
2494 UINT64_C(0),
2495 UINT64_C(0),
2496 UINT64_C(0),
2497 UINT64_C(0),
2498 UINT64_C(0),
2499 UINT64_C(0),
2500 UINT64_C(0),
2501 UINT64_C(0),
2502 UINT64_C(0),
2503 UINT64_C(0),
2504 UINT64_C(0),
2505 UINT64_C(0),
2506 UINT64_C(0),
2507 UINT64_C(0),
2508 UINT64_C(0),
2509 UINT64_C(0),
2510 UINT64_C(0),
2511 UINT64_C(0),
2512 UINT64_C(0),
2513 UINT64_C(0),
2514 UINT64_C(0),
2515 UINT64_C(0),
2516 UINT64_C(0),
2517 UINT64_C(0),
2518 UINT64_C(0),
2519 UINT64_C(0),
2520 UINT64_C(0),
2521 UINT64_C(0),
2522 UINT64_C(0),
2523 UINT64_C(0),
2524 UINT64_C(0),
2525 UINT64_C(0),
2526 UINT64_C(0),
2527 UINT64_C(0),
2528 UINT64_C(0),
2529 UINT64_C(0),
2530 UINT64_C(0),
2531 UINT64_C(0),
2532 UINT64_C(0),
2533 UINT64_C(0),
2534 UINT64_C(0),
2535 UINT64_C(0),
2536 UINT64_C(0),
2537 UINT64_C(0),
2538 UINT64_C(0),
2539 UINT64_C(0),
2540 UINT64_C(0),
2541 UINT64_C(0),
2542 UINT64_C(0),
2543 UINT64_C(0),
2544 UINT64_C(0),
2545 UINT64_C(0),
2546 UINT64_C(0),
2547 UINT64_C(0),
2548 UINT64_C(0),
2549 UINT64_C(0),
2550 UINT64_C(0),
2551 UINT64_C(0),
2552 UINT64_C(0),
2553 UINT64_C(0),
2554 UINT64_C(0),
2555 UINT64_C(0),
2556 UINT64_C(0),
2557 UINT64_C(0),
2558 UINT64_C(0),
2559 UINT64_C(0),
2560 UINT64_C(0),
2561 UINT64_C(0),
2562 UINT64_C(0),
2563 UINT64_C(0),
2564 UINT64_C(0),
2565 UINT64_C(0),
2566 UINT64_C(0),
2567 UINT64_C(0),
2568 UINT64_C(0),
2569 UINT64_C(0),
2570 UINT64_C(0),
2571 UINT64_C(0),
2572 UINT64_C(0),
2573 UINT64_C(0),
2574 UINT64_C(0),
2575 UINT64_C(0),
2576 UINT64_C(0),
2577 UINT64_C(0),
2578 UINT64_C(0),
2579 UINT64_C(0),
2580 UINT64_C(0),
2581 UINT64_C(0),
2582 UINT64_C(0),
2583 UINT64_C(0),
2584 UINT64_C(0),
2585 UINT64_C(0),
2586 UINT64_C(0),
2587 UINT64_C(0),
2588 UINT64_C(0),
2589 UINT64_C(0),
2590 UINT64_C(0),
2591 UINT64_C(0),
2592 UINT64_C(0),
2593 UINT64_C(0),
2594 UINT64_C(0),
2595 UINT64_C(0),
2596 UINT64_C(0),
2597 UINT64_C(0),
2598 UINT64_C(0),
2599 UINT64_C(0),
2600 UINT64_C(0),
2601 UINT64_C(0),
2602 UINT64_C(0),
2603 UINT64_C(0),
2604 UINT64_C(0),
2605 UINT64_C(0),
2606 UINT64_C(0),
2607 UINT64_C(0),
2608 UINT64_C(0),
2609 UINT64_C(0),
2610 UINT64_C(0),
2611 UINT64_C(0),
2612 UINT64_C(0),
2613 UINT64_C(0),
2614 UINT64_C(0),
2615 UINT64_C(0),
2616 UINT64_C(0),
2617 UINT64_C(0),
2618 UINT64_C(0),
2619 UINT64_C(0),
2620 UINT64_C(0),
2621 UINT64_C(0),
2622 UINT64_C(0),
2623 UINT64_C(0),
2624 UINT64_C(0),
2625 UINT64_C(0),
2626 UINT64_C(0),
2627 UINT64_C(0),
2628 UINT64_C(0),
2629 UINT64_C(0),
2630 UINT64_C(0),
2631 UINT64_C(0),
2632 UINT64_C(0),
2633 UINT64_C(0),
2634 UINT64_C(0),
2635 UINT64_C(0),
2636 UINT64_C(0),
2637 UINT64_C(0),
2638 UINT64_C(0),
2639 UINT64_C(0),
2640 UINT64_C(0),
2641 UINT64_C(0),
2642 UINT64_C(0),
2643 UINT64_C(0),
2644 UINT64_C(0),
2645 UINT64_C(0),
2646 UINT64_C(0),
2647 UINT64_C(0),
2648 UINT64_C(0),
2649 UINT64_C(0),
2650 UINT64_C(0),
2651 UINT64_C(0),
2652 UINT64_C(0),
2653 UINT64_C(0),
2654 UINT64_C(0),
2655 UINT64_C(0),
2656 UINT64_C(0),
2657 UINT64_C(0),
2658 UINT64_C(0),
2659 UINT64_C(0),
2660 UINT64_C(0),
2661 UINT64_C(0),
2662 UINT64_C(0),
2663 UINT64_C(0),
2664 UINT64_C(0),
2665 UINT64_C(0),
2666 UINT64_C(0),
2667 UINT64_C(0),
2668 UINT64_C(0),
2669 UINT64_C(0),
2670 UINT64_C(0),
2671 UINT64_C(0),
2672 UINT64_C(0),
2673 UINT64_C(0),
2674 UINT64_C(0),
2675 UINT64_C(0),
2676 UINT64_C(0),
2677 UINT64_C(0),
2678 UINT64_C(0),
2679 UINT64_C(0),
2680 UINT64_C(0),
2681 UINT64_C(0),
2682 UINT64_C(0),
2683 UINT64_C(0),
2684 UINT64_C(0),
2685 UINT64_C(0),
2686 UINT64_C(0),
2687 UINT64_C(0),
2688 UINT64_C(0),
2689 UINT64_C(0),
2690 UINT64_C(0),
2691 UINT64_C(0),
2692 UINT64_C(0),
2693 UINT64_C(0),
2694 UINT64_C(0),
2695 UINT64_C(0),
2696 UINT64_C(0),
2697 UINT64_C(0),
2698 UINT64_C(0),
2699 UINT64_C(0),
2700 UINT64_C(0),
2701 UINT64_C(0),
2702 UINT64_C(0),
2703 UINT64_C(0),
2704 UINT64_C(0),
2705 UINT64_C(0),
2706 UINT64_C(0),
2707 UINT64_C(0),
2708 UINT64_C(0),
2709 UINT64_C(0),
2710 UINT64_C(0),
2711 UINT64_C(0),
2712 UINT64_C(0),
2713 UINT64_C(0),
2714 UINT64_C(0),
2715 UINT64_C(0),
2716 UINT64_C(0),
2717 UINT64_C(0),
2718 UINT64_C(0),
2719 UINT64_C(0),
2720 UINT64_C(0),
2721 UINT64_C(0),
2722 UINT64_C(0),
2723 UINT64_C(0),
2724 UINT64_C(0),
2725 UINT64_C(0),
2726 UINT64_C(0),
2727 UINT64_C(0),
2728 UINT64_C(0),
2729 UINT64_C(0),
2730 UINT64_C(0),
2731 UINT64_C(0),
2732 UINT64_C(0),
2733 UINT64_C(0),
2734 UINT64_C(0),
2735 UINT64_C(0),
2736 UINT64_C(0),
2737 UINT64_C(0),
2738 UINT64_C(0),
2739 UINT64_C(0),
2740 UINT64_C(0),
2741 UINT64_C(0),
2742 UINT64_C(0),
2743 UINT64_C(0),
2744 UINT64_C(0),
2745 UINT64_C(0),
2746 UINT64_C(0),
2747 UINT64_C(0),
2748 UINT64_C(0),
2749 UINT64_C(0),
2750 UINT64_C(0),
2751 UINT64_C(0),
2752 UINT64_C(0),
2753 UINT64_C(0),
2754 UINT64_C(0),
2755 UINT64_C(0),
2756 UINT64_C(0),
2757 UINT64_C(0),
2758 UINT64_C(0),
2759 UINT64_C(0),
2760 UINT64_C(0),
2761 UINT64_C(0),
2762 UINT64_C(0),
2763 UINT64_C(0),
2764 UINT64_C(0),
2765 UINT64_C(0),
2766 UINT64_C(0),
2767 UINT64_C(0),
2768 UINT64_C(0),
2769 UINT64_C(0),
2770 UINT64_C(0),
2771 UINT64_C(0),
2772 UINT64_C(0),
2773 UINT64_C(0),
2774 UINT64_C(0),
2775 UINT64_C(0),
2776 UINT64_C(0),
2777 UINT64_C(0),
2778 UINT64_C(0),
2779 UINT64_C(0),
2780 UINT64_C(0),
2781 UINT64_C(0),
2782 UINT64_C(0),
2783 UINT64_C(0),
2784 UINT64_C(0),
2785 UINT64_C(0),
2786 UINT64_C(0),
2787 UINT64_C(0),
2788 UINT64_C(0),
2789 UINT64_C(0),
2790 UINT64_C(0),
2791 UINT64_C(0),
2792 UINT64_C(0),
2793 UINT64_C(0),
2794 UINT64_C(0),
2795 UINT64_C(0),
2796 UINT64_C(0),
2797 UINT64_C(0),
2798 UINT64_C(0),
2799 UINT64_C(0),
2800 UINT64_C(0),
2801 UINT64_C(0),
2802 UINT64_C(0),
2803 UINT64_C(0),
2804 UINT64_C(0),
2805 UINT64_C(0),
2806 UINT64_C(0),
2807 UINT64_C(0),
2808 UINT64_C(0),
2809 UINT64_C(0),
2810 UINT64_C(0),
2811 UINT64_C(0),
2812 UINT64_C(0),
2813 UINT64_C(0),
2814 UINT64_C(0),
2815 UINT64_C(0),
2816 UINT64_C(0),
2817 UINT64_C(0),
2818 UINT64_C(0),
2819 UINT64_C(0),
2820 UINT64_C(0),
2821 UINT64_C(0),
2822 UINT64_C(0),
2823 UINT64_C(0),
2824 UINT64_C(0),
2825 UINT64_C(0),
2826 UINT64_C(0),
2827 UINT64_C(0),
2828 UINT64_C(0),
2829 UINT64_C(0),
2830 UINT64_C(0),
2831 UINT64_C(0),
2832 UINT64_C(0),
2833 UINT64_C(0),
2834 UINT64_C(0),
2835 UINT64_C(0),
2836 UINT64_C(0),
2837 UINT64_C(0),
2838 UINT64_C(0),
2839 UINT64_C(0),
2840 UINT64_C(0),
2841 UINT64_C(0),
2842 UINT64_C(0),
2843 UINT64_C(0),
2844 UINT64_C(0),
2845 UINT64_C(0),
2846 UINT64_C(0),
2847 UINT64_C(0),
2848 UINT64_C(0),
2849 UINT64_C(0),
2850 UINT64_C(0),
2851 UINT64_C(0),
2852 UINT64_C(0),
2853 UINT64_C(0),
2854 UINT64_C(0),
2855 UINT64_C(0),
2856 UINT64_C(0),
2857 UINT64_C(0),
2858 UINT64_C(0),
2859 UINT64_C(0),
2860 UINT64_C(0),
2861 UINT64_C(0),
2862 UINT64_C(0),
2863 UINT64_C(0),
2864 UINT64_C(0),
2865 UINT64_C(0),
2866 UINT64_C(0),
2867 UINT64_C(0),
2868 UINT64_C(0),
2869 UINT64_C(0),
2870 UINT64_C(0),
2871 UINT64_C(0),
2872 UINT64_C(0),
2873 UINT64_C(0),
2874 UINT64_C(0),
2875 UINT64_C(0),
2876 UINT64_C(0),
2877 UINT64_C(0),
2878 UINT64_C(0),
2879 UINT64_C(0),
2880 UINT64_C(0),
2881 UINT64_C(0),
2882 UINT64_C(0),
2883 UINT64_C(0),
2884 UINT64_C(0),
2885 UINT64_C(0),
2886 UINT64_C(0),
2887 UINT64_C(0),
2888 UINT64_C(0),
2889 UINT64_C(0),
2890 UINT64_C(0),
2891 UINT64_C(0),
2892 UINT64_C(0),
2893 UINT64_C(0),
2894 UINT64_C(0),
2895 UINT64_C(0),
2896 UINT64_C(0),
2897 UINT64_C(0),
2898 UINT64_C(0),
2899 UINT64_C(0),
2900 UINT64_C(0),
2901 UINT64_C(0),
2902 UINT64_C(0),
2903 UINT64_C(0),
2904 UINT64_C(0),
2905 UINT64_C(0),
2906 UINT64_C(0),
2907 UINT64_C(0),
2908 UINT64_C(0),
2909 UINT64_C(0),
2910 UINT64_C(0),
2911 UINT64_C(0),
2912 UINT64_C(0),
2913 UINT64_C(0),
2914 UINT64_C(0),
2915 UINT64_C(0),
2916 UINT64_C(0),
2917 UINT64_C(0),
2918 UINT64_C(0),
2919 UINT64_C(0),
2920 UINT64_C(0),
2921 UINT64_C(0),
2922 UINT64_C(0),
2923 UINT64_C(0),
2924 UINT64_C(0),
2925 UINT64_C(0),
2926 UINT64_C(0),
2927 UINT64_C(0),
2928 UINT64_C(0),
2929 UINT64_C(0),
2930 UINT64_C(0),
2931 UINT64_C(0),
2932 UINT64_C(0),
2933 UINT64_C(0),
2934 UINT64_C(0),
2935 UINT64_C(0),
2936 UINT64_C(0),
2937 UINT64_C(0),
2938 UINT64_C(0),
2939 UINT64_C(0),
2940 UINT64_C(0),
2941 UINT64_C(0),
2942 UINT64_C(0),
2943 UINT64_C(0),
2944 UINT64_C(0),
2945 UINT64_C(0),
2946 UINT64_C(0),
2947 UINT64_C(0),
2948 UINT64_C(0),
2949 UINT64_C(0),
2950 UINT64_C(0),
2951 UINT64_C(0),
2952 UINT64_C(0),
2953 UINT64_C(0),
2954 UINT64_C(0),
2955 UINT64_C(0),
2956 UINT64_C(0),
2957 UINT64_C(0),
2958 UINT64_C(0),
2959 UINT64_C(0),
2960 UINT64_C(0),
2961 UINT64_C(0),
2962 UINT64_C(0),
2963 UINT64_C(0),
2964 UINT64_C(0),
2965 UINT64_C(0),
2966 UINT64_C(0),
2967 UINT64_C(0),
2968 UINT64_C(0),
2969 UINT64_C(0),
2970 UINT64_C(0),
2971 UINT64_C(0),
2972 UINT64_C(0),
2973 UINT64_C(0),
2974 UINT64_C(0),
2975 UINT64_C(0),
2976 UINT64_C(0),
2977 UINT64_C(0),
2978 UINT64_C(0),
2979 UINT64_C(0),
2980 UINT64_C(0),
2981 UINT64_C(0),
2982 UINT64_C(0),
2983 UINT64_C(0),
2984 UINT64_C(0),
2985 UINT64_C(0),
2986 UINT64_C(0),
2987 UINT64_C(0),
2988 UINT64_C(0),
2989 UINT64_C(0),
2990 UINT64_C(0),
2991 UINT64_C(0),
2992 UINT64_C(0),
2993 UINT64_C(0),
2994 UINT64_C(0),
2995 UINT64_C(0),
2996 UINT64_C(0),
2997 UINT64_C(0),
2998 UINT64_C(0),
2999 UINT64_C(0),
3000 UINT64_C(0),
3001 UINT64_C(0),
3002 UINT64_C(0),
3003 UINT64_C(0),
3004 UINT64_C(0),
3005 UINT64_C(0),
3006 UINT64_C(0),
3007 UINT64_C(0),
3008 UINT64_C(0),
3009 UINT64_C(0),
3010 UINT64_C(0),
3011 UINT64_C(0),
3012 UINT64_C(0),
3013 UINT64_C(0),
3014 UINT64_C(0),
3015 UINT64_C(0),
3016 UINT64_C(0),
3017 UINT64_C(0),
3018 UINT64_C(0),
3019 UINT64_C(0),
3020 UINT64_C(0),
3021 UINT64_C(0),
3022 UINT64_C(0),
3023 UINT64_C(0),
3024 UINT64_C(0),
3025 UINT64_C(0),
3026 UINT64_C(0),
3027 UINT64_C(0),
3028 UINT64_C(0),
3029 UINT64_C(0),
3030 UINT64_C(0),
3031 UINT64_C(0),
3032 UINT64_C(0),
3033 UINT64_C(0),
3034 UINT64_C(0),
3035 UINT64_C(0),
3036 UINT64_C(0),
3037 UINT64_C(0),
3038 UINT64_C(0),
3039 UINT64_C(0),
3040 UINT64_C(0),
3041 UINT64_C(0),
3042 UINT64_C(0),
3043 UINT64_C(0),
3044 UINT64_C(0),
3045 UINT64_C(0),
3046 UINT64_C(0),
3047 UINT64_C(0),
3048 UINT64_C(0),
3049 UINT64_C(0),
3050 UINT64_C(0),
3051 UINT64_C(0),
3052 UINT64_C(0),
3053 UINT64_C(0),
3054 UINT64_C(0),
3055 UINT64_C(0),
3056 UINT64_C(0),
3057 UINT64_C(0),
3058 UINT64_C(0),
3059 UINT64_C(0),
3060 UINT64_C(0),
3061 UINT64_C(0),
3062 UINT64_C(0),
3063 UINT64_C(0),
3064 UINT64_C(0),
3065 UINT64_C(0),
3066 UINT64_C(0),
3067 UINT64_C(0),
3068 UINT64_C(0),
3069 UINT64_C(0),
3070 UINT64_C(0),
3071 UINT64_C(0),
3072 UINT64_C(0),
3073 UINT64_C(0),
3074 UINT64_C(0),
3075 UINT64_C(0),
3076 UINT64_C(0),
3077 UINT64_C(0),
3078 UINT64_C(0),
3079 UINT64_C(0),
3080 UINT64_C(0),
3081 UINT64_C(0),
3082 UINT64_C(0),
3083 UINT64_C(0),
3084 UINT64_C(0),
3085 UINT64_C(0),
3086 UINT64_C(0),
3087 UINT64_C(0),
3088 UINT64_C(0),
3089 UINT64_C(0),
3090 UINT64_C(0),
3091 UINT64_C(0),
3092 UINT64_C(0),
3093 UINT64_C(0),
3094 UINT64_C(0),
3095 UINT64_C(0),
3096 UINT64_C(0),
3097 UINT64_C(0),
3098 UINT64_C(0),
3099 UINT64_C(0),
3100 UINT64_C(0),
3101 UINT64_C(0),
3102 UINT64_C(0),
3103 UINT64_C(0),
3104 UINT64_C(0),
3105 UINT64_C(0),
3106 UINT64_C(0),
3107 UINT64_C(0),
3108 UINT64_C(0),
3109 UINT64_C(0),
3110 UINT64_C(0),
3111 UINT64_C(0),
3112 UINT64_C(0),
3113 UINT64_C(0),
3114 UINT64_C(0),
3115 UINT64_C(0),
3116 UINT64_C(0),
3117 UINT64_C(0),
3118 UINT64_C(0),
3119 UINT64_C(0),
3120 UINT64_C(0),
3121 UINT64_C(0),
3122 UINT64_C(0),
3123 UINT64_C(0),
3124 UINT64_C(0),
3125 UINT64_C(0),
3126 UINT64_C(0),
3127 UINT64_C(0),
3128 UINT64_C(0),
3129 UINT64_C(0),
3130 UINT64_C(0),
3131 UINT64_C(0),
3132 UINT64_C(0),
3133 UINT64_C(0),
3134 UINT64_C(0),
3135 UINT64_C(0),
3136 UINT64_C(0),
3137 UINT64_C(0),
3138 UINT64_C(0),
3139 UINT64_C(0),
3140 UINT64_C(0),
3141 UINT64_C(0),
3142 UINT64_C(0),
3143 UINT64_C(0),
3144 UINT64_C(0),
3145 UINT64_C(0),
3146 UINT64_C(0),
3147 UINT64_C(0),
3148 UINT64_C(0),
3149 UINT64_C(0),
3150 UINT64_C(0),
3151 UINT64_C(0),
3152 UINT64_C(0),
3153 UINT64_C(0),
3154 UINT64_C(0),
3155 UINT64_C(0),
3156 UINT64_C(0),
3157 UINT64_C(0),
3158 UINT64_C(0),
3159 UINT64_C(0),
3160 UINT64_C(0),
3161 UINT64_C(0),
3162 UINT64_C(0),
3163 UINT64_C(0),
3164 UINT64_C(0),
3165 UINT64_C(0),
3166 UINT64_C(0),
3167 UINT64_C(0),
3168 UINT64_C(0),
3169 UINT64_C(0),
3170 UINT64_C(0),
3171 UINT64_C(0),
3172 UINT64_C(0),
3173 UINT64_C(0),
3174 UINT64_C(0),
3175 UINT64_C(0),
3176 UINT64_C(0),
3177 UINT64_C(0),
3178 UINT64_C(0),
3179 UINT64_C(0),
3180 UINT64_C(0),
3181 UINT64_C(0),
3182 UINT64_C(0),
3183 UINT64_C(0),
3184 UINT64_C(0),
3185 UINT64_C(0),
3186 UINT64_C(0),
3187 UINT64_C(0),
3188 UINT64_C(0),
3189 UINT64_C(0),
3190 UINT64_C(0),
3191 UINT64_C(0),
3192 UINT64_C(0),
3193 UINT64_C(0),
3194 UINT64_C(0),
3195 UINT64_C(0),
3196 UINT64_C(0),
3197 UINT64_C(0),
3198 UINT64_C(0),
3199 UINT64_C(0),
3200 UINT64_C(0),
3201 UINT64_C(0),
3202 UINT64_C(0),
3203 UINT64_C(0),
3204 UINT64_C(0),
3205 UINT64_C(0),
3206 UINT64_C(0),
3207 UINT64_C(0),
3208 UINT64_C(0),
3209 UINT64_C(0),
3210 UINT64_C(0),
3211 UINT64_C(0),
3212 UINT64_C(0),
3213 UINT64_C(0),
3214 UINT64_C(0),
3215 UINT64_C(0),
3216 UINT64_C(0),
3217 UINT64_C(0),
3218 UINT64_C(0),
3219 UINT64_C(0),
3220 UINT64_C(0),
3221 UINT64_C(0),
3222 UINT64_C(0),
3223 UINT64_C(0),
3224 UINT64_C(0),
3225 UINT64_C(0),
3226 UINT64_C(0),
3227 UINT64_C(0),
3228 UINT64_C(0),
3229 UINT64_C(0),
3230 UINT64_C(0),
3231 UINT64_C(0),
3232 UINT64_C(0),
3233 UINT64_C(0),
3234 UINT64_C(0),
3235 UINT64_C(0),
3236 UINT64_C(0),
3237 UINT64_C(0),
3238 UINT64_C(0),
3239 UINT64_C(0),
3240 UINT64_C(0),
3241 UINT64_C(0),
3242 UINT64_C(0),
3243 UINT64_C(0),
3244 UINT64_C(0),
3245 UINT64_C(0),
3246 UINT64_C(0),
3247 UINT64_C(0),
3248 UINT64_C(0),
3249 UINT64_C(0),
3250 UINT64_C(0),
3251 UINT64_C(0),
3252 UINT64_C(0),
3253 UINT64_C(0),
3254 UINT64_C(0),
3255 UINT64_C(0),
3256 UINT64_C(0),
3257 UINT64_C(0),
3258 UINT64_C(0),
3259 UINT64_C(0),
3260 UINT64_C(0),
3261 UINT64_C(0),
3262 UINT64_C(0),
3263 UINT64_C(0),
3264 UINT64_C(0),
3265 UINT64_C(0),
3266 UINT64_C(0),
3267 UINT64_C(0),
3268 UINT64_C(0),
3269 UINT64_C(0),
3270 UINT64_C(0),
3271 UINT64_C(0),
3272 UINT64_C(0),
3273 UINT64_C(0),
3274 UINT64_C(0),
3275 UINT64_C(0),
3276 UINT64_C(0),
3277 UINT64_C(0),
3278 UINT64_C(0),
3279 UINT64_C(0),
3280 UINT64_C(0),
3281 UINT64_C(0),
3282 UINT64_C(0),
3283 UINT64_C(0),
3284 UINT64_C(0),
3285 UINT64_C(0),
3286 UINT64_C(0),
3287 UINT64_C(0),
3288 UINT64_C(0),
3289 UINT64_C(0),
3290 UINT64_C(0),
3291 UINT64_C(0),
3292 UINT64_C(0),
3293 UINT64_C(0),
3294 UINT64_C(0),
3295 UINT64_C(0),
3296 UINT64_C(0),
3297 UINT64_C(0),
3298 UINT64_C(0),
3299 UINT64_C(0),
3300 UINT64_C(0),
3301 UINT64_C(0),
3302 UINT64_C(0),
3303 UINT64_C(0),
3304 UINT64_C(0),
3305 UINT64_C(0),
3306 UINT64_C(0),
3307 UINT64_C(0),
3308 UINT64_C(0),
3309 UINT64_C(0),
3310 UINT64_C(0),
3311 UINT64_C(0),
3312 UINT64_C(0),
3313 UINT64_C(0),
3314 UINT64_C(0),
3315 UINT64_C(0),
3316 UINT64_C(0),
3317 UINT64_C(0),
3318 UINT64_C(0),
3319 UINT64_C(0),
3320 UINT64_C(0),
3321 UINT64_C(0),
3322 UINT64_C(0),
3323 UINT64_C(0),
3324 UINT64_C(0),
3325 UINT64_C(0),
3326 UINT64_C(0),
3327 UINT64_C(0),
3328 UINT64_C(0),
3329 UINT64_C(0),
3330 UINT64_C(0),
3331 UINT64_C(0),
3332 UINT64_C(0),
3333 UINT64_C(0),
3334 UINT64_C(0),
3335 UINT64_C(0),
3336 UINT64_C(0),
3337 UINT64_C(0),
3338 UINT64_C(0),
3339 UINT64_C(0),
3340 UINT64_C(0),
3341 UINT64_C(0),
3342 UINT64_C(0),
3343 UINT64_C(0),
3344 UINT64_C(0),
3345 UINT64_C(0),
3346 UINT64_C(0),
3347 UINT64_C(0),
3348 UINT64_C(0),
3349 UINT64_C(0),
3350 UINT64_C(0),
3351 UINT64_C(0),
3352 UINT64_C(0),
3353 UINT64_C(0),
3354 UINT64_C(0),
3355 UINT64_C(0),
3356 UINT64_C(0),
3357 UINT64_C(0),
3358 UINT64_C(0),
3359 UINT64_C(0),
3360 UINT64_C(0),
3361 UINT64_C(0),
3362 UINT64_C(0),
3363 UINT64_C(0),
3364 UINT64_C(0),
3365 UINT64_C(0),
3366 UINT64_C(0),
3367 UINT64_C(0),
3368 UINT64_C(0),
3369 UINT64_C(0),
3370 UINT64_C(0),
3371 UINT64_C(0),
3372 UINT64_C(0),
3373 UINT64_C(0),
3374 UINT64_C(0),
3375 UINT64_C(0),
3376 UINT64_C(0),
3377 UINT64_C(0),
3378 UINT64_C(0),
3379 UINT64_C(0),
3380 UINT64_C(0),
3381 UINT64_C(0),
3382 UINT64_C(0),
3383 UINT64_C(0),
3384 UINT64_C(0),
3385 UINT64_C(0),
3386 UINT64_C(0),
3387 UINT64_C(0),
3388 UINT64_C(0),
3389 UINT64_C(0),
3390 UINT64_C(0),
3391 UINT64_C(0),
3392 UINT64_C(0),
3393 UINT64_C(0),
3394 UINT64_C(0),
3395 UINT64_C(0),
3396 UINT64_C(0),
3397 UINT64_C(0),
3398 UINT64_C(0),
3399 UINT64_C(0),
3400 UINT64_C(0),
3401 UINT64_C(0),
3402 UINT64_C(0),
3403 UINT64_C(0),
3404 UINT64_C(0),
3405 UINT64_C(0),
3406 UINT64_C(0),
3407 UINT64_C(0),
3408 UINT64_C(0),
3409 UINT64_C(0),
3410 UINT64_C(0),
3411 UINT64_C(0),
3412 UINT64_C(0),
3413 UINT64_C(0),
3414 UINT64_C(0),
3415 UINT64_C(0),
3416 UINT64_C(0),
3417 UINT64_C(0),
3418 UINT64_C(0),
3419 UINT64_C(0),
3420 UINT64_C(0),
3421 UINT64_C(0),
3422 UINT64_C(0),
3423 UINT64_C(0),
3424 UINT64_C(0),
3425 UINT64_C(0),
3426 UINT64_C(0),
3427 UINT64_C(0),
3428 UINT64_C(0),
3429 UINT64_C(0),
3430 UINT64_C(0),
3431 UINT64_C(0),
3432 UINT64_C(0),
3433 UINT64_C(0),
3434 UINT64_C(0),
3435 UINT64_C(0),
3436 UINT64_C(0),
3437 UINT64_C(0),
3438 UINT64_C(0),
3439 UINT64_C(0),
3440 UINT64_C(0),
3441 UINT64_C(0),
3442 UINT64_C(0),
3443 UINT64_C(0),
3444 UINT64_C(0),
3445 UINT64_C(0),
3446 UINT64_C(0),
3447 UINT64_C(0),
3448 UINT64_C(0),
3449 UINT64_C(0),
3450 UINT64_C(0),
3451 UINT64_C(0),
3452 UINT64_C(0),
3453 UINT64_C(0),
3454 UINT64_C(0),
3455 UINT64_C(0),
3456 UINT64_C(0),
3457 UINT64_C(0),
3458 UINT64_C(0),
3459 UINT64_C(0),
3460 UINT64_C(0),
3461 UINT64_C(0),
3462 UINT64_C(0),
3463 UINT64_C(0),
3464 UINT64_C(0),
3465 UINT64_C(0),
3466 UINT64_C(0),
3467 UINT64_C(0),
3468 UINT64_C(0),
3469 UINT64_C(0),
3470 UINT64_C(0),
3471 UINT64_C(0),
3472 UINT64_C(0),
3473 UINT64_C(0),
3474 UINT64_C(0),
3475 UINT64_C(0),
3476 UINT64_C(0),
3477 UINT64_C(0),
3478 UINT64_C(0),
3479 UINT64_C(0),
3480 UINT64_C(0),
3481 UINT64_C(0),
3482 UINT64_C(0),
3483 UINT64_C(0),
3484 UINT64_C(0),
3485 UINT64_C(0),
3486 UINT64_C(0),
3487 UINT64_C(0),
3488 UINT64_C(0),
3489 UINT64_C(0),
3490 UINT64_C(0),
3491 UINT64_C(0),
3492 UINT64_C(0),
3493 UINT64_C(0),
3494 UINT64_C(0),
3495 UINT64_C(0),
3496 UINT64_C(0),
3497 UINT64_C(0),
3498 UINT64_C(0),
3499 UINT64_C(0),
3500 UINT64_C(0),
3501 UINT64_C(0),
3502 UINT64_C(0),
3503 UINT64_C(0),
3504 UINT64_C(0),
3505 UINT64_C(0),
3506 UINT64_C(0),
3507 UINT64_C(0),
3508 UINT64_C(0),
3509 UINT64_C(0),
3510 UINT64_C(0),
3511 UINT64_C(0),
3512 UINT64_C(0),
3513 UINT64_C(0),
3514 UINT64_C(0),
3515 UINT64_C(0),
3516 UINT64_C(0),
3517 UINT64_C(0),
3518 UINT64_C(0),
3519 UINT64_C(0),
3520 UINT64_C(0),
3521 UINT64_C(0),
3522 UINT64_C(0),
3523 UINT64_C(0),
3524 UINT64_C(0),
3525 UINT64_C(0),
3526 UINT64_C(0),
3527 UINT64_C(0),
3528 UINT64_C(0),
3529 UINT64_C(0),
3530 UINT64_C(0),
3531 UINT64_C(0),
3532 UINT64_C(0),
3533 UINT64_C(0),
3534 UINT64_C(0),
3535 UINT64_C(0),
3536 UINT64_C(0),
3537 UINT64_C(0),
3538 UINT64_C(0),
3539 UINT64_C(0),
3540 UINT64_C(0),
3541 UINT64_C(0),
3542 UINT64_C(0),
3543 UINT64_C(0),
3544 UINT64_C(0),
3545 UINT64_C(0),
3546 UINT64_C(0),
3547 UINT64_C(0),
3548 UINT64_C(0),
3549 UINT64_C(0),
3550 UINT64_C(0),
3551 UINT64_C(0),
3552 UINT64_C(0),
3553 UINT64_C(0),
3554 UINT64_C(0),
3555 UINT64_C(0),
3556 UINT64_C(0),
3557 UINT64_C(0),
3558 UINT64_C(0),
3559 UINT64_C(0),
3560 UINT64_C(0),
3561 UINT64_C(0),
3562 UINT64_C(0),
3563 UINT64_C(0),
3564 UINT64_C(0),
3565 UINT64_C(0),
3566 UINT64_C(0),
3567 UINT64_C(0),
3568 UINT64_C(0),
3569 UINT64_C(0),
3570 UINT64_C(0),
3571 UINT64_C(0),
3572 UINT64_C(0),
3573 UINT64_C(0),
3574 UINT64_C(0),
3575 UINT64_C(0),
3576 UINT64_C(0),
3577 UINT64_C(0),
3578 UINT64_C(0),
3579 UINT64_C(0),
3580 UINT64_C(0),
3581 UINT64_C(0),
3582 UINT64_C(0),
3583 UINT64_C(0),
3584 UINT64_C(0),
3585 UINT64_C(0),
3586 UINT64_C(0),
3587 UINT64_C(0),
3588 UINT64_C(0),
3589 UINT64_C(0),
3590 UINT64_C(0),
3591 UINT64_C(0),
3592 UINT64_C(0),
3593 UINT64_C(0),
3594 UINT64_C(0),
3595 UINT64_C(0),
3596 UINT64_C(0),
3597 UINT64_C(0),
3598 UINT64_C(0),
3599 UINT64_C(0),
3600 UINT64_C(0),
3601 UINT64_C(0),
3602 UINT64_C(0),
3603 UINT64_C(0),
3604 UINT64_C(0),
3605 UINT64_C(0),
3606 UINT64_C(0),
3607 UINT64_C(0),
3608 UINT64_C(0),
3609 UINT64_C(0),
3610 UINT64_C(0),
3611 UINT64_C(0),
3612 UINT64_C(0),
3613 UINT64_C(0),
3614 UINT64_C(0),
3615 UINT64_C(0),
3616 UINT64_C(0),
3617 UINT64_C(0),
3618 UINT64_C(0),
3619 UINT64_C(0),
3620 UINT64_C(0),
3621 UINT64_C(0),
3622 UINT64_C(0),
3623 UINT64_C(0),
3624 UINT64_C(0),
3625 UINT64_C(0),
3626 UINT64_C(0),
3627 UINT64_C(0),
3628 UINT64_C(0),
3629 UINT64_C(0),
3630 UINT64_C(0),
3631 UINT64_C(0),
3632 UINT64_C(0),
3633 UINT64_C(0),
3634 UINT64_C(0),
3635 UINT64_C(0),
3636 UINT64_C(0),
3637 UINT64_C(0),
3638 UINT64_C(0),
3639 UINT64_C(0),
3640 UINT64_C(0),
3641 UINT64_C(0),
3642 UINT64_C(0),
3643 UINT64_C(0),
3644 UINT64_C(0),
3645 UINT64_C(0),
3646 UINT64_C(0),
3647 UINT64_C(0),
3648 UINT64_C(0),
3649 UINT64_C(0),
3650 UINT64_C(0),
3651 UINT64_C(0),
3652 UINT64_C(0),
3653 UINT64_C(0),
3654 UINT64_C(0),
3655 UINT64_C(0),
3656 UINT64_C(0),
3657 UINT64_C(0),
3658 UINT64_C(0),
3659 UINT64_C(0),
3660 UINT64_C(0),
3661 UINT64_C(0),
3662 UINT64_C(0),
3663 UINT64_C(0),
3664 UINT64_C(0),
3665 UINT64_C(0),
3666 UINT64_C(0),
3667 UINT64_C(0),
3668 UINT64_C(0),
3669 UINT64_C(0),
3670 UINT64_C(0),
3671 UINT64_C(0),
3672 UINT64_C(0),
3673 UINT64_C(0),
3674 UINT64_C(0),
3675 UINT64_C(0),
3676 UINT64_C(0),
3677 UINT64_C(0),
3678 UINT64_C(0),
3679 UINT64_C(0),
3680 UINT64_C(0),
3681 UINT64_C(0),
3682 UINT64_C(0),
3683 UINT64_C(0),
3684 UINT64_C(0),
3685 UINT64_C(0),
3686 UINT64_C(0),
3687 UINT64_C(0),
3688 UINT64_C(0),
3689 UINT64_C(0),
3690 UINT64_C(0),
3691 UINT64_C(0),
3692 UINT64_C(0),
3693 UINT64_C(0),
3694 UINT64_C(0),
3695 UINT64_C(0),
3696 UINT64_C(0),
3697 UINT64_C(0),
3698 UINT64_C(0),
3699 UINT64_C(0),
3700 UINT64_C(0),
3701 UINT64_C(0),
3702 UINT64_C(0),
3703 UINT64_C(0),
3704 UINT64_C(0),
3705 UINT64_C(0),
3706 UINT64_C(0),
3707 UINT64_C(0),
3708 UINT64_C(0),
3709 UINT64_C(0),
3710 UINT64_C(0),
3711 UINT64_C(0),
3712 UINT64_C(0),
3713 UINT64_C(0),
3714 UINT64_C(0),
3715 UINT64_C(0),
3716 UINT64_C(0),
3717 UINT64_C(0),
3718 UINT64_C(0),
3719 UINT64_C(0),
3720 UINT64_C(0),
3721 UINT64_C(0),
3722 UINT64_C(0),
3723 UINT64_C(0),
3724 UINT64_C(0),
3725 UINT64_C(0),
3726 UINT64_C(0),
3727 UINT64_C(0),
3728 UINT64_C(0),
3729 UINT64_C(0),
3730 UINT64_C(0),
3731 UINT64_C(0),
3732 UINT64_C(0),
3733 UINT64_C(0),
3734 UINT64_C(0),
3735 UINT64_C(0),
3736 UINT64_C(0),
3737 UINT64_C(0),
3738 UINT64_C(0),
3739 UINT64_C(0),
3740 UINT64_C(0),
3741 UINT64_C(0),
3742 UINT64_C(0),
3743 UINT64_C(0),
3744 UINT64_C(0),
3745 UINT64_C(0),
3746 UINT64_C(0),
3747 UINT64_C(0),
3748 UINT64_C(0),
3749 UINT64_C(0),
3750 UINT64_C(0),
3751 UINT64_C(0),
3752 UINT64_C(0),
3753 UINT64_C(0),
3754 UINT64_C(0),
3755 UINT64_C(0),
3756 UINT64_C(0),
3757 UINT64_C(0),
3758 UINT64_C(0),
3759 UINT64_C(0),
3760 UINT64_C(0),
3761 UINT64_C(0),
3762 UINT64_C(0),
3763 UINT64_C(0),
3764 UINT64_C(0),
3765 UINT64_C(0),
3766 UINT64_C(0),
3767 UINT64_C(0),
3768 UINT64_C(0),
3769 UINT64_C(0),
3770 UINT64_C(0),
3771 UINT64_C(0),
3772 UINT64_C(0),
3773 UINT64_C(0),
3774 UINT64_C(0),
3775 UINT64_C(0),
3776 UINT64_C(0),
3777 UINT64_C(0),
3778 UINT64_C(0),
3779 UINT64_C(0),
3780 UINT64_C(0),
3781 UINT64_C(0),
3782 UINT64_C(0),
3783 UINT64_C(0),
3784 UINT64_C(0),
3785 UINT64_C(0),
3786 UINT64_C(0),
3787 UINT64_C(0),
3788 UINT64_C(0),
3789 UINT64_C(0),
3790 UINT64_C(0),
3791 UINT64_C(0),
3792 UINT64_C(0),
3793 UINT64_C(0),
3794 UINT64_C(0),
3795 UINT64_C(0),
3796 UINT64_C(0),
3797 UINT64_C(0),
3798 UINT64_C(0),
3799 UINT64_C(0),
3800 UINT64_C(0),
3801 UINT64_C(0),
3802 UINT64_C(0),
3803 UINT64_C(0),
3804 UINT64_C(0),
3805 UINT64_C(0),
3806 UINT64_C(0),
3807 UINT64_C(0),
3808 UINT64_C(0),
3809 UINT64_C(0),
3810 UINT64_C(0),
3811 UINT64_C(0),
3812 UINT64_C(0),
3813 UINT64_C(0),
3814 UINT64_C(0),
3815 UINT64_C(0),
3816 UINT64_C(0),
3817 UINT64_C(0),
3818 UINT64_C(0),
3819 UINT64_C(0),
3820 UINT64_C(0),
3821 UINT64_C(0),
3822 UINT64_C(0),
3823 UINT64_C(0),
3824 UINT64_C(0),
3825 UINT64_C(0),
3826 UINT64_C(0),
3827 UINT64_C(0),
3828 UINT64_C(0),
3829 UINT64_C(0),
3830 UINT64_C(0),
3831 UINT64_C(0),
3832 UINT64_C(0),
3833 UINT64_C(0),
3834 UINT64_C(0),
3835 UINT64_C(0),
3836 UINT64_C(0),
3837 UINT64_C(0),
3838 UINT64_C(0),
3839 UINT64_C(0),
3840 UINT64_C(0),
3841 UINT64_C(0),
3842 UINT64_C(0),
3843 UINT64_C(0),
3844 UINT64_C(0),
3845 UINT64_C(0),
3846 UINT64_C(0),
3847 UINT64_C(0),
3848 UINT64_C(0),
3849 UINT64_C(0),
3850 UINT64_C(0),
3851 UINT64_C(0),
3852 UINT64_C(0),
3853 UINT64_C(0),
3854 UINT64_C(0),
3855 UINT64_C(0),
3856 UINT64_C(0),
3857 UINT64_C(0),
3858 UINT64_C(0),
3859 UINT64_C(0),
3860 UINT64_C(0),
3861 UINT64_C(0),
3862 UINT64_C(0),
3863 UINT64_C(0),
3864 UINT64_C(0),
3865 UINT64_C(0),
3866 UINT64_C(0),
3867 UINT64_C(0),
3868 UINT64_C(0),
3869 UINT64_C(0),
3870 UINT64_C(0),
3871 UINT64_C(0),
3872 UINT64_C(0),
3873 UINT64_C(0),
3874 UINT64_C(0),
3875 UINT64_C(0),
3876 UINT64_C(0),
3877 UINT64_C(0),
3878 UINT64_C(0),
3879 UINT64_C(0),
3880 UINT64_C(0),
3881 UINT64_C(0),
3882 UINT64_C(0),
3883 UINT64_C(0),
3884 UINT64_C(0),
3885 UINT64_C(0),
3886 UINT64_C(0),
3887 UINT64_C(0),
3888 UINT64_C(0),
3889 UINT64_C(0),
3890 UINT64_C(0),
3891 UINT64_C(0),
3892 UINT64_C(0),
3893 UINT64_C(0),
3894 UINT64_C(0),
3895 UINT64_C(0),
3896 UINT64_C(0),
3897 UINT64_C(0),
3898 UINT64_C(0),
3899 UINT64_C(0),
3900 UINT64_C(0),
3901 UINT64_C(0),
3902 UINT64_C(0),
3903 UINT64_C(0),
3904 UINT64_C(0),
3905 UINT64_C(0),
3906 UINT64_C(0),
3907 UINT64_C(0),
3908 UINT64_C(0),
3909 UINT64_C(0),
3910 UINT64_C(0),
3911 UINT64_C(0),
3912 UINT64_C(0),
3913 UINT64_C(0),
3914 UINT64_C(0),
3915 UINT64_C(0),
3916 UINT64_C(0),
3917 UINT64_C(0),
3918 UINT64_C(0),
3919 UINT64_C(0),
3920 UINT64_C(0),
3921 UINT64_C(0),
3922 UINT64_C(0),
3923 UINT64_C(0),
3924 UINT64_C(0),
3925 UINT64_C(0),
3926 UINT64_C(0),
3927 UINT64_C(0),
3928 UINT64_C(0),
3929 UINT64_C(0),
3930 UINT64_C(0),
3931 UINT64_C(0),
3932 UINT64_C(0),
3933 UINT64_C(0),
3934 UINT64_C(0),
3935 UINT64_C(0),
3936 UINT64_C(0),
3937 UINT64_C(0),
3938 UINT64_C(0),
3939 UINT64_C(0),
3940 UINT64_C(0),
3941 UINT64_C(0),
3942 UINT64_C(0),
3943 UINT64_C(0),
3944 UINT64_C(0),
3945 UINT64_C(0),
3946 UINT64_C(0),
3947 UINT64_C(0),
3948 UINT64_C(0),
3949 UINT64_C(0),
3950 UINT64_C(0),
3951 UINT64_C(0),
3952 UINT64_C(0),
3953 UINT64_C(0),
3954 UINT64_C(0),
3955 UINT64_C(0),
3956 UINT64_C(0),
3957 UINT64_C(0),
3958 UINT64_C(0),
3959 UINT64_C(0),
3960 UINT64_C(0),
3961 UINT64_C(0),
3962 UINT64_C(0),
3963 UINT64_C(0),
3964 UINT64_C(0),
3965 UINT64_C(0),
3966 UINT64_C(0),
3967 UINT64_C(0),
3968 UINT64_C(0),
3969 UINT64_C(0),
3970 UINT64_C(0),
3971 UINT64_C(0),
3972 UINT64_C(0),
3973 UINT64_C(0),
3974 UINT64_C(0),
3975 UINT64_C(0),
3976 UINT64_C(0),
3977 UINT64_C(0),
3978 UINT64_C(0),
3979 UINT64_C(0),
3980 UINT64_C(0),
3981 UINT64_C(0),
3982 UINT64_C(0),
3983 UINT64_C(0),
3984 UINT64_C(0),
3985 UINT64_C(0),
3986 UINT64_C(0),
3987 UINT64_C(0),
3988 UINT64_C(0),
3989 UINT64_C(0),
3990 UINT64_C(0),
3991 UINT64_C(0),
3992 UINT64_C(0),
3993 UINT64_C(0),
3994 UINT64_C(0),
3995 UINT64_C(0),
3996 UINT64_C(0),
3997 UINT64_C(0),
3998 UINT64_C(0),
3999 UINT64_C(0),
4000 UINT64_C(0),
4001 UINT64_C(0),
4002 UINT64_C(0),
4003 UINT64_C(0),
4004 UINT64_C(0),
4005 UINT64_C(0),
4006 UINT64_C(0),
4007 UINT64_C(0),
4008 UINT64_C(0),
4009 UINT64_C(0),
4010 UINT64_C(0),
4011 UINT64_C(0),
4012 UINT64_C(0),
4013 UINT64_C(0),
4014 UINT64_C(0),
4015 UINT64_C(0),
4016 UINT64_C(0),
4017 UINT64_C(0),
4018 UINT64_C(0),
4019 UINT64_C(0),
4020 UINT64_C(0),
4021 UINT64_C(0),
4022 UINT64_C(0),
4023 UINT64_C(0),
4024 UINT64_C(0),
4025 UINT64_C(0),
4026 UINT64_C(0),
4027 UINT64_C(0),
4028 UINT64_C(0),
4029 UINT64_C(0),
4030 UINT64_C(0),
4031 UINT64_C(0),
4032 UINT64_C(0),
4033 UINT64_C(0),
4034 UINT64_C(0),
4035 UINT64_C(0),
4036 UINT64_C(0),
4037 UINT64_C(0),
4038 UINT64_C(0),
4039 UINT64_C(0),
4040 UINT64_C(0),
4041 UINT64_C(0),
4042 UINT64_C(0),
4043 UINT64_C(0),
4044 UINT64_C(0),
4045 UINT64_C(0),
4046 UINT64_C(0),
4047 UINT64_C(0),
4048 UINT64_C(0),
4049 UINT64_C(0),
4050 UINT64_C(0),
4051 UINT64_C(0),
4052 UINT64_C(0),
4053 UINT64_C(0),
4054 UINT64_C(0),
4055 UINT64_C(0),
4056 UINT64_C(0),
4057 UINT64_C(0),
4058 UINT64_C(0),
4059 UINT64_C(0),
4060 UINT64_C(0),
4061 UINT64_C(0),
4062 UINT64_C(0),
4063 UINT64_C(0),
4064 UINT64_C(0),
4065 UINT64_C(0),
4066 UINT64_C(0),
4067 UINT64_C(0),
4068 UINT64_C(0),
4069 UINT64_C(0),
4070 UINT64_C(0),
4071 UINT64_C(0),
4072 UINT64_C(0),
4073 UINT64_C(0),
4074 UINT64_C(0),
4075 UINT64_C(0),
4076 UINT64_C(0),
4077 UINT64_C(0),
4078 UINT64_C(0),
4079 UINT64_C(0),
4080 UINT64_C(0),
4081 UINT64_C(0),
4082 UINT64_C(0),
4083 UINT64_C(0),
4084 UINT64_C(0),
4085 UINT64_C(0),
4086 UINT64_C(0),
4087 UINT64_C(0),
4088 UINT64_C(0),
4089 UINT64_C(0),
4090 UINT64_C(0),
4091 UINT64_C(0),
4092 UINT64_C(0),
4093 UINT64_C(0),
4094 UINT64_C(0),
4095 UINT64_C(0),
4096 UINT64_C(0),
4097 UINT64_C(0),
4098 UINT64_C(0),
4099 UINT64_C(0),
4100 UINT64_C(0),
4101 UINT64_C(0),
4102 UINT64_C(0),
4103 UINT64_C(0),
4104 UINT64_C(0),
4105 UINT64_C(0),
4106 UINT64_C(0),
4107 UINT64_C(0),
4108 UINT64_C(0),
4109 UINT64_C(0),
4110 UINT64_C(0),
4111 UINT64_C(0),
4112 UINT64_C(0),
4113 UINT64_C(0),
4114 UINT64_C(0),
4115 UINT64_C(0),
4116 UINT64_C(0),
4117 UINT64_C(0),
4118 UINT64_C(0),
4119 UINT64_C(0),
4120 UINT64_C(0),
4121 UINT64_C(0),
4122 UINT64_C(0),
4123 UINT64_C(0),
4124 UINT64_C(0),
4125 UINT64_C(0),
4126 UINT64_C(0),
4127 UINT64_C(0),
4128 UINT64_C(0),
4129 UINT64_C(0),
4130 UINT64_C(0),
4131 UINT64_C(0),
4132 UINT64_C(0),
4133 UINT64_C(0),
4134 UINT64_C(0),
4135 UINT64_C(0),
4136 UINT64_C(0),
4137 UINT64_C(0),
4138 UINT64_C(0),
4139 UINT64_C(0),
4140 UINT64_C(0),
4141 UINT64_C(0),
4142 UINT64_C(0),
4143 UINT64_C(0),
4144 UINT64_C(0),
4145 UINT64_C(0),
4146 UINT64_C(0),
4147 UINT64_C(0),
4148 UINT64_C(0),
4149 UINT64_C(0),
4150 UINT64_C(0),
4151 UINT64_C(0),
4152 UINT64_C(0),
4153 UINT64_C(0),
4154 UINT64_C(0),
4155 UINT64_C(0),
4156 UINT64_C(0),
4157 UINT64_C(0),
4158 UINT64_C(0),
4159 UINT64_C(0),
4160 UINT64_C(0),
4161 UINT64_C(0),
4162 UINT64_C(0),
4163 UINT64_C(0),
4164 UINT64_C(0),
4165 UINT64_C(0),
4166 UINT64_C(0),
4167 UINT64_C(0),
4168 UINT64_C(0),
4169 UINT64_C(0),
4170 UINT64_C(0),
4171 UINT64_C(0),
4172 UINT64_C(0),
4173 UINT64_C(0),
4174 UINT64_C(0),
4175 UINT64_C(0),
4176 UINT64_C(0),
4177 UINT64_C(0),
4178 UINT64_C(0),
4179 UINT64_C(0),
4180 UINT64_C(0),
4181 UINT64_C(0),
4182 UINT64_C(0),
4183 UINT64_C(0),
4184 UINT64_C(0),
4185 UINT64_C(0),
4186 UINT64_C(0),
4187 UINT64_C(0),
4188 UINT64_C(0),
4189 UINT64_C(0),
4190 UINT64_C(0),
4191 UINT64_C(0),
4192 UINT64_C(0),
4193 UINT64_C(0),
4194 UINT64_C(0),
4195 UINT64_C(0),
4196 UINT64_C(0),
4197 UINT64_C(0),
4198 UINT64_C(0),
4199 UINT64_C(0),
4200 UINT64_C(0),
4201 UINT64_C(0),
4202 UINT64_C(0),
4203 UINT64_C(0),
4204 UINT64_C(0),
4205 UINT64_C(0),
4206 UINT64_C(0),
4207 UINT64_C(0),
4208 UINT64_C(0),
4209 UINT64_C(0),
4210 UINT64_C(0),
4211 UINT64_C(0),
4212 UINT64_C(0),
4213 UINT64_C(0),
4214 UINT64_C(0),
4215 UINT64_C(0),
4216 UINT64_C(0),
4217 UINT64_C(0),
4218 UINT64_C(0),
4219 UINT64_C(0),
4220 UINT64_C(0),
4221 UINT64_C(0),
4222 UINT64_C(0),
4223 UINT64_C(0),
4224 UINT64_C(0),
4225 UINT64_C(0),
4226 UINT64_C(0),
4227 UINT64_C(0),
4228 UINT64_C(0),
4229 UINT64_C(0),
4230 UINT64_C(0),
4231 UINT64_C(0),
4232 UINT64_C(0),
4233 UINT64_C(0),
4234 UINT64_C(0),
4235 UINT64_C(0),
4236 UINT64_C(0),
4237 UINT64_C(0),
4238 UINT64_C(0),
4239 UINT64_C(0),
4240 UINT64_C(0),
4241 UINT64_C(0),
4242 UINT64_C(0),
4243 UINT64_C(0),
4244 UINT64_C(0),
4245 UINT64_C(0),
4246 UINT64_C(0),
4247 UINT64_C(0),
4248 UINT64_C(0),
4249 UINT64_C(0),
4250 UINT64_C(0),
4251 UINT64_C(0),
4252 UINT64_C(0),
4253 UINT64_C(0),
4254 UINT64_C(0),
4255 UINT64_C(0),
4256 UINT64_C(0),
4257 UINT64_C(0),
4258 UINT64_C(0),
4259 UINT64_C(0),
4260 UINT64_C(0),
4261 UINT64_C(0),
4262 UINT64_C(0),
4263 UINT64_C(0),
4264 UINT64_C(0),
4265 UINT64_C(0),
4266 UINT64_C(0),
4267 UINT64_C(0),
4268 UINT64_C(0),
4269 UINT64_C(0),
4270 UINT64_C(0),
4271 UINT64_C(0),
4272 UINT64_C(0),
4273 UINT64_C(0),
4274 UINT64_C(0),
4275 UINT64_C(0),
4276 UINT64_C(0),
4277 UINT64_C(0),
4278 UINT64_C(0),
4279 UINT64_C(0),
4280 UINT64_C(0),
4281 UINT64_C(0),
4282 UINT64_C(0),
4283 UINT64_C(0),
4284 UINT64_C(0),
4285 UINT64_C(0),
4286 UINT64_C(0),
4287 UINT64_C(0),
4288 UINT64_C(0),
4289 UINT64_C(0),
4290 UINT64_C(0),
4291 UINT64_C(0),
4292 UINT64_C(0),
4293 UINT64_C(0),
4294 UINT64_C(0),
4295 UINT64_C(0),
4296 UINT64_C(0),
4297 UINT64_C(0),
4298 UINT64_C(0),
4299 UINT64_C(0),
4300 UINT64_C(0),
4301 UINT64_C(0),
4302 UINT64_C(0),
4303 UINT64_C(0),
4304 UINT64_C(0),
4305 UINT64_C(0),
4306 UINT64_C(0),
4307 UINT64_C(0),
4308 UINT64_C(0),
4309 UINT64_C(0),
4310 UINT64_C(0),
4311 UINT64_C(0),
4312 UINT64_C(0),
4313 UINT64_C(0),
4314 UINT64_C(0),
4315 UINT64_C(0),
4316 UINT64_C(0),
4317 UINT64_C(0),
4318 UINT64_C(0),
4319 UINT64_C(0),
4320 UINT64_C(0),
4321 UINT64_C(0),
4322 UINT64_C(0),
4323 UINT64_C(0),
4324 UINT64_C(0),
4325 UINT64_C(0),
4326 UINT64_C(0),
4327 UINT64_C(0),
4328 UINT64_C(0),
4329 UINT64_C(0),
4330 UINT64_C(0),
4331 UINT64_C(0),
4332 UINT64_C(0),
4333 UINT64_C(0),
4334 UINT64_C(0),
4335 UINT64_C(0),
4336 UINT64_C(0),
4337 UINT64_C(0),
4338 UINT64_C(0),
4339 UINT64_C(0),
4340 UINT64_C(0),
4341 UINT64_C(0),
4342 UINT64_C(0),
4343 UINT64_C(0),
4344 UINT64_C(0),
4345 UINT64_C(0),
4346 UINT64_C(0),
4347 UINT64_C(0),
4348 UINT64_C(0),
4349 UINT64_C(0),
4350 UINT64_C(0),
4351 UINT64_C(0),
4352 UINT64_C(0),
4353 UINT64_C(0),
4354 UINT64_C(0),
4355 UINT64_C(0),
4356 UINT64_C(0),
4357 UINT64_C(0),
4358 UINT64_C(0),
4359 UINT64_C(0),
4360 UINT64_C(0),
4361 UINT64_C(0),
4362 UINT64_C(0),
4363 UINT64_C(0),
4364 UINT64_C(0),
4365 UINT64_C(0),
4366 UINT64_C(0),
4367 UINT64_C(0),
4368 UINT64_C(0),
4369 UINT64_C(0),
4370 UINT64_C(0),
4371 UINT64_C(0),
4372 UINT64_C(0),
4373 UINT64_C(0),
4374 UINT64_C(0),
4375 UINT64_C(0),
4376 UINT64_C(0),
4377 UINT64_C(0),
4378 UINT64_C(0),
4379 UINT64_C(0),
4380 UINT64_C(0),
4381 UINT64_C(0),
4382 UINT64_C(0),
4383 UINT64_C(0),
4384 UINT64_C(0),
4385 UINT64_C(0),
4386 UINT64_C(0),
4387 UINT64_C(0),
4388 UINT64_C(0),
4389 UINT64_C(0),
4390 UINT64_C(0),
4391 UINT64_C(0),
4392 UINT64_C(0),
4393 UINT64_C(0),
4394 UINT64_C(0),
4395 UINT64_C(0),
4396 UINT64_C(0),
4397 UINT64_C(0),
4398 UINT64_C(0),
4399 UINT64_C(0),
4400 UINT64_C(0),
4401 UINT64_C(0),
4402 UINT64_C(0),
4403 UINT64_C(0),
4404 UINT64_C(0),
4405 UINT64_C(0),
4406 UINT64_C(0),
4407 UINT64_C(0),
4408 UINT64_C(0),
4409 UINT64_C(0),
4410 UINT64_C(0),
4411 UINT64_C(0),
4412 UINT64_C(0),
4413 UINT64_C(0),
4414 UINT64_C(0),
4415 UINT64_C(0),
4416 UINT64_C(0),
4417 UINT64_C(0),
4418 UINT64_C(0),
4419 UINT64_C(0),
4420 UINT64_C(0),
4421 UINT64_C(0),
4422 UINT64_C(0),
4423 UINT64_C(0),
4424 UINT64_C(0),
4425 UINT64_C(0),
4426 UINT64_C(0),
4427 UINT64_C(0),
4428 UINT64_C(0),
4429 UINT64_C(0),
4430 UINT64_C(0),
4431 UINT64_C(0),
4432 UINT64_C(0),
4433 UINT64_C(0),
4434 UINT64_C(0),
4435 UINT64_C(0),
4436 UINT64_C(0),
4437 UINT64_C(0),
4438 UINT64_C(0),
4439 UINT64_C(0),
4440 UINT64_C(0),
4441 UINT64_C(0),
4442 UINT64_C(0),
4443 UINT64_C(0),
4444 UINT64_C(0),
4445 UINT64_C(0),
4446 UINT64_C(0),
4447 UINT64_C(0),
4448 UINT64_C(0),
4449 UINT64_C(0),
4450 UINT64_C(0),
4451 UINT64_C(0),
4452 UINT64_C(0),
4453 UINT64_C(0),
4454 UINT64_C(0),
4455 UINT64_C(0),
4456 UINT64_C(0),
4457 UINT64_C(0),
4458 UINT64_C(0),
4459 UINT64_C(0),
4460 UINT64_C(0),
4461 UINT64_C(0),
4462 UINT64_C(0),
4463 UINT64_C(0),
4464 UINT64_C(0),
4465 UINT64_C(0),
4466 UINT64_C(0),
4467 UINT64_C(0),
4468 UINT64_C(0),
4469 UINT64_C(0),
4470 UINT64_C(0),
4471 UINT64_C(0),
4472 UINT64_C(0),
4473 UINT64_C(0),
4474 UINT64_C(0),
4475 UINT64_C(0),
4476 UINT64_C(0),
4477 UINT64_C(0),
4478 UINT64_C(0),
4479 UINT64_C(0),
4480 UINT64_C(0),
4481 UINT64_C(0),
4482 UINT64_C(0),
4483 UINT64_C(0),
4484 UINT64_C(0),
4485 UINT64_C(0),
4486 UINT64_C(0),
4487 UINT64_C(0),
4488 UINT64_C(0),
4489 UINT64_C(0),
4490 UINT64_C(0),
4491 UINT64_C(0),
4492 UINT64_C(0),
4493 UINT64_C(0),
4494 UINT64_C(0),
4495 UINT64_C(0),
4496 UINT64_C(0),
4497 UINT64_C(0),
4498 UINT64_C(0),
4499 UINT64_C(0),
4500 UINT64_C(0),
4501 UINT64_C(0),
4502 UINT64_C(0),
4503 UINT64_C(0),
4504 UINT64_C(0),
4505 UINT64_C(0),
4506 UINT64_C(0),
4507 UINT64_C(0),
4508 UINT64_C(0),
4509 UINT64_C(0),
4510 UINT64_C(0),
4511 UINT64_C(0),
4512 UINT64_C(0),
4513 UINT64_C(0),
4514 UINT64_C(0),
4515 UINT64_C(0),
4516 UINT64_C(0),
4517 UINT64_C(0),
4518 UINT64_C(0),
4519 UINT64_C(0),
4520 UINT64_C(0),
4521 UINT64_C(0),
4522 UINT64_C(0),
4523 UINT64_C(0),
4524 UINT64_C(0),
4525 UINT64_C(0),
4526 UINT64_C(0),
4527 UINT64_C(0),
4528 UINT64_C(0),
4529 UINT64_C(0),
4530 UINT64_C(0),
4531 UINT64_C(0),
4532 UINT64_C(0),
4533 UINT64_C(0),
4534 UINT64_C(0),
4535 UINT64_C(0),
4536 UINT64_C(0),
4537 UINT64_C(0),
4538 UINT64_C(0),
4539 UINT64_C(0),
4540 UINT64_C(0),
4541 UINT64_C(0),
4542 UINT64_C(0),
4543 UINT64_C(0),
4544 UINT64_C(0),
4545 UINT64_C(0),
4546 UINT64_C(0),
4547 UINT64_C(0),
4548 UINT64_C(0),
4549 UINT64_C(0),
4550 UINT64_C(0),
4551 UINT64_C(0),
4552 UINT64_C(0),
4553 UINT64_C(0),
4554 UINT64_C(0),
4555 UINT64_C(0),
4556 UINT64_C(0),
4557 UINT64_C(0),
4558 UINT64_C(0),
4559 UINT64_C(0),
4560 UINT64_C(0),
4561 UINT64_C(0),
4562 UINT64_C(0),
4563 UINT64_C(0),
4564 UINT64_C(0),
4565 UINT64_C(0),
4566 UINT64_C(0),
4567 UINT64_C(0),
4568 UINT64_C(0),
4569 UINT64_C(0),
4570 UINT64_C(0),
4571 UINT64_C(0),
4572 UINT64_C(0),
4573 UINT64_C(0),
4574 UINT64_C(0),
4575 UINT64_C(0),
4576 UINT64_C(0),
4577 UINT64_C(0),
4578 UINT64_C(0),
4579 UINT64_C(0),
4580 UINT64_C(0),
4581 UINT64_C(0),
4582 UINT64_C(0),
4583 UINT64_C(0),
4584 UINT64_C(0),
4585 UINT64_C(0),
4586 UINT64_C(0),
4587 UINT64_C(0),
4588 UINT64_C(0),
4589 UINT64_C(0),
4590 UINT64_C(0),
4591 UINT64_C(0),
4592 UINT64_C(0),
4593 UINT64_C(0),
4594 UINT64_C(0),
4595 UINT64_C(0),
4596 UINT64_C(0),
4597 UINT64_C(0),
4598 UINT64_C(0),
4599 UINT64_C(0),
4600 UINT64_C(0),
4601 UINT64_C(0),
4602 UINT64_C(0),
4603 UINT64_C(0),
4604 UINT64_C(0),
4605 UINT64_C(0),
4606 UINT64_C(0),
4607 UINT64_C(0),
4608 UINT64_C(0),
4609 UINT64_C(0),
4610 UINT64_C(0),
4611 UINT64_C(0),
4612 UINT64_C(0),
4613 UINT64_C(0),
4614 UINT64_C(0),
4615 UINT64_C(0),
4616 UINT64_C(0),
4617 UINT64_C(0),
4618 UINT64_C(0),
4619 UINT64_C(0),
4620 UINT64_C(0),
4621 UINT64_C(0),
4622 UINT64_C(0),
4623 UINT64_C(0),
4624 UINT64_C(0),
4625 UINT64_C(0),
4626 UINT64_C(0),
4627 UINT64_C(0),
4628 UINT64_C(0),
4629 UINT64_C(0),
4630 UINT64_C(0),
4631 UINT64_C(0),
4632 UINT64_C(0),
4633 UINT64_C(0),
4634 UINT64_C(0),
4635 UINT64_C(0),
4636 UINT64_C(0),
4637 UINT64_C(0),
4638 UINT64_C(0),
4639 UINT64_C(0),
4640 UINT64_C(0),
4641 UINT64_C(0),
4642 UINT64_C(0),
4643 UINT64_C(0),
4644 UINT64_C(0),
4645 UINT64_C(0),
4646 UINT64_C(0),
4647 UINT64_C(0),
4648 UINT64_C(0),
4649 UINT64_C(0),
4650 UINT64_C(0),
4651 UINT64_C(0),
4652 UINT64_C(0),
4653 UINT64_C(0),
4654 UINT64_C(0),
4655 UINT64_C(0),
4656 UINT64_C(0),
4657 UINT64_C(0),
4658 UINT64_C(0),
4659 UINT64_C(0),
4660 UINT64_C(0),
4661 UINT64_C(0),
4662 UINT64_C(0),
4663 UINT64_C(0),
4664 UINT64_C(0),
4665 UINT64_C(0),
4666 UINT64_C(0),
4667 UINT64_C(0),
4668 UINT64_C(0),
4669 UINT64_C(0),
4670 UINT64_C(0),
4671 UINT64_C(0),
4672 UINT64_C(0),
4673 UINT64_C(0),
4674 UINT64_C(0),
4675 UINT64_C(0),
4676 UINT64_C(0),
4677 UINT64_C(0),
4678 UINT64_C(0),
4679 UINT64_C(0),
4680 UINT64_C(0),
4681 UINT64_C(0),
4682 UINT64_C(0),
4683 UINT64_C(0),
4684 UINT64_C(0),
4685 UINT64_C(0),
4686 UINT64_C(0),
4687 UINT64_C(0),
4688 UINT64_C(0),
4689 UINT64_C(0),
4690 UINT64_C(0),
4691 UINT64_C(0),
4692 UINT64_C(0),
4693 UINT64_C(0),
4694 UINT64_C(0),
4695 UINT64_C(0),
4696 UINT64_C(0),
4697 UINT64_C(0),
4698 UINT64_C(0),
4699 UINT64_C(0),
4700 UINT64_C(0),
4701 UINT64_C(0),
4702 UINT64_C(0),
4703 UINT64_C(0),
4704 UINT64_C(0),
4705 UINT64_C(0),
4706 UINT64_C(0),
4707 UINT64_C(0),
4708 UINT64_C(0),
4709 UINT64_C(0),
4710 UINT64_C(0),
4711 UINT64_C(0),
4712 UINT64_C(0),
4713 UINT64_C(0),
4714 UINT64_C(0),
4715 UINT64_C(0),
4716 UINT64_C(0),
4717 UINT64_C(0),
4718 UINT64_C(0),
4719 UINT64_C(0),
4720 UINT64_C(0),
4721 UINT64_C(0),
4722 UINT64_C(0),
4723 UINT64_C(0),
4724 UINT64_C(0),
4725 UINT64_C(0),
4726 UINT64_C(0),
4727 UINT64_C(0),
4728 UINT64_C(0),
4729 UINT64_C(0),
4730 UINT64_C(0),
4731 UINT64_C(0),
4732 UINT64_C(0),
4733 UINT64_C(0),
4734 UINT64_C(0),
4735 UINT64_C(0),
4736 UINT64_C(0),
4737 UINT64_C(0),
4738 UINT64_C(0),
4739 UINT64_C(0),
4740 UINT64_C(0),
4741 UINT64_C(0),
4742 UINT64_C(0),
4743 UINT64_C(0),
4744 UINT64_C(0),
4745 UINT64_C(0),
4746 UINT64_C(0),
4747 UINT64_C(0),
4748 UINT64_C(0),
4749 UINT64_C(0),
4750 UINT64_C(0),
4751 UINT64_C(0),
4752 UINT64_C(0),
4753 UINT64_C(0),
4754 UINT64_C(0),
4755 UINT64_C(0),
4756 UINT64_C(0),
4757 UINT64_C(0),
4758 UINT64_C(0),
4759 UINT64_C(0),
4760 UINT64_C(0),
4761 UINT64_C(0),
4762 UINT64_C(0),
4763 UINT64_C(0),
4764 UINT64_C(0),
4765 UINT64_C(0),
4766 UINT64_C(0),
4767 UINT64_C(0),
4768 UINT64_C(0),
4769 UINT64_C(0),
4770 UINT64_C(0),
4771 UINT64_C(0),
4772 UINT64_C(0),
4773 UINT64_C(0),
4774 UINT64_C(0),
4775 UINT64_C(0),
4776 UINT64_C(0),
4777 UINT64_C(0),
4778 UINT64_C(0),
4779 UINT64_C(0),
4780 UINT64_C(0),
4781 UINT64_C(0),
4782 UINT64_C(0),
4783 UINT64_C(0),
4784 UINT64_C(0),
4785 UINT64_C(0),
4786 UINT64_C(0),
4787 UINT64_C(0),
4788 UINT64_C(0),
4789 UINT64_C(0),
4790 UINT64_C(0),
4791 UINT64_C(0),
4792 UINT64_C(0),
4793 UINT64_C(0),
4794 UINT64_C(0),
4795 UINT64_C(0),
4796 UINT64_C(0),
4797 UINT64_C(0),
4798 UINT64_C(0),
4799 UINT64_C(0),
4800 UINT64_C(0),
4801 UINT64_C(0),
4802 UINT64_C(0),
4803 UINT64_C(0),
4804 UINT64_C(0),
4805 UINT64_C(0),
4806 UINT64_C(0),
4807 UINT64_C(0),
4808 UINT64_C(0),
4809 UINT64_C(0),
4810 UINT64_C(0),
4811 UINT64_C(0),
4812 UINT64_C(0),
4813 UINT64_C(0),
4814 UINT64_C(0),
4815 UINT64_C(0),
4816 UINT64_C(0),
4817 UINT64_C(0),
4818 UINT64_C(0),
4819 UINT64_C(0),
4820 UINT64_C(0),
4821 UINT64_C(0),
4822 UINT64_C(0),
4823 UINT64_C(0),
4824 UINT64_C(0),
4825 UINT64_C(0),
4826 UINT64_C(0),
4827 UINT64_C(0),
4828 UINT64_C(0),
4829 UINT64_C(0),
4830 UINT64_C(0),
4831 UINT64_C(0),
4832 UINT64_C(0),
4833 UINT64_C(0),
4834 UINT64_C(0),
4835 UINT64_C(0),
4836 UINT64_C(0),
4837 UINT64_C(0),
4838 UINT64_C(0),
4839 UINT64_C(0),
4840 UINT64_C(0),
4841 UINT64_C(0),
4842 UINT64_C(0),
4843 UINT64_C(0),
4844 UINT64_C(0),
4845 UINT64_C(0),
4846 UINT64_C(0),
4847 UINT64_C(0),
4848 UINT64_C(0),
4849 UINT64_C(0),
4850 UINT64_C(0),
4851 UINT64_C(0),
4852 UINT64_C(0),
4853 UINT64_C(0),
4854 UINT64_C(0),
4855 UINT64_C(0),
4856 UINT64_C(0),
4857 UINT64_C(0),
4858 UINT64_C(0),
4859 UINT64_C(0),
4860 UINT64_C(0),
4861 UINT64_C(0),
4862 UINT64_C(0),
4863 UINT64_C(0),
4864 UINT64_C(0),
4865 UINT64_C(0),
4866 UINT64_C(0),
4867 UINT64_C(0),
4868 UINT64_C(0),
4869 UINT64_C(0),
4870 UINT64_C(0),
4871 UINT64_C(0),
4872 UINT64_C(0),
4873 UINT64_C(0),
4874 UINT64_C(0),
4875 UINT64_C(0),
4876 UINT64_C(0),
4877 UINT64_C(0),
4878 UINT64_C(0),
4879 UINT64_C(0),
4880 UINT64_C(0),
4881 UINT64_C(0),
4882 UINT64_C(0),
4883 UINT64_C(0),
4884 UINT64_C(0),
4885 UINT64_C(0),
4886 UINT64_C(0),
4887 UINT64_C(0),
4888 UINT64_C(0),
4889 UINT64_C(0),
4890 UINT64_C(0),
4891 UINT64_C(0),
4892 UINT64_C(0),
4893 UINT64_C(0),
4894 UINT64_C(0),
4895 UINT64_C(0),
4896 UINT64_C(0),
4897 UINT64_C(0),
4898 UINT64_C(0),
4899 UINT64_C(0),
4900 UINT64_C(0),
4901 UINT64_C(0),
4902 UINT64_C(0),
4903 UINT64_C(0),
4904 UINT64_C(0),
4905 UINT64_C(0),
4906 UINT64_C(0),
4907 UINT64_C(0),
4908 UINT64_C(0),
4909 UINT64_C(0),
4910 UINT64_C(0),
4911 UINT64_C(0),
4912 UINT64_C(0),
4913 UINT64_C(0),
4914 UINT64_C(0),
4915 UINT64_C(0),
4916 UINT64_C(0),
4917 UINT64_C(0),
4918 UINT64_C(0),
4919 UINT64_C(0),
4920 UINT64_C(0),
4921 UINT64_C(0),
4922 UINT64_C(0),
4923 UINT64_C(0),
4924 UINT64_C(0),
4925 UINT64_C(0),
4926 UINT64_C(0),
4927 UINT64_C(0),
4928 UINT64_C(0),
4929 UINT64_C(0),
4930 UINT64_C(0),
4931 UINT64_C(0),
4932 UINT64_C(0),
4933 UINT64_C(0),
4934 UINT64_C(0),
4935 UINT64_C(0),
4936 UINT64_C(0),
4937 UINT64_C(0),
4938 UINT64_C(0),
4939 UINT64_C(0),
4940 UINT64_C(0),
4941 UINT64_C(0),
4942 UINT64_C(0),
4943 UINT64_C(0),
4944 UINT64_C(0),
4945 UINT64_C(0),
4946 UINT64_C(0),
4947 UINT64_C(0),
4948 UINT64_C(0),
4949 UINT64_C(0),
4950 UINT64_C(0),
4951 UINT64_C(0),
4952 UINT64_C(0),
4953 UINT64_C(0),
4954 UINT64_C(0),
4955 UINT64_C(0),
4956 UINT64_C(0),
4957 UINT64_C(0),
4958 UINT64_C(0),
4959 UINT64_C(0),
4960 UINT64_C(0),
4961 UINT64_C(0),
4962 UINT64_C(0),
4963 UINT64_C(0),
4964 UINT64_C(0),
4965 UINT64_C(0),
4966 UINT64_C(0),
4967 UINT64_C(0),
4968 UINT64_C(0),
4969 UINT64_C(0),
4970 UINT64_C(0),
4971 UINT64_C(0),
4972 UINT64_C(0),
4973 UINT64_C(0),
4974 UINT64_C(0),
4975 UINT64_C(0),
4976 UINT64_C(0),
4977 UINT64_C(0),
4978 UINT64_C(0),
4979 UINT64_C(0),
4980 UINT64_C(0),
4981 UINT64_C(0),
4982 UINT64_C(0),
4983 UINT64_C(0),
4984 UINT64_C(0),
4985 UINT64_C(0),
4986 UINT64_C(0),
4987 UINT64_C(0),
4988 UINT64_C(0),
4989 UINT64_C(0),
4990 UINT64_C(0),
4991 UINT64_C(0),
4992 UINT64_C(0),
4993 UINT64_C(0),
4994 UINT64_C(0),
4995 UINT64_C(0),
4996 UINT64_C(0),
4997 UINT64_C(0),
4998 UINT64_C(0),
4999 UINT64_C(0),
5000 UINT64_C(0),
5001 UINT64_C(0),
5002 UINT64_C(0),
5003 UINT64_C(0),
5004 UINT64_C(0),
5005 UINT64_C(0),
5006 UINT64_C(0),
5007 UINT64_C(0),
5008 UINT64_C(0),
5009 UINT64_C(0),
5010 UINT64_C(0),
5011 UINT64_C(0),
5012 UINT64_C(0),
5013 UINT64_C(0),
5014 UINT64_C(0),
5015 UINT64_C(0),
5016 UINT64_C(0),
5017 UINT64_C(0),
5018 UINT64_C(0),
5019 UINT64_C(0),
5020 UINT64_C(0),
5021 UINT64_C(0),
5022 UINT64_C(0),
5023 UINT64_C(0),
5024 UINT64_C(0),
5025 UINT64_C(0),
5026 UINT64_C(0),
5027 UINT64_C(0),
5028 UINT64_C(0),
5029 UINT64_C(0),
5030 UINT64_C(0),
5031 UINT64_C(0),
5032 UINT64_C(0),
5033 UINT64_C(0),
5034 UINT64_C(0),
5035 UINT64_C(0),
5036 UINT64_C(0),
5037 UINT64_C(0),
5038 UINT64_C(0),
5039 UINT64_C(0),
5040 UINT64_C(0),
5041 UINT64_C(0),
5042 UINT64_C(0),
5043 UINT64_C(0),
5044 UINT64_C(0),
5045 UINT64_C(0),
5046 UINT64_C(0),
5047 UINT64_C(0),
5048 UINT64_C(0),
5049 UINT64_C(0),
5050 UINT64_C(0),
5051 UINT64_C(0),
5052 UINT64_C(0),
5053 UINT64_C(0),
5054 UINT64_C(0),
5055 UINT64_C(0),
5056 UINT64_C(0),
5057 UINT64_C(0),
5058 UINT64_C(0),
5059 UINT64_C(0),
5060 UINT64_C(0),
5061 UINT64_C(0),
5062 UINT64_C(0),
5063 UINT64_C(0),
5064 UINT64_C(0),
5065 UINT64_C(0),
5066 UINT64_C(0),
5067 UINT64_C(0),
5068 UINT64_C(0),
5069 UINT64_C(0),
5070 UINT64_C(0),
5071 UINT64_C(0),
5072 UINT64_C(0),
5073 UINT64_C(0),
5074 UINT64_C(0),
5075 UINT64_C(0),
5076 UINT64_C(0),
5077 UINT64_C(0),
5078 UINT64_C(0),
5079 UINT64_C(0),
5080 UINT64_C(0),
5081 UINT64_C(0),
5082 UINT64_C(0),
5083 UINT64_C(0),
5084 UINT64_C(0),
5085 UINT64_C(0),
5086 UINT64_C(0),
5087 UINT64_C(0),
5088 UINT64_C(0),
5089 UINT64_C(0),
5090 UINT64_C(0),
5091 UINT64_C(0),
5092 UINT64_C(0),
5093 UINT64_C(0),
5094 UINT64_C(0),
5095 UINT64_C(0),
5096 UINT64_C(0),
5097 UINT64_C(0),
5098 UINT64_C(0),
5099 UINT64_C(0),
5100 UINT64_C(0),
5101 UINT64_C(0),
5102 UINT64_C(0),
5103 UINT64_C(0),
5104 UINT64_C(0),
5105 UINT64_C(0),
5106 UINT64_C(0),
5107 UINT64_C(0),
5108 UINT64_C(0),
5109 UINT64_C(0),
5110 UINT64_C(0),
5111 UINT64_C(0),
5112 UINT64_C(0),
5113 UINT64_C(0),
5114 UINT64_C(0),
5115 UINT64_C(0),
5116 UINT64_C(0),
5117 UINT64_C(0),
5118 UINT64_C(0),
5119 UINT64_C(0),
5120 UINT64_C(0),
5121 UINT64_C(0),
5122 UINT64_C(0),
5123 UINT64_C(0),
5124 UINT64_C(0),
5125 UINT64_C(0),
5126 UINT64_C(0),
5127 UINT64_C(0),
5128 UINT64_C(0),
5129 UINT64_C(0),
5130 UINT64_C(0),
5131 UINT64_C(0),
5132 UINT64_C(0),
5133 UINT64_C(0),
5134 UINT64_C(0),
5135 UINT64_C(0),
5136 UINT64_C(0),
5137 UINT64_C(0),
5138 UINT64_C(0),
5139 UINT64_C(0),
5140 UINT64_C(0),
5141 UINT64_C(0),
5142 UINT64_C(0),
5143 UINT64_C(0),
5144 UINT64_C(0),
5145 UINT64_C(0),
5146 UINT64_C(0),
5147 UINT64_C(0),
5148 UINT64_C(0),
5149 UINT64_C(0),
5150 UINT64_C(0),
5151 UINT64_C(0),
5152 UINT64_C(0),
5153 UINT64_C(0),
5154 UINT64_C(0),
5155 UINT64_C(0),
5156 UINT64_C(0),
5157 UINT64_C(0),
5158 UINT64_C(0),
5159 UINT64_C(0),
5160 UINT64_C(0),
5161 UINT64_C(0),
5162 UINT64_C(0),
5163 UINT64_C(0),
5164 UINT64_C(0),
5165 UINT64_C(0),
5166 UINT64_C(0),
5167 UINT64_C(0),
5168 UINT64_C(0),
5169 UINT64_C(0),
5170 UINT64_C(0),
5171 UINT64_C(0),
5172 UINT64_C(0),
5173 UINT64_C(0),
5174 UINT64_C(0),
5175 UINT64_C(0),
5176 UINT64_C(0),
5177 UINT64_C(0),
5178 UINT64_C(0),
5179 UINT64_C(0),
5180 UINT64_C(0),
5181 UINT64_C(0),
5182 UINT64_C(0),
5183 UINT64_C(0),
5184 UINT64_C(0),
5185 UINT64_C(0),
5186 UINT64_C(0),
5187 UINT64_C(0),
5188 UINT64_C(0),
5189 UINT64_C(0),
5190 UINT64_C(0),
5191 UINT64_C(0),
5192 UINT64_C(0),
5193 UINT64_C(0),
5194 UINT64_C(0),
5195 UINT64_C(0),
5196 UINT64_C(0),
5197 UINT64_C(0),
5198 UINT64_C(0),
5199 UINT64_C(0),
5200 UINT64_C(0),
5201 UINT64_C(0),
5202 UINT64_C(0),
5203 UINT64_C(0),
5204 UINT64_C(0),
5205 UINT64_C(0),
5206 UINT64_C(0),
5207 UINT64_C(0),
5208 UINT64_C(0),
5209 UINT64_C(0),
5210 UINT64_C(0),
5211 UINT64_C(0),
5212 UINT64_C(0),
5213 UINT64_C(0),
5214 UINT64_C(0),
5215 UINT64_C(0),
5216 UINT64_C(0),
5217 UINT64_C(0),
5218 UINT64_C(0),
5219 UINT64_C(0),
5220 UINT64_C(0),
5221 UINT64_C(0),
5222 UINT64_C(0),
5223 UINT64_C(0),
5224 UINT64_C(0),
5225 UINT64_C(0),
5226 UINT64_C(0),
5227 UINT64_C(0),
5228 UINT64_C(0),
5229 UINT64_C(0),
5230 UINT64_C(0),
5231 UINT64_C(0),
5232 UINT64_C(0),
5233 UINT64_C(0),
5234 UINT64_C(0),
5235 UINT64_C(0),
5236 UINT64_C(0),
5237 UINT64_C(0),
5238 UINT64_C(0),
5239 UINT64_C(0),
5240 UINT64_C(0),
5241 UINT64_C(0),
5242 UINT64_C(0),
5243 UINT64_C(0),
5244 UINT64_C(0),
5245 UINT64_C(0),
5246 UINT64_C(0),
5247 UINT64_C(0),
5248 UINT64_C(0),
5249 UINT64_C(0),
5250 UINT64_C(0),
5251 UINT64_C(0),
5252 UINT64_C(0),
5253 UINT64_C(0),
5254 UINT64_C(0),
5255 UINT64_C(0),
5256 UINT64_C(0),
5257 UINT64_C(0),
5258 UINT64_C(0),
5259 UINT64_C(0),
5260 UINT64_C(0),
5261 UINT64_C(0),
5262 UINT64_C(0),
5263 UINT64_C(0),
5264 UINT64_C(0),
5265 UINT64_C(0),
5266 UINT64_C(0),
5267 UINT64_C(0),
5268 UINT64_C(0),
5269 UINT64_C(0),
5270 UINT64_C(0),
5271 UINT64_C(0),
5272 UINT64_C(0),
5273 UINT64_C(0),
5274 UINT64_C(0),
5275 UINT64_C(0),
5276 UINT64_C(0),
5277 UINT64_C(0),
5278 UINT64_C(0),
5279 UINT64_C(0),
5280 UINT64_C(0),
5281 UINT64_C(0),
5282 UINT64_C(0),
5283 UINT64_C(0),
5284 UINT64_C(0),
5285 UINT64_C(0),
5286 UINT64_C(0),
5287 UINT64_C(0),
5288 UINT64_C(0),
5289 UINT64_C(0),
5290 UINT64_C(0),
5291 UINT64_C(0),
5292 UINT64_C(0),
5293 UINT64_C(0),
5294 UINT64_C(0),
5295 UINT64_C(0),
5296 UINT64_C(0),
5297 UINT64_C(0),
5298 UINT64_C(0),
5299 UINT64_C(0),
5300 UINT64_C(0),
5301 UINT64_C(0),
5302 UINT64_C(0),
5303 UINT64_C(0),
5304 UINT64_C(0),
5305 UINT64_C(0),
5306 UINT64_C(0),
5307 UINT64_C(0),
5308 UINT64_C(0),
5309 UINT64_C(0),
5310 UINT64_C(0),
5311 UINT64_C(0),
5312 UINT64_C(0),
5313 UINT64_C(0),
5314 UINT64_C(0),
5315 UINT64_C(0),
5316 UINT64_C(0),
5317 UINT64_C(0),
5318 UINT64_C(0),
5319 UINT64_C(0),
5320 UINT64_C(0),
5321 UINT64_C(0),
5322 UINT64_C(0),
5323 UINT64_C(0),
5324 UINT64_C(0),
5325 UINT64_C(0),
5326 UINT64_C(0),
5327 UINT64_C(0),
5328 UINT64_C(0),
5329 UINT64_C(0),
5330 UINT64_C(0),
5331 UINT64_C(0),
5332 UINT64_C(0),
5333 UINT64_C(0),
5334 UINT64_C(0),
5335 UINT64_C(0),
5336 UINT64_C(0),
5337 UINT64_C(0),
5338 UINT64_C(0),
5339 UINT64_C(0),
5340 UINT64_C(0),
5341 UINT64_C(0),
5342 UINT64_C(0),
5343 UINT64_C(0),
5344 UINT64_C(0),
5345 UINT64_C(0),
5346 UINT64_C(0),
5347 UINT64_C(0),
5348 UINT64_C(0),
5349 UINT64_C(0),
5350 UINT64_C(0),
5351 UINT64_C(0),
5352 UINT64_C(0),
5353 UINT64_C(0),
5354 UINT64_C(0),
5355 UINT64_C(0),
5356 UINT64_C(0),
5357 UINT64_C(0),
5358 UINT64_C(0),
5359 UINT64_C(0),
5360 UINT64_C(0),
5361 UINT64_C(0),
5362 UINT64_C(0),
5363 UINT64_C(0),
5364 UINT64_C(0),
5365 UINT64_C(0),
5366 UINT64_C(0),
5367 UINT64_C(0),
5368 UINT64_C(0),
5369 UINT64_C(0),
5370 UINT64_C(0),
5371 UINT64_C(0),
5372 UINT64_C(0),
5373 UINT64_C(0),
5374 UINT64_C(0),
5375 UINT64_C(0),
5376 UINT64_C(0),
5377 UINT64_C(0),
5378 UINT64_C(0),
5379 UINT64_C(0),
5380 UINT64_C(0),
5381 UINT64_C(0),
5382 UINT64_C(0),
5383 UINT64_C(0),
5384 UINT64_C(0),
5385 UINT64_C(0),
5386 UINT64_C(0),
5387 UINT64_C(0),
5388 UINT64_C(0),
5389 UINT64_C(0),
5390 UINT64_C(0),
5391 UINT64_C(0),
5392 UINT64_C(0),
5393 UINT64_C(0),
5394 UINT64_C(0),
5395 UINT64_C(0),
5396 UINT64_C(0),
5397 UINT64_C(0),
5398 UINT64_C(0),
5399 UINT64_C(0),
5400 UINT64_C(0),
5401 UINT64_C(0),
5402 UINT64_C(0),
5403 UINT64_C(0),
5404 UINT64_C(0),
5405 UINT64_C(0),
5406 UINT64_C(0),
5407 UINT64_C(0),
5408 UINT64_C(0),
5409 UINT64_C(0),
5410 UINT64_C(0),
5411 UINT64_C(0),
5412 UINT64_C(0),
5413 UINT64_C(0),
5414 UINT64_C(0),
5415 UINT64_C(0),
5416 UINT64_C(0),
5417 UINT64_C(0),
5418 UINT64_C(0),
5419 UINT64_C(0),
5420 UINT64_C(0),
5421 UINT64_C(0),
5422 UINT64_C(0),
5423 UINT64_C(0),
5424 UINT64_C(0),
5425 UINT64_C(0),
5426 UINT64_C(0),
5427 UINT64_C(0),
5428 UINT64_C(0),
5429 UINT64_C(0),
5430 UINT64_C(0),
5431 UINT64_C(0),
5432 UINT64_C(0),
5433 UINT64_C(0),
5434 UINT64_C(0),
5435 UINT64_C(0),
5436 UINT64_C(0),
5437 UINT64_C(0),
5438 UINT64_C(0),
5439 UINT64_C(0),
5440 UINT64_C(0),
5441 UINT64_C(0),
5442 UINT64_C(0),
5443 UINT64_C(0),
5444 UINT64_C(0),
5445 UINT64_C(0),
5446 UINT64_C(0),
5447 UINT64_C(0),
5448 UINT64_C(0),
5449 UINT64_C(0),
5450 UINT64_C(0),
5451 UINT64_C(0),
5452 UINT64_C(0),
5453 UINT64_C(0),
5454 UINT64_C(0),
5455 UINT64_C(0),
5456 UINT64_C(0),
5457 UINT64_C(0),
5458 UINT64_C(0),
5459 UINT64_C(0),
5460 UINT64_C(0),
5461 UINT64_C(0),
5462 UINT64_C(0),
5463 UINT64_C(0),
5464 UINT64_C(0),
5465 UINT64_C(0),
5466 UINT64_C(0),
5467 UINT64_C(0),
5468 UINT64_C(0),
5469 UINT64_C(0),
5470 UINT64_C(0),
5471 UINT64_C(0),
5472 UINT64_C(0),
5473 UINT64_C(0),
5474 UINT64_C(0),
5475 UINT64_C(0),
5476 UINT64_C(0),
5477 UINT64_C(0),
5478 UINT64_C(0),
5479 UINT64_C(0),
5480 UINT64_C(0),
5481 UINT64_C(0),
5482 UINT64_C(0),
5483 UINT64_C(0),
5484 UINT64_C(0),
5485 UINT64_C(0),
5486 UINT64_C(0),
5487 UINT64_C(0),
5488 UINT64_C(0),
5489 UINT64_C(0),
5490 UINT64_C(0),
5491 UINT64_C(0),
5492 UINT64_C(0),
5493 UINT64_C(0),
5494 UINT64_C(0),
5495 UINT64_C(0),
5496 UINT64_C(0),
5497 UINT64_C(0),
5498 UINT64_C(0),
5499 UINT64_C(0),
5500 UINT64_C(0),
5501 UINT64_C(0),
5502 UINT64_C(0),
5503 UINT64_C(0),
5504 UINT64_C(0),
5505 UINT64_C(0),
5506 UINT64_C(0),
5507 UINT64_C(0),
5508 UINT64_C(0),
5509 UINT64_C(0),
5510 UINT64_C(0),
5511 UINT64_C(0),
5512 UINT64_C(0),
5513 UINT64_C(0),
5514 UINT64_C(0),
5515 UINT64_C(0),
5516 UINT64_C(0),
5517 UINT64_C(0),
5518 UINT64_C(0),
5519 UINT64_C(0),
5520 UINT64_C(0),
5521 UINT64_C(0),
5522 UINT64_C(0),
5523 UINT64_C(0),
5524 UINT64_C(0),
5525 UINT64_C(0),
5526 UINT64_C(0),
5527 UINT64_C(0),
5528 UINT64_C(0),
5529 UINT64_C(0),
5530 UINT64_C(0),
5531 UINT64_C(0),
5532 UINT64_C(0),
5533 UINT64_C(0),
5534 UINT64_C(0),
5535 UINT64_C(0),
5536 UINT64_C(0),
5537 UINT64_C(0),
5538 UINT64_C(0),
5539 UINT64_C(0),
5540 UINT64_C(0),
5541 UINT64_C(0),
5542 UINT64_C(0),
5543 UINT64_C(0),
5544 UINT64_C(0),
5545 UINT64_C(0),
5546 UINT64_C(0),
5547 UINT64_C(0),
5548 UINT64_C(0),
5549 UINT64_C(0),
5550 UINT64_C(0),
5551 UINT64_C(0),
5552 UINT64_C(0),
5553 UINT64_C(0),
5554 UINT64_C(0),
5555 UINT64_C(0),
5556 UINT64_C(0),
5557 UINT64_C(0),
5558 UINT64_C(0),
5559 UINT64_C(0),
5560 UINT64_C(0),
5561 UINT64_C(0),
5562 UINT64_C(0),
5563 UINT64_C(0),
5564 UINT64_C(0),
5565 UINT64_C(0),
5566 UINT64_C(0),
5567 UINT64_C(0),
5568 UINT64_C(0),
5569 UINT64_C(0),
5570 UINT64_C(0),
5571 UINT64_C(0),
5572 UINT64_C(0),
5573 UINT64_C(0),
5574 UINT64_C(0),
5575 UINT64_C(0),
5576 UINT64_C(0),
5577 UINT64_C(0),
5578 UINT64_C(0),
5579 UINT64_C(0),
5580 UINT64_C(0),
5581 UINT64_C(0),
5582 UINT64_C(0),
5583 UINT64_C(0),
5584 UINT64_C(0),
5585 UINT64_C(0),
5586 UINT64_C(0),
5587 UINT64_C(0),
5588 UINT64_C(0),
5589 UINT64_C(0),
5590 UINT64_C(0),
5591 UINT64_C(0),
5592 UINT64_C(0),
5593 UINT64_C(0),
5594 UINT64_C(0),
5595 UINT64_C(0),
5596 UINT64_C(0),
5597 UINT64_C(0),
5598 UINT64_C(0),
5599 UINT64_C(0),
5600 UINT64_C(0),
5601 UINT64_C(0),
5602 UINT64_C(0),
5603 UINT64_C(0),
5604 UINT64_C(0),
5605 UINT64_C(0),
5606 UINT64_C(0),
5607 UINT64_C(0),
5608 UINT64_C(0),
5609 UINT64_C(0),
5610 UINT64_C(0),
5611 UINT64_C(0),
5612 UINT64_C(0),
5613 UINT64_C(0),
5614 UINT64_C(0),
5615 UINT64_C(0),
5616 UINT64_C(0),
5617 UINT64_C(0),
5618 UINT64_C(0),
5619 UINT64_C(0),
5620 UINT64_C(0),
5621 UINT64_C(0),
5622 UINT64_C(0),
5623 UINT64_C(0),
5624 UINT64_C(0),
5625 UINT64_C(0),
5626 UINT64_C(0),
5627 UINT64_C(0),
5628 UINT64_C(0),
5629 UINT64_C(0),
5630 UINT64_C(0),
5631 UINT64_C(0),
5632 UINT64_C(0),
5633 UINT64_C(0),
5634 UINT64_C(0),
5635 UINT64_C(0),
5636 UINT64_C(0),
5637 UINT64_C(0),
5638 UINT64_C(0),
5639 UINT64_C(0),
5640 UINT64_C(0),
5641 UINT64_C(0),
5642 UINT64_C(0),
5643 UINT64_C(0),
5644 UINT64_C(0),
5645 UINT64_C(0),
5646 UINT64_C(0),
5647 UINT64_C(0),
5648 UINT64_C(0),
5649 UINT64_C(0),
5650 UINT64_C(0),
5651 UINT64_C(0),
5652 UINT64_C(0),
5653 UINT64_C(0),
5654 UINT64_C(0),
5655 UINT64_C(0),
5656 UINT64_C(0),
5657 UINT64_C(0),
5658 UINT64_C(0),
5659 UINT64_C(0),
5660 UINT64_C(0),
5661 UINT64_C(0),
5662 UINT64_C(0),
5663 UINT64_C(0),
5664 UINT64_C(0),
5665 UINT64_C(0),
5666 UINT64_C(0),
5667 UINT64_C(0),
5668 UINT64_C(0),
5669 UINT64_C(0),
5670 UINT64_C(0),
5671 UINT64_C(0),
5672 UINT64_C(0),
5673 UINT64_C(0),
5674 UINT64_C(0),
5675 UINT64_C(0),
5676 UINT64_C(0),
5677 UINT64_C(0),
5678 UINT64_C(0),
5679 UINT64_C(0),
5680 UINT64_C(0),
5681 UINT64_C(0),
5682 UINT64_C(0),
5683 UINT64_C(0),
5684 UINT64_C(0),
5685 UINT64_C(0),
5686 UINT64_C(0),
5687 UINT64_C(0),
5688 UINT64_C(0),
5689 UINT64_C(0),
5690 UINT64_C(0),
5691 UINT64_C(0),
5692 UINT64_C(0),
5693 UINT64_C(0),
5694 UINT64_C(0),
5695 UINT64_C(0),
5696 UINT64_C(0),
5697 UINT64_C(0),
5698 UINT64_C(0),
5699 UINT64_C(0),
5700 UINT64_C(0),
5701 UINT64_C(0),
5702 UINT64_C(0),
5703 UINT64_C(0),
5704 UINT64_C(0),
5705 UINT64_C(0),
5706 UINT64_C(0),
5707 UINT64_C(0),
5708 UINT64_C(0),
5709 UINT64_C(0),
5710 UINT64_C(0),
5711 UINT64_C(0),
5712 UINT64_C(0),
5713 UINT64_C(0),
5714 UINT64_C(0),
5715 UINT64_C(0),
5716 UINT64_C(0),
5717 UINT64_C(0),
5718 UINT64_C(0),
5719 UINT64_C(0),
5720 UINT64_C(0),
5721 UINT64_C(0),
5722 UINT64_C(0),
5723 UINT64_C(0),
5724 UINT64_C(0),
5725 UINT64_C(0),
5726 UINT64_C(0),
5727 UINT64_C(0),
5728 UINT64_C(0),
5729 UINT64_C(0),
5730 UINT64_C(0),
5731 UINT64_C(0),
5732 UINT64_C(0),
5733 UINT64_C(0),
5734 UINT64_C(0),
5735 UINT64_C(0),
5736 UINT64_C(0),
5737 UINT64_C(0),
5738 UINT64_C(0),
5739 UINT64_C(0),
5740 UINT64_C(0),
5741 UINT64_C(0),
5742 UINT64_C(0),
5743 UINT64_C(0),
5744 UINT64_C(0),
5745 UINT64_C(0),
5746 UINT64_C(0),
5747 UINT64_C(0),
5748 UINT64_C(0),
5749 UINT64_C(0),
5750 UINT64_C(0),
5751 UINT64_C(0),
5752 UINT64_C(0),
5753 UINT64_C(0),
5754 UINT64_C(0),
5755 UINT64_C(0),
5756 UINT64_C(0),
5757 UINT64_C(0),
5758 UINT64_C(0),
5759 UINT64_C(0),
5760 UINT64_C(0),
5761 UINT64_C(0),
5762 UINT64_C(0),
5763 UINT64_C(0),
5764 UINT64_C(0),
5765 UINT64_C(0),
5766 UINT64_C(0),
5767 UINT64_C(0),
5768 UINT64_C(0),
5769 UINT64_C(0),
5770 UINT64_C(0),
5771 UINT64_C(0),
5772 UINT64_C(0),
5773 UINT64_C(0),
5774 UINT64_C(0),
5775 UINT64_C(0),
5776 UINT64_C(0),
5777 UINT64_C(0),
5778 UINT64_C(0),
5779 UINT64_C(0),
5780 UINT64_C(0),
5781 UINT64_C(0),
5782 UINT64_C(0),
5783 UINT64_C(0),
5784 UINT64_C(0),
5785 UINT64_C(0),
5786 UINT64_C(0),
5787 UINT64_C(0),
5788 UINT64_C(0),
5789 UINT64_C(0),
5790 UINT64_C(0),
5791 UINT64_C(0),
5792 UINT64_C(0),
5793 UINT64_C(0),
5794 UINT64_C(0),
5795 UINT64_C(0),
5796 UINT64_C(0),
5797 UINT64_C(0),
5798 UINT64_C(0),
5799 UINT64_C(0),
5800 UINT64_C(0),
5801 UINT64_C(0),
5802 UINT64_C(0),
5803 UINT64_C(0),
5804 UINT64_C(0),
5805 UINT64_C(0),
5806 UINT64_C(0),
5807 UINT64_C(0),
5808 UINT64_C(0),
5809 UINT64_C(0),
5810 UINT64_C(0),
5811 UINT64_C(0),
5812 UINT64_C(0),
5813 UINT64_C(0),
5814 UINT64_C(0),
5815 UINT64_C(0),
5816 UINT64_C(0),
5817 UINT64_C(0),
5818 UINT64_C(0),
5819 UINT64_C(0),
5820 UINT64_C(0),
5821 UINT64_C(0),
5822 UINT64_C(0),
5823 UINT64_C(0),
5824 UINT64_C(0),
5825 UINT64_C(0),
5826 UINT64_C(0),
5827 UINT64_C(0),
5828 UINT64_C(0),
5829 UINT64_C(0),
5830 UINT64_C(0),
5831 UINT64_C(0),
5832 UINT64_C(0),
5833 UINT64_C(0),
5834 UINT64_C(0),
5835 UINT64_C(0),
5836 UINT64_C(0),
5837 UINT64_C(0),
5838 UINT64_C(0),
5839 UINT64_C(0),
5840 UINT64_C(0),
5841 UINT64_C(0),
5842 UINT64_C(0),
5843 UINT64_C(0),
5844 UINT64_C(0),
5845 UINT64_C(0),
5846 UINT64_C(0),
5847 UINT64_C(0),
5848 UINT64_C(0),
5849 UINT64_C(0),
5850 UINT64_C(0),
5851 UINT64_C(0),
5852 UINT64_C(0),
5853 UINT64_C(0),
5854 UINT64_C(0),
5855 UINT64_C(0),
5856 UINT64_C(0),
5857 UINT64_C(0),
5858 UINT64_C(0),
5859 UINT64_C(0),
5860 UINT64_C(0),
5861 UINT64_C(0),
5862 UINT64_C(0),
5863 UINT64_C(0),
5864 UINT64_C(0),
5865 UINT64_C(0),
5866 UINT64_C(0),
5867 UINT64_C(0),
5868 UINT64_C(0),
5869 UINT64_C(0),
5870 UINT64_C(0),
5871 UINT64_C(0),
5872 UINT64_C(0),
5873 UINT64_C(0),
5874 UINT64_C(0),
5875 UINT64_C(0),
5876 UINT64_C(0),
5877 UINT64_C(0),
5878 UINT64_C(0),
5879 UINT64_C(0),
5880 UINT64_C(0),
5881 UINT64_C(0),
5882 UINT64_C(0),
5883 UINT64_C(0),
5884 UINT64_C(0),
5885 UINT64_C(0),
5886 UINT64_C(0),
5887 UINT64_C(0),
5888 UINT64_C(0),
5889 UINT64_C(0),
5890 UINT64_C(0),
5891 UINT64_C(0),
5892 UINT64_C(0),
5893 UINT64_C(0),
5894 UINT64_C(0),
5895 UINT64_C(0),
5896 UINT64_C(0),
5897 UINT64_C(0),
5898 UINT64_C(0),
5899 UINT64_C(0),
5900 UINT64_C(0),
5901 UINT64_C(0),
5902 UINT64_C(0),
5903 UINT64_C(0),
5904 UINT64_C(0),
5905 UINT64_C(0),
5906 UINT64_C(0),
5907 UINT64_C(0),
5908 UINT64_C(0),
5909 UINT64_C(0),
5910 UINT64_C(0),
5911 UINT64_C(0),
5912 UINT64_C(0),
5913 UINT64_C(0),
5914 UINT64_C(0),
5915 UINT64_C(0),
5916 UINT64_C(0),
5917 UINT64_C(0),
5918 UINT64_C(0),
5919 UINT64_C(0),
5920 UINT64_C(0),
5921 UINT64_C(0),
5922 UINT64_C(0),
5923 UINT64_C(0),
5924 UINT64_C(0),
5925 UINT64_C(0),
5926 UINT64_C(0),
5927 UINT64_C(0),
5928 UINT64_C(0),
5929 UINT64_C(0),
5930 UINT64_C(0),
5931 UINT64_C(0),
5932 UINT64_C(0),
5933 UINT64_C(0),
5934 UINT64_C(0),
5935 UINT64_C(0),
5936 UINT64_C(0),
5937 UINT64_C(0),
5938 UINT64_C(0),
5939 UINT64_C(0),
5940 UINT64_C(0),
5941 UINT64_C(0),
5942 UINT64_C(0),
5943 UINT64_C(0),
5944 UINT64_C(0),
5945 UINT64_C(0),
5946 UINT64_C(0),
5947 UINT64_C(0),
5948 UINT64_C(0),
5949 UINT64_C(0),
5950 UINT64_C(0),
5951 UINT64_C(0),
5952 UINT64_C(0),
5953 UINT64_C(0),
5954 UINT64_C(0),
5955 UINT64_C(0),
5956 UINT64_C(0),
5957 UINT64_C(0),
5958 UINT64_C(0),
5959 UINT64_C(0),
5960 UINT64_C(0),
5961 UINT64_C(0),
5962 UINT64_C(0),
5963 UINT64_C(0),
5964 UINT64_C(0),
5965 UINT64_C(0),
5966 UINT64_C(0),
5967 UINT64_C(0),
5968 UINT64_C(0),
5969 UINT64_C(0),
5970 UINT64_C(0),
5971 UINT64_C(0),
5972 UINT64_C(0),
5973 UINT64_C(0),
5974 UINT64_C(0),
5975 UINT64_C(0),
5976 UINT64_C(0),
5977 UINT64_C(0),
5978 UINT64_C(0),
5979 UINT64_C(0),
5980 UINT64_C(0),
5981 UINT64_C(0),
5982 UINT64_C(0),
5983 UINT64_C(0),
5984 UINT64_C(0),
5985 UINT64_C(0),
5986 UINT64_C(0),
5987 UINT64_C(0),
5988 UINT64_C(0),
5989 UINT64_C(0),
5990 UINT64_C(0),
5991 UINT64_C(0),
5992 UINT64_C(0),
5993 UINT64_C(0),
5994 UINT64_C(0),
5995 UINT64_C(0),
5996 UINT64_C(0),
5997 UINT64_C(0),
5998 UINT64_C(0),
5999 UINT64_C(0),
6000 UINT64_C(0),
6001 UINT64_C(0),
6002 UINT64_C(0),
6003 UINT64_C(0),
6004 UINT64_C(0),
6005 UINT64_C(0),
6006 UINT64_C(0),
6007 UINT64_C(0),
6008 UINT64_C(0),
6009 UINT64_C(0),
6010 UINT64_C(0),
6011 UINT64_C(0),
6012 UINT64_C(0),
6013 UINT64_C(0),
6014 UINT64_C(0),
6015 UINT64_C(0),
6016 UINT64_C(0),
6017 UINT64_C(0),
6018 UINT64_C(0),
6019 UINT64_C(0),
6020 UINT64_C(0),
6021 UINT64_C(0),
6022 UINT64_C(0),
6023 UINT64_C(0),
6024 UINT64_C(0),
6025 UINT64_C(0),
6026 UINT64_C(0),
6027 UINT64_C(0),
6028 UINT64_C(0),
6029 UINT64_C(0),
6030 UINT64_C(0),
6031 UINT64_C(0),
6032 UINT64_C(0),
6033 UINT64_C(0),
6034 UINT64_C(0),
6035 UINT64_C(0),
6036 UINT64_C(0),
6037 UINT64_C(0),
6038 UINT64_C(0),
6039 UINT64_C(0),
6040 UINT64_C(0),
6041 UINT64_C(0),
6042 UINT64_C(0),
6043 UINT64_C(0),
6044 UINT64_C(0),
6045 UINT64_C(0),
6046 UINT64_C(0),
6047 UINT64_C(0),
6048 UINT64_C(0),
6049 UINT64_C(0),
6050 UINT64_C(0),
6051 UINT64_C(0),
6052 UINT64_C(0),
6053 UINT64_C(0),
6054 UINT64_C(0),
6055 UINT64_C(0),
6056 UINT64_C(0),
6057 UINT64_C(0),
6058 UINT64_C(0),
6059 UINT64_C(0),
6060 UINT64_C(0),
6061 UINT64_C(0),
6062 UINT64_C(0),
6063 UINT64_C(0),
6064 UINT64_C(0),
6065 UINT64_C(0),
6066 UINT64_C(0),
6067 UINT64_C(0),
6068 UINT64_C(0),
6069 UINT64_C(0),
6070 UINT64_C(0),
6071 UINT64_C(0),
6072 UINT64_C(0),
6073 UINT64_C(0),
6074 UINT64_C(0),
6075 UINT64_C(0),
6076 UINT64_C(0),
6077 UINT64_C(0),
6078 UINT64_C(0),
6079 UINT64_C(0),
6080 UINT64_C(0),
6081 UINT64_C(0),
6082 UINT64_C(0),
6083 UINT64_C(0),
6084 UINT64_C(0),
6085 UINT64_C(0),
6086 UINT64_C(0),
6087 UINT64_C(0),
6088 UINT64_C(0),
6089 UINT64_C(0),
6090 UINT64_C(0),
6091 UINT64_C(0),
6092 UINT64_C(0),
6093 UINT64_C(0),
6094 UINT64_C(0),
6095 UINT64_C(0),
6096 UINT64_C(0),
6097 UINT64_C(0),
6098 UINT64_C(0),
6099 UINT64_C(0),
6100 UINT64_C(0),
6101 UINT64_C(0),
6102 UINT64_C(0),
6103 UINT64_C(0),
6104 UINT64_C(0),
6105 UINT64_C(0),
6106 UINT64_C(0),
6107 UINT64_C(0),
6108 UINT64_C(0),
6109 UINT64_C(0),
6110 UINT64_C(0),
6111 UINT64_C(0),
6112 UINT64_C(0),
6113 UINT64_C(0),
6114 UINT64_C(0),
6115 UINT64_C(0),
6116 UINT64_C(0),
6117 UINT64_C(0),
6118 UINT64_C(0),
6119 UINT64_C(0),
6120 UINT64_C(0),
6121 UINT64_C(0),
6122 UINT64_C(0),
6123 UINT64_C(0),
6124 UINT64_C(0),
6125 UINT64_C(0),
6126 UINT64_C(0),
6127 UINT64_C(0),
6128 UINT64_C(0),
6129 UINT64_C(0),
6130 UINT64_C(0),
6131 UINT64_C(0),
6132 UINT64_C(0),
6133 UINT64_C(0),
6134 UINT64_C(0),
6135 UINT64_C(0),
6136 UINT64_C(0),
6137 UINT64_C(0),
6138 UINT64_C(0),
6139 UINT64_C(0),
6140 UINT64_C(0),
6141 UINT64_C(0),
6142 UINT64_C(0),
6143 UINT64_C(0),
6144 UINT64_C(0),
6145 UINT64_C(0),
6146 UINT64_C(0),
6147 UINT64_C(0),
6148 UINT64_C(0),
6149 UINT64_C(0),
6150 UINT64_C(0),
6151 UINT64_C(0),
6152 UINT64_C(0),
6153 UINT64_C(0),
6154 UINT64_C(0),
6155 UINT64_C(0),
6156 UINT64_C(0),
6157 UINT64_C(0),
6158 UINT64_C(0),
6159 UINT64_C(0),
6160 UINT64_C(0),
6161 UINT64_C(0),
6162 UINT64_C(0),
6163 UINT64_C(0),
6164 UINT64_C(0),
6165 UINT64_C(0),
6166 UINT64_C(0),
6167 UINT64_C(0),
6168 UINT64_C(0),
6169 UINT64_C(0),
6170 UINT64_C(0),
6171 UINT64_C(0),
6172 UINT64_C(0),
6173 UINT64_C(0),
6174 UINT64_C(0),
6175 UINT64_C(0),
6176 UINT64_C(0),
6177 UINT64_C(0),
6178 UINT64_C(0),
6179 UINT64_C(0),
6180 UINT64_C(0),
6181 UINT64_C(0),
6182 UINT64_C(0),
6183 UINT64_C(0),
6184 UINT64_C(0),
6185 UINT64_C(0),
6186 UINT64_C(0),
6187 UINT64_C(0),
6188 UINT64_C(0),
6189 UINT64_C(0),
6190 UINT64_C(0),
6191 UINT64_C(0),
6192 UINT64_C(0),
6193 UINT64_C(0),
6194 UINT64_C(0),
6195 UINT64_C(0),
6196 UINT64_C(0),
6197 UINT64_C(0),
6198 UINT64_C(0),
6199 UINT64_C(0),
6200 UINT64_C(0),
6201 UINT64_C(0),
6202 UINT64_C(0),
6203 UINT64_C(0),
6204 UINT64_C(0),
6205 UINT64_C(0),
6206 UINT64_C(0),
6207 UINT64_C(0),
6208 UINT64_C(0),
6209 UINT64_C(0),
6210 UINT64_C(0),
6211 UINT64_C(0),
6212 UINT64_C(0),
6213 UINT64_C(0),
6214 UINT64_C(0),
6215 UINT64_C(0),
6216 UINT64_C(0),
6217 UINT64_C(0),
6218 UINT64_C(0),
6219 UINT64_C(0),
6220 UINT64_C(0),
6221 UINT64_C(0),
6222 UINT64_C(0),
6223 UINT64_C(0),
6224 UINT64_C(0),
6225 UINT64_C(0),
6226 UINT64_C(0),
6227 UINT64_C(0),
6228 UINT64_C(0),
6229 UINT64_C(0),
6230 UINT64_C(0),
6231 UINT64_C(0),
6232 UINT64_C(0),
6233 UINT64_C(0),
6234 UINT64_C(0),
6235 UINT64_C(0),
6236 UINT64_C(0),
6237 UINT64_C(0),
6238 UINT64_C(0),
6239 UINT64_C(0),
6240 UINT64_C(0),
6241 UINT64_C(0),
6242 UINT64_C(0),
6243 UINT64_C(0),
6244 UINT64_C(0),
6245 UINT64_C(0),
6246 UINT64_C(0),
6247 UINT64_C(0),
6248 UINT64_C(0),
6249 UINT64_C(0),
6250 UINT64_C(0),
6251 UINT64_C(0),
6252 UINT64_C(0),
6253 UINT64_C(0),
6254 UINT64_C(0),
6255 UINT64_C(0),
6256 UINT64_C(0),
6257 UINT64_C(0),
6258 UINT64_C(0),
6259 UINT64_C(0),
6260 UINT64_C(0),
6261 UINT64_C(0),
6262 UINT64_C(0),
6263 UINT64_C(0),
6264 UINT64_C(0),
6265 UINT64_C(0),
6266 UINT64_C(0),
6267 UINT64_C(0),
6268 UINT64_C(0),
6269 UINT64_C(0),
6270 UINT64_C(0),
6271 UINT64_C(0),
6272 UINT64_C(0),
6273 UINT64_C(0),
6274 UINT64_C(0),
6275 UINT64_C(0),
6276 UINT64_C(0),
6277 UINT64_C(0),
6278 UINT64_C(0),
6279 UINT64_C(0),
6280 UINT64_C(0),
6281 UINT64_C(0),
6282 UINT64_C(0),
6283 UINT64_C(0),
6284 UINT64_C(0),
6285 UINT64_C(0),
6286 UINT64_C(0),
6287 UINT64_C(0),
6288 UINT64_C(0),
6289 UINT64_C(0),
6290 UINT64_C(0),
6291 UINT64_C(0),
6292 UINT64_C(0),
6293 UINT64_C(0),
6294 UINT64_C(0),
6295 UINT64_C(0),
6296 UINT64_C(0),
6297 UINT64_C(0),
6298 UINT64_C(0),
6299 UINT64_C(0),
6300 UINT64_C(0),
6301 UINT64_C(0),
6302 UINT64_C(0),
6303 UINT64_C(0),
6304 UINT64_C(0),
6305 UINT64_C(0),
6306 UINT64_C(0),
6307 UINT64_C(0),
6308 UINT64_C(0),
6309 UINT64_C(0),
6310 UINT64_C(0),
6311 UINT64_C(0),
6312 UINT64_C(0),
6313 UINT64_C(0),
6314 UINT64_C(0),
6315 UINT64_C(0),
6316 UINT64_C(0),
6317 UINT64_C(0),
6318 UINT64_C(0),
6319 UINT64_C(0),
6320 UINT64_C(0),
6321 UINT64_C(0),
6322 UINT64_C(0),
6323 UINT64_C(0),
6324 UINT64_C(0),
6325 UINT64_C(0),
6326 UINT64_C(0),
6327 UINT64_C(0),
6328 UINT64_C(0),
6329 UINT64_C(0),
6330 UINT64_C(0),
6331 UINT64_C(0),
6332 UINT64_C(0),
6333 UINT64_C(0),
6334 UINT64_C(0),
6335 UINT64_C(0),
6336 UINT64_C(0),
6337 UINT64_C(0),
6338 UINT64_C(0),
6339 UINT64_C(0),
6340 UINT64_C(0),
6341 UINT64_C(0),
6342 UINT64_C(0),
6343 UINT64_C(0),
6344 UINT64_C(0),
6345 UINT64_C(0),
6346 UINT64_C(0),
6347 UINT64_C(0),
6348 UINT64_C(0),
6349 UINT64_C(0),
6350 UINT64_C(0),
6351 UINT64_C(0),
6352 UINT64_C(0),
6353 UINT64_C(0),
6354 UINT64_C(0),
6355 UINT64_C(0),
6356 UINT64_C(0),
6357 UINT64_C(0),
6358 UINT64_C(0),
6359 UINT64_C(0),
6360 UINT64_C(0),
6361 UINT64_C(0),
6362 UINT64_C(0),
6363 UINT64_C(0),
6364 UINT64_C(0),
6365 UINT64_C(0),
6366 UINT64_C(0),
6367 UINT64_C(0),
6368 UINT64_C(0),
6369 UINT64_C(0),
6370 UINT64_C(0),
6371 UINT64_C(0),
6372 UINT64_C(0),
6373 UINT64_C(0),
6374 UINT64_C(0),
6375 UINT64_C(0),
6376 UINT64_C(0),
6377 UINT64_C(0),
6378 UINT64_C(0),
6379 UINT64_C(0),
6380 UINT64_C(0),
6381 UINT64_C(0),
6382 UINT64_C(0),
6383 UINT64_C(0),
6384 UINT64_C(0),
6385 UINT64_C(0),
6386 UINT64_C(0),
6387 UINT64_C(0),
6388 UINT64_C(0),
6389 UINT64_C(0),
6390 UINT64_C(0),
6391 UINT64_C(0),
6392 UINT64_C(0),
6393 UINT64_C(0),
6394 UINT64_C(0),
6395 UINT64_C(0),
6396 UINT64_C(0),
6397 UINT64_C(0),
6398 UINT64_C(0),
6399 UINT64_C(0),
6400 UINT64_C(0),
6401 UINT64_C(0),
6402 UINT64_C(0),
6403 UINT64_C(0),
6404 UINT64_C(0),
6405 UINT64_C(0),
6406 UINT64_C(0),
6407 UINT64_C(0),
6408 UINT64_C(0),
6409 UINT64_C(0),
6410 UINT64_C(0),
6411 UINT64_C(0),
6412 UINT64_C(0),
6413 UINT64_C(0),
6414 UINT64_C(0),
6415 UINT64_C(0),
6416 UINT64_C(0),
6417 UINT64_C(0),
6418 UINT64_C(0),
6419 UINT64_C(0),
6420 UINT64_C(0),
6421 UINT64_C(0),
6422 UINT64_C(0),
6423 UINT64_C(0),
6424 UINT64_C(0),
6425 UINT64_C(0),
6426 UINT64_C(0),
6427 UINT64_C(0),
6428 UINT64_C(0),
6429 UINT64_C(0),
6430 UINT64_C(0),
6431 UINT64_C(0),
6432 UINT64_C(0),
6433 UINT64_C(0),
6434 UINT64_C(0),
6435 UINT64_C(0),
6436 UINT64_C(0),
6437 UINT64_C(0),
6438 UINT64_C(0),
6439 UINT64_C(0),
6440 UINT64_C(0),
6441 UINT64_C(0),
6442 UINT64_C(0),
6443 UINT64_C(0),
6444 UINT64_C(0),
6445 UINT64_C(0),
6446 UINT64_C(0),
6447 UINT64_C(0),
6448 UINT64_C(0),
6449 UINT64_C(0),
6450 UINT64_C(0),
6451 UINT64_C(0),
6452 UINT64_C(0),
6453 UINT64_C(0),
6454 UINT64_C(0),
6455 UINT64_C(0),
6456 UINT64_C(0),
6457 UINT64_C(0),
6458 UINT64_C(0),
6459 UINT64_C(0),
6460 UINT64_C(0),
6461 UINT64_C(0),
6462 UINT64_C(0),
6463 UINT64_C(0),
6464 UINT64_C(0),
6465 UINT64_C(0),
6466 UINT64_C(0),
6467 UINT64_C(0),
6468 UINT64_C(0),
6469 UINT64_C(0),
6470 UINT64_C(0),
6471 UINT64_C(0),
6472 UINT64_C(0),
6473 UINT64_C(0),
6474 UINT64_C(0),
6475 UINT64_C(0),
6476 UINT64_C(0),
6477 UINT64_C(0),
6478 UINT64_C(0),
6479 UINT64_C(0),
6480 UINT64_C(0),
6481 UINT64_C(0),
6482 UINT64_C(0),
6483 UINT64_C(0),
6484 UINT64_C(0),
6485 UINT64_C(0),
6486 UINT64_C(0),
6487 UINT64_C(0),
6488 UINT64_C(0),
6489 UINT64_C(0),
6490 UINT64_C(0),
6491 UINT64_C(0),
6492 UINT64_C(0),
6493 UINT64_C(0),
6494 UINT64_C(0),
6495 UINT64_C(0),
6496 UINT64_C(0),
6497 UINT64_C(0),
6498 UINT64_C(0),
6499 UINT64_C(0),
6500 UINT64_C(0),
6501 UINT64_C(0),
6502 UINT64_C(0),
6503 UINT64_C(0),
6504 UINT64_C(0),
6505 UINT64_C(0),
6506 UINT64_C(0),
6507 UINT64_C(0),
6508 UINT64_C(0),
6509 UINT64_C(0),
6510 UINT64_C(0),
6511 UINT64_C(0),
6512 UINT64_C(0),
6513 UINT64_C(0),
6514 UINT64_C(0),
6515 UINT64_C(0),
6516 UINT64_C(0),
6517 UINT64_C(0),
6518 UINT64_C(0),
6519 UINT64_C(0),
6520 UINT64_C(0),
6521 UINT64_C(0),
6522 UINT64_C(0),
6523 UINT64_C(0),
6524 UINT64_C(0),
6525 UINT64_C(0),
6526 UINT64_C(0),
6527 UINT64_C(0),
6528 UINT64_C(0),
6529 UINT64_C(0),
6530 UINT64_C(0),
6531 UINT64_C(0),
6532 UINT64_C(0),
6533 UINT64_C(0),
6534 UINT64_C(0),
6535 UINT64_C(0),
6536 UINT64_C(0),
6537 UINT64_C(0),
6538 UINT64_C(0),
6539 UINT64_C(0),
6540 UINT64_C(0),
6541 UINT64_C(0),
6542 UINT64_C(0),
6543 UINT64_C(0),
6544 UINT64_C(0),
6545 UINT64_C(0),
6546 UINT64_C(0),
6547 UINT64_C(0),
6548 UINT64_C(0),
6549 UINT64_C(0),
6550 UINT64_C(0),
6551 UINT64_C(0),
6552 UINT64_C(0),
6553 UINT64_C(0),
6554 UINT64_C(0),
6555 UINT64_C(0),
6556 UINT64_C(0),
6557 UINT64_C(0),
6558 UINT64_C(0),
6559 UINT64_C(0),
6560 UINT64_C(0),
6561 UINT64_C(0),
6562 UINT64_C(0),
6563 UINT64_C(0),
6564 UINT64_C(0),
6565 UINT64_C(0),
6566 UINT64_C(0),
6567 UINT64_C(0),
6568 UINT64_C(0),
6569 UINT64_C(0),
6570 UINT64_C(0),
6571 UINT64_C(0),
6572 UINT64_C(0),
6573 UINT64_C(0),
6574 UINT64_C(0),
6575 UINT64_C(0),
6576 UINT64_C(0),
6577 UINT64_C(0),
6578 UINT64_C(0),
6579 UINT64_C(0),
6580 UINT64_C(0),
6581 UINT64_C(0),
6582 UINT64_C(0),
6583 UINT64_C(0),
6584 UINT64_C(0),
6585 UINT64_C(0),
6586 UINT64_C(0),
6587 UINT64_C(0),
6588 UINT64_C(0),
6589 UINT64_C(0),
6590 UINT64_C(0),
6591 UINT64_C(0),
6592 UINT64_C(0),
6593 UINT64_C(0),
6594 UINT64_C(0),
6595 UINT64_C(0),
6596 UINT64_C(0),
6597 UINT64_C(0),
6598 UINT64_C(0),
6599 UINT64_C(0),
6600 UINT64_C(0),
6601 UINT64_C(0),
6602 UINT64_C(0),
6603 UINT64_C(0),
6604 UINT64_C(0),
6605 UINT64_C(0),
6606 UINT64_C(0),
6607 UINT64_C(0),
6608 UINT64_C(0),
6609 UINT64_C(0),
6610 UINT64_C(0),
6611 UINT64_C(0),
6612 UINT64_C(0),
6613 UINT64_C(0),
6614 UINT64_C(0),
6615 UINT64_C(0),
6616 UINT64_C(0),
6617 UINT64_C(0),
6618 UINT64_C(0),
6619 UINT64_C(0),
6620 UINT64_C(0),
6621 UINT64_C(0),
6622 UINT64_C(0),
6623 UINT64_C(0),
6624 UINT64_C(0),
6625 UINT64_C(0),
6626 UINT64_C(0),
6627 UINT64_C(0),
6628 UINT64_C(0),
6629 UINT64_C(0),
6630 UINT64_C(0),
6631 UINT64_C(0),
6632 UINT64_C(0),
6633 UINT64_C(0),
6634 UINT64_C(0),
6635 UINT64_C(0),
6636 UINT64_C(0),
6637 UINT64_C(0),
6638 UINT64_C(0),
6639 UINT64_C(0),
6640 UINT64_C(0),
6641 UINT64_C(0),
6642 UINT64_C(0),
6643 UINT64_C(0),
6644 UINT64_C(0),
6645 UINT64_C(0),
6646 UINT64_C(0),
6647 UINT64_C(0),
6648 UINT64_C(0),
6649 UINT64_C(0),
6650 UINT64_C(0),
6651 UINT64_C(0),
6652 UINT64_C(0),
6653 UINT64_C(0),
6654 UINT64_C(0),
6655 UINT64_C(0),
6656 UINT64_C(0),
6657 UINT64_C(0),
6658 UINT64_C(0),
6659 UINT64_C(0),
6660 UINT64_C(0),
6661 UINT64_C(0),
6662 UINT64_C(0),
6663 UINT64_C(0),
6664 UINT64_C(0),
6665 UINT64_C(0),
6666 UINT64_C(0),
6667 UINT64_C(0),
6668 UINT64_C(0),
6669 UINT64_C(0),
6670 UINT64_C(0),
6671 UINT64_C(0),
6672 UINT64_C(0),
6673 UINT64_C(0),
6674 UINT64_C(0),
6675 UINT64_C(0),
6676 UINT64_C(0),
6677 UINT64_C(0),
6678 UINT64_C(0),
6679 UINT64_C(0),
6680 UINT64_C(0),
6681 UINT64_C(0),
6682 UINT64_C(0),
6683 UINT64_C(0),
6684 UINT64_C(0),
6685 UINT64_C(0),
6686 UINT64_C(0),
6687 UINT64_C(0),
6688 UINT64_C(0),
6689 UINT64_C(0),
6690 UINT64_C(0),
6691 UINT64_C(0),
6692 UINT64_C(0),
6693 UINT64_C(0),
6694 UINT64_C(0),
6695 UINT64_C(0),
6696 UINT64_C(0),
6697 UINT64_C(0),
6698 UINT64_C(0),
6699 UINT64_C(0),
6700 UINT64_C(0),
6701 UINT64_C(0),
6702 UINT64_C(0),
6703 UINT64_C(0),
6704 UINT64_C(0),
6705 UINT64_C(0),
6706 UINT64_C(0),
6707 UINT64_C(0),
6708 UINT64_C(0),
6709 UINT64_C(0),
6710 UINT64_C(0),
6711 UINT64_C(0),
6712 UINT64_C(0),
6713 UINT64_C(0),
6714 UINT64_C(0),
6715 UINT64_C(0),
6716 UINT64_C(0),
6717 UINT64_C(0),
6718 UINT64_C(0),
6719 UINT64_C(0),
6720 UINT64_C(0),
6721 UINT64_C(0),
6722 UINT64_C(0),
6723 UINT64_C(0),
6724 UINT64_C(0),
6725 UINT64_C(0),
6726 UINT64_C(0),
6727 UINT64_C(0),
6728 UINT64_C(0),
6729 UINT64_C(0),
6730 UINT64_C(0),
6731 UINT64_C(0),
6732 UINT64_C(0),
6733 UINT64_C(0),
6734 UINT64_C(0),
6735 UINT64_C(0),
6736 UINT64_C(0),
6737 UINT64_C(0),
6738 UINT64_C(0),
6739 UINT64_C(0),
6740 UINT64_C(0),
6741 UINT64_C(0),
6742 UINT64_C(0),
6743 UINT64_C(0),
6744 UINT64_C(0),
6745 UINT64_C(0),
6746 UINT64_C(0),
6747 UINT64_C(0),
6748 UINT64_C(0),
6749 UINT64_C(0),
6750 UINT64_C(0),
6751 UINT64_C(0),
6752 UINT64_C(0),
6753 UINT64_C(0),
6754 UINT64_C(0),
6755 UINT64_C(0),
6756 UINT64_C(0),
6757 UINT64_C(0),
6758 UINT64_C(0),
6759 UINT64_C(0),
6760 UINT64_C(0),
6761 UINT64_C(0),
6762 UINT64_C(0),
6763 UINT64_C(0),
6764 UINT64_C(0),
6765 UINT64_C(0),
6766 UINT64_C(0),
6767 UINT64_C(0),
6768 UINT64_C(0),
6769 UINT64_C(0),
6770 UINT64_C(0),
6771 UINT64_C(0),
6772 UINT64_C(0),
6773 UINT64_C(0),
6774 UINT64_C(0),
6775 UINT64_C(0),
6776 UINT64_C(0),
6777 UINT64_C(0),
6778 UINT64_C(0),
6779 UINT64_C(0),
6780 UINT64_C(0),
6781 UINT64_C(0),
6782 UINT64_C(0),
6783 UINT64_C(0),
6784 UINT64_C(0),
6785 UINT64_C(0),
6786 UINT64_C(0),
6787 UINT64_C(0),
6788 UINT64_C(0),
6789 UINT64_C(0),
6790 UINT64_C(0),
6791 UINT64_C(0),
6792 UINT64_C(0),
6793 UINT64_C(0),
6794 UINT64_C(0),
6795 UINT64_C(0),
6796 UINT64_C(0),
6797 UINT64_C(0),
6798 UINT64_C(0),
6799 UINT64_C(0),
6800 UINT64_C(0),
6801 UINT64_C(0),
6802 UINT64_C(0),
6803 UINT64_C(0),
6804 UINT64_C(0),
6805 UINT64_C(0),
6806 UINT64_C(0),
6807 UINT64_C(0),
6808 UINT64_C(0),
6809 UINT64_C(0),
6810 UINT64_C(0),
6811 UINT64_C(0),
6812 UINT64_C(0),
6813 UINT64_C(0),
6814 UINT64_C(0),
6815 UINT64_C(0),
6816 UINT64_C(0),
6817 UINT64_C(0),
6818 UINT64_C(0),
6819 UINT64_C(0),
6820 UINT64_C(0),
6821 UINT64_C(0),
6822 UINT64_C(0),
6823 UINT64_C(0),
6824 UINT64_C(0),
6825 UINT64_C(0),
6826 UINT64_C(0),
6827 UINT64_C(0),
6828 UINT64_C(0),
6829 UINT64_C(0),
6830 UINT64_C(0),
6831 UINT64_C(0),
6832 UINT64_C(0),
6833 UINT64_C(0),
6834 UINT64_C(0),
6835 UINT64_C(0),
6836 UINT64_C(0),
6837 UINT64_C(0),
6838 UINT64_C(0),
6839 UINT64_C(0),
6840 UINT64_C(0),
6841 UINT64_C(0),
6842 UINT64_C(0),
6843 UINT64_C(0),
6844 UINT64_C(0),
6845 UINT64_C(0),
6846 UINT64_C(0),
6847 UINT64_C(0),
6848 UINT64_C(0),
6849 UINT64_C(0),
6850 UINT64_C(0),
6851 UINT64_C(0),
6852 UINT64_C(0),
6853 UINT64_C(0),
6854 UINT64_C(0),
6855 UINT64_C(0),
6856 UINT64_C(0),
6857 UINT64_C(0),
6858 UINT64_C(0),
6859 UINT64_C(0),
6860 UINT64_C(0),
6861 UINT64_C(0),
6862 UINT64_C(0),
6863 UINT64_C(0),
6864 UINT64_C(0),
6865 UINT64_C(0),
6866 UINT64_C(0),
6867 UINT64_C(0),
6868 UINT64_C(0),
6869 UINT64_C(0),
6870 UINT64_C(0),
6871 UINT64_C(0),
6872 UINT64_C(0),
6873 UINT64_C(0),
6874 UINT64_C(0),
6875 UINT64_C(0),
6876 UINT64_C(0),
6877 UINT64_C(0),
6878 UINT64_C(0),
6879 UINT64_C(0),
6880 UINT64_C(0),
6881 UINT64_C(0),
6882 UINT64_C(0),
6883 UINT64_C(0),
6884 UINT64_C(0),
6885 UINT64_C(0),
6886 UINT64_C(0),
6887 UINT64_C(0),
6888 UINT64_C(0),
6889 UINT64_C(0),
6890 UINT64_C(0),
6891 UINT64_C(0),
6892 UINT64_C(0),
6893 UINT64_C(0),
6894 UINT64_C(0),
6895 UINT64_C(0),
6896 UINT64_C(0),
6897 UINT64_C(0),
6898 UINT64_C(0),
6899 UINT64_C(0),
6900 UINT64_C(0),
6901 UINT64_C(0),
6902 UINT64_C(0),
6903 UINT64_C(0),
6904 UINT64_C(0),
6905 UINT64_C(0),
6906 UINT64_C(0),
6907 UINT64_C(0),
6908 UINT64_C(0),
6909 UINT64_C(0),
6910 UINT64_C(0),
6911 UINT64_C(0),
6912 UINT64_C(0),
6913 UINT64_C(0),
6914 UINT64_C(0),
6915 UINT64_C(0),
6916 UINT64_C(0),
6917 UINT64_C(0),
6918 UINT64_C(0),
6919 UINT64_C(0),
6920 UINT64_C(0),
6921 UINT64_C(0),
6922 UINT64_C(0),
6923 UINT64_C(0),
6924 UINT64_C(0),
6925 UINT64_C(0),
6926 UINT64_C(0),
6927 UINT64_C(0),
6928 UINT64_C(0),
6929 UINT64_C(0),
6930 UINT64_C(0),
6931 UINT64_C(0),
6932 UINT64_C(0),
6933 UINT64_C(0),
6934 UINT64_C(0),
6935 UINT64_C(0),
6936 UINT64_C(0),
6937 UINT64_C(0),
6938 UINT64_C(0),
6939 UINT64_C(0),
6940 UINT64_C(0),
6941 UINT64_C(0),
6942 UINT64_C(0),
6943 UINT64_C(0),
6944 UINT64_C(0),
6945 UINT64_C(0),
6946 UINT64_C(0),
6947 UINT64_C(0),
6948 UINT64_C(0),
6949 UINT64_C(0),
6950 UINT64_C(0),
6951 UINT64_C(0),
6952 UINT64_C(0),
6953 UINT64_C(0),
6954 UINT64_C(0),
6955 UINT64_C(0),
6956 UINT64_C(0),
6957 UINT64_C(0),
6958 UINT64_C(0),
6959 UINT64_C(0),
6960 UINT64_C(0),
6961 UINT64_C(0),
6962 UINT64_C(0),
6963 UINT64_C(0),
6964 UINT64_C(0),
6965 UINT64_C(0),
6966 UINT64_C(0),
6967 UINT64_C(0),
6968 UINT64_C(0),
6969 UINT64_C(0),
6970 UINT64_C(0),
6971 UINT64_C(0),
6972 UINT64_C(0),
6973 UINT64_C(0),
6974 UINT64_C(0),
6975 UINT64_C(0),
6976 UINT64_C(0),
6977 UINT64_C(0),
6978 UINT64_C(0),
6979 UINT64_C(0),
6980 UINT64_C(0),
6981 UINT64_C(0),
6982 UINT64_C(0),
6983 UINT64_C(0),
6984 UINT64_C(0),
6985 UINT64_C(0),
6986 UINT64_C(0),
6987 UINT64_C(0),
6988 UINT64_C(0),
6989 UINT64_C(0),
6990 UINT64_C(0),
6991 UINT64_C(0),
6992 UINT64_C(0),
6993 UINT64_C(0),
6994 UINT64_C(0),
6995 UINT64_C(0),
6996 UINT64_C(0),
6997 UINT64_C(0),
6998 UINT64_C(0),
6999 UINT64_C(0),
7000 UINT64_C(0),
7001 UINT64_C(0),
7002 UINT64_C(0),
7003 UINT64_C(0),
7004 UINT64_C(0),
7005 UINT64_C(0),
7006 UINT64_C(0),
7007 UINT64_C(0),
7008 UINT64_C(0),
7009 UINT64_C(0),
7010 UINT64_C(0),
7011 UINT64_C(0),
7012 UINT64_C(0),
7013 UINT64_C(0),
7014 UINT64_C(0),
7015 UINT64_C(0),
7016 UINT64_C(0),
7017 UINT64_C(0),
7018 UINT64_C(0),
7019 UINT64_C(0),
7020 UINT64_C(0),
7021 UINT64_C(0),
7022 UINT64_C(0),
7023 UINT64_C(0),
7024 UINT64_C(0),
7025 UINT64_C(0),
7026 UINT64_C(0),
7027 UINT64_C(0),
7028 UINT64_C(0),
7029 UINT64_C(0),
7030 UINT64_C(0),
7031 UINT64_C(0),
7032 UINT64_C(0),
7033 UINT64_C(0),
7034 UINT64_C(0),
7035 UINT64_C(0),
7036 UINT64_C(0),
7037 UINT64_C(0),
7038 UINT64_C(0),
7039 UINT64_C(0),
7040 UINT64_C(0),
7041 UINT64_C(0),
7042 UINT64_C(0),
7043 UINT64_C(0),
7044 UINT64_C(0),
7045 UINT64_C(0),
7046 UINT64_C(0),
7047 UINT64_C(0),
7048 UINT64_C(0),
7049 UINT64_C(0),
7050 UINT64_C(0),
7051 UINT64_C(0),
7052 UINT64_C(0),
7053 UINT64_C(0),
7054 UINT64_C(0),
7055 UINT64_C(0),
7056 UINT64_C(0),
7057 UINT64_C(0),
7058 UINT64_C(0),
7059 UINT64_C(0),
7060 UINT64_C(0),
7061 UINT64_C(0),
7062 UINT64_C(0),
7063 UINT64_C(0),
7064 UINT64_C(0),
7065 UINT64_C(0),
7066 UINT64_C(0),
7067 UINT64_C(0),
7068 UINT64_C(0),
7069 UINT64_C(0),
7070 UINT64_C(0),
7071 UINT64_C(0),
7072 UINT64_C(0),
7073 UINT64_C(0),
7074 UINT64_C(0),
7075 UINT64_C(0),
7076 UINT64_C(0),
7077 UINT64_C(0),
7078 UINT64_C(0),
7079 UINT64_C(0),
7080 UINT64_C(0),
7081 UINT64_C(0),
7082 UINT64_C(0),
7083 UINT64_C(0),
7084 UINT64_C(0),
7085 UINT64_C(0),
7086 UINT64_C(0),
7087 UINT64_C(0),
7088 UINT64_C(0),
7089 UINT64_C(0),
7090 UINT64_C(0),
7091 UINT64_C(0),
7092 UINT64_C(0),
7093 UINT64_C(0),
7094 UINT64_C(0),
7095 UINT64_C(0),
7096 UINT64_C(0),
7097 UINT64_C(0),
7098 UINT64_C(0),
7099 UINT64_C(0),
7100 UINT64_C(0),
7101 UINT64_C(0),
7102 UINT64_C(0),
7103 UINT64_C(0),
7104 UINT64_C(0),
7105 UINT64_C(0),
7106 UINT64_C(0),
7107 UINT64_C(0),
7108 UINT64_C(0),
7109 UINT64_C(0),
7110 UINT64_C(0),
7111 UINT64_C(0),
7112 UINT64_C(0),
7113 UINT64_C(0),
7114 UINT64_C(0),
7115 UINT64_C(0),
7116 UINT64_C(0),
7117 UINT64_C(0),
7118 UINT64_C(0),
7119 UINT64_C(0),
7120 UINT64_C(0),
7121 UINT64_C(0),
7122 UINT64_C(0),
7123 UINT64_C(0),
7124 UINT64_C(0),
7125 UINT64_C(0),
7126 UINT64_C(0),
7127 UINT64_C(0),
7128 UINT64_C(0),
7129 UINT64_C(0),
7130 UINT64_C(0),
7131 UINT64_C(0),
7132 UINT64_C(0),
7133 UINT64_C(0),
7134 UINT64_C(0),
7135 UINT64_C(0),
7136 UINT64_C(0),
7137 UINT64_C(0),
7138 UINT64_C(0),
7139 UINT64_C(0),
7140 UINT64_C(0),
7141 UINT64_C(0),
7142 UINT64_C(0),
7143 UINT64_C(0),
7144 UINT64_C(0),
7145 UINT64_C(0),
7146 UINT64_C(0),
7147 UINT64_C(0),
7148 UINT64_C(0),
7149 UINT64_C(0),
7150 UINT64_C(0),
7151 UINT64_C(0),
7152 UINT64_C(0),
7153 UINT64_C(0),
7154 UINT64_C(0),
7155 UINT64_C(0),
7156 UINT64_C(0),
7157 UINT64_C(0),
7158 UINT64_C(0),
7159 UINT64_C(0),
7160 UINT64_C(0),
7161 UINT64_C(0),
7162 UINT64_C(0),
7163 UINT64_C(0),
7164 UINT64_C(0),
7165 UINT64_C(0),
7166 UINT64_C(0),
7167 UINT64_C(0),
7168 UINT64_C(0),
7169 UINT64_C(0),
7170 UINT64_C(0),
7171 UINT64_C(0),
7172 UINT64_C(0),
7173 UINT64_C(0),
7174 UINT64_C(0),
7175 UINT64_C(0),
7176 UINT64_C(0),
7177 UINT64_C(0),
7178 UINT64_C(0),
7179 UINT64_C(0),
7180 UINT64_C(0),
7181 UINT64_C(0),
7182 UINT64_C(0),
7183 UINT64_C(0),
7184 UINT64_C(0),
7185 UINT64_C(0),
7186 UINT64_C(0),
7187 UINT64_C(0),
7188 UINT64_C(0),
7189 UINT64_C(0),
7190 UINT64_C(0),
7191 UINT64_C(0),
7192 UINT64_C(0),
7193 UINT64_C(0),
7194 UINT64_C(0),
7195 UINT64_C(0),
7196 UINT64_C(0),
7197 UINT64_C(0),
7198 UINT64_C(0),
7199 UINT64_C(0),
7200 UINT64_C(0),
7201 UINT64_C(0),
7202 UINT64_C(0),
7203 UINT64_C(0),
7204 UINT64_C(0),
7205 UINT64_C(0),
7206 UINT64_C(0),
7207 UINT64_C(0),
7208 UINT64_C(0),
7209 UINT64_C(0),
7210 UINT64_C(0),
7211 UINT64_C(0),
7212 UINT64_C(0),
7213 UINT64_C(0),
7214 UINT64_C(0),
7215 UINT64_C(0),
7216 UINT64_C(0),
7217 UINT64_C(0),
7218 UINT64_C(0),
7219 UINT64_C(0),
7220 UINT64_C(0),
7221 UINT64_C(0),
7222 UINT64_C(0),
7223 UINT64_C(0),
7224 UINT64_C(0),
7225 UINT64_C(0),
7226 UINT64_C(0),
7227 UINT64_C(0),
7228 UINT64_C(0),
7229 UINT64_C(0),
7230 UINT64_C(0),
7231 UINT64_C(0),
7232 UINT64_C(0),
7233 UINT64_C(0),
7234 UINT64_C(0),
7235 UINT64_C(0),
7236 UINT64_C(0),
7237 UINT64_C(0),
7238 UINT64_C(0),
7239 UINT64_C(0),
7240 UINT64_C(0),
7241 UINT64_C(0),
7242 UINT64_C(0),
7243 UINT64_C(0),
7244 UINT64_C(0),
7245 UINT64_C(0),
7246 UINT64_C(0),
7247 UINT64_C(0),
7248 UINT64_C(0),
7249 UINT64_C(0),
7250 UINT64_C(0),
7251 UINT64_C(0),
7252 UINT64_C(0),
7253 UINT64_C(0),
7254 UINT64_C(0),
7255 UINT64_C(0),
7256 UINT64_C(0),
7257 UINT64_C(0),
7258 UINT64_C(0),
7259 UINT64_C(0),
7260 UINT64_C(0),
7261 UINT64_C(0),
7262 UINT64_C(0),
7263 UINT64_C(0),
7264 UINT64_C(0),
7265 UINT64_C(0),
7266 UINT64_C(0),
7267 UINT64_C(0),
7268 UINT64_C(0),
7269 UINT64_C(0),
7270 UINT64_C(0),
7271 UINT64_C(0),
7272 UINT64_C(0),
7273 UINT64_C(0),
7274 UINT64_C(0),
7275 UINT64_C(0),
7276 UINT64_C(0),
7277 UINT64_C(0),
7278 UINT64_C(0),
7279 UINT64_C(0),
7280 UINT64_C(0),
7281 UINT64_C(0),
7282 UINT64_C(0),
7283 UINT64_C(0),
7284 UINT64_C(0),
7285 UINT64_C(0),
7286 UINT64_C(0),
7287 UINT64_C(0),
7288 UINT64_C(0),
7289 UINT64_C(0),
7290 UINT64_C(0),
7291 UINT64_C(0),
7292 UINT64_C(0),
7293 UINT64_C(0),
7294 UINT64_C(0),
7295 UINT64_C(0),
7296 UINT64_C(0),
7297 UINT64_C(0),
7298 UINT64_C(0),
7299 UINT64_C(0),
7300 UINT64_C(0),
7301 UINT64_C(0),
7302 UINT64_C(0),
7303 UINT64_C(0),
7304 UINT64_C(0),
7305 UINT64_C(0),
7306 UINT64_C(0),
7307 UINT64_C(0),
7308 UINT64_C(0),
7309 UINT64_C(0),
7310 UINT64_C(0),
7311 UINT64_C(0),
7312 UINT64_C(0),
7313 UINT64_C(0),
7314 UINT64_C(0),
7315 UINT64_C(0),
7316 UINT64_C(0),
7317 UINT64_C(0),
7318 UINT64_C(0),
7319 UINT64_C(0),
7320 UINT64_C(0),
7321 UINT64_C(0),
7322 UINT64_C(0),
7323 UINT64_C(0),
7324 UINT64_C(0),
7325 UINT64_C(0),
7326 UINT64_C(0),
7327 UINT64_C(0),
7328 UINT64_C(0),
7329 UINT64_C(0),
7330 UINT64_C(0),
7331 UINT64_C(0),
7332 UINT64_C(0),
7333 UINT64_C(0),
7334 UINT64_C(0),
7335 UINT64_C(0),
7336 UINT64_C(0),
7337 UINT64_C(0),
7338 UINT64_C(0),
7339 UINT64_C(0),
7340 UINT64_C(0),
7341 UINT64_C(0),
7342 UINT64_C(0),
7343 UINT64_C(0),
7344 UINT64_C(0),
7345 UINT64_C(0),
7346 UINT64_C(0),
7347 UINT64_C(0),
7348 UINT64_C(0),
7349 UINT64_C(0),
7350 UINT64_C(0),
7351 UINT64_C(0),
7352 UINT64_C(0),
7353 UINT64_C(0),
7354 UINT64_C(0),
7355 UINT64_C(0),
7356 UINT64_C(0),
7357 UINT64_C(0),
7358 UINT64_C(0),
7359 UINT64_C(0),
7360 UINT64_C(0),
7361 UINT64_C(0),
7362 UINT64_C(0),
7363 UINT64_C(0),
7364 UINT64_C(0),
7365 UINT64_C(0),
7366 UINT64_C(0),
7367 UINT64_C(0),
7368 UINT64_C(0),
7369 UINT64_C(0),
7370 UINT64_C(0),
7371 UINT64_C(0),
7372 UINT64_C(0),
7373 UINT64_C(0),
7374 UINT64_C(0),
7375 UINT64_C(0),
7376 UINT64_C(0),
7377 UINT64_C(0),
7378 UINT64_C(0),
7379 UINT64_C(0),
7380 UINT64_C(0),
7381 UINT64_C(0),
7382 UINT64_C(0),
7383 UINT64_C(0),
7384 UINT64_C(0),
7385 UINT64_C(0),
7386 UINT64_C(0),
7387 UINT64_C(0),
7388 UINT64_C(0),
7389 UINT64_C(0),
7390 UINT64_C(0),
7391 UINT64_C(0),
7392 UINT64_C(0),
7393 UINT64_C(0),
7394 UINT64_C(0),
7395 UINT64_C(0),
7396 UINT64_C(0),
7397 UINT64_C(0),
7398 UINT64_C(0),
7399 UINT64_C(0),
7400 UINT64_C(0),
7401 UINT64_C(0),
7402 UINT64_C(0),
7403 UINT64_C(0),
7404 UINT64_C(0),
7405 UINT64_C(0),
7406 UINT64_C(0),
7407 UINT64_C(0),
7408 UINT64_C(0),
7409 UINT64_C(0),
7410 UINT64_C(0),
7411 UINT64_C(0),
7412 UINT64_C(0),
7413 UINT64_C(0),
7414 UINT64_C(0),
7415 UINT64_C(0),
7416 UINT64_C(0),
7417 UINT64_C(0),
7418 UINT64_C(0),
7419 UINT64_C(0),
7420 UINT64_C(0),
7421 UINT64_C(0),
7422 UINT64_C(0),
7423 UINT64_C(0),
7424 UINT64_C(0),
7425 UINT64_C(0),
7426 UINT64_C(0),
7427 UINT64_C(0),
7428 UINT64_C(0),
7429 UINT64_C(0),
7430 UINT64_C(0),
7431 UINT64_C(0),
7432 UINT64_C(0),
7433 UINT64_C(0),
7434 UINT64_C(0),
7435 UINT64_C(0),
7436 UINT64_C(0),
7437 UINT64_C(0),
7438 UINT64_C(0),
7439 UINT64_C(0),
7440 UINT64_C(0),
7441 UINT64_C(0),
7442 UINT64_C(0),
7443 UINT64_C(0),
7444 UINT64_C(0),
7445 UINT64_C(0),
7446 UINT64_C(0),
7447 UINT64_C(0),
7448 UINT64_C(0),
7449 UINT64_C(0),
7450 UINT64_C(0),
7451 UINT64_C(0),
7452 UINT64_C(0),
7453 UINT64_C(0),
7454 UINT64_C(0),
7455 UINT64_C(0),
7456 UINT64_C(0),
7457 UINT64_C(0),
7458 UINT64_C(0),
7459 UINT64_C(0),
7460 UINT64_C(0),
7461 UINT64_C(0),
7462 UINT64_C(0),
7463 UINT64_C(0),
7464 UINT64_C(0),
7465 UINT64_C(0),
7466 UINT64_C(0),
7467 UINT64_C(0),
7468 UINT64_C(0),
7469 UINT64_C(0),
7470 UINT64_C(0),
7471 UINT64_C(0),
7472 UINT64_C(0),
7473 UINT64_C(0),
7474 UINT64_C(0),
7475 UINT64_C(0),
7476 UINT64_C(0),
7477 UINT64_C(0),
7478 UINT64_C(0),
7479 UINT64_C(0),
7480 UINT64_C(0),
7481 UINT64_C(0),
7482 UINT64_C(0),
7483 UINT64_C(0),
7484 UINT64_C(0),
7485 UINT64_C(0),
7486 UINT64_C(0),
7487 UINT64_C(0),
7488 UINT64_C(0),
7489 UINT64_C(0),
7490 UINT64_C(0),
7491 UINT64_C(0),
7492 UINT64_C(0),
7493 UINT64_C(0),
7494 UINT64_C(0),
7495 UINT64_C(0),
7496 UINT64_C(0),
7497 UINT64_C(0),
7498 UINT64_C(0),
7499 UINT64_C(0),
7500 UINT64_C(0),
7501 UINT64_C(0),
7502 UINT64_C(0),
7503 UINT64_C(0),
7504 UINT64_C(0),
7505 UINT64_C(0),
7506 UINT64_C(0),
7507 UINT64_C(0),
7508 UINT64_C(0),
7509 UINT64_C(0),
7510 UINT64_C(0),
7511 UINT64_C(0),
7512 UINT64_C(0),
7513 UINT64_C(0),
7514 UINT64_C(0),
7515 UINT64_C(0),
7516 UINT64_C(0),
7517 UINT64_C(0),
7518 UINT64_C(0),
7519 UINT64_C(0),
7520 UINT64_C(0),
7521 UINT64_C(0),
7522 UINT64_C(0),
7523 UINT64_C(0),
7524 UINT64_C(0),
7525 UINT64_C(0),
7526 UINT64_C(0),
7527 UINT64_C(0),
7528 UINT64_C(0),
7529 UINT64_C(0),
7530 UINT64_C(0),
7531 UINT64_C(0),
7532 UINT64_C(0),
7533 UINT64_C(0),
7534 UINT64_C(0),
7535 UINT64_C(0),
7536 UINT64_C(0),
7537 UINT64_C(0),
7538 UINT64_C(0),
7539 UINT64_C(0),
7540 UINT64_C(0),
7541 UINT64_C(0),
7542 UINT64_C(0),
7543 UINT64_C(0),
7544 UINT64_C(0),
7545 UINT64_C(0),
7546 UINT64_C(0),
7547 UINT64_C(0),
7548 UINT64_C(0),
7549 UINT64_C(0),
7550 UINT64_C(0),
7551 UINT64_C(0),
7552 UINT64_C(0),
7553 UINT64_C(0),
7554 UINT64_C(0),
7555 UINT64_C(0),
7556 UINT64_C(0),
7557 UINT64_C(0),
7558 UINT64_C(0),
7559 UINT64_C(0),
7560 UINT64_C(0),
7561 UINT64_C(0),
7562 UINT64_C(0),
7563 UINT64_C(0),
7564 UINT64_C(0),
7565 UINT64_C(0),
7566 UINT64_C(0),
7567 UINT64_C(0),
7568 UINT64_C(0),
7569 UINT64_C(0),
7570 UINT64_C(0),
7571 UINT64_C(0),
7572 UINT64_C(0),
7573 UINT64_C(0),
7574 UINT64_C(0),
7575 UINT64_C(0),
7576 UINT64_C(0),
7577 UINT64_C(0),
7578 UINT64_C(0),
7579 UINT64_C(0),
7580 UINT64_C(0),
7581 UINT64_C(0),
7582 UINT64_C(0),
7583 UINT64_C(0),
7584 UINT64_C(0),
7585 UINT64_C(0),
7586 UINT64_C(0),
7587 UINT64_C(0),
7588 UINT64_C(0),
7589 UINT64_C(0),
7590 UINT64_C(0),
7591 UINT64_C(0),
7592 UINT64_C(0),
7593 UINT64_C(0),
7594 UINT64_C(0),
7595 UINT64_C(0),
7596 UINT64_C(0),
7597 UINT64_C(0),
7598 UINT64_C(0),
7599 UINT64_C(0),
7600 UINT64_C(0),
7601 UINT64_C(0),
7602 UINT64_C(0),
7603 UINT64_C(0),
7604 UINT64_C(0),
7605 UINT64_C(0),
7606 UINT64_C(0),
7607 UINT64_C(0),
7608 UINT64_C(0),
7609 UINT64_C(0),
7610 UINT64_C(0),
7611 UINT64_C(0),
7612 UINT64_C(0),
7613 UINT64_C(0),
7614 UINT64_C(0),
7615 UINT64_C(0),
7616 UINT64_C(0),
7617 UINT64_C(0),
7618 UINT64_C(0),
7619 UINT64_C(0),
7620 UINT64_C(0),
7621 UINT64_C(0),
7622 UINT64_C(0),
7623 UINT64_C(0),
7624 UINT64_C(0),
7625 UINT64_C(0),
7626 UINT64_C(0),
7627 UINT64_C(0),
7628 UINT64_C(0),
7629 UINT64_C(0),
7630 UINT64_C(0),
7631 UINT64_C(0),
7632 UINT64_C(0),
7633 UINT64_C(0),
7634 UINT64_C(0),
7635 UINT64_C(0),
7636 UINT64_C(0),
7637 UINT64_C(0),
7638 UINT64_C(0),
7639 UINT64_C(0),
7640 UINT64_C(0),
7641 UINT64_C(0),
7642 UINT64_C(0),
7643 UINT64_C(0),
7644 UINT64_C(0),
7645 UINT64_C(0),
7646 UINT64_C(0),
7647 UINT64_C(0),
7648 UINT64_C(0),
7649 UINT64_C(0),
7650 UINT64_C(0),
7651 UINT64_C(0),
7652 UINT64_C(0),
7653 UINT64_C(0),
7654 UINT64_C(0),
7655 UINT64_C(0),
7656 UINT64_C(0),
7657 UINT64_C(0),
7658 UINT64_C(0),
7659 UINT64_C(0),
7660 UINT64_C(0),
7661 UINT64_C(0),
7662 UINT64_C(0),
7663 UINT64_C(0),
7664 UINT64_C(0),
7665 UINT64_C(0),
7666 UINT64_C(0),
7667 UINT64_C(0),
7668 UINT64_C(0),
7669 UINT64_C(0),
7670 UINT64_C(0),
7671 UINT64_C(0),
7672 UINT64_C(0),
7673 UINT64_C(0),
7674 UINT64_C(0),
7675 UINT64_C(0),
7676 UINT64_C(0),
7677 UINT64_C(0),
7678 UINT64_C(0),
7679 UINT64_C(0),
7680 UINT64_C(0),
7681 UINT64_C(0),
7682 UINT64_C(0),
7683 UINT64_C(0),
7684 UINT64_C(0),
7685 UINT64_C(0),
7686 UINT64_C(0),
7687 UINT64_C(0),
7688 UINT64_C(0),
7689 UINT64_C(0),
7690 UINT64_C(0),
7691 UINT64_C(0),
7692 UINT64_C(0),
7693 UINT64_C(0),
7694 UINT64_C(0),
7695 UINT64_C(0),
7696 UINT64_C(0),
7697 UINT64_C(0),
7698 UINT64_C(0),
7699 UINT64_C(0),
7700 UINT64_C(0),
7701 UINT64_C(0),
7702 UINT64_C(0),
7703 UINT64_C(0),
7704 UINT64_C(0),
7705 UINT64_C(0),
7706 UINT64_C(0),
7707 UINT64_C(0),
7708 UINT64_C(0),
7709 UINT64_C(0),
7710 UINT64_C(0),
7711 UINT64_C(0),
7712 UINT64_C(0),
7713 UINT64_C(0),
7714 UINT64_C(0),
7715 UINT64_C(0),
7716 UINT64_C(0),
7717 UINT64_C(0),
7718 UINT64_C(0),
7719 UINT64_C(0),
7720 UINT64_C(0),
7721 UINT64_C(0),
7722 UINT64_C(0),
7723 UINT64_C(0),
7724 UINT64_C(0),
7725 UINT64_C(0),
7726 UINT64_C(0),
7727 UINT64_C(0),
7728 UINT64_C(0),
7729 UINT64_C(0),
7730 UINT64_C(0),
7731 UINT64_C(0),
7732 UINT64_C(0),
7733 UINT64_C(0),
7734 UINT64_C(0),
7735 UINT64_C(0),
7736 UINT64_C(0),
7737 UINT64_C(0),
7738 UINT64_C(0),
7739 UINT64_C(0),
7740 UINT64_C(0),
7741 UINT64_C(0),
7742 UINT64_C(0),
7743 UINT64_C(0),
7744 UINT64_C(0),
7745 UINT64_C(0),
7746 UINT64_C(0),
7747 UINT64_C(0),
7748 UINT64_C(0),
7749 UINT64_C(0),
7750 UINT64_C(0),
7751 UINT64_C(0),
7752 UINT64_C(0),
7753 UINT64_C(0),
7754 UINT64_C(0),
7755 UINT64_C(0),
7756 UINT64_C(0),
7757 UINT64_C(0),
7758 UINT64_C(0),
7759 UINT64_C(0),
7760 UINT64_C(0),
7761 UINT64_C(0),
7762 UINT64_C(0),
7763 UINT64_C(0),
7764 UINT64_C(0),
7765 UINT64_C(0),
7766 UINT64_C(0),
7767 UINT64_C(0),
7768 UINT64_C(0),
7769 UINT64_C(0),
7770 UINT64_C(0),
7771 UINT64_C(0),
7772 UINT64_C(0),
7773 UINT64_C(0),
7774 UINT64_C(0),
7775 UINT64_C(0),
7776 UINT64_C(0),
7777 UINT64_C(0),
7778 UINT64_C(0),
7779 UINT64_C(0),
7780 UINT64_C(0),
7781 UINT64_C(0),
7782 UINT64_C(0),
7783 UINT64_C(0),
7784 UINT64_C(0),
7785 UINT64_C(0),
7786 UINT64_C(0),
7787 UINT64_C(0),
7788 UINT64_C(0),
7789 UINT64_C(0),
7790 UINT64_C(0),
7791 UINT64_C(0),
7792 UINT64_C(0),
7793 UINT64_C(0),
7794 UINT64_C(0),
7795 UINT64_C(0),
7796 UINT64_C(0),
7797 UINT64_C(0),
7798 UINT64_C(0),
7799 UINT64_C(0),
7800 UINT64_C(0),
7801 UINT64_C(0),
7802 UINT64_C(0),
7803 UINT64_C(0),
7804 UINT64_C(0),
7805 UINT64_C(0),
7806 UINT64_C(0),
7807 UINT64_C(0),
7808 UINT64_C(0),
7809 UINT64_C(0),
7810 UINT64_C(0),
7811 UINT64_C(0),
7812 UINT64_C(0),
7813 UINT64_C(0),
7814 UINT64_C(0),
7815 UINT64_C(0),
7816 UINT64_C(0),
7817 UINT64_C(0),
7818 UINT64_C(0),
7819 UINT64_C(0),
7820 UINT64_C(0),
7821 UINT64_C(0),
7822 UINT64_C(0),
7823 UINT64_C(0),
7824 UINT64_C(0),
7825 UINT64_C(0),
7826 UINT64_C(0),
7827 UINT64_C(0),
7828 UINT64_C(0),
7829 UINT64_C(0),
7830 UINT64_C(0),
7831 UINT64_C(0),
7832 UINT64_C(0),
7833 UINT64_C(0),
7834 UINT64_C(0),
7835 UINT64_C(0),
7836 UINT64_C(0),
7837 UINT64_C(0),
7838 UINT64_C(0),
7839 UINT64_C(0),
7840 UINT64_C(0),
7841 UINT64_C(0),
7842 UINT64_C(0),
7843 UINT64_C(0),
7844 UINT64_C(0),
7845 UINT64_C(0),
7846 UINT64_C(0),
7847 UINT64_C(0),
7848 UINT64_C(0),
7849 UINT64_C(0),
7850 UINT64_C(0),
7851 UINT64_C(0),
7852 UINT64_C(0),
7853 UINT64_C(0),
7854 UINT64_C(0),
7855 UINT64_C(0),
7856 UINT64_C(0),
7857 UINT64_C(0),
7858 UINT64_C(0),
7859 UINT64_C(0),
7860 UINT64_C(0),
7861 UINT64_C(0),
7862 UINT64_C(0),
7863 UINT64_C(0),
7864 UINT64_C(0),
7865 UINT64_C(0),
7866 UINT64_C(0),
7867 UINT64_C(0),
7868 UINT64_C(0),
7869 UINT64_C(0),
7870 UINT64_C(0),
7871 UINT64_C(0),
7872 UINT64_C(0),
7873 UINT64_C(0),
7874 UINT64_C(0),
7875 UINT64_C(0),
7876 UINT64_C(0),
7877 UINT64_C(0),
7878 UINT64_C(0),
7879 UINT64_C(0),
7880 UINT64_C(0),
7881 UINT64_C(0),
7882 UINT64_C(0),
7883 UINT64_C(0),
7884 UINT64_C(0),
7885 UINT64_C(0),
7886 UINT64_C(0),
7887 UINT64_C(0),
7888 UINT64_C(0),
7889 UINT64_C(0),
7890 UINT64_C(0),
7891 UINT64_C(0),
7892 UINT64_C(0),
7893 UINT64_C(0),
7894 UINT64_C(0),
7895 UINT64_C(0),
7896 UINT64_C(0),
7897 UINT64_C(0),
7898 UINT64_C(0),
7899 UINT64_C(0),
7900 UINT64_C(0),
7901 UINT64_C(0),
7902 UINT64_C(0),
7903 UINT64_C(0),
7904 UINT64_C(0),
7905 UINT64_C(0),
7906 UINT64_C(0),
7907 UINT64_C(0),
7908 UINT64_C(0),
7909 UINT64_C(0),
7910 UINT64_C(0),
7911 UINT64_C(0),
7912 UINT64_C(0),
7913 UINT64_C(0),
7914 UINT64_C(0),
7915 UINT64_C(0),
7916 UINT64_C(0),
7917 UINT64_C(0),
7918 UINT64_C(0),
7919 UINT64_C(0),
7920 UINT64_C(0),
7921 UINT64_C(0),
7922 UINT64_C(0),
7923 UINT64_C(0),
7924 UINT64_C(0),
7925 UINT64_C(0),
7926 UINT64_C(0),
7927 UINT64_C(0),
7928 UINT64_C(0),
7929 UINT64_C(0),
7930 UINT64_C(0),
7931 UINT64_C(0),
7932 UINT64_C(0),
7933 UINT64_C(0),
7934 UINT64_C(0),
7935 UINT64_C(0),
7936 UINT64_C(0),
7937 UINT64_C(0),
7938 UINT64_C(0),
7939 UINT64_C(0),
7940 UINT64_C(0),
7941 UINT64_C(0),
7942 UINT64_C(0),
7943 UINT64_C(0),
7944 UINT64_C(0),
7945 UINT64_C(0),
7946 UINT64_C(0),
7947 UINT64_C(0),
7948 UINT64_C(0),
7949 UINT64_C(0),
7950 UINT64_C(0),
7951 UINT64_C(0),
7952 UINT64_C(0),
7953 UINT64_C(0),
7954 UINT64_C(0),
7955 UINT64_C(0),
7956 UINT64_C(0),
7957 UINT64_C(0),
7958 UINT64_C(0),
7959 UINT64_C(0),
7960 UINT64_C(0),
7961 UINT64_C(0),
7962 UINT64_C(0),
7963 UINT64_C(0),
7964 UINT64_C(0),
7965 UINT64_C(0),
7966 UINT64_C(0),
7967 UINT64_C(0),
7968 UINT64_C(0),
7969 UINT64_C(0),
7970 UINT64_C(0),
7971 UINT64_C(0),
7972 UINT64_C(0),
7973 UINT64_C(0),
7974 UINT64_C(0),
7975 UINT64_C(0),
7976 UINT64_C(0),
7977 UINT64_C(0),
7978 UINT64_C(0),
7979 UINT64_C(0),
7980 UINT64_C(0),
7981 UINT64_C(0),
7982 UINT64_C(0),
7983 UINT64_C(0),
7984 UINT64_C(0),
7985 UINT64_C(0),
7986 UINT64_C(0),
7987 UINT64_C(0),
7988 UINT64_C(0),
7989 UINT64_C(0),
7990 UINT64_C(0),
7991 UINT64_C(0),
7992 UINT64_C(0),
7993 UINT64_C(0),
7994 UINT64_C(0),
7995 UINT64_C(0),
7996 UINT64_C(0),
7997 UINT64_C(0),
7998 UINT64_C(0),
7999 UINT64_C(0),
8000 UINT64_C(0),
8001 UINT64_C(0),
8002 UINT64_C(0),
8003 UINT64_C(0),
8004 UINT64_C(0),
8005 UINT64_C(0),
8006 UINT64_C(0),
8007 UINT64_C(0),
8008 UINT64_C(0),
8009 UINT64_C(0),
8010 UINT64_C(0),
8011 UINT64_C(0),
8012 UINT64_C(0),
8013 UINT64_C(0),
8014 UINT64_C(0),
8015 UINT64_C(0),
8016 UINT64_C(0),
8017 UINT64_C(0),
8018 UINT64_C(0),
8019 UINT64_C(0),
8020 UINT64_C(0),
8021 UINT64_C(0),
8022 UINT64_C(0),
8023 UINT64_C(0),
8024 UINT64_C(0),
8025 UINT64_C(0),
8026 UINT64_C(0),
8027 UINT64_C(0),
8028 UINT64_C(0),
8029 UINT64_C(0),
8030 UINT64_C(0),
8031 UINT64_C(0),
8032 UINT64_C(0),
8033 UINT64_C(0),
8034 UINT64_C(0),
8035 UINT64_C(0),
8036 UINT64_C(0),
8037 UINT64_C(0),
8038 UINT64_C(0),
8039 UINT64_C(0),
8040 UINT64_C(0),
8041 UINT64_C(0),
8042 UINT64_C(0),
8043 UINT64_C(0),
8044 UINT64_C(0),
8045 UINT64_C(0),
8046 UINT64_C(0),
8047 UINT64_C(0),
8048 UINT64_C(0),
8049 UINT64_C(0),
8050 UINT64_C(0),
8051 UINT64_C(0),
8052 UINT64_C(0),
8053 UINT64_C(0),
8054 UINT64_C(0),
8055 UINT64_C(0),
8056 UINT64_C(0),
8057 UINT64_C(0),
8058 UINT64_C(0),
8059 UINT64_C(0),
8060 UINT64_C(0),
8061 UINT64_C(0),
8062 UINT64_C(0),
8063 UINT64_C(0),
8064 UINT64_C(0),
8065 UINT64_C(0),
8066 UINT64_C(0),
8067 UINT64_C(0),
8068 UINT64_C(0),
8069 UINT64_C(0),
8070 UINT64_C(0),
8071 UINT64_C(0),
8072 UINT64_C(0),
8073 UINT64_C(0),
8074 UINT64_C(0),
8075 UINT64_C(0),
8076 UINT64_C(0),
8077 UINT64_C(0),
8078 UINT64_C(0),
8079 UINT64_C(0),
8080 UINT64_C(0),
8081 UINT64_C(0),
8082 UINT64_C(0),
8083 UINT64_C(0),
8084 UINT64_C(0),
8085 UINT64_C(0),
8086 UINT64_C(0),
8087 UINT64_C(0),
8088 UINT64_C(0),
8089 UINT64_C(0),
8090 UINT64_C(0),
8091 UINT64_C(0),
8092 UINT64_C(0),
8093 UINT64_C(0),
8094 UINT64_C(0),
8095 UINT64_C(0),
8096 UINT64_C(0),
8097 UINT64_C(0),
8098 UINT64_C(0),
8099 UINT64_C(0),
8100 UINT64_C(0),
8101 UINT64_C(0),
8102 UINT64_C(0),
8103 UINT64_C(0),
8104 UINT64_C(0),
8105 UINT64_C(0),
8106 UINT64_C(0),
8107 UINT64_C(0),
8108 UINT64_C(0),
8109 UINT64_C(0),
8110 UINT64_C(0),
8111 UINT64_C(0),
8112 UINT64_C(0),
8113 UINT64_C(0),
8114 UINT64_C(0),
8115 UINT64_C(0),
8116 UINT64_C(0),
8117 UINT64_C(0),
8118 UINT64_C(0),
8119 UINT64_C(0),
8120 UINT64_C(0),
8121 UINT64_C(0),
8122 UINT64_C(0),
8123 UINT64_C(0),
8124 UINT64_C(0),
8125 UINT64_C(0),
8126 UINT64_C(0),
8127 UINT64_C(0),
8128 UINT64_C(0),
8129 UINT64_C(0),
8130 UINT64_C(0),
8131 UINT64_C(0),
8132 UINT64_C(0),
8133 UINT64_C(0),
8134 UINT64_C(0),
8135 UINT64_C(0),
8136 UINT64_C(0),
8137 UINT64_C(0),
8138 UINT64_C(0),
8139 UINT64_C(0),
8140 UINT64_C(0),
8141 UINT64_C(0),
8142 UINT64_C(0),
8143 UINT64_C(0),
8144 UINT64_C(0),
8145 UINT64_C(0),
8146 UINT64_C(0),
8147 UINT64_C(0),
8148 UINT64_C(0),
8149 UINT64_C(0),
8150 UINT64_C(0),
8151 UINT64_C(0),
8152 UINT64_C(0),
8153 UINT64_C(0),
8154 UINT64_C(0),
8155 UINT64_C(0),
8156 UINT64_C(0),
8157 UINT64_C(0),
8158 UINT64_C(0),
8159 UINT64_C(0),
8160 UINT64_C(0),
8161 UINT64_C(0),
8162 UINT64_C(0),
8163 UINT64_C(0),
8164 UINT64_C(0),
8165 UINT64_C(0),
8166 UINT64_C(0),
8167 UINT64_C(0),
8168 UINT64_C(0),
8169 UINT64_C(0),
8170 UINT64_C(0),
8171 UINT64_C(0),
8172 UINT64_C(0),
8173 UINT64_C(0),
8174 UINT64_C(0),
8175 UINT64_C(0),
8176 UINT64_C(0),
8177 UINT64_C(0),
8178 UINT64_C(0),
8179 UINT64_C(0),
8180 UINT64_C(0),
8181 UINT64_C(0),
8182 UINT64_C(0),
8183 UINT64_C(0),
8184 UINT64_C(0),
8185 UINT64_C(0),
8186 UINT64_C(0),
8187 UINT64_C(0),
8188 UINT64_C(0),
8189 UINT64_C(0),
8190 UINT64_C(0),
8191 UINT64_C(0),
8192 UINT64_C(0),
8193 UINT64_C(0),
8194 UINT64_C(0),
8195 UINT64_C(0),
8196 UINT64_C(0),
8197 UINT64_C(0),
8198 UINT64_C(0),
8199 UINT64_C(0),
8200 UINT64_C(0),
8201 UINT64_C(0),
8202 UINT64_C(0),
8203 UINT64_C(0),
8204 UINT64_C(0),
8205 UINT64_C(0),
8206 UINT64_C(0),
8207 UINT64_C(0),
8208 UINT64_C(0),
8209 UINT64_C(0),
8210 UINT64_C(0),
8211 UINT64_C(0),
8212 UINT64_C(0),
8213 UINT64_C(0),
8214 UINT64_C(0),
8215 UINT64_C(0),
8216 UINT64_C(0),
8217 UINT64_C(0),
8218 UINT64_C(0),
8219 UINT64_C(0),
8220 UINT64_C(0),
8221 UINT64_C(0),
8222 UINT64_C(0),
8223 UINT64_C(0),
8224 UINT64_C(0),
8225 UINT64_C(0),
8226 UINT64_C(0),
8227 UINT64_C(0),
8228 UINT64_C(0),
8229 UINT64_C(0),
8230 UINT64_C(0),
8231 UINT64_C(0),
8232 UINT64_C(0),
8233 UINT64_C(0),
8234 UINT64_C(0),
8235 UINT64_C(0),
8236 UINT64_C(0),
8237 UINT64_C(0),
8238 UINT64_C(0),
8239 UINT64_C(0),
8240 UINT64_C(0),
8241 UINT64_C(0),
8242 UINT64_C(0),
8243 UINT64_C(0),
8244 UINT64_C(0),
8245 UINT64_C(0),
8246 UINT64_C(0),
8247 UINT64_C(0),
8248 UINT64_C(0),
8249 UINT64_C(0),
8250 UINT64_C(0),
8251 UINT64_C(0),
8252 UINT64_C(0),
8253 UINT64_C(0),
8254 UINT64_C(0),
8255 UINT64_C(0),
8256 UINT64_C(0),
8257 UINT64_C(0),
8258 UINT64_C(0),
8259 UINT64_C(0),
8260 UINT64_C(0),
8261 UINT64_C(0),
8262 UINT64_C(0),
8263 UINT64_C(0),
8264 UINT64_C(0),
8265 UINT64_C(0),
8266 UINT64_C(0),
8267 UINT64_C(0),
8268 UINT64_C(0),
8269 UINT64_C(0),
8270 UINT64_C(0),
8271 UINT64_C(0),
8272 UINT64_C(0),
8273 UINT64_C(0),
8274 UINT64_C(0),
8275 UINT64_C(0),
8276 UINT64_C(0),
8277 UINT64_C(0),
8278 UINT64_C(0),
8279 UINT64_C(0),
8280 UINT64_C(0),
8281 UINT64_C(0),
8282 UINT64_C(0),
8283 UINT64_C(0),
8284 UINT64_C(0),
8285 UINT64_C(0),
8286 UINT64_C(0),
8287 UINT64_C(0),
8288 UINT64_C(0),
8289 UINT64_C(0),
8290 UINT64_C(0),
8291 UINT64_C(0),
8292 UINT64_C(0),
8293 UINT64_C(0),
8294 UINT64_C(0),
8295 UINT64_C(0),
8296 UINT64_C(0),
8297 UINT64_C(0),
8298 UINT64_C(0),
8299 UINT64_C(0),
8300 UINT64_C(0),
8301 UINT64_C(0),
8302 UINT64_C(0),
8303 UINT64_C(0),
8304 UINT64_C(0),
8305 UINT64_C(0),
8306 UINT64_C(0),
8307 UINT64_C(0),
8308 UINT64_C(0),
8309 UINT64_C(0),
8310 UINT64_C(0),
8311 UINT64_C(0),
8312 UINT64_C(0),
8313 UINT64_C(0),
8314 UINT64_C(0),
8315 UINT64_C(0),
8316 UINT64_C(0),
8317 UINT64_C(0),
8318 UINT64_C(0),
8319 UINT64_C(0),
8320 UINT64_C(0),
8321 UINT64_C(0),
8322 UINT64_C(0),
8323 UINT64_C(0),
8324 UINT64_C(0),
8325 UINT64_C(0),
8326 UINT64_C(0),
8327 UINT64_C(0),
8328 UINT64_C(0),
8329 UINT64_C(0),
8330 UINT64_C(0),
8331 UINT64_C(0),
8332 UINT64_C(0),
8333 UINT64_C(0),
8334 UINT64_C(0),
8335 UINT64_C(0),
8336 UINT64_C(0),
8337 UINT64_C(0),
8338 UINT64_C(0),
8339 UINT64_C(0),
8340 UINT64_C(0),
8341 UINT64_C(0),
8342 UINT64_C(0),
8343 UINT64_C(0),
8344 UINT64_C(0),
8345 UINT64_C(0),
8346 UINT64_C(0),
8347 UINT64_C(0),
8348 UINT64_C(0),
8349 UINT64_C(0),
8350 UINT64_C(0),
8351 UINT64_C(0),
8352 UINT64_C(0),
8353 UINT64_C(0),
8354 UINT64_C(0),
8355 UINT64_C(0),
8356 UINT64_C(0),
8357 UINT64_C(0),
8358 UINT64_C(0),
8359 UINT64_C(0),
8360 UINT64_C(0),
8361 UINT64_C(0),
8362 UINT64_C(0),
8363 UINT64_C(0),
8364 UINT64_C(0),
8365 UINT64_C(0),
8366 UINT64_C(0),
8367 UINT64_C(0),
8368 UINT64_C(0),
8369 UINT64_C(0),
8370 UINT64_C(0),
8371 UINT64_C(0),
8372 UINT64_C(0),
8373 UINT64_C(0),
8374 UINT64_C(0),
8375 UINT64_C(0),
8376 UINT64_C(0),
8377 UINT64_C(0),
8378 UINT64_C(0),
8379 UINT64_C(0),
8380 UINT64_C(0),
8381 UINT64_C(0),
8382 UINT64_C(0),
8383 UINT64_C(0),
8384 UINT64_C(0),
8385 UINT64_C(0),
8386 UINT64_C(0),
8387 UINT64_C(0),
8388 UINT64_C(0),
8389 UINT64_C(0),
8390 UINT64_C(0),
8391 UINT64_C(0),
8392 UINT64_C(0),
8393 UINT64_C(0),
8394 UINT64_C(0),
8395 UINT64_C(0),
8396 UINT64_C(0),
8397 UINT64_C(0),
8398 UINT64_C(0),
8399 UINT64_C(0),
8400 UINT64_C(0),
8401 UINT64_C(0),
8402 UINT64_C(0),
8403 UINT64_C(0),
8404 UINT64_C(0),
8405 UINT64_C(0),
8406 UINT64_C(0),
8407 UINT64_C(0),
8408 UINT64_C(0),
8409 UINT64_C(0),
8410 UINT64_C(0),
8411 UINT64_C(0),
8412 UINT64_C(0),
8413 UINT64_C(0),
8414 UINT64_C(0),
8415 UINT64_C(0),
8416 UINT64_C(0),
8417 UINT64_C(0),
8418 UINT64_C(0),
8419 UINT64_C(0),
8420 UINT64_C(0),
8421 UINT64_C(0),
8422 UINT64_C(0),
8423 UINT64_C(0),
8424 UINT64_C(0),
8425 UINT64_C(0),
8426 UINT64_C(0),
8427 UINT64_C(0),
8428 UINT64_C(0),
8429 UINT64_C(0),
8430 UINT64_C(0),
8431 UINT64_C(0),
8432 UINT64_C(0),
8433 UINT64_C(0),
8434 UINT64_C(0),
8435 UINT64_C(0),
8436 UINT64_C(0),
8437 UINT64_C(0),
8438 UINT64_C(0),
8439 UINT64_C(0),
8440 UINT64_C(0),
8441 UINT64_C(0),
8442 UINT64_C(0),
8443 UINT64_C(0),
8444 UINT64_C(0),
8445 UINT64_C(0),
8446 UINT64_C(0),
8447 UINT64_C(0),
8448 UINT64_C(0),
8449 UINT64_C(0),
8450 UINT64_C(0),
8451 UINT64_C(0),
8452 UINT64_C(0),
8453 UINT64_C(0),
8454 UINT64_C(0),
8455 UINT64_C(0),
8456 UINT64_C(0),
8457 UINT64_C(0),
8458 UINT64_C(0),
8459 UINT64_C(0),
8460 UINT64_C(0),
8461 UINT64_C(0),
8462 UINT64_C(0),
8463 UINT64_C(0),
8464 UINT64_C(0),
8465 UINT64_C(0),
8466 UINT64_C(0),
8467 UINT64_C(0),
8468 UINT64_C(0),
8469 UINT64_C(0),
8470 UINT64_C(0),
8471 UINT64_C(0),
8472 UINT64_C(0),
8473 UINT64_C(0),
8474 UINT64_C(0),
8475 UINT64_C(0),
8476 UINT64_C(0),
8477 UINT64_C(0),
8478 UINT64_C(0),
8479 UINT64_C(0),
8480 UINT64_C(0),
8481 UINT64_C(0),
8482 UINT64_C(0),
8483 UINT64_C(0),
8484 UINT64_C(0),
8485 UINT64_C(0),
8486 UINT64_C(0),
8487 UINT64_C(0),
8488 UINT64_C(0),
8489 UINT64_C(0),
8490 UINT64_C(0),
8491 UINT64_C(0),
8492 UINT64_C(0),
8493 UINT64_C(0),
8494 UINT64_C(0),
8495 UINT64_C(0),
8496 UINT64_C(0),
8497 UINT64_C(0),
8498 UINT64_C(0),
8499 UINT64_C(0),
8500 UINT64_C(0),
8501 UINT64_C(0),
8502 UINT64_C(0),
8503 UINT64_C(0),
8504 UINT64_C(0),
8505 UINT64_C(0),
8506 UINT64_C(0),
8507 UINT64_C(0),
8508 UINT64_C(0),
8509 UINT64_C(0),
8510 UINT64_C(0),
8511 UINT64_C(0),
8512 UINT64_C(0),
8513 UINT64_C(0),
8514 UINT64_C(0),
8515 UINT64_C(0),
8516 UINT64_C(0),
8517 UINT64_C(0),
8518 UINT64_C(0),
8519 UINT64_C(0),
8520 UINT64_C(0),
8521 UINT64_C(0),
8522 UINT64_C(0),
8523 UINT64_C(0),
8524 UINT64_C(0),
8525 UINT64_C(0),
8526 UINT64_C(0),
8527 UINT64_C(0),
8528 UINT64_C(0),
8529 UINT64_C(0),
8530 UINT64_C(0),
8531 UINT64_C(0),
8532 UINT64_C(0),
8533 UINT64_C(0),
8534 UINT64_C(0),
8535 UINT64_C(0),
8536 UINT64_C(0),
8537 UINT64_C(0),
8538 UINT64_C(0),
8539 UINT64_C(0),
8540 UINT64_C(0),
8541 UINT64_C(0),
8542 UINT64_C(0),
8543 UINT64_C(0),
8544 UINT64_C(0),
8545 UINT64_C(0),
8546 UINT64_C(0),
8547 UINT64_C(0),
8548 UINT64_C(0),
8549 UINT64_C(0),
8550 UINT64_C(0),
8551 UINT64_C(0),
8552 UINT64_C(0),
8553 UINT64_C(0),
8554 UINT64_C(0),
8555 UINT64_C(0),
8556 UINT64_C(0),
8557 UINT64_C(0),
8558 UINT64_C(0),
8559 UINT64_C(0),
8560 UINT64_C(0),
8561 UINT64_C(0),
8562 UINT64_C(0),
8563 UINT64_C(0),
8564 UINT64_C(0),
8565 UINT64_C(0),
8566 UINT64_C(0),
8567 UINT64_C(0),
8568 UINT64_C(0),
8569 UINT64_C(0),
8570 UINT64_C(0),
8571 UINT64_C(0),
8572 UINT64_C(0),
8573 UINT64_C(0),
8574 UINT64_C(0),
8575 UINT64_C(0),
8576 UINT64_C(0),
8577 UINT64_C(0),
8578 UINT64_C(0),
8579 UINT64_C(0),
8580 UINT64_C(0),
8581 UINT64_C(0),
8582 UINT64_C(0),
8583 UINT64_C(0),
8584 UINT64_C(0),
8585 UINT64_C(0),
8586 UINT64_C(0),
8587 UINT64_C(0),
8588 UINT64_C(0),
8589 UINT64_C(0),
8590 UINT64_C(0),
8591 UINT64_C(0),
8592 UINT64_C(0),
8593 UINT64_C(0),
8594 UINT64_C(0),
8595 UINT64_C(0),
8596 UINT64_C(0),
8597 UINT64_C(0),
8598 UINT64_C(0),
8599 UINT64_C(0),
8600 UINT64_C(0),
8601 UINT64_C(0),
8602 UINT64_C(0),
8603 UINT64_C(0),
8604 UINT64_C(0),
8605 UINT64_C(0),
8606 UINT64_C(0),
8607 UINT64_C(0),
8608 UINT64_C(0),
8609 UINT64_C(0),
8610 UINT64_C(0),
8611 UINT64_C(0),
8612 UINT64_C(0),
8613 UINT64_C(0),
8614 UINT64_C(0),
8615 UINT64_C(0),
8616 UINT64_C(0),
8617 UINT64_C(0),
8618 UINT64_C(0),
8619 UINT64_C(0),
8620 UINT64_C(0),
8621 UINT64_C(0),
8622 UINT64_C(0),
8623 UINT64_C(0),
8624 UINT64_C(0),
8625 UINT64_C(0),
8626 UINT64_C(0),
8627 UINT64_C(0),
8628 UINT64_C(0),
8629 UINT64_C(0),
8630 UINT64_C(0),
8631 UINT64_C(0),
8632 UINT64_C(0),
8633 UINT64_C(0),
8634 UINT64_C(0),
8635 UINT64_C(0),
8636 UINT64_C(0),
8637 UINT64_C(0),
8638 UINT64_C(0),
8639 UINT64_C(0),
8640 UINT64_C(0),
8641 UINT64_C(0),
8642 UINT64_C(0),
8643 UINT64_C(0),
8644 UINT64_C(0),
8645 UINT64_C(0),
8646 UINT64_C(0),
8647 UINT64_C(0),
8648 UINT64_C(0),
8649 UINT64_C(0),
8650 UINT64_C(0),
8651 UINT64_C(0),
8652 UINT64_C(0),
8653 UINT64_C(0),
8654 UINT64_C(0),
8655 UINT64_C(0),
8656 UINT64_C(0),
8657 UINT64_C(0),
8658 UINT64_C(0),
8659 UINT64_C(0),
8660 UINT64_C(0),
8661 UINT64_C(0),
8662 UINT64_C(0),
8663 UINT64_C(0),
8664 UINT64_C(0),
8665 UINT64_C(0),
8666 UINT64_C(0),
8667 UINT64_C(0),
8668 UINT64_C(0),
8669 UINT64_C(0),
8670 UINT64_C(0),
8671 UINT64_C(0),
8672 UINT64_C(0),
8673 UINT64_C(0),
8674 UINT64_C(0),
8675 UINT64_C(0),
8676 UINT64_C(0),
8677 UINT64_C(0),
8678 UINT64_C(0),
8679 UINT64_C(0),
8680 UINT64_C(0),
8681 UINT64_C(0),
8682 UINT64_C(0),
8683 UINT64_C(0),
8684 UINT64_C(0),
8685 UINT64_C(0),
8686 UINT64_C(0),
8687 UINT64_C(0),
8688 UINT64_C(0),
8689 UINT64_C(0),
8690 UINT64_C(0),
8691 UINT64_C(0),
8692 UINT64_C(0),
8693 UINT64_C(0),
8694 UINT64_C(0),
8695 UINT64_C(0),
8696 UINT64_C(0),
8697 UINT64_C(0),
8698 UINT64_C(0),
8699 UINT64_C(0),
8700 UINT64_C(0),
8701 UINT64_C(0),
8702 UINT64_C(0),
8703 UINT64_C(0),
8704 UINT64_C(0),
8705 UINT64_C(0),
8706 UINT64_C(0),
8707 UINT64_C(0),
8708 UINT64_C(0),
8709 UINT64_C(0),
8710 UINT64_C(0),
8711 UINT64_C(0),
8712 UINT64_C(0),
8713 UINT64_C(0),
8714 UINT64_C(0),
8715 UINT64_C(0),
8716 UINT64_C(0),
8717 UINT64_C(0),
8718 UINT64_C(0),
8719 UINT64_C(0),
8720 UINT64_C(0),
8721 UINT64_C(0),
8722 UINT64_C(0),
8723 UINT64_C(0),
8724 UINT64_C(0),
8725 UINT64_C(0),
8726 UINT64_C(0),
8727 UINT64_C(0),
8728 UINT64_C(0),
8729 UINT64_C(0),
8730 UINT64_C(0),
8731 UINT64_C(0),
8732 UINT64_C(0),
8733 UINT64_C(0),
8734 UINT64_C(0),
8735 UINT64_C(0),
8736 UINT64_C(0),
8737 UINT64_C(0),
8738 UINT64_C(0),
8739 UINT64_C(0),
8740 UINT64_C(0),
8741 UINT64_C(0),
8742 UINT64_C(0),
8743 UINT64_C(0),
8744 UINT64_C(0),
8745 UINT64_C(0),
8746 UINT64_C(0),
8747 UINT64_C(0),
8748 UINT64_C(0),
8749 UINT64_C(0),
8750 UINT64_C(0),
8751 UINT64_C(0),
8752 UINT64_C(0),
8753 UINT64_C(0),
8754 UINT64_C(0),
8755 UINT64_C(0),
8756 UINT64_C(0),
8757 UINT64_C(0),
8758 UINT64_C(0),
8759 UINT64_C(0),
8760 UINT64_C(0),
8761 UINT64_C(0),
8762 UINT64_C(0),
8763 UINT64_C(0),
8764 UINT64_C(0),
8765 UINT64_C(0),
8766 UINT64_C(0),
8767 UINT64_C(0),
8768 UINT64_C(0),
8769 UINT64_C(0),
8770 UINT64_C(0),
8771 UINT64_C(0),
8772 UINT64_C(0),
8773 UINT64_C(0),
8774 UINT64_C(0),
8775 UINT64_C(0),
8776 UINT64_C(0),
8777 UINT64_C(0),
8778 UINT64_C(0),
8779 UINT64_C(0),
8780 UINT64_C(0),
8781 UINT64_C(0),
8782 UINT64_C(0),
8783 UINT64_C(0),
8784 UINT64_C(0),
8785 UINT64_C(0),
8786 UINT64_C(0),
8787 UINT64_C(0),
8788 UINT64_C(0),
8789 UINT64_C(0),
8790 UINT64_C(0),
8791 UINT64_C(0),
8792 UINT64_C(0),
8793 UINT64_C(0),
8794 UINT64_C(0),
8795 UINT64_C(0),
8796 UINT64_C(0),
8797 UINT64_C(0),
8798 UINT64_C(0),
8799 UINT64_C(0),
8800 UINT64_C(0),
8801 UINT64_C(0),
8802 UINT64_C(0),
8803 UINT64_C(0),
8804 UINT64_C(0),
8805 UINT64_C(0),
8806 UINT64_C(0),
8807 UINT64_C(0),
8808 UINT64_C(0),
8809 UINT64_C(0),
8810 UINT64_C(0),
8811 UINT64_C(0),
8812 UINT64_C(0),
8813 UINT64_C(0),
8814 UINT64_C(0),
8815 UINT64_C(0),
8816 UINT64_C(0),
8817 UINT64_C(0),
8818 UINT64_C(0),
8819 UINT64_C(0),
8820 UINT64_C(0),
8821 UINT64_C(0),
8822 UINT64_C(0),
8823 UINT64_C(0),
8824 UINT64_C(0),
8825 UINT64_C(0),
8826 UINT64_C(0),
8827 UINT64_C(0),
8828 UINT64_C(0),
8829 UINT64_C(0),
8830 UINT64_C(0),
8831 UINT64_C(0),
8832 UINT64_C(0),
8833 UINT64_C(0),
8834 UINT64_C(0),
8835 UINT64_C(0),
8836 UINT64_C(0),
8837 UINT64_C(0),
8838 UINT64_C(0),
8839 UINT64_C(0),
8840 UINT64_C(0),
8841 UINT64_C(0),
8842 UINT64_C(0),
8843 UINT64_C(0),
8844 UINT64_C(0),
8845 UINT64_C(0),
8846 UINT64_C(0),
8847 UINT64_C(0),
8848 UINT64_C(0),
8849 UINT64_C(0),
8850 UINT64_C(0),
8851 UINT64_C(0),
8852 UINT64_C(0),
8853 UINT64_C(0),
8854 UINT64_C(0),
8855 UINT64_C(0),
8856 UINT64_C(0),
8857 UINT64_C(0),
8858 UINT64_C(0),
8859 UINT64_C(0),
8860 UINT64_C(0),
8861 UINT64_C(0),
8862 UINT64_C(0),
8863 UINT64_C(0),
8864 UINT64_C(0),
8865 UINT64_C(0),
8866 UINT64_C(0),
8867 UINT64_C(0),
8868 UINT64_C(0),
8869 UINT64_C(0),
8870 UINT64_C(0),
8871 UINT64_C(0),
8872 UINT64_C(0),
8873 UINT64_C(0),
8874 UINT64_C(0),
8875 UINT64_C(0),
8876 UINT64_C(0),
8877 UINT64_C(0),
8878 UINT64_C(0),
8879 UINT64_C(0),
8880 UINT64_C(0),
8881 UINT64_C(0),
8882 UINT64_C(0),
8883 UINT64_C(0),
8884 UINT64_C(0),
8885 UINT64_C(0),
8886 UINT64_C(0),
8887 UINT64_C(0),
8888 UINT64_C(0),
8889 UINT64_C(0),
8890 UINT64_C(0),
8891 UINT64_C(0),
8892 UINT64_C(0),
8893 UINT64_C(0),
8894 UINT64_C(0),
8895 UINT64_C(0),
8896 UINT64_C(0),
8897 UINT64_C(0),
8898 UINT64_C(0),
8899 UINT64_C(0),
8900 UINT64_C(0),
8901 UINT64_C(0),
8902 UINT64_C(0),
8903 UINT64_C(0),
8904 UINT64_C(0),
8905 UINT64_C(0),
8906 UINT64_C(0),
8907 UINT64_C(0),
8908 UINT64_C(0),
8909 UINT64_C(0),
8910 UINT64_C(0),
8911 UINT64_C(0),
8912 UINT64_C(0),
8913 UINT64_C(0),
8914 UINT64_C(0),
8915 UINT64_C(0),
8916 UINT64_C(0),
8917 UINT64_C(0),
8918 UINT64_C(0),
8919 UINT64_C(0),
8920 UINT64_C(0),
8921 UINT64_C(0),
8922 UINT64_C(0),
8923 UINT64_C(0),
8924 UINT64_C(0),
8925 UINT64_C(0),
8926 UINT64_C(0),
8927 UINT64_C(0),
8928 UINT64_C(0),
8929 UINT64_C(0),
8930 UINT64_C(0),
8931 UINT64_C(0),
8932 UINT64_C(0),
8933 UINT64_C(0),
8934 UINT64_C(0),
8935 UINT64_C(0),
8936 UINT64_C(0),
8937 UINT64_C(0),
8938 UINT64_C(0),
8939 UINT64_C(0),
8940 UINT64_C(0),
8941 UINT64_C(0),
8942 UINT64_C(0),
8943 UINT64_C(0),
8944 UINT64_C(0),
8945 UINT64_C(0),
8946 UINT64_C(0),
8947 UINT64_C(0),
8948 UINT64_C(0),
8949 UINT64_C(0),
8950 UINT64_C(0),
8951 UINT64_C(0),
8952 UINT64_C(0),
8953 UINT64_C(0),
8954 UINT64_C(0),
8955 UINT64_C(0),
8956 UINT64_C(0),
8957 UINT64_C(0),
8958 UINT64_C(0),
8959 UINT64_C(0),
8960 UINT64_C(0),
8961 UINT64_C(0),
8962 UINT64_C(0),
8963 UINT64_C(0),
8964 UINT64_C(0),
8965 UINT64_C(0),
8966 UINT64_C(0),
8967 UINT64_C(0),
8968 UINT64_C(0),
8969 UINT64_C(0),
8970 UINT64_C(0),
8971 UINT64_C(0),
8972 UINT64_C(0),
8973 UINT64_C(0),
8974 UINT64_C(0),
8975 UINT64_C(0),
8976 UINT64_C(0),
8977 UINT64_C(0),
8978 UINT64_C(0),
8979 UINT64_C(0),
8980 UINT64_C(0),
8981 UINT64_C(0),
8982 UINT64_C(0),
8983 UINT64_C(0),
8984 UINT64_C(0),
8985 UINT64_C(0),
8986 UINT64_C(0),
8987 UINT64_C(0),
8988 UINT64_C(0),
8989 UINT64_C(0),
8990 UINT64_C(0),
8991 UINT64_C(0),
8992 UINT64_C(0),
8993 UINT64_C(0),
8994 UINT64_C(0),
8995 UINT64_C(0),
8996 UINT64_C(0),
8997 UINT64_C(0),
8998 UINT64_C(0),
8999 UINT64_C(0),
9000 UINT64_C(0),
9001 UINT64_C(0),
9002 UINT64_C(0),
9003 UINT64_C(0),
9004 UINT64_C(0),
9005 UINT64_C(0),
9006 UINT64_C(0),
9007 UINT64_C(0),
9008 UINT64_C(0),
9009 UINT64_C(0),
9010 UINT64_C(0),
9011 UINT64_C(0),
9012 UINT64_C(0),
9013 UINT64_C(0),
9014 UINT64_C(0),
9015 UINT64_C(0),
9016 UINT64_C(0),
9017 UINT64_C(0),
9018 UINT64_C(0),
9019 UINT64_C(0),
9020 UINT64_C(0),
9021 UINT64_C(0),
9022 UINT64_C(0),
9023 UINT64_C(0),
9024 UINT64_C(0),
9025 UINT64_C(0),
9026 UINT64_C(0),
9027 UINT64_C(0),
9028 UINT64_C(0),
9029 UINT64_C(0),
9030 UINT64_C(0),
9031 UINT64_C(0),
9032 UINT64_C(0),
9033 UINT64_C(0),
9034 UINT64_C(0),
9035 UINT64_C(0),
9036 UINT64_C(0),
9037 UINT64_C(0),
9038 UINT64_C(0),
9039 UINT64_C(0),
9040 UINT64_C(0),
9041 UINT64_C(0),
9042 UINT64_C(0),
9043 UINT64_C(0),
9044 UINT64_C(0),
9045 UINT64_C(0),
9046 UINT64_C(0),
9047 UINT64_C(0),
9048 UINT64_C(0),
9049 UINT64_C(0),
9050 UINT64_C(0),
9051 UINT64_C(0),
9052 UINT64_C(0),
9053 UINT64_C(0),
9054 UINT64_C(0),
9055 UINT64_C(0),
9056 UINT64_C(0),
9057 UINT64_C(0),
9058 UINT64_C(0),
9059 UINT64_C(0),
9060 UINT64_C(0),
9061 UINT64_C(0),
9062 UINT64_C(0),
9063 UINT64_C(0),
9064 UINT64_C(0),
9065 UINT64_C(0),
9066 UINT64_C(0),
9067 UINT64_C(0),
9068 UINT64_C(0),
9069 UINT64_C(0),
9070 UINT64_C(0),
9071 UINT64_C(0),
9072 UINT64_C(0),
9073 UINT64_C(0),
9074 UINT64_C(0),
9075 UINT64_C(0),
9076 UINT64_C(0),
9077 UINT64_C(0),
9078 UINT64_C(0),
9079 UINT64_C(0),
9080 UINT64_C(0),
9081 UINT64_C(0),
9082 UINT64_C(0),
9083 UINT64_C(0),
9084 UINT64_C(0),
9085 UINT64_C(0),
9086 UINT64_C(0),
9087 UINT64_C(0),
9088 UINT64_C(0),
9089 UINT64_C(0),
9090 UINT64_C(0),
9091 UINT64_C(0),
9092 UINT64_C(0),
9093 UINT64_C(0),
9094 UINT64_C(0),
9095 UINT64_C(0),
9096 UINT64_C(0),
9097 UINT64_C(0),
9098 UINT64_C(0),
9099 UINT64_C(0),
9100 UINT64_C(0),
9101 UINT64_C(0),
9102 UINT64_C(0),
9103 UINT64_C(0),
9104 UINT64_C(0),
9105 UINT64_C(0),
9106 UINT64_C(0),
9107 UINT64_C(0),
9108 UINT64_C(0),
9109 UINT64_C(0),
9110 UINT64_C(0),
9111 UINT64_C(0),
9112 UINT64_C(0),
9113 UINT64_C(0),
9114 UINT64_C(0),
9115 UINT64_C(0),
9116 UINT64_C(0),
9117 UINT64_C(0),
9118 UINT64_C(0),
9119 UINT64_C(0),
9120 UINT64_C(0),
9121 UINT64_C(0),
9122 UINT64_C(0),
9123 UINT64_C(0),
9124 UINT64_C(0),
9125 UINT64_C(0),
9126 UINT64_C(0),
9127 UINT64_C(0),
9128 UINT64_C(0),
9129 UINT64_C(0),
9130 UINT64_C(0),
9131 UINT64_C(0),
9132 UINT64_C(0),
9133 UINT64_C(0),
9134 UINT64_C(0),
9135 UINT64_C(0),
9136 UINT64_C(0),
9137 UINT64_C(0),
9138 UINT64_C(0),
9139 UINT64_C(0),
9140 UINT64_C(0),
9141 UINT64_C(0),
9142 UINT64_C(0),
9143 UINT64_C(0),
9144 UINT64_C(0),
9145 UINT64_C(0),
9146 UINT64_C(0),
9147 UINT64_C(0),
9148 UINT64_C(0),
9149 UINT64_C(0),
9150 UINT64_C(0),
9151 UINT64_C(0),
9152 UINT64_C(0),
9153 UINT64_C(0),
9154 UINT64_C(0),
9155 UINT64_C(0),
9156 UINT64_C(0),
9157 UINT64_C(0),
9158 UINT64_C(0),
9159 UINT64_C(0),
9160 UINT64_C(0),
9161 UINT64_C(0),
9162 UINT64_C(0),
9163 UINT64_C(0),
9164 UINT64_C(0),
9165 UINT64_C(0),
9166 UINT64_C(0),
9167 UINT64_C(0),
9168 UINT64_C(0),
9169 UINT64_C(0),
9170 UINT64_C(0),
9171 UINT64_C(0),
9172 UINT64_C(0),
9173 UINT64_C(0),
9174 UINT64_C(0),
9175 UINT64_C(0),
9176 UINT64_C(0),
9177 UINT64_C(0),
9178 UINT64_C(0),
9179 UINT64_C(0),
9180 UINT64_C(0),
9181 UINT64_C(0),
9182 UINT64_C(0),
9183 UINT64_C(0),
9184 UINT64_C(0),
9185 UINT64_C(0),
9186 UINT64_C(0),
9187 UINT64_C(0),
9188 UINT64_C(0),
9189 UINT64_C(0),
9190 UINT64_C(0),
9191 UINT64_C(0),
9192 UINT64_C(0),
9193 UINT64_C(0),
9194 UINT64_C(0),
9195 UINT64_C(0),
9196 UINT64_C(0),
9197 UINT64_C(0),
9198 UINT64_C(0),
9199 UINT64_C(0),
9200 UINT64_C(0),
9201 UINT64_C(0),
9202 UINT64_C(0),
9203 UINT64_C(0),
9204 UINT64_C(0),
9205 UINT64_C(0),
9206 UINT64_C(0),
9207 UINT64_C(0),
9208 UINT64_C(0),
9209 UINT64_C(0),
9210 UINT64_C(0),
9211 UINT64_C(0),
9212 UINT64_C(0),
9213 UINT64_C(0),
9214 UINT64_C(0),
9215 UINT64_C(0),
9216 UINT64_C(0),
9217 UINT64_C(0),
9218 UINT64_C(0),
9219 UINT64_C(0),
9220 UINT64_C(0),
9221 UINT64_C(0),
9222 UINT64_C(0),
9223 UINT64_C(0),
9224 UINT64_C(0),
9225 UINT64_C(0),
9226 UINT64_C(0),
9227 UINT64_C(0),
9228 UINT64_C(0),
9229 UINT64_C(0),
9230 UINT64_C(0),
9231 UINT64_C(0),
9232 UINT64_C(0),
9233 UINT64_C(0),
9234 UINT64_C(0),
9235 UINT64_C(0),
9236 UINT64_C(0),
9237 UINT64_C(0),
9238 UINT64_C(0),
9239 UINT64_C(0),
9240 UINT64_C(0),
9241 UINT64_C(0),
9242 UINT64_C(0),
9243 UINT64_C(0),
9244 UINT64_C(0),
9245 UINT64_C(0),
9246 UINT64_C(0),
9247 UINT64_C(0),
9248 UINT64_C(0),
9249 UINT64_C(0),
9250 UINT64_C(0),
9251 UINT64_C(0),
9252 UINT64_C(0),
9253 UINT64_C(0),
9254 UINT64_C(0),
9255 UINT64_C(0),
9256 UINT64_C(0),
9257 UINT64_C(0),
9258 UINT64_C(0),
9259 UINT64_C(0),
9260 UINT64_C(0),
9261 UINT64_C(0),
9262 UINT64_C(0),
9263 UINT64_C(0),
9264 UINT64_C(0),
9265 UINT64_C(0),
9266 UINT64_C(0),
9267 UINT64_C(0),
9268 UINT64_C(0),
9269 UINT64_C(0),
9270 UINT64_C(0),
9271 UINT64_C(0),
9272 UINT64_C(0),
9273 UINT64_C(0),
9274 UINT64_C(0),
9275 UINT64_C(0),
9276 UINT64_C(0),
9277 UINT64_C(0),
9278 UINT64_C(0),
9279 UINT64_C(0),
9280 UINT64_C(0),
9281 UINT64_C(0),
9282 UINT64_C(0),
9283 UINT64_C(0),
9284 UINT64_C(0),
9285 UINT64_C(0),
9286 UINT64_C(0),
9287 UINT64_C(0),
9288 UINT64_C(0),
9289 UINT64_C(0),
9290 UINT64_C(0),
9291 UINT64_C(0),
9292 UINT64_C(0),
9293 UINT64_C(0),
9294 UINT64_C(0),
9295 UINT64_C(0),
9296 UINT64_C(0),
9297 UINT64_C(0),
9298 UINT64_C(0),
9299 UINT64_C(0),
9300 UINT64_C(0),
9301 UINT64_C(0),
9302 UINT64_C(0),
9303 UINT64_C(0),
9304 UINT64_C(0),
9305 UINT64_C(0),
9306 UINT64_C(0),
9307 UINT64_C(0),
9308 UINT64_C(0),
9309 UINT64_C(0),
9310 UINT64_C(0),
9311 UINT64_C(0),
9312 UINT64_C(0),
9313 UINT64_C(0),
9314 UINT64_C(0),
9315 UINT64_C(0),
9316 UINT64_C(0),
9317 UINT64_C(0),
9318 UINT64_C(0),
9319 UINT64_C(0),
9320 UINT64_C(0),
9321 UINT64_C(0),
9322 UINT64_C(0),
9323 UINT64_C(0),
9324 UINT64_C(0),
9325 UINT64_C(0),
9326 UINT64_C(0),
9327 UINT64_C(0),
9328 UINT64_C(0),
9329 UINT64_C(0),
9330 UINT64_C(0),
9331 UINT64_C(0),
9332 UINT64_C(0),
9333 UINT64_C(0),
9334 UINT64_C(0),
9335 UINT64_C(0),
9336 UINT64_C(0),
9337 UINT64_C(0),
9338 UINT64_C(0),
9339 UINT64_C(0),
9340 UINT64_C(0),
9341 UINT64_C(0),
9342 UINT64_C(0),
9343 UINT64_C(0),
9344 UINT64_C(0),
9345 UINT64_C(0),
9346 UINT64_C(0),
9347 UINT64_C(0),
9348 UINT64_C(0),
9349 UINT64_C(0),
9350 UINT64_C(0),
9351 UINT64_C(0),
9352 UINT64_C(0),
9353 UINT64_C(0),
9354 UINT64_C(0),
9355 UINT64_C(0),
9356 UINT64_C(0),
9357 UINT64_C(0),
9358 UINT64_C(0),
9359 UINT64_C(0),
9360 UINT64_C(0),
9361 UINT64_C(0),
9362 UINT64_C(0),
9363 UINT64_C(0),
9364 UINT64_C(0),
9365 UINT64_C(0),
9366 UINT64_C(0),
9367 UINT64_C(0),
9368 UINT64_C(0),
9369 UINT64_C(0),
9370 UINT64_C(0),
9371 UINT64_C(0),
9372 UINT64_C(0),
9373 UINT64_C(0),
9374 UINT64_C(0),
9375 UINT64_C(0),
9376 UINT64_C(0),
9377 UINT64_C(0),
9378 UINT64_C(0),
9379 UINT64_C(0),
9380 UINT64_C(0),
9381 UINT64_C(0),
9382 UINT64_C(0),
9383 UINT64_C(0),
9384 UINT64_C(0),
9385 UINT64_C(0),
9386 UINT64_C(0),
9387 UINT64_C(0),
9388 UINT64_C(0),
9389 UINT64_C(0),
9390 UINT64_C(0),
9391 UINT64_C(0),
9392 UINT64_C(0),
9393 UINT64_C(0),
9394 UINT64_C(0),
9395 UINT64_C(0),
9396 UINT64_C(0),
9397 UINT64_C(0),
9398 UINT64_C(0),
9399 UINT64_C(0),
9400 UINT64_C(0),
9401 UINT64_C(0),
9402 UINT64_C(0),
9403 UINT64_C(0),
9404 UINT64_C(0),
9405 UINT64_C(0),
9406 UINT64_C(0),
9407 UINT64_C(0),
9408 UINT64_C(0),
9409 UINT64_C(0),
9410 UINT64_C(0),
9411 UINT64_C(0),
9412 UINT64_C(0),
9413 UINT64_C(0),
9414 UINT64_C(0),
9415 UINT64_C(0),
9416 UINT64_C(0),
9417 UINT64_C(0),
9418 UINT64_C(0),
9419 UINT64_C(0),
9420 UINT64_C(0),
9421 UINT64_C(0),
9422 UINT64_C(0),
9423 UINT64_C(0),
9424 UINT64_C(0),
9425 UINT64_C(0),
9426 UINT64_C(0),
9427 UINT64_C(0),
9428 UINT64_C(0),
9429 UINT64_C(0),
9430 UINT64_C(0),
9431 UINT64_C(0),
9432 UINT64_C(0),
9433 UINT64_C(0),
9434 UINT64_C(0),
9435 UINT64_C(0),
9436 UINT64_C(0),
9437 UINT64_C(0),
9438 UINT64_C(0),
9439 UINT64_C(0),
9440 UINT64_C(0),
9441 UINT64_C(0),
9442 UINT64_C(0),
9443 UINT64_C(0),
9444 UINT64_C(0),
9445 UINT64_C(0),
9446 UINT64_C(0),
9447 UINT64_C(0),
9448 UINT64_C(0),
9449 UINT64_C(0),
9450 UINT64_C(0),
9451 UINT64_C(0),
9452 UINT64_C(0),
9453 UINT64_C(0),
9454 UINT64_C(0),
9455 UINT64_C(0),
9456 UINT64_C(0),
9457 UINT64_C(0),
9458 UINT64_C(0),
9459 UINT64_C(0),
9460 UINT64_C(0),
9461 UINT64_C(0),
9462 UINT64_C(0),
9463 UINT64_C(0),
9464 UINT64_C(0),
9465 UINT64_C(0),
9466 UINT64_C(0),
9467 UINT64_C(0),
9468 UINT64_C(0),
9469 UINT64_C(0),
9470 UINT64_C(0),
9471 UINT64_C(0),
9472 UINT64_C(0),
9473 UINT64_C(0),
9474 UINT64_C(0),
9475 UINT64_C(0),
9476 UINT64_C(0),
9477 UINT64_C(0),
9478 UINT64_C(0),
9479 UINT64_C(0),
9480 UINT64_C(0),
9481 UINT64_C(0),
9482 UINT64_C(0),
9483 UINT64_C(0),
9484 UINT64_C(0),
9485 UINT64_C(0),
9486 UINT64_C(0),
9487 UINT64_C(0),
9488 UINT64_C(0),
9489 UINT64_C(0),
9490 UINT64_C(0),
9491 UINT64_C(0),
9492 UINT64_C(0),
9493 UINT64_C(0),
9494 UINT64_C(0),
9495 UINT64_C(0),
9496 UINT64_C(0),
9497 UINT64_C(0),
9498 UINT64_C(0),
9499 UINT64_C(0),
9500 UINT64_C(0),
9501 UINT64_C(0),
9502 UINT64_C(0),
9503 UINT64_C(0),
9504 UINT64_C(0),
9505 UINT64_C(0),
9506 UINT64_C(0),
9507 UINT64_C(0),
9508 UINT64_C(0),
9509 UINT64_C(0),
9510 UINT64_C(0),
9511 UINT64_C(0),
9512 UINT64_C(0),
9513 UINT64_C(0),
9514 UINT64_C(0),
9515 UINT64_C(0),
9516 UINT64_C(0),
9517 UINT64_C(0),
9518 UINT64_C(0),
9519 UINT64_C(0),
9520 UINT64_C(0),
9521 UINT64_C(0),
9522 UINT64_C(0),
9523 UINT64_C(0),
9524 UINT64_C(0),
9525 UINT64_C(0),
9526 UINT64_C(0),
9527 UINT64_C(0),
9528 UINT64_C(0),
9529 UINT64_C(0),
9530 UINT64_C(0),
9531 UINT64_C(0),
9532 UINT64_C(0),
9533 UINT64_C(0),
9534 UINT64_C(0),
9535 UINT64_C(0),
9536 UINT64_C(0),
9537 UINT64_C(0),
9538 UINT64_C(0),
9539 UINT64_C(0),
9540 UINT64_C(0),
9541 UINT64_C(0),
9542 UINT64_C(0),
9543 UINT64_C(0),
9544 UINT64_C(0),
9545 UINT64_C(0),
9546 UINT64_C(0),
9547 UINT64_C(0),
9548 UINT64_C(0),
9549 UINT64_C(0),
9550 UINT64_C(0),
9551 UINT64_C(0),
9552 UINT64_C(0),
9553 UINT64_C(0),
9554 UINT64_C(0),
9555 UINT64_C(0),
9556 UINT64_C(0),
9557 UINT64_C(0),
9558 UINT64_C(0),
9559 UINT64_C(0),
9560 UINT64_C(0),
9561 UINT64_C(0),
9562 UINT64_C(0),
9563 UINT64_C(0),
9564 UINT64_C(0),
9565 UINT64_C(0),
9566 UINT64_C(0),
9567 UINT64_C(0),
9568 UINT64_C(0),
9569 UINT64_C(0),
9570 UINT64_C(0),
9571 UINT64_C(0),
9572 UINT64_C(0),
9573 UINT64_C(0),
9574 UINT64_C(0),
9575 UINT64_C(0),
9576 UINT64_C(0),
9577 UINT64_C(0),
9578 UINT64_C(0),
9579 UINT64_C(0),
9580 UINT64_C(0),
9581 UINT64_C(0),
9582 UINT64_C(0),
9583 UINT64_C(0),
9584 UINT64_C(0),
9585 UINT64_C(0),
9586 UINT64_C(0),
9587 UINT64_C(0),
9588 UINT64_C(0),
9589 UINT64_C(0),
9590 UINT64_C(0),
9591 UINT64_C(0),
9592 UINT64_C(0),
9593 UINT64_C(0),
9594 UINT64_C(0),
9595 UINT64_C(0),
9596 UINT64_C(0),
9597 UINT64_C(0),
9598 UINT64_C(0),
9599 UINT64_C(0),
9600 UINT64_C(0),
9601 UINT64_C(0),
9602 UINT64_C(0),
9603 UINT64_C(0),
9604 UINT64_C(0),
9605 UINT64_C(0),
9606 UINT64_C(0),
9607 UINT64_C(0),
9608 UINT64_C(0),
9609 UINT64_C(0),
9610 UINT64_C(0),
9611 UINT64_C(0),
9612 UINT64_C(0),
9613 UINT64_C(0),
9614 UINT64_C(0),
9615 UINT64_C(0),
9616 UINT64_C(0),
9617 UINT64_C(0),
9618 UINT64_C(0),
9619 UINT64_C(0),
9620 UINT64_C(0),
9621 UINT64_C(0),
9622 UINT64_C(0),
9623 UINT64_C(0),
9624 UINT64_C(0),
9625 UINT64_C(0),
9626 UINT64_C(0),
9627 UINT64_C(0),
9628 UINT64_C(0),
9629 UINT64_C(0),
9630 UINT64_C(0),
9631 UINT64_C(0),
9632 UINT64_C(0),
9633 UINT64_C(0),
9634 UINT64_C(0),
9635 UINT64_C(0),
9636 UINT64_C(0),
9637 UINT64_C(0),
9638 UINT64_C(0),
9639 UINT64_C(0),
9640 UINT64_C(0),
9641 UINT64_C(0),
9642 UINT64_C(0),
9643 UINT64_C(0),
9644 UINT64_C(0),
9645 UINT64_C(0),
9646 UINT64_C(0),
9647 UINT64_C(0),
9648 UINT64_C(0),
9649 UINT64_C(0),
9650 UINT64_C(0),
9651 UINT64_C(0),
9652 UINT64_C(0),
9653 UINT64_C(0),
9654 UINT64_C(0),
9655 UINT64_C(0),
9656 UINT64_C(0),
9657 UINT64_C(0),
9658 UINT64_C(0),
9659 UINT64_C(0),
9660 UINT64_C(0),
9661 UINT64_C(0),
9662 UINT64_C(0),
9663 UINT64_C(0),
9664 UINT64_C(0),
9665 UINT64_C(0),
9666 UINT64_C(0),
9667 UINT64_C(0),
9668 UINT64_C(0),
9669 UINT64_C(0),
9670 UINT64_C(0),
9671 UINT64_C(0),
9672 UINT64_C(0),
9673 UINT64_C(0),
9674 UINT64_C(0),
9675 UINT64_C(0),
9676 UINT64_C(0),
9677 UINT64_C(0),
9678 UINT64_C(0),
9679 UINT64_C(0),
9680 UINT64_C(0),
9681 UINT64_C(0),
9682 UINT64_C(0),
9683 UINT64_C(0),
9684 UINT64_C(0),
9685 UINT64_C(0),
9686 UINT64_C(0),
9687 UINT64_C(0),
9688 UINT64_C(0),
9689 UINT64_C(0),
9690 UINT64_C(0),
9691 UINT64_C(0),
9692 UINT64_C(0),
9693 UINT64_C(0),
9694 UINT64_C(0),
9695 UINT64_C(0),
9696 UINT64_C(0),
9697 UINT64_C(0),
9698 UINT64_C(0),
9699 UINT64_C(0),
9700 UINT64_C(0),
9701 UINT64_C(0),
9702 UINT64_C(0),
9703 UINT64_C(0),
9704 UINT64_C(0),
9705 UINT64_C(0),
9706 UINT64_C(0),
9707 UINT64_C(0),
9708 UINT64_C(0),
9709 UINT64_C(0),
9710 UINT64_C(0),
9711 UINT64_C(0),
9712 UINT64_C(0),
9713 UINT64_C(0),
9714 UINT64_C(0),
9715 UINT64_C(0),
9716 UINT64_C(0),
9717 UINT64_C(0),
9718 UINT64_C(0),
9719 UINT64_C(0),
9720 UINT64_C(0),
9721 UINT64_C(0),
9722 UINT64_C(0),
9723 UINT64_C(0),
9724 UINT64_C(0),
9725 UINT64_C(0),
9726 UINT64_C(0),
9727 UINT64_C(0),
9728 UINT64_C(0),
9729 UINT64_C(0),
9730 UINT64_C(0),
9731 UINT64_C(0),
9732 UINT64_C(0),
9733 UINT64_C(0),
9734 UINT64_C(0),
9735 UINT64_C(0),
9736 UINT64_C(0),
9737 UINT64_C(0),
9738 UINT64_C(0),
9739 UINT64_C(0),
9740 UINT64_C(0),
9741 UINT64_C(0),
9742 UINT64_C(0),
9743 UINT64_C(0),
9744 UINT64_C(0),
9745 UINT64_C(0),
9746 UINT64_C(0),
9747 UINT64_C(0),
9748 UINT64_C(0),
9749 UINT64_C(0),
9750 UINT64_C(0),
9751 UINT64_C(0),
9752 UINT64_C(0),
9753 UINT64_C(0),
9754 UINT64_C(0),
9755 UINT64_C(0),
9756 UINT64_C(0),
9757 UINT64_C(0),
9758 UINT64_C(0),
9759 UINT64_C(0),
9760 UINT64_C(0),
9761 UINT64_C(0),
9762 UINT64_C(0),
9763 UINT64_C(0),
9764 UINT64_C(0),
9765 UINT64_C(0),
9766 UINT64_C(0),
9767 UINT64_C(0),
9768 UINT64_C(0),
9769 UINT64_C(0),
9770 UINT64_C(0),
9771 UINT64_C(0),
9772 UINT64_C(0),
9773 UINT64_C(0),
9774 UINT64_C(0),
9775 UINT64_C(0),
9776 UINT64_C(0),
9777 UINT64_C(0),
9778 UINT64_C(0),
9779 UINT64_C(0),
9780 UINT64_C(0),
9781 UINT64_C(0),
9782 UINT64_C(0),
9783 UINT64_C(0),
9784 UINT64_C(0),
9785 UINT64_C(0),
9786 UINT64_C(0),
9787 UINT64_C(0),
9788 UINT64_C(0),
9789 UINT64_C(0),
9790 UINT64_C(0),
9791 UINT64_C(0),
9792 UINT64_C(0),
9793 UINT64_C(0),
9794 UINT64_C(0),
9795 UINT64_C(0),
9796 UINT64_C(0),
9797 UINT64_C(0),
9798 UINT64_C(0),
9799 UINT64_C(0),
9800 UINT64_C(0),
9801 UINT64_C(0),
9802 UINT64_C(0),
9803 UINT64_C(0),
9804 UINT64_C(0),
9805 UINT64_C(0),
9806 UINT64_C(0),
9807 UINT64_C(0),
9808 UINT64_C(0),
9809 UINT64_C(0),
9810 UINT64_C(0),
9811 UINT64_C(0),
9812 UINT64_C(0),
9813 UINT64_C(0),
9814 UINT64_C(0),
9815 UINT64_C(0),
9816 UINT64_C(0),
9817 UINT64_C(0),
9818 UINT64_C(0),
9819 UINT64_C(0),
9820 UINT64_C(0),
9821 UINT64_C(0),
9822 UINT64_C(0),
9823 UINT64_C(0),
9824 UINT64_C(0),
9825 UINT64_C(0),
9826 UINT64_C(0),
9827 UINT64_C(0),
9828 UINT64_C(0),
9829 UINT64_C(0),
9830 UINT64_C(0),
9831 UINT64_C(0),
9832 UINT64_C(0),
9833 UINT64_C(0),
9834 UINT64_C(0),
9835 UINT64_C(0),
9836 UINT64_C(0),
9837 UINT64_C(0),
9838 UINT64_C(0),
9839 UINT64_C(0),
9840 UINT64_C(0),
9841 UINT64_C(0),
9842 UINT64_C(0),
9843 UINT64_C(0),
9844 UINT64_C(0),
9845 UINT64_C(0),
9846 UINT64_C(0),
9847 UINT64_C(0),
9848 UINT64_C(0),
9849 UINT64_C(0),
9850 UINT64_C(0),
9851 UINT64_C(0),
9852 UINT64_C(0),
9853 UINT64_C(0),
9854 UINT64_C(0),
9855 UINT64_C(0),
9856 UINT64_C(0),
9857 UINT64_C(0),
9858 UINT64_C(0),
9859 UINT64_C(0),
9860 UINT64_C(0),
9861 UINT64_C(0),
9862 UINT64_C(0),
9863 UINT64_C(0),
9864 UINT64_C(0),
9865 UINT64_C(0),
9866 UINT64_C(0),
9867 UINT64_C(0),
9868 UINT64_C(0),
9869 UINT64_C(0),
9870 UINT64_C(0),
9871 UINT64_C(0),
9872 UINT64_C(0),
9873 UINT64_C(0),
9874 UINT64_C(0),
9875 UINT64_C(0),
9876 UINT64_C(0),
9877 UINT64_C(0),
9878 UINT64_C(0),
9879 UINT64_C(0),
9880 UINT64_C(0),
9881 UINT64_C(0),
9882 UINT64_C(0),
9883 UINT64_C(0),
9884 UINT64_C(0),
9885 UINT64_C(0),
9886 UINT64_C(0),
9887 UINT64_C(0),
9888 UINT64_C(0),
9889 UINT64_C(0),
9890 UINT64_C(0),
9891 UINT64_C(0),
9892 UINT64_C(0),
9893 UINT64_C(0),
9894 UINT64_C(0),
9895 UINT64_C(0),
9896 UINT64_C(0),
9897 UINT64_C(0),
9898 UINT64_C(0),
9899 UINT64_C(0),
9900 UINT64_C(0),
9901 UINT64_C(0),
9902 UINT64_C(0),
9903 UINT64_C(0),
9904 UINT64_C(0),
9905 UINT64_C(0),
9906 UINT64_C(0),
9907 UINT64_C(0),
9908 UINT64_C(0),
9909 UINT64_C(0),
9910 UINT64_C(0),
9911 UINT64_C(0),
9912 UINT64_C(0),
9913 UINT64_C(0),
9914 UINT64_C(0),
9915 UINT64_C(0),
9916 UINT64_C(0),
9917 UINT64_C(0),
9918 UINT64_C(0),
9919 UINT64_C(0),
9920 UINT64_C(0),
9921 UINT64_C(0),
9922 UINT64_C(0),
9923 UINT64_C(0),
9924 UINT64_C(0),
9925 UINT64_C(0),
9926 UINT64_C(0),
9927 UINT64_C(0),
9928 UINT64_C(0),
9929 UINT64_C(0),
9930 UINT64_C(0),
9931 UINT64_C(0),
9932 UINT64_C(0),
9933 UINT64_C(0),
9934 UINT64_C(0),
9935 UINT64_C(0),
9936 UINT64_C(0),
9937 UINT64_C(0),
9938 UINT64_C(0),
9939 UINT64_C(0),
9940 UINT64_C(0),
9941 UINT64_C(0),
9942 UINT64_C(0),
9943 UINT64_C(0),
9944 UINT64_C(0),
9945 UINT64_C(0),
9946 UINT64_C(0),
9947 UINT64_C(0),
9948 UINT64_C(0),
9949 UINT64_C(0),
9950 UINT64_C(0),
9951 UINT64_C(0),
9952 UINT64_C(0),
9953 UINT64_C(0),
9954 UINT64_C(0),
9955 UINT64_C(0),
9956 UINT64_C(0),
9957 UINT64_C(0),
9958 UINT64_C(0),
9959 UINT64_C(0),
9960 UINT64_C(0),
9961 UINT64_C(0),
9962 UINT64_C(0),
9963 UINT64_C(0),
9964 UINT64_C(0),
9965 UINT64_C(0),
9966 UINT64_C(0),
9967 UINT64_C(0),
9968 UINT64_C(0),
9969 UINT64_C(0),
9970 UINT64_C(0),
9971 UINT64_C(0),
9972 UINT64_C(0),
9973 UINT64_C(0),
9974 UINT64_C(0),
9975 UINT64_C(0),
9976 UINT64_C(0),
9977 UINT64_C(0),
9978 UINT64_C(0),
9979 UINT64_C(0),
9980 UINT64_C(0),
9981 UINT64_C(0),
9982 UINT64_C(0),
9983 UINT64_C(0),
9984 UINT64_C(0),
9985 UINT64_C(0),
9986 UINT64_C(0),
9987 UINT64_C(0),
9988 UINT64_C(0),
9989 UINT64_C(0),
9990 UINT64_C(0),
9991 UINT64_C(0),
9992 UINT64_C(0),
9993 UINT64_C(0),
9994 UINT64_C(0),
9995 UINT64_C(0),
9996 UINT64_C(0),
9997 UINT64_C(0),
9998 UINT64_C(0),
9999 UINT64_C(0),
10000 UINT64_C(0),
10001 UINT64_C(0),
10002 UINT64_C(0),
10003 UINT64_C(0),
10004 UINT64_C(0),
10005 UINT64_C(0),
10006 UINT64_C(0),
10007 UINT64_C(0),
10008 UINT64_C(0),
10009 UINT64_C(0),
10010 UINT64_C(0),
10011 UINT64_C(0),
10012 UINT64_C(0),
10013 UINT64_C(0),
10014 UINT64_C(0),
10015 UINT64_C(0),
10016 UINT64_C(0),
10017 UINT64_C(0),
10018 UINT64_C(0),
10019 UINT64_C(0),
10020 UINT64_C(0),
10021 UINT64_C(0),
10022 UINT64_C(0),
10023 UINT64_C(0),
10024 UINT64_C(0),
10025 UINT64_C(0),
10026 UINT64_C(0),
10027 UINT64_C(0),
10028 UINT64_C(0),
10029 UINT64_C(0),
10030 UINT64_C(0),
10031 UINT64_C(0),
10032 UINT64_C(0),
10033 UINT64_C(0),
10034 UINT64_C(0),
10035 UINT64_C(0),
10036 UINT64_C(0),
10037 UINT64_C(0),
10038 UINT64_C(0),
10039 UINT64_C(0),
10040 UINT64_C(0),
10041 UINT64_C(0),
10042 UINT64_C(0),
10043 UINT64_C(0),
10044 UINT64_C(0),
10045 UINT64_C(0),
10046 UINT64_C(0),
10047 UINT64_C(0),
10048 UINT64_C(0),
10049 UINT64_C(0),
10050 UINT64_C(0),
10051 UINT64_C(0),
10052 UINT64_C(0),
10053 UINT64_C(0),
10054 UINT64_C(0),
10055 UINT64_C(0),
10056 UINT64_C(0),
10057 UINT64_C(0),
10058 UINT64_C(0),
10059 UINT64_C(0),
10060 UINT64_C(0),
10061 UINT64_C(0),
10062 UINT64_C(0),
10063 UINT64_C(0),
10064 UINT64_C(0),
10065 UINT64_C(0),
10066 UINT64_C(0),
10067 UINT64_C(0),
10068 UINT64_C(0),
10069 UINT64_C(0),
10070 UINT64_C(0),
10071 UINT64_C(0),
10072 UINT64_C(0),
10073 UINT64_C(0),
10074 UINT64_C(0),
10075 UINT64_C(0),
10076 UINT64_C(0),
10077 UINT64_C(0),
10078 UINT64_C(0),
10079 UINT64_C(0),
10080 UINT64_C(0),
10081 UINT64_C(0),
10082 UINT64_C(0),
10083 UINT64_C(0),
10084 UINT64_C(0),
10085 UINT64_C(0),
10086 UINT64_C(0),
10087 UINT64_C(0),
10088 UINT64_C(0),
10089 UINT64_C(0),
10090 UINT64_C(0),
10091 UINT64_C(0),
10092 UINT64_C(0),
10093 UINT64_C(0),
10094 UINT64_C(0),
10095 UINT64_C(0),
10096 UINT64_C(0),
10097 UINT64_C(0),
10098 UINT64_C(0),
10099 UINT64_C(0),
10100 UINT64_C(0),
10101 UINT64_C(0),
10102 UINT64_C(0),
10103 UINT64_C(0),
10104 UINT64_C(0),
10105 UINT64_C(0),
10106 UINT64_C(0),
10107 UINT64_C(0),
10108 UINT64_C(0),
10109 UINT64_C(0),
10110 UINT64_C(0),
10111 UINT64_C(0),
10112 UINT64_C(0),
10113 UINT64_C(0),
10114 UINT64_C(0),
10115 UINT64_C(0),
10116 UINT64_C(0),
10117 UINT64_C(0),
10118 UINT64_C(0),
10119 UINT64_C(0),
10120 UINT64_C(0),
10121 UINT64_C(0),
10122 UINT64_C(0),
10123 UINT64_C(0),
10124 UINT64_C(0),
10125 UINT64_C(0),
10126 UINT64_C(0),
10127 UINT64_C(0),
10128 UINT64_C(0),
10129 UINT64_C(0),
10130 UINT64_C(0),
10131 UINT64_C(0),
10132 UINT64_C(0),
10133 UINT64_C(0),
10134 UINT64_C(0),
10135 UINT64_C(0),
10136 UINT64_C(0),
10137 UINT64_C(0),
10138 UINT64_C(0),
10139 UINT64_C(0),
10140 UINT64_C(0),
10141 UINT64_C(0),
10142 UINT64_C(0),
10143 UINT64_C(0),
10144 UINT64_C(0),
10145 UINT64_C(0),
10146 UINT64_C(0),
10147 UINT64_C(0),
10148 UINT64_C(0),
10149 UINT64_C(0),
10150 UINT64_C(0),
10151 UINT64_C(0),
10152 UINT64_C(0),
10153 UINT64_C(0),
10154 UINT64_C(0),
10155 UINT64_C(0),
10156 UINT64_C(0),
10157 UINT64_C(0),
10158 UINT64_C(0),
10159 UINT64_C(0),
10160 UINT64_C(0),
10161 UINT64_C(0),
10162 UINT64_C(0),
10163 UINT64_C(0),
10164 UINT64_C(0),
10165 UINT64_C(0),
10166 UINT64_C(0),
10167 UINT64_C(0),
10168 UINT64_C(0),
10169 UINT64_C(0),
10170 UINT64_C(0),
10171 UINT64_C(0),
10172 UINT64_C(0),
10173 UINT64_C(0),
10174 UINT64_C(0),
10175 UINT64_C(0),
10176 UINT64_C(0),
10177 UINT64_C(0),
10178 UINT64_C(0),
10179 UINT64_C(0),
10180 UINT64_C(0),
10181 UINT64_C(0),
10182 UINT64_C(0),
10183 UINT64_C(0),
10184 UINT64_C(0),
10185 UINT64_C(0),
10186 UINT64_C(0),
10187 UINT64_C(0),
10188 UINT64_C(0),
10189 UINT64_C(0),
10190 UINT64_C(0),
10191 UINT64_C(0),
10192 UINT64_C(0),
10193 UINT64_C(0),
10194 UINT64_C(0),
10195 UINT64_C(0),
10196 UINT64_C(0),
10197 UINT64_C(0),
10198 UINT64_C(0),
10199 UINT64_C(0),
10200 UINT64_C(0),
10201 UINT64_C(0),
10202 UINT64_C(0),
10203 UINT64_C(0),
10204 UINT64_C(0),
10205 UINT64_C(0),
10206 UINT64_C(0),
10207 UINT64_C(0),
10208 UINT64_C(0),
10209 UINT64_C(0),
10210 UINT64_C(0),
10211 UINT64_C(0),
10212 UINT64_C(0),
10213 UINT64_C(0),
10214 UINT64_C(0),
10215 UINT64_C(0),
10216 UINT64_C(0),
10217 UINT64_C(0),
10218 UINT64_C(0),
10219 UINT64_C(0),
10220 UINT64_C(0),
10221 UINT64_C(0),
10222 UINT64_C(0),
10223 UINT64_C(0),
10224 UINT64_C(0),
10225 UINT64_C(0),
10226 UINT64_C(0),
10227 UINT64_C(0),
10228 UINT64_C(0),
10229 UINT64_C(0),
10230 UINT64_C(0),
10231 UINT64_C(0),
10232 UINT64_C(0),
10233 UINT64_C(0),
10234 UINT64_C(0),
10235 UINT64_C(0),
10236 UINT64_C(0),
10237 UINT64_C(0),
10238 UINT64_C(0),
10239 UINT64_C(0),
10240 UINT64_C(0),
10241 UINT64_C(0),
10242 UINT64_C(0),
10243 UINT64_C(0),
10244 UINT64_C(0),
10245 UINT64_C(0),
10246 UINT64_C(0),
10247 UINT64_C(0),
10248 UINT64_C(0),
10249 UINT64_C(0),
10250 UINT64_C(0),
10251 UINT64_C(0),
10252 UINT64_C(0),
10253 UINT64_C(0),
10254 UINT64_C(0),
10255 UINT64_C(0),
10256 UINT64_C(0),
10257 UINT64_C(0),
10258 UINT64_C(0),
10259 UINT64_C(0),
10260 UINT64_C(0),
10261 UINT64_C(0),
10262 UINT64_C(0),
10263 UINT64_C(0),
10264 UINT64_C(0),
10265 UINT64_C(0),
10266 UINT64_C(0),
10267 UINT64_C(0),
10268 UINT64_C(0),
10269 UINT64_C(0),
10270 UINT64_C(0),
10271 UINT64_C(0),
10272 UINT64_C(0),
10273 UINT64_C(0),
10274 UINT64_C(0),
10275 UINT64_C(0),
10276 UINT64_C(0),
10277 UINT64_C(0),
10278 UINT64_C(0),
10279 UINT64_C(0),
10280 UINT64_C(0),
10281 UINT64_C(0),
10282 UINT64_C(0),
10283 UINT64_C(0),
10284 UINT64_C(0),
10285 UINT64_C(0),
10286 UINT64_C(0),
10287 UINT64_C(0),
10288 UINT64_C(0),
10289 UINT64_C(0),
10290 UINT64_C(0),
10291 UINT64_C(0),
10292 UINT64_C(0),
10293 UINT64_C(0),
10294 UINT64_C(0),
10295 UINT64_C(0),
10296 UINT64_C(0),
10297 UINT64_C(0),
10298 UINT64_C(0),
10299 UINT64_C(0),
10300 UINT64_C(0),
10301 UINT64_C(0),
10302 UINT64_C(0),
10303 UINT64_C(0),
10304 UINT64_C(0),
10305 UINT64_C(0),
10306 UINT64_C(0),
10307 UINT64_C(0),
10308 UINT64_C(0),
10309 UINT64_C(0),
10310 UINT64_C(0),
10311 UINT64_C(0),
10312 UINT64_C(0),
10313 UINT64_C(0),
10314 UINT64_C(0),
10315 UINT64_C(0),
10316 UINT64_C(0),
10317 UINT64_C(0),
10318 UINT64_C(0),
10319 UINT64_C(0),
10320 UINT64_C(0),
10321 UINT64_C(0),
10322 UINT64_C(0),
10323 UINT64_C(0),
10324 UINT64_C(0),
10325 UINT64_C(0),
10326 UINT64_C(0),
10327 UINT64_C(0),
10328 UINT64_C(0),
10329 UINT64_C(0),
10330 UINT64_C(0),
10331 UINT64_C(0),
10332 UINT64_C(0),
10333 UINT64_C(0),
10334 UINT64_C(0),
10335 UINT64_C(0),
10336 UINT64_C(0),
10337 UINT64_C(0),
10338 UINT64_C(0),
10339 UINT64_C(0),
10340 UINT64_C(0),
10341 UINT64_C(0),
10342 UINT64_C(0),
10343 UINT64_C(0),
10344 UINT64_C(0),
10345 UINT64_C(0),
10346 UINT64_C(0),
10347 UINT64_C(0),
10348 UINT64_C(0),
10349 UINT64_C(0),
10350 UINT64_C(0),
10351 UINT64_C(0),
10352 UINT64_C(0),
10353 UINT64_C(0),
10354 UINT64_C(0),
10355 UINT64_C(0),
10356 UINT64_C(0),
10357 UINT64_C(0),
10358 UINT64_C(0),
10359 UINT64_C(0),
10360 UINT64_C(0),
10361 UINT64_C(0),
10362 UINT64_C(0),
10363 UINT64_C(0),
10364 UINT64_C(0),
10365 UINT64_C(0),
10366 UINT64_C(0),
10367 UINT64_C(0),
10368 UINT64_C(0),
10369 UINT64_C(0),
10370 UINT64_C(0),
10371 UINT64_C(0),
10372 UINT64_C(0),
10373 UINT64_C(0),
10374 UINT64_C(0),
10375 UINT64_C(0),
10376 UINT64_C(0),
10377 UINT64_C(0),
10378 UINT64_C(0),
10379 UINT64_C(0),
10380 UINT64_C(0),
10381 UINT64_C(0),
10382 UINT64_C(0),
10383 UINT64_C(0),
10384 UINT64_C(0),
10385 UINT64_C(0),
10386 UINT64_C(0),
10387 UINT64_C(0),
10388 UINT64_C(0),
10389 UINT64_C(0),
10390 UINT64_C(0),
10391 UINT64_C(0),
10392 UINT64_C(0),
10393 UINT64_C(0),
10394 UINT64_C(0),
10395 UINT64_C(0),
10396 UINT64_C(0),
10397 UINT64_C(0),
10398 UINT64_C(0),
10399 UINT64_C(0),
10400 UINT64_C(0),
10401 UINT64_C(0),
10402 UINT64_C(0),
10403 UINT64_C(0),
10404 UINT64_C(0),
10405 UINT64_C(0),
10406 UINT64_C(0),
10407 UINT64_C(0),
10408 UINT64_C(0),
10409 UINT64_C(0),
10410 UINT64_C(0),
10411 UINT64_C(0),
10412 UINT64_C(0),
10413 UINT64_C(0),
10414 UINT64_C(0),
10415 UINT64_C(0),
10416 UINT64_C(0),
10417 UINT64_C(0),
10418 UINT64_C(0),
10419 UINT64_C(0),
10420 UINT64_C(0),
10421 UINT64_C(0),
10422 UINT64_C(0),
10423 UINT64_C(0),
10424 UINT64_C(0),
10425 UINT64_C(0),
10426 UINT64_C(0),
10427 UINT64_C(0),
10428 UINT64_C(0),
10429 UINT64_C(0),
10430 UINT64_C(0),
10431 UINT64_C(0),
10432 UINT64_C(0),
10433 UINT64_C(0),
10434 UINT64_C(0),
10435 UINT64_C(0),
10436 UINT64_C(0),
10437 UINT64_C(0),
10438 UINT64_C(0),
10439 UINT64_C(0),
10440 UINT64_C(0),
10441 UINT64_C(0),
10442 UINT64_C(0),
10443 UINT64_C(0),
10444 UINT64_C(0),
10445 UINT64_C(0),
10446 UINT64_C(0),
10447 UINT64_C(0),
10448 UINT64_C(0),
10449 UINT64_C(0),
10450 UINT64_C(0),
10451 UINT64_C(0),
10452 UINT64_C(0),
10453 UINT64_C(0),
10454 UINT64_C(0),
10455 UINT64_C(0),
10456 UINT64_C(0),
10457 UINT64_C(0),
10458 UINT64_C(0),
10459 UINT64_C(0),
10460 UINT64_C(0),
10461 UINT64_C(0),
10462 UINT64_C(0),
10463 UINT64_C(0),
10464 UINT64_C(0),
10465 UINT64_C(0),
10466 UINT64_C(0),
10467 UINT64_C(0),
10468 UINT64_C(0),
10469 UINT64_C(0),
10470 UINT64_C(0),
10471 UINT64_C(0),
10472 UINT64_C(0),
10473 UINT64_C(0),
10474 UINT64_C(0),
10475 UINT64_C(0),
10476 UINT64_C(0),
10477 UINT64_C(0),
10478 UINT64_C(0),
10479 UINT64_C(0),
10480 UINT64_C(0),
10481 UINT64_C(0),
10482 UINT64_C(0),
10483 UINT64_C(0),
10484 UINT64_C(0),
10485 UINT64_C(0),
10486 UINT64_C(0),
10487 UINT64_C(0),
10488 UINT64_C(0),
10489 UINT64_C(0),
10490 UINT64_C(0),
10491 UINT64_C(0),
10492 UINT64_C(0),
10493 UINT64_C(0),
10494 UINT64_C(0),
10495 UINT64_C(0),
10496 UINT64_C(0),
10497 UINT64_C(0),
10498 UINT64_C(0),
10499 UINT64_C(0),
10500 UINT64_C(0),
10501 UINT64_C(0),
10502 UINT64_C(0),
10503 UINT64_C(0),
10504 UINT64_C(0),
10505 UINT64_C(0),
10506 UINT64_C(0),
10507 UINT64_C(0),
10508 UINT64_C(0),
10509 UINT64_C(0),
10510 UINT64_C(0),
10511 UINT64_C(0),
10512 UINT64_C(0),
10513 UINT64_C(0),
10514 UINT64_C(0),
10515 UINT64_C(0),
10516 UINT64_C(0),
10517 UINT64_C(0),
10518 UINT64_C(0),
10519 UINT64_C(0),
10520 UINT64_C(0),
10521 UINT64_C(0),
10522 UINT64_C(0),
10523 UINT64_C(0),
10524 UINT64_C(0),
10525 UINT64_C(0),
10526 UINT64_C(0),
10527 UINT64_C(0),
10528 UINT64_C(0),
10529 UINT64_C(0),
10530 UINT64_C(0),
10531 UINT64_C(0),
10532 UINT64_C(0),
10533 UINT64_C(0),
10534 UINT64_C(0),
10535 UINT64_C(0),
10536 UINT64_C(0),
10537 UINT64_C(0),
10538 UINT64_C(0),
10539 UINT64_C(0),
10540 UINT64_C(0),
10541 UINT64_C(0),
10542 UINT64_C(0),
10543 UINT64_C(0),
10544 UINT64_C(0),
10545 UINT64_C(0),
10546 UINT64_C(0),
10547 UINT64_C(0),
10548 UINT64_C(0),
10549 UINT64_C(0),
10550 UINT64_C(0),
10551 UINT64_C(0),
10552 UINT64_C(0),
10553 UINT64_C(0),
10554 UINT64_C(0),
10555 UINT64_C(0),
10556 UINT64_C(0),
10557 UINT64_C(0),
10558 UINT64_C(0),
10559 UINT64_C(0),
10560 UINT64_C(0),
10561 UINT64_C(0),
10562 UINT64_C(0),
10563 UINT64_C(0),
10564 UINT64_C(0),
10565 UINT64_C(0),
10566 UINT64_C(0),
10567 UINT64_C(0),
10568 UINT64_C(0),
10569 UINT64_C(0),
10570 UINT64_C(0),
10571 UINT64_C(0),
10572 UINT64_C(0),
10573 UINT64_C(0),
10574 UINT64_C(0),
10575 UINT64_C(0),
10576 UINT64_C(0),
10577 UINT64_C(0),
10578 UINT64_C(0),
10579 UINT64_C(0),
10580 UINT64_C(0),
10581 UINT64_C(0),
10582 UINT64_C(0),
10583 UINT64_C(0),
10584 UINT64_C(0),
10585 UINT64_C(0),
10586 UINT64_C(0),
10587 UINT64_C(0),
10588 UINT64_C(0),
10589 UINT64_C(0),
10590 UINT64_C(0),
10591 UINT64_C(0),
10592 UINT64_C(0),
10593 UINT64_C(0),
10594 UINT64_C(0),
10595 UINT64_C(0),
10596 UINT64_C(0),
10597 UINT64_C(0),
10598 UINT64_C(0),
10599 UINT64_C(0),
10600 UINT64_C(0),
10601 UINT64_C(0),
10602 UINT64_C(0),
10603 UINT64_C(0),
10604 UINT64_C(0),
10605 UINT64_C(0),
10606 UINT64_C(0),
10607 UINT64_C(0),
10608 UINT64_C(0),
10609 UINT64_C(0),
10610 UINT64_C(0),
10611 UINT64_C(0),
10612 UINT64_C(0),
10613 UINT64_C(0),
10614 UINT64_C(0),
10615 UINT64_C(0),
10616 UINT64_C(0),
10617 UINT64_C(0),
10618 UINT64_C(0),
10619 UINT64_C(0),
10620 UINT64_C(0),
10621 UINT64_C(0),
10622 UINT64_C(0),
10623 UINT64_C(0),
10624 UINT64_C(0),
10625 UINT64_C(0),
10626 UINT64_C(0),
10627 UINT64_C(0),
10628 UINT64_C(0),
10629 UINT64_C(0),
10630 UINT64_C(0),
10631 UINT64_C(0),
10632 UINT64_C(0),
10633 UINT64_C(0),
10634 UINT64_C(0),
10635 UINT64_C(0),
10636 UINT64_C(0),
10637 UINT64_C(0),
10638 UINT64_C(0),
10639 UINT64_C(0),
10640 UINT64_C(0),
10641 UINT64_C(0),
10642 UINT64_C(0),
10643 UINT64_C(0),
10644 UINT64_C(0),
10645 UINT64_C(0),
10646 UINT64_C(0),
10647 UINT64_C(0),
10648 UINT64_C(0),
10649 UINT64_C(0),
10650 UINT64_C(0),
10651 UINT64_C(0),
10652 UINT64_C(0),
10653 UINT64_C(0),
10654 UINT64_C(0),
10655 UINT64_C(0),
10656 UINT64_C(0),
10657 UINT64_C(0),
10658 UINT64_C(0),
10659 UINT64_C(0),
10660 UINT64_C(0),
10661 UINT64_C(0),
10662 UINT64_C(0),
10663 UINT64_C(0),
10664 UINT64_C(0),
10665 UINT64_C(0),
10666 UINT64_C(0),
10667 UINT64_C(0),
10668 UINT64_C(0),
10669 UINT64_C(0),
10670 UINT64_C(0),
10671 UINT64_C(0),
10672 UINT64_C(0),
10673 UINT64_C(0),
10674 UINT64_C(0),
10675 UINT64_C(0),
10676 UINT64_C(0),
10677 UINT64_C(0),
10678 UINT64_C(0),
10679 UINT64_C(0),
10680 UINT64_C(0),
10681 UINT64_C(0),
10682 UINT64_C(0),
10683 UINT64_C(0),
10684 UINT64_C(0),
10685 UINT64_C(0),
10686 UINT64_C(0),
10687 UINT64_C(0),
10688 UINT64_C(0),
10689 UINT64_C(0),
10690 UINT64_C(0),
10691 UINT64_C(0),
10692 UINT64_C(0),
10693 UINT64_C(0),
10694 UINT64_C(0),
10695 UINT64_C(0),
10696 UINT64_C(0),
10697 UINT64_C(0),
10698 UINT64_C(0),
10699 UINT64_C(0),
10700 UINT64_C(0),
10701 UINT64_C(0),
10702 UINT64_C(0),
10703 UINT64_C(0),
10704 UINT64_C(0),
10705 UINT64_C(0),
10706 UINT64_C(0),
10707 UINT64_C(0),
10708 UINT64_C(0),
10709 UINT64_C(0),
10710 UINT64_C(0),
10711 UINT64_C(0),
10712 UINT64_C(0),
10713 UINT64_C(0),
10714 UINT64_C(0),
10715 UINT64_C(0),
10716 UINT64_C(0),
10717 UINT64_C(0),
10718 UINT64_C(0),
10719 UINT64_C(0),
10720 UINT64_C(0),
10721 UINT64_C(0),
10722 UINT64_C(0),
10723 UINT64_C(0),
10724 UINT64_C(0),
10725 UINT64_C(0),
10726 UINT64_C(0),
10727 UINT64_C(0),
10728 UINT64_C(0),
10729 UINT64_C(0),
10730 UINT64_C(0),
10731 UINT64_C(0),
10732 UINT64_C(0),
10733 UINT64_C(0),
10734 UINT64_C(0),
10735 UINT64_C(0),
10736 UINT64_C(0),
10737 UINT64_C(0),
10738 UINT64_C(0),
10739 UINT64_C(0),
10740 UINT64_C(0),
10741 UINT64_C(0),
10742 UINT64_C(0),
10743 UINT64_C(0),
10744 UINT64_C(0),
10745 UINT64_C(0),
10746 UINT64_C(0),
10747 UINT64_C(0),
10748 UINT64_C(0),
10749 UINT64_C(0),
10750 UINT64_C(0),
10751 UINT64_C(0),
10752 UINT64_C(0),
10753 UINT64_C(0),
10754 UINT64_C(0),
10755 UINT64_C(0),
10756 UINT64_C(0),
10757 UINT64_C(0),
10758 UINT64_C(0),
10759 UINT64_C(0),
10760 UINT64_C(0),
10761 UINT64_C(0),
10762 UINT64_C(0),
10763 UINT64_C(0),
10764 UINT64_C(0),
10765 UINT64_C(0),
10766 UINT64_C(0),
10767 UINT64_C(0),
10768 UINT64_C(0),
10769 UINT64_C(0),
10770 UINT64_C(0),
10771 UINT64_C(0),
10772 UINT64_C(0),
10773 UINT64_C(0),
10774 UINT64_C(0),
10775 UINT64_C(0),
10776 UINT64_C(0),
10777 UINT64_C(0),
10778 UINT64_C(0),
10779 UINT64_C(0),
10780 UINT64_C(0),
10781 UINT64_C(0),
10782 UINT64_C(0),
10783 UINT64_C(0),
10784 UINT64_C(0),
10785 UINT64_C(0),
10786 UINT64_C(0),
10787 UINT64_C(0),
10788 UINT64_C(0),
10789 UINT64_C(0),
10790 UINT64_C(0),
10791 UINT64_C(0),
10792 UINT64_C(0),
10793 UINT64_C(0),
10794 UINT64_C(0),
10795 UINT64_C(0),
10796 UINT64_C(0),
10797 UINT64_C(0),
10798 UINT64_C(0),
10799 UINT64_C(0),
10800 UINT64_C(0),
10801 UINT64_C(0),
10802 UINT64_C(0),
10803 UINT64_C(0),
10804 UINT64_C(0),
10805 UINT64_C(0),
10806 UINT64_C(0),
10807 UINT64_C(0),
10808 UINT64_C(0),
10809 UINT64_C(0),
10810 UINT64_C(0),
10811 UINT64_C(0),
10812 UINT64_C(0),
10813 UINT64_C(0),
10814 UINT64_C(0),
10815 UINT64_C(0),
10816 UINT64_C(0),
10817 UINT64_C(0),
10818 UINT64_C(0),
10819 UINT64_C(0),
10820 UINT64_C(0),
10821 UINT64_C(0),
10822 UINT64_C(0),
10823 UINT64_C(0),
10824 UINT64_C(0),
10825 UINT64_C(0),
10826 UINT64_C(0),
10827 UINT64_C(0),
10828 UINT64_C(0),
10829 UINT64_C(0),
10830 UINT64_C(0),
10831 UINT64_C(0),
10832 UINT64_C(0),
10833 UINT64_C(0),
10834 UINT64_C(0),
10835 UINT64_C(0),
10836 UINT64_C(0),
10837 UINT64_C(0),
10838 UINT64_C(0),
10839 UINT64_C(0),
10840 UINT64_C(0),
10841 UINT64_C(0),
10842 UINT64_C(0),
10843 UINT64_C(0),
10844 UINT64_C(0),
10845 UINT64_C(0),
10846 UINT64_C(0),
10847 UINT64_C(0),
10848 UINT64_C(0),
10849 UINT64_C(0),
10850 UINT64_C(0),
10851 UINT64_C(0),
10852 UINT64_C(0),
10853 UINT64_C(0),
10854 UINT64_C(0),
10855 UINT64_C(0),
10856 UINT64_C(0),
10857 UINT64_C(0),
10858 UINT64_C(0),
10859 UINT64_C(0),
10860 UINT64_C(0),
10861 UINT64_C(0),
10862 UINT64_C(0),
10863 UINT64_C(0),
10864 UINT64_C(0),
10865 UINT64_C(0),
10866 UINT64_C(0),
10867 UINT64_C(0),
10868 UINT64_C(0),
10869 UINT64_C(0),
10870 UINT64_C(0),
10871 UINT64_C(0),
10872 UINT64_C(0),
10873 UINT64_C(0),
10874 UINT64_C(0),
10875 UINT64_C(0),
10876 UINT64_C(0),
10877 UINT64_C(0),
10878 UINT64_C(0),
10879 UINT64_C(0),
10880 UINT64_C(0),
10881 UINT64_C(0),
10882 UINT64_C(0),
10883 UINT64_C(0),
10884 UINT64_C(0),
10885 UINT64_C(0),
10886 UINT64_C(0),
10887 UINT64_C(0),
10888 UINT64_C(0),
10889 UINT64_C(0),
10890 UINT64_C(0),
10891 UINT64_C(0),
10892 UINT64_C(0),
10893 UINT64_C(0),
10894 UINT64_C(0),
10895 UINT64_C(0),
10896 UINT64_C(0),
10897 UINT64_C(0),
10898 UINT64_C(0),
10899 UINT64_C(0),
10900 UINT64_C(0),
10901 UINT64_C(0),
10902 UINT64_C(0),
10903 UINT64_C(0),
10904 UINT64_C(0),
10905 UINT64_C(0),
10906 UINT64_C(0),
10907 UINT64_C(0),
10908 UINT64_C(0),
10909 UINT64_C(0),
10910 UINT64_C(0),
10911 UINT64_C(0),
10912 UINT64_C(0),
10913 UINT64_C(0),
10914 UINT64_C(0),
10915 UINT64_C(0),
10916 UINT64_C(0),
10917 UINT64_C(0),
10918 UINT64_C(0),
10919 UINT64_C(0),
10920 UINT64_C(0),
10921 UINT64_C(0),
10922 UINT64_C(0),
10923 UINT64_C(0),
10924 UINT64_C(0),
10925 UINT64_C(0),
10926 UINT64_C(0),
10927 UINT64_C(0),
10928 UINT64_C(0),
10929 UINT64_C(0),
10930 UINT64_C(0),
10931 UINT64_C(0),
10932 UINT64_C(0),
10933 UINT64_C(0),
10934 UINT64_C(0),
10935 UINT64_C(0),
10936 UINT64_C(0),
10937 UINT64_C(0),
10938 UINT64_C(0),
10939 UINT64_C(0),
10940 UINT64_C(0),
10941 UINT64_C(0),
10942 UINT64_C(0),
10943 UINT64_C(0),
10944 UINT64_C(0),
10945 UINT64_C(0),
10946 UINT64_C(0),
10947 UINT64_C(0),
10948 UINT64_C(0),
10949 UINT64_C(0),
10950 UINT64_C(0),
10951 UINT64_C(0),
10952 UINT64_C(0),
10953 UINT64_C(0),
10954 UINT64_C(0),
10955 UINT64_C(0),
10956 UINT64_C(0),
10957 UINT64_C(0),
10958 UINT64_C(0),
10959 UINT64_C(0),
10960 UINT64_C(0),
10961 UINT64_C(0),
10962 UINT64_C(0),
10963 UINT64_C(0),
10964 UINT64_C(0),
10965 UINT64_C(0),
10966 UINT64_C(0),
10967 UINT64_C(0),
10968 UINT64_C(0),
10969 UINT64_C(0),
10970 UINT64_C(0),
10971 UINT64_C(0),
10972 UINT64_C(0),
10973 UINT64_C(0),
10974 UINT64_C(0),
10975 UINT64_C(0),
10976 UINT64_C(0),
10977 UINT64_C(0),
10978 UINT64_C(0),
10979 UINT64_C(0),
10980 UINT64_C(0),
10981 UINT64_C(0),
10982 UINT64_C(0),
10983 UINT64_C(0),
10984 UINT64_C(0),
10985 UINT64_C(0),
10986 UINT64_C(0),
10987 UINT64_C(0),
10988 UINT64_C(0),
10989 UINT64_C(0),
10990 UINT64_C(0),
10991 UINT64_C(0),
10992 UINT64_C(0),
10993 UINT64_C(0),
10994 UINT64_C(0),
10995 UINT64_C(0),
10996 UINT64_C(0),
10997 UINT64_C(0),
10998 UINT64_C(0),
10999 UINT64_C(0),
11000 UINT64_C(0),
11001 UINT64_C(0),
11002 UINT64_C(0),
11003 UINT64_C(0),
11004 UINT64_C(0),
11005 UINT64_C(0),
11006 UINT64_C(0),
11007 UINT64_C(0),
11008 UINT64_C(0),
11009 UINT64_C(0),
11010 UINT64_C(0),
11011 UINT64_C(0),
11012 UINT64_C(0),
11013 UINT64_C(0),
11014 UINT64_C(0),
11015 UINT64_C(0),
11016 UINT64_C(0),
11017 UINT64_C(0),
11018 UINT64_C(0),
11019 UINT64_C(0),
11020 UINT64_C(0),
11021 UINT64_C(0),
11022 UINT64_C(0),
11023 UINT64_C(0),
11024 UINT64_C(0),
11025 UINT64_C(0),
11026 UINT64_C(0),
11027 UINT64_C(0),
11028 UINT64_C(0),
11029 UINT64_C(0),
11030 UINT64_C(0),
11031 UINT64_C(0),
11032 UINT64_C(0),
11033 UINT64_C(0),
11034 UINT64_C(0),
11035 UINT64_C(0),
11036 UINT64_C(0),
11037 UINT64_C(0),
11038 UINT64_C(0),
11039 UINT64_C(0),
11040 UINT64_C(0),
11041 UINT64_C(0),
11042 UINT64_C(0),
11043 UINT64_C(0),
11044 UINT64_C(0),
11045 UINT64_C(0),
11046 UINT64_C(0),
11047 UINT64_C(0),
11048 UINT64_C(0),
11049 UINT64_C(0),
11050 UINT64_C(0),
11051 UINT64_C(0),
11052 UINT64_C(0),
11053 UINT64_C(0),
11054 UINT64_C(0),
11055 UINT64_C(0),
11056 UINT64_C(0),
11057 UINT64_C(0),
11058 UINT64_C(0),
11059 UINT64_C(0),
11060 UINT64_C(0),
11061 UINT64_C(0),
11062 UINT64_C(0),
11063 UINT64_C(0),
11064 UINT64_C(0),
11065 UINT64_C(0),
11066 UINT64_C(0),
11067 UINT64_C(0),
11068 UINT64_C(0),
11069 UINT64_C(0),
11070 UINT64_C(0),
11071 UINT64_C(0),
11072 UINT64_C(0),
11073 UINT64_C(0),
11074 UINT64_C(0),
11075 UINT64_C(0),
11076 UINT64_C(0),
11077 UINT64_C(0),
11078 UINT64_C(0),
11079 UINT64_C(0),
11080 UINT64_C(0),
11081 UINT64_C(0),
11082 UINT64_C(0),
11083 UINT64_C(0),
11084 UINT64_C(0),
11085 UINT64_C(0),
11086 UINT64_C(0),
11087 UINT64_C(0),
11088 UINT64_C(0),
11089 UINT64_C(0),
11090 UINT64_C(0),
11091 UINT64_C(0),
11092 UINT64_C(0),
11093 UINT64_C(0),
11094 UINT64_C(0),
11095 UINT64_C(0),
11096 UINT64_C(0),
11097 UINT64_C(0),
11098 UINT64_C(0),
11099 UINT64_C(0),
11100 UINT64_C(0),
11101 UINT64_C(0),
11102 UINT64_C(0),
11103 UINT64_C(0),
11104 UINT64_C(0),
11105 UINT64_C(0),
11106 UINT64_C(0),
11107 UINT64_C(0),
11108 UINT64_C(0),
11109 UINT64_C(0),
11110 UINT64_C(0),
11111 UINT64_C(0),
11112 UINT64_C(0),
11113 UINT64_C(0),
11114 UINT64_C(0),
11115 UINT64_C(0),
11116 UINT64_C(0),
11117 UINT64_C(0),
11118 UINT64_C(0),
11119 UINT64_C(0),
11120 UINT64_C(0),
11121 UINT64_C(0),
11122 UINT64_C(0),
11123 UINT64_C(0),
11124 UINT64_C(0),
11125 UINT64_C(0),
11126 UINT64_C(0),
11127 UINT64_C(0),
11128 UINT64_C(0),
11129 UINT64_C(0),
11130 UINT64_C(0),
11131 UINT64_C(0),
11132 UINT64_C(0),
11133 UINT64_C(0),
11134 UINT64_C(0),
11135 UINT64_C(0),
11136 UINT64_C(0),
11137 UINT64_C(0),
11138 UINT64_C(0),
11139 UINT64_C(0),
11140 UINT64_C(0),
11141 UINT64_C(0),
11142 UINT64_C(0),
11143 UINT64_C(0),
11144 UINT64_C(0),
11145 UINT64_C(0),
11146 UINT64_C(0),
11147 UINT64_C(0),
11148 UINT64_C(0),
11149 UINT64_C(0),
11150 UINT64_C(0),
11151 UINT64_C(0),
11152 UINT64_C(0),
11153 UINT64_C(0),
11154 UINT64_C(0),
11155 UINT64_C(0),
11156 UINT64_C(0),
11157 UINT64_C(0),
11158 UINT64_C(0),
11159 UINT64_C(0),
11160 UINT64_C(0),
11161 UINT64_C(0),
11162 UINT64_C(0),
11163 UINT64_C(0),
11164 UINT64_C(0),
11165 UINT64_C(0),
11166 UINT64_C(0),
11167 UINT64_C(0),
11168 UINT64_C(0),
11169 UINT64_C(0),
11170 UINT64_C(0),
11171 UINT64_C(0),
11172 UINT64_C(0),
11173 UINT64_C(0),
11174 UINT64_C(0),
11175 UINT64_C(0),
11176 UINT64_C(0),
11177 UINT64_C(0),
11178 UINT64_C(0),
11179 UINT64_C(0),
11180 UINT64_C(0),
11181 UINT64_C(0),
11182 UINT64_C(0),
11183 UINT64_C(0),
11184 UINT64_C(0),
11185 UINT64_C(0),
11186 UINT64_C(0),
11187 UINT64_C(0),
11188 UINT64_C(0),
11189 UINT64_C(0),
11190 UINT64_C(0),
11191 UINT64_C(0),
11192 UINT64_C(0),
11193 UINT64_C(0),
11194 UINT64_C(0),
11195 UINT64_C(0),
11196 UINT64_C(0),
11197 UINT64_C(0),
11198 UINT64_C(0),
11199 UINT64_C(0),
11200 UINT64_C(0),
11201 UINT64_C(0),
11202 UINT64_C(0),
11203 UINT64_C(0),
11204 UINT64_C(0),
11205 UINT64_C(0),
11206 UINT64_C(0),
11207 UINT64_C(0),
11208 UINT64_C(0),
11209 UINT64_C(0),
11210 UINT64_C(0),
11211 UINT64_C(0),
11212 UINT64_C(0),
11213 UINT64_C(0),
11214 UINT64_C(0),
11215 UINT64_C(0),
11216 UINT64_C(0),
11217 UINT64_C(0),
11218 UINT64_C(0),
11219 UINT64_C(0),
11220 UINT64_C(0),
11221 UINT64_C(0),
11222 UINT64_C(0),
11223 UINT64_C(0),
11224 UINT64_C(0),
11225 UINT64_C(0),
11226 UINT64_C(0),
11227 UINT64_C(0),
11228 UINT64_C(0),
11229 UINT64_C(0),
11230 UINT64_C(0),
11231 UINT64_C(0),
11232 UINT64_C(0),
11233 UINT64_C(0),
11234 UINT64_C(0),
11235 UINT64_C(0),
11236 UINT64_C(0),
11237 UINT64_C(0),
11238 UINT64_C(0),
11239 UINT64_C(0),
11240 UINT64_C(0),
11241 UINT64_C(0),
11242 UINT64_C(0),
11243 UINT64_C(0),
11244 UINT64_C(0),
11245 UINT64_C(0),
11246 UINT64_C(0),
11247 UINT64_C(0),
11248 UINT64_C(0),
11249 UINT64_C(0),
11250 UINT64_C(0),
11251 UINT64_C(0),
11252 UINT64_C(0),
11253 UINT64_C(0),
11254 UINT64_C(0),
11255 UINT64_C(0),
11256 UINT64_C(0),
11257 UINT64_C(0),
11258 UINT64_C(0),
11259 UINT64_C(0),
11260 UINT64_C(0),
11261 UINT64_C(0),
11262 UINT64_C(0),
11263 UINT64_C(0),
11264 UINT64_C(0),
11265 UINT64_C(0),
11266 UINT64_C(0),
11267 UINT64_C(0),
11268 UINT64_C(0),
11269 UINT64_C(0),
11270 UINT64_C(0),
11271 UINT64_C(0),
11272 UINT64_C(0),
11273 UINT64_C(0),
11274 UINT64_C(0),
11275 UINT64_C(0),
11276 UINT64_C(0),
11277 UINT64_C(0),
11278 UINT64_C(0),
11279 UINT64_C(0),
11280 UINT64_C(0),
11281 UINT64_C(0),
11282 UINT64_C(0),
11283 UINT64_C(0),
11284 UINT64_C(0),
11285 UINT64_C(0),
11286 UINT64_C(0),
11287 UINT64_C(0),
11288 UINT64_C(0),
11289 UINT64_C(0),
11290 UINT64_C(0),
11291 UINT64_C(0),
11292 UINT64_C(0),
11293 UINT64_C(0),
11294 UINT64_C(0),
11295 UINT64_C(0),
11296 UINT64_C(0),
11297 UINT64_C(0),
11298 UINT64_C(0),
11299 UINT64_C(0),
11300 UINT64_C(0),
11301 UINT64_C(0),
11302 UINT64_C(0),
11303 UINT64_C(0),
11304 UINT64_C(0),
11305 UINT64_C(0),
11306 UINT64_C(0),
11307 UINT64_C(0),
11308 UINT64_C(0),
11309 UINT64_C(0),
11310 UINT64_C(0),
11311 UINT64_C(0),
11312 UINT64_C(0),
11313 UINT64_C(0),
11314 UINT64_C(0),
11315 UINT64_C(0),
11316 UINT64_C(0),
11317 UINT64_C(0),
11318 UINT64_C(0),
11319 UINT64_C(0),
11320 UINT64_C(0),
11321 UINT64_C(0),
11322 UINT64_C(0),
11323 UINT64_C(0),
11324 UINT64_C(0),
11325 UINT64_C(0),
11326 UINT64_C(0),
11327 UINT64_C(0),
11328 UINT64_C(0),
11329 UINT64_C(0),
11330 UINT64_C(0),
11331 UINT64_C(0),
11332 UINT64_C(0),
11333 UINT64_C(0),
11334 UINT64_C(0),
11335 UINT64_C(0),
11336 UINT64_C(0),
11337 UINT64_C(0),
11338 UINT64_C(0),
11339 UINT64_C(0),
11340 UINT64_C(0),
11341 UINT64_C(0),
11342 UINT64_C(0),
11343 UINT64_C(0),
11344 UINT64_C(0),
11345 UINT64_C(0),
11346 UINT64_C(0),
11347 UINT64_C(0),
11348 UINT64_C(0),
11349 UINT64_C(0),
11350 UINT64_C(0),
11351 UINT64_C(0),
11352 UINT64_C(0),
11353 UINT64_C(0),
11354 UINT64_C(0),
11355 UINT64_C(0),
11356 UINT64_C(0),
11357 UINT64_C(0),
11358 UINT64_C(0),
11359 UINT64_C(0),
11360 UINT64_C(0),
11361 UINT64_C(0),
11362 UINT64_C(0),
11363 UINT64_C(0),
11364 UINT64_C(0),
11365 UINT64_C(0),
11366 UINT64_C(0),
11367 UINT64_C(0),
11368 UINT64_C(0),
11369 UINT64_C(0),
11370 UINT64_C(0),
11371 UINT64_C(0),
11372 UINT64_C(0),
11373 UINT64_C(0),
11374 UINT64_C(0),
11375 UINT64_C(0),
11376 UINT64_C(0),
11377 UINT64_C(0),
11378 UINT64_C(0),
11379 UINT64_C(0),
11380 UINT64_C(0),
11381 UINT64_C(0),
11382 UINT64_C(0),
11383 UINT64_C(0),
11384 UINT64_C(0),
11385 UINT64_C(0),
11386 UINT64_C(0),
11387 UINT64_C(0),
11388 UINT64_C(0),
11389 UINT64_C(0),
11390 UINT64_C(0),
11391 UINT64_C(0),
11392 UINT64_C(0),
11393 UINT64_C(0),
11394 UINT64_C(0),
11395 UINT64_C(0),
11396 UINT64_C(0),
11397 UINT64_C(0),
11398 UINT64_C(0),
11399 UINT64_C(0),
11400 UINT64_C(0),
11401 UINT64_C(0),
11402 UINT64_C(0),
11403 UINT64_C(0),
11404 UINT64_C(0),
11405 UINT64_C(0),
11406 UINT64_C(0),
11407 UINT64_C(0),
11408 UINT64_C(0),
11409 UINT64_C(0),
11410 UINT64_C(0),
11411 UINT64_C(0),
11412 UINT64_C(0),
11413 UINT64_C(0),
11414 UINT64_C(0),
11415 UINT64_C(0),
11416 UINT64_C(0),
11417 UINT64_C(0),
11418 UINT64_C(0),
11419 UINT64_C(0),
11420 UINT64_C(0),
11421 UINT64_C(0),
11422 UINT64_C(0),
11423 UINT64_C(0),
11424 UINT64_C(0),
11425 UINT64_C(0),
11426 UINT64_C(0),
11427 UINT64_C(0),
11428 UINT64_C(0),
11429 UINT64_C(0),
11430 UINT64_C(0),
11431 UINT64_C(0),
11432 UINT64_C(0),
11433 UINT64_C(0),
11434 UINT64_C(0),
11435 UINT64_C(0),
11436 UINT64_C(0),
11437 UINT64_C(0),
11438 UINT64_C(0),
11439 UINT64_C(0),
11440 UINT64_C(0),
11441 UINT64_C(0),
11442 UINT64_C(0),
11443 UINT64_C(0),
11444 UINT64_C(0),
11445 UINT64_C(0),
11446 UINT64_C(0),
11447 UINT64_C(0),
11448 UINT64_C(0),
11449 UINT64_C(0),
11450 UINT64_C(0),
11451 UINT64_C(0),
11452 UINT64_C(0),
11453 UINT64_C(0),
11454 UINT64_C(0),
11455 UINT64_C(0),
11456 UINT64_C(0),
11457 UINT64_C(0),
11458 UINT64_C(0),
11459 UINT64_C(0),
11460 UINT64_C(0),
11461 UINT64_C(0),
11462 UINT64_C(0),
11463 UINT64_C(0),
11464 UINT64_C(0),
11465 UINT64_C(0),
11466 UINT64_C(0),
11467 UINT64_C(0),
11468 UINT64_C(0),
11469 UINT64_C(0),
11470 UINT64_C(0),
11471 UINT64_C(0),
11472 UINT64_C(0),
11473 UINT64_C(0),
11474 UINT64_C(0),
11475 UINT64_C(0),
11476 UINT64_C(0),
11477 UINT64_C(0),
11478 UINT64_C(0),
11479 UINT64_C(0),
11480 UINT64_C(0),
11481 UINT64_C(0),
11482 UINT64_C(0),
11483 UINT64_C(0),
11484 UINT64_C(0),
11485 UINT64_C(0),
11486 UINT64_C(0),
11487 UINT64_C(0),
11488 UINT64_C(0),
11489 UINT64_C(0),
11490 UINT64_C(0),
11491 UINT64_C(0),
11492 UINT64_C(0),
11493 UINT64_C(0),
11494 UINT64_C(0),
11495 UINT64_C(0),
11496 UINT64_C(0),
11497 UINT64_C(0),
11498 UINT64_C(0),
11499 UINT64_C(0),
11500 UINT64_C(0),
11501 UINT64_C(0),
11502 UINT64_C(0),
11503 UINT64_C(0),
11504 UINT64_C(0),
11505 UINT64_C(0),
11506 UINT64_C(0),
11507 UINT64_C(0),
11508 UINT64_C(0),
11509 UINT64_C(0),
11510 UINT64_C(0),
11511 UINT64_C(0),
11512 UINT64_C(0),
11513 UINT64_C(0),
11514 UINT64_C(0),
11515 UINT64_C(0),
11516 UINT64_C(0),
11517 UINT64_C(0),
11518 UINT64_C(0),
11519 UINT64_C(0),
11520 UINT64_C(0),
11521 UINT64_C(0),
11522 UINT64_C(0),
11523 UINT64_C(0),
11524 UINT64_C(0),
11525 UINT64_C(0),
11526 UINT64_C(0),
11527 UINT64_C(0),
11528 UINT64_C(0),
11529 UINT64_C(0),
11530 UINT64_C(0),
11531 UINT64_C(0),
11532 UINT64_C(0),
11533 UINT64_C(0),
11534 UINT64_C(0),
11535 UINT64_C(0),
11536 UINT64_C(0),
11537 UINT64_C(0),
11538 UINT64_C(0),
11539 UINT64_C(0),
11540 UINT64_C(0),
11541 UINT64_C(0),
11542 UINT64_C(0),
11543 UINT64_C(0),
11544 UINT64_C(0),
11545 UINT64_C(0),
11546 UINT64_C(0),
11547 UINT64_C(0),
11548 UINT64_C(0),
11549 UINT64_C(0),
11550 UINT64_C(0),
11551 UINT64_C(0),
11552 UINT64_C(0),
11553 UINT64_C(0),
11554 UINT64_C(0),
11555 UINT64_C(0),
11556 UINT64_C(0),
11557 UINT64_C(0),
11558 UINT64_C(0),
11559 UINT64_C(0),
11560 UINT64_C(0),
11561 UINT64_C(0),
11562 UINT64_C(0),
11563 UINT64_C(0),
11564 UINT64_C(0),
11565 UINT64_C(0),
11566 UINT64_C(0),
11567 UINT64_C(0),
11568 UINT64_C(0),
11569 UINT64_C(0),
11570 UINT64_C(0),
11571 UINT64_C(0),
11572 UINT64_C(0),
11573 UINT64_C(0),
11574 UINT64_C(0),
11575 UINT64_C(0),
11576 UINT64_C(0),
11577 UINT64_C(0),
11578 UINT64_C(0),
11579 UINT64_C(0),
11580 UINT64_C(0),
11581 UINT64_C(0),
11582 UINT64_C(0),
11583 UINT64_C(0),
11584 UINT64_C(0),
11585 UINT64_C(0),
11586 UINT64_C(0),
11587 UINT64_C(0),
11588 UINT64_C(0),
11589 UINT64_C(0),
11590 UINT64_C(0),
11591 UINT64_C(0),
11592 UINT64_C(0),
11593 UINT64_C(0),
11594 UINT64_C(0),
11595 UINT64_C(0),
11596 UINT64_C(0),
11597 UINT64_C(0),
11598 UINT64_C(0),
11599 UINT64_C(0),
11600 UINT64_C(0),
11601 UINT64_C(0),
11602 UINT64_C(0),
11603 UINT64_C(0),
11604 UINT64_C(0),
11605 UINT64_C(0),
11606 UINT64_C(0),
11607 UINT64_C(0),
11608 UINT64_C(0),
11609 UINT64_C(0),
11610 UINT64_C(0),
11611 UINT64_C(0),
11612 UINT64_C(0),
11613 UINT64_C(0),
11614 UINT64_C(0),
11615 UINT64_C(0),
11616 UINT64_C(0),
11617 UINT64_C(0),
11618 UINT64_C(0),
11619 UINT64_C(0),
11620 UINT64_C(0),
11621 UINT64_C(0),
11622 UINT64_C(0),
11623 UINT64_C(0),
11624 UINT64_C(0),
11625 UINT64_C(0),
11626 UINT64_C(0),
11627 UINT64_C(0),
11628 UINT64_C(0),
11629 UINT64_C(0),
11630 UINT64_C(0),
11631 UINT64_C(0),
11632 UINT64_C(0),
11633 UINT64_C(0),
11634 UINT64_C(0),
11635 UINT64_C(0),
11636 UINT64_C(0),
11637 UINT64_C(0),
11638 UINT64_C(0),
11639 UINT64_C(0),
11640 UINT64_C(0),
11641 UINT64_C(0),
11642 UINT64_C(0),
11643 UINT64_C(0),
11644 UINT64_C(0),
11645 UINT64_C(0),
11646 UINT64_C(0),
11647 UINT64_C(0),
11648 UINT64_C(0),
11649 UINT64_C(0),
11650 UINT64_C(0),
11651 UINT64_C(0),
11652 UINT64_C(0),
11653 UINT64_C(0),
11654 UINT64_C(0),
11655 UINT64_C(0),
11656 UINT64_C(0),
11657 UINT64_C(0),
11658 UINT64_C(0),
11659 UINT64_C(0),
11660 UINT64_C(0),
11661 UINT64_C(0),
11662 UINT64_C(0),
11663 UINT64_C(0),
11664 UINT64_C(0),
11665 UINT64_C(0),
11666 UINT64_C(0),
11667 UINT64_C(0),
11668 UINT64_C(0),
11669 UINT64_C(0),
11670 UINT64_C(0),
11671 UINT64_C(0),
11672 UINT64_C(0),
11673 UINT64_C(0),
11674 UINT64_C(0),
11675 UINT64_C(0),
11676 UINT64_C(0),
11677 UINT64_C(0),
11678 UINT64_C(0),
11679 UINT64_C(0),
11680 UINT64_C(0),
11681 UINT64_C(0),
11682 UINT64_C(0),
11683 UINT64_C(0),
11684 UINT64_C(0),
11685 UINT64_C(0),
11686 UINT64_C(0),
11687 UINT64_C(0),
11688 UINT64_C(0),
11689 UINT64_C(0),
11690 UINT64_C(0),
11691 UINT64_C(0),
11692 UINT64_C(0),
11693 UINT64_C(0),
11694 UINT64_C(0),
11695 UINT64_C(0),
11696 UINT64_C(0),
11697 UINT64_C(0),
11698 UINT64_C(0),
11699 UINT64_C(0),
11700 UINT64_C(0),
11701 UINT64_C(0),
11702 UINT64_C(0),
11703 UINT64_C(0),
11704 UINT64_C(0),
11705 UINT64_C(0),
11706 UINT64_C(0),
11707 UINT64_C(0),
11708 UINT64_C(0),
11709 UINT64_C(0),
11710 UINT64_C(0),
11711 UINT64_C(0),
11712 UINT64_C(0),
11713 UINT64_C(0),
11714 UINT64_C(0),
11715 UINT64_C(0),
11716 UINT64_C(0),
11717 UINT64_C(0),
11718 UINT64_C(0),
11719 UINT64_C(0),
11720 UINT64_C(0),
11721 UINT64_C(0),
11722 UINT64_C(0),
11723 UINT64_C(0),
11724 UINT64_C(0),
11725 UINT64_C(0),
11726 UINT64_C(0),
11727 UINT64_C(0),
11728 UINT64_C(0),
11729 UINT64_C(0),
11730 UINT64_C(0),
11731 UINT64_C(0),
11732 UINT64_C(0),
11733 UINT64_C(0),
11734 UINT64_C(0),
11735 UINT64_C(0),
11736 UINT64_C(0),
11737 UINT64_C(0),
11738 UINT64_C(0),
11739 UINT64_C(0),
11740 UINT64_C(0),
11741 UINT64_C(0),
11742 UINT64_C(0),
11743 UINT64_C(0),
11744 UINT64_C(0),
11745 UINT64_C(0),
11746 UINT64_C(0),
11747 UINT64_C(0),
11748 UINT64_C(0),
11749 UINT64_C(0),
11750 UINT64_C(0),
11751 UINT64_C(0),
11752 UINT64_C(0),
11753 UINT64_C(0),
11754 UINT64_C(0),
11755 UINT64_C(0),
11756 UINT64_C(0),
11757 UINT64_C(0),
11758 UINT64_C(0),
11759 UINT64_C(0),
11760 UINT64_C(0),
11761 UINT64_C(0),
11762 UINT64_C(0),
11763 UINT64_C(0),
11764 UINT64_C(0),
11765 UINT64_C(0),
11766 UINT64_C(0),
11767 UINT64_C(0),
11768 UINT64_C(0),
11769 UINT64_C(0),
11770 UINT64_C(0),
11771 UINT64_C(0),
11772 UINT64_C(0),
11773 UINT64_C(0),
11774 UINT64_C(0),
11775 UINT64_C(0),
11776 UINT64_C(0),
11777 UINT64_C(0),
11778 UINT64_C(0),
11779 UINT64_C(0),
11780 UINT64_C(0),
11781 UINT64_C(0),
11782 UINT64_C(0),
11783 UINT64_C(0),
11784 UINT64_C(0),
11785 UINT64_C(0),
11786 UINT64_C(0),
11787 UINT64_C(0),
11788 UINT64_C(0),
11789 UINT64_C(0),
11790 UINT64_C(0),
11791 UINT64_C(0),
11792 UINT64_C(0),
11793 UINT64_C(0),
11794 UINT64_C(0),
11795 UINT64_C(0),
11796 UINT64_C(0),
11797 UINT64_C(0),
11798 UINT64_C(0),
11799 UINT64_C(0),
11800 UINT64_C(0),
11801 UINT64_C(0),
11802 UINT64_C(0),
11803 UINT64_C(0),
11804 UINT64_C(0),
11805 UINT64_C(0),
11806 UINT64_C(0),
11807 UINT64_C(0),
11808 UINT64_C(0),
11809 UINT64_C(0),
11810 UINT64_C(0),
11811 UINT64_C(0),
11812 UINT64_C(0),
11813 UINT64_C(0),
11814 UINT64_C(0),
11815 UINT64_C(0),
11816 UINT64_C(0),
11817 UINT64_C(0),
11818 UINT64_C(0),
11819 UINT64_C(0),
11820 UINT64_C(0),
11821 UINT64_C(0),
11822 UINT64_C(0),
11823 UINT64_C(0),
11824 UINT64_C(0),
11825 UINT64_C(0),
11826 UINT64_C(0),
11827 UINT64_C(0),
11828 UINT64_C(0),
11829 UINT64_C(0),
11830 UINT64_C(0),
11831 UINT64_C(0),
11832 UINT64_C(0),
11833 UINT64_C(0),
11834 UINT64_C(0),
11835 UINT64_C(0),
11836 UINT64_C(0),
11837 UINT64_C(0),
11838 UINT64_C(0),
11839 UINT64_C(0),
11840 UINT64_C(0),
11841 UINT64_C(0),
11842 UINT64_C(0),
11843 UINT64_C(0),
11844 UINT64_C(0),
11845 UINT64_C(0),
11846 UINT64_C(0),
11847 UINT64_C(0),
11848 UINT64_C(0),
11849 UINT64_C(0),
11850 UINT64_C(0),
11851 UINT64_C(0),
11852 UINT64_C(0),
11853 UINT64_C(0),
11854 UINT64_C(0),
11855 UINT64_C(0),
11856 UINT64_C(0),
11857 UINT64_C(0),
11858 UINT64_C(0),
11859 UINT64_C(0),
11860 UINT64_C(0),
11861 UINT64_C(0),
11862 UINT64_C(0),
11863 UINT64_C(0),
11864 UINT64_C(0),
11865 UINT64_C(0),
11866 UINT64_C(0),
11867 UINT64_C(0),
11868 UINT64_C(0),
11869 UINT64_C(0),
11870 UINT64_C(0),
11871 UINT64_C(0),
11872 UINT64_C(0),
11873 UINT64_C(0),
11874 UINT64_C(0),
11875 UINT64_C(0),
11876 UINT64_C(0),
11877 UINT64_C(0),
11878 UINT64_C(0),
11879 UINT64_C(0),
11880 UINT64_C(0),
11881 UINT64_C(0),
11882 UINT64_C(0),
11883 UINT64_C(0),
11884 UINT64_C(0),
11885 UINT64_C(0),
11886 UINT64_C(0),
11887 UINT64_C(0),
11888 UINT64_C(0),
11889 UINT64_C(0),
11890 UINT64_C(0),
11891 UINT64_C(0),
11892 UINT64_C(0),
11893 UINT64_C(0),
11894 UINT64_C(0),
11895 UINT64_C(0),
11896 UINT64_C(0),
11897 UINT64_C(0),
11898 UINT64_C(0),
11899 UINT64_C(0),
11900 UINT64_C(0),
11901 UINT64_C(0),
11902 UINT64_C(0),
11903 UINT64_C(0),
11904 UINT64_C(0),
11905 UINT64_C(0),
11906 UINT64_C(0),
11907 UINT64_C(0),
11908 UINT64_C(0),
11909 UINT64_C(0),
11910 UINT64_C(0),
11911 UINT64_C(0),
11912 UINT64_C(0),
11913 UINT64_C(0),
11914 UINT64_C(0),
11915 UINT64_C(0),
11916 UINT64_C(0),
11917 UINT64_C(0),
11918 UINT64_C(0),
11919 UINT64_C(0),
11920 UINT64_C(0),
11921 UINT64_C(0),
11922 UINT64_C(0),
11923 UINT64_C(0),
11924 UINT64_C(0),
11925 UINT64_C(0),
11926 UINT64_C(0),
11927 UINT64_C(0),
11928 UINT64_C(0),
11929 UINT64_C(0),
11930 UINT64_C(0),
11931 UINT64_C(0),
11932 UINT64_C(0),
11933 UINT64_C(0),
11934 UINT64_C(0),
11935 UINT64_C(0),
11936 UINT64_C(0),
11937 UINT64_C(0),
11938 UINT64_C(0),
11939 UINT64_C(0),
11940 UINT64_C(0),
11941 UINT64_C(0),
11942 UINT64_C(0),
11943 UINT64_C(0),
11944 UINT64_C(0),
11945 UINT64_C(0),
11946 UINT64_C(0),
11947 UINT64_C(0),
11948 UINT64_C(0),
11949 UINT64_C(0),
11950 UINT64_C(0),
11951 UINT64_C(0),
11952 UINT64_C(0),
11953 UINT64_C(0),
11954 UINT64_C(0),
11955 UINT64_C(0),
11956 UINT64_C(0),
11957 UINT64_C(0),
11958 UINT64_C(0),
11959 UINT64_C(0),
11960 UINT64_C(0),
11961 UINT64_C(0),
11962 UINT64_C(0),
11963 UINT64_C(0),
11964 UINT64_C(0),
11965 UINT64_C(0),
11966 UINT64_C(0),
11967 UINT64_C(0),
11968 UINT64_C(0),
11969 UINT64_C(0),
11970 UINT64_C(0),
11971 UINT64_C(0),
11972 UINT64_C(0),
11973 UINT64_C(0),
11974 UINT64_C(0),
11975 UINT64_C(0),
11976 UINT64_C(0),
11977 UINT64_C(0),
11978 UINT64_C(0),
11979 UINT64_C(0),
11980 UINT64_C(0),
11981 UINT64_C(0),
11982 UINT64_C(0),
11983 UINT64_C(0),
11984 UINT64_C(0),
11985 UINT64_C(0),
11986 UINT64_C(0),
11987 UINT64_C(0),
11988 UINT64_C(0),
11989 UINT64_C(0),
11990 UINT64_C(0),
11991 UINT64_C(0),
11992 UINT64_C(0),
11993 UINT64_C(0),
11994 UINT64_C(0),
11995 UINT64_C(0),
11996 UINT64_C(0),
11997 UINT64_C(0),
11998 UINT64_C(0),
11999 UINT64_C(0),
12000 UINT64_C(0),
12001 UINT64_C(0),
12002 UINT64_C(0),
12003 UINT64_C(0),
12004 UINT64_C(0),
12005 UINT64_C(0),
12006 UINT64_C(0),
12007 UINT64_C(0),
12008 UINT64_C(0),
12009 UINT64_C(0),
12010 UINT64_C(0),
12011 UINT64_C(0),
12012 UINT64_C(0),
12013 UINT64_C(0),
12014 UINT64_C(0),
12015 UINT64_C(0),
12016 UINT64_C(0),
12017 UINT64_C(0),
12018 UINT64_C(0),
12019 UINT64_C(0),
12020 UINT64_C(0),
12021 UINT64_C(0),
12022 UINT64_C(0),
12023 UINT64_C(0),
12024 UINT64_C(0),
12025 UINT64_C(0),
12026 UINT64_C(0),
12027 UINT64_C(0),
12028 UINT64_C(1617956883), // ABS
12029 UINT64_C(1617956891), // ABSW
12030 UINT64_C(51), // ADD
12031 UINT64_C(19), // ADDI
12032 UINT64_C(27), // ADDIW
12033 UINT64_C(59), // ADDW
12034 UINT64_C(134217787), // ADD_UW
12035 UINT64_C(704643123), // AES32DSI
12036 UINT64_C(771751987), // AES32DSMI
12037 UINT64_C(570425395), // AES32ESI
12038 UINT64_C(637534259), // AES32ESMI
12039 UINT64_C(973078579), // AES64DS
12040 UINT64_C(1040187443), // AES64DSM
12041 UINT64_C(838860851), // AES64ES
12042 UINT64_C(905969715), // AES64ESM
12043 UINT64_C(805310483), // AES64IM
12044 UINT64_C(822087699), // AES64KS1I
12045 UINT64_C(2113929267), // AES64KS2
12046 UINT64_C(47), // AMOADD_B
12047 UINT64_C(67108911), // AMOADD_B_AQ
12048 UINT64_C(100663343), // AMOADD_B_AQ_RL
12049 UINT64_C(33554479), // AMOADD_B_RL
12050 UINT64_C(12335), // AMOADD_D
12051 UINT64_C(67121199), // AMOADD_D_AQ
12052 UINT64_C(100675631), // AMOADD_D_AQ_RL
12053 UINT64_C(33566767), // AMOADD_D_RL
12054 UINT64_C(4143), // AMOADD_H
12055 UINT64_C(67113007), // AMOADD_H_AQ
12056 UINT64_C(100667439), // AMOADD_H_AQ_RL
12057 UINT64_C(33558575), // AMOADD_H_RL
12058 UINT64_C(8239), // AMOADD_W
12059 UINT64_C(67117103), // AMOADD_W_AQ
12060 UINT64_C(100671535), // AMOADD_W_AQ_RL
12061 UINT64_C(33562671), // AMOADD_W_RL
12062 UINT64_C(1610612783), // AMOAND_B
12063 UINT64_C(1677721647), // AMOAND_B_AQ
12064 UINT64_C(1711276079), // AMOAND_B_AQ_RL
12065 UINT64_C(1644167215), // AMOAND_B_RL
12066 UINT64_C(1610625071), // AMOAND_D
12067 UINT64_C(1677733935), // AMOAND_D_AQ
12068 UINT64_C(1711288367), // AMOAND_D_AQ_RL
12069 UINT64_C(1644179503), // AMOAND_D_RL
12070 UINT64_C(1610616879), // AMOAND_H
12071 UINT64_C(1677725743), // AMOAND_H_AQ
12072 UINT64_C(1711280175), // AMOAND_H_AQ_RL
12073 UINT64_C(1644171311), // AMOAND_H_RL
12074 UINT64_C(1610620975), // AMOAND_W
12075 UINT64_C(1677729839), // AMOAND_W_AQ
12076 UINT64_C(1711284271), // AMOAND_W_AQ_RL
12077 UINT64_C(1644175407), // AMOAND_W_RL
12078 UINT64_C(671088687), // AMOCAS_B
12079 UINT64_C(738197551), // AMOCAS_B_AQ
12080 UINT64_C(771751983), // AMOCAS_B_AQ_RL
12081 UINT64_C(704643119), // AMOCAS_B_RL
12082 UINT64_C(671100975), // AMOCAS_D_RV32
12083 UINT64_C(738209839), // AMOCAS_D_RV32_AQ
12084 UINT64_C(771764271), // AMOCAS_D_RV32_AQ_RL
12085 UINT64_C(704655407), // AMOCAS_D_RV32_RL
12086 UINT64_C(671100975), // AMOCAS_D_RV64
12087 UINT64_C(738209839), // AMOCAS_D_RV64_AQ
12088 UINT64_C(771764271), // AMOCAS_D_RV64_AQ_RL
12089 UINT64_C(704655407), // AMOCAS_D_RV64_RL
12090 UINT64_C(671092783), // AMOCAS_H
12091 UINT64_C(738201647), // AMOCAS_H_AQ
12092 UINT64_C(771756079), // AMOCAS_H_AQ_RL
12093 UINT64_C(704647215), // AMOCAS_H_RL
12094 UINT64_C(671105071), // AMOCAS_Q
12095 UINT64_C(738213935), // AMOCAS_Q_AQ
12096 UINT64_C(771768367), // AMOCAS_Q_AQ_RL
12097 UINT64_C(704659503), // AMOCAS_Q_RL
12098 UINT64_C(671096879), // AMOCAS_W
12099 UINT64_C(738205743), // AMOCAS_W_AQ
12100 UINT64_C(771760175), // AMOCAS_W_AQ_RL
12101 UINT64_C(704651311), // AMOCAS_W_RL
12102 UINT64_C(3758096431), // AMOMAXU_B
12103 UINT64_C(3825205295), // AMOMAXU_B_AQ
12104 UINT64_C(3858759727), // AMOMAXU_B_AQ_RL
12105 UINT64_C(3791650863), // AMOMAXU_B_RL
12106 UINT64_C(3758108719), // AMOMAXU_D
12107 UINT64_C(3825217583), // AMOMAXU_D_AQ
12108 UINT64_C(3858772015), // AMOMAXU_D_AQ_RL
12109 UINT64_C(3791663151), // AMOMAXU_D_RL
12110 UINT64_C(3758100527), // AMOMAXU_H
12111 UINT64_C(3825209391), // AMOMAXU_H_AQ
12112 UINT64_C(3858763823), // AMOMAXU_H_AQ_RL
12113 UINT64_C(3791654959), // AMOMAXU_H_RL
12114 UINT64_C(3758104623), // AMOMAXU_W
12115 UINT64_C(3825213487), // AMOMAXU_W_AQ
12116 UINT64_C(3858767919), // AMOMAXU_W_AQ_RL
12117 UINT64_C(3791659055), // AMOMAXU_W_RL
12118 UINT64_C(2684354607), // AMOMAX_B
12119 UINT64_C(2751463471), // AMOMAX_B_AQ
12120 UINT64_C(2785017903), // AMOMAX_B_AQ_RL
12121 UINT64_C(2717909039), // AMOMAX_B_RL
12122 UINT64_C(2684366895), // AMOMAX_D
12123 UINT64_C(2751475759), // AMOMAX_D_AQ
12124 UINT64_C(2785030191), // AMOMAX_D_AQ_RL
12125 UINT64_C(2717921327), // AMOMAX_D_RL
12126 UINT64_C(2684358703), // AMOMAX_H
12127 UINT64_C(2751467567), // AMOMAX_H_AQ
12128 UINT64_C(2785021999), // AMOMAX_H_AQ_RL
12129 UINT64_C(2717913135), // AMOMAX_H_RL
12130 UINT64_C(2684362799), // AMOMAX_W
12131 UINT64_C(2751471663), // AMOMAX_W_AQ
12132 UINT64_C(2785026095), // AMOMAX_W_AQ_RL
12133 UINT64_C(2717917231), // AMOMAX_W_RL
12134 UINT64_C(3221225519), // AMOMINU_B
12135 UINT64_C(3288334383), // AMOMINU_B_AQ
12136 UINT64_C(3321888815), // AMOMINU_B_AQ_RL
12137 UINT64_C(3254779951), // AMOMINU_B_RL
12138 UINT64_C(3221237807), // AMOMINU_D
12139 UINT64_C(3288346671), // AMOMINU_D_AQ
12140 UINT64_C(3321901103), // AMOMINU_D_AQ_RL
12141 UINT64_C(3254792239), // AMOMINU_D_RL
12142 UINT64_C(3221229615), // AMOMINU_H
12143 UINT64_C(3288338479), // AMOMINU_H_AQ
12144 UINT64_C(3321892911), // AMOMINU_H_AQ_RL
12145 UINT64_C(3254784047), // AMOMINU_H_RL
12146 UINT64_C(3221233711), // AMOMINU_W
12147 UINT64_C(3288342575), // AMOMINU_W_AQ
12148 UINT64_C(3321897007), // AMOMINU_W_AQ_RL
12149 UINT64_C(3254788143), // AMOMINU_W_RL
12150 UINT64_C(2147483695), // AMOMIN_B
12151 UINT64_C(2214592559), // AMOMIN_B_AQ
12152 UINT64_C(2248146991), // AMOMIN_B_AQ_RL
12153 UINT64_C(2181038127), // AMOMIN_B_RL
12154 UINT64_C(2147495983), // AMOMIN_D
12155 UINT64_C(2214604847), // AMOMIN_D_AQ
12156 UINT64_C(2248159279), // AMOMIN_D_AQ_RL
12157 UINT64_C(2181050415), // AMOMIN_D_RL
12158 UINT64_C(2147487791), // AMOMIN_H
12159 UINT64_C(2214596655), // AMOMIN_H_AQ
12160 UINT64_C(2248151087), // AMOMIN_H_AQ_RL
12161 UINT64_C(2181042223), // AMOMIN_H_RL
12162 UINT64_C(2147491887), // AMOMIN_W
12163 UINT64_C(2214600751), // AMOMIN_W_AQ
12164 UINT64_C(2248155183), // AMOMIN_W_AQ_RL
12165 UINT64_C(2181046319), // AMOMIN_W_RL
12166 UINT64_C(1073741871), // AMOOR_B
12167 UINT64_C(1140850735), // AMOOR_B_AQ
12168 UINT64_C(1174405167), // AMOOR_B_AQ_RL
12169 UINT64_C(1107296303), // AMOOR_B_RL
12170 UINT64_C(1073754159), // AMOOR_D
12171 UINT64_C(1140863023), // AMOOR_D_AQ
12172 UINT64_C(1174417455), // AMOOR_D_AQ_RL
12173 UINT64_C(1107308591), // AMOOR_D_RL
12174 UINT64_C(1073745967), // AMOOR_H
12175 UINT64_C(1140854831), // AMOOR_H_AQ
12176 UINT64_C(1174409263), // AMOOR_H_AQ_RL
12177 UINT64_C(1107300399), // AMOOR_H_RL
12178 UINT64_C(1073750063), // AMOOR_W
12179 UINT64_C(1140858927), // AMOOR_W_AQ
12180 UINT64_C(1174413359), // AMOOR_W_AQ_RL
12181 UINT64_C(1107304495), // AMOOR_W_RL
12182 UINT64_C(134217775), // AMOSWAP_B
12183 UINT64_C(201326639), // AMOSWAP_B_AQ
12184 UINT64_C(234881071), // AMOSWAP_B_AQ_RL
12185 UINT64_C(167772207), // AMOSWAP_B_RL
12186 UINT64_C(134230063), // AMOSWAP_D
12187 UINT64_C(201338927), // AMOSWAP_D_AQ
12188 UINT64_C(234893359), // AMOSWAP_D_AQ_RL
12189 UINT64_C(167784495), // AMOSWAP_D_RL
12190 UINT64_C(134221871), // AMOSWAP_H
12191 UINT64_C(201330735), // AMOSWAP_H_AQ
12192 UINT64_C(234885167), // AMOSWAP_H_AQ_RL
12193 UINT64_C(167776303), // AMOSWAP_H_RL
12194 UINT64_C(134225967), // AMOSWAP_W
12195 UINT64_C(201334831), // AMOSWAP_W_AQ
12196 UINT64_C(234889263), // AMOSWAP_W_AQ_RL
12197 UINT64_C(167780399), // AMOSWAP_W_RL
12198 UINT64_C(536870959), // AMOXOR_B
12199 UINT64_C(603979823), // AMOXOR_B_AQ
12200 UINT64_C(637534255), // AMOXOR_B_AQ_RL
12201 UINT64_C(570425391), // AMOXOR_B_RL
12202 UINT64_C(536883247), // AMOXOR_D
12203 UINT64_C(603992111), // AMOXOR_D_AQ
12204 UINT64_C(637546543), // AMOXOR_D_AQ_RL
12205 UINT64_C(570437679), // AMOXOR_D_RL
12206 UINT64_C(536875055), // AMOXOR_H
12207 UINT64_C(603983919), // AMOXOR_H_AQ
12208 UINT64_C(637538351), // AMOXOR_H_AQ_RL
12209 UINT64_C(570429487), // AMOXOR_H_RL
12210 UINT64_C(536879151), // AMOXOR_W
12211 UINT64_C(603988015), // AMOXOR_W_AQ
12212 UINT64_C(637542447), // AMOXOR_W_AQ_RL
12213 UINT64_C(570433583), // AMOXOR_W_RL
12214 UINT64_C(28723), // AND
12215 UINT64_C(28691), // ANDI
12216 UINT64_C(1073770547), // ANDN
12217 UINT64_C(23), // AUIPC
12218 UINT64_C(1207963699), // BCLR
12219 UINT64_C(1207963667), // BCLRI
12220 UINT64_C(99), // BEQ
12221 UINT64_C(1207980083), // BEXT
12222 UINT64_C(1207980051), // BEXTI
12223 UINT64_C(20579), // BGE
12224 UINT64_C(28771), // BGEU
12225 UINT64_C(1744834611), // BINV
12226 UINT64_C(1744834579), // BINVI
12227 UINT64_C(16483), // BLT
12228 UINT64_C(24675), // BLTU
12229 UINT64_C(4195), // BNE
12230 UINT64_C(1752190995), // BREV8
12231 UINT64_C(671092787), // BSET
12232 UINT64_C(671092755), // BSETI
12233 UINT64_C(1056783), // CBO_CLEAN
12234 UINT64_C(2105359), // CBO_FLUSH
12235 UINT64_C(8207), // CBO_INVAL
12236 UINT64_C(4202511), // CBO_ZERO
12237 UINT64_C(167776307), // CLMUL
12238 UINT64_C(167784499), // CLMULH
12239 UINT64_C(167780403), // CLMULR
12240 UINT64_C(1613762579), // CLS
12241 UINT64_C(1613762587), // CLSW
12242 UINT64_C(1610616851), // CLZ
12243 UINT64_C(1610616859), // CLZW
12244 UINT64_C(40962), // CM_JALT
12245 UINT64_C(40962), // CM_JT
12246 UINT64_C(44130), // CM_MVA01S
12247 UINT64_C(44066), // CM_MVSA01
12248 UINT64_C(47618), // CM_POP
12249 UINT64_C(48642), // CM_POPRET
12250 UINT64_C(48130), // CM_POPRETZ
12251 UINT64_C(47106), // CM_PUSH
12252 UINT64_C(1612714003), // CPOP
12253 UINT64_C(1612714011), // CPOPW
12254 UINT64_C(12403), // CSRRC
12255 UINT64_C(28787), // CSRRCI
12256 UINT64_C(8307), // CSRRS
12257 UINT64_C(24691), // CSRRSI
12258 UINT64_C(4211), // CSRRW
12259 UINT64_C(20595), // CSRRWI
12260 UINT64_C(1611665427), // CTZ
12261 UINT64_C(1611665435), // CTZW
12262 UINT64_C(1342189611), // CV_ABS
12263 UINT64_C(1879052411), // CV_ABS_B
12264 UINT64_C(1879048315), // CV_ABS_H
12265 UINT64_C(8283), // CV_ADDN
12266 UINT64_C(2147495979), // CV_ADDNR
12267 UINT64_C(2147491931), // CV_ADDRN
12268 UINT64_C(2214604843), // CV_ADDRNR
12269 UINT64_C(1073750107), // CV_ADDUN
12270 UINT64_C(2181050411), // CV_ADDUNR
12271 UINT64_C(3221233755), // CV_ADDURN
12272 UINT64_C(2248159275), // CV_ADDURNR
12273 UINT64_C(4219), // CV_ADD_B
12274 UINT64_C(1811947643), // CV_ADD_DIV2
12275 UINT64_C(1811955835), // CV_ADD_DIV4
12276 UINT64_C(1811964027), // CV_ADD_DIV8
12277 UINT64_C(123), // CV_ADD_H
12278 UINT64_C(28795), // CV_ADD_SCI_B
12279 UINT64_C(24699), // CV_ADD_SCI_H
12280 UINT64_C(20603), // CV_ADD_SC_B
12281 UINT64_C(16507), // CV_ADD_SC_H
12282 UINT64_C(1744834683), // CV_AND_B
12283 UINT64_C(1744830587), // CV_AND_H
12284 UINT64_C(1744859259), // CV_AND_SCI_B
12285 UINT64_C(1744855163), // CV_AND_SCI_H
12286 UINT64_C(1744851067), // CV_AND_SC_B
12287 UINT64_C(1744846971), // CV_AND_SC_H
12288 UINT64_C(402657403), // CV_AVGU_B
12289 UINT64_C(402653307), // CV_AVGU_H
12290 UINT64_C(402681979), // CV_AVGU_SCI_B
12291 UINT64_C(402677883), // CV_AVGU_SCI_H
12292 UINT64_C(402673787), // CV_AVGU_SC_B
12293 UINT64_C(402669691), // CV_AVGU_SC_H
12294 UINT64_C(268439675), // CV_AVG_B
12295 UINT64_C(268435579), // CV_AVG_H
12296 UINT64_C(268464251), // CV_AVG_SCI_B
12297 UINT64_C(268460155), // CV_AVG_SCI_H
12298 UINT64_C(268456059), // CV_AVG_SC_B
12299 UINT64_C(268451963), // CV_AVG_SC_H
12300 UINT64_C(4187), // CV_BCLR
12301 UINT64_C(939536427), // CV_BCLRR
12302 UINT64_C(24587), // CV_BEQIMM
12303 UINT64_C(3221229659), // CV_BITREV
12304 UINT64_C(28683), // CV_BNEIMM
12305 UINT64_C(1073746011), // CV_BSET
12306 UINT64_C(973090859), // CV_BSETR
12307 UINT64_C(1174417451), // CV_CLB
12308 UINT64_C(1879060523), // CV_CLIP
12309 UINT64_C(1946169387), // CV_CLIPR
12310 UINT64_C(1912614955), // CV_CLIPU
12311 UINT64_C(1979723819), // CV_CLIPUR
12312 UINT64_C(67113083), // CV_CMPEQ_B
12313 UINT64_C(67108987), // CV_CMPEQ_H
12314 UINT64_C(67137659), // CV_CMPEQ_SCI_B
12315 UINT64_C(67133563), // CV_CMPEQ_SCI_H
12316 UINT64_C(67129467), // CV_CMPEQ_SC_B
12317 UINT64_C(67125371), // CV_CMPEQ_SC_H
12318 UINT64_C(1006637179), // CV_CMPGEU_B
12319 UINT64_C(1006633083), // CV_CMPGEU_H
12320 UINT64_C(1006661755), // CV_CMPGEU_SCI_B
12321 UINT64_C(1006657659), // CV_CMPGEU_SCI_H
12322 UINT64_C(1006653563), // CV_CMPGEU_SC_B
12323 UINT64_C(1006649467), // CV_CMPGEU_SC_H
12324 UINT64_C(469766267), // CV_CMPGE_B
12325 UINT64_C(469762171), // CV_CMPGE_H
12326 UINT64_C(469790843), // CV_CMPGE_SCI_B
12327 UINT64_C(469786747), // CV_CMPGE_SCI_H
12328 UINT64_C(469782651), // CV_CMPGE_SC_B
12329 UINT64_C(469778555), // CV_CMPGE_SC_H
12330 UINT64_C(872419451), // CV_CMPGTU_B
12331 UINT64_C(872415355), // CV_CMPGTU_H
12332 UINT64_C(872444027), // CV_CMPGTU_SCI_B
12333 UINT64_C(872439931), // CV_CMPGTU_SCI_H
12334 UINT64_C(872435835), // CV_CMPGTU_SC_B
12335 UINT64_C(872431739), // CV_CMPGTU_SC_H
12336 UINT64_C(335548539), // CV_CMPGT_B
12337 UINT64_C(335544443), // CV_CMPGT_H
12338 UINT64_C(335573115), // CV_CMPGT_SCI_B
12339 UINT64_C(335569019), // CV_CMPGT_SCI_H
12340 UINT64_C(335564923), // CV_CMPGT_SC_B
12341 UINT64_C(335560827), // CV_CMPGT_SC_H
12342 UINT64_C(1275072635), // CV_CMPLEU_B
12343 UINT64_C(1275068539), // CV_CMPLEU_H
12344 UINT64_C(1275097211), // CV_CMPLEU_SCI_B
12345 UINT64_C(1275093115), // CV_CMPLEU_SCI_H
12346 UINT64_C(1275089019), // CV_CMPLEU_SC_B
12347 UINT64_C(1275084923), // CV_CMPLEU_SC_H
12348 UINT64_C(738201723), // CV_CMPLE_B
12349 UINT64_C(738197627), // CV_CMPLE_H
12350 UINT64_C(738226299), // CV_CMPLE_SCI_B
12351 UINT64_C(738222203), // CV_CMPLE_SCI_H
12352 UINT64_C(738218107), // CV_CMPLE_SC_B
12353 UINT64_C(738214011), // CV_CMPLE_SC_H
12354 UINT64_C(1140854907), // CV_CMPLTU_B
12355 UINT64_C(1140850811), // CV_CMPLTU_H
12356 UINT64_C(1140879483), // CV_CMPLTU_SCI_B
12357 UINT64_C(1140875387), // CV_CMPLTU_SCI_H
12358 UINT64_C(1140871291), // CV_CMPLTU_SC_B
12359 UINT64_C(1140867195), // CV_CMPLTU_SC_H
12360 UINT64_C(603983995), // CV_CMPLT_B
12361 UINT64_C(603979899), // CV_CMPLT_H
12362 UINT64_C(604008571), // CV_CMPLT_SCI_B
12363 UINT64_C(604004475), // CV_CMPLT_SCI_H
12364 UINT64_C(604000379), // CV_CMPLT_SC_B
12365 UINT64_C(603996283), // CV_CMPLT_SC_H
12366 UINT64_C(201330811), // CV_CMPNE_B
12367 UINT64_C(201326715), // CV_CMPNE_H
12368 UINT64_C(201355387), // CV_CMPNE_SCI_B
12369 UINT64_C(201351291), // CV_CMPNE_SCI_H
12370 UINT64_C(201347195), // CV_CMPNE_SC_B
12371 UINT64_C(201343099), // CV_CMPNE_SC_H
12372 UINT64_C(1207971883), // CV_CNT
12373 UINT64_C(1543503995), // CV_CPLXCONJ
12374 UINT64_C(1442840699), // CV_CPLXMUL_I
12375 UINT64_C(1442848891), // CV_CPLXMUL_I_DIV2
12376 UINT64_C(1442857083), // CV_CPLXMUL_I_DIV4
12377 UINT64_C(1442865275), // CV_CPLXMUL_I_DIV8
12378 UINT64_C(1409286267), // CV_CPLXMUL_R
12379 UINT64_C(1409294459), // CV_CPLXMUL_R_DIV2
12380 UINT64_C(1409302651), // CV_CPLXMUL_R_DIV4
12381 UINT64_C(1409310843), // CV_CPLXMUL_R_DIV8
12382 UINT64_C(2415923323), // CV_DOTSP_B
12383 UINT64_C(2415919227), // CV_DOTSP_H
12384 UINT64_C(2415947899), // CV_DOTSP_SCI_B
12385 UINT64_C(2415943803), // CV_DOTSP_SCI_H
12386 UINT64_C(2415939707), // CV_DOTSP_SC_B
12387 UINT64_C(2415935611), // CV_DOTSP_SC_H
12388 UINT64_C(2147487867), // CV_DOTUP_B
12389 UINT64_C(2147483771), // CV_DOTUP_H
12390 UINT64_C(2147512443), // CV_DOTUP_SCI_B
12391 UINT64_C(2147508347), // CV_DOTUP_SCI_H
12392 UINT64_C(2147504251), // CV_DOTUP_SC_B
12393 UINT64_C(2147500155), // CV_DOTUP_SC_H
12394 UINT64_C(2281705595), // CV_DOTUSP_B
12395 UINT64_C(2281701499), // CV_DOTUSP_H
12396 UINT64_C(2281730171), // CV_DOTUSP_SCI_B
12397 UINT64_C(2281726075), // CV_DOTUSP_SCI_H
12398 UINT64_C(2281721979), // CV_DOTUSP_SC_B
12399 UINT64_C(2281717883), // CV_DOTUSP_SC_H
12400 UINT64_C(12299), // CV_ELW
12401 UINT64_C(1677733931), // CV_EXTBS
12402 UINT64_C(1711288363), // CV_EXTBZ
12403 UINT64_C(1610625067), // CV_EXTHS
12404 UINT64_C(1644179499), // CV_EXTHZ
12405 UINT64_C(91), // CV_EXTRACT
12406 UINT64_C(805318699), // CV_EXTRACTR
12407 UINT64_C(1073741915), // CV_EXTRACTU
12408 UINT64_C(838873131), // CV_EXTRACTUR
12409 UINT64_C(3087020155), // CV_EXTRACTU_B
12410 UINT64_C(3087016059), // CV_EXTRACTU_H
12411 UINT64_C(3087011963), // CV_EXTRACT_B
12412 UINT64_C(3087007867), // CV_EXTRACT_H
12413 UINT64_C(1107308587), // CV_FF1
12414 UINT64_C(1140863019), // CV_FL1
12415 UINT64_C(2147483739), // CV_INSERT
12416 UINT64_C(872427563), // CV_INSERTR
12417 UINT64_C(3087028347), // CV_INSERT_B
12418 UINT64_C(3087024251), // CV_INSERT_H
12419 UINT64_C(16395), // CV_LBU_ri_inc
12420 UINT64_C(402665515), // CV_LBU_rr
12421 UINT64_C(268447787), // CV_LBU_rr_inc
12422 UINT64_C(11), // CV_LB_ri_inc
12423 UINT64_C(134230059), // CV_LB_rr
12424 UINT64_C(12331), // CV_LB_rr_inc
12425 UINT64_C(20491), // CV_LHU_ri_inc
12426 UINT64_C(436219947), // CV_LHU_rr
12427 UINT64_C(302002219), // CV_LHU_rr_inc
12428 UINT64_C(4107), // CV_LH_ri_inc
12429 UINT64_C(167784491), // CV_LH_rr
12430 UINT64_C(33566763), // CV_LH_rr_inc
12431 UINT64_C(8203), // CV_LW_ri_inc
12432 UINT64_C(201338923), // CV_LW_rr
12433 UINT64_C(67121195), // CV_LW_rr_inc
12434 UINT64_C(2415931435), // CV_MAC
12435 UINT64_C(1073766491), // CV_MACHHSN
12436 UINT64_C(3221250139), // CV_MACHHSRN
12437 UINT64_C(1073770587), // CV_MACHHUN
12438 UINT64_C(3221254235), // CV_MACHHURN
12439 UINT64_C(24667), // CV_MACSN
12440 UINT64_C(2147508315), // CV_MACSRN
12441 UINT64_C(28763), // CV_MACUN
12442 UINT64_C(2147512411), // CV_MACURN
12443 UINT64_C(1509961771), // CV_MAX
12444 UINT64_C(1543516203), // CV_MAXU
12445 UINT64_C(939528315), // CV_MAXU_B
12446 UINT64_C(939524219), // CV_MAXU_H
12447 UINT64_C(939552891), // CV_MAXU_SCI_B
12448 UINT64_C(939548795), // CV_MAXU_SCI_H
12449 UINT64_C(939544699), // CV_MAXU_SC_B
12450 UINT64_C(939540603), // CV_MAXU_SC_H
12451 UINT64_C(805310587), // CV_MAX_B
12452 UINT64_C(805306491), // CV_MAX_H
12453 UINT64_C(805335163), // CV_MAX_SCI_B
12454 UINT64_C(805331067), // CV_MAX_SCI_H
12455 UINT64_C(805326971), // CV_MAX_SC_B
12456 UINT64_C(805322875), // CV_MAX_SC_H
12457 UINT64_C(1442852907), // CV_MIN
12458 UINT64_C(1476407339), // CV_MINU
12459 UINT64_C(671092859), // CV_MINU_B
12460 UINT64_C(671088763), // CV_MINU_H
12461 UINT64_C(671117435), // CV_MINU_SCI_B
12462 UINT64_C(671113339), // CV_MINU_SCI_H
12463 UINT64_C(671109243), // CV_MINU_SC_B
12464 UINT64_C(671105147), // CV_MINU_SC_H
12465 UINT64_C(536875131), // CV_MIN_B
12466 UINT64_C(536871035), // CV_MIN_H
12467 UINT64_C(536899707), // CV_MIN_SCI_B
12468 UINT64_C(536895611), // CV_MIN_SCI_H
12469 UINT64_C(536891515), // CV_MIN_SC_B
12470 UINT64_C(536887419), // CV_MIN_SC_H
12471 UINT64_C(2449485867), // CV_MSU
12472 UINT64_C(1073758299), // CV_MULHHSN
12473 UINT64_C(3221241947), // CV_MULHHSRN
12474 UINT64_C(1073762395), // CV_MULHHUN
12475 UINT64_C(3221246043), // CV_MULHHURN
12476 UINT64_C(16475), // CV_MULSN
12477 UINT64_C(2147500123), // CV_MULSRN
12478 UINT64_C(20571), // CV_MULUN
12479 UINT64_C(2147504219), // CV_MULURN
12480 UINT64_C(1476399227), // CV_OR_B
12481 UINT64_C(1476395131), // CV_OR_H
12482 UINT64_C(1476423803), // CV_OR_SCI_B
12483 UINT64_C(1476419707), // CV_OR_SCI_H
12484 UINT64_C(1476415611), // CV_OR_SC_B
12485 UINT64_C(1476411515), // CV_OR_SC_H
12486 UINT64_C(4026531963), // CV_PACK
12487 UINT64_C(4194308219), // CV_PACKHI_B
12488 UINT64_C(4160753787), // CV_PACKLO_B
12489 UINT64_C(4060086395), // CV_PACK_H
12490 UINT64_C(1073754155), // CV_ROR
12491 UINT64_C(43), // CV_SB_ri_inc
12492 UINT64_C(671100971), // CV_SB_rr
12493 UINT64_C(536883243), // CV_SB_rr_inc
12494 UINT64_C(2818576507), // CV_SDOTSP_B
12495 UINT64_C(2818572411), // CV_SDOTSP_H
12496 UINT64_C(2818601083), // CV_SDOTSP_SCI_B
12497 UINT64_C(2818596987), // CV_SDOTSP_SCI_H
12498 UINT64_C(2818592891), // CV_SDOTSP_SC_B
12499 UINT64_C(2818588795), // CV_SDOTSP_SC_H
12500 UINT64_C(2550141051), // CV_SDOTUP_B
12501 UINT64_C(2550136955), // CV_SDOTUP_H
12502 UINT64_C(2550165627), // CV_SDOTUP_SCI_B
12503 UINT64_C(2550161531), // CV_SDOTUP_SCI_H
12504 UINT64_C(2550157435), // CV_SDOTUP_SC_B
12505 UINT64_C(2550153339), // CV_SDOTUP_SC_H
12506 UINT64_C(2684358779), // CV_SDOTUSP_B
12507 UINT64_C(2684354683), // CV_SDOTUSP_H
12508 UINT64_C(2684383355), // CV_SDOTUSP_SCI_B
12509 UINT64_C(2684379259), // CV_SDOTUSP_SCI_H
12510 UINT64_C(2684375163), // CV_SDOTUSP_SC_B
12511 UINT64_C(2684371067), // CV_SDOTUSP_SC_H
12512 UINT64_C(3758100603), // CV_SHUFFLE2_B
12513 UINT64_C(3758096507), // CV_SHUFFLE2_H
12514 UINT64_C(3221254267), // CV_SHUFFLEI0_SCI_B
12515 UINT64_C(3355471995), // CV_SHUFFLEI1_SCI_B
12516 UINT64_C(3489689723), // CV_SHUFFLEI2_SCI_B
12517 UINT64_C(3623907451), // CV_SHUFFLEI3_SCI_B
12518 UINT64_C(3221229691), // CV_SHUFFLE_B
12519 UINT64_C(3221225595), // CV_SHUFFLE_H
12520 UINT64_C(3221250171), // CV_SHUFFLE_SCI_H
12521 UINT64_C(4139), // CV_SH_ri_inc
12522 UINT64_C(704655403), // CV_SH_rr
12523 UINT64_C(570437675), // CV_SH_rr_inc
12524 UINT64_C(1375744043), // CV_SLE
12525 UINT64_C(1409298475), // CV_SLEU
12526 UINT64_C(1342181499), // CV_SLL_B
12527 UINT64_C(1342177403), // CV_SLL_H
12528 UINT64_C(1342206075), // CV_SLL_SCI_B
12529 UINT64_C(1342201979), // CV_SLL_SCI_H
12530 UINT64_C(1342197883), // CV_SLL_SC_B
12531 UINT64_C(1342193787), // CV_SLL_SC_H
12532 UINT64_C(1207963771), // CV_SRA_B
12533 UINT64_C(1207959675), // CV_SRA_H
12534 UINT64_C(1207988347), // CV_SRA_SCI_B
12535 UINT64_C(1207984251), // CV_SRA_SCI_H
12536 UINT64_C(1207980155), // CV_SRA_SC_B
12537 UINT64_C(1207976059), // CV_SRA_SC_H
12538 UINT64_C(1073746043), // CV_SRL_B
12539 UINT64_C(1073741947), // CV_SRL_H
12540 UINT64_C(1073770619), // CV_SRL_SCI_B
12541 UINT64_C(1073766523), // CV_SRL_SCI_H
12542 UINT64_C(1073762427), // CV_SRL_SC_B
12543 UINT64_C(1073758331), // CV_SRL_SC_H
12544 UINT64_C(12379), // CV_SUBN
12545 UINT64_C(2281713707), // CV_SUBNR
12546 UINT64_C(2147496027), // CV_SUBRN
12547 UINT64_C(2348822571), // CV_SUBRNR
12548 UINT64_C(1677721723), // CV_SUBROTMJ
12549 UINT64_C(1677729915), // CV_SUBROTMJ_DIV2
12550 UINT64_C(1677738107), // CV_SUBROTMJ_DIV4
12551 UINT64_C(1677746299), // CV_SUBROTMJ_DIV8
12552 UINT64_C(1073754203), // CV_SUBUN
12553 UINT64_C(2315268139), // CV_SUBUNR
12554 UINT64_C(3221237851), // CV_SUBURN
12555 UINT64_C(2382377003), // CV_SUBURNR
12556 UINT64_C(134221947), // CV_SUB_B
12557 UINT64_C(1946165371), // CV_SUB_DIV2
12558 UINT64_C(1946173563), // CV_SUB_DIV4
12559 UINT64_C(1946181755), // CV_SUB_DIV8
12560 UINT64_C(134217851), // CV_SUB_H
12561 UINT64_C(134246523), // CV_SUB_SCI_B
12562 UINT64_C(134242427), // CV_SUB_SCI_H
12563 UINT64_C(134238331), // CV_SUB_SC_B
12564 UINT64_C(134234235), // CV_SUB_SC_H
12565 UINT64_C(8235), // CV_SW_ri_inc
12566 UINT64_C(738209835), // CV_SW_rr
12567 UINT64_C(603992107), // CV_SW_rr_inc
12568 UINT64_C(1610616955), // CV_XOR_B
12569 UINT64_C(1610612859), // CV_XOR_H
12570 UINT64_C(1610641531), // CV_XOR_SCI_B
12571 UINT64_C(1610637435), // CV_XOR_SCI_H
12572 UINT64_C(1610633339), // CV_XOR_SC_B
12573 UINT64_C(1610629243), // CV_XOR_SC_H
12574 UINT64_C(234901555), // CZERO_EQZ
12575 UINT64_C(234909747), // CZERO_NEZ
12576 UINT64_C(36866), // C_ADD
12577 UINT64_C(1), // C_ADDI
12578 UINT64_C(24833), // C_ADDI16SP
12579 UINT64_C(0), // C_ADDI4SPN
12580 UINT64_C(8193), // C_ADDIW
12581 UINT64_C(1), // C_ADDI_HINT_IMM_ZERO
12582 UINT64_C(39969), // C_ADDW
12583 UINT64_C(36866), // C_ADD_HINT
12584 UINT64_C(35937), // C_AND
12585 UINT64_C(34817), // C_ANDI
12586 UINT64_C(49153), // C_BEQZ
12587 UINT64_C(57345), // C_BNEZ
12588 UINT64_C(36866), // C_EBREAK
12589 UINT64_C(8192), // C_FLD
12590 UINT64_C(8194), // C_FLDSP
12591 UINT64_C(24576), // C_FLW
12592 UINT64_C(24578), // C_FLWSP
12593 UINT64_C(40960), // C_FSD
12594 UINT64_C(40962), // C_FSDSP
12595 UINT64_C(57344), // C_FSW
12596 UINT64_C(57346), // C_FSWSP
12597 UINT64_C(40961), // C_J
12598 UINT64_C(8193), // C_JAL
12599 UINT64_C(36866), // C_JALR
12600 UINT64_C(32770), // C_JR
12601 UINT64_C(32768), // C_LBU
12602 UINT64_C(24576), // C_LD
12603 UINT64_C(24578), // C_LDSP
12604 UINT64_C(24578), // C_LDSP_RV32
12605 UINT64_C(24576), // C_LD_RV32
12606 UINT64_C(33856), // C_LH
12607 UINT64_C(33792), // C_LHU
12608 UINT64_C(33856), // C_LH_INX
12609 UINT64_C(16385), // C_LI
12610 UINT64_C(16385), // C_LI_HINT
12611 UINT64_C(24577), // C_LUI
12612 UINT64_C(24577), // C_LUI_HINT
12613 UINT64_C(16384), // C_LW
12614 UINT64_C(16386), // C_LWSP
12615 UINT64_C(16386), // C_LWSP_INX
12616 UINT64_C(16384), // C_LW_INX
12617 UINT64_C(24705), // C_MOP1
12618 UINT64_C(25985), // C_MOP11
12619 UINT64_C(26241), // C_MOP13
12620 UINT64_C(26497), // C_MOP15
12621 UINT64_C(24961), // C_MOP3
12622 UINT64_C(25217), // C_MOP5
12623 UINT64_C(25473), // C_MOP7
12624 UINT64_C(25729), // C_MOP9
12625 UINT64_C(40001), // C_MUL
12626 UINT64_C(32770), // C_MV
12627 UINT64_C(32770), // C_MV_HINT
12628 UINT64_C(1), // C_NOP
12629 UINT64_C(1), // C_NOP_HINT
12630 UINT64_C(40053), // C_NOT
12631 UINT64_C(35905), // C_OR
12632 UINT64_C(34816), // C_SB
12633 UINT64_C(57344), // C_SD
12634 UINT64_C(57346), // C_SDSP
12635 UINT64_C(57346), // C_SDSP_RV32
12636 UINT64_C(57344), // C_SD_RV32
12637 UINT64_C(40037), // C_SEXT_B
12638 UINT64_C(40045), // C_SEXT_H
12639 UINT64_C(35840), // C_SH
12640 UINT64_C(35840), // C_SH_INX
12641 UINT64_C(2), // C_SLLI
12642 UINT64_C(2), // C_SLLI64_HINT
12643 UINT64_C(2), // C_SLLI_HINT
12644 UINT64_C(33793), // C_SRAI
12645 UINT64_C(33793), // C_SRAI64_HINT
12646 UINT64_C(32769), // C_SRLI
12647 UINT64_C(32769), // C_SRLI64_HINT
12648 UINT64_C(25217), // C_SSPOPCHK
12649 UINT64_C(24705), // C_SSPUSH
12650 UINT64_C(35841), // C_SUB
12651 UINT64_C(39937), // C_SUBW
12652 UINT64_C(49152), // C_SW
12653 UINT64_C(49154), // C_SWSP
12654 UINT64_C(49154), // C_SWSP_INX
12655 UINT64_C(49152), // C_SW_INX
12656 UINT64_C(0), // C_UNIMP
12657 UINT64_C(35873), // C_XOR
12658 UINT64_C(40033), // C_ZEXT_B
12659 UINT64_C(40041), // C_ZEXT_H
12660 UINT64_C(40049), // C_ZEXT_W
12661 UINT64_C(33570867), // DIV
12662 UINT64_C(33574963), // DIVU
12663 UINT64_C(33574971), // DIVUW
12664 UINT64_C(33570875), // DIVW
12665 UINT64_C(2065694835), // DRET
12666 UINT64_C(1048691), // EBREAK
12667 UINT64_C(115), // ECALL
12668 UINT64_C(33554515), // FADD_D
12669 UINT64_C(33554515), // FADD_D_IN32X
12670 UINT64_C(33554515), // FADD_D_INX
12671 UINT64_C(67108947), // FADD_H
12672 UINT64_C(67108947), // FADD_H_INX
12673 UINT64_C(100663379), // FADD_Q
12674 UINT64_C(83), // FADD_S
12675 UINT64_C(83), // FADD_S_INX
12676 UINT64_C(3791654995), // FCLASS_D
12677 UINT64_C(3791654995), // FCLASS_D_IN32X
12678 UINT64_C(3791654995), // FCLASS_D_INX
12679 UINT64_C(3825209427), // FCLASS_H
12680 UINT64_C(3825209427), // FCLASS_H_INX
12681 UINT64_C(3858763859), // FCLASS_Q
12682 UINT64_C(3758100563), // FCLASS_S
12683 UINT64_C(3758100563), // FCLASS_S_INX
12684 UINT64_C(3263168595), // FCVTMOD_W_D
12685 UINT64_C(1149239379), // FCVT_BF16_S
12686 UINT64_C(1109393491), // FCVT_D_H
12687 UINT64_C(1109393491), // FCVT_D_H_IN32X
12688 UINT64_C(1109393491), // FCVT_D_H_INX
12689 UINT64_C(3525312595), // FCVT_D_L
12690 UINT64_C(3526361171), // FCVT_D_LU
12691 UINT64_C(3526361171), // FCVT_D_LU_INX
12692 UINT64_C(3525312595), // FCVT_D_L_INX
12693 UINT64_C(1110442067), // FCVT_D_Q
12694 UINT64_C(1107296339), // FCVT_D_S
12695 UINT64_C(1107296339), // FCVT_D_S_IN32X
12696 UINT64_C(1107296339), // FCVT_D_S_INX
12697 UINT64_C(3523215443), // FCVT_D_W
12698 UINT64_C(3524264019), // FCVT_D_WU
12699 UINT64_C(3524264019), // FCVT_D_WU_IN32X
12700 UINT64_C(3524264019), // FCVT_D_WU_INX
12701 UINT64_C(3523215443), // FCVT_D_W_IN32X
12702 UINT64_C(3523215443), // FCVT_D_W_INX
12703 UINT64_C(1141899347), // FCVT_H_D
12704 UINT64_C(1141899347), // FCVT_H_D_IN32X
12705 UINT64_C(1141899347), // FCVT_H_D_INX
12706 UINT64_C(3558867027), // FCVT_H_L
12707 UINT64_C(3559915603), // FCVT_H_LU
12708 UINT64_C(3559915603), // FCVT_H_LU_INX
12709 UINT64_C(3558867027), // FCVT_H_L_INX
12710 UINT64_C(1140850771), // FCVT_H_S
12711 UINT64_C(1140850771), // FCVT_H_S_INX
12712 UINT64_C(3556769875), // FCVT_H_W
12713 UINT64_C(3557818451), // FCVT_H_WU
12714 UINT64_C(3557818451), // FCVT_H_WU_INX
12715 UINT64_C(3556769875), // FCVT_H_W_INX
12716 UINT64_C(3257925715), // FCVT_LU_D
12717 UINT64_C(3257925715), // FCVT_LU_D_INX
12718 UINT64_C(3291480147), // FCVT_LU_H
12719 UINT64_C(3291480147), // FCVT_LU_H_INX
12720 UINT64_C(3325034579), // FCVT_LU_Q
12721 UINT64_C(3224371283), // FCVT_LU_S
12722 UINT64_C(3224371283), // FCVT_LU_S_INX
12723 UINT64_C(3256877139), // FCVT_L_D
12724 UINT64_C(3256877139), // FCVT_L_D_INX
12725 UINT64_C(3290431571), // FCVT_L_H
12726 UINT64_C(3290431571), // FCVT_L_H_INX
12727 UINT64_C(3323986003), // FCVT_L_Q
12728 UINT64_C(3223322707), // FCVT_L_S
12729 UINT64_C(3223322707), // FCVT_L_S_INX
12730 UINT64_C(1175453779), // FCVT_Q_D
12731 UINT64_C(3592421459), // FCVT_Q_L
12732 UINT64_C(3593470035), // FCVT_Q_LU
12733 UINT64_C(1174405203), // FCVT_Q_S
12734 UINT64_C(3590324307), // FCVT_Q_W
12735 UINT64_C(3591372883), // FCVT_Q_WU
12736 UINT64_C(1080033363), // FCVT_S_BF16
12737 UINT64_C(1074790483), // FCVT_S_D
12738 UINT64_C(1074790483), // FCVT_S_D_IN32X
12739 UINT64_C(1074790483), // FCVT_S_D_INX
12740 UINT64_C(1075839059), // FCVT_S_H
12741 UINT64_C(1075839059), // FCVT_S_H_INX
12742 UINT64_C(3491758163), // FCVT_S_L
12743 UINT64_C(3492806739), // FCVT_S_LU
12744 UINT64_C(3492806739), // FCVT_S_LU_INX
12745 UINT64_C(3491758163), // FCVT_S_L_INX
12746 UINT64_C(1076887635), // FCVT_S_Q
12747 UINT64_C(3489661011), // FCVT_S_W
12748 UINT64_C(3490709587), // FCVT_S_WU
12749 UINT64_C(3490709587), // FCVT_S_WU_INX
12750 UINT64_C(3489661011), // FCVT_S_W_INX
12751 UINT64_C(3255828563), // FCVT_WU_D
12752 UINT64_C(3255828563), // FCVT_WU_D_IN32X
12753 UINT64_C(3255828563), // FCVT_WU_D_INX
12754 UINT64_C(3289382995), // FCVT_WU_H
12755 UINT64_C(3289382995), // FCVT_WU_H_INX
12756 UINT64_C(3322937427), // FCVT_WU_Q
12757 UINT64_C(3222274131), // FCVT_WU_S
12758 UINT64_C(3222274131), // FCVT_WU_S_INX
12759 UINT64_C(3254779987), // FCVT_W_D
12760 UINT64_C(3254779987), // FCVT_W_D_IN32X
12761 UINT64_C(3254779987), // FCVT_W_D_INX
12762 UINT64_C(3288334419), // FCVT_W_H
12763 UINT64_C(3288334419), // FCVT_W_H_INX
12764 UINT64_C(3321888851), // FCVT_W_Q
12765 UINT64_C(3221225555), // FCVT_W_S
12766 UINT64_C(3221225555), // FCVT_W_S_INX
12767 UINT64_C(436207699), // FDIV_D
12768 UINT64_C(436207699), // FDIV_D_IN32X
12769 UINT64_C(436207699), // FDIV_D_INX
12770 UINT64_C(469762131), // FDIV_H
12771 UINT64_C(469762131), // FDIV_H_INX
12772 UINT64_C(503316563), // FDIV_Q
12773 UINT64_C(402653267), // FDIV_S
12774 UINT64_C(402653267), // FDIV_S_INX
12775 UINT64_C(15), // FENCE
12776 UINT64_C(4111), // FENCE_I
12777 UINT64_C(2200961039), // FENCE_TSO
12778 UINT64_C(2717917267), // FEQ_D
12779 UINT64_C(2717917267), // FEQ_D_IN32X
12780 UINT64_C(2717917267), // FEQ_D_INX
12781 UINT64_C(2751471699), // FEQ_H
12782 UINT64_C(2751471699), // FEQ_H_INX
12783 UINT64_C(2785026131), // FEQ_Q
12784 UINT64_C(2684362835), // FEQ_S
12785 UINT64_C(2684362835), // FEQ_S_INX
12786 UINT64_C(12295), // FLD
12787 UINT64_C(2717925459), // FLEQ_D
12788 UINT64_C(2751479891), // FLEQ_H
12789 UINT64_C(2785034323), // FLEQ_Q
12790 UINT64_C(2684371027), // FLEQ_S
12791 UINT64_C(2717909075), // FLE_D
12792 UINT64_C(2717909075), // FLE_D_IN32X
12793 UINT64_C(2717909075), // FLE_D_INX
12794 UINT64_C(2751463507), // FLE_H
12795 UINT64_C(2751463507), // FLE_H_INX
12796 UINT64_C(2785017939), // FLE_Q
12797 UINT64_C(2684354643), // FLE_S
12798 UINT64_C(2684354643), // FLE_S_INX
12799 UINT64_C(4103), // FLH
12800 UINT64_C(4061134931), // FLI_D
12801 UINT64_C(4094689363), // FLI_H
12802 UINT64_C(4128243795), // FLI_Q
12803 UINT64_C(4027580499), // FLI_S
12804 UINT64_C(16391), // FLQ
12805 UINT64_C(2717929555), // FLTQ_D
12806 UINT64_C(2751483987), // FLTQ_H
12807 UINT64_C(2785038419), // FLTQ_Q
12808 UINT64_C(2684375123), // FLTQ_S
12809 UINT64_C(2717913171), // FLT_D
12810 UINT64_C(2717913171), // FLT_D_IN32X
12811 UINT64_C(2717913171), // FLT_D_INX
12812 UINT64_C(2751467603), // FLT_H
12813 UINT64_C(2751467603), // FLT_H_INX
12814 UINT64_C(2785022035), // FLT_Q
12815 UINT64_C(2684358739), // FLT_S
12816 UINT64_C(2684358739), // FLT_S_INX
12817 UINT64_C(8199), // FLW
12818 UINT64_C(33554499), // FMADD_D
12819 UINT64_C(33554499), // FMADD_D_IN32X
12820 UINT64_C(33554499), // FMADD_D_INX
12821 UINT64_C(67108931), // FMADD_H
12822 UINT64_C(67108931), // FMADD_H_INX
12823 UINT64_C(100663363), // FMADD_Q
12824 UINT64_C(67), // FMADD_S
12825 UINT64_C(67), // FMADD_S_INX
12826 UINT64_C(704655443), // FMAXM_D
12827 UINT64_C(738209875), // FMAXM_H
12828 UINT64_C(771764307), // FMAXM_Q
12829 UINT64_C(671101011), // FMAXM_S
12830 UINT64_C(704647251), // FMAX_D
12831 UINT64_C(704647251), // FMAX_D_IN32X
12832 UINT64_C(704647251), // FMAX_D_INX
12833 UINT64_C(738201683), // FMAX_H
12834 UINT64_C(738201683), // FMAX_H_INX
12835 UINT64_C(771756115), // FMAX_Q
12836 UINT64_C(671092819), // FMAX_S
12837 UINT64_C(671092819), // FMAX_S_INX
12838 UINT64_C(704651347), // FMINM_D
12839 UINT64_C(738205779), // FMINM_H
12840 UINT64_C(771760211), // FMINM_Q
12841 UINT64_C(671096915), // FMINM_S
12842 UINT64_C(704643155), // FMIN_D
12843 UINT64_C(704643155), // FMIN_D_IN32X
12844 UINT64_C(704643155), // FMIN_D_INX
12845 UINT64_C(738197587), // FMIN_H
12846 UINT64_C(738197587), // FMIN_H_INX
12847 UINT64_C(771752019), // FMIN_Q
12848 UINT64_C(671088723), // FMIN_S
12849 UINT64_C(671088723), // FMIN_S_INX
12850 UINT64_C(33554503), // FMSUB_D
12851 UINT64_C(33554503), // FMSUB_D_IN32X
12852 UINT64_C(33554503), // FMSUB_D_INX
12853 UINT64_C(67108935), // FMSUB_H
12854 UINT64_C(67108935), // FMSUB_H_INX
12855 UINT64_C(100663367), // FMSUB_Q
12856 UINT64_C(71), // FMSUB_S
12857 UINT64_C(71), // FMSUB_S_INX
12858 UINT64_C(301989971), // FMUL_D
12859 UINT64_C(301989971), // FMUL_D_IN32X
12860 UINT64_C(301989971), // FMUL_D_INX
12861 UINT64_C(335544403), // FMUL_H
12862 UINT64_C(335544403), // FMUL_H_INX
12863 UINT64_C(369098835), // FMUL_Q
12864 UINT64_C(268435539), // FMUL_S
12865 UINT64_C(268435539), // FMUL_S_INX
12866 UINT64_C(3792699475), // FMVH_X_D
12867 UINT64_C(3859808339), // FMVH_X_Q
12868 UINT64_C(2986344531), // FMVP_D_X
12869 UINT64_C(3053453395), // FMVP_Q_X
12870 UINT64_C(4060086355), // FMV_D_X
12871 UINT64_C(4093640787), // FMV_H_X
12872 UINT64_C(4026531923), // FMV_W_X
12873 UINT64_C(3791650899), // FMV_X_D
12874 UINT64_C(3825205331), // FMV_X_H
12875 UINT64_C(3758096467), // FMV_X_W
12876 UINT64_C(3758096467), // FMV_X_W_FPR64
12877 UINT64_C(33554511), // FNMADD_D
12878 UINT64_C(33554511), // FNMADD_D_IN32X
12879 UINT64_C(33554511), // FNMADD_D_INX
12880 UINT64_C(67108943), // FNMADD_H
12881 UINT64_C(67108943), // FNMADD_H_INX
12882 UINT64_C(100663375), // FNMADD_Q
12883 UINT64_C(79), // FNMADD_S
12884 UINT64_C(79), // FNMADD_S_INX
12885 UINT64_C(33554507), // FNMSUB_D
12886 UINT64_C(33554507), // FNMSUB_D_IN32X
12887 UINT64_C(33554507), // FNMSUB_D_INX
12888 UINT64_C(67108939), // FNMSUB_H
12889 UINT64_C(67108939), // FNMSUB_H_INX
12890 UINT64_C(100663371), // FNMSUB_Q
12891 UINT64_C(75), // FNMSUB_S
12892 UINT64_C(75), // FNMSUB_S_INX
12893 UINT64_C(1112539219), // FROUNDNX_D
12894 UINT64_C(1146093651), // FROUNDNX_H
12895 UINT64_C(1179648083), // FROUNDNX_Q
12896 UINT64_C(1078984787), // FROUNDNX_S
12897 UINT64_C(1111490643), // FROUND_D
12898 UINT64_C(1145045075), // FROUND_H
12899 UINT64_C(1178599507), // FROUND_Q
12900 UINT64_C(1077936211), // FROUND_S
12901 UINT64_C(12327), // FSD
12902 UINT64_C(570429523), // FSGNJN_D
12903 UINT64_C(570429523), // FSGNJN_D_IN32X
12904 UINT64_C(570429523), // FSGNJN_D_INX
12905 UINT64_C(603983955), // FSGNJN_H
12906 UINT64_C(603983955), // FSGNJN_H_INX
12907 UINT64_C(637538387), // FSGNJN_Q
12908 UINT64_C(536875091), // FSGNJN_S
12909 UINT64_C(536875091), // FSGNJN_S_INX
12910 UINT64_C(570433619), // FSGNJX_D
12911 UINT64_C(570433619), // FSGNJX_D_IN32X
12912 UINT64_C(570433619), // FSGNJX_D_INX
12913 UINT64_C(603988051), // FSGNJX_H
12914 UINT64_C(603988051), // FSGNJX_H_INX
12915 UINT64_C(637542483), // FSGNJX_Q
12916 UINT64_C(536879187), // FSGNJX_S
12917 UINT64_C(536879187), // FSGNJX_S_INX
12918 UINT64_C(570425427), // FSGNJ_D
12919 UINT64_C(570425427), // FSGNJ_D_IN32X
12920 UINT64_C(570425427), // FSGNJ_D_INX
12921 UINT64_C(603979859), // FSGNJ_H
12922 UINT64_C(603979859), // FSGNJ_H_INX
12923 UINT64_C(637534291), // FSGNJ_Q
12924 UINT64_C(536870995), // FSGNJ_S
12925 UINT64_C(536870995), // FSGNJ_S_INX
12926 UINT64_C(4135), // FSH
12927 UINT64_C(16423), // FSQ
12928 UINT64_C(1509949523), // FSQRT_D
12929 UINT64_C(1509949523), // FSQRT_D_IN32X
12930 UINT64_C(1509949523), // FSQRT_D_INX
12931 UINT64_C(1543503955), // FSQRT_H
12932 UINT64_C(1543503955), // FSQRT_H_INX
12933 UINT64_C(1577058387), // FSQRT_Q
12934 UINT64_C(1476395091), // FSQRT_S
12935 UINT64_C(1476395091), // FSQRT_S_INX
12936 UINT64_C(167772243), // FSUB_D
12937 UINT64_C(167772243), // FSUB_D_IN32X
12938 UINT64_C(167772243), // FSUB_D_INX
12939 UINT64_C(201326675), // FSUB_H
12940 UINT64_C(201326675), // FSUB_H_INX
12941 UINT64_C(234881107), // FSUB_Q
12942 UINT64_C(134217811), // FSUB_S
12943 UINT64_C(134217811), // FSUB_S_INX
12944 UINT64_C(8231), // FSW
12945 UINT64_C(1644167283), // HFENCE_GVMA
12946 UINT64_C(570425459), // HFENCE_VVMA
12947 UINT64_C(1711276147), // HINVAL_GVMA
12948 UINT64_C(637534323), // HINVAL_VVMA
12949 UINT64_C(1680883827), // HLVX_HU
12950 UINT64_C(1747992691), // HLVX_WU
12951 UINT64_C(1610629235), // HLV_B
12952 UINT64_C(1611677811), // HLV_BU
12953 UINT64_C(1811955827), // HLV_D
12954 UINT64_C(1677738099), // HLV_H
12955 UINT64_C(1678786675), // HLV_HU
12956 UINT64_C(1744846963), // HLV_W
12957 UINT64_C(1745895539), // HLV_WU
12958 UINT64_C(1644183667), // HSV_B
12959 UINT64_C(1845510259), // HSV_D
12960 UINT64_C(1711292531), // HSV_H
12961 UINT64_C(1778401395), // HSV_W
12962 UINT64_C(0), // Insn16
12963 UINT64_C(0), // Insn32
12964 UINT64_C(0), // Insn48
12965 UINT64_C(0), // Insn64
12966 UINT64_C(0), // InsnB
12967 UINT64_C(0), // InsnCA
12968 UINT64_C(0), // InsnCB
12969 UINT64_C(0), // InsnCI
12970 UINT64_C(0), // InsnCIW
12971 UINT64_C(0), // InsnCJ
12972 UINT64_C(0), // InsnCL
12973 UINT64_C(0), // InsnCR
12974 UINT64_C(0), // InsnCS
12975 UINT64_C(0), // InsnCSS
12976 UINT64_C(0), // InsnI
12977 UINT64_C(0), // InsnI_Mem
12978 UINT64_C(0), // InsnJ
12979 UINT64_C(0), // InsnQC_EAI
12980 UINT64_C(0), // InsnQC_EB
12981 UINT64_C(0), // InsnQC_EI
12982 UINT64_C(0), // InsnQC_EI_Mem
12983 UINT64_C(0), // InsnQC_EJ
12984 UINT64_C(0), // InsnQC_ES
12985 UINT64_C(0), // InsnR
12986 UINT64_C(0), // InsnR4
12987 UINT64_C(0), // InsnS
12988 UINT64_C(0), // InsnU
12989 UINT64_C(111), // JAL
12990 UINT64_C(103), // JALR
12991 UINT64_C(3), // LB
12992 UINT64_C(16387), // LBU
12993 UINT64_C(872415279), // LB_AQ
12994 UINT64_C(905969711), // LB_AQ_RL
12995 UINT64_C(12291), // LD
12996 UINT64_C(872427567), // LD_AQ
12997 UINT64_C(905981999), // LD_AQ_RL
12998 UINT64_C(12291), // LD_RV32
12999 UINT64_C(4099), // LH
13000 UINT64_C(20483), // LHU
13001 UINT64_C(872419375), // LH_AQ
13002 UINT64_C(905973807), // LH_AQ_RL
13003 UINT64_C(4099), // LH_INX
13004 UINT64_C(268447791), // LR_D
13005 UINT64_C(335556655), // LR_D_AQ
13006 UINT64_C(369111087), // LR_D_AQ_RL
13007 UINT64_C(302002223), // LR_D_RL
13008 UINT64_C(268443695), // LR_W
13009 UINT64_C(335552559), // LR_W_AQ
13010 UINT64_C(369106991), // LR_W_AQ_RL
13011 UINT64_C(301998127), // LR_W_RL
13012 UINT64_C(55), // LUI
13013 UINT64_C(8195), // LW
13014 UINT64_C(24579), // LWU
13015 UINT64_C(872423471), // LW_AQ
13016 UINT64_C(905977903), // LW_AQ_RL
13017 UINT64_C(8195), // LW_INX
13018 UINT64_C(167796787), // MAX
13019 UINT64_C(167800883), // MAXU
13020 UINT64_C(167788595), // MIN
13021 UINT64_C(167792691), // MINU
13022 UINT64_C(100675595), // MIPS_CCMOV
13023 UINT64_C(16395), // MIPS_LDP
13024 UINT64_C(1064971), // MIPS_LWP
13025 UINT64_C(11), // MIPS_PREFETCH
13026 UINT64_C(20491), // MIPS_SDP
13027 UINT64_C(20619), // MIPS_SWP
13028 UINT64_C(1881145459), // MNRET
13029 UINT64_C(2176860275), // MOPR0
13030 UINT64_C(2177908851), // MOPR1
13031 UINT64_C(2313175155), // MOPR10
13032 UINT64_C(2314223731), // MOPR11
13033 UINT64_C(2378186867), // MOPR12
13034 UINT64_C(2379235443), // MOPR13
13035 UINT64_C(2380284019), // MOPR14
13036 UINT64_C(2381332595), // MOPR15
13037 UINT64_C(3250602099), // MOPR16
13038 UINT64_C(3251650675), // MOPR17
13039 UINT64_C(3252699251), // MOPR18
13040 UINT64_C(3253747827), // MOPR19
13041 UINT64_C(2178957427), // MOPR2
13042 UINT64_C(3317710963), // MOPR20
13043 UINT64_C(3318759539), // MOPR21
13044 UINT64_C(3319808115), // MOPR22
13045 UINT64_C(3320856691), // MOPR23
13046 UINT64_C(3384819827), // MOPR24
13047 UINT64_C(3385868403), // MOPR25
13048 UINT64_C(3386916979), // MOPR26
13049 UINT64_C(3387965555), // MOPR27
13050 UINT64_C(3451928691), // MOPR28
13051 UINT64_C(3452977267), // MOPR29
13052 UINT64_C(2180006003), // MOPR3
13053 UINT64_C(3454025843), // MOPR30
13054 UINT64_C(3455074419), // MOPR31
13055 UINT64_C(2243969139), // MOPR4
13056 UINT64_C(2245017715), // MOPR5
13057 UINT64_C(2246066291), // MOPR6
13058 UINT64_C(2247114867), // MOPR7
13059 UINT64_C(2311078003), // MOPR8
13060 UINT64_C(2312126579), // MOPR9
13061 UINT64_C(2181054579), // MOPRR0
13062 UINT64_C(2248163443), // MOPRR1
13063 UINT64_C(2315272307), // MOPRR2
13064 UINT64_C(2382381171), // MOPRR3
13065 UINT64_C(3254796403), // MOPRR4
13066 UINT64_C(3321905267), // MOPRR5
13067 UINT64_C(3389014131), // MOPRR6
13068 UINT64_C(3456122995), // MOPRR7
13069 UINT64_C(807403635), // MRET
13070 UINT64_C(33554483), // MUL
13071 UINT64_C(33558579), // MULH
13072 UINT64_C(33562675), // MULHSU
13073 UINT64_C(33566771), // MULHU
13074 UINT64_C(33554491), // MULW
13075 UINT64_C(4107), // NDS_ADDIGP
13076 UINT64_C(28763), // NDS_BBC
13077 UINT64_C(1073770587), // NDS_BBS
13078 UINT64_C(20571), // NDS_BEQC
13079 UINT64_C(12379), // NDS_BFOS
13080 UINT64_C(8283), // NDS_BFOZ
13081 UINT64_C(24667), // NDS_BNEC
13082 UINT64_C(536871003), // NDS_FFB
13083 UINT64_C(603979867), // NDS_FFMISM
13084 UINT64_C(570425435), // NDS_FFZMISM
13085 UINT64_C(637534299), // NDS_FLMISM
13086 UINT64_C(11), // NDS_LBGP
13087 UINT64_C(8203), // NDS_LBUGP
13088 UINT64_C(12331), // NDS_LDGP
13089 UINT64_C(268435547), // NDS_LEA_B_ZE
13090 UINT64_C(234881115), // NDS_LEA_D
13091 UINT64_C(369098843), // NDS_LEA_D_ZE
13092 UINT64_C(167772251), // NDS_LEA_H
13093 UINT64_C(301989979), // NDS_LEA_H_ZE
13094 UINT64_C(201326683), // NDS_LEA_W
13095 UINT64_C(335544411), // NDS_LEA_W_ZE
13096 UINT64_C(4139), // NDS_LHGP
13097 UINT64_C(20523), // NDS_LHUGP
13098 UINT64_C(8235), // NDS_LWGP
13099 UINT64_C(24619), // NDS_LWUGP
13100 UINT64_C(12299), // NDS_SBGP
13101 UINT64_C(28715), // NDS_SDGP
13102 UINT64_C(43), // NDS_SHGP
13103 UINT64_C(16427), // NDS_SWGP
13104 UINT64_C(335560795), // NDS_VD4DOTSU_VV
13105 UINT64_C(268451931), // NDS_VD4DOTS_VV
13106 UINT64_C(469778523), // NDS_VD4DOTU_VV
13107 UINT64_C(49243), // NDS_VFNCVT_BF16_S
13108 UINT64_C(201343067), // NDS_VFPMADB_VF
13109 UINT64_C(134234203), // NDS_VFPMADT_VF
13110 UINT64_C(16475), // NDS_VFWCVT_S_BF16
13111 UINT64_C(24627), // OR
13112 UINT64_C(678449171), // ORC_B
13113 UINT64_C(24595), // ORI
13114 UINT64_C(1073766451), // ORN
13115 UINT64_C(134234163), // PACK
13116 UINT64_C(134246451), // PACKH
13117 UINT64_C(134234171), // PACKW
13118 UINT64_C(3019907099), // PLI_B
13119 UINT64_C(2952798235), // PLI_H
13120 UINT64_C(2986352667), // PLI_W
13121 UINT64_C(4026540059), // PLUI_H
13122 UINT64_C(4060094491), // PLUI_W
13123 UINT64_C(24595), // PREFETCH_I
13124 UINT64_C(1073171), // PREFETCH_R
13125 UINT64_C(3170323), // PREFETCH_W
13126 UINT64_C(3832553499), // PSABS_B
13127 UINT64_C(3765444635), // PSABS_H
13128 UINT64_C(3762298907), // PSEXT_H_B
13129 UINT64_C(3795853339), // PSEXT_W_B
13130 UINT64_C(3796901915), // PSEXT_W_H
13131 UINT64_C(2155880475), // PSLLI_B
13132 UINT64_C(2164269083), // PSLLI_H
13133 UINT64_C(2181046299), // PSLLI_W
13134 UINT64_C(3506446363), // PSSLAI_H
13135 UINT64_C(3523223579), // PSSLAI_W
13136 UINT64_C(469774347), // QC_ADDSAT
13137 UINT64_C(503328779), // QC_ADDUSAT
13138 UINT64_C(123), // QC_BEQI
13139 UINT64_C(20603), // QC_BGEI
13140 UINT64_C(28795), // QC_BGEUI
13141 UINT64_C(16507), // QC_BLTI
13142 UINT64_C(24699), // QC_BLTUI
13143 UINT64_C(4219), // QC_BNEI
13144 UINT64_C(201338891), // QC_BREV32
13145 UINT64_C(134230027), // QC_CLO
13146 UINT64_C(3456106611), // QC_CLRINTI
13147 UINT64_C(44130), // QC_CM_MVA01S
13148 UINT64_C(44066), // QC_CM_MVSA01
13149 UINT64_C(47618), // QC_CM_POP
13150 UINT64_C(48642), // QC_CM_POPRET
13151 UINT64_C(48130), // QC_CM_POPRETZ
13152 UINT64_C(47106), // QC_CM_PUSH
13153 UINT64_C(47362), // QC_CM_PUSHFP
13154 UINT64_C(12299), // QC_COMPRESS2
13155 UINT64_C(33566731), // QC_COMPRESS3
13156 UINT64_C(2348810355), // QC_CSRRWR
13157 UINT64_C(2382364787), // QC_CSRRWRI
13158 UINT64_C(167784459), // QC_CTO
13159 UINT64_C(36865), // QC_C_BEXTI
13160 UINT64_C(37889), // QC_C_BSETI
13161 UINT64_C(4110), // QC_C_CLRINT
13162 UINT64_C(2), // QC_C_DELAY
13163 UINT64_C(6930), // QC_C_DI
13164 UINT64_C(4098), // QC_C_DIR
13165 UINT64_C(7058), // QC_C_EI
13166 UINT64_C(4102), // QC_C_EIR
13167 UINT64_C(4098), // QC_C_EXTU
13168 UINT64_C(6162), // QC_C_MIENTER
13169 UINT64_C(6290), // QC_C_MIENTER_NEST
13170 UINT64_C(6674), // QC_C_MILEAVERET
13171 UINT64_C(6546), // QC_C_MNRET
13172 UINT64_C(6418), // QC_C_MRET
13173 UINT64_C(8194), // QC_C_MULIADD
13174 UINT64_C(44034), // QC_C_MVEQZ
13175 UINT64_C(2), // QC_C_PTRACE
13176 UINT64_C(4106), // QC_C_SETINT
13177 UINT64_C(32769), // QC_C_SYNC
13178 UINT64_C(33793), // QC_C_SYNCR
13179 UINT64_C(36865), // QC_C_SYNCWF
13180 UINT64_C(37889), // QC_C_SYNCWL
13181 UINT64_C(67121163), // QC_EXPAND2
13182 UINT64_C(100675595), // QC_EXPAND3
13183 UINT64_C(1073750027), // QC_EXT
13184 UINT64_C(3221233675), // QC_EXTD
13185 UINT64_C(268447755), // QC_EXTDPR
13186 UINT64_C(302002187), // QC_EXTDPRH
13187 UINT64_C(167784459), // QC_EXTDR
13188 UINT64_C(2147491851), // QC_EXTDU
13189 UINT64_C(201338891), // QC_EXTDUPR
13190 UINT64_C(234893323), // QC_EXTDUPRH
13191 UINT64_C(134230027), // QC_EXTDUR
13192 UINT64_C(8203), // QC_EXTU
13193 UINT64_C(8223), // QC_E_ADDAI
13194 UINT64_C(2147495967), // QC_E_ADDI
13195 UINT64_C(40991), // QC_E_ANDAI
13196 UINT64_C(3221237791), // QC_E_ANDI
13197 UINT64_C(25182239), // QC_E_BEQI
13198 UINT64_C(30425119), // QC_E_BGEI
13199 UINT64_C(32522271), // QC_E_BGEUI
13200 UINT64_C(29376543), // QC_E_BLTI
13201 UINT64_C(31473695), // QC_E_BLTUI
13202 UINT64_C(26230815), // QC_E_BNEI
13203 UINT64_C(16415), // QC_E_J
13204 UINT64_C(49183), // QC_E_JAL
13205 UINT64_C(20511), // QC_E_LB
13206 UINT64_C(1073762335), // QC_E_LBU
13207 UINT64_C(2147504159), // QC_E_LH
13208 UINT64_C(3221245983), // QC_E_LHU
13209 UINT64_C(31), // QC_E_LI
13210 UINT64_C(24607), // QC_E_LW
13211 UINT64_C(36895), // QC_E_ORAI
13212 UINT64_C(1073754143), // QC_E_ORI
13213 UINT64_C(1073766431), // QC_E_SB
13214 UINT64_C(2147508255), // QC_E_SH
13215 UINT64_C(3221250079), // QC_E_SW
13216 UINT64_C(4127), // QC_E_XORAI
13217 UINT64_C(12319), // QC_E_XORI
13218 UINT64_C(1073745931), // QC_INSB
13219 UINT64_C(2147487755), // QC_INSBH
13220 UINT64_C(33566731), // QC_INSBHR
13221 UINT64_C(4107), // QC_INSBI
13222 UINT64_C(67121163), // QC_INSBPR
13223 UINT64_C(100675595), // QC_INSBPRH
13224 UINT64_C(12299), // QC_INSBR
13225 UINT64_C(2147483659), // QC_INSBRI
13226 UINT64_C(20491), // QC_INW
13227 UINT64_C(27), // QC_LI
13228 UINT64_C(33554523), // QC_LIEQ
13229 UINT64_C(100663387), // QC_LIEQI
13230 UINT64_C(33575003), // QC_LIGE
13231 UINT64_C(100683867), // QC_LIGEI
13232 UINT64_C(33583195), // QC_LIGEU
13233 UINT64_C(100692059), // QC_LIGEUI
13234 UINT64_C(33570907), // QC_LILT
13235 UINT64_C(100679771), // QC_LILTI
13236 UINT64_C(33579099), // QC_LILTU
13237 UINT64_C(100687963), // QC_LILTUI
13238 UINT64_C(33558619), // QC_LINE
13239 UINT64_C(100667483), // QC_LINEI
13240 UINT64_C(2147512331), // QC_LRB
13241 UINT64_C(2952818699), // QC_LRBU
13242 UINT64_C(2415947787), // QC_LRH
13243 UINT64_C(3221254155), // QC_LRHU
13244 UINT64_C(2684383243), // QC_LRW
13245 UINT64_C(28683), // QC_LWM
13246 UINT64_C(1073770507), // QC_LWMI
13247 UINT64_C(24587), // QC_MULIADD
13248 UINT64_C(91), // QC_MVEQ
13249 UINT64_C(67108955), // QC_MVEQI
13250 UINT64_C(20571), // QC_MVGE
13251 UINT64_C(67129435), // QC_MVGEI
13252 UINT64_C(28763), // QC_MVGEU
13253 UINT64_C(67137627), // QC_MVGEUI
13254 UINT64_C(16475), // QC_MVLT
13255 UINT64_C(67125339), // QC_MVLTI
13256 UINT64_C(24667), // QC_MVLTU
13257 UINT64_C(67133531), // QC_MVLTUI
13258 UINT64_C(4187), // QC_MVNE
13259 UINT64_C(67113051), // QC_MVNEI
13260 UINT64_C(234893323), // QC_NORM
13261 UINT64_C(302002187), // QC_NORMEU
13262 UINT64_C(268447755), // QC_NORMU
13263 UINT64_C(16395), // QC_OUTW
13264 UINT64_C(1610620947), // QC_PCOREDUMP
13265 UINT64_C(2952798227), // QC_PEXIT
13266 UINT64_C(2147491859), // QC_PPREG
13267 UINT64_C(1879056403), // QC_PPREGS
13268 UINT64_C(2415927315), // QC_PPUTC
13269 UINT64_C(1073750035), // QC_PPUTCI
13270 UINT64_C(2684362771), // QC_PPUTS
13271 UINT64_C(3221233683), // QC_PSYSCALL
13272 UINT64_C(8211), // QC_PSYSCALLI
13273 UINT64_C(67117147), // QC_SELECTEQI
13274 UINT64_C(33562715), // QC_SELECTIEQ
13275 UINT64_C(100671579), // QC_SELECTIEQI
13276 UINT64_C(8283), // QC_SELECTIIEQ
13277 UINT64_C(12379), // QC_SELECTIINE
13278 UINT64_C(33566811), // QC_SELECTINE
13279 UINT64_C(100675675), // QC_SELECTINEI
13280 UINT64_C(67121243), // QC_SELECTNEI
13281 UINT64_C(3422552179), // QC_SETINTI
13282 UINT64_C(2147512363), // QC_SETWM
13283 UINT64_C(3221254187), // QC_SETWMI
13284 UINT64_C(1073754123), // QC_SHLADD
13285 UINT64_C(335556619), // QC_SHLSAT
13286 UINT64_C(402665483), // QC_SHLUSAT
13287 UINT64_C(3489685547), // QC_SRB
13288 UINT64_C(3758121003), // QC_SRH
13289 UINT64_C(4026556459), // QC_SRW
13290 UINT64_C(536883211), // QC_SUBSAT
13291 UINT64_C(570437643), // QC_SUBUSAT
13292 UINT64_C(28715), // QC_SWM
13293 UINT64_C(1073770539), // QC_SWMI
13294 UINT64_C(268447763), // QC_SYNC
13295 UINT64_C(536883219), // QC_SYNCR
13296 UINT64_C(1073754131), // QC_SYNCWF
13297 UINT64_C(2147495955), // QC_SYNCWL
13298 UINT64_C(603992075), // QC_WRAP
13299 UINT64_C(11), // QC_WRAPI
13300 UINT64_C(8192), // QK_C_LBU
13301 UINT64_C(32768), // QK_C_LBUSP
13302 UINT64_C(8194), // QK_C_LHU
13303 UINT64_C(32800), // QK_C_LHUSP
13304 UINT64_C(40960), // QK_C_SB
13305 UINT64_C(32832), // QK_C_SBSP
13306 UINT64_C(40962), // QK_C_SH
13307 UINT64_C(32864), // QK_C_SHSP
13308 UINT64_C(33579059), // REM
13309 UINT64_C(33583155), // REMU
13310 UINT64_C(33583163), // REMUW
13311 UINT64_C(33579067), // REMW
13312 UINT64_C(1795182611), // REV16
13313 UINT64_C(1770016787), // REV8_RV32
13314 UINT64_C(1803571219), // REV8_RV64
13315 UINT64_C(1777356819), // REV_RV32
13316 UINT64_C(1810911251), // REV_RV64
13317 UINT64_C(1577066587), // RI_VEXTRACT
13318 UINT64_C(1073766491), // RI_VINSERT
13319 UINT64_C(536871003), // RI_VUNZIP2A_VV
13320 UINT64_C(1610612827), // RI_VUNZIP2B_VV
13321 UINT64_C(28763), // RI_VZERO
13322 UINT64_C(268435547), // RI_VZIP2A_VV
13323 UINT64_C(1342177371), // RI_VZIP2B_VV
13324 UINT64_C(805306459), // RI_VZIPEVEN_VV
13325 UINT64_C(1879048283), // RI_VZIPODD_VV
13326 UINT64_C(1610616883), // ROL
13327 UINT64_C(1610616891), // ROLW
13328 UINT64_C(1610633267), // ROR
13329 UINT64_C(1610633235), // RORI
13330 UINT64_C(1610633243), // RORIW
13331 UINT64_C(1610633275), // RORW
13332 UINT64_C(35), // SB
13333 UINT64_C(1040187439), // SB_AQ_RL
13334 UINT64_C(973078575), // SB_RL
13335 UINT64_C(272629875), // SCTRCLR
13336 UINT64_C(402665519), // SC_D
13337 UINT64_C(469774383), // SC_D_AQ
13338 UINT64_C(503328815), // SC_D_AQ_RL
13339 UINT64_C(436219951), // SC_D_RL
13340 UINT64_C(402661423), // SC_W
13341 UINT64_C(469770287), // SC_W_AQ
13342 UINT64_C(503324719), // SC_W_AQ_RL
13343 UINT64_C(436215855), // SC_W_RL
13344 UINT64_C(12323), // SD
13345 UINT64_C(1040199727), // SD_AQ_RL
13346 UINT64_C(973090863), // SD_RL
13347 UINT64_C(12323), // SD_RV32
13348 UINT64_C(1614811155), // SEXT_B
13349 UINT64_C(1615859731), // SEXT_H
13350 UINT64_C(403701875), // SFENCE_INVAL_IR
13351 UINT64_C(301990003), // SFENCE_VMA
13352 UINT64_C(402653299), // SFENCE_W_INVAL
13353 UINT64_C(4229955699), // SF_CDISCARD_D_L1
13354 UINT64_C(810549363), // SF_CEASE
13355 UINT64_C(4227858547), // SF_CFLUSH_D_L1
13356 UINT64_C(4261417207), // SF_MM_E4M3_E4M3
13357 UINT64_C(4261417079), // SF_MM_E4M3_E5M2
13358 UINT64_C(4194308343), // SF_MM_E5M2_E4M3
13359 UINT64_C(4194308215), // SF_MM_E5M2_E5M2
13360 UINT64_C(4060090487), // SF_MM_F_F
13361 UINT64_C(4127195383), // SF_MM_S_S
13362 UINT64_C(4127195255), // SF_MM_S_U
13363 UINT64_C(4060086519), // SF_MM_U_S
13364 UINT64_C(4060086391), // SF_MM_U_U
13365 UINT64_C(704663643), // SF_VC_FV
13366 UINT64_C(2852147291), // SF_VC_FVV
13367 UINT64_C(4194324571), // SF_VC_FVW
13368 UINT64_C(33566811), // SF_VC_I
13369 UINT64_C(570437723), // SF_VC_IV
13370 UINT64_C(2717921371), // SF_VC_IVV
13371 UINT64_C(4060098651), // SF_VC_IVW
13372 UINT64_C(570425435), // SF_VC_VV
13373 UINT64_C(2717909083), // SF_VC_VVV
13374 UINT64_C(4060086363), // SF_VC_VVW
13375 UINT64_C(671109211), // SF_VC_V_FV
13376 UINT64_C(2818592859), // SF_VC_V_FVV
13377 UINT64_C(4160770139), // SF_VC_V_FVW
13378 UINT64_C(12379), // SF_VC_V_I
13379 UINT64_C(536883291), // SF_VC_V_IV
13380 UINT64_C(2684366939), // SF_VC_V_IVV
13381 UINT64_C(4026544219), // SF_VC_V_IVW
13382 UINT64_C(536871003), // SF_VC_V_VV
13383 UINT64_C(2684354651), // SF_VC_V_VVV
13384 UINT64_C(4026531931), // SF_VC_V_VVW
13385 UINT64_C(16475), // SF_VC_V_X
13386 UINT64_C(536887387), // SF_VC_V_XV
13387 UINT64_C(2684371035), // SF_VC_V_XVV
13388 UINT64_C(4026548315), // SF_VC_V_XVW
13389 UINT64_C(33570907), // SF_VC_X
13390 UINT64_C(570441819), // SF_VC_XV
13391 UINT64_C(2717925467), // SF_VC_XVV
13392 UINT64_C(4060102747), // SF_VC_XVW
13393 UINT64_C(2281721947), // SF_VFNRCLIP_XU_F_QF
13394 UINT64_C(2348830811), // SF_VFNRCLIP_X_F_QF
13395 UINT64_C(4060090459), // SF_VFWMACC_4x4x4
13396 UINT64_C(838889479), // SF_VLTE16
13397 UINT64_C(1375760391), // SF_VLTE32
13398 UINT64_C(1912631303), // SF_VLTE64
13399 UINT64_C(302018567), // SF_VLTE8
13400 UINT64_C(3187679323), // SF_VQMACCSU_2x8x2
13401 UINT64_C(4261421147), // SF_VQMACCSU_4x8x4
13402 UINT64_C(3120570459), // SF_VQMACCUS_2x8x2
13403 UINT64_C(4194312283), // SF_VQMACCUS_4x8x4
13404 UINT64_C(2986352731), // SF_VQMACCU_2x8x2
13405 UINT64_C(4060094555), // SF_VQMACCU_4x8x4
13406 UINT64_C(3053461595), // SF_VQMACC_2x8x2
13407 UINT64_C(4127203419), // SF_VQMACC_4x8x4
13408 UINT64_C(2216718423), // SF_VSETTK
13409 UINT64_C(2215669847), // SF_VSETTM
13410 UINT64_C(2214621271), // SF_VSETTN
13411 UINT64_C(838889511), // SF_VSTE16
13412 UINT64_C(1375760423), // SF_VSTE32
13413 UINT64_C(1912631335), // SF_VSTE64
13414 UINT64_C(302018599), // SF_VSTE8
13415 UINT64_C(1136681047), // SF_VTDISCARD
13416 UINT64_C(1577082967), // SF_VTMV_T_V
13417 UINT64_C(1139826775), // SF_VTMV_V_T
13418 UINT64_C(1138778199), // SF_VTZERO_T
13419 UINT64_C(4131), // SH
13420 UINT64_C(536879155), // SH1ADD
13421 UINT64_C(536879163), // SH1ADD_UW
13422 UINT64_C(536887347), // SH2ADD
13423 UINT64_C(536887355), // SH2ADD_UW
13424 UINT64_C(536895539), // SH3ADD
13425 UINT64_C(536895547), // SH3ADD_UW
13426 UINT64_C(270536723), // SHA256SIG0
13427 UINT64_C(271585299), // SHA256SIG1
13428 UINT64_C(268439571), // SHA256SUM0
13429 UINT64_C(269488147), // SHA256SUM1
13430 UINT64_C(274731027), // SHA512SIG0
13431 UINT64_C(1543503923), // SHA512SIG0H
13432 UINT64_C(1409286195), // SHA512SIG0L
13433 UINT64_C(275779603), // SHA512SIG1
13434 UINT64_C(1577058355), // SHA512SIG1H
13435 UINT64_C(1442840627), // SHA512SIG1L
13436 UINT64_C(272633875), // SHA512SUM0
13437 UINT64_C(1342177331), // SHA512SUM0R
13438 UINT64_C(273682451), // SHA512SUM1
13439 UINT64_C(1375731763), // SHA512SUM1R
13440 UINT64_C(1040191535), // SH_AQ_RL
13441 UINT64_C(4131), // SH_INX
13442 UINT64_C(973082671), // SH_RL
13443 UINT64_C(369098867), // SINVAL_VMA
13444 UINT64_C(4147), // SLL
13445 UINT64_C(4115), // SLLI
13446 UINT64_C(4123), // SLLIW
13447 UINT64_C(134221851), // SLLI_UW
13448 UINT64_C(4155), // SLLW
13449 UINT64_C(8243), // SLT
13450 UINT64_C(8211), // SLTI
13451 UINT64_C(12307), // SLTIU
13452 UINT64_C(12339), // SLTU
13453 UINT64_C(276828179), // SM3P0
13454 UINT64_C(277876755), // SM3P1
13455 UINT64_C(805306419), // SM4ED
13456 UINT64_C(872415283), // SM4KS
13457 UINT64_C(1073762355), // SRA
13458 UINT64_C(1073762323), // SRAI
13459 UINT64_C(1073762331), // SRAIW
13460 UINT64_C(1073762363), // SRAW
13461 UINT64_C(270532723), // SRET
13462 UINT64_C(20531), // SRL
13463 UINT64_C(20499), // SRLI
13464 UINT64_C(20507), // SRLIW
13465 UINT64_C(20539), // SRLW
13466 UINT64_C(1207971887), // SSAMOSWAP_D
13467 UINT64_C(1275080751), // SSAMOSWAP_D_AQ
13468 UINT64_C(1308635183), // SSAMOSWAP_D_AQ_RL
13469 UINT64_C(1241526319), // SSAMOSWAP_D_RL
13470 UINT64_C(1207967791), // SSAMOSWAP_W
13471 UINT64_C(1275076655), // SSAMOSWAP_W_AQ
13472 UINT64_C(1308631087), // SSAMOSWAP_W_AQ_RL
13473 UINT64_C(1241522223), // SSAMOSWAP_W_RL
13474 UINT64_C(3523223579), // SSLAI
13475 UINT64_C(3451928691), // SSPOPCHK
13476 UINT64_C(3456122995), // SSPUSH
13477 UINT64_C(3451928691), // SSRDP
13478 UINT64_C(1073741875), // SUB
13479 UINT64_C(1073741883), // SUBW
13480 UINT64_C(8227), // SW
13481 UINT64_C(1040195631), // SW_AQ_RL
13482 UINT64_C(8227), // SW_INX
13483 UINT64_C(973086767), // SW_RL
13484 UINT64_C(4107), // TH_ADDSL
13485 UINT64_C(1048587), // TH_DCACHE_CALL
13486 UINT64_C(3145739), // TH_DCACHE_CIALL
13487 UINT64_C(45088779), // TH_DCACHE_CIPA
13488 UINT64_C(36700171), // TH_DCACHE_CISW
13489 UINT64_C(40894475), // TH_DCACHE_CIVA
13490 UINT64_C(42991627), // TH_DCACHE_CPA
13491 UINT64_C(41943051), // TH_DCACHE_CPAL1
13492 UINT64_C(34603019), // TH_DCACHE_CSW
13493 UINT64_C(38797323), // TH_DCACHE_CVA
13494 UINT64_C(37748747), // TH_DCACHE_CVAL1
13495 UINT64_C(2097163), // TH_DCACHE_IALL
13496 UINT64_C(44040203), // TH_DCACHE_IPA
13497 UINT64_C(35651595), // TH_DCACHE_ISW
13498 UINT64_C(39845899), // TH_DCACHE_IVA
13499 UINT64_C(8203), // TH_EXT
13500 UINT64_C(12299), // TH_EXTU
13501 UINT64_C(2214596619), // TH_FF0
13502 UINT64_C(2248151051), // TH_FF1
13503 UINT64_C(1610637323), // TH_FLRD
13504 UINT64_C(1073766411), // TH_FLRW
13505 UINT64_C(1879072779), // TH_FLURD
13506 UINT64_C(1342201867), // TH_FLURW
13507 UINT64_C(1610641419), // TH_FSRD
13508 UINT64_C(1073770507), // TH_FSRW
13509 UINT64_C(1879076875), // TH_FSURD
13510 UINT64_C(1342205963), // TH_FSURW
13511 UINT64_C(16777227), // TH_ICACHE_IALL
13512 UINT64_C(17825803), // TH_ICACHE_IALLS
13513 UINT64_C(58720267), // TH_ICACHE_IPA
13514 UINT64_C(50331659), // TH_ICACHE_IVA
13515 UINT64_C(22020107), // TH_L2CACHE_CALL
13516 UINT64_C(24117259), // TH_L2CACHE_CIALL
13517 UINT64_C(23068683), // TH_L2CACHE_IALL
13518 UINT64_C(402669579), // TH_LBIA
13519 UINT64_C(134234123), // TH_LBIB
13520 UINT64_C(2550153227), // TH_LBUIA
13521 UINT64_C(2281717771), // TH_LBUIB
13522 UINT64_C(4160765963), // TH_LDD
13523 UINT64_C(2013282315), // TH_LDIA
13524 UINT64_C(1744846859), // TH_LDIB
13525 UINT64_C(939540491), // TH_LHIA
13526 UINT64_C(671105035), // TH_LHIB
13527 UINT64_C(3087024139), // TH_LHUIA
13528 UINT64_C(2818588683), // TH_LHUIB
13529 UINT64_C(16395), // TH_LRB
13530 UINT64_C(2147500043), // TH_LRBU
13531 UINT64_C(1610629131), // TH_LRD
13532 UINT64_C(536887307), // TH_LRH
13533 UINT64_C(2684370955), // TH_LRHU
13534 UINT64_C(1073758219), // TH_LRW
13535 UINT64_C(3221241867), // TH_LRWU
13536 UINT64_C(268451851), // TH_LURB
13537 UINT64_C(2415935499), // TH_LURBU
13538 UINT64_C(1879064587), // TH_LURD
13539 UINT64_C(805322763), // TH_LURH
13540 UINT64_C(2952806411), // TH_LURHU
13541 UINT64_C(1342193675), // TH_LURW
13542 UINT64_C(3489677323), // TH_LURWU
13543 UINT64_C(3758112779), // TH_LWD
13544 UINT64_C(1476411403), // TH_LWIA
13545 UINT64_C(1207975947), // TH_LWIB
13546 UINT64_C(4026548235), // TH_LWUD
13547 UINT64_C(3623895051), // TH_LWUIA
13548 UINT64_C(3355459595), // TH_LWUIB
13549 UINT64_C(536875019), // TH_MULA
13550 UINT64_C(671092747), // TH_MULAH
13551 UINT64_C(603983883), // TH_MULAW
13552 UINT64_C(570429451), // TH_MULS
13553 UINT64_C(704647179), // TH_MULSH
13554 UINT64_C(637538315), // TH_MULSW
13555 UINT64_C(1073745931), // TH_MVEQZ
13556 UINT64_C(1107300363), // TH_MVNEZ
13557 UINT64_C(2181042187), // TH_REV
13558 UINT64_C(2415923211), // TH_REVW
13559 UINT64_C(402673675), // TH_SBIA
13560 UINT64_C(134238219), // TH_SBIB
13561 UINT64_C(4160770059), // TH_SDD
13562 UINT64_C(2013286411), // TH_SDIA
13563 UINT64_C(1744850955), // TH_SDIB
13564 UINT64_C(67108875), // TH_SFENCE_VMAS
13565 UINT64_C(939544587), // TH_SHIA
13566 UINT64_C(671109131), // TH_SHIB
13567 UINT64_C(20491), // TH_SRB
13568 UINT64_C(1610633227), // TH_SRD
13569 UINT64_C(536891403), // TH_SRH
13570 UINT64_C(268439563), // TH_SRRI
13571 UINT64_C(335548427), // TH_SRRIW
13572 UINT64_C(1073762315), // TH_SRW
13573 UINT64_C(268455947), // TH_SURB
13574 UINT64_C(1879068683), // TH_SURD
13575 UINT64_C(805326859), // TH_SURH
13576 UINT64_C(1342197771), // TH_SURW
13577 UINT64_C(3758116875), // TH_SWD
13578 UINT64_C(1476415499), // TH_SWIA
13579 UINT64_C(1207980043), // TH_SWIB
13580 UINT64_C(25165835), // TH_SYNC
13581 UINT64_C(27262987), // TH_SYNC_I
13582 UINT64_C(28311563), // TH_SYNC_IS
13583 UINT64_C(26214411), // TH_SYNC_S
13584 UINT64_C(2281705483), // TH_TST
13585 UINT64_C(2147487755), // TH_TSTNBZ
13586 UINT64_C(2415943691), // TH_VMAQASU_VV
13587 UINT64_C(2483052555), // TH_VMAQASU_VX
13588 UINT64_C(2617270283), // TH_VMAQAUS_VX
13589 UINT64_C(2281725963), // TH_VMAQAU_VV
13590 UINT64_C(2348834827), // TH_VMAQAU_VX
13591 UINT64_C(2147508235), // TH_VMAQA_VV
13592 UINT64_C(2214617099), // TH_VMAQA_VX
13593 UINT64_C(3221229683), // UNIMP
13594 UINT64_C(149966867), // UNZIP_RV32
13595 UINT64_C(536879191), // VAADDU_VV
13596 UINT64_C(536895575), // VAADDU_VX
13597 UINT64_C(603988055), // VAADD_VV
13598 UINT64_C(604004439), // VAADD_VX
13599 UINT64_C(1073754199), // VADC_VIM
13600 UINT64_C(1073741911), // VADC_VVM
13601 UINT64_C(1073758295), // VADC_VXM
13602 UINT64_C(12375), // VADD_VI
13603 UINT64_C(87), // VADD_VV
13604 UINT64_C(16471), // VADD_VX
13605 UINT64_C(2785058935), // VAESDF_VS
13606 UINT64_C(2717950071), // VAESDF_VV
13607 UINT64_C(2785026167), // VAESDM_VS
13608 UINT64_C(2717917303), // VAESDM_VV
13609 UINT64_C(2785124471), // VAESEF_VS
13610 UINT64_C(2718015607), // VAESEF_VV
13611 UINT64_C(2785091703), // VAESEM_VS
13612 UINT64_C(2717982839), // VAESEM_VV
13613 UINT64_C(2315264119), // VAESKF1_VI
13614 UINT64_C(2852135031), // VAESKF2_VI
13615 UINT64_C(2785255543), // VAESZ_VS
13616 UINT64_C(67108951), // VANDN_VV
13617 UINT64_C(67125335), // VANDN_VX
13618 UINT64_C(603992151), // VAND_VI
13619 UINT64_C(603979863), // VAND_VV
13620 UINT64_C(603996247), // VAND_VX
13621 UINT64_C(671096919), // VASUBU_VV
13622 UINT64_C(671113303), // VASUBU_VX
13623 UINT64_C(738205783), // VASUB_VV
13624 UINT64_C(738222167), // VASUB_VX
13625 UINT64_C(1208229975), // VBREV8_V
13626 UINT64_C(1208295511), // VBREV_V
13627 UINT64_C(872423511), // VCLMULH_VV
13628 UINT64_C(872439895), // VCLMULH_VX
13629 UINT64_C(805314647), // VCLMUL_VV
13630 UINT64_C(805331031), // VCLMUL_VX
13631 UINT64_C(1208361047), // VCLZ_V
13632 UINT64_C(1577066583), // VCOMPRESS_VM
13633 UINT64_C(1074274391), // VCPOP_M
13634 UINT64_C(1208426583), // VCPOP_V
13635 UINT64_C(1208393815), // VCTZ_V
13636 UINT64_C(2147491927), // VDIVU_VV
13637 UINT64_C(2147508311), // VDIVU_VX
13638 UINT64_C(2214600791), // VDIV_VV
13639 UINT64_C(2214617175), // VDIV_VX
13640 UINT64_C(20567), // VFADD_VF
13641 UINT64_C(4183), // VFADD_VV
13642 UINT64_C(1275596887), // VFCLASS_V
13643 UINT64_C(1208029271), // VFCVT_F_XU_V
13644 UINT64_C(1208062039), // VFCVT_F_X_V
13645 UINT64_C(1208160343), // VFCVT_RTZ_XU_F_V
13646 UINT64_C(1208193111), // VFCVT_RTZ_X_F_V
13647 UINT64_C(1207963735), // VFCVT_XU_F_V
13648 UINT64_C(1207996503), // VFCVT_X_F_V
13649 UINT64_C(2147504215), // VFDIV_VF
13650 UINT64_C(2147487831), // VFDIV_VV
13651 UINT64_C(1074307159), // VFIRST_M
13652 UINT64_C(2952810583), // VFMACC_VF
13653 UINT64_C(2952794199), // VFMACC_VV
13654 UINT64_C(2684375127), // VFMADD_VF
13655 UINT64_C(2684358743), // VFMADD_VV
13656 UINT64_C(402673751), // VFMAX_VF
13657 UINT64_C(402657367), // VFMAX_VV
13658 UINT64_C(1543524439), // VFMERGE_VFM
13659 UINT64_C(268456023), // VFMIN_VF
13660 UINT64_C(268439639), // VFMIN_VV
13661 UINT64_C(3087028311), // VFMSAC_VF
13662 UINT64_C(3087011927), // VFMSAC_VV
13663 UINT64_C(2818592855), // VFMSUB_VF
13664 UINT64_C(2818576471), // VFMSUB_VV
13665 UINT64_C(2415939671), // VFMUL_VF
13666 UINT64_C(2415923287), // VFMUL_VV
13667 UINT64_C(1107300439), // VFMV_F_S
13668 UINT64_C(1107316823), // VFMV_S_F
13669 UINT64_C(1577078871), // VFMV_V_F
13670 UINT64_C(1208914007), // VFNCVTBF16_F_F_W
13671 UINT64_C(1208619095), // VFNCVT_F_F_W
13672 UINT64_C(1208553559), // VFNCVT_F_XU_W
13673 UINT64_C(1208586327), // VFNCVT_F_X_W
13674 UINT64_C(1208651863), // VFNCVT_ROD_F_F_W
13675 UINT64_C(1208684631), // VFNCVT_RTZ_XU_F_W
13676 UINT64_C(1208717399), // VFNCVT_RTZ_X_F_W
13677 UINT64_C(1208488023), // VFNCVT_XU_F_W
13678 UINT64_C(1208520791), // VFNCVT_X_F_W
13679 UINT64_C(3019919447), // VFNMACC_VF
13680 UINT64_C(3019903063), // VFNMACC_VV
13681 UINT64_C(2751483991), // VFNMADD_VF
13682 UINT64_C(2751467607), // VFNMADD_VV
13683 UINT64_C(3154137175), // VFNMSAC_VF
13684 UINT64_C(3154120791), // VFNMSAC_VV
13685 UINT64_C(2885701719), // VFNMSUB_VF
13686 UINT64_C(2885685335), // VFNMSUB_VV
13687 UINT64_C(2214613079), // VFRDIV_VF
13688 UINT64_C(1275236439), // VFREC7_V
13689 UINT64_C(469766231), // VFREDMAX_VS
13690 UINT64_C(335548503), // VFREDMIN_VS
13691 UINT64_C(201330775), // VFREDOSUM_VS
13692 UINT64_C(67113047), // VFREDUSUM_VS
13693 UINT64_C(1275203671), // VFRSQRT7_V
13694 UINT64_C(2617266263), // VFRSUB_VF
13695 UINT64_C(604000343), // VFSGNJN_VF
13696 UINT64_C(603983959), // VFSGNJN_VV
13697 UINT64_C(671109207), // VFSGNJX_VF
13698 UINT64_C(671092823), // VFSGNJX_VV
13699 UINT64_C(536891479), // VFSGNJ_VF
13700 UINT64_C(536875095), // VFSGNJ_VV
13701 UINT64_C(1006653527), // VFSLIDE1DOWN_VF
13702 UINT64_C(939544663), // VFSLIDE1UP_VF
13703 UINT64_C(1275072599), // VFSQRT_V
13704 UINT64_C(134238295), // VFSUB_VF
13705 UINT64_C(134221911), // VFSUB_VV
13706 UINT64_C(3221246039), // VFWADD_VF
13707 UINT64_C(3221229655), // VFWADD_VV
13708 UINT64_C(3489681495), // VFWADD_WF
13709 UINT64_C(3489665111), // VFWADD_WV
13710 UINT64_C(1208389719), // VFWCVTBF16_F_F_V
13711 UINT64_C(1208356951), // VFWCVT_F_F_V
13712 UINT64_C(1208291415), // VFWCVT_F_XU_V
13713 UINT64_C(1208324183), // VFWCVT_F_X_V
13714 UINT64_C(1208422487), // VFWCVT_RTZ_XU_F_V
13715 UINT64_C(1208455255), // VFWCVT_RTZ_X_F_V
13716 UINT64_C(1208225879), // VFWCVT_XU_F_V
13717 UINT64_C(1208258647), // VFWCVT_X_F_V
13718 UINT64_C(3959443543), // VFWMACCBF16_VF
13719 UINT64_C(3959427159), // VFWMACCBF16_VV
13720 UINT64_C(4026552407), // VFWMACC_VF
13721 UINT64_C(4026536023), // VFWMACC_VV
13722 UINT64_C(4160770135), // VFWMSAC_VF
13723 UINT64_C(4160753751), // VFWMSAC_VV
13724 UINT64_C(3758116951), // VFWMUL_VF
13725 UINT64_C(3758100567), // VFWMUL_VV
13726 UINT64_C(4093661271), // VFWNMACC_VF
13727 UINT64_C(4093644887), // VFWNMACC_VV
13728 UINT64_C(4227878999), // VFWNMSAC_VF
13729 UINT64_C(4227862615), // VFWNMSAC_VV
13730 UINT64_C(3422556247), // VFWREDOSUM_VS
13731 UINT64_C(3288338519), // VFWREDUSUM_VS
13732 UINT64_C(3355463767), // VFWSUB_VF
13733 UINT64_C(3355447383), // VFWSUB_VV
13734 UINT64_C(3623899223), // VFWSUB_WF
13735 UINT64_C(3623882839), // VFWSUB_WV
13736 UINT64_C(2382372983), // VGHSH_VS
13737 UINT64_C(2986352759), // VGHSH_VV
13738 UINT64_C(2785583223), // VGMUL_VS
13739 UINT64_C(2718474359), // VGMUL_VV
13740 UINT64_C(1342742615), // VID_V
13741 UINT64_C(1342709847), // VIOTA_M
13742 UINT64_C(41963527), // VL1RE16_V
13743 UINT64_C(41967623), // VL1RE32_V
13744 UINT64_C(41971719), // VL1RE64_V
13745 UINT64_C(41943047), // VL1RE8_V
13746 UINT64_C(578834439), // VL2RE16_V
13747 UINT64_C(578838535), // VL2RE32_V
13748 UINT64_C(578842631), // VL2RE64_V
13749 UINT64_C(578813959), // VL2RE8_V
13750 UINT64_C(1652576263), // VL4RE16_V
13751 UINT64_C(1652580359), // VL4RE32_V
13752 UINT64_C(1652584455), // VL4RE64_V
13753 UINT64_C(1652555783), // VL4RE8_V
13754 UINT64_C(3800059911), // VL8RE16_V
13755 UINT64_C(3800064007), // VL8RE32_V
13756 UINT64_C(3800068103), // VL8RE64_V
13757 UINT64_C(3800039431), // VL8RE8_V
13758 UINT64_C(16797703), // VLE16FF_V
13759 UINT64_C(20487), // VLE16_V
13760 UINT64_C(16801799), // VLE32FF_V
13761 UINT64_C(24583), // VLE32_V
13762 UINT64_C(16805895), // VLE64FF_V
13763 UINT64_C(28679), // VLE64_V
13764 UINT64_C(16777223), // VLE8FF_V
13765 UINT64_C(7), // VLE8_V
13766 UINT64_C(45088775), // VLM_V
13767 UINT64_C(201347079), // VLOXEI16_V
13768 UINT64_C(201351175), // VLOXEI32_V
13769 UINT64_C(201355271), // VLOXEI64_V
13770 UINT64_C(201326599), // VLOXEI8_V
13771 UINT64_C(738217991), // VLOXSEG2EI16_V
13772 UINT64_C(738222087), // VLOXSEG2EI32_V
13773 UINT64_C(738226183), // VLOXSEG2EI64_V
13774 UINT64_C(738197511), // VLOXSEG2EI8_V
13775 UINT64_C(1275088903), // VLOXSEG3EI16_V
13776 UINT64_C(1275092999), // VLOXSEG3EI32_V
13777 UINT64_C(1275097095), // VLOXSEG3EI64_V
13778 UINT64_C(1275068423), // VLOXSEG3EI8_V
13779 UINT64_C(1811959815), // VLOXSEG4EI16_V
13780 UINT64_C(1811963911), // VLOXSEG4EI32_V
13781 UINT64_C(1811968007), // VLOXSEG4EI64_V
13782 UINT64_C(1811939335), // VLOXSEG4EI8_V
13783 UINT64_C(2348830727), // VLOXSEG5EI16_V
13784 UINT64_C(2348834823), // VLOXSEG5EI32_V
13785 UINT64_C(2348838919), // VLOXSEG5EI64_V
13786 UINT64_C(2348810247), // VLOXSEG5EI8_V
13787 UINT64_C(2885701639), // VLOXSEG6EI16_V
13788 UINT64_C(2885705735), // VLOXSEG6EI32_V
13789 UINT64_C(2885709831), // VLOXSEG6EI64_V
13790 UINT64_C(2885681159), // VLOXSEG6EI8_V
13791 UINT64_C(3422572551), // VLOXSEG7EI16_V
13792 UINT64_C(3422576647), // VLOXSEG7EI32_V
13793 UINT64_C(3422580743), // VLOXSEG7EI64_V
13794 UINT64_C(3422552071), // VLOXSEG7EI8_V
13795 UINT64_C(3959443463), // VLOXSEG8EI16_V
13796 UINT64_C(3959447559), // VLOXSEG8EI32_V
13797 UINT64_C(3959451655), // VLOXSEG8EI64_V
13798 UINT64_C(3959422983), // VLOXSEG8EI8_V
13799 UINT64_C(134238215), // VLSE16_V
13800 UINT64_C(134242311), // VLSE32_V
13801 UINT64_C(134246407), // VLSE64_V
13802 UINT64_C(134217735), // VLSE8_V
13803 UINT64_C(553668615), // VLSEG2E16FF_V
13804 UINT64_C(536891399), // VLSEG2E16_V
13805 UINT64_C(553672711), // VLSEG2E32FF_V
13806 UINT64_C(536895495), // VLSEG2E32_V
13807 UINT64_C(553676807), // VLSEG2E64FF_V
13808 UINT64_C(536899591), // VLSEG2E64_V
13809 UINT64_C(553648135), // VLSEG2E8FF_V
13810 UINT64_C(536870919), // VLSEG2E8_V
13811 UINT64_C(1090539527), // VLSEG3E16FF_V
13812 UINT64_C(1073762311), // VLSEG3E16_V
13813 UINT64_C(1090543623), // VLSEG3E32FF_V
13814 UINT64_C(1073766407), // VLSEG3E32_V
13815 UINT64_C(1090547719), // VLSEG3E64FF_V
13816 UINT64_C(1073770503), // VLSEG3E64_V
13817 UINT64_C(1090519047), // VLSEG3E8FF_V
13818 UINT64_C(1073741831), // VLSEG3E8_V
13819 UINT64_C(1627410439), // VLSEG4E16FF_V
13820 UINT64_C(1610633223), // VLSEG4E16_V
13821 UINT64_C(1627414535), // VLSEG4E32FF_V
13822 UINT64_C(1610637319), // VLSEG4E32_V
13823 UINT64_C(1627418631), // VLSEG4E64FF_V
13824 UINT64_C(1610641415), // VLSEG4E64_V
13825 UINT64_C(1627389959), // VLSEG4E8FF_V
13826 UINT64_C(1610612743), // VLSEG4E8_V
13827 UINT64_C(2164281351), // VLSEG5E16FF_V
13828 UINT64_C(2147504135), // VLSEG5E16_V
13829 UINT64_C(2164285447), // VLSEG5E32FF_V
13830 UINT64_C(2147508231), // VLSEG5E32_V
13831 UINT64_C(2164289543), // VLSEG5E64FF_V
13832 UINT64_C(2147512327), // VLSEG5E64_V
13833 UINT64_C(2164260871), // VLSEG5E8FF_V
13834 UINT64_C(2147483655), // VLSEG5E8_V
13835 UINT64_C(2701152263), // VLSEG6E16FF_V
13836 UINT64_C(2684375047), // VLSEG6E16_V
13837 UINT64_C(2701156359), // VLSEG6E32FF_V
13838 UINT64_C(2684379143), // VLSEG6E32_V
13839 UINT64_C(2701160455), // VLSEG6E64FF_V
13840 UINT64_C(2684383239), // VLSEG6E64_V
13841 UINT64_C(2701131783), // VLSEG6E8FF_V
13842 UINT64_C(2684354567), // VLSEG6E8_V
13843 UINT64_C(3238023175), // VLSEG7E16FF_V
13844 UINT64_C(3221245959), // VLSEG7E16_V
13845 UINT64_C(3238027271), // VLSEG7E32FF_V
13846 UINT64_C(3221250055), // VLSEG7E32_V
13847 UINT64_C(3238031367), // VLSEG7E64FF_V
13848 UINT64_C(3221254151), // VLSEG7E64_V
13849 UINT64_C(3238002695), // VLSEG7E8FF_V
13850 UINT64_C(3221225479), // VLSEG7E8_V
13851 UINT64_C(3774894087), // VLSEG8E16FF_V
13852 UINT64_C(3758116871), // VLSEG8E16_V
13853 UINT64_C(3774898183), // VLSEG8E32FF_V
13854 UINT64_C(3758120967), // VLSEG8E32_V
13855 UINT64_C(3774902279), // VLSEG8E64FF_V
13856 UINT64_C(3758125063), // VLSEG8E64_V
13857 UINT64_C(3774873607), // VLSEG8E8FF_V
13858 UINT64_C(3758096391), // VLSEG8E8_V
13859 UINT64_C(671109127), // VLSSEG2E16_V
13860 UINT64_C(671113223), // VLSSEG2E32_V
13861 UINT64_C(671117319), // VLSSEG2E64_V
13862 UINT64_C(671088647), // VLSSEG2E8_V
13863 UINT64_C(1207980039), // VLSSEG3E16_V
13864 UINT64_C(1207984135), // VLSSEG3E32_V
13865 UINT64_C(1207988231), // VLSSEG3E64_V
13866 UINT64_C(1207959559), // VLSSEG3E8_V
13867 UINT64_C(1744850951), // VLSSEG4E16_V
13868 UINT64_C(1744855047), // VLSSEG4E32_V
13869 UINT64_C(1744859143), // VLSSEG4E64_V
13870 UINT64_C(1744830471), // VLSSEG4E8_V
13871 UINT64_C(2281721863), // VLSSEG5E16_V
13872 UINT64_C(2281725959), // VLSSEG5E32_V
13873 UINT64_C(2281730055), // VLSSEG5E64_V
13874 UINT64_C(2281701383), // VLSSEG5E8_V
13875 UINT64_C(2818592775), // VLSSEG6E16_V
13876 UINT64_C(2818596871), // VLSSEG6E32_V
13877 UINT64_C(2818600967), // VLSSEG6E64_V
13878 UINT64_C(2818572295), // VLSSEG6E8_V
13879 UINT64_C(3355463687), // VLSSEG7E16_V
13880 UINT64_C(3355467783), // VLSSEG7E32_V
13881 UINT64_C(3355471879), // VLSSEG7E64_V
13882 UINT64_C(3355443207), // VLSSEG7E8_V
13883 UINT64_C(3892334599), // VLSSEG8E16_V
13884 UINT64_C(3892338695), // VLSSEG8E32_V
13885 UINT64_C(3892342791), // VLSSEG8E64_V
13886 UINT64_C(3892314119), // VLSSEG8E8_V
13887 UINT64_C(67129351), // VLUXEI16_V
13888 UINT64_C(67133447), // VLUXEI32_V
13889 UINT64_C(67137543), // VLUXEI64_V
13890 UINT64_C(67108871), // VLUXEI8_V
13891 UINT64_C(604000263), // VLUXSEG2EI16_V
13892 UINT64_C(604004359), // VLUXSEG2EI32_V
13893 UINT64_C(604008455), // VLUXSEG2EI64_V
13894 UINT64_C(603979783), // VLUXSEG2EI8_V
13895 UINT64_C(1140871175), // VLUXSEG3EI16_V
13896 UINT64_C(1140875271), // VLUXSEG3EI32_V
13897 UINT64_C(1140879367), // VLUXSEG3EI64_V
13898 UINT64_C(1140850695), // VLUXSEG3EI8_V
13899 UINT64_C(1677742087), // VLUXSEG4EI16_V
13900 UINT64_C(1677746183), // VLUXSEG4EI32_V
13901 UINT64_C(1677750279), // VLUXSEG4EI64_V
13902 UINT64_C(1677721607), // VLUXSEG4EI8_V
13903 UINT64_C(2214612999), // VLUXSEG5EI16_V
13904 UINT64_C(2214617095), // VLUXSEG5EI32_V
13905 UINT64_C(2214621191), // VLUXSEG5EI64_V
13906 UINT64_C(2214592519), // VLUXSEG5EI8_V
13907 UINT64_C(2751483911), // VLUXSEG6EI16_V
13908 UINT64_C(2751488007), // VLUXSEG6EI32_V
13909 UINT64_C(2751492103), // VLUXSEG6EI64_V
13910 UINT64_C(2751463431), // VLUXSEG6EI8_V
13911 UINT64_C(3288354823), // VLUXSEG7EI16_V
13912 UINT64_C(3288358919), // VLUXSEG7EI32_V
13913 UINT64_C(3288363015), // VLUXSEG7EI64_V
13914 UINT64_C(3288334343), // VLUXSEG7EI8_V
13915 UINT64_C(3825225735), // VLUXSEG8EI16_V
13916 UINT64_C(3825229831), // VLUXSEG8EI32_V
13917 UINT64_C(3825233927), // VLUXSEG8EI64_V
13918 UINT64_C(3825205255), // VLUXSEG8EI8_V
13919 UINT64_C(3019907159), // VMACC_VV
13920 UINT64_C(3019923543), // VMACC_VX
13921 UINT64_C(1174417495), // VMADC_VI
13922 UINT64_C(1140863063), // VMADC_VIM
13923 UINT64_C(1174405207), // VMADC_VV
13924 UINT64_C(1140850775), // VMADC_VVM
13925 UINT64_C(1174421591), // VMADC_VX
13926 UINT64_C(1140867159), // VMADC_VXM
13927 UINT64_C(2751471703), // VMADD_VV
13928 UINT64_C(2751488087), // VMADD_VX
13929 UINT64_C(1644175447), // VMANDN_MM
13930 UINT64_C(1711284311), // VMAND_MM
13931 UINT64_C(402653271), // VMAXU_VV
13932 UINT64_C(402669655), // VMAXU_VX
13933 UINT64_C(469762135), // VMAX_VV
13934 UINT64_C(469778519), // VMAX_VX
13935 UINT64_C(1543516247), // VMERGE_VIM
13936 UINT64_C(1543503959), // VMERGE_VVM
13937 UINT64_C(1543520343), // VMERGE_VXM
13938 UINT64_C(1610633303), // VMFEQ_VF
13939 UINT64_C(1610616919), // VMFEQ_VV
13940 UINT64_C(2080395351), // VMFGE_VF
13941 UINT64_C(1946177623), // VMFGT_VF
13942 UINT64_C(1677742167), // VMFLE_VF
13943 UINT64_C(1677725783), // VMFLE_VV
13944 UINT64_C(1811959895), // VMFLT_VF
13945 UINT64_C(1811943511), // VMFLT_VV
13946 UINT64_C(1879068759), // VMFNE_VF
13947 UINT64_C(1879052375), // VMFNE_VV
13948 UINT64_C(268435543), // VMINU_VV
13949 UINT64_C(268451927), // VMINU_VX
13950 UINT64_C(335544407), // VMIN_VV
13951 UINT64_C(335560791), // VMIN_VX
13952 UINT64_C(1979719767), // VMNAND_MM
13953 UINT64_C(2046828631), // VMNOR_MM
13954 UINT64_C(1912610903), // VMORN_MM
13955 UINT64_C(1778393175), // VMOR_MM
13956 UINT64_C(1308622935), // VMSBC_VV
13957 UINT64_C(1275068503), // VMSBC_VVM
13958 UINT64_C(1308639319), // VMSBC_VX
13959 UINT64_C(1275084887), // VMSBC_VXM
13960 UINT64_C(1342218327), // VMSBF_M
13961 UINT64_C(1610625111), // VMSEQ_VI
13962 UINT64_C(1610612823), // VMSEQ_VV
13963 UINT64_C(1610629207), // VMSEQ_VX
13964 UINT64_C(2013278295), // VMSGTU_VI
13965 UINT64_C(2013282391), // VMSGTU_VX
13966 UINT64_C(2080387159), // VMSGT_VI
13967 UINT64_C(2080391255), // VMSGT_VX
13968 UINT64_C(1342283863), // VMSIF_M
13969 UINT64_C(1879060567), // VMSLEU_VI
13970 UINT64_C(1879048279), // VMSLEU_VV
13971 UINT64_C(1879064663), // VMSLEU_VX
13972 UINT64_C(1946169431), // VMSLE_VI
13973 UINT64_C(1946157143), // VMSLE_VV
13974 UINT64_C(1946173527), // VMSLE_VX
13975 UINT64_C(1744830551), // VMSLTU_VV
13976 UINT64_C(1744846935), // VMSLTU_VX
13977 UINT64_C(1811939415), // VMSLT_VV
13978 UINT64_C(1811955799), // VMSLT_VX
13979 UINT64_C(1677733975), // VMSNE_VI
13980 UINT64_C(1677721687), // VMSNE_VV
13981 UINT64_C(1677738071), // VMSNE_VX
13982 UINT64_C(1342251095), // VMSOF_M
13983 UINT64_C(2550145111), // VMULHSU_VV
13984 UINT64_C(2550161495), // VMULHSU_VX
13985 UINT64_C(2415927383), // VMULHU_VV
13986 UINT64_C(2415943767), // VMULHU_VX
13987 UINT64_C(2617253975), // VMULH_VV
13988 UINT64_C(2617270359), // VMULH_VX
13989 UINT64_C(2483036247), // VMUL_VV
13990 UINT64_C(2483052631), // VMUL_VX
13991 UINT64_C(2650812503), // VMV1R_V
13992 UINT64_C(2650845271), // VMV2R_V
13993 UINT64_C(2650910807), // VMV4R_V
13994 UINT64_C(2651041879), // VMV8R_V
13995 UINT64_C(1107320919), // VMV_S_X
13996 UINT64_C(1577070679), // VMV_V_I
13997 UINT64_C(1577058391), // VMV_V_V
13998 UINT64_C(1577074775), // VMV_V_X
13999 UINT64_C(1107304535), // VMV_X_S
14000 UINT64_C(2113937495), // VMXNOR_MM
14001 UINT64_C(1845502039), // VMXOR_MM
14002 UINT64_C(3087020119), // VNCLIPU_WI
14003 UINT64_C(3087007831), // VNCLIPU_WV
14004 UINT64_C(3087024215), // VNCLIPU_WX
14005 UINT64_C(3154128983), // VNCLIP_WI
14006 UINT64_C(3154116695), // VNCLIP_WV
14007 UINT64_C(3154133079), // VNCLIP_WX
14008 UINT64_C(3154124887), // VNMSAC_VV
14009 UINT64_C(3154141271), // VNMSAC_VX
14010 UINT64_C(2885689431), // VNMSUB_VV
14011 UINT64_C(2885705815), // VNMSUB_VX
14012 UINT64_C(3019911255), // VNSRA_WI
14013 UINT64_C(3019898967), // VNSRA_WV
14014 UINT64_C(3019915351), // VNSRA_WX
14015 UINT64_C(2952802391), // VNSRL_WI
14016 UINT64_C(2952790103), // VNSRL_WV
14017 UINT64_C(2952806487), // VNSRL_WX
14018 UINT64_C(671101015), // VOR_VI
14019 UINT64_C(671088727), // VOR_VV
14020 UINT64_C(671105111), // VOR_VX
14021 UINT64_C(2818580567), // VQDOTSU_VV
14022 UINT64_C(2818596951), // VQDOTSU_VX
14023 UINT64_C(3087032407), // VQDOTUS_VX
14024 UINT64_C(2684362839), // VQDOTU_VV
14025 UINT64_C(2684379223), // VQDOTU_VX
14026 UINT64_C(2952798295), // VQDOT_VV
14027 UINT64_C(2952814679), // VQDOT_VX
14028 UINT64_C(67117143), // VREDAND_VS
14029 UINT64_C(402661463), // VREDMAXU_VS
14030 UINT64_C(469770327), // VREDMAX_VS
14031 UINT64_C(268443735), // VREDMINU_VS
14032 UINT64_C(335552599), // VREDMIN_VS
14033 UINT64_C(134226007), // VREDOR_VS
14034 UINT64_C(8279), // VREDSUM_VS
14035 UINT64_C(201334871), // VREDXOR_VS
14036 UINT64_C(2281709655), // VREMU_VV
14037 UINT64_C(2281726039), // VREMU_VX
14038 UINT64_C(2348818519), // VREM_VV
14039 UINT64_C(2348834903), // VREM_VX
14040 UINT64_C(1208262743), // VREV8_V
14041 UINT64_C(939524183), // VRGATHEREI16_VV
14042 UINT64_C(805318743), // VRGATHER_VI
14043 UINT64_C(805306455), // VRGATHER_VV
14044 UINT64_C(805322839), // VRGATHER_VX
14045 UINT64_C(1409286231), // VROL_VV
14046 UINT64_C(1409302615), // VROL_VX
14047 UINT64_C(1342189655), // VROR_VI
14048 UINT64_C(1342177367), // VROR_VV
14049 UINT64_C(1342193751), // VROR_VX
14050 UINT64_C(201338967), // VRSUB_VI
14051 UINT64_C(201343063), // VRSUB_VX
14052 UINT64_C(41943079), // VS1R_V
14053 UINT64_C(578813991), // VS2R_V
14054 UINT64_C(1652555815), // VS4R_V
14055 UINT64_C(3800039463), // VS8R_V
14056 UINT64_C(2147496023), // VSADDU_VI
14057 UINT64_C(2147483735), // VSADDU_VV
14058 UINT64_C(2147500119), // VSADDU_VX
14059 UINT64_C(2214604887), // VSADD_VI
14060 UINT64_C(2214592599), // VSADD_VV
14061 UINT64_C(2214608983), // VSADD_VX
14062 UINT64_C(1207959639), // VSBC_VVM
14063 UINT64_C(1207976023), // VSBC_VXM
14064 UINT64_C(20519), // VSE16_V
14065 UINT64_C(24615), // VSE32_V
14066 UINT64_C(28711), // VSE64_V
14067 UINT64_C(39), // VSE8_V
14068 UINT64_C(3221254231), // VSETIVLI
14069 UINT64_C(2147512407), // VSETVL
14070 UINT64_C(28759), // VSETVLI
14071 UINT64_C(1208197207), // VSEXT_VF2
14072 UINT64_C(1208131671), // VSEXT_VF4
14073 UINT64_C(1208066135), // VSEXT_VF8
14074 UINT64_C(3120570487), // VSHA2CH_VV
14075 UINT64_C(3187679351), // VSHA2CL_VV
14076 UINT64_C(3053461623), // VSHA2MS_VV
14077 UINT64_C(1006657623), // VSLIDE1DOWN_VX
14078 UINT64_C(939548759), // VSLIDE1UP_VX
14079 UINT64_C(1006645335), // VSLIDEDOWN_VI
14080 UINT64_C(1006649431), // VSLIDEDOWN_VX
14081 UINT64_C(939536471), // VSLIDEUP_VI
14082 UINT64_C(939540567), // VSLIDEUP_VX
14083 UINT64_C(2483040343), // VSLL_VI
14084 UINT64_C(2483028055), // VSLL_VV
14085 UINT64_C(2483044439), // VSLL_VX
14086 UINT64_C(2919243895), // VSM3C_VI
14087 UINT64_C(2181046391), // VSM3ME_VV
14088 UINT64_C(2248155255), // VSM4K_VI
14089 UINT64_C(2785550455), // VSM4R_VS
14090 UINT64_C(2718441591), // VSM4R_VV
14091 UINT64_C(2617245783), // VSMUL_VV
14092 UINT64_C(2617262167), // VSMUL_VX
14093 UINT64_C(45088807), // VSM_V
14094 UINT64_C(201347111), // VSOXEI16_V
14095 UINT64_C(201351207), // VSOXEI32_V
14096 UINT64_C(201355303), // VSOXEI64_V
14097 UINT64_C(201326631), // VSOXEI8_V
14098 UINT64_C(738218023), // VSOXSEG2EI16_V
14099 UINT64_C(738222119), // VSOXSEG2EI32_V
14100 UINT64_C(738226215), // VSOXSEG2EI64_V
14101 UINT64_C(738197543), // VSOXSEG2EI8_V
14102 UINT64_C(1275088935), // VSOXSEG3EI16_V
14103 UINT64_C(1275093031), // VSOXSEG3EI32_V
14104 UINT64_C(1275097127), // VSOXSEG3EI64_V
14105 UINT64_C(1275068455), // VSOXSEG3EI8_V
14106 UINT64_C(1811959847), // VSOXSEG4EI16_V
14107 UINT64_C(1811963943), // VSOXSEG4EI32_V
14108 UINT64_C(1811968039), // VSOXSEG4EI64_V
14109 UINT64_C(1811939367), // VSOXSEG4EI8_V
14110 UINT64_C(2348830759), // VSOXSEG5EI16_V
14111 UINT64_C(2348834855), // VSOXSEG5EI32_V
14112 UINT64_C(2348838951), // VSOXSEG5EI64_V
14113 UINT64_C(2348810279), // VSOXSEG5EI8_V
14114 UINT64_C(2885701671), // VSOXSEG6EI16_V
14115 UINT64_C(2885705767), // VSOXSEG6EI32_V
14116 UINT64_C(2885709863), // VSOXSEG6EI64_V
14117 UINT64_C(2885681191), // VSOXSEG6EI8_V
14118 UINT64_C(3422572583), // VSOXSEG7EI16_V
14119 UINT64_C(3422576679), // VSOXSEG7EI32_V
14120 UINT64_C(3422580775), // VSOXSEG7EI64_V
14121 UINT64_C(3422552103), // VSOXSEG7EI8_V
14122 UINT64_C(3959443495), // VSOXSEG8EI16_V
14123 UINT64_C(3959447591), // VSOXSEG8EI32_V
14124 UINT64_C(3959451687), // VSOXSEG8EI64_V
14125 UINT64_C(3959423015), // VSOXSEG8EI8_V
14126 UINT64_C(2751475799), // VSRA_VI
14127 UINT64_C(2751463511), // VSRA_VV
14128 UINT64_C(2751479895), // VSRA_VX
14129 UINT64_C(2684366935), // VSRL_VI
14130 UINT64_C(2684354647), // VSRL_VV
14131 UINT64_C(2684371031), // VSRL_VX
14132 UINT64_C(134238247), // VSSE16_V
14133 UINT64_C(134242343), // VSSE32_V
14134 UINT64_C(134246439), // VSSE64_V
14135 UINT64_C(134217767), // VSSE8_V
14136 UINT64_C(536891431), // VSSEG2E16_V
14137 UINT64_C(536895527), // VSSEG2E32_V
14138 UINT64_C(536899623), // VSSEG2E64_V
14139 UINT64_C(536870951), // VSSEG2E8_V
14140 UINT64_C(1073762343), // VSSEG3E16_V
14141 UINT64_C(1073766439), // VSSEG3E32_V
14142 UINT64_C(1073770535), // VSSEG3E64_V
14143 UINT64_C(1073741863), // VSSEG3E8_V
14144 UINT64_C(1610633255), // VSSEG4E16_V
14145 UINT64_C(1610637351), // VSSEG4E32_V
14146 UINT64_C(1610641447), // VSSEG4E64_V
14147 UINT64_C(1610612775), // VSSEG4E8_V
14148 UINT64_C(2147504167), // VSSEG5E16_V
14149 UINT64_C(2147508263), // VSSEG5E32_V
14150 UINT64_C(2147512359), // VSSEG5E64_V
14151 UINT64_C(2147483687), // VSSEG5E8_V
14152 UINT64_C(2684375079), // VSSEG6E16_V
14153 UINT64_C(2684379175), // VSSEG6E32_V
14154 UINT64_C(2684383271), // VSSEG6E64_V
14155 UINT64_C(2684354599), // VSSEG6E8_V
14156 UINT64_C(3221245991), // VSSEG7E16_V
14157 UINT64_C(3221250087), // VSSEG7E32_V
14158 UINT64_C(3221254183), // VSSEG7E64_V
14159 UINT64_C(3221225511), // VSSEG7E8_V
14160 UINT64_C(3758116903), // VSSEG8E16_V
14161 UINT64_C(3758120999), // VSSEG8E32_V
14162 UINT64_C(3758125095), // VSSEG8E64_V
14163 UINT64_C(3758096423), // VSSEG8E8_V
14164 UINT64_C(2885693527), // VSSRA_VI
14165 UINT64_C(2885681239), // VSSRA_VV
14166 UINT64_C(2885697623), // VSSRA_VX
14167 UINT64_C(2818584663), // VSSRL_VI
14168 UINT64_C(2818572375), // VSSRL_VV
14169 UINT64_C(2818588759), // VSSRL_VX
14170 UINT64_C(671109159), // VSSSEG2E16_V
14171 UINT64_C(671113255), // VSSSEG2E32_V
14172 UINT64_C(671117351), // VSSSEG2E64_V
14173 UINT64_C(671088679), // VSSSEG2E8_V
14174 UINT64_C(1207980071), // VSSSEG3E16_V
14175 UINT64_C(1207984167), // VSSSEG3E32_V
14176 UINT64_C(1207988263), // VSSSEG3E64_V
14177 UINT64_C(1207959591), // VSSSEG3E8_V
14178 UINT64_C(1744850983), // VSSSEG4E16_V
14179 UINT64_C(1744855079), // VSSSEG4E32_V
14180 UINT64_C(1744859175), // VSSSEG4E64_V
14181 UINT64_C(1744830503), // VSSSEG4E8_V
14182 UINT64_C(2281721895), // VSSSEG5E16_V
14183 UINT64_C(2281725991), // VSSSEG5E32_V
14184 UINT64_C(2281730087), // VSSSEG5E64_V
14185 UINT64_C(2281701415), // VSSSEG5E8_V
14186 UINT64_C(2818592807), // VSSSEG6E16_V
14187 UINT64_C(2818596903), // VSSSEG6E32_V
14188 UINT64_C(2818600999), // VSSSEG6E64_V
14189 UINT64_C(2818572327), // VSSSEG6E8_V
14190 UINT64_C(3355463719), // VSSSEG7E16_V
14191 UINT64_C(3355467815), // VSSSEG7E32_V
14192 UINT64_C(3355471911), // VSSSEG7E64_V
14193 UINT64_C(3355443239), // VSSSEG7E8_V
14194 UINT64_C(3892334631), // VSSSEG8E16_V
14195 UINT64_C(3892338727), // VSSSEG8E32_V
14196 UINT64_C(3892342823), // VSSSEG8E64_V
14197 UINT64_C(3892314151), // VSSSEG8E8_V
14198 UINT64_C(2281701463), // VSSUBU_VV
14199 UINT64_C(2281717847), // VSSUBU_VX
14200 UINT64_C(2348810327), // VSSUB_VV
14201 UINT64_C(2348826711), // VSSUB_VX
14202 UINT64_C(134217815), // VSUB_VV
14203 UINT64_C(134234199), // VSUB_VX
14204 UINT64_C(67129383), // VSUXEI16_V
14205 UINT64_C(67133479), // VSUXEI32_V
14206 UINT64_C(67137575), // VSUXEI64_V
14207 UINT64_C(67108903), // VSUXEI8_V
14208 UINT64_C(604000295), // VSUXSEG2EI16_V
14209 UINT64_C(604004391), // VSUXSEG2EI32_V
14210 UINT64_C(604008487), // VSUXSEG2EI64_V
14211 UINT64_C(603979815), // VSUXSEG2EI8_V
14212 UINT64_C(1140871207), // VSUXSEG3EI16_V
14213 UINT64_C(1140875303), // VSUXSEG3EI32_V
14214 UINT64_C(1140879399), // VSUXSEG3EI64_V
14215 UINT64_C(1140850727), // VSUXSEG3EI8_V
14216 UINT64_C(1677742119), // VSUXSEG4EI16_V
14217 UINT64_C(1677746215), // VSUXSEG4EI32_V
14218 UINT64_C(1677750311), // VSUXSEG4EI64_V
14219 UINT64_C(1677721639), // VSUXSEG4EI8_V
14220 UINT64_C(2214613031), // VSUXSEG5EI16_V
14221 UINT64_C(2214617127), // VSUXSEG5EI32_V
14222 UINT64_C(2214621223), // VSUXSEG5EI64_V
14223 UINT64_C(2214592551), // VSUXSEG5EI8_V
14224 UINT64_C(2751483943), // VSUXSEG6EI16_V
14225 UINT64_C(2751488039), // VSUXSEG6EI32_V
14226 UINT64_C(2751492135), // VSUXSEG6EI64_V
14227 UINT64_C(2751463463), // VSUXSEG6EI8_V
14228 UINT64_C(3288354855), // VSUXSEG7EI16_V
14229 UINT64_C(3288358951), // VSUXSEG7EI32_V
14230 UINT64_C(3288363047), // VSUXSEG7EI64_V
14231 UINT64_C(3288334375), // VSUXSEG7EI8_V
14232 UINT64_C(3825225767), // VSUXSEG8EI16_V
14233 UINT64_C(3825229863), // VSUXSEG8EI32_V
14234 UINT64_C(3825233959), // VSUXSEG8EI64_V
14235 UINT64_C(3825205287), // VSUXSEG8EI8_V
14236 UINT64_C(24699), // VT_MASKC
14237 UINT64_C(28795), // VT_MASKCN
14238 UINT64_C(3221233751), // VWADDU_VV
14239 UINT64_C(3221250135), // VWADDU_VX
14240 UINT64_C(3489669207), // VWADDU_WV
14241 UINT64_C(3489685591), // VWADDU_WX
14242 UINT64_C(3288342615), // VWADD_VV
14243 UINT64_C(3288358999), // VWADD_VX
14244 UINT64_C(3556778071), // VWADD_WV
14245 UINT64_C(3556794455), // VWADD_WX
14246 UINT64_C(4227866711), // VWMACCSU_VV
14247 UINT64_C(4227883095), // VWMACCSU_VX
14248 UINT64_C(4160774231), // VWMACCUS_VX
14249 UINT64_C(4026540119), // VWMACCU_VV
14250 UINT64_C(4026556503), // VWMACCU_VX
14251 UINT64_C(4093648983), // VWMACC_VV
14252 UINT64_C(4093665367), // VWMACC_VX
14253 UINT64_C(3892322391), // VWMULSU_VV
14254 UINT64_C(3892338775), // VWMULSU_VX
14255 UINT64_C(3758104663), // VWMULU_VV
14256 UINT64_C(3758121047), // VWMULU_VX
14257 UINT64_C(3959431255), // VWMUL_VV
14258 UINT64_C(3959447639), // VWMUL_VX
14259 UINT64_C(3221225559), // VWREDSUMU_VS
14260 UINT64_C(3288334423), // VWREDSUM_VS
14261 UINT64_C(3556782167), // VWSLL_VI
14262 UINT64_C(3556769879), // VWSLL_VV
14263 UINT64_C(3556786263), // VWSLL_VX
14264 UINT64_C(3355451479), // VWSUBU_VV
14265 UINT64_C(3355467863), // VWSUBU_VX
14266 UINT64_C(3623886935), // VWSUBU_WV
14267 UINT64_C(3623903319), // VWSUBU_WX
14268 UINT64_C(3422560343), // VWSUB_VV
14269 UINT64_C(3422576727), // VWSUB_VX
14270 UINT64_C(3690995799), // VWSUB_WV
14271 UINT64_C(3691012183), // VWSUB_WX
14272 UINT64_C(738209879), // VXOR_VI
14273 UINT64_C(738197591), // VXOR_VV
14274 UINT64_C(738213975), // VXOR_VX
14275 UINT64_C(1208164439), // VZEXT_VF2
14276 UINT64_C(1208098903), // VZEXT_VF4
14277 UINT64_C(1208033367), // VZEXT_VF8
14278 UINT64_C(273678451), // WFI
14279 UINT64_C(13631603), // WRS_NTO
14280 UINT64_C(30408819), // WRS_STO
14281 UINT64_C(1073758259), // XNOR
14282 UINT64_C(16435), // XOR
14283 UINT64_C(16403), // XORI
14284 UINT64_C(671096883), // XPERM4
14285 UINT64_C(671105075), // XPERM8
14286 UINT64_C(134234163), // ZEXT_H_RV32
14287 UINT64_C(134234171), // ZEXT_H_RV64
14288 UINT64_C(149950483), // ZIP_RV32
14289 UINT64_C(0)
14290 };
14291 const unsigned opcode = MI.getOpcode();
14292 uint64_t Value = InstBits[opcode];
14293 uint64_t op = 0;
14294 (void)op; // suppress warning
14295 switch (opcode) {
14296 case RISCV::C_EBREAK:
14297 case RISCV::C_MOP1:
14298 case RISCV::C_MOP3:
14299 case RISCV::C_MOP5:
14300 case RISCV::C_MOP7:
14301 case RISCV::C_MOP9:
14302 case RISCV::C_MOP11:
14303 case RISCV::C_MOP13:
14304 case RISCV::C_MOP15:
14305 case RISCV::C_NOP:
14306 case RISCV::C_SSPOPCHK:
14307 case RISCV::C_SSPUSH:
14308 case RISCV::C_UNIMP:
14309 case RISCV::DRET:
14310 case RISCV::EBREAK:
14311 case RISCV::ECALL:
14312 case RISCV::FENCE_I:
14313 case RISCV::FENCE_TSO:
14314 case RISCV::MNRET:
14315 case RISCV::MRET:
14316 case RISCV::QC_C_DI:
14317 case RISCV::QC_C_EI:
14318 case RISCV::QC_C_MIENTER:
14319 case RISCV::QC_C_MIENTER_NEST:
14320 case RISCV::QC_C_MILEAVERET:
14321 case RISCV::QC_C_MNRET:
14322 case RISCV::QC_C_MRET:
14323 case RISCV::QC_C_PTRACE:
14324 case RISCV::QC_PCOREDUMP:
14325 case RISCV::QC_PPREGS:
14326 case RISCV::SCTRCLR:
14327 case RISCV::SFENCE_INVAL_IR:
14328 case RISCV::SFENCE_W_INVAL:
14329 case RISCV::SF_CEASE:
14330 case RISCV::SF_VTDISCARD:
14331 case RISCV::SRET:
14332 case RISCV::TH_DCACHE_CALL:
14333 case RISCV::TH_DCACHE_CIALL:
14334 case RISCV::TH_DCACHE_IALL:
14335 case RISCV::TH_ICACHE_IALL:
14336 case RISCV::TH_ICACHE_IALLS:
14337 case RISCV::TH_L2CACHE_CALL:
14338 case RISCV::TH_L2CACHE_CIALL:
14339 case RISCV::TH_L2CACHE_IALL:
14340 case RISCV::TH_SYNC:
14341 case RISCV::TH_SYNC_I:
14342 case RISCV::TH_SYNC_IS:
14343 case RISCV::TH_SYNC_S:
14344 case RISCV::UNIMP:
14345 case RISCV::WFI:
14346 case RISCV::WRS_NTO:
14347 case RISCV::WRS_STO: {
14348 break;
14349 }
14350 case RISCV::C_NOP_HINT: {
14351 // op: imm
14352 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
14353 Value |= (op & UINT64_C(32)) << 7;
14354 Value |= (op & UINT64_C(31)) << 2;
14355 break;
14356 }
14357 case RISCV::C_LI_HINT:
14358 case RISCV::C_LUI_HINT: {
14359 // op: imm
14360 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14361 Value |= (op & UINT64_C(32)) << 7;
14362 Value |= (op & UINT64_C(31)) << 2;
14363 break;
14364 }
14365 case RISCV::C_LI:
14366 case RISCV::C_LUI: {
14367 // op: imm
14368 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14369 Value |= (op & UINT64_C(32)) << 7;
14370 Value |= (op & UINT64_C(31)) << 2;
14371 // op: rd
14372 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14373 op &= UINT64_C(31);
14374 op <<= 7;
14375 Value |= op;
14376 break;
14377 }
14378 case RISCV::VMV_V_I: {
14379 // op: imm
14380 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14381 op &= UINT64_C(31);
14382 op <<= 15;
14383 Value |= op;
14384 // op: vd
14385 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14386 op &= UINT64_C(31);
14387 op <<= 7;
14388 Value |= op;
14389 break;
14390 }
14391 case RISCV::C_FLDSP:
14392 case RISCV::C_LDSP:
14393 case RISCV::C_LDSP_RV32: {
14394 // op: imm
14395 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14396 Value |= (op & UINT64_C(32)) << 7;
14397 Value |= (op & UINT64_C(24)) << 2;
14398 Value |= (op & UINT64_C(448)) >> 4;
14399 // op: rd
14400 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14401 op &= UINT64_C(31);
14402 op <<= 7;
14403 Value |= op;
14404 break;
14405 }
14406 case RISCV::C_FLWSP:
14407 case RISCV::C_LWSP:
14408 case RISCV::C_LWSP_INX: {
14409 // op: imm
14410 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14411 Value |= (op & UINT64_C(32)) << 7;
14412 Value |= (op & UINT64_C(28)) << 2;
14413 Value |= (op & UINT64_C(192)) >> 4;
14414 // op: rd
14415 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14416 op &= UINT64_C(31);
14417 op <<= 7;
14418 Value |= op;
14419 break;
14420 }
14421 case RISCV::C_ADDI:
14422 case RISCV::C_ADDIW: {
14423 // op: imm
14424 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14425 Value |= (op & UINT64_C(32)) << 7;
14426 Value |= (op & UINT64_C(31)) << 2;
14427 // op: rd
14428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14429 op &= UINT64_C(31);
14430 op <<= 7;
14431 Value |= op;
14432 break;
14433 }
14434 case RISCV::C_ANDI: {
14435 // op: imm
14436 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14437 Value |= (op & UINT64_C(32)) << 7;
14438 Value |= (op & UINT64_C(31)) << 2;
14439 // op: rs1
14440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14441 op &= UINT64_C(7);
14442 op <<= 7;
14443 Value |= op;
14444 break;
14445 }
14446 case RISCV::C_ADDI4SPN: {
14447 // op: imm
14448 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14449 Value |= (op & UINT64_C(48)) << 7;
14450 Value |= (op & UINT64_C(960)) << 1;
14451 Value |= (op & UINT64_C(4)) << 4;
14452 Value |= (op & UINT64_C(8)) << 2;
14453 // op: rd
14454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14455 op &= UINT64_C(7);
14456 op <<= 2;
14457 Value |= op;
14458 break;
14459 }
14460 case RISCV::C_ADDI16SP: {
14461 // op: imm
14462 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14463 Value |= (op & UINT64_C(512)) << 3;
14464 Value |= (op & UINT64_C(16)) << 2;
14465 Value |= (op & UINT64_C(64)) >> 1;
14466 Value |= (op & UINT64_C(384)) >> 4;
14467 Value |= (op & UINT64_C(32)) >> 3;
14468 break;
14469 }
14470 case RISCV::C_FSDSP:
14471 case RISCV::C_SDSP:
14472 case RISCV::C_SDSP_RV32: {
14473 // op: imm
14474 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14475 Value |= (op & UINT64_C(56)) << 7;
14476 Value |= (op & UINT64_C(448)) << 1;
14477 // op: rs2
14478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14479 op &= UINT64_C(31);
14480 op <<= 2;
14481 Value |= op;
14482 break;
14483 }
14484 case RISCV::C_FSWSP:
14485 case RISCV::C_SWSP:
14486 case RISCV::C_SWSP_INX: {
14487 // op: imm
14488 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14489 Value |= (op & UINT64_C(60)) << 7;
14490 Value |= (op & UINT64_C(192)) << 1;
14491 // op: rs2
14492 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14493 op &= UINT64_C(31);
14494 op <<= 2;
14495 Value |= op;
14496 break;
14497 }
14498 case RISCV::RI_VEXTRACT: {
14499 // op: imm
14500 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14501 op &= UINT64_C(31);
14502 op <<= 15;
14503 Value |= op;
14504 // op: vs2
14505 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14506 op &= UINT64_C(31);
14507 op <<= 20;
14508 Value |= op;
14509 // op: rd
14510 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14511 op &= UINT64_C(31);
14512 op <<= 7;
14513 Value |= op;
14514 break;
14515 }
14516 case RISCV::RI_VINSERT: {
14517 // op: imm
14518 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
14519 op &= UINT64_C(31);
14520 op <<= 20;
14521 Value |= op;
14522 // op: rs1
14523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14524 op &= UINT64_C(31);
14525 op <<= 15;
14526 Value |= op;
14527 // op: vd
14528 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14529 op &= UINT64_C(31);
14530 op <<= 7;
14531 Value |= op;
14532 break;
14533 }
14534 case RISCV::C_BEQZ:
14535 case RISCV::C_BNEZ: {
14536 // op: imm
14537 op = getImmOpValueAsrN<1>(MI, OpNo: 1, Fixups, STI);
14538 Value |= (op & UINT64_C(128)) << 5;
14539 Value |= (op & UINT64_C(12)) << 8;
14540 Value |= (op & UINT64_C(96));
14541 Value |= (op & UINT64_C(3)) << 3;
14542 Value |= (op & UINT64_C(16)) >> 2;
14543 // op: rs1
14544 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14545 op &= UINT64_C(7);
14546 op <<= 7;
14547 Value |= op;
14548 break;
14549 }
14550 case RISCV::QC_C_DELAY: {
14551 // op: imm
14552 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14553 op &= UINT64_C(31);
14554 op <<= 2;
14555 Value |= op;
14556 break;
14557 }
14558 case RISCV::C_SLLI_HINT: {
14559 // op: imm
14560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14561 Value |= (op & UINT64_C(32)) << 7;
14562 Value |= (op & UINT64_C(31)) << 2;
14563 break;
14564 }
14565 case RISCV::C_SLLI: {
14566 // op: imm
14567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14568 Value |= (op & UINT64_C(32)) << 7;
14569 Value |= (op & UINT64_C(31)) << 2;
14570 // op: rd
14571 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14572 op &= UINT64_C(31);
14573 op <<= 7;
14574 Value |= op;
14575 break;
14576 }
14577 case RISCV::C_SRAI:
14578 case RISCV::C_SRLI: {
14579 // op: imm
14580 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14581 Value |= (op & UINT64_C(32)) << 7;
14582 Value |= (op & UINT64_C(31)) << 2;
14583 // op: rs1
14584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14585 op &= UINT64_C(7);
14586 op <<= 7;
14587 Value |= op;
14588 break;
14589 }
14590 case RISCV::QC_CLRINTI:
14591 case RISCV::QC_SETINTI: {
14592 // op: imm10
14593 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
14594 op &= UINT64_C(1023);
14595 op <<= 15;
14596 Value |= op;
14597 break;
14598 }
14599 case RISCV::QC_PSYSCALLI: {
14600 // op: imm10
14601 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
14602 op &= UINT64_C(1023);
14603 op <<= 20;
14604 Value |= op;
14605 break;
14606 }
14607 case RISCV::NDS_BEQC:
14608 case RISCV::NDS_BNEC: {
14609 // op: imm10
14610 op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI);
14611 Value |= (op & UINT64_C(512)) << 22;
14612 Value |= (op & UINT64_C(496)) << 21;
14613 Value |= (op & UINT64_C(15)) << 8;
14614 // op: rs1
14615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14616 op &= UINT64_C(31);
14617 op <<= 15;
14618 Value |= op;
14619 // op: cimm
14620 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14621 Value |= (op & UINT64_C(64)) << 24;
14622 Value |= (op & UINT64_C(31)) << 20;
14623 Value |= (op & UINT64_C(32)) << 2;
14624 break;
14625 }
14626 case RISCV::NDS_BBC:
14627 case RISCV::NDS_BBS: {
14628 // op: imm10
14629 op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI);
14630 Value |= (op & UINT64_C(512)) << 22;
14631 Value |= (op & UINT64_C(496)) << 21;
14632 Value |= (op & UINT64_C(15)) << 8;
14633 // op: rs1
14634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14635 op &= UINT64_C(31);
14636 op <<= 15;
14637 Value |= op;
14638 // op: cimm
14639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14640 Value |= (op & UINT64_C(31)) << 20;
14641 Value |= (op & UINT64_C(32)) << 2;
14642 break;
14643 }
14644 case RISCV::PREFETCH_I:
14645 case RISCV::PREFETCH_R:
14646 case RISCV::PREFETCH_W: {
14647 // op: imm12
14648 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14649 op &= UINT64_C(4064);
14650 op <<= 20;
14651 Value |= op;
14652 // op: rs1
14653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14654 op &= UINT64_C(31);
14655 op <<= 15;
14656 Value |= op;
14657 break;
14658 }
14659 case RISCV::FSD:
14660 case RISCV::FSH:
14661 case RISCV::FSQ:
14662 case RISCV::FSW:
14663 case RISCV::SB:
14664 case RISCV::SD:
14665 case RISCV::SD_RV32:
14666 case RISCV::SH:
14667 case RISCV::SH_INX:
14668 case RISCV::SW:
14669 case RISCV::SW_INX: {
14670 // op: imm12
14671 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
14672 Value |= (op & UINT64_C(4064)) << 20;
14673 Value |= (op & UINT64_C(31)) << 7;
14674 // op: rs2
14675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14676 op &= UINT64_C(31);
14677 op <<= 20;
14678 Value |= op;
14679 // op: rs1
14680 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14681 op &= UINT64_C(31);
14682 op <<= 15;
14683 Value |= op;
14684 break;
14685 }
14686 case RISCV::CV_SB_ri_inc:
14687 case RISCV::CV_SH_ri_inc:
14688 case RISCV::CV_SW_ri_inc: {
14689 // op: imm12
14690 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
14691 Value |= (op & UINT64_C(4064)) << 20;
14692 Value |= (op & UINT64_C(31)) << 7;
14693 // op: rs2
14694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14695 op &= UINT64_C(31);
14696 op <<= 20;
14697 Value |= op;
14698 // op: rs1
14699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14700 op &= UINT64_C(31);
14701 op <<= 15;
14702 Value |= op;
14703 break;
14704 }
14705 case RISCV::CV_BEQIMM:
14706 case RISCV::CV_BNEIMM: {
14707 // op: imm12
14708 op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI);
14709 Value |= (op & UINT64_C(2048)) << 20;
14710 Value |= (op & UINT64_C(1008)) << 21;
14711 Value |= (op & UINT64_C(15)) << 8;
14712 Value |= (op & UINT64_C(1024)) >> 3;
14713 // op: rs1
14714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14715 op &= UINT64_C(31);
14716 op <<= 15;
14717 Value |= op;
14718 // op: imm5
14719 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14720 op &= UINT64_C(31);
14721 op <<= 20;
14722 Value |= op;
14723 break;
14724 }
14725 case RISCV::BEQ:
14726 case RISCV::BGE:
14727 case RISCV::BGEU:
14728 case RISCV::BLT:
14729 case RISCV::BLTU:
14730 case RISCV::BNE:
14731 case RISCV::QC_BEQI:
14732 case RISCV::QC_BGEI:
14733 case RISCV::QC_BGEUI:
14734 case RISCV::QC_BLTI:
14735 case RISCV::QC_BLTUI:
14736 case RISCV::QC_BNEI: {
14737 // op: imm12
14738 op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI);
14739 Value |= (op & UINT64_C(2048)) << 20;
14740 Value |= (op & UINT64_C(1008)) << 21;
14741 Value |= (op & UINT64_C(15)) << 8;
14742 Value |= (op & UINT64_C(1024)) >> 3;
14743 // op: rs2
14744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14745 op &= UINT64_C(31);
14746 op <<= 20;
14747 Value |= op;
14748 // op: rs1
14749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14750 op &= UINT64_C(31);
14751 op <<= 15;
14752 Value |= op;
14753 break;
14754 }
14755 case RISCV::NDS_SHGP: {
14756 // op: imm17
14757 op = getImmOpValueAsrN<1>(MI, OpNo: 1, Fixups, STI);
14758 Value |= (op & UINT64_C(65536)) << 15;
14759 Value |= (op & UINT64_C(1008)) << 21;
14760 Value |= (op & UINT64_C(14336)) << 6;
14761 Value |= (op & UINT64_C(49152)) << 1;
14762 Value |= (op & UINT64_C(15)) << 8;
14763 Value |= (op & UINT64_C(1024)) >> 3;
14764 // op: rs2
14765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14766 op &= UINT64_C(31);
14767 op <<= 20;
14768 Value |= op;
14769 break;
14770 }
14771 case RISCV::NDS_LHGP:
14772 case RISCV::NDS_LHUGP: {
14773 // op: imm17
14774 op = getImmOpValueAsrN<1>(MI, OpNo: 1, Fixups, STI);
14775 Value |= (op & UINT64_C(65536)) << 15;
14776 Value |= (op & UINT64_C(1023)) << 21;
14777 Value |= (op & UINT64_C(1024)) << 10;
14778 Value |= (op & UINT64_C(14336)) << 6;
14779 Value |= (op & UINT64_C(49152)) << 1;
14780 // op: rd
14781 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14782 op &= UINT64_C(31);
14783 op <<= 7;
14784 Value |= op;
14785 break;
14786 }
14787 case RISCV::NDS_SWGP: {
14788 // op: imm17
14789 op = getImmOpValueAsrN<2>(MI, OpNo: 1, Fixups, STI);
14790 Value |= (op & UINT64_C(65536)) << 15;
14791 Value |= (op & UINT64_C(504)) << 22;
14792 Value |= (op & UINT64_C(7168)) << 7;
14793 Value |= (op & UINT64_C(24576)) << 2;
14794 Value |= (op & UINT64_C(7)) << 9;
14795 Value |= (op & UINT64_C(32768)) >> 7;
14796 Value |= (op & UINT64_C(512)) >> 2;
14797 // op: rs2
14798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14799 op &= UINT64_C(31);
14800 op <<= 20;
14801 Value |= op;
14802 break;
14803 }
14804 case RISCV::NDS_LWGP:
14805 case RISCV::NDS_LWUGP: {
14806 // op: imm17
14807 op = getImmOpValueAsrN<2>(MI, OpNo: 1, Fixups, STI);
14808 Value |= (op & UINT64_C(65536)) << 15;
14809 Value |= (op & UINT64_C(511)) << 22;
14810 Value |= (op & UINT64_C(32768)) << 6;
14811 Value |= (op & UINT64_C(512)) << 11;
14812 Value |= (op & UINT64_C(7168)) << 7;
14813 Value |= (op & UINT64_C(24576)) << 2;
14814 // op: rd
14815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14816 op &= UINT64_C(31);
14817 op <<= 7;
14818 Value |= op;
14819 break;
14820 }
14821 case RISCV::NDS_SDGP: {
14822 // op: imm17
14823 op = getImmOpValueAsrN<3>(MI, OpNo: 1, Fixups, STI);
14824 Value |= (op & UINT64_C(65536)) << 15;
14825 Value |= (op & UINT64_C(252)) << 23;
14826 Value |= (op & UINT64_C(3584)) << 8;
14827 Value |= (op & UINT64_C(12288)) << 3;
14828 Value |= (op & UINT64_C(3)) << 10;
14829 Value |= (op & UINT64_C(49152)) >> 6;
14830 Value |= (op & UINT64_C(256)) >> 1;
14831 // op: rs2
14832 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14833 op &= UINT64_C(31);
14834 op <<= 20;
14835 Value |= op;
14836 break;
14837 }
14838 case RISCV::NDS_LDGP: {
14839 // op: imm17
14840 op = getImmOpValueAsrN<3>(MI, OpNo: 1, Fixups, STI);
14841 Value |= (op & UINT64_C(65536)) << 15;
14842 Value |= (op & UINT64_C(255)) << 23;
14843 Value |= (op & UINT64_C(49152)) << 7;
14844 Value |= (op & UINT64_C(256)) << 12;
14845 Value |= (op & UINT64_C(3584)) << 8;
14846 Value |= (op & UINT64_C(12288)) << 3;
14847 // op: rd
14848 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14849 op &= UINT64_C(31);
14850 op <<= 7;
14851 Value |= op;
14852 break;
14853 }
14854 case RISCV::NDS_SBGP: {
14855 // op: imm18
14856 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14857 Value |= (op & UINT64_C(131072)) << 14;
14858 Value |= (op & UINT64_C(2016)) << 20;
14859 Value |= (op & UINT64_C(28672)) << 5;
14860 Value |= (op & UINT64_C(98304));
14861 Value |= (op & UINT64_C(1)) << 14;
14862 Value |= (op & UINT64_C(30)) << 7;
14863 Value |= (op & UINT64_C(2048)) >> 4;
14864 // op: rs2
14865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14866 op &= UINT64_C(31);
14867 op <<= 20;
14868 Value |= op;
14869 break;
14870 }
14871 case RISCV::NDS_ADDIGP:
14872 case RISCV::NDS_LBGP:
14873 case RISCV::NDS_LBUGP: {
14874 // op: imm18
14875 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14876 Value |= (op & UINT64_C(131072)) << 14;
14877 Value |= (op & UINT64_C(2046)) << 20;
14878 Value |= (op & UINT64_C(2048)) << 9;
14879 Value |= (op & UINT64_C(28672)) << 5;
14880 Value |= (op & UINT64_C(98304));
14881 Value |= (op & UINT64_C(1)) << 14;
14882 // op: rd
14883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14884 op &= UINT64_C(31);
14885 op <<= 7;
14886 Value |= op;
14887 break;
14888 }
14889 case RISCV::QC_LI: {
14890 // op: imm20
14891 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14892 Value |= (op & UINT64_C(524288)) << 12;
14893 Value |= (op & UINT64_C(32767)) << 16;
14894 Value |= (op & UINT64_C(491520)) >> 3;
14895 // op: rd
14896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14897 op &= UINT64_C(31);
14898 op <<= 7;
14899 Value |= op;
14900 break;
14901 }
14902 case RISCV::AUIPC:
14903 case RISCV::LUI: {
14904 // op: imm20
14905 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
14906 op &= UINT64_C(1048575);
14907 op <<= 12;
14908 Value |= op;
14909 // op: rd
14910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14911 op &= UINT64_C(31);
14912 op <<= 7;
14913 Value |= op;
14914 break;
14915 }
14916 case RISCV::JAL: {
14917 // op: imm20
14918 op = getImmOpValueAsrN<1>(MI, OpNo: 1, Fixups, STI);
14919 Value |= (op & UINT64_C(524288)) << 12;
14920 Value |= (op & UINT64_C(1023)) << 21;
14921 Value |= (op & UINT64_C(1024)) << 10;
14922 Value |= (op & UINT64_C(522240)) << 1;
14923 // op: rd
14924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14925 op &= UINT64_C(31);
14926 op <<= 7;
14927 Value |= op;
14928 break;
14929 }
14930 case RISCV::QC_E_J:
14931 case RISCV::QC_E_JAL: {
14932 // op: imm31
14933 op = getImmOpValueAsrN<1>(MI, OpNo: 0, Fixups, STI);
14934 Value |= (op & UINT64_C(2147450880)) << 17;
14935 Value |= (op & UINT64_C(2048)) << 20;
14936 Value |= (op & UINT64_C(1008)) << 21;
14937 Value |= (op & UINT64_C(28672)) << 5;
14938 Value |= (op & UINT64_C(15)) << 8;
14939 Value |= (op & UINT64_C(1024)) >> 3;
14940 break;
14941 }
14942 case RISCV::QC_SYNC:
14943 case RISCV::QC_SYNCR:
14944 case RISCV::QC_SYNCWF:
14945 case RISCV::QC_SYNCWL: {
14946 // op: imm5
14947 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
14948 op &= UINT64_C(31);
14949 op <<= 20;
14950 Value |= op;
14951 break;
14952 }
14953 case RISCV::MIPS_SDP: {
14954 // op: imm7
14955 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
14956 Value |= (op & UINT64_C(96)) << 20;
14957 Value |= (op & UINT64_C(24)) << 7;
14958 // op: rs3
14959 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14960 op &= UINT64_C(31);
14961 op <<= 27;
14962 Value |= op;
14963 // op: rs2
14964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14965 op &= UINT64_C(31);
14966 op <<= 20;
14967 Value |= op;
14968 // op: rs1
14969 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14970 op &= UINT64_C(31);
14971 op <<= 15;
14972 Value |= op;
14973 break;
14974 }
14975 case RISCV::MIPS_SWP: {
14976 // op: imm7
14977 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
14978 Value |= (op & UINT64_C(96)) << 20;
14979 Value |= (op & UINT64_C(28)) << 7;
14980 // op: rs3
14981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14982 op &= UINT64_C(31);
14983 op <<= 27;
14984 Value |= op;
14985 // op: rs2
14986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14987 op &= UINT64_C(31);
14988 op <<= 20;
14989 Value |= op;
14990 // op: rs1
14991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14992 op &= UINT64_C(31);
14993 op <<= 15;
14994 Value |= op;
14995 break;
14996 }
14997 case RISCV::MIPS_LDP: {
14998 // op: imm7
14999 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15000 op &= UINT64_C(120);
15001 op <<= 20;
15002 Value |= op;
15003 // op: rs1
15004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15005 op &= UINT64_C(31);
15006 op <<= 15;
15007 Value |= op;
15008 // op: rd1
15009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15010 op &= UINT64_C(31);
15011 op <<= 7;
15012 Value |= op;
15013 // op: rd2
15014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15015 op &= UINT64_C(31);
15016 op <<= 27;
15017 Value |= op;
15018 break;
15019 }
15020 case RISCV::MIPS_LWP: {
15021 // op: imm7
15022 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15023 op &= UINT64_C(124);
15024 op <<= 20;
15025 Value |= op;
15026 // op: rs1
15027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15028 op &= UINT64_C(31);
15029 op <<= 15;
15030 Value |= op;
15031 // op: rd1
15032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15033 op &= UINT64_C(31);
15034 op <<= 7;
15035 Value |= op;
15036 // op: rd2
15037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15038 op &= UINT64_C(31);
15039 op <<= 27;
15040 Value |= op;
15041 break;
15042 }
15043 case RISCV::QC_PPUTCI: {
15044 // op: imm8
15045 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15046 op &= UINT64_C(255);
15047 op <<= 20;
15048 Value |= op;
15049 break;
15050 }
15051 case RISCV::MIPS_PREFETCH: {
15052 // op: imm9
15053 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15054 op &= UINT64_C(511);
15055 op <<= 20;
15056 Value |= op;
15057 // op: rs1
15058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15059 op &= UINT64_C(31);
15060 op <<= 15;
15061 Value |= op;
15062 // op: hint
15063 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15064 op &= UINT64_C(31);
15065 op <<= 7;
15066 Value |= op;
15067 break;
15068 }
15069 case RISCV::CM_JT: {
15070 // op: index
15071 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15072 op &= UINT64_C(31);
15073 op <<= 2;
15074 Value |= op;
15075 break;
15076 }
15077 case RISCV::CM_JALT: {
15078 // op: index
15079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15080 op &= UINT64_C(255);
15081 op <<= 2;
15082 Value |= op;
15083 break;
15084 }
15085 case RISCV::C_J:
15086 case RISCV::C_JAL: {
15087 // op: offset
15088 op = getImmOpValueAsrN<1>(MI, OpNo: 0, Fixups, STI);
15089 Value |= (op & UINT64_C(1024)) << 2;
15090 Value |= (op & UINT64_C(8)) << 8;
15091 Value |= (op & UINT64_C(384)) << 2;
15092 Value |= (op & UINT64_C(512)) >> 1;
15093 Value |= (op & UINT64_C(32)) << 2;
15094 Value |= (op & UINT64_C(64));
15095 Value |= (op & UINT64_C(7)) << 3;
15096 Value |= (op & UINT64_C(16)) >> 2;
15097 break;
15098 }
15099 case RISCV::InsnQC_EJ: {
15100 // op: opcode
15101 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15102 op &= UINT64_C(127);
15103 Value |= op;
15104 // op: func3
15105 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15106 op &= UINT64_C(7);
15107 op <<= 12;
15108 Value |= op;
15109 // op: func2
15110 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15111 op &= UINT64_C(3);
15112 op <<= 15;
15113 Value |= op;
15114 // op: func5
15115 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15116 op &= UINT64_C(31);
15117 op <<= 20;
15118 Value |= op;
15119 // op: imm31
15120 op = getImmOpValueAsrN<1>(MI, OpNo: 4, Fixups, STI);
15121 Value |= (op & UINT64_C(2147450880)) << 17;
15122 Value |= (op & UINT64_C(2048)) << 20;
15123 Value |= (op & UINT64_C(1008)) << 21;
15124 Value |= (op & UINT64_C(28672)) << 5;
15125 Value |= (op & UINT64_C(15)) << 8;
15126 Value |= (op & UINT64_C(1024)) >> 3;
15127 break;
15128 }
15129 case RISCV::InsnQC_ES: {
15130 // op: opcode
15131 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15132 op &= UINT64_C(127);
15133 Value |= op;
15134 // op: func3
15135 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15136 op &= UINT64_C(7);
15137 op <<= 12;
15138 Value |= op;
15139 // op: func2
15140 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15141 op &= UINT64_C(3);
15142 op <<= 30;
15143 Value |= op;
15144 // op: rs1
15145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15146 op &= UINT64_C(31);
15147 op <<= 15;
15148 Value |= op;
15149 // op: rs2
15150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15151 op &= UINT64_C(31);
15152 op <<= 20;
15153 Value |= op;
15154 // op: imm26
15155 op = getImmOpValue(MI, OpNo: 5, Fixups, STI);
15156 Value |= (op & UINT64_C(67107840)) << 22;
15157 Value |= (op & UINT64_C(992)) << 20;
15158 Value |= (op & UINT64_C(31)) << 7;
15159 break;
15160 }
15161 case RISCV::InsnQC_EB: {
15162 // op: opcode
15163 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15164 op &= UINT64_C(127);
15165 Value |= op;
15166 // op: func3
15167 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15168 op &= UINT64_C(7);
15169 op <<= 12;
15170 Value |= op;
15171 // op: func5
15172 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15173 op &= UINT64_C(31);
15174 op <<= 20;
15175 Value |= op;
15176 // op: rs1
15177 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15178 op &= UINT64_C(31);
15179 op <<= 15;
15180 Value |= op;
15181 // op: imm12
15182 op = getImmOpValueAsrN<1>(MI, OpNo: 5, Fixups, STI);
15183 Value |= (op & UINT64_C(2048)) << 20;
15184 Value |= (op & UINT64_C(1008)) << 21;
15185 Value |= (op & UINT64_C(15)) << 8;
15186 Value |= (op & UINT64_C(1024)) >> 3;
15187 // op: imm16
15188 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
15189 op &= UINT64_C(65535);
15190 op <<= 32;
15191 Value |= op;
15192 break;
15193 }
15194 case RISCV::InsnS: {
15195 // op: opcode
15196 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15197 op &= UINT64_C(127);
15198 Value |= op;
15199 // op: funct3
15200 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15201 op &= UINT64_C(7);
15202 op <<= 12;
15203 Value |= op;
15204 // op: imm12
15205 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
15206 Value |= (op & UINT64_C(4064)) << 20;
15207 Value |= (op & UINT64_C(31)) << 7;
15208 // op: rs2
15209 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15210 op &= UINT64_C(31);
15211 op <<= 20;
15212 Value |= op;
15213 // op: rs1
15214 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15215 op &= UINT64_C(31);
15216 op <<= 15;
15217 Value |= op;
15218 break;
15219 }
15220 case RISCV::InsnB: {
15221 // op: opcode
15222 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15223 op &= UINT64_C(127);
15224 Value |= op;
15225 // op: funct3
15226 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15227 op &= UINT64_C(7);
15228 op <<= 12;
15229 Value |= op;
15230 // op: imm12
15231 op = getImmOpValueAsrN<1>(MI, OpNo: 4, Fixups, STI);
15232 Value |= (op & UINT64_C(2048)) << 20;
15233 Value |= (op & UINT64_C(1008)) << 21;
15234 Value |= (op & UINT64_C(15)) << 8;
15235 Value |= (op & UINT64_C(1024)) >> 3;
15236 // op: rs2
15237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15238 op &= UINT64_C(31);
15239 op <<= 20;
15240 Value |= op;
15241 // op: rs1
15242 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15243 op &= UINT64_C(31);
15244 op <<= 15;
15245 Value |= op;
15246 break;
15247 }
15248 case RISCV::InsnCJ: {
15249 // op: opcode
15250 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15251 op &= UINT64_C(3);
15252 Value |= op;
15253 // op: funct3
15254 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15255 op &= UINT64_C(7);
15256 op <<= 13;
15257 Value |= op;
15258 // op: imm11
15259 op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI);
15260 Value |= (op & UINT64_C(1024)) << 2;
15261 Value |= (op & UINT64_C(8)) << 8;
15262 Value |= (op & UINT64_C(384)) << 2;
15263 Value |= (op & UINT64_C(512)) >> 1;
15264 Value |= (op & UINT64_C(32)) << 2;
15265 Value |= (op & UINT64_C(64));
15266 Value |= (op & UINT64_C(7)) << 3;
15267 Value |= (op & UINT64_C(16)) >> 2;
15268 break;
15269 }
15270 case RISCV::InsnCS: {
15271 // op: opcode
15272 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15273 op &= UINT64_C(3);
15274 Value |= op;
15275 // op: funct3
15276 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15277 op &= UINT64_C(7);
15278 op <<= 13;
15279 Value |= op;
15280 // op: imm5
15281 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
15282 Value |= (op & UINT64_C(28)) << 8;
15283 Value |= (op & UINT64_C(3)) << 5;
15284 // op: rs2
15285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15286 op &= UINT64_C(7);
15287 op <<= 2;
15288 Value |= op;
15289 // op: rs1
15290 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15291 op &= UINT64_C(7);
15292 op <<= 7;
15293 Value |= op;
15294 break;
15295 }
15296 case RISCV::InsnCSS: {
15297 // op: opcode
15298 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15299 op &= UINT64_C(3);
15300 Value |= op;
15301 // op: funct3
15302 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15303 op &= UINT64_C(7);
15304 op <<= 13;
15305 Value |= op;
15306 // op: imm6
15307 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15308 op &= UINT64_C(63);
15309 op <<= 7;
15310 Value |= op;
15311 // op: rs2
15312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15313 op &= UINT64_C(31);
15314 op <<= 2;
15315 Value |= op;
15316 break;
15317 }
15318 case RISCV::InsnCB: {
15319 // op: opcode
15320 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
15321 op &= UINT64_C(3);
15322 Value |= op;
15323 // op: funct3
15324 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15325 op &= UINT64_C(7);
15326 op <<= 13;
15327 Value |= op;
15328 // op: imm8
15329 op = getImmOpValueAsrN<1>(MI, OpNo: 3, Fixups, STI);
15330 Value |= (op & UINT64_C(128)) << 5;
15331 Value |= (op & UINT64_C(12)) << 8;
15332 Value |= (op & UINT64_C(96));
15333 Value |= (op & UINT64_C(3)) << 3;
15334 Value |= (op & UINT64_C(16)) >> 2;
15335 // op: rs1
15336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15337 op &= UINT64_C(7);
15338 op <<= 7;
15339 Value |= op;
15340 break;
15341 }
15342 case RISCV::InsnQC_EAI: {
15343 // op: opcode
15344 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15345 op &= UINT64_C(127);
15346 Value |= op;
15347 // op: func3
15348 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15349 op &= UINT64_C(7);
15350 op <<= 12;
15351 Value |= op;
15352 // op: func1
15353 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15354 op &= UINT64_C(1);
15355 op <<= 15;
15356 Value |= op;
15357 // op: rd
15358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15359 op &= UINT64_C(31);
15360 op <<= 7;
15361 Value |= op;
15362 // op: imm32
15363 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
15364 op &= UINT64_C(4294967295);
15365 op <<= 16;
15366 Value |= op;
15367 break;
15368 }
15369 case RISCV::InsnQC_EI:
15370 case RISCV::InsnQC_EI_Mem: {
15371 // op: opcode
15372 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15373 op &= UINT64_C(127);
15374 Value |= op;
15375 // op: func3
15376 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15377 op &= UINT64_C(7);
15378 op <<= 12;
15379 Value |= op;
15380 // op: func2
15381 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15382 op &= UINT64_C(3);
15383 op <<= 30;
15384 Value |= op;
15385 // op: rd
15386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15387 op &= UINT64_C(31);
15388 op <<= 7;
15389 Value |= op;
15390 // op: rs1
15391 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15392 op &= UINT64_C(31);
15393 op <<= 15;
15394 Value |= op;
15395 // op: imm26
15396 op = getImmOpValue(MI, OpNo: 5, Fixups, STI);
15397 Value |= (op & UINT64_C(67107840)) << 22;
15398 Value |= (op & UINT64_C(1023)) << 20;
15399 break;
15400 }
15401 case RISCV::InsnR4: {
15402 // op: opcode
15403 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15404 op &= UINT64_C(127);
15405 Value |= op;
15406 // op: funct2
15407 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15408 op &= UINT64_C(3);
15409 op <<= 25;
15410 Value |= op;
15411 // op: funct3
15412 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15413 op &= UINT64_C(7);
15414 op <<= 12;
15415 Value |= op;
15416 // op: rs3
15417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
15418 op &= UINT64_C(31);
15419 op <<= 27;
15420 Value |= op;
15421 // op: rs2
15422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
15423 op &= UINT64_C(31);
15424 op <<= 20;
15425 Value |= op;
15426 // op: rs1
15427 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15428 op &= UINT64_C(31);
15429 op <<= 15;
15430 Value |= op;
15431 // op: rd
15432 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15433 op &= UINT64_C(31);
15434 op <<= 7;
15435 Value |= op;
15436 break;
15437 }
15438 case RISCV::InsnI:
15439 case RISCV::InsnI_Mem: {
15440 // op: opcode
15441 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15442 op &= UINT64_C(127);
15443 Value |= op;
15444 // op: funct3
15445 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15446 op &= UINT64_C(7);
15447 op <<= 12;
15448 Value |= op;
15449 // op: imm12
15450 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
15451 op &= UINT64_C(4095);
15452 op <<= 20;
15453 Value |= op;
15454 // op: rs1
15455 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15456 op &= UINT64_C(31);
15457 op <<= 15;
15458 Value |= op;
15459 // op: rd
15460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15461 op &= UINT64_C(31);
15462 op <<= 7;
15463 Value |= op;
15464 break;
15465 }
15466 case RISCV::InsnR: {
15467 // op: opcode
15468 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15469 op &= UINT64_C(127);
15470 Value |= op;
15471 // op: funct7
15472 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15473 op &= UINT64_C(127);
15474 op <<= 25;
15475 Value |= op;
15476 // op: funct3
15477 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15478 op &= UINT64_C(7);
15479 op <<= 12;
15480 Value |= op;
15481 // op: rs2
15482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
15483 op &= UINT64_C(31);
15484 op <<= 20;
15485 Value |= op;
15486 // op: rs1
15487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15488 op &= UINT64_C(31);
15489 op <<= 15;
15490 Value |= op;
15491 // op: rd
15492 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15493 op &= UINT64_C(31);
15494 op <<= 7;
15495 Value |= op;
15496 break;
15497 }
15498 case RISCV::InsnU: {
15499 // op: opcode
15500 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15501 op &= UINT64_C(127);
15502 Value |= op;
15503 // op: imm20
15504 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15505 op &= UINT64_C(1048575);
15506 op <<= 12;
15507 Value |= op;
15508 // op: rd
15509 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15510 op &= UINT64_C(31);
15511 op <<= 7;
15512 Value |= op;
15513 break;
15514 }
15515 case RISCV::InsnJ: {
15516 // op: opcode
15517 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15518 op &= UINT64_C(127);
15519 Value |= op;
15520 // op: imm20
15521 op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI);
15522 op &= UINT64_C(1048575);
15523 op <<= 12;
15524 Value |= op;
15525 // op: rd
15526 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15527 op &= UINT64_C(31);
15528 op <<= 7;
15529 Value |= op;
15530 break;
15531 }
15532 case RISCV::InsnCL: {
15533 // op: opcode
15534 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15535 op &= UINT64_C(3);
15536 Value |= op;
15537 // op: funct3
15538 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15539 op &= UINT64_C(7);
15540 op <<= 13;
15541 Value |= op;
15542 // op: imm5
15543 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
15544 Value |= (op & UINT64_C(28)) << 8;
15545 Value |= (op & UINT64_C(3)) << 5;
15546 // op: rd
15547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15548 op &= UINT64_C(7);
15549 op <<= 2;
15550 Value |= op;
15551 // op: rs1
15552 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15553 op &= UINT64_C(7);
15554 op <<= 7;
15555 Value |= op;
15556 break;
15557 }
15558 case RISCV::InsnCI: {
15559 // op: opcode
15560 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15561 op &= UINT64_C(3);
15562 Value |= op;
15563 // op: funct3
15564 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15565 op &= UINT64_C(7);
15566 op <<= 13;
15567 Value |= op;
15568 // op: imm6
15569 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15570 Value |= (op & UINT64_C(32)) << 7;
15571 Value |= (op & UINT64_C(31)) << 2;
15572 // op: rd
15573 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15574 op &= UINT64_C(31);
15575 op <<= 7;
15576 Value |= op;
15577 break;
15578 }
15579 case RISCV::InsnCIW: {
15580 // op: opcode
15581 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15582 op &= UINT64_C(3);
15583 Value |= op;
15584 // op: funct3
15585 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15586 op &= UINT64_C(7);
15587 op <<= 13;
15588 Value |= op;
15589 // op: imm8
15590 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15591 op &= UINT64_C(255);
15592 op <<= 5;
15593 Value |= op;
15594 // op: rd
15595 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15596 op &= UINT64_C(7);
15597 op <<= 2;
15598 Value |= op;
15599 break;
15600 }
15601 case RISCV::InsnCR: {
15602 // op: opcode
15603 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15604 op &= UINT64_C(3);
15605 Value |= op;
15606 // op: funct4
15607 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15608 op &= UINT64_C(15);
15609 op <<= 12;
15610 Value |= op;
15611 // op: rs2
15612 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15613 op &= UINT64_C(31);
15614 op <<= 2;
15615 Value |= op;
15616 // op: rd
15617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15618 op &= UINT64_C(31);
15619 op <<= 7;
15620 Value |= op;
15621 break;
15622 }
15623 case RISCV::InsnCA: {
15624 // op: opcode
15625 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15626 op &= UINT64_C(3);
15627 Value |= op;
15628 // op: funct6
15629 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15630 op &= UINT64_C(63);
15631 op <<= 10;
15632 Value |= op;
15633 // op: funct2
15634 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15635 op &= UINT64_C(3);
15636 op <<= 5;
15637 Value |= op;
15638 // op: rd
15639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15640 op &= UINT64_C(7);
15641 op <<= 7;
15642 Value |= op;
15643 // op: rs2
15644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15645 op &= UINT64_C(7);
15646 op <<= 2;
15647 Value |= op;
15648 break;
15649 }
15650 case RISCV::FENCE: {
15651 // op: pred
15652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15653 op &= UINT64_C(15);
15654 op <<= 24;
15655 Value |= op;
15656 // op: succ
15657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15658 op &= UINT64_C(15);
15659 op <<= 20;
15660 Value |= op;
15661 break;
15662 }
15663 case RISCV::SF_VTZERO_T: {
15664 // op: rd
15665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15666 op &= UINT64_C(15);
15667 op <<= 8;
15668 Value |= op;
15669 break;
15670 }
15671 case RISCV::QC_C_DIR:
15672 case RISCV::SSRDP: {
15673 // op: rd
15674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15675 op &= UINT64_C(31);
15676 op <<= 7;
15677 Value |= op;
15678 break;
15679 }
15680 case RISCV::QC_E_LI: {
15681 // op: rd
15682 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15683 op &= UINT64_C(31);
15684 op <<= 7;
15685 Value |= op;
15686 // op: imm
15687 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15688 op &= UINT64_C(4294967295);
15689 op <<= 16;
15690 Value |= op;
15691 break;
15692 }
15693 case RISCV::FLI_D:
15694 case RISCV::FLI_H:
15695 case RISCV::FLI_Q:
15696 case RISCV::FLI_S: {
15697 // op: rd
15698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15699 op &= UINT64_C(31);
15700 op <<= 7;
15701 Value |= op;
15702 // op: imm
15703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15704 op &= UINT64_C(31);
15705 op <<= 15;
15706 Value |= op;
15707 break;
15708 }
15709 case RISCV::PLI_H:
15710 case RISCV::PLI_W:
15711 case RISCV::PLUI_H:
15712 case RISCV::PLUI_W: {
15713 // op: rd
15714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15715 op &= UINT64_C(31);
15716 op <<= 7;
15717 Value |= op;
15718 // op: imm10
15719 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15720 Value |= (op & UINT64_C(511)) << 16;
15721 Value |= (op & UINT64_C(512)) << 6;
15722 break;
15723 }
15724 case RISCV::QC_INSBI: {
15725 // op: rd
15726 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15727 op &= UINT64_C(31);
15728 op <<= 7;
15729 Value |= op;
15730 // op: imm5
15731 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15732 op &= UINT64_C(31);
15733 op <<= 15;
15734 Value |= op;
15735 // op: shamt
15736 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15737 op &= UINT64_C(31);
15738 op <<= 20;
15739 Value |= op;
15740 // op: width
15741 op = getImmOpValueMinus1(MI, OpNo: 2, Fixups, STI);
15742 op &= UINT64_C(31);
15743 op <<= 25;
15744 Value |= op;
15745 break;
15746 }
15747 case RISCV::QC_E_ADDI:
15748 case RISCV::QC_E_ANDI:
15749 case RISCV::QC_E_LB:
15750 case RISCV::QC_E_LBU:
15751 case RISCV::QC_E_LH:
15752 case RISCV::QC_E_LHU:
15753 case RISCV::QC_E_LW:
15754 case RISCV::QC_E_ORI:
15755 case RISCV::QC_E_XORI: {
15756 // op: rd
15757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15758 op &= UINT64_C(31);
15759 op <<= 7;
15760 Value |= op;
15761 // op: rs1
15762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15763 op &= UINT64_C(31);
15764 op <<= 15;
15765 Value |= op;
15766 // op: imm
15767 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15768 Value |= (op & UINT64_C(67107840)) << 22;
15769 Value |= (op & UINT64_C(1023)) << 20;
15770 break;
15771 }
15772 case RISCV::NDS_BFOS:
15773 case RISCV::NDS_BFOZ: {
15774 // op: rd
15775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15776 op &= UINT64_C(31);
15777 op <<= 7;
15778 Value |= op;
15779 // op: rs1
15780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15781 op &= UINT64_C(31);
15782 op <<= 15;
15783 Value |= op;
15784 // op: msb
15785 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15786 op &= UINT64_C(63);
15787 op <<= 26;
15788 Value |= op;
15789 // op: lsb
15790 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15791 op &= UINT64_C(63);
15792 op <<= 20;
15793 Value |= op;
15794 break;
15795 }
15796 case RISCV::PLI_B: {
15797 // op: rd
15798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15799 op &= UINT64_C(31);
15800 op <<= 7;
15801 Value |= op;
15802 // op: uimm8
15803 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
15804 op &= UINT64_C(255);
15805 op <<= 16;
15806 Value |= op;
15807 break;
15808 }
15809 case RISCV::QK_C_LBU: {
15810 // op: rd
15811 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15812 op &= UINT64_C(7);
15813 op <<= 2;
15814 Value |= op;
15815 // op: rs1
15816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15817 op &= UINT64_C(7);
15818 op <<= 7;
15819 Value |= op;
15820 // op: imm
15821 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15822 Value |= (op & UINT64_C(1)) << 12;
15823 Value |= (op & UINT64_C(24)) << 7;
15824 Value |= (op & UINT64_C(6)) << 4;
15825 break;
15826 }
15827 case RISCV::C_LBU: {
15828 // op: rd
15829 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15830 op &= UINT64_C(7);
15831 op <<= 2;
15832 Value |= op;
15833 // op: rs1
15834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15835 op &= UINT64_C(7);
15836 op <<= 7;
15837 Value |= op;
15838 // op: imm
15839 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15840 Value |= (op & UINT64_C(1)) << 6;
15841 Value |= (op & UINT64_C(2)) << 4;
15842 break;
15843 }
15844 case RISCV::C_FLD:
15845 case RISCV::C_LD:
15846 case RISCV::C_LD_RV32: {
15847 // op: rd
15848 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15849 op &= UINT64_C(7);
15850 op <<= 2;
15851 Value |= op;
15852 // op: rs1
15853 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15854 op &= UINT64_C(7);
15855 op <<= 7;
15856 Value |= op;
15857 // op: imm
15858 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15859 Value |= (op & UINT64_C(56)) << 7;
15860 Value |= (op & UINT64_C(192)) >> 1;
15861 break;
15862 }
15863 case RISCV::C_FLW:
15864 case RISCV::C_LW:
15865 case RISCV::C_LW_INX: {
15866 // op: rd
15867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15868 op &= UINT64_C(7);
15869 op <<= 2;
15870 Value |= op;
15871 // op: rs1
15872 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15873 op &= UINT64_C(7);
15874 op <<= 7;
15875 Value |= op;
15876 // op: imm
15877 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15878 Value |= (op & UINT64_C(56)) << 7;
15879 Value |= (op & UINT64_C(4)) << 4;
15880 Value |= (op & UINT64_C(64)) >> 1;
15881 break;
15882 }
15883 case RISCV::QK_C_LHU: {
15884 // op: rd
15885 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15886 op &= UINT64_C(7);
15887 op <<= 2;
15888 Value |= op;
15889 // op: rs1
15890 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15891 op &= UINT64_C(7);
15892 op <<= 7;
15893 Value |= op;
15894 // op: imm
15895 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15896 Value |= (op & UINT64_C(56)) << 7;
15897 Value |= (op & UINT64_C(6)) << 4;
15898 break;
15899 }
15900 case RISCV::C_LH:
15901 case RISCV::C_LHU:
15902 case RISCV::C_LH_INX: {
15903 // op: rd
15904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15905 op &= UINT64_C(7);
15906 op <<= 2;
15907 Value |= op;
15908 // op: rs1
15909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15910 op &= UINT64_C(7);
15911 op <<= 7;
15912 Value |= op;
15913 // op: imm
15914 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15915 op &= UINT64_C(2);
15916 op <<= 4;
15917 Value |= op;
15918 break;
15919 }
15920 case RISCV::C_ADDI_HINT_IMM_ZERO:
15921 case RISCV::C_SLLI64_HINT: {
15922 // op: rd
15923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15924 op &= UINT64_C(31);
15925 op <<= 7;
15926 Value |= op;
15927 break;
15928 }
15929 case RISCV::QC_E_ADDAI:
15930 case RISCV::QC_E_ANDAI:
15931 case RISCV::QC_E_ORAI:
15932 case RISCV::QC_E_XORAI: {
15933 // op: rd
15934 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15935 op &= UINT64_C(31);
15936 op <<= 7;
15937 Value |= op;
15938 // op: imm
15939 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
15940 op &= UINT64_C(4294967295);
15941 op <<= 16;
15942 Value |= op;
15943 break;
15944 }
15945 case RISCV::QC_C_EXTU: {
15946 // op: rd
15947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15948 op &= UINT64_C(31);
15949 op <<= 7;
15950 Value |= op;
15951 // op: width
15952 op = getImmOpValueMinus1(MI, OpNo: 2, Fixups, STI);
15953 op &= UINT64_C(31);
15954 op <<= 2;
15955 Value |= op;
15956 break;
15957 }
15958 case RISCV::QC_C_MVEQZ: {
15959 // op: rd
15960 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15961 op &= UINT64_C(7);
15962 op <<= 2;
15963 Value |= op;
15964 // op: rs1
15965 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15966 op &= UINT64_C(7);
15967 op <<= 7;
15968 Value |= op;
15969 break;
15970 }
15971 case RISCV::QC_C_MULIADD: {
15972 // op: rd
15973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15974 op &= UINT64_C(7);
15975 op <<= 2;
15976 Value |= op;
15977 // op: rs1
15978 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15979 op &= UINT64_C(7);
15980 op <<= 7;
15981 Value |= op;
15982 // op: uimm
15983 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
15984 Value |= (op & UINT64_C(14)) << 9;
15985 Value |= (op & UINT64_C(1)) << 6;
15986 Value |= (op & UINT64_C(16)) << 1;
15987 break;
15988 }
15989 case RISCV::C_NOT:
15990 case RISCV::C_SEXT_B:
15991 case RISCV::C_SEXT_H:
15992 case RISCV::C_ZEXT_B:
15993 case RISCV::C_ZEXT_H:
15994 case RISCV::C_ZEXT_W: {
15995 // op: rd
15996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15997 op &= UINT64_C(7);
15998 op <<= 7;
15999 Value |= op;
16000 break;
16001 }
16002 case RISCV::QK_C_LHUSP:
16003 case RISCV::QK_C_SHSP: {
16004 // op: rd_rs2
16005 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16006 op &= UINT64_C(7);
16007 op <<= 2;
16008 Value |= op;
16009 // op: imm
16010 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16011 Value |= (op & UINT64_C(14)) << 7;
16012 Value |= (op & UINT64_C(16)) << 3;
16013 break;
16014 }
16015 case RISCV::QK_C_LBUSP:
16016 case RISCV::QK_C_SBSP: {
16017 // op: rd_rs2
16018 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16019 op &= UINT64_C(7);
16020 op <<= 2;
16021 Value |= op;
16022 // op: imm
16023 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16024 op &= UINT64_C(15);
16025 op <<= 7;
16026 Value |= op;
16027 break;
16028 }
16029 case RISCV::CM_POP:
16030 case RISCV::CM_POPRET:
16031 case RISCV::CM_POPRETZ:
16032 case RISCV::CM_PUSH:
16033 case RISCV::QC_CM_POP:
16034 case RISCV::QC_CM_POPRET:
16035 case RISCV::QC_CM_POPRETZ:
16036 case RISCV::QC_CM_PUSH: {
16037 // op: rlist
16038 op = getRlistOpValue(MI, OpNo: 0, Fixups, STI);
16039 op &= UINT64_C(15);
16040 op <<= 4;
16041 Value |= op;
16042 // op: stackadj
16043 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16044 op &= UINT64_C(48);
16045 op >>= 2;
16046 Value |= op;
16047 break;
16048 }
16049 case RISCV::QC_CM_PUSHFP: {
16050 // op: rlist
16051 op = getRlistS0OpValue(MI, OpNo: 0, Fixups, STI);
16052 op &= UINT64_C(15);
16053 op <<= 4;
16054 Value |= op;
16055 // op: stackadj
16056 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16057 op &= UINT64_C(48);
16058 op >>= 2;
16059 Value |= op;
16060 break;
16061 }
16062 case RISCV::CSRRCI:
16063 case RISCV::CSRRSI:
16064 case RISCV::CSRRWI: {
16065 // op: rs1
16066 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16067 op &= UINT64_C(31);
16068 op <<= 15;
16069 Value |= op;
16070 // op: rd
16071 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16072 op &= UINT64_C(31);
16073 op <<= 7;
16074 Value |= op;
16075 // op: imm12
16076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16077 op &= UINT64_C(4095);
16078 op <<= 20;
16079 Value |= op;
16080 break;
16081 }
16082 case RISCV::CBO_CLEAN:
16083 case RISCV::CBO_FLUSH:
16084 case RISCV::CBO_INVAL:
16085 case RISCV::CBO_ZERO:
16086 case RISCV::QC_PEXIT:
16087 case RISCV::QC_PPREG:
16088 case RISCV::QC_PPUTC:
16089 case RISCV::QC_PPUTS:
16090 case RISCV::QC_PSYSCALL:
16091 case RISCV::SF_CDISCARD_D_L1:
16092 case RISCV::SF_CFLUSH_D_L1:
16093 case RISCV::SSPOPCHK:
16094 case RISCV::TH_DCACHE_CIPA:
16095 case RISCV::TH_DCACHE_CISW:
16096 case RISCV::TH_DCACHE_CIVA:
16097 case RISCV::TH_DCACHE_CPA:
16098 case RISCV::TH_DCACHE_CPAL1:
16099 case RISCV::TH_DCACHE_CSW:
16100 case RISCV::TH_DCACHE_CVA:
16101 case RISCV::TH_DCACHE_CVAL1:
16102 case RISCV::TH_DCACHE_IPA:
16103 case RISCV::TH_DCACHE_ISW:
16104 case RISCV::TH_DCACHE_IVA:
16105 case RISCV::TH_ICACHE_IPA:
16106 case RISCV::TH_ICACHE_IVA: {
16107 // op: rs1
16108 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16109 op &= UINT64_C(31);
16110 op <<= 15;
16111 Value |= op;
16112 break;
16113 }
16114 case RISCV::QC_E_BEQI:
16115 case RISCV::QC_E_BGEI:
16116 case RISCV::QC_E_BGEUI:
16117 case RISCV::QC_E_BLTI:
16118 case RISCV::QC_E_BLTUI:
16119 case RISCV::QC_E_BNEI: {
16120 // op: rs1
16121 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16122 op &= UINT64_C(31);
16123 op <<= 15;
16124 Value |= op;
16125 // op: imm16
16126 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16127 op &= UINT64_C(65535);
16128 op <<= 32;
16129 Value |= op;
16130 // op: imm12
16131 op = getImmOpValueAsrN<1>(MI, OpNo: 2, Fixups, STI);
16132 Value |= (op & UINT64_C(2048)) << 20;
16133 Value |= (op & UINT64_C(1008)) << 21;
16134 Value |= (op & UINT64_C(15)) << 8;
16135 Value |= (op & UINT64_C(1024)) >> 3;
16136 break;
16137 }
16138 case RISCV::C_JALR:
16139 case RISCV::C_JR:
16140 case RISCV::QC_C_CLRINT:
16141 case RISCV::QC_C_EIR:
16142 case RISCV::QC_C_SETINT: {
16143 // op: rs1
16144 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16145 op &= UINT64_C(31);
16146 op <<= 7;
16147 Value |= op;
16148 break;
16149 }
16150 case RISCV::C_MV: {
16151 // op: rs1
16152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16153 op &= UINT64_C(31);
16154 op <<= 7;
16155 Value |= op;
16156 // op: rs2
16157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16158 op &= UINT64_C(31);
16159 op <<= 2;
16160 Value |= op;
16161 break;
16162 }
16163 case RISCV::FCVTMOD_W_D:
16164 case RISCV::FCVT_BF16_S:
16165 case RISCV::FCVT_D_H:
16166 case RISCV::FCVT_D_H_IN32X:
16167 case RISCV::FCVT_D_H_INX:
16168 case RISCV::FCVT_D_L:
16169 case RISCV::FCVT_D_LU:
16170 case RISCV::FCVT_D_LU_INX:
16171 case RISCV::FCVT_D_L_INX:
16172 case RISCV::FCVT_D_Q:
16173 case RISCV::FCVT_D_S:
16174 case RISCV::FCVT_D_S_IN32X:
16175 case RISCV::FCVT_D_S_INX:
16176 case RISCV::FCVT_D_W:
16177 case RISCV::FCVT_D_WU:
16178 case RISCV::FCVT_D_WU_IN32X:
16179 case RISCV::FCVT_D_WU_INX:
16180 case RISCV::FCVT_D_W_IN32X:
16181 case RISCV::FCVT_D_W_INX:
16182 case RISCV::FCVT_H_D:
16183 case RISCV::FCVT_H_D_IN32X:
16184 case RISCV::FCVT_H_D_INX:
16185 case RISCV::FCVT_H_L:
16186 case RISCV::FCVT_H_LU:
16187 case RISCV::FCVT_H_LU_INX:
16188 case RISCV::FCVT_H_L_INX:
16189 case RISCV::FCVT_H_S:
16190 case RISCV::FCVT_H_S_INX:
16191 case RISCV::FCVT_H_W:
16192 case RISCV::FCVT_H_WU:
16193 case RISCV::FCVT_H_WU_INX:
16194 case RISCV::FCVT_H_W_INX:
16195 case RISCV::FCVT_LU_D:
16196 case RISCV::FCVT_LU_D_INX:
16197 case RISCV::FCVT_LU_H:
16198 case RISCV::FCVT_LU_H_INX:
16199 case RISCV::FCVT_LU_Q:
16200 case RISCV::FCVT_LU_S:
16201 case RISCV::FCVT_LU_S_INX:
16202 case RISCV::FCVT_L_D:
16203 case RISCV::FCVT_L_D_INX:
16204 case RISCV::FCVT_L_H:
16205 case RISCV::FCVT_L_H_INX:
16206 case RISCV::FCVT_L_Q:
16207 case RISCV::FCVT_L_S:
16208 case RISCV::FCVT_L_S_INX:
16209 case RISCV::FCVT_Q_D:
16210 case RISCV::FCVT_Q_L:
16211 case RISCV::FCVT_Q_LU:
16212 case RISCV::FCVT_Q_S:
16213 case RISCV::FCVT_Q_W:
16214 case RISCV::FCVT_Q_WU:
16215 case RISCV::FCVT_S_BF16:
16216 case RISCV::FCVT_S_D:
16217 case RISCV::FCVT_S_D_IN32X:
16218 case RISCV::FCVT_S_D_INX:
16219 case RISCV::FCVT_S_H:
16220 case RISCV::FCVT_S_H_INX:
16221 case RISCV::FCVT_S_L:
16222 case RISCV::FCVT_S_LU:
16223 case RISCV::FCVT_S_LU_INX:
16224 case RISCV::FCVT_S_L_INX:
16225 case RISCV::FCVT_S_Q:
16226 case RISCV::FCVT_S_W:
16227 case RISCV::FCVT_S_WU:
16228 case RISCV::FCVT_S_WU_INX:
16229 case RISCV::FCVT_S_W_INX:
16230 case RISCV::FCVT_WU_D:
16231 case RISCV::FCVT_WU_D_IN32X:
16232 case RISCV::FCVT_WU_D_INX:
16233 case RISCV::FCVT_WU_H:
16234 case RISCV::FCVT_WU_H_INX:
16235 case RISCV::FCVT_WU_Q:
16236 case RISCV::FCVT_WU_S:
16237 case RISCV::FCVT_WU_S_INX:
16238 case RISCV::FCVT_W_D:
16239 case RISCV::FCVT_W_D_IN32X:
16240 case RISCV::FCVT_W_D_INX:
16241 case RISCV::FCVT_W_H:
16242 case RISCV::FCVT_W_H_INX:
16243 case RISCV::FCVT_W_Q:
16244 case RISCV::FCVT_W_S:
16245 case RISCV::FCVT_W_S_INX:
16246 case RISCV::FROUNDNX_D:
16247 case RISCV::FROUNDNX_H:
16248 case RISCV::FROUNDNX_Q:
16249 case RISCV::FROUNDNX_S:
16250 case RISCV::FROUND_D:
16251 case RISCV::FROUND_H:
16252 case RISCV::FROUND_Q:
16253 case RISCV::FROUND_S:
16254 case RISCV::FSQRT_D:
16255 case RISCV::FSQRT_D_IN32X:
16256 case RISCV::FSQRT_D_INX:
16257 case RISCV::FSQRT_H:
16258 case RISCV::FSQRT_H_INX:
16259 case RISCV::FSQRT_Q:
16260 case RISCV::FSQRT_S:
16261 case RISCV::FSQRT_S_INX: {
16262 // op: rs1
16263 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16264 op &= UINT64_C(31);
16265 op <<= 15;
16266 Value |= op;
16267 // op: frm
16268 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16269 op &= UINT64_C(7);
16270 op <<= 12;
16271 Value |= op;
16272 // op: rd
16273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16274 op &= UINT64_C(31);
16275 op <<= 7;
16276 Value |= op;
16277 break;
16278 }
16279 case RISCV::ABS:
16280 case RISCV::ABSW:
16281 case RISCV::AES64IM:
16282 case RISCV::BREV8:
16283 case RISCV::CLS:
16284 case RISCV::CLSW:
16285 case RISCV::CLZ:
16286 case RISCV::CLZW:
16287 case RISCV::CPOP:
16288 case RISCV::CPOPW:
16289 case RISCV::CTZ:
16290 case RISCV::CTZW:
16291 case RISCV::CV_ABS:
16292 case RISCV::CV_ABS_B:
16293 case RISCV::CV_ABS_H:
16294 case RISCV::CV_CLB:
16295 case RISCV::CV_CNT:
16296 case RISCV::CV_CPLXCONJ:
16297 case RISCV::CV_EXTBS:
16298 case RISCV::CV_EXTBZ:
16299 case RISCV::CV_EXTHS:
16300 case RISCV::CV_EXTHZ:
16301 case RISCV::CV_FF1:
16302 case RISCV::CV_FL1:
16303 case RISCV::FCLASS_D:
16304 case RISCV::FCLASS_D_IN32X:
16305 case RISCV::FCLASS_D_INX:
16306 case RISCV::FCLASS_H:
16307 case RISCV::FCLASS_H_INX:
16308 case RISCV::FCLASS_Q:
16309 case RISCV::FCLASS_S:
16310 case RISCV::FCLASS_S_INX:
16311 case RISCV::FMVH_X_D:
16312 case RISCV::FMVH_X_Q:
16313 case RISCV::FMV_D_X:
16314 case RISCV::FMV_H_X:
16315 case RISCV::FMV_W_X:
16316 case RISCV::FMV_X_D:
16317 case RISCV::FMV_X_H:
16318 case RISCV::FMV_X_W:
16319 case RISCV::FMV_X_W_FPR64:
16320 case RISCV::HLVX_HU:
16321 case RISCV::HLVX_WU:
16322 case RISCV::HLV_B:
16323 case RISCV::HLV_BU:
16324 case RISCV::HLV_D:
16325 case RISCV::HLV_H:
16326 case RISCV::HLV_HU:
16327 case RISCV::HLV_W:
16328 case RISCV::HLV_WU:
16329 case RISCV::LB_AQ:
16330 case RISCV::LB_AQ_RL:
16331 case RISCV::LD_AQ:
16332 case RISCV::LD_AQ_RL:
16333 case RISCV::LH_AQ:
16334 case RISCV::LH_AQ_RL:
16335 case RISCV::LR_D:
16336 case RISCV::LR_D_AQ:
16337 case RISCV::LR_D_AQ_RL:
16338 case RISCV::LR_D_RL:
16339 case RISCV::LR_W:
16340 case RISCV::LR_W_AQ:
16341 case RISCV::LR_W_AQ_RL:
16342 case RISCV::LR_W_RL:
16343 case RISCV::LW_AQ:
16344 case RISCV::LW_AQ_RL:
16345 case RISCV::MOPR0:
16346 case RISCV::MOPR1:
16347 case RISCV::MOPR2:
16348 case RISCV::MOPR3:
16349 case RISCV::MOPR4:
16350 case RISCV::MOPR5:
16351 case RISCV::MOPR6:
16352 case RISCV::MOPR7:
16353 case RISCV::MOPR8:
16354 case RISCV::MOPR9:
16355 case RISCV::MOPR10:
16356 case RISCV::MOPR11:
16357 case RISCV::MOPR12:
16358 case RISCV::MOPR13:
16359 case RISCV::MOPR14:
16360 case RISCV::MOPR15:
16361 case RISCV::MOPR16:
16362 case RISCV::MOPR17:
16363 case RISCV::MOPR18:
16364 case RISCV::MOPR19:
16365 case RISCV::MOPR20:
16366 case RISCV::MOPR21:
16367 case RISCV::MOPR22:
16368 case RISCV::MOPR23:
16369 case RISCV::MOPR24:
16370 case RISCV::MOPR25:
16371 case RISCV::MOPR26:
16372 case RISCV::MOPR27:
16373 case RISCV::MOPR28:
16374 case RISCV::MOPR29:
16375 case RISCV::MOPR30:
16376 case RISCV::MOPR31:
16377 case RISCV::ORC_B:
16378 case RISCV::PSABS_B:
16379 case RISCV::PSABS_H:
16380 case RISCV::PSEXT_H_B:
16381 case RISCV::PSEXT_W_B:
16382 case RISCV::PSEXT_W_H:
16383 case RISCV::QC_BREV32:
16384 case RISCV::QC_CLO:
16385 case RISCV::QC_COMPRESS2:
16386 case RISCV::QC_COMPRESS3:
16387 case RISCV::QC_CTO:
16388 case RISCV::QC_EXPAND2:
16389 case RISCV::QC_EXPAND3:
16390 case RISCV::QC_NORM:
16391 case RISCV::QC_NORMEU:
16392 case RISCV::QC_NORMU:
16393 case RISCV::REV8_RV32:
16394 case RISCV::REV8_RV64:
16395 case RISCV::REV16:
16396 case RISCV::REV_RV32:
16397 case RISCV::REV_RV64:
16398 case RISCV::SEXT_B:
16399 case RISCV::SEXT_H:
16400 case RISCV::SF_VSETTK:
16401 case RISCV::SF_VSETTM:
16402 case RISCV::SF_VSETTN:
16403 case RISCV::SHA256SIG0:
16404 case RISCV::SHA256SIG1:
16405 case RISCV::SHA256SUM0:
16406 case RISCV::SHA256SUM1:
16407 case RISCV::SHA512SIG0:
16408 case RISCV::SHA512SIG1:
16409 case RISCV::SHA512SUM0:
16410 case RISCV::SHA512SUM1:
16411 case RISCV::SM3P0:
16412 case RISCV::SM3P1:
16413 case RISCV::TH_FF0:
16414 case RISCV::TH_FF1:
16415 case RISCV::TH_REV:
16416 case RISCV::TH_REVW:
16417 case RISCV::TH_TSTNBZ:
16418 case RISCV::UNZIP_RV32:
16419 case RISCV::ZEXT_H_RV32:
16420 case RISCV::ZEXT_H_RV64:
16421 case RISCV::ZIP_RV32: {
16422 // op: rs1
16423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16424 op &= UINT64_C(31);
16425 op <<= 15;
16426 Value |= op;
16427 // op: rd
16428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16429 op &= UINT64_C(31);
16430 op <<= 7;
16431 Value |= op;
16432 break;
16433 }
16434 case RISCV::QC_INSBRI:
16435 case RISCV::QC_WRAPI: {
16436 // op: rs1
16437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16438 op &= UINT64_C(31);
16439 op <<= 15;
16440 Value |= op;
16441 // op: rd
16442 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16443 op &= UINT64_C(31);
16444 op <<= 7;
16445 Value |= op;
16446 // op: imm11
16447 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16448 op &= UINT64_C(2047);
16449 op <<= 20;
16450 Value |= op;
16451 break;
16452 }
16453 case RISCV::ADDI:
16454 case RISCV::ADDIW:
16455 case RISCV::ANDI:
16456 case RISCV::CV_ELW:
16457 case RISCV::FLD:
16458 case RISCV::FLH:
16459 case RISCV::FLQ:
16460 case RISCV::FLW:
16461 case RISCV::JALR:
16462 case RISCV::LB:
16463 case RISCV::LBU:
16464 case RISCV::LD:
16465 case RISCV::LD_RV32:
16466 case RISCV::LH:
16467 case RISCV::LHU:
16468 case RISCV::LH_INX:
16469 case RISCV::LW:
16470 case RISCV::LWU:
16471 case RISCV::LW_INX:
16472 case RISCV::ORI:
16473 case RISCV::SLTI:
16474 case RISCV::SLTIU:
16475 case RISCV::XORI: {
16476 // op: rs1
16477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16478 op &= UINT64_C(31);
16479 op <<= 15;
16480 Value |= op;
16481 // op: rd
16482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16483 op &= UINT64_C(31);
16484 op <<= 7;
16485 Value |= op;
16486 // op: imm12
16487 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16488 op &= UINT64_C(4095);
16489 op <<= 20;
16490 Value |= op;
16491 break;
16492 }
16493 case RISCV::QC_INW: {
16494 // op: rs1
16495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16496 op &= UINT64_C(31);
16497 op <<= 15;
16498 Value |= op;
16499 // op: rd
16500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16501 op &= UINT64_C(31);
16502 op <<= 7;
16503 Value |= op;
16504 // op: imm14
16505 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16506 op &= UINT64_C(16380);
16507 op <<= 18;
16508 Value |= op;
16509 break;
16510 }
16511 case RISCV::CV_CLIP:
16512 case RISCV::CV_CLIPU: {
16513 // op: rs1
16514 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16515 op &= UINT64_C(31);
16516 op <<= 15;
16517 Value |= op;
16518 // op: rd
16519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16520 op &= UINT64_C(31);
16521 op <<= 7;
16522 Value |= op;
16523 // op: imm5
16524 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16525 op &= UINT64_C(31);
16526 op <<= 20;
16527 Value |= op;
16528 break;
16529 }
16530 case RISCV::CV_ADD_SCI_B:
16531 case RISCV::CV_ADD_SCI_H:
16532 case RISCV::CV_AND_SCI_B:
16533 case RISCV::CV_AND_SCI_H:
16534 case RISCV::CV_AVGU_SCI_B:
16535 case RISCV::CV_AVGU_SCI_H:
16536 case RISCV::CV_AVG_SCI_B:
16537 case RISCV::CV_AVG_SCI_H:
16538 case RISCV::CV_CMPEQ_SCI_B:
16539 case RISCV::CV_CMPEQ_SCI_H:
16540 case RISCV::CV_CMPGEU_SCI_B:
16541 case RISCV::CV_CMPGEU_SCI_H:
16542 case RISCV::CV_CMPGE_SCI_B:
16543 case RISCV::CV_CMPGE_SCI_H:
16544 case RISCV::CV_CMPGTU_SCI_B:
16545 case RISCV::CV_CMPGTU_SCI_H:
16546 case RISCV::CV_CMPGT_SCI_B:
16547 case RISCV::CV_CMPGT_SCI_H:
16548 case RISCV::CV_CMPLEU_SCI_B:
16549 case RISCV::CV_CMPLEU_SCI_H:
16550 case RISCV::CV_CMPLE_SCI_B:
16551 case RISCV::CV_CMPLE_SCI_H:
16552 case RISCV::CV_CMPLTU_SCI_B:
16553 case RISCV::CV_CMPLTU_SCI_H:
16554 case RISCV::CV_CMPLT_SCI_B:
16555 case RISCV::CV_CMPLT_SCI_H:
16556 case RISCV::CV_CMPNE_SCI_B:
16557 case RISCV::CV_CMPNE_SCI_H:
16558 case RISCV::CV_DOTSP_SCI_B:
16559 case RISCV::CV_DOTSP_SCI_H:
16560 case RISCV::CV_DOTUP_SCI_B:
16561 case RISCV::CV_DOTUP_SCI_H:
16562 case RISCV::CV_DOTUSP_SCI_B:
16563 case RISCV::CV_DOTUSP_SCI_H:
16564 case RISCV::CV_EXTRACTU_B:
16565 case RISCV::CV_EXTRACTU_H:
16566 case RISCV::CV_EXTRACT_B:
16567 case RISCV::CV_EXTRACT_H:
16568 case RISCV::CV_MAXU_SCI_B:
16569 case RISCV::CV_MAXU_SCI_H:
16570 case RISCV::CV_MAX_SCI_B:
16571 case RISCV::CV_MAX_SCI_H:
16572 case RISCV::CV_MINU_SCI_B:
16573 case RISCV::CV_MINU_SCI_H:
16574 case RISCV::CV_MIN_SCI_B:
16575 case RISCV::CV_MIN_SCI_H:
16576 case RISCV::CV_OR_SCI_B:
16577 case RISCV::CV_OR_SCI_H:
16578 case RISCV::CV_SHUFFLEI0_SCI_B:
16579 case RISCV::CV_SHUFFLEI1_SCI_B:
16580 case RISCV::CV_SHUFFLEI2_SCI_B:
16581 case RISCV::CV_SHUFFLEI3_SCI_B:
16582 case RISCV::CV_SHUFFLE_SCI_H:
16583 case RISCV::CV_SLL_SCI_B:
16584 case RISCV::CV_SLL_SCI_H:
16585 case RISCV::CV_SRA_SCI_B:
16586 case RISCV::CV_SRA_SCI_H:
16587 case RISCV::CV_SRL_SCI_B:
16588 case RISCV::CV_SRL_SCI_H:
16589 case RISCV::CV_SUB_SCI_B:
16590 case RISCV::CV_SUB_SCI_H:
16591 case RISCV::CV_XOR_SCI_B:
16592 case RISCV::CV_XOR_SCI_H: {
16593 // op: rs1
16594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16595 op &= UINT64_C(31);
16596 op <<= 15;
16597 Value |= op;
16598 // op: rd
16599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16600 op &= UINT64_C(31);
16601 op <<= 7;
16602 Value |= op;
16603 // op: imm6
16604 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16605 Value |= (op & UINT64_C(1)) << 25;
16606 Value |= (op & UINT64_C(62)) << 19;
16607 break;
16608 }
16609 case RISCV::CV_BCLR:
16610 case RISCV::CV_BITREV:
16611 case RISCV::CV_BSET:
16612 case RISCV::CV_EXTRACT:
16613 case RISCV::CV_EXTRACTU: {
16614 // op: rs1
16615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16616 op &= UINT64_C(31);
16617 op <<= 15;
16618 Value |= op;
16619 // op: rd
16620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16621 op &= UINT64_C(31);
16622 op <<= 7;
16623 Value |= op;
16624 // op: is3
16625 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16626 op &= UINT64_C(31);
16627 op <<= 25;
16628 Value |= op;
16629 // op: is2
16630 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
16631 op &= UINT64_C(31);
16632 op <<= 20;
16633 Value |= op;
16634 break;
16635 }
16636 case RISCV::TH_EXT:
16637 case RISCV::TH_EXTU: {
16638 // op: rs1
16639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16640 op &= UINT64_C(31);
16641 op <<= 15;
16642 Value |= op;
16643 // op: rd
16644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16645 op &= UINT64_C(31);
16646 op <<= 7;
16647 Value |= op;
16648 // op: msb
16649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16650 op &= UINT64_C(63);
16651 op <<= 26;
16652 Value |= op;
16653 // op: lsb
16654 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16655 op &= UINT64_C(63);
16656 op <<= 20;
16657 Value |= op;
16658 break;
16659 }
16660 case RISCV::AES64KS1I: {
16661 // op: rs1
16662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16663 op &= UINT64_C(31);
16664 op <<= 15;
16665 Value |= op;
16666 // op: rd
16667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16668 op &= UINT64_C(31);
16669 op <<= 7;
16670 Value |= op;
16671 // op: rnum
16672 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16673 op &= UINT64_C(15);
16674 op <<= 20;
16675 Value |= op;
16676 break;
16677 }
16678 case RISCV::RORIW:
16679 case RISCV::SLLIW:
16680 case RISCV::SRAIW:
16681 case RISCV::SRLIW:
16682 case RISCV::TH_SRRIW: {
16683 // op: rs1
16684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16685 op &= UINT64_C(31);
16686 op <<= 15;
16687 Value |= op;
16688 // op: rd
16689 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16690 op &= UINT64_C(31);
16691 op <<= 7;
16692 Value |= op;
16693 // op: shamt
16694 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16695 op &= UINT64_C(31);
16696 op <<= 20;
16697 Value |= op;
16698 break;
16699 }
16700 case RISCV::QC_EXT:
16701 case RISCV::QC_EXTD:
16702 case RISCV::QC_EXTDU:
16703 case RISCV::QC_EXTU:
16704 case RISCV::QC_INSB:
16705 case RISCV::QC_INSBH: {
16706 // op: rs1
16707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16708 op &= UINT64_C(31);
16709 op <<= 15;
16710 Value |= op;
16711 // op: rd
16712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16713 op &= UINT64_C(31);
16714 op <<= 7;
16715 Value |= op;
16716 // op: shamt
16717 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
16718 op &= UINT64_C(31);
16719 op <<= 20;
16720 Value |= op;
16721 // op: width
16722 op = getImmOpValueMinus1(MI, OpNo: 2, Fixups, STI);
16723 op &= UINT64_C(31);
16724 op <<= 25;
16725 Value |= op;
16726 break;
16727 }
16728 case RISCV::BCLRI:
16729 case RISCV::BEXTI:
16730 case RISCV::BINVI:
16731 case RISCV::BSETI:
16732 case RISCV::RORI:
16733 case RISCV::SLLI:
16734 case RISCV::SLLI_UW:
16735 case RISCV::SRAI:
16736 case RISCV::SRLI:
16737 case RISCV::TH_SRRI:
16738 case RISCV::TH_TST: {
16739 // op: rs1
16740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16741 op &= UINT64_C(31);
16742 op <<= 15;
16743 Value |= op;
16744 // op: rd
16745 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16746 op &= UINT64_C(31);
16747 op <<= 7;
16748 Value |= op;
16749 // op: shamt
16750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16751 op &= UINT64_C(63);
16752 op <<= 20;
16753 Value |= op;
16754 break;
16755 }
16756 case RISCV::PSLLI_B: {
16757 // op: rs1
16758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16759 op &= UINT64_C(31);
16760 op <<= 15;
16761 Value |= op;
16762 // op: rd
16763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16764 op &= UINT64_C(31);
16765 op <<= 7;
16766 Value |= op;
16767 // op: uimm3
16768 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16769 op &= UINT64_C(7);
16770 op <<= 20;
16771 Value |= op;
16772 break;
16773 }
16774 case RISCV::PSLLI_H:
16775 case RISCV::PSSLAI_H: {
16776 // op: rs1
16777 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16778 op &= UINT64_C(31);
16779 op <<= 15;
16780 Value |= op;
16781 // op: rd
16782 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16783 op &= UINT64_C(31);
16784 op <<= 7;
16785 Value |= op;
16786 // op: uimm4
16787 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16788 op &= UINT64_C(15);
16789 op <<= 20;
16790 Value |= op;
16791 break;
16792 }
16793 case RISCV::PSLLI_W:
16794 case RISCV::PSSLAI_W:
16795 case RISCV::SSLAI: {
16796 // op: rs1
16797 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16798 op &= UINT64_C(31);
16799 op <<= 15;
16800 Value |= op;
16801 // op: rd
16802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16803 op &= UINT64_C(31);
16804 op <<= 7;
16805 Value |= op;
16806 // op: uimm5
16807 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16808 op &= UINT64_C(31);
16809 op <<= 20;
16810 Value |= op;
16811 break;
16812 }
16813 case RISCV::VSETVLI: {
16814 // op: rs1
16815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16816 op &= UINT64_C(31);
16817 op <<= 15;
16818 Value |= op;
16819 // op: rd
16820 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16821 op &= UINT64_C(31);
16822 op <<= 7;
16823 Value |= op;
16824 // op: vtypei
16825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16826 op &= UINT64_C(2047);
16827 op <<= 20;
16828 Value |= op;
16829 break;
16830 }
16831 case RISCV::QC_E_SB:
16832 case RISCV::QC_E_SH:
16833 case RISCV::QC_E_SW: {
16834 // op: rs1
16835 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16836 op &= UINT64_C(31);
16837 op <<= 15;
16838 Value |= op;
16839 // op: rs2
16840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16841 op &= UINT64_C(31);
16842 op <<= 20;
16843 Value |= op;
16844 // op: imm
16845 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16846 Value |= (op & UINT64_C(67107840)) << 22;
16847 Value |= (op & UINT64_C(992)) << 20;
16848 Value |= (op & UINT64_C(31)) << 7;
16849 break;
16850 }
16851 case RISCV::CV_SB_rr:
16852 case RISCV::CV_SH_rr:
16853 case RISCV::CV_SW_rr: {
16854 // op: rs1
16855 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16856 op &= UINT64_C(31);
16857 op <<= 15;
16858 Value |= op;
16859 // op: rs2
16860 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16861 op &= UINT64_C(31);
16862 op <<= 20;
16863 Value |= op;
16864 // op: rs3
16865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16866 op &= UINT64_C(31);
16867 op <<= 7;
16868 Value |= op;
16869 break;
16870 }
16871 case RISCV::QC_OUTW: {
16872 // op: rs1
16873 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16874 op &= UINT64_C(31);
16875 op <<= 15;
16876 Value |= op;
16877 // op: rs2
16878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16879 op &= UINT64_C(31);
16880 op <<= 7;
16881 Value |= op;
16882 // op: imm14
16883 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
16884 op &= UINT64_C(16380);
16885 op <<= 18;
16886 Value |= op;
16887 break;
16888 }
16889 case RISCV::SF_VTMV_V_T:
16890 case RISCV::VFMV_V_F:
16891 case RISCV::VL1RE8_V:
16892 case RISCV::VL1RE16_V:
16893 case RISCV::VL1RE32_V:
16894 case RISCV::VL1RE64_V:
16895 case RISCV::VL2RE8_V:
16896 case RISCV::VL2RE16_V:
16897 case RISCV::VL2RE32_V:
16898 case RISCV::VL2RE64_V:
16899 case RISCV::VL4RE8_V:
16900 case RISCV::VL4RE16_V:
16901 case RISCV::VL4RE32_V:
16902 case RISCV::VL4RE64_V:
16903 case RISCV::VL8RE8_V:
16904 case RISCV::VL8RE16_V:
16905 case RISCV::VL8RE32_V:
16906 case RISCV::VL8RE64_V:
16907 case RISCV::VLM_V:
16908 case RISCV::VMV_V_X: {
16909 // op: rs1
16910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16911 op &= UINT64_C(31);
16912 op <<= 15;
16913 Value |= op;
16914 // op: vd
16915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16916 op &= UINT64_C(31);
16917 op <<= 7;
16918 Value |= op;
16919 break;
16920 }
16921 case RISCV::VLE8FF_V:
16922 case RISCV::VLE8_V:
16923 case RISCV::VLE16FF_V:
16924 case RISCV::VLE16_V:
16925 case RISCV::VLE32FF_V:
16926 case RISCV::VLE32_V:
16927 case RISCV::VLE64FF_V:
16928 case RISCV::VLE64_V:
16929 case RISCV::VLSEG2E8FF_V:
16930 case RISCV::VLSEG2E8_V:
16931 case RISCV::VLSEG2E16FF_V:
16932 case RISCV::VLSEG2E16_V:
16933 case RISCV::VLSEG2E32FF_V:
16934 case RISCV::VLSEG2E32_V:
16935 case RISCV::VLSEG2E64FF_V:
16936 case RISCV::VLSEG2E64_V:
16937 case RISCV::VLSEG3E8FF_V:
16938 case RISCV::VLSEG3E8_V:
16939 case RISCV::VLSEG3E16FF_V:
16940 case RISCV::VLSEG3E16_V:
16941 case RISCV::VLSEG3E32FF_V:
16942 case RISCV::VLSEG3E32_V:
16943 case RISCV::VLSEG3E64FF_V:
16944 case RISCV::VLSEG3E64_V:
16945 case RISCV::VLSEG4E8FF_V:
16946 case RISCV::VLSEG4E8_V:
16947 case RISCV::VLSEG4E16FF_V:
16948 case RISCV::VLSEG4E16_V:
16949 case RISCV::VLSEG4E32FF_V:
16950 case RISCV::VLSEG4E32_V:
16951 case RISCV::VLSEG4E64FF_V:
16952 case RISCV::VLSEG4E64_V:
16953 case RISCV::VLSEG5E8FF_V:
16954 case RISCV::VLSEG5E8_V:
16955 case RISCV::VLSEG5E16FF_V:
16956 case RISCV::VLSEG5E16_V:
16957 case RISCV::VLSEG5E32FF_V:
16958 case RISCV::VLSEG5E32_V:
16959 case RISCV::VLSEG5E64FF_V:
16960 case RISCV::VLSEG5E64_V:
16961 case RISCV::VLSEG6E8FF_V:
16962 case RISCV::VLSEG6E8_V:
16963 case RISCV::VLSEG6E16FF_V:
16964 case RISCV::VLSEG6E16_V:
16965 case RISCV::VLSEG6E32FF_V:
16966 case RISCV::VLSEG6E32_V:
16967 case RISCV::VLSEG6E64FF_V:
16968 case RISCV::VLSEG6E64_V:
16969 case RISCV::VLSEG7E8FF_V:
16970 case RISCV::VLSEG7E8_V:
16971 case RISCV::VLSEG7E16FF_V:
16972 case RISCV::VLSEG7E16_V:
16973 case RISCV::VLSEG7E32FF_V:
16974 case RISCV::VLSEG7E32_V:
16975 case RISCV::VLSEG7E64FF_V:
16976 case RISCV::VLSEG7E64_V:
16977 case RISCV::VLSEG8E8FF_V:
16978 case RISCV::VLSEG8E8_V:
16979 case RISCV::VLSEG8E16FF_V:
16980 case RISCV::VLSEG8E16_V:
16981 case RISCV::VLSEG8E32FF_V:
16982 case RISCV::VLSEG8E32_V:
16983 case RISCV::VLSEG8E64FF_V:
16984 case RISCV::VLSEG8E64_V: {
16985 // op: rs1
16986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16987 op &= UINT64_C(31);
16988 op <<= 15;
16989 Value |= op;
16990 // op: vd
16991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16992 op &= UINT64_C(31);
16993 op <<= 7;
16994 Value |= op;
16995 // op: vm
16996 op = getVMaskReg(MI, OpNo: 2, Fixups, STI);
16997 op &= UINT64_C(1);
16998 op <<= 25;
16999 Value |= op;
17000 break;
17001 }
17002 case RISCV::VS1R_V:
17003 case RISCV::VS2R_V:
17004 case RISCV::VS4R_V:
17005 case RISCV::VS8R_V:
17006 case RISCV::VSM_V: {
17007 // op: rs1
17008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17009 op &= UINT64_C(31);
17010 op <<= 15;
17011 Value |= op;
17012 // op: vs3
17013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17014 op &= UINT64_C(31);
17015 op <<= 7;
17016 Value |= op;
17017 break;
17018 }
17019 case RISCV::VSE8_V:
17020 case RISCV::VSE16_V:
17021 case RISCV::VSE32_V:
17022 case RISCV::VSE64_V:
17023 case RISCV::VSSEG2E8_V:
17024 case RISCV::VSSEG2E16_V:
17025 case RISCV::VSSEG2E32_V:
17026 case RISCV::VSSEG2E64_V:
17027 case RISCV::VSSEG3E8_V:
17028 case RISCV::VSSEG3E16_V:
17029 case RISCV::VSSEG3E32_V:
17030 case RISCV::VSSEG3E64_V:
17031 case RISCV::VSSEG4E8_V:
17032 case RISCV::VSSEG4E16_V:
17033 case RISCV::VSSEG4E32_V:
17034 case RISCV::VSSEG4E64_V:
17035 case RISCV::VSSEG5E8_V:
17036 case RISCV::VSSEG5E16_V:
17037 case RISCV::VSSEG5E32_V:
17038 case RISCV::VSSEG5E64_V:
17039 case RISCV::VSSEG6E8_V:
17040 case RISCV::VSSEG6E16_V:
17041 case RISCV::VSSEG6E32_V:
17042 case RISCV::VSSEG6E64_V:
17043 case RISCV::VSSEG7E8_V:
17044 case RISCV::VSSEG7E16_V:
17045 case RISCV::VSSEG7E32_V:
17046 case RISCV::VSSEG7E64_V:
17047 case RISCV::VSSEG8E8_V:
17048 case RISCV::VSSEG8E16_V:
17049 case RISCV::VSSEG8E32_V:
17050 case RISCV::VSSEG8E64_V: {
17051 // op: rs1
17052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17053 op &= UINT64_C(31);
17054 op <<= 15;
17055 Value |= op;
17056 // op: vs3
17057 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17058 op &= UINT64_C(31);
17059 op <<= 7;
17060 Value |= op;
17061 // op: vm
17062 op = getVMaskReg(MI, OpNo: 2, Fixups, STI);
17063 op &= UINT64_C(1);
17064 op <<= 25;
17065 Value |= op;
17066 break;
17067 }
17068 case RISCV::C_ADD: {
17069 // op: rs1
17070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17071 op &= UINT64_C(31);
17072 op <<= 7;
17073 Value |= op;
17074 // op: rs2
17075 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17076 op &= UINT64_C(31);
17077 op <<= 2;
17078 Value |= op;
17079 break;
17080 }
17081 case RISCV::C_SRAI64_HINT:
17082 case RISCV::C_SRLI64_HINT: {
17083 // op: rs1
17084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17085 op &= UINT64_C(7);
17086 op <<= 7;
17087 Value |= op;
17088 break;
17089 }
17090 case RISCV::QC_C_BEXTI:
17091 case RISCV::QC_C_BSETI: {
17092 // op: rs1
17093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17094 op &= UINT64_C(7);
17095 op <<= 7;
17096 Value |= op;
17097 // op: shamt
17098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17099 op &= UINT64_C(31);
17100 op <<= 2;
17101 Value |= op;
17102 break;
17103 }
17104 case RISCV::CV_LBU_ri_inc:
17105 case RISCV::CV_LB_ri_inc:
17106 case RISCV::CV_LHU_ri_inc:
17107 case RISCV::CV_LH_ri_inc:
17108 case RISCV::CV_LW_ri_inc: {
17109 // op: rs1
17110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17111 op &= UINT64_C(31);
17112 op <<= 15;
17113 Value |= op;
17114 // op: rd
17115 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17116 op &= UINT64_C(31);
17117 op <<= 7;
17118 Value |= op;
17119 // op: imm12
17120 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17121 op &= UINT64_C(4095);
17122 op <<= 20;
17123 Value |= op;
17124 break;
17125 }
17126 case RISCV::CSRRC:
17127 case RISCV::CSRRS:
17128 case RISCV::CSRRW: {
17129 // op: rs1
17130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17131 op &= UINT64_C(31);
17132 op <<= 15;
17133 Value |= op;
17134 // op: rd
17135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17136 op &= UINT64_C(31);
17137 op <<= 7;
17138 Value |= op;
17139 // op: imm12
17140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17141 op &= UINT64_C(4095);
17142 op <<= 20;
17143 Value |= op;
17144 break;
17145 }
17146 case RISCV::TH_LBIA:
17147 case RISCV::TH_LBIB:
17148 case RISCV::TH_LBUIA:
17149 case RISCV::TH_LBUIB:
17150 case RISCV::TH_LDIA:
17151 case RISCV::TH_LDIB:
17152 case RISCV::TH_LHIA:
17153 case RISCV::TH_LHIB:
17154 case RISCV::TH_LHUIA:
17155 case RISCV::TH_LHUIB:
17156 case RISCV::TH_LWIA:
17157 case RISCV::TH_LWIB:
17158 case RISCV::TH_LWUIA:
17159 case RISCV::TH_LWUIB: {
17160 // op: rs1
17161 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17162 op &= UINT64_C(31);
17163 op <<= 15;
17164 Value |= op;
17165 // op: rd
17166 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17167 op &= UINT64_C(31);
17168 op <<= 7;
17169 Value |= op;
17170 // op: simm5
17171 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17172 op &= UINT64_C(31);
17173 op <<= 20;
17174 Value |= op;
17175 // op: uimm2
17176 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
17177 op &= UINT64_C(3);
17178 op <<= 25;
17179 Value |= op;
17180 break;
17181 }
17182 case RISCV::QC_MULIADD: {
17183 // op: rs1
17184 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17185 op &= UINT64_C(31);
17186 op <<= 15;
17187 Value |= op;
17188 // op: rd
17189 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17190 op &= UINT64_C(31);
17191 op <<= 7;
17192 Value |= op;
17193 // op: imm12
17194 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17195 op &= UINT64_C(4095);
17196 op <<= 20;
17197 Value |= op;
17198 break;
17199 }
17200 case RISCV::CV_INSERT_B:
17201 case RISCV::CV_INSERT_H:
17202 case RISCV::CV_SDOTSP_SCI_B:
17203 case RISCV::CV_SDOTSP_SCI_H:
17204 case RISCV::CV_SDOTUP_SCI_B:
17205 case RISCV::CV_SDOTUP_SCI_H:
17206 case RISCV::CV_SDOTUSP_SCI_B:
17207 case RISCV::CV_SDOTUSP_SCI_H: {
17208 // op: rs1
17209 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17210 op &= UINT64_C(31);
17211 op <<= 15;
17212 Value |= op;
17213 // op: rd
17214 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17215 op &= UINT64_C(31);
17216 op <<= 7;
17217 Value |= op;
17218 // op: imm6
17219 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17220 Value |= (op & UINT64_C(1)) << 25;
17221 Value |= (op & UINT64_C(62)) << 19;
17222 break;
17223 }
17224 case RISCV::CV_INSERT: {
17225 // op: rs1
17226 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17227 op &= UINT64_C(31);
17228 op <<= 15;
17229 Value |= op;
17230 // op: rd
17231 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17232 op &= UINT64_C(31);
17233 op <<= 7;
17234 Value |= op;
17235 // op: is3
17236 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17237 op &= UINT64_C(31);
17238 op <<= 25;
17239 Value |= op;
17240 // op: is2
17241 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
17242 op &= UINT64_C(31);
17243 op <<= 20;
17244 Value |= op;
17245 break;
17246 }
17247 case RISCV::QC_SELECTIIEQ:
17248 case RISCV::QC_SELECTIINE: {
17249 // op: rs1
17250 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17251 op &= UINT64_C(31);
17252 op <<= 15;
17253 Value |= op;
17254 // op: rd
17255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17256 op &= UINT64_C(31);
17257 op <<= 7;
17258 Value |= op;
17259 // op: simm1
17260 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17261 op &= UINT64_C(31);
17262 op <<= 20;
17263 Value |= op;
17264 // op: simm2
17265 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
17266 op &= UINT64_C(31);
17267 op <<= 27;
17268 Value |= op;
17269 break;
17270 }
17271 case RISCV::TH_SBIA:
17272 case RISCV::TH_SBIB:
17273 case RISCV::TH_SDIA:
17274 case RISCV::TH_SDIB:
17275 case RISCV::TH_SHIA:
17276 case RISCV::TH_SHIB:
17277 case RISCV::TH_SWIA:
17278 case RISCV::TH_SWIB: {
17279 // op: rs1
17280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17281 op &= UINT64_C(31);
17282 op <<= 15;
17283 Value |= op;
17284 // op: rd
17285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17286 op &= UINT64_C(31);
17287 op <<= 7;
17288 Value |= op;
17289 // op: simm5
17290 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17291 op &= UINT64_C(31);
17292 op <<= 20;
17293 Value |= op;
17294 // op: uimm2
17295 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
17296 op &= UINT64_C(3);
17297 op <<= 25;
17298 Value |= op;
17299 break;
17300 }
17301 case RISCV::VFMV_S_F:
17302 case RISCV::VMV_S_X: {
17303 // op: rs1
17304 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17305 op &= UINT64_C(31);
17306 op <<= 15;
17307 Value |= op;
17308 // op: vd
17309 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17310 op &= UINT64_C(31);
17311 op <<= 7;
17312 Value |= op;
17313 break;
17314 }
17315 case RISCV::SF_VC_I: {
17316 // op: rs2
17317 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
17318 op &= UINT64_C(31);
17319 op <<= 20;
17320 Value |= op;
17321 // op: rs1
17322 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17323 op &= UINT64_C(31);
17324 op <<= 15;
17325 Value |= op;
17326 // op: rd
17327 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17328 op &= UINT64_C(31);
17329 op <<= 7;
17330 Value |= op;
17331 // op: funct6_lo2
17332 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
17333 op &= UINT64_C(3);
17334 op <<= 26;
17335 Value |= op;
17336 break;
17337 }
17338 case RISCV::SF_VC_X: {
17339 // op: rs2
17340 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
17341 op &= UINT64_C(31);
17342 op <<= 20;
17343 Value |= op;
17344 // op: rs1
17345 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17346 op &= UINT64_C(31);
17347 op <<= 15;
17348 Value |= op;
17349 // op: rd
17350 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17351 op &= UINT64_C(31);
17352 op <<= 7;
17353 Value |= op;
17354 // op: funct6_lo2
17355 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
17356 op &= UINT64_C(3);
17357 op <<= 26;
17358 Value |= op;
17359 break;
17360 }
17361 case RISCV::SF_VC_V_I: {
17362 // op: rs2
17363 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17364 op &= UINT64_C(31);
17365 op <<= 20;
17366 Value |= op;
17367 // op: rs1
17368 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17369 op &= UINT64_C(31);
17370 op <<= 15;
17371 Value |= op;
17372 // op: rd
17373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17374 op &= UINT64_C(31);
17375 op <<= 7;
17376 Value |= op;
17377 // op: funct6_lo2
17378 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
17379 op &= UINT64_C(3);
17380 op <<= 26;
17381 Value |= op;
17382 break;
17383 }
17384 case RISCV::SF_VC_V_X: {
17385 // op: rs2
17386 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17387 op &= UINT64_C(31);
17388 op <<= 20;
17389 Value |= op;
17390 // op: rs1
17391 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17392 op &= UINT64_C(31);
17393 op <<= 15;
17394 Value |= op;
17395 // op: rd
17396 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17397 op &= UINT64_C(31);
17398 op <<= 7;
17399 Value |= op;
17400 // op: funct6_lo2
17401 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
17402 op &= UINT64_C(3);
17403 op <<= 26;
17404 Value |= op;
17405 break;
17406 }
17407 case RISCV::QC_LIEQI:
17408 case RISCV::QC_LIGEI:
17409 case RISCV::QC_LIGEUI:
17410 case RISCV::QC_LILTI:
17411 case RISCV::QC_LILTUI:
17412 case RISCV::QC_LINEI: {
17413 // op: rs2
17414 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17415 op &= UINT64_C(31);
17416 op <<= 20;
17417 Value |= op;
17418 // op: rs1
17419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17420 op &= UINT64_C(31);
17421 op <<= 15;
17422 Value |= op;
17423 // op: rd
17424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17425 op &= UINT64_C(31);
17426 op <<= 7;
17427 Value |= op;
17428 // op: simm
17429 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
17430 op &= UINT64_C(31);
17431 op <<= 27;
17432 Value |= op;
17433 break;
17434 }
17435 case RISCV::SSPUSH: {
17436 // op: rs2
17437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17438 op &= UINT64_C(31);
17439 op <<= 20;
17440 Value |= op;
17441 break;
17442 }
17443 case RISCV::HSV_B:
17444 case RISCV::HSV_D:
17445 case RISCV::HSV_H:
17446 case RISCV::HSV_W:
17447 case RISCV::SF_VLTE8:
17448 case RISCV::SF_VLTE16:
17449 case RISCV::SF_VLTE32:
17450 case RISCV::SF_VLTE64:
17451 case RISCV::SF_VSTE8:
17452 case RISCV::SF_VSTE16:
17453 case RISCV::SF_VSTE32:
17454 case RISCV::SF_VSTE64: {
17455 // op: rs2
17456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17457 op &= UINT64_C(31);
17458 op <<= 20;
17459 Value |= op;
17460 // op: rs1
17461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17462 op &= UINT64_C(31);
17463 op <<= 15;
17464 Value |= op;
17465 break;
17466 }
17467 case RISCV::QK_C_SB: {
17468 // op: rs2
17469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17470 op &= UINT64_C(7);
17471 op <<= 2;
17472 Value |= op;
17473 // op: rs1
17474 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17475 op &= UINT64_C(7);
17476 op <<= 7;
17477 Value |= op;
17478 // op: imm
17479 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17480 Value |= (op & UINT64_C(1)) << 12;
17481 Value |= (op & UINT64_C(24)) << 7;
17482 Value |= (op & UINT64_C(6)) << 4;
17483 break;
17484 }
17485 case RISCV::C_SB: {
17486 // op: rs2
17487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17488 op &= UINT64_C(7);
17489 op <<= 2;
17490 Value |= op;
17491 // op: rs1
17492 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17493 op &= UINT64_C(7);
17494 op <<= 7;
17495 Value |= op;
17496 // op: imm
17497 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17498 Value |= (op & UINT64_C(1)) << 6;
17499 Value |= (op & UINT64_C(2)) << 4;
17500 break;
17501 }
17502 case RISCV::C_FSD:
17503 case RISCV::C_SD:
17504 case RISCV::C_SD_RV32: {
17505 // op: rs2
17506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17507 op &= UINT64_C(7);
17508 op <<= 2;
17509 Value |= op;
17510 // op: rs1
17511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17512 op &= UINT64_C(7);
17513 op <<= 7;
17514 Value |= op;
17515 // op: imm
17516 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17517 Value |= (op & UINT64_C(56)) << 7;
17518 Value |= (op & UINT64_C(192)) >> 1;
17519 break;
17520 }
17521 case RISCV::C_FSW:
17522 case RISCV::C_SW:
17523 case RISCV::C_SW_INX: {
17524 // op: rs2
17525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17526 op &= UINT64_C(7);
17527 op <<= 2;
17528 Value |= op;
17529 // op: rs1
17530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17531 op &= UINT64_C(7);
17532 op <<= 7;
17533 Value |= op;
17534 // op: imm
17535 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17536 Value |= (op & UINT64_C(56)) << 7;
17537 Value |= (op & UINT64_C(4)) << 4;
17538 Value |= (op & UINT64_C(64)) >> 1;
17539 break;
17540 }
17541 case RISCV::QK_C_SH: {
17542 // op: rs2
17543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17544 op &= UINT64_C(7);
17545 op <<= 2;
17546 Value |= op;
17547 // op: rs1
17548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17549 op &= UINT64_C(7);
17550 op <<= 7;
17551 Value |= op;
17552 // op: imm
17553 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17554 Value |= (op & UINT64_C(56)) << 7;
17555 Value |= (op & UINT64_C(6)) << 4;
17556 break;
17557 }
17558 case RISCV::C_SH:
17559 case RISCV::C_SH_INX: {
17560 // op: rs2
17561 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17562 op &= UINT64_C(7);
17563 op <<= 2;
17564 Value |= op;
17565 // op: rs1
17566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17567 op &= UINT64_C(7);
17568 op <<= 7;
17569 Value |= op;
17570 // op: imm
17571 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
17572 op &= UINT64_C(2);
17573 op <<= 4;
17574 Value |= op;
17575 break;
17576 }
17577 case RISCV::HFENCE_GVMA:
17578 case RISCV::HFENCE_VVMA:
17579 case RISCV::HINVAL_GVMA:
17580 case RISCV::HINVAL_VVMA:
17581 case RISCV::SB_AQ_RL:
17582 case RISCV::SB_RL:
17583 case RISCV::SD_AQ_RL:
17584 case RISCV::SD_RL:
17585 case RISCV::SFENCE_VMA:
17586 case RISCV::SF_VTMV_T_V:
17587 case RISCV::SH_AQ_RL:
17588 case RISCV::SH_RL:
17589 case RISCV::SINVAL_VMA:
17590 case RISCV::SW_AQ_RL:
17591 case RISCV::SW_RL:
17592 case RISCV::TH_SFENCE_VMAS: {
17593 // op: rs2
17594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17595 op &= UINT64_C(31);
17596 op <<= 20;
17597 Value |= op;
17598 // op: rs1
17599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17600 op &= UINT64_C(31);
17601 op <<= 15;
17602 Value |= op;
17603 break;
17604 }
17605 case RISCV::NDS_LEA_B_ZE:
17606 case RISCV::NDS_LEA_D:
17607 case RISCV::NDS_LEA_D_ZE:
17608 case RISCV::NDS_LEA_H:
17609 case RISCV::NDS_LEA_H_ZE:
17610 case RISCV::NDS_LEA_W:
17611 case RISCV::NDS_LEA_W_ZE: {
17612 // op: rs2
17613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17614 op &= UINT64_C(31);
17615 op <<= 20;
17616 Value |= op;
17617 // op: rs1
17618 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17619 op &= UINT64_C(31);
17620 op <<= 15;
17621 Value |= op;
17622 // op: rd
17623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17624 op &= UINT64_C(31);
17625 op <<= 7;
17626 Value |= op;
17627 break;
17628 }
17629 case RISCV::TH_LDD:
17630 case RISCV::TH_LWD:
17631 case RISCV::TH_LWUD:
17632 case RISCV::TH_SDD:
17633 case RISCV::TH_SWD: {
17634 // op: rs2
17635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17636 op &= UINT64_C(31);
17637 op <<= 20;
17638 Value |= op;
17639 // op: rs1
17640 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17641 op &= UINT64_C(31);
17642 op <<= 15;
17643 Value |= op;
17644 // op: rd
17645 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17646 op &= UINT64_C(31);
17647 op <<= 7;
17648 Value |= op;
17649 // op: uimm2
17650 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17651 op &= UINT64_C(3);
17652 op <<= 25;
17653 Value |= op;
17654 break;
17655 }
17656 case RISCV::C_MV_HINT: {
17657 // op: rs2
17658 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17659 op &= UINT64_C(31);
17660 op <<= 2;
17661 Value |= op;
17662 break;
17663 }
17664 case RISCV::CM_MVA01S:
17665 case RISCV::CM_MVSA01:
17666 case RISCV::QC_CM_MVA01S:
17667 case RISCV::QC_CM_MVSA01: {
17668 // op: rs2
17669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17670 op &= UINT64_C(7);
17671 op <<= 2;
17672 Value |= op;
17673 // op: rs1
17674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17675 op &= UINT64_C(7);
17676 op <<= 7;
17677 Value |= op;
17678 break;
17679 }
17680 case RISCV::QC_CSRRWRI: {
17681 // op: rs2
17682 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17683 op &= UINT64_C(31);
17684 op <<= 20;
17685 Value |= op;
17686 // op: rs1
17687 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
17688 op &= UINT64_C(31);
17689 op <<= 15;
17690 Value |= op;
17691 // op: rd
17692 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17693 op &= UINT64_C(31);
17694 op <<= 7;
17695 Value |= op;
17696 break;
17697 }
17698 case RISCV::SF_VC_IV: {
17699 // op: rs2
17700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17701 op &= UINT64_C(31);
17702 op <<= 20;
17703 Value |= op;
17704 // op: rs1
17705 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17706 op &= UINT64_C(31);
17707 op <<= 15;
17708 Value |= op;
17709 // op: rd
17710 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
17711 op &= UINT64_C(31);
17712 op <<= 7;
17713 Value |= op;
17714 // op: funct6_lo2
17715 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
17716 op &= UINT64_C(3);
17717 op <<= 26;
17718 Value |= op;
17719 break;
17720 }
17721 case RISCV::SF_VC_V_IV: {
17722 // op: rs2
17723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17724 op &= UINT64_C(31);
17725 op <<= 20;
17726 Value |= op;
17727 // op: rs1
17728 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17729 op &= UINT64_C(31);
17730 op <<= 15;
17731 Value |= op;
17732 // op: rd
17733 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17734 op &= UINT64_C(31);
17735 op <<= 7;
17736 Value |= op;
17737 // op: funct6_lo2
17738 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
17739 op &= UINT64_C(3);
17740 op <<= 26;
17741 Value |= op;
17742 break;
17743 }
17744 case RISCV::SF_VC_IVV:
17745 case RISCV::SF_VC_IVW: {
17746 // op: rs2
17747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17748 op &= UINT64_C(31);
17749 op <<= 20;
17750 Value |= op;
17751 // op: rs1
17752 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
17753 op &= UINT64_C(31);
17754 op <<= 15;
17755 Value |= op;
17756 // op: rd
17757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17758 op &= UINT64_C(31);
17759 op <<= 7;
17760 Value |= op;
17761 // op: funct6_lo2
17762 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
17763 op &= UINT64_C(3);
17764 op <<= 26;
17765 Value |= op;
17766 break;
17767 }
17768 case RISCV::FADD_D:
17769 case RISCV::FADD_D_IN32X:
17770 case RISCV::FADD_D_INX:
17771 case RISCV::FADD_H:
17772 case RISCV::FADD_H_INX:
17773 case RISCV::FADD_Q:
17774 case RISCV::FADD_S:
17775 case RISCV::FADD_S_INX:
17776 case RISCV::FDIV_D:
17777 case RISCV::FDIV_D_IN32X:
17778 case RISCV::FDIV_D_INX:
17779 case RISCV::FDIV_H:
17780 case RISCV::FDIV_H_INX:
17781 case RISCV::FDIV_Q:
17782 case RISCV::FDIV_S:
17783 case RISCV::FDIV_S_INX:
17784 case RISCV::FMUL_D:
17785 case RISCV::FMUL_D_IN32X:
17786 case RISCV::FMUL_D_INX:
17787 case RISCV::FMUL_H:
17788 case RISCV::FMUL_H_INX:
17789 case RISCV::FMUL_Q:
17790 case RISCV::FMUL_S:
17791 case RISCV::FMUL_S_INX:
17792 case RISCV::FSUB_D:
17793 case RISCV::FSUB_D_IN32X:
17794 case RISCV::FSUB_D_INX:
17795 case RISCV::FSUB_H:
17796 case RISCV::FSUB_H_INX:
17797 case RISCV::FSUB_Q:
17798 case RISCV::FSUB_S:
17799 case RISCV::FSUB_S_INX: {
17800 // op: rs2
17801 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17802 op &= UINT64_C(31);
17803 op <<= 20;
17804 Value |= op;
17805 // op: rs1
17806 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17807 op &= UINT64_C(31);
17808 op <<= 15;
17809 Value |= op;
17810 // op: frm
17811 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17812 op &= UINT64_C(7);
17813 op <<= 12;
17814 Value |= op;
17815 // op: rd
17816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17817 op &= UINT64_C(31);
17818 op <<= 7;
17819 Value |= op;
17820 break;
17821 }
17822 case RISCV::ADD:
17823 case RISCV::ADDW:
17824 case RISCV::ADD_UW:
17825 case RISCV::AES64DS:
17826 case RISCV::AES64DSM:
17827 case RISCV::AES64ES:
17828 case RISCV::AES64ESM:
17829 case RISCV::AES64KS2:
17830 case RISCV::AMOADD_B:
17831 case RISCV::AMOADD_B_AQ:
17832 case RISCV::AMOADD_B_AQ_RL:
17833 case RISCV::AMOADD_B_RL:
17834 case RISCV::AMOADD_D:
17835 case RISCV::AMOADD_D_AQ:
17836 case RISCV::AMOADD_D_AQ_RL:
17837 case RISCV::AMOADD_D_RL:
17838 case RISCV::AMOADD_H:
17839 case RISCV::AMOADD_H_AQ:
17840 case RISCV::AMOADD_H_AQ_RL:
17841 case RISCV::AMOADD_H_RL:
17842 case RISCV::AMOADD_W:
17843 case RISCV::AMOADD_W_AQ:
17844 case RISCV::AMOADD_W_AQ_RL:
17845 case RISCV::AMOADD_W_RL:
17846 case RISCV::AMOAND_B:
17847 case RISCV::AMOAND_B_AQ:
17848 case RISCV::AMOAND_B_AQ_RL:
17849 case RISCV::AMOAND_B_RL:
17850 case RISCV::AMOAND_D:
17851 case RISCV::AMOAND_D_AQ:
17852 case RISCV::AMOAND_D_AQ_RL:
17853 case RISCV::AMOAND_D_RL:
17854 case RISCV::AMOAND_H:
17855 case RISCV::AMOAND_H_AQ:
17856 case RISCV::AMOAND_H_AQ_RL:
17857 case RISCV::AMOAND_H_RL:
17858 case RISCV::AMOAND_W:
17859 case RISCV::AMOAND_W_AQ:
17860 case RISCV::AMOAND_W_AQ_RL:
17861 case RISCV::AMOAND_W_RL:
17862 case RISCV::AMOMAXU_B:
17863 case RISCV::AMOMAXU_B_AQ:
17864 case RISCV::AMOMAXU_B_AQ_RL:
17865 case RISCV::AMOMAXU_B_RL:
17866 case RISCV::AMOMAXU_D:
17867 case RISCV::AMOMAXU_D_AQ:
17868 case RISCV::AMOMAXU_D_AQ_RL:
17869 case RISCV::AMOMAXU_D_RL:
17870 case RISCV::AMOMAXU_H:
17871 case RISCV::AMOMAXU_H_AQ:
17872 case RISCV::AMOMAXU_H_AQ_RL:
17873 case RISCV::AMOMAXU_H_RL:
17874 case RISCV::AMOMAXU_W:
17875 case RISCV::AMOMAXU_W_AQ:
17876 case RISCV::AMOMAXU_W_AQ_RL:
17877 case RISCV::AMOMAXU_W_RL:
17878 case RISCV::AMOMAX_B:
17879 case RISCV::AMOMAX_B_AQ:
17880 case RISCV::AMOMAX_B_AQ_RL:
17881 case RISCV::AMOMAX_B_RL:
17882 case RISCV::AMOMAX_D:
17883 case RISCV::AMOMAX_D_AQ:
17884 case RISCV::AMOMAX_D_AQ_RL:
17885 case RISCV::AMOMAX_D_RL:
17886 case RISCV::AMOMAX_H:
17887 case RISCV::AMOMAX_H_AQ:
17888 case RISCV::AMOMAX_H_AQ_RL:
17889 case RISCV::AMOMAX_H_RL:
17890 case RISCV::AMOMAX_W:
17891 case RISCV::AMOMAX_W_AQ:
17892 case RISCV::AMOMAX_W_AQ_RL:
17893 case RISCV::AMOMAX_W_RL:
17894 case RISCV::AMOMINU_B:
17895 case RISCV::AMOMINU_B_AQ:
17896 case RISCV::AMOMINU_B_AQ_RL:
17897 case RISCV::AMOMINU_B_RL:
17898 case RISCV::AMOMINU_D:
17899 case RISCV::AMOMINU_D_AQ:
17900 case RISCV::AMOMINU_D_AQ_RL:
17901 case RISCV::AMOMINU_D_RL:
17902 case RISCV::AMOMINU_H:
17903 case RISCV::AMOMINU_H_AQ:
17904 case RISCV::AMOMINU_H_AQ_RL:
17905 case RISCV::AMOMINU_H_RL:
17906 case RISCV::AMOMINU_W:
17907 case RISCV::AMOMINU_W_AQ:
17908 case RISCV::AMOMINU_W_AQ_RL:
17909 case RISCV::AMOMINU_W_RL:
17910 case RISCV::AMOMIN_B:
17911 case RISCV::AMOMIN_B_AQ:
17912 case RISCV::AMOMIN_B_AQ_RL:
17913 case RISCV::AMOMIN_B_RL:
17914 case RISCV::AMOMIN_D:
17915 case RISCV::AMOMIN_D_AQ:
17916 case RISCV::AMOMIN_D_AQ_RL:
17917 case RISCV::AMOMIN_D_RL:
17918 case RISCV::AMOMIN_H:
17919 case RISCV::AMOMIN_H_AQ:
17920 case RISCV::AMOMIN_H_AQ_RL:
17921 case RISCV::AMOMIN_H_RL:
17922 case RISCV::AMOMIN_W:
17923 case RISCV::AMOMIN_W_AQ:
17924 case RISCV::AMOMIN_W_AQ_RL:
17925 case RISCV::AMOMIN_W_RL:
17926 case RISCV::AMOOR_B:
17927 case RISCV::AMOOR_B_AQ:
17928 case RISCV::AMOOR_B_AQ_RL:
17929 case RISCV::AMOOR_B_RL:
17930 case RISCV::AMOOR_D:
17931 case RISCV::AMOOR_D_AQ:
17932 case RISCV::AMOOR_D_AQ_RL:
17933 case RISCV::AMOOR_D_RL:
17934 case RISCV::AMOOR_H:
17935 case RISCV::AMOOR_H_AQ:
17936 case RISCV::AMOOR_H_AQ_RL:
17937 case RISCV::AMOOR_H_RL:
17938 case RISCV::AMOOR_W:
17939 case RISCV::AMOOR_W_AQ:
17940 case RISCV::AMOOR_W_AQ_RL:
17941 case RISCV::AMOOR_W_RL:
17942 case RISCV::AMOSWAP_B:
17943 case RISCV::AMOSWAP_B_AQ:
17944 case RISCV::AMOSWAP_B_AQ_RL:
17945 case RISCV::AMOSWAP_B_RL:
17946 case RISCV::AMOSWAP_D:
17947 case RISCV::AMOSWAP_D_AQ:
17948 case RISCV::AMOSWAP_D_AQ_RL:
17949 case RISCV::AMOSWAP_D_RL:
17950 case RISCV::AMOSWAP_H:
17951 case RISCV::AMOSWAP_H_AQ:
17952 case RISCV::AMOSWAP_H_AQ_RL:
17953 case RISCV::AMOSWAP_H_RL:
17954 case RISCV::AMOSWAP_W:
17955 case RISCV::AMOSWAP_W_AQ:
17956 case RISCV::AMOSWAP_W_AQ_RL:
17957 case RISCV::AMOSWAP_W_RL:
17958 case RISCV::AMOXOR_B:
17959 case RISCV::AMOXOR_B_AQ:
17960 case RISCV::AMOXOR_B_AQ_RL:
17961 case RISCV::AMOXOR_B_RL:
17962 case RISCV::AMOXOR_D:
17963 case RISCV::AMOXOR_D_AQ:
17964 case RISCV::AMOXOR_D_AQ_RL:
17965 case RISCV::AMOXOR_D_RL:
17966 case RISCV::AMOXOR_H:
17967 case RISCV::AMOXOR_H_AQ:
17968 case RISCV::AMOXOR_H_AQ_RL:
17969 case RISCV::AMOXOR_H_RL:
17970 case RISCV::AMOXOR_W:
17971 case RISCV::AMOXOR_W_AQ:
17972 case RISCV::AMOXOR_W_AQ_RL:
17973 case RISCV::AMOXOR_W_RL:
17974 case RISCV::AND:
17975 case RISCV::ANDN:
17976 case RISCV::BCLR:
17977 case RISCV::BEXT:
17978 case RISCV::BINV:
17979 case RISCV::BSET:
17980 case RISCV::CLMUL:
17981 case RISCV::CLMULH:
17982 case RISCV::CLMULR:
17983 case RISCV::CV_ADD_B:
17984 case RISCV::CV_ADD_DIV2:
17985 case RISCV::CV_ADD_DIV4:
17986 case RISCV::CV_ADD_DIV8:
17987 case RISCV::CV_ADD_H:
17988 case RISCV::CV_ADD_SC_B:
17989 case RISCV::CV_ADD_SC_H:
17990 case RISCV::CV_AND_B:
17991 case RISCV::CV_AND_H:
17992 case RISCV::CV_AND_SC_B:
17993 case RISCV::CV_AND_SC_H:
17994 case RISCV::CV_AVGU_B:
17995 case RISCV::CV_AVGU_H:
17996 case RISCV::CV_AVGU_SC_B:
17997 case RISCV::CV_AVGU_SC_H:
17998 case RISCV::CV_AVG_B:
17999 case RISCV::CV_AVG_H:
18000 case RISCV::CV_AVG_SC_B:
18001 case RISCV::CV_AVG_SC_H:
18002 case RISCV::CV_BCLRR:
18003 case RISCV::CV_BSETR:
18004 case RISCV::CV_CLIPR:
18005 case RISCV::CV_CLIPUR:
18006 case RISCV::CV_CMPEQ_B:
18007 case RISCV::CV_CMPEQ_H:
18008 case RISCV::CV_CMPEQ_SC_B:
18009 case RISCV::CV_CMPEQ_SC_H:
18010 case RISCV::CV_CMPGEU_B:
18011 case RISCV::CV_CMPGEU_H:
18012 case RISCV::CV_CMPGEU_SC_B:
18013 case RISCV::CV_CMPGEU_SC_H:
18014 case RISCV::CV_CMPGE_B:
18015 case RISCV::CV_CMPGE_H:
18016 case RISCV::CV_CMPGE_SC_B:
18017 case RISCV::CV_CMPGE_SC_H:
18018 case RISCV::CV_CMPGTU_B:
18019 case RISCV::CV_CMPGTU_H:
18020 case RISCV::CV_CMPGTU_SC_B:
18021 case RISCV::CV_CMPGTU_SC_H:
18022 case RISCV::CV_CMPGT_B:
18023 case RISCV::CV_CMPGT_H:
18024 case RISCV::CV_CMPGT_SC_B:
18025 case RISCV::CV_CMPGT_SC_H:
18026 case RISCV::CV_CMPLEU_B:
18027 case RISCV::CV_CMPLEU_H:
18028 case RISCV::CV_CMPLEU_SC_B:
18029 case RISCV::CV_CMPLEU_SC_H:
18030 case RISCV::CV_CMPLE_B:
18031 case RISCV::CV_CMPLE_H:
18032 case RISCV::CV_CMPLE_SC_B:
18033 case RISCV::CV_CMPLE_SC_H:
18034 case RISCV::CV_CMPLTU_B:
18035 case RISCV::CV_CMPLTU_H:
18036 case RISCV::CV_CMPLTU_SC_B:
18037 case RISCV::CV_CMPLTU_SC_H:
18038 case RISCV::CV_CMPLT_B:
18039 case RISCV::CV_CMPLT_H:
18040 case RISCV::CV_CMPLT_SC_B:
18041 case RISCV::CV_CMPLT_SC_H:
18042 case RISCV::CV_CMPNE_B:
18043 case RISCV::CV_CMPNE_H:
18044 case RISCV::CV_CMPNE_SC_B:
18045 case RISCV::CV_CMPNE_SC_H:
18046 case RISCV::CV_DOTSP_B:
18047 case RISCV::CV_DOTSP_H:
18048 case RISCV::CV_DOTSP_SC_B:
18049 case RISCV::CV_DOTSP_SC_H:
18050 case RISCV::CV_DOTUP_B:
18051 case RISCV::CV_DOTUP_H:
18052 case RISCV::CV_DOTUP_SC_B:
18053 case RISCV::CV_DOTUP_SC_H:
18054 case RISCV::CV_DOTUSP_B:
18055 case RISCV::CV_DOTUSP_H:
18056 case RISCV::CV_DOTUSP_SC_B:
18057 case RISCV::CV_DOTUSP_SC_H:
18058 case RISCV::CV_EXTRACTR:
18059 case RISCV::CV_EXTRACTUR:
18060 case RISCV::CV_LBU_rr:
18061 case RISCV::CV_LB_rr:
18062 case RISCV::CV_LHU_rr:
18063 case RISCV::CV_LH_rr:
18064 case RISCV::CV_LW_rr:
18065 case RISCV::CV_MAX:
18066 case RISCV::CV_MAXU:
18067 case RISCV::CV_MAXU_B:
18068 case RISCV::CV_MAXU_H:
18069 case RISCV::CV_MAXU_SC_B:
18070 case RISCV::CV_MAXU_SC_H:
18071 case RISCV::CV_MAX_B:
18072 case RISCV::CV_MAX_H:
18073 case RISCV::CV_MAX_SC_B:
18074 case RISCV::CV_MAX_SC_H:
18075 case RISCV::CV_MIN:
18076 case RISCV::CV_MINU:
18077 case RISCV::CV_MINU_B:
18078 case RISCV::CV_MINU_H:
18079 case RISCV::CV_MINU_SC_B:
18080 case RISCV::CV_MINU_SC_H:
18081 case RISCV::CV_MIN_B:
18082 case RISCV::CV_MIN_H:
18083 case RISCV::CV_MIN_SC_B:
18084 case RISCV::CV_MIN_SC_H:
18085 case RISCV::CV_OR_B:
18086 case RISCV::CV_OR_H:
18087 case RISCV::CV_OR_SC_B:
18088 case RISCV::CV_OR_SC_H:
18089 case RISCV::CV_PACK:
18090 case RISCV::CV_PACK_H:
18091 case RISCV::CV_ROR:
18092 case RISCV::CV_SHUFFLE_B:
18093 case RISCV::CV_SHUFFLE_H:
18094 case RISCV::CV_SLE:
18095 case RISCV::CV_SLEU:
18096 case RISCV::CV_SLL_B:
18097 case RISCV::CV_SLL_H:
18098 case RISCV::CV_SLL_SC_B:
18099 case RISCV::CV_SLL_SC_H:
18100 case RISCV::CV_SRA_B:
18101 case RISCV::CV_SRA_H:
18102 case RISCV::CV_SRA_SC_B:
18103 case RISCV::CV_SRA_SC_H:
18104 case RISCV::CV_SRL_B:
18105 case RISCV::CV_SRL_H:
18106 case RISCV::CV_SRL_SC_B:
18107 case RISCV::CV_SRL_SC_H:
18108 case RISCV::CV_SUBROTMJ:
18109 case RISCV::CV_SUBROTMJ_DIV2:
18110 case RISCV::CV_SUBROTMJ_DIV4:
18111 case RISCV::CV_SUBROTMJ_DIV8:
18112 case RISCV::CV_SUB_B:
18113 case RISCV::CV_SUB_DIV2:
18114 case RISCV::CV_SUB_DIV4:
18115 case RISCV::CV_SUB_DIV8:
18116 case RISCV::CV_SUB_H:
18117 case RISCV::CV_SUB_SC_B:
18118 case RISCV::CV_SUB_SC_H:
18119 case RISCV::CV_XOR_B:
18120 case RISCV::CV_XOR_H:
18121 case RISCV::CV_XOR_SC_B:
18122 case RISCV::CV_XOR_SC_H:
18123 case RISCV::CZERO_EQZ:
18124 case RISCV::CZERO_NEZ:
18125 case RISCV::DIV:
18126 case RISCV::DIVU:
18127 case RISCV::DIVUW:
18128 case RISCV::DIVW:
18129 case RISCV::FEQ_D:
18130 case RISCV::FEQ_D_IN32X:
18131 case RISCV::FEQ_D_INX:
18132 case RISCV::FEQ_H:
18133 case RISCV::FEQ_H_INX:
18134 case RISCV::FEQ_Q:
18135 case RISCV::FEQ_S:
18136 case RISCV::FEQ_S_INX:
18137 case RISCV::FLEQ_D:
18138 case RISCV::FLEQ_H:
18139 case RISCV::FLEQ_Q:
18140 case RISCV::FLEQ_S:
18141 case RISCV::FLE_D:
18142 case RISCV::FLE_D_IN32X:
18143 case RISCV::FLE_D_INX:
18144 case RISCV::FLE_H:
18145 case RISCV::FLE_H_INX:
18146 case RISCV::FLE_Q:
18147 case RISCV::FLE_S:
18148 case RISCV::FLE_S_INX:
18149 case RISCV::FLTQ_D:
18150 case RISCV::FLTQ_H:
18151 case RISCV::FLTQ_Q:
18152 case RISCV::FLTQ_S:
18153 case RISCV::FLT_D:
18154 case RISCV::FLT_D_IN32X:
18155 case RISCV::FLT_D_INX:
18156 case RISCV::FLT_H:
18157 case RISCV::FLT_H_INX:
18158 case RISCV::FLT_Q:
18159 case RISCV::FLT_S:
18160 case RISCV::FLT_S_INX:
18161 case RISCV::FMAXM_D:
18162 case RISCV::FMAXM_H:
18163 case RISCV::FMAXM_Q:
18164 case RISCV::FMAXM_S:
18165 case RISCV::FMAX_D:
18166 case RISCV::FMAX_D_IN32X:
18167 case RISCV::FMAX_D_INX:
18168 case RISCV::FMAX_H:
18169 case RISCV::FMAX_H_INX:
18170 case RISCV::FMAX_Q:
18171 case RISCV::FMAX_S:
18172 case RISCV::FMAX_S_INX:
18173 case RISCV::FMINM_D:
18174 case RISCV::FMINM_H:
18175 case RISCV::FMINM_Q:
18176 case RISCV::FMINM_S:
18177 case RISCV::FMIN_D:
18178 case RISCV::FMIN_D_IN32X:
18179 case RISCV::FMIN_D_INX:
18180 case RISCV::FMIN_H:
18181 case RISCV::FMIN_H_INX:
18182 case RISCV::FMIN_Q:
18183 case RISCV::FMIN_S:
18184 case RISCV::FMIN_S_INX:
18185 case RISCV::FMVP_D_X:
18186 case RISCV::FMVP_Q_X:
18187 case RISCV::FSGNJN_D:
18188 case RISCV::FSGNJN_D_IN32X:
18189 case RISCV::FSGNJN_D_INX:
18190 case RISCV::FSGNJN_H:
18191 case RISCV::FSGNJN_H_INX:
18192 case RISCV::FSGNJN_Q:
18193 case RISCV::FSGNJN_S:
18194 case RISCV::FSGNJN_S_INX:
18195 case RISCV::FSGNJX_D:
18196 case RISCV::FSGNJX_D_IN32X:
18197 case RISCV::FSGNJX_D_INX:
18198 case RISCV::FSGNJX_H:
18199 case RISCV::FSGNJX_H_INX:
18200 case RISCV::FSGNJX_Q:
18201 case RISCV::FSGNJX_S:
18202 case RISCV::FSGNJX_S_INX:
18203 case RISCV::FSGNJ_D:
18204 case RISCV::FSGNJ_D_IN32X:
18205 case RISCV::FSGNJ_D_INX:
18206 case RISCV::FSGNJ_H:
18207 case RISCV::FSGNJ_H_INX:
18208 case RISCV::FSGNJ_Q:
18209 case RISCV::FSGNJ_S:
18210 case RISCV::FSGNJ_S_INX:
18211 case RISCV::MAX:
18212 case RISCV::MAXU:
18213 case RISCV::MIN:
18214 case RISCV::MINU:
18215 case RISCV::MOPRR0:
18216 case RISCV::MOPRR1:
18217 case RISCV::MOPRR2:
18218 case RISCV::MOPRR3:
18219 case RISCV::MOPRR4:
18220 case RISCV::MOPRR5:
18221 case RISCV::MOPRR6:
18222 case RISCV::MOPRR7:
18223 case RISCV::MUL:
18224 case RISCV::MULH:
18225 case RISCV::MULHSU:
18226 case RISCV::MULHU:
18227 case RISCV::MULW:
18228 case RISCV::NDS_FFB:
18229 case RISCV::NDS_FFMISM:
18230 case RISCV::NDS_FFZMISM:
18231 case RISCV::NDS_FLMISM:
18232 case RISCV::OR:
18233 case RISCV::ORN:
18234 case RISCV::PACK:
18235 case RISCV::PACKH:
18236 case RISCV::PACKW:
18237 case RISCV::QC_ADDSAT:
18238 case RISCV::QC_ADDUSAT:
18239 case RISCV::QC_CSRRWR:
18240 case RISCV::QC_EXTDPR:
18241 case RISCV::QC_EXTDPRH:
18242 case RISCV::QC_EXTDR:
18243 case RISCV::QC_EXTDUPR:
18244 case RISCV::QC_EXTDUPRH:
18245 case RISCV::QC_EXTDUR:
18246 case RISCV::QC_INSBHR:
18247 case RISCV::QC_INSBPR:
18248 case RISCV::QC_INSBPRH:
18249 case RISCV::QC_INSBR:
18250 case RISCV::QC_SHLSAT:
18251 case RISCV::QC_SHLUSAT:
18252 case RISCV::QC_SUBSAT:
18253 case RISCV::QC_SUBUSAT:
18254 case RISCV::QC_WRAP:
18255 case RISCV::REM:
18256 case RISCV::REMU:
18257 case RISCV::REMUW:
18258 case RISCV::REMW:
18259 case RISCV::ROL:
18260 case RISCV::ROLW:
18261 case RISCV::ROR:
18262 case RISCV::RORW:
18263 case RISCV::SC_D:
18264 case RISCV::SC_D_AQ:
18265 case RISCV::SC_D_AQ_RL:
18266 case RISCV::SC_D_RL:
18267 case RISCV::SC_W:
18268 case RISCV::SC_W_AQ:
18269 case RISCV::SC_W_AQ_RL:
18270 case RISCV::SC_W_RL:
18271 case RISCV::SF_VFWMACC_4x4x4:
18272 case RISCV::SF_VQMACCSU_2x8x2:
18273 case RISCV::SF_VQMACCSU_4x8x4:
18274 case RISCV::SF_VQMACCUS_2x8x2:
18275 case RISCV::SF_VQMACCUS_4x8x4:
18276 case RISCV::SF_VQMACCU_2x8x2:
18277 case RISCV::SF_VQMACCU_4x8x4:
18278 case RISCV::SF_VQMACC_2x8x2:
18279 case RISCV::SF_VQMACC_4x8x4:
18280 case RISCV::SH1ADD:
18281 case RISCV::SH1ADD_UW:
18282 case RISCV::SH2ADD:
18283 case RISCV::SH2ADD_UW:
18284 case RISCV::SH3ADD:
18285 case RISCV::SH3ADD_UW:
18286 case RISCV::SHA512SIG0H:
18287 case RISCV::SHA512SIG0L:
18288 case RISCV::SHA512SIG1H:
18289 case RISCV::SHA512SIG1L:
18290 case RISCV::SHA512SUM0R:
18291 case RISCV::SHA512SUM1R:
18292 case RISCV::SLL:
18293 case RISCV::SLLW:
18294 case RISCV::SLT:
18295 case RISCV::SLTU:
18296 case RISCV::SRA:
18297 case RISCV::SRAW:
18298 case RISCV::SRL:
18299 case RISCV::SRLW:
18300 case RISCV::SSAMOSWAP_D:
18301 case RISCV::SSAMOSWAP_D_AQ:
18302 case RISCV::SSAMOSWAP_D_AQ_RL:
18303 case RISCV::SSAMOSWAP_D_RL:
18304 case RISCV::SSAMOSWAP_W:
18305 case RISCV::SSAMOSWAP_W_AQ:
18306 case RISCV::SSAMOSWAP_W_AQ_RL:
18307 case RISCV::SSAMOSWAP_W_RL:
18308 case RISCV::SUB:
18309 case RISCV::SUBW:
18310 case RISCV::VSETVL:
18311 case RISCV::VT_MASKC:
18312 case RISCV::VT_MASKCN:
18313 case RISCV::XNOR:
18314 case RISCV::XOR:
18315 case RISCV::XPERM4:
18316 case RISCV::XPERM8: {
18317 // op: rs2
18318 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18319 op &= UINT64_C(31);
18320 op <<= 20;
18321 Value |= op;
18322 // op: rs1
18323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18324 op &= UINT64_C(31);
18325 op <<= 15;
18326 Value |= op;
18327 // op: rd
18328 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18329 op &= UINT64_C(31);
18330 op <<= 7;
18331 Value |= op;
18332 break;
18333 }
18334 case RISCV::AES32DSI:
18335 case RISCV::AES32DSMI:
18336 case RISCV::AES32ESI:
18337 case RISCV::AES32ESMI:
18338 case RISCV::SM4ED:
18339 case RISCV::SM4KS: {
18340 // op: rs2
18341 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18342 op &= UINT64_C(31);
18343 op <<= 20;
18344 Value |= op;
18345 // op: rs1
18346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18347 op &= UINT64_C(31);
18348 op <<= 15;
18349 Value |= op;
18350 // op: rd
18351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18352 op &= UINT64_C(31);
18353 op <<= 7;
18354 Value |= op;
18355 // op: bs
18356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18357 op &= UINT64_C(3);
18358 op <<= 30;
18359 Value |= op;
18360 break;
18361 }
18362 case RISCV::QC_LWM:
18363 case RISCV::QC_LWMI:
18364 case RISCV::QC_SETWM:
18365 case RISCV::QC_SETWMI:
18366 case RISCV::QC_SWM:
18367 case RISCV::QC_SWMI: {
18368 // op: rs2
18369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18370 op &= UINT64_C(31);
18371 op <<= 20;
18372 Value |= op;
18373 // op: rs1
18374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18375 op &= UINT64_C(31);
18376 op <<= 15;
18377 Value |= op;
18378 // op: rd
18379 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18380 op &= UINT64_C(31);
18381 op <<= 7;
18382 Value |= op;
18383 // op: imm
18384 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
18385 op &= UINT64_C(124);
18386 op <<= 23;
18387 Value |= op;
18388 break;
18389 }
18390 case RISCV::CV_ADDN:
18391 case RISCV::CV_ADDRN:
18392 case RISCV::CV_ADDUN:
18393 case RISCV::CV_ADDURN:
18394 case RISCV::CV_MULHHSN:
18395 case RISCV::CV_MULHHSRN:
18396 case RISCV::CV_MULHHUN:
18397 case RISCV::CV_MULHHURN:
18398 case RISCV::CV_MULSN:
18399 case RISCV::CV_MULSRN:
18400 case RISCV::CV_MULUN:
18401 case RISCV::CV_MULURN:
18402 case RISCV::CV_SUBN:
18403 case RISCV::CV_SUBRN:
18404 case RISCV::CV_SUBUN:
18405 case RISCV::CV_SUBURN: {
18406 // op: rs2
18407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18408 op &= UINT64_C(31);
18409 op <<= 20;
18410 Value |= op;
18411 // op: rs1
18412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18413 op &= UINT64_C(31);
18414 op <<= 15;
18415 Value |= op;
18416 // op: rd
18417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18418 op &= UINT64_C(31);
18419 op <<= 7;
18420 Value |= op;
18421 // op: imm5
18422 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
18423 op &= UINT64_C(31);
18424 op <<= 25;
18425 Value |= op;
18426 break;
18427 }
18428 case RISCV::QC_LRB:
18429 case RISCV::QC_LRBU:
18430 case RISCV::QC_LRH:
18431 case RISCV::QC_LRHU:
18432 case RISCV::QC_LRW:
18433 case RISCV::QC_SRB:
18434 case RISCV::QC_SRH:
18435 case RISCV::QC_SRW: {
18436 // op: rs2
18437 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18438 op &= UINT64_C(31);
18439 op <<= 20;
18440 Value |= op;
18441 // op: rs1
18442 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18443 op &= UINT64_C(31);
18444 op <<= 15;
18445 Value |= op;
18446 // op: rd
18447 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18448 op &= UINT64_C(31);
18449 op <<= 7;
18450 Value |= op;
18451 // op: shamt
18452 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
18453 op &= UINT64_C(7);
18454 op <<= 25;
18455 Value |= op;
18456 break;
18457 }
18458 case RISCV::QC_SHLADD: {
18459 // op: rs2
18460 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18461 op &= UINT64_C(31);
18462 op <<= 20;
18463 Value |= op;
18464 // op: rs1
18465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18466 op &= UINT64_C(31);
18467 op <<= 15;
18468 Value |= op;
18469 // op: rd
18470 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18471 op &= UINT64_C(31);
18472 op <<= 7;
18473 Value |= op;
18474 // op: shamt
18475 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18476 op &= UINT64_C(31);
18477 op <<= 25;
18478 Value |= op;
18479 break;
18480 }
18481 case RISCV::TH_ADDSL:
18482 case RISCV::TH_FLRD:
18483 case RISCV::TH_FLRW:
18484 case RISCV::TH_FLURD:
18485 case RISCV::TH_FLURW:
18486 case RISCV::TH_FSRD:
18487 case RISCV::TH_FSRW:
18488 case RISCV::TH_FSURD:
18489 case RISCV::TH_FSURW:
18490 case RISCV::TH_LRB:
18491 case RISCV::TH_LRBU:
18492 case RISCV::TH_LRD:
18493 case RISCV::TH_LRH:
18494 case RISCV::TH_LRHU:
18495 case RISCV::TH_LRW:
18496 case RISCV::TH_LRWU:
18497 case RISCV::TH_LURB:
18498 case RISCV::TH_LURBU:
18499 case RISCV::TH_LURD:
18500 case RISCV::TH_LURH:
18501 case RISCV::TH_LURHU:
18502 case RISCV::TH_LURW:
18503 case RISCV::TH_LURWU:
18504 case RISCV::TH_SRB:
18505 case RISCV::TH_SRD:
18506 case RISCV::TH_SRH:
18507 case RISCV::TH_SRW:
18508 case RISCV::TH_SURB:
18509 case RISCV::TH_SURD:
18510 case RISCV::TH_SURH:
18511 case RISCV::TH_SURW: {
18512 // op: rs2
18513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18514 op &= UINT64_C(31);
18515 op <<= 20;
18516 Value |= op;
18517 // op: rs1
18518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18519 op &= UINT64_C(31);
18520 op <<= 15;
18521 Value |= op;
18522 // op: rd
18523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18524 op &= UINT64_C(31);
18525 op <<= 7;
18526 Value |= op;
18527 // op: uimm2
18528 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
18529 op &= UINT64_C(3);
18530 op <<= 25;
18531 Value |= op;
18532 break;
18533 }
18534 case RISCV::VLSE8_V:
18535 case RISCV::VLSE16_V:
18536 case RISCV::VLSE32_V:
18537 case RISCV::VLSE64_V:
18538 case RISCV::VLSSEG2E8_V:
18539 case RISCV::VLSSEG2E16_V:
18540 case RISCV::VLSSEG2E32_V:
18541 case RISCV::VLSSEG2E64_V:
18542 case RISCV::VLSSEG3E8_V:
18543 case RISCV::VLSSEG3E16_V:
18544 case RISCV::VLSSEG3E32_V:
18545 case RISCV::VLSSEG3E64_V:
18546 case RISCV::VLSSEG4E8_V:
18547 case RISCV::VLSSEG4E16_V:
18548 case RISCV::VLSSEG4E32_V:
18549 case RISCV::VLSSEG4E64_V:
18550 case RISCV::VLSSEG5E8_V:
18551 case RISCV::VLSSEG5E16_V:
18552 case RISCV::VLSSEG5E32_V:
18553 case RISCV::VLSSEG5E64_V:
18554 case RISCV::VLSSEG6E8_V:
18555 case RISCV::VLSSEG6E16_V:
18556 case RISCV::VLSSEG6E32_V:
18557 case RISCV::VLSSEG6E64_V:
18558 case RISCV::VLSSEG7E8_V:
18559 case RISCV::VLSSEG7E16_V:
18560 case RISCV::VLSSEG7E32_V:
18561 case RISCV::VLSSEG7E64_V:
18562 case RISCV::VLSSEG8E8_V:
18563 case RISCV::VLSSEG8E16_V:
18564 case RISCV::VLSSEG8E32_V:
18565 case RISCV::VLSSEG8E64_V: {
18566 // op: rs2
18567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18568 op &= UINT64_C(31);
18569 op <<= 20;
18570 Value |= op;
18571 // op: rs1
18572 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18573 op &= UINT64_C(31);
18574 op <<= 15;
18575 Value |= op;
18576 // op: vd
18577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18578 op &= UINT64_C(31);
18579 op <<= 7;
18580 Value |= op;
18581 // op: vm
18582 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
18583 op &= UINT64_C(1);
18584 op <<= 25;
18585 Value |= op;
18586 break;
18587 }
18588 case RISCV::VSSE8_V:
18589 case RISCV::VSSE16_V:
18590 case RISCV::VSSE32_V:
18591 case RISCV::VSSE64_V:
18592 case RISCV::VSSSEG2E8_V:
18593 case RISCV::VSSSEG2E16_V:
18594 case RISCV::VSSSEG2E32_V:
18595 case RISCV::VSSSEG2E64_V:
18596 case RISCV::VSSSEG3E8_V:
18597 case RISCV::VSSSEG3E16_V:
18598 case RISCV::VSSSEG3E32_V:
18599 case RISCV::VSSSEG3E64_V:
18600 case RISCV::VSSSEG4E8_V:
18601 case RISCV::VSSSEG4E16_V:
18602 case RISCV::VSSSEG4E32_V:
18603 case RISCV::VSSSEG4E64_V:
18604 case RISCV::VSSSEG5E8_V:
18605 case RISCV::VSSSEG5E16_V:
18606 case RISCV::VSSSEG5E32_V:
18607 case RISCV::VSSSEG5E64_V:
18608 case RISCV::VSSSEG6E8_V:
18609 case RISCV::VSSSEG6E16_V:
18610 case RISCV::VSSSEG6E32_V:
18611 case RISCV::VSSSEG6E64_V:
18612 case RISCV::VSSSEG7E8_V:
18613 case RISCV::VSSSEG7E16_V:
18614 case RISCV::VSSSEG7E32_V:
18615 case RISCV::VSSSEG7E64_V:
18616 case RISCV::VSSSEG8E8_V:
18617 case RISCV::VSSSEG8E16_V:
18618 case RISCV::VSSSEG8E32_V:
18619 case RISCV::VSSSEG8E64_V: {
18620 // op: rs2
18621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18622 op &= UINT64_C(31);
18623 op <<= 20;
18624 Value |= op;
18625 // op: rs1
18626 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18627 op &= UINT64_C(31);
18628 op <<= 15;
18629 Value |= op;
18630 // op: vs3
18631 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18632 op &= UINT64_C(31);
18633 op <<= 7;
18634 Value |= op;
18635 // op: vm
18636 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
18637 op &= UINT64_C(1);
18638 op <<= 25;
18639 Value |= op;
18640 break;
18641 }
18642 case RISCV::SF_VC_FV: {
18643 // op: rs2
18644 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18645 op &= UINT64_C(31);
18646 op <<= 20;
18647 Value |= op;
18648 // op: rs1
18649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18650 op &= UINT64_C(31);
18651 op <<= 15;
18652 Value |= op;
18653 // op: rd
18654 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
18655 op &= UINT64_C(31);
18656 op <<= 7;
18657 Value |= op;
18658 // op: funct6_lo1
18659 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
18660 op &= UINT64_C(1);
18661 op <<= 26;
18662 Value |= op;
18663 break;
18664 }
18665 case RISCV::SF_VC_VV:
18666 case RISCV::SF_VC_XV: {
18667 // op: rs2
18668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18669 op &= UINT64_C(31);
18670 op <<= 20;
18671 Value |= op;
18672 // op: rs1
18673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18674 op &= UINT64_C(31);
18675 op <<= 15;
18676 Value |= op;
18677 // op: rd
18678 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
18679 op &= UINT64_C(31);
18680 op <<= 7;
18681 Value |= op;
18682 // op: funct6_lo2
18683 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
18684 op &= UINT64_C(3);
18685 op <<= 26;
18686 Value |= op;
18687 break;
18688 }
18689 case RISCV::SF_VC_V_FV: {
18690 // op: rs2
18691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18692 op &= UINT64_C(31);
18693 op <<= 20;
18694 Value |= op;
18695 // op: rs1
18696 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18697 op &= UINT64_C(31);
18698 op <<= 15;
18699 Value |= op;
18700 // op: rd
18701 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18702 op &= UINT64_C(31);
18703 op <<= 7;
18704 Value |= op;
18705 // op: funct6_lo1
18706 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
18707 op &= UINT64_C(1);
18708 op <<= 26;
18709 Value |= op;
18710 break;
18711 }
18712 case RISCV::SF_VC_V_VV:
18713 case RISCV::SF_VC_V_XV: {
18714 // op: rs2
18715 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18716 op &= UINT64_C(31);
18717 op <<= 20;
18718 Value |= op;
18719 // op: rs1
18720 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18721 op &= UINT64_C(31);
18722 op <<= 15;
18723 Value |= op;
18724 // op: rd
18725 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18726 op &= UINT64_C(31);
18727 op <<= 7;
18728 Value |= op;
18729 // op: funct6_lo2
18730 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
18731 op &= UINT64_C(3);
18732 op <<= 26;
18733 Value |= op;
18734 break;
18735 }
18736 case RISCV::SF_VC_FVV:
18737 case RISCV::SF_VC_FVW: {
18738 // op: rs2
18739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18740 op &= UINT64_C(31);
18741 op <<= 20;
18742 Value |= op;
18743 // op: rs1
18744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18745 op &= UINT64_C(31);
18746 op <<= 15;
18747 Value |= op;
18748 // op: rd
18749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18750 op &= UINT64_C(31);
18751 op <<= 7;
18752 Value |= op;
18753 // op: funct6_lo1
18754 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
18755 op &= UINT64_C(1);
18756 op <<= 26;
18757 Value |= op;
18758 break;
18759 }
18760 case RISCV::SF_VC_VVV:
18761 case RISCV::SF_VC_VVW:
18762 case RISCV::SF_VC_XVV:
18763 case RISCV::SF_VC_XVW: {
18764 // op: rs2
18765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18766 op &= UINT64_C(31);
18767 op <<= 20;
18768 Value |= op;
18769 // op: rs1
18770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18771 op &= UINT64_C(31);
18772 op <<= 15;
18773 Value |= op;
18774 // op: rd
18775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18776 op &= UINT64_C(31);
18777 op <<= 7;
18778 Value |= op;
18779 // op: funct6_lo2
18780 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
18781 op &= UINT64_C(3);
18782 op <<= 26;
18783 Value |= op;
18784 break;
18785 }
18786 case RISCV::C_ADD_HINT: {
18787 // op: rs2
18788 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18789 op &= UINT64_C(31);
18790 op <<= 2;
18791 Value |= op;
18792 break;
18793 }
18794 case RISCV::C_ADDW:
18795 case RISCV::C_AND:
18796 case RISCV::C_MUL:
18797 case RISCV::C_OR:
18798 case RISCV::C_SUB:
18799 case RISCV::C_SUBW:
18800 case RISCV::C_XOR: {
18801 // op: rs2
18802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18803 op &= UINT64_C(7);
18804 op <<= 2;
18805 Value |= op;
18806 // op: rd
18807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18808 op &= UINT64_C(7);
18809 op <<= 7;
18810 Value |= op;
18811 break;
18812 }
18813 case RISCV::QC_SELECTIEQI:
18814 case RISCV::QC_SELECTINEI: {
18815 // op: rs2
18816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18817 op &= UINT64_C(31);
18818 op <<= 20;
18819 Value |= op;
18820 // op: rd
18821 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18822 op &= UINT64_C(31);
18823 op <<= 7;
18824 Value |= op;
18825 // op: imm
18826 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
18827 op &= UINT64_C(31);
18828 op <<= 15;
18829 Value |= op;
18830 // op: simm2
18831 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
18832 op &= UINT64_C(31);
18833 op <<= 27;
18834 Value |= op;
18835 break;
18836 }
18837 case RISCV::SF_VC_V_IVV:
18838 case RISCV::SF_VC_V_IVW: {
18839 // op: rs2
18840 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18841 op &= UINT64_C(31);
18842 op <<= 20;
18843 Value |= op;
18844 // op: rs1
18845 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
18846 op &= UINT64_C(31);
18847 op <<= 15;
18848 Value |= op;
18849 // op: rd
18850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18851 op &= UINT64_C(31);
18852 op <<= 7;
18853 Value |= op;
18854 // op: funct6_lo2
18855 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
18856 op &= UINT64_C(3);
18857 op <<= 26;
18858 Value |= op;
18859 break;
18860 }
18861 case RISCV::CV_LBU_rr_inc:
18862 case RISCV::CV_LB_rr_inc:
18863 case RISCV::CV_LHU_rr_inc:
18864 case RISCV::CV_LH_rr_inc:
18865 case RISCV::CV_LW_rr_inc: {
18866 // op: rs2
18867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18868 op &= UINT64_C(31);
18869 op <<= 20;
18870 Value |= op;
18871 // op: rs1
18872 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18873 op &= UINT64_C(31);
18874 op <<= 15;
18875 Value |= op;
18876 // op: rd
18877 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18878 op &= UINT64_C(31);
18879 op <<= 7;
18880 Value |= op;
18881 break;
18882 }
18883 case RISCV::AMOCAS_B:
18884 case RISCV::AMOCAS_B_AQ:
18885 case RISCV::AMOCAS_B_AQ_RL:
18886 case RISCV::AMOCAS_B_RL:
18887 case RISCV::AMOCAS_D_RV32:
18888 case RISCV::AMOCAS_D_RV32_AQ:
18889 case RISCV::AMOCAS_D_RV32_AQ_RL:
18890 case RISCV::AMOCAS_D_RV32_RL:
18891 case RISCV::AMOCAS_D_RV64:
18892 case RISCV::AMOCAS_D_RV64_AQ:
18893 case RISCV::AMOCAS_D_RV64_AQ_RL:
18894 case RISCV::AMOCAS_D_RV64_RL:
18895 case RISCV::AMOCAS_H:
18896 case RISCV::AMOCAS_H_AQ:
18897 case RISCV::AMOCAS_H_AQ_RL:
18898 case RISCV::AMOCAS_H_RL:
18899 case RISCV::AMOCAS_Q:
18900 case RISCV::AMOCAS_Q_AQ:
18901 case RISCV::AMOCAS_Q_AQ_RL:
18902 case RISCV::AMOCAS_Q_RL:
18903 case RISCV::AMOCAS_W:
18904 case RISCV::AMOCAS_W_AQ:
18905 case RISCV::AMOCAS_W_AQ_RL:
18906 case RISCV::AMOCAS_W_RL:
18907 case RISCV::CV_ADDNR:
18908 case RISCV::CV_ADDRNR:
18909 case RISCV::CV_ADDUNR:
18910 case RISCV::CV_ADDURNR:
18911 case RISCV::CV_CPLXMUL_I:
18912 case RISCV::CV_CPLXMUL_I_DIV2:
18913 case RISCV::CV_CPLXMUL_I_DIV4:
18914 case RISCV::CV_CPLXMUL_I_DIV8:
18915 case RISCV::CV_CPLXMUL_R:
18916 case RISCV::CV_CPLXMUL_R_DIV2:
18917 case RISCV::CV_CPLXMUL_R_DIV4:
18918 case RISCV::CV_CPLXMUL_R_DIV8:
18919 case RISCV::CV_INSERTR:
18920 case RISCV::CV_MAC:
18921 case RISCV::CV_MSU:
18922 case RISCV::CV_PACKHI_B:
18923 case RISCV::CV_PACKLO_B:
18924 case RISCV::CV_SDOTSP_B:
18925 case RISCV::CV_SDOTSP_H:
18926 case RISCV::CV_SDOTSP_SC_B:
18927 case RISCV::CV_SDOTSP_SC_H:
18928 case RISCV::CV_SDOTUP_B:
18929 case RISCV::CV_SDOTUP_H:
18930 case RISCV::CV_SDOTUP_SC_B:
18931 case RISCV::CV_SDOTUP_SC_H:
18932 case RISCV::CV_SDOTUSP_B:
18933 case RISCV::CV_SDOTUSP_H:
18934 case RISCV::CV_SDOTUSP_SC_B:
18935 case RISCV::CV_SDOTUSP_SC_H:
18936 case RISCV::CV_SHUFFLE2_B:
18937 case RISCV::CV_SHUFFLE2_H:
18938 case RISCV::CV_SUBNR:
18939 case RISCV::CV_SUBRNR:
18940 case RISCV::CV_SUBUNR:
18941 case RISCV::CV_SUBURNR:
18942 case RISCV::TH_MULA:
18943 case RISCV::TH_MULAH:
18944 case RISCV::TH_MULAW:
18945 case RISCV::TH_MULS:
18946 case RISCV::TH_MULSH:
18947 case RISCV::TH_MULSW:
18948 case RISCV::TH_MVEQZ:
18949 case RISCV::TH_MVNEZ: {
18950 // op: rs2
18951 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18952 op &= UINT64_C(31);
18953 op <<= 20;
18954 Value |= op;
18955 // op: rs1
18956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18957 op &= UINT64_C(31);
18958 op <<= 15;
18959 Value |= op;
18960 // op: rd
18961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18962 op &= UINT64_C(31);
18963 op <<= 7;
18964 Value |= op;
18965 break;
18966 }
18967 case RISCV::CV_MACHHSN:
18968 case RISCV::CV_MACHHSRN:
18969 case RISCV::CV_MACHHUN:
18970 case RISCV::CV_MACHHURN:
18971 case RISCV::CV_MACSN:
18972 case RISCV::CV_MACSRN:
18973 case RISCV::CV_MACUN:
18974 case RISCV::CV_MACURN: {
18975 // op: rs2
18976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18977 op &= UINT64_C(31);
18978 op <<= 20;
18979 Value |= op;
18980 // op: rs1
18981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18982 op &= UINT64_C(31);
18983 op <<= 15;
18984 Value |= op;
18985 // op: rd
18986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18987 op &= UINT64_C(31);
18988 op <<= 7;
18989 Value |= op;
18990 // op: imm5
18991 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
18992 op &= UINT64_C(31);
18993 op <<= 25;
18994 Value |= op;
18995 break;
18996 }
18997 case RISCV::QC_LIEQ:
18998 case RISCV::QC_LIGE:
18999 case RISCV::QC_LIGEU:
19000 case RISCV::QC_LILT:
19001 case RISCV::QC_LILTU:
19002 case RISCV::QC_LINE: {
19003 // op: rs2
19004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19005 op &= UINT64_C(31);
19006 op <<= 20;
19007 Value |= op;
19008 // op: rs1
19009 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19010 op &= UINT64_C(31);
19011 op <<= 15;
19012 Value |= op;
19013 // op: rd
19014 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19015 op &= UINT64_C(31);
19016 op <<= 7;
19017 Value |= op;
19018 // op: simm
19019 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
19020 op &= UINT64_C(31);
19021 op <<= 27;
19022 Value |= op;
19023 break;
19024 }
19025 case RISCV::QC_SELECTIEQ:
19026 case RISCV::QC_SELECTINE: {
19027 // op: rs2
19028 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19029 op &= UINT64_C(31);
19030 op <<= 20;
19031 Value |= op;
19032 // op: rs1
19033 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19034 op &= UINT64_C(31);
19035 op <<= 15;
19036 Value |= op;
19037 // op: rd
19038 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19039 op &= UINT64_C(31);
19040 op <<= 7;
19041 Value |= op;
19042 // op: simm2
19043 op = getImmOpValue(MI, OpNo: 4, Fixups, STI);
19044 op &= UINT64_C(31);
19045 op <<= 27;
19046 Value |= op;
19047 break;
19048 }
19049 case RISCV::SF_VC_V_FVV:
19050 case RISCV::SF_VC_V_FVW: {
19051 // op: rs2
19052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19053 op &= UINT64_C(31);
19054 op <<= 20;
19055 Value |= op;
19056 // op: rs1
19057 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19058 op &= UINT64_C(31);
19059 op <<= 15;
19060 Value |= op;
19061 // op: rd
19062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19063 op &= UINT64_C(31);
19064 op <<= 7;
19065 Value |= op;
19066 // op: funct6_lo1
19067 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
19068 op &= UINT64_C(1);
19069 op <<= 26;
19070 Value |= op;
19071 break;
19072 }
19073 case RISCV::SF_VC_V_VVV:
19074 case RISCV::SF_VC_V_VVW:
19075 case RISCV::SF_VC_V_XVV:
19076 case RISCV::SF_VC_V_XVW: {
19077 // op: rs2
19078 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19079 op &= UINT64_C(31);
19080 op <<= 20;
19081 Value |= op;
19082 // op: rs1
19083 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19084 op &= UINT64_C(31);
19085 op <<= 15;
19086 Value |= op;
19087 // op: rd
19088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19089 op &= UINT64_C(31);
19090 op <<= 7;
19091 Value |= op;
19092 // op: funct6_lo2
19093 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
19094 op &= UINT64_C(3);
19095 op <<= 26;
19096 Value |= op;
19097 break;
19098 }
19099 case RISCV::FMADD_D:
19100 case RISCV::FMADD_D_IN32X:
19101 case RISCV::FMADD_D_INX:
19102 case RISCV::FMADD_H:
19103 case RISCV::FMADD_H_INX:
19104 case RISCV::FMADD_Q:
19105 case RISCV::FMADD_S:
19106 case RISCV::FMADD_S_INX:
19107 case RISCV::FMSUB_D:
19108 case RISCV::FMSUB_D_IN32X:
19109 case RISCV::FMSUB_D_INX:
19110 case RISCV::FMSUB_H:
19111 case RISCV::FMSUB_H_INX:
19112 case RISCV::FMSUB_Q:
19113 case RISCV::FMSUB_S:
19114 case RISCV::FMSUB_S_INX:
19115 case RISCV::FNMADD_D:
19116 case RISCV::FNMADD_D_IN32X:
19117 case RISCV::FNMADD_D_INX:
19118 case RISCV::FNMADD_H:
19119 case RISCV::FNMADD_H_INX:
19120 case RISCV::FNMADD_Q:
19121 case RISCV::FNMADD_S:
19122 case RISCV::FNMADD_S_INX:
19123 case RISCV::FNMSUB_D:
19124 case RISCV::FNMSUB_D_IN32X:
19125 case RISCV::FNMSUB_D_INX:
19126 case RISCV::FNMSUB_H:
19127 case RISCV::FNMSUB_H_INX:
19128 case RISCV::FNMSUB_Q:
19129 case RISCV::FNMSUB_S:
19130 case RISCV::FNMSUB_S_INX: {
19131 // op: rs3
19132 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19133 op &= UINT64_C(31);
19134 op <<= 27;
19135 Value |= op;
19136 // op: rs2
19137 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19138 op &= UINT64_C(31);
19139 op <<= 20;
19140 Value |= op;
19141 // op: rs1
19142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19143 op &= UINT64_C(31);
19144 op <<= 15;
19145 Value |= op;
19146 // op: frm
19147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19148 op &= UINT64_C(7);
19149 op <<= 12;
19150 Value |= op;
19151 // op: rd
19152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19153 op &= UINT64_C(31);
19154 op <<= 7;
19155 Value |= op;
19156 break;
19157 }
19158 case RISCV::MIPS_CCMOV: {
19159 // op: rs3
19160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19161 op &= UINT64_C(31);
19162 op <<= 27;
19163 Value |= op;
19164 // op: rs2
19165 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19166 op &= UINT64_C(31);
19167 op <<= 20;
19168 Value |= op;
19169 // op: rs1
19170 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19171 op &= UINT64_C(31);
19172 op <<= 15;
19173 Value |= op;
19174 // op: rd
19175 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19176 op &= UINT64_C(31);
19177 op <<= 7;
19178 Value |= op;
19179 break;
19180 }
19181 case RISCV::CV_SB_rr_inc:
19182 case RISCV::CV_SH_rr_inc:
19183 case RISCV::CV_SW_rr_inc: {
19184 // op: rs3
19185 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19186 op &= UINT64_C(31);
19187 op <<= 7;
19188 Value |= op;
19189 // op: rs2
19190 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19191 op &= UINT64_C(31);
19192 op <<= 20;
19193 Value |= op;
19194 // op: rs1
19195 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19196 op &= UINT64_C(31);
19197 op <<= 15;
19198 Value |= op;
19199 break;
19200 }
19201 case RISCV::QC_MVEQI:
19202 case RISCV::QC_MVGEI:
19203 case RISCV::QC_MVGEUI:
19204 case RISCV::QC_MVLTI:
19205 case RISCV::QC_MVLTUI:
19206 case RISCV::QC_MVNEI: {
19207 // op: rs3
19208 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19209 op &= UINT64_C(31);
19210 op <<= 27;
19211 Value |= op;
19212 // op: rs1
19213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19214 op &= UINT64_C(31);
19215 op <<= 15;
19216 Value |= op;
19217 // op: rd
19218 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19219 op &= UINT64_C(31);
19220 op <<= 7;
19221 Value |= op;
19222 // op: imm
19223 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
19224 op &= UINT64_C(31);
19225 op <<= 20;
19226 Value |= op;
19227 break;
19228 }
19229 case RISCV::QC_SELECTEQI:
19230 case RISCV::QC_SELECTNEI: {
19231 // op: rs3
19232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19233 op &= UINT64_C(31);
19234 op <<= 27;
19235 Value |= op;
19236 // op: rs2
19237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19238 op &= UINT64_C(31);
19239 op <<= 20;
19240 Value |= op;
19241 // op: rd
19242 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19243 op &= UINT64_C(31);
19244 op <<= 7;
19245 Value |= op;
19246 // op: imm
19247 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
19248 op &= UINT64_C(31);
19249 op <<= 15;
19250 Value |= op;
19251 break;
19252 }
19253 case RISCV::QC_MVEQ:
19254 case RISCV::QC_MVGE:
19255 case RISCV::QC_MVGEU:
19256 case RISCV::QC_MVLT:
19257 case RISCV::QC_MVLTU:
19258 case RISCV::QC_MVNE: {
19259 // op: rs3
19260 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
19261 op &= UINT64_C(31);
19262 op <<= 27;
19263 Value |= op;
19264 // op: rs2
19265 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19266 op &= UINT64_C(31);
19267 op <<= 20;
19268 Value |= op;
19269 // op: rs1
19270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19271 op &= UINT64_C(31);
19272 op <<= 15;
19273 Value |= op;
19274 // op: rd
19275 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19276 op &= UINT64_C(31);
19277 op <<= 7;
19278 Value |= op;
19279 break;
19280 }
19281 case RISCV::QC_C_SYNC:
19282 case RISCV::QC_C_SYNCR:
19283 case RISCV::QC_C_SYNCWF:
19284 case RISCV::QC_C_SYNCWL: {
19285 // op: slist
19286 op = getImmOpValueSlist(MI, OpNo: 0, Fixups, STI);
19287 op &= UINT64_C(7);
19288 op <<= 7;
19289 Value |= op;
19290 break;
19291 }
19292 case RISCV::VSETIVLI: {
19293 // op: uimm
19294 op = getImmOpValue(MI, OpNo: 1, Fixups, STI);
19295 op &= UINT64_C(31);
19296 op <<= 15;
19297 Value |= op;
19298 // op: rd
19299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19300 op &= UINT64_C(31);
19301 op <<= 7;
19302 Value |= op;
19303 // op: vtypei
19304 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19305 op &= UINT64_C(1023);
19306 op <<= 20;
19307 Value |= op;
19308 break;
19309 }
19310 case RISCV::Insn64: {
19311 // op: value
19312 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
19313 op &= UINT64_C(18446744073709551615);
19314 Value |= op;
19315 break;
19316 }
19317 case RISCV::Insn48: {
19318 // op: value
19319 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
19320 op &= UINT64_C(281474976710655);
19321 Value |= op;
19322 break;
19323 }
19324 case RISCV::Insn32: {
19325 // op: value
19326 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
19327 op &= UINT64_C(4294967295);
19328 Value |= op;
19329 break;
19330 }
19331 case RISCV::Insn16: {
19332 // op: value
19333 op = getImmOpValue(MI, OpNo: 0, Fixups, STI);
19334 op &= UINT64_C(65535);
19335 Value |= op;
19336 break;
19337 }
19338 case RISCV::RI_VZERO: {
19339 // op: vd
19340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19341 op &= UINT64_C(31);
19342 op <<= 7;
19343 Value |= op;
19344 break;
19345 }
19346 case RISCV::VID_V: {
19347 // op: vd
19348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19349 op &= UINT64_C(31);
19350 op <<= 7;
19351 Value |= op;
19352 // op: vm
19353 op = getVMaskReg(MI, OpNo: 1, Fixups, STI);
19354 op &= UINT64_C(1);
19355 op <<= 25;
19356 Value |= op;
19357 break;
19358 }
19359 case RISCV::VMV_V_V: {
19360 // op: vs1
19361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19362 op &= UINT64_C(31);
19363 op <<= 15;
19364 Value |= op;
19365 // op: vd
19366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19367 op &= UINT64_C(31);
19368 op <<= 7;
19369 Value |= op;
19370 break;
19371 }
19372 case RISCV::VROR_VI: {
19373 // op: vs2
19374 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19375 op &= UINT64_C(31);
19376 op <<= 20;
19377 Value |= op;
19378 // op: imm
19379 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
19380 Value |= (op & UINT64_C(32)) << 21;
19381 Value |= (op & UINT64_C(31)) << 15;
19382 // op: vd
19383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19384 op &= UINT64_C(31);
19385 op <<= 7;
19386 Value |= op;
19387 // op: vm
19388 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
19389 op &= UINT64_C(1);
19390 op <<= 25;
19391 Value |= op;
19392 break;
19393 }
19394 case RISCV::VAESKF1_VI:
19395 case RISCV::VMADC_VI:
19396 case RISCV::VSM4K_VI: {
19397 // op: vs2
19398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19399 op &= UINT64_C(31);
19400 op <<= 20;
19401 Value |= op;
19402 // op: imm
19403 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
19404 op &= UINT64_C(31);
19405 op <<= 15;
19406 Value |= op;
19407 // op: vd
19408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19409 op &= UINT64_C(31);
19410 op <<= 7;
19411 Value |= op;
19412 break;
19413 }
19414 case RISCV::VADC_VIM:
19415 case RISCV::VADD_VI:
19416 case RISCV::VAND_VI:
19417 case RISCV::VMADC_VIM:
19418 case RISCV::VMERGE_VIM:
19419 case RISCV::VMSEQ_VI:
19420 case RISCV::VMSGTU_VI:
19421 case RISCV::VMSGT_VI:
19422 case RISCV::VMSLEU_VI:
19423 case RISCV::VMSLE_VI:
19424 case RISCV::VMSNE_VI:
19425 case RISCV::VNCLIPU_WI:
19426 case RISCV::VNCLIP_WI:
19427 case RISCV::VNSRA_WI:
19428 case RISCV::VNSRL_WI:
19429 case RISCV::VOR_VI:
19430 case RISCV::VRGATHER_VI:
19431 case RISCV::VRSUB_VI:
19432 case RISCV::VSADDU_VI:
19433 case RISCV::VSADD_VI:
19434 case RISCV::VSLIDEDOWN_VI:
19435 case RISCV::VSLIDEUP_VI:
19436 case RISCV::VSLL_VI:
19437 case RISCV::VSRA_VI:
19438 case RISCV::VSRL_VI:
19439 case RISCV::VSSRA_VI:
19440 case RISCV::VSSRL_VI:
19441 case RISCV::VWSLL_VI:
19442 case RISCV::VXOR_VI: {
19443 // op: vs2
19444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19445 op &= UINT64_C(31);
19446 op <<= 20;
19447 Value |= op;
19448 // op: imm
19449 op = getImmOpValue(MI, OpNo: 2, Fixups, STI);
19450 op &= UINT64_C(31);
19451 op <<= 15;
19452 Value |= op;
19453 // op: vd
19454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19455 op &= UINT64_C(31);
19456 op <<= 7;
19457 Value |= op;
19458 // op: vm
19459 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
19460 op &= UINT64_C(1);
19461 op <<= 25;
19462 Value |= op;
19463 break;
19464 }
19465 case RISCV::VMADC_VX:
19466 case RISCV::VMSBC_VX: {
19467 // op: vs2
19468 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19469 op &= UINT64_C(31);
19470 op <<= 20;
19471 Value |= op;
19472 // op: rs1
19473 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19474 op &= UINT64_C(31);
19475 op <<= 15;
19476 Value |= op;
19477 // op: vd
19478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19479 op &= UINT64_C(31);
19480 op <<= 7;
19481 Value |= op;
19482 break;
19483 }
19484 case RISCV::NDS_VFPMADB_VF:
19485 case RISCV::NDS_VFPMADT_VF:
19486 case RISCV::SF_VFNRCLIP_XU_F_QF:
19487 case RISCV::SF_VFNRCLIP_X_F_QF:
19488 case RISCV::VAADDU_VX:
19489 case RISCV::VAADD_VX:
19490 case RISCV::VADC_VXM:
19491 case RISCV::VADD_VX:
19492 case RISCV::VANDN_VX:
19493 case RISCV::VAND_VX:
19494 case RISCV::VASUBU_VX:
19495 case RISCV::VASUB_VX:
19496 case RISCV::VCLMULH_VX:
19497 case RISCV::VCLMUL_VX:
19498 case RISCV::VDIVU_VX:
19499 case RISCV::VDIV_VX:
19500 case RISCV::VFADD_VF:
19501 case RISCV::VFDIV_VF:
19502 case RISCV::VFMAX_VF:
19503 case RISCV::VFMERGE_VFM:
19504 case RISCV::VFMIN_VF:
19505 case RISCV::VFMUL_VF:
19506 case RISCV::VFRDIV_VF:
19507 case RISCV::VFRSUB_VF:
19508 case RISCV::VFSGNJN_VF:
19509 case RISCV::VFSGNJX_VF:
19510 case RISCV::VFSGNJ_VF:
19511 case RISCV::VFSLIDE1DOWN_VF:
19512 case RISCV::VFSLIDE1UP_VF:
19513 case RISCV::VFSUB_VF:
19514 case RISCV::VFWADD_VF:
19515 case RISCV::VFWADD_WF:
19516 case RISCV::VFWMUL_VF:
19517 case RISCV::VFWSUB_VF:
19518 case RISCV::VFWSUB_WF:
19519 case RISCV::VMADC_VXM:
19520 case RISCV::VMAXU_VX:
19521 case RISCV::VMAX_VX:
19522 case RISCV::VMERGE_VXM:
19523 case RISCV::VMFEQ_VF:
19524 case RISCV::VMFGE_VF:
19525 case RISCV::VMFGT_VF:
19526 case RISCV::VMFLE_VF:
19527 case RISCV::VMFLT_VF:
19528 case RISCV::VMFNE_VF:
19529 case RISCV::VMINU_VX:
19530 case RISCV::VMIN_VX:
19531 case RISCV::VMSBC_VXM:
19532 case RISCV::VMSEQ_VX:
19533 case RISCV::VMSGTU_VX:
19534 case RISCV::VMSGT_VX:
19535 case RISCV::VMSLEU_VX:
19536 case RISCV::VMSLE_VX:
19537 case RISCV::VMSLTU_VX:
19538 case RISCV::VMSLT_VX:
19539 case RISCV::VMSNE_VX:
19540 case RISCV::VMULHSU_VX:
19541 case RISCV::VMULHU_VX:
19542 case RISCV::VMULH_VX:
19543 case RISCV::VMUL_VX:
19544 case RISCV::VNCLIPU_WX:
19545 case RISCV::VNCLIP_WX:
19546 case RISCV::VNSRA_WX:
19547 case RISCV::VNSRL_WX:
19548 case RISCV::VOR_VX:
19549 case RISCV::VQDOTSU_VX:
19550 case RISCV::VQDOTUS_VX:
19551 case RISCV::VQDOTU_VX:
19552 case RISCV::VQDOT_VX:
19553 case RISCV::VREMU_VX:
19554 case RISCV::VREM_VX:
19555 case RISCV::VRGATHER_VX:
19556 case RISCV::VROL_VX:
19557 case RISCV::VROR_VX:
19558 case RISCV::VRSUB_VX:
19559 case RISCV::VSADDU_VX:
19560 case RISCV::VSADD_VX:
19561 case RISCV::VSBC_VXM:
19562 case RISCV::VSLIDE1DOWN_VX:
19563 case RISCV::VSLIDE1UP_VX:
19564 case RISCV::VSLIDEDOWN_VX:
19565 case RISCV::VSLIDEUP_VX:
19566 case RISCV::VSLL_VX:
19567 case RISCV::VSMUL_VX:
19568 case RISCV::VSRA_VX:
19569 case RISCV::VSRL_VX:
19570 case RISCV::VSSRA_VX:
19571 case RISCV::VSSRL_VX:
19572 case RISCV::VSSUBU_VX:
19573 case RISCV::VSSUB_VX:
19574 case RISCV::VSUB_VX:
19575 case RISCV::VWADDU_VX:
19576 case RISCV::VWADDU_WX:
19577 case RISCV::VWADD_VX:
19578 case RISCV::VWADD_WX:
19579 case RISCV::VWMULSU_VX:
19580 case RISCV::VWMULU_VX:
19581 case RISCV::VWMUL_VX:
19582 case RISCV::VWSLL_VX:
19583 case RISCV::VWSUBU_VX:
19584 case RISCV::VWSUBU_WX:
19585 case RISCV::VWSUB_VX:
19586 case RISCV::VWSUB_WX:
19587 case RISCV::VXOR_VX: {
19588 // op: vs2
19589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19590 op &= UINT64_C(31);
19591 op <<= 20;
19592 Value |= op;
19593 // op: rs1
19594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19595 op &= UINT64_C(31);
19596 op <<= 15;
19597 Value |= op;
19598 // op: vd
19599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19600 op &= UINT64_C(31);
19601 op <<= 7;
19602 Value |= op;
19603 // op: vm
19604 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
19605 op &= UINT64_C(1);
19606 op <<= 25;
19607 Value |= op;
19608 break;
19609 }
19610 case RISCV::NDS_VFNCVT_BF16_S:
19611 case RISCV::NDS_VFWCVT_S_BF16:
19612 case RISCV::VFMV_F_S:
19613 case RISCV::VMV1R_V:
19614 case RISCV::VMV2R_V:
19615 case RISCV::VMV4R_V:
19616 case RISCV::VMV8R_V:
19617 case RISCV::VMV_X_S: {
19618 // op: vs2
19619 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19620 op &= UINT64_C(31);
19621 op <<= 20;
19622 Value |= op;
19623 // op: vd
19624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19625 op &= UINT64_C(31);
19626 op <<= 7;
19627 Value |= op;
19628 break;
19629 }
19630 case RISCV::VBREV8_V:
19631 case RISCV::VBREV_V:
19632 case RISCV::VCLZ_V:
19633 case RISCV::VCPOP_M:
19634 case RISCV::VCPOP_V:
19635 case RISCV::VCTZ_V:
19636 case RISCV::VFCLASS_V:
19637 case RISCV::VFCVT_F_XU_V:
19638 case RISCV::VFCVT_F_X_V:
19639 case RISCV::VFCVT_RTZ_XU_F_V:
19640 case RISCV::VFCVT_RTZ_X_F_V:
19641 case RISCV::VFCVT_XU_F_V:
19642 case RISCV::VFCVT_X_F_V:
19643 case RISCV::VFIRST_M:
19644 case RISCV::VFNCVTBF16_F_F_W:
19645 case RISCV::VFNCVT_F_F_W:
19646 case RISCV::VFNCVT_F_XU_W:
19647 case RISCV::VFNCVT_F_X_W:
19648 case RISCV::VFNCVT_ROD_F_F_W:
19649 case RISCV::VFNCVT_RTZ_XU_F_W:
19650 case RISCV::VFNCVT_RTZ_X_F_W:
19651 case RISCV::VFNCVT_XU_F_W:
19652 case RISCV::VFNCVT_X_F_W:
19653 case RISCV::VFREC7_V:
19654 case RISCV::VFRSQRT7_V:
19655 case RISCV::VFSQRT_V:
19656 case RISCV::VFWCVTBF16_F_F_V:
19657 case RISCV::VFWCVT_F_F_V:
19658 case RISCV::VFWCVT_F_XU_V:
19659 case RISCV::VFWCVT_F_X_V:
19660 case RISCV::VFWCVT_RTZ_XU_F_V:
19661 case RISCV::VFWCVT_RTZ_X_F_V:
19662 case RISCV::VFWCVT_XU_F_V:
19663 case RISCV::VFWCVT_X_F_V:
19664 case RISCV::VIOTA_M:
19665 case RISCV::VMSBF_M:
19666 case RISCV::VMSIF_M:
19667 case RISCV::VMSOF_M:
19668 case RISCV::VREV8_V:
19669 case RISCV::VSEXT_VF2:
19670 case RISCV::VSEXT_VF4:
19671 case RISCV::VSEXT_VF8:
19672 case RISCV::VZEXT_VF2:
19673 case RISCV::VZEXT_VF4:
19674 case RISCV::VZEXT_VF8: {
19675 // op: vs2
19676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19677 op &= UINT64_C(31);
19678 op <<= 20;
19679 Value |= op;
19680 // op: vd
19681 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19682 op &= UINT64_C(31);
19683 op <<= 7;
19684 Value |= op;
19685 // op: vm
19686 op = getVMaskReg(MI, OpNo: 2, Fixups, STI);
19687 op &= UINT64_C(1);
19688 op <<= 25;
19689 Value |= op;
19690 break;
19691 }
19692 case RISCV::SF_MM_E4M3_E4M3:
19693 case RISCV::SF_MM_E4M3_E5M2:
19694 case RISCV::SF_MM_E5M2_E4M3:
19695 case RISCV::SF_MM_E5M2_E5M2:
19696 case RISCV::SF_MM_S_S:
19697 case RISCV::SF_MM_S_U:
19698 case RISCV::SF_MM_U_S:
19699 case RISCV::SF_MM_U_U: {
19700 // op: vs2
19701 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19702 op &= UINT64_C(31);
19703 op <<= 20;
19704 Value |= op;
19705 // op: vs1
19706 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19707 op &= UINT64_C(31);
19708 op <<= 15;
19709 Value |= op;
19710 // op: rd
19711 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19712 op &= UINT64_C(12);
19713 op <<= 8;
19714 Value |= op;
19715 break;
19716 }
19717 case RISCV::SF_MM_F_F: {
19718 // op: vs2
19719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19720 op &= UINT64_C(31);
19721 op <<= 20;
19722 Value |= op;
19723 // op: vs1
19724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19725 op &= UINT64_C(31);
19726 op <<= 15;
19727 Value |= op;
19728 // op: rd
19729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19730 op &= UINT64_C(14);
19731 op <<= 8;
19732 Value |= op;
19733 break;
19734 }
19735 case RISCV::VCOMPRESS_VM:
19736 case RISCV::VMADC_VV:
19737 case RISCV::VMANDN_MM:
19738 case RISCV::VMAND_MM:
19739 case RISCV::VMNAND_MM:
19740 case RISCV::VMNOR_MM:
19741 case RISCV::VMORN_MM:
19742 case RISCV::VMOR_MM:
19743 case RISCV::VMSBC_VV:
19744 case RISCV::VMXNOR_MM:
19745 case RISCV::VMXOR_MM:
19746 case RISCV::VSM3ME_VV: {
19747 // op: vs2
19748 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19749 op &= UINT64_C(31);
19750 op <<= 20;
19751 Value |= op;
19752 // op: vs1
19753 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19754 op &= UINT64_C(31);
19755 op <<= 15;
19756 Value |= op;
19757 // op: vd
19758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19759 op &= UINT64_C(31);
19760 op <<= 7;
19761 Value |= op;
19762 break;
19763 }
19764 case RISCV::RI_VUNZIP2A_VV:
19765 case RISCV::RI_VUNZIP2B_VV:
19766 case RISCV::RI_VZIP2A_VV:
19767 case RISCV::RI_VZIP2B_VV:
19768 case RISCV::RI_VZIPEVEN_VV:
19769 case RISCV::RI_VZIPODD_VV:
19770 case RISCV::VAADDU_VV:
19771 case RISCV::VAADD_VV:
19772 case RISCV::VADC_VVM:
19773 case RISCV::VADD_VV:
19774 case RISCV::VANDN_VV:
19775 case RISCV::VAND_VV:
19776 case RISCV::VASUBU_VV:
19777 case RISCV::VASUB_VV:
19778 case RISCV::VCLMULH_VV:
19779 case RISCV::VCLMUL_VV:
19780 case RISCV::VDIVU_VV:
19781 case RISCV::VDIV_VV:
19782 case RISCV::VFADD_VV:
19783 case RISCV::VFDIV_VV:
19784 case RISCV::VFMAX_VV:
19785 case RISCV::VFMIN_VV:
19786 case RISCV::VFMUL_VV:
19787 case RISCV::VFREDMAX_VS:
19788 case RISCV::VFREDMIN_VS:
19789 case RISCV::VFREDOSUM_VS:
19790 case RISCV::VFREDUSUM_VS:
19791 case RISCV::VFSGNJN_VV:
19792 case RISCV::VFSGNJX_VV:
19793 case RISCV::VFSGNJ_VV:
19794 case RISCV::VFSUB_VV:
19795 case RISCV::VFWADD_VV:
19796 case RISCV::VFWADD_WV:
19797 case RISCV::VFWMUL_VV:
19798 case RISCV::VFWREDOSUM_VS:
19799 case RISCV::VFWREDUSUM_VS:
19800 case RISCV::VFWSUB_VV:
19801 case RISCV::VFWSUB_WV:
19802 case RISCV::VMADC_VVM:
19803 case RISCV::VMAXU_VV:
19804 case RISCV::VMAX_VV:
19805 case RISCV::VMERGE_VVM:
19806 case RISCV::VMFEQ_VV:
19807 case RISCV::VMFLE_VV:
19808 case RISCV::VMFLT_VV:
19809 case RISCV::VMFNE_VV:
19810 case RISCV::VMINU_VV:
19811 case RISCV::VMIN_VV:
19812 case RISCV::VMSBC_VVM:
19813 case RISCV::VMSEQ_VV:
19814 case RISCV::VMSLEU_VV:
19815 case RISCV::VMSLE_VV:
19816 case RISCV::VMSLTU_VV:
19817 case RISCV::VMSLT_VV:
19818 case RISCV::VMSNE_VV:
19819 case RISCV::VMULHSU_VV:
19820 case RISCV::VMULHU_VV:
19821 case RISCV::VMULH_VV:
19822 case RISCV::VMUL_VV:
19823 case RISCV::VNCLIPU_WV:
19824 case RISCV::VNCLIP_WV:
19825 case RISCV::VNSRA_WV:
19826 case RISCV::VNSRL_WV:
19827 case RISCV::VOR_VV:
19828 case RISCV::VQDOTSU_VV:
19829 case RISCV::VQDOTU_VV:
19830 case RISCV::VQDOT_VV:
19831 case RISCV::VREDAND_VS:
19832 case RISCV::VREDMAXU_VS:
19833 case RISCV::VREDMAX_VS:
19834 case RISCV::VREDMINU_VS:
19835 case RISCV::VREDMIN_VS:
19836 case RISCV::VREDOR_VS:
19837 case RISCV::VREDSUM_VS:
19838 case RISCV::VREDXOR_VS:
19839 case RISCV::VREMU_VV:
19840 case RISCV::VREM_VV:
19841 case RISCV::VRGATHEREI16_VV:
19842 case RISCV::VRGATHER_VV:
19843 case RISCV::VROL_VV:
19844 case RISCV::VROR_VV:
19845 case RISCV::VSADDU_VV:
19846 case RISCV::VSADD_VV:
19847 case RISCV::VSBC_VVM:
19848 case RISCV::VSLL_VV:
19849 case RISCV::VSMUL_VV:
19850 case RISCV::VSRA_VV:
19851 case RISCV::VSRL_VV:
19852 case RISCV::VSSRA_VV:
19853 case RISCV::VSSRL_VV:
19854 case RISCV::VSSUBU_VV:
19855 case RISCV::VSSUB_VV:
19856 case RISCV::VSUB_VV:
19857 case RISCV::VWADDU_VV:
19858 case RISCV::VWADDU_WV:
19859 case RISCV::VWADD_VV:
19860 case RISCV::VWADD_WV:
19861 case RISCV::VWMULSU_VV:
19862 case RISCV::VWMULU_VV:
19863 case RISCV::VWMUL_VV:
19864 case RISCV::VWREDSUMU_VS:
19865 case RISCV::VWREDSUM_VS:
19866 case RISCV::VWSLL_VV:
19867 case RISCV::VWSUBU_VV:
19868 case RISCV::VWSUBU_WV:
19869 case RISCV::VWSUB_VV:
19870 case RISCV::VWSUB_WV:
19871 case RISCV::VXOR_VV: {
19872 // op: vs2
19873 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19874 op &= UINT64_C(31);
19875 op <<= 20;
19876 Value |= op;
19877 // op: vs1
19878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19879 op &= UINT64_C(31);
19880 op <<= 15;
19881 Value |= op;
19882 // op: vd
19883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19884 op &= UINT64_C(31);
19885 op <<= 7;
19886 Value |= op;
19887 // op: vm
19888 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
19889 op &= UINT64_C(1);
19890 op <<= 25;
19891 Value |= op;
19892 break;
19893 }
19894 case RISCV::VAESKF2_VI:
19895 case RISCV::VSM3C_VI: {
19896 // op: vs2
19897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19898 op &= UINT64_C(31);
19899 op <<= 20;
19900 Value |= op;
19901 // op: imm
19902 op = getImmOpValue(MI, OpNo: 3, Fixups, STI);
19903 op &= UINT64_C(31);
19904 op <<= 15;
19905 Value |= op;
19906 // op: vd
19907 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19908 op &= UINT64_C(31);
19909 op <<= 7;
19910 Value |= op;
19911 break;
19912 }
19913 case RISCV::VLOXEI8_V:
19914 case RISCV::VLOXEI16_V:
19915 case RISCV::VLOXEI32_V:
19916 case RISCV::VLOXEI64_V:
19917 case RISCV::VLOXSEG2EI8_V:
19918 case RISCV::VLOXSEG2EI16_V:
19919 case RISCV::VLOXSEG2EI32_V:
19920 case RISCV::VLOXSEG2EI64_V:
19921 case RISCV::VLOXSEG3EI8_V:
19922 case RISCV::VLOXSEG3EI16_V:
19923 case RISCV::VLOXSEG3EI32_V:
19924 case RISCV::VLOXSEG3EI64_V:
19925 case RISCV::VLOXSEG4EI8_V:
19926 case RISCV::VLOXSEG4EI16_V:
19927 case RISCV::VLOXSEG4EI32_V:
19928 case RISCV::VLOXSEG4EI64_V:
19929 case RISCV::VLOXSEG5EI8_V:
19930 case RISCV::VLOXSEG5EI16_V:
19931 case RISCV::VLOXSEG5EI32_V:
19932 case RISCV::VLOXSEG5EI64_V:
19933 case RISCV::VLOXSEG6EI8_V:
19934 case RISCV::VLOXSEG6EI16_V:
19935 case RISCV::VLOXSEG6EI32_V:
19936 case RISCV::VLOXSEG6EI64_V:
19937 case RISCV::VLOXSEG7EI8_V:
19938 case RISCV::VLOXSEG7EI16_V:
19939 case RISCV::VLOXSEG7EI32_V:
19940 case RISCV::VLOXSEG7EI64_V:
19941 case RISCV::VLOXSEG8EI8_V:
19942 case RISCV::VLOXSEG8EI16_V:
19943 case RISCV::VLOXSEG8EI32_V:
19944 case RISCV::VLOXSEG8EI64_V:
19945 case RISCV::VLUXEI8_V:
19946 case RISCV::VLUXEI16_V:
19947 case RISCV::VLUXEI32_V:
19948 case RISCV::VLUXEI64_V:
19949 case RISCV::VLUXSEG2EI8_V:
19950 case RISCV::VLUXSEG2EI16_V:
19951 case RISCV::VLUXSEG2EI32_V:
19952 case RISCV::VLUXSEG2EI64_V:
19953 case RISCV::VLUXSEG3EI8_V:
19954 case RISCV::VLUXSEG3EI16_V:
19955 case RISCV::VLUXSEG3EI32_V:
19956 case RISCV::VLUXSEG3EI64_V:
19957 case RISCV::VLUXSEG4EI8_V:
19958 case RISCV::VLUXSEG4EI16_V:
19959 case RISCV::VLUXSEG4EI32_V:
19960 case RISCV::VLUXSEG4EI64_V:
19961 case RISCV::VLUXSEG5EI8_V:
19962 case RISCV::VLUXSEG5EI16_V:
19963 case RISCV::VLUXSEG5EI32_V:
19964 case RISCV::VLUXSEG5EI64_V:
19965 case RISCV::VLUXSEG6EI8_V:
19966 case RISCV::VLUXSEG6EI16_V:
19967 case RISCV::VLUXSEG6EI32_V:
19968 case RISCV::VLUXSEG6EI64_V:
19969 case RISCV::VLUXSEG7EI8_V:
19970 case RISCV::VLUXSEG7EI16_V:
19971 case RISCV::VLUXSEG7EI32_V:
19972 case RISCV::VLUXSEG7EI64_V:
19973 case RISCV::VLUXSEG8EI8_V:
19974 case RISCV::VLUXSEG8EI16_V:
19975 case RISCV::VLUXSEG8EI32_V:
19976 case RISCV::VLUXSEG8EI64_V: {
19977 // op: vs2
19978 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19979 op &= UINT64_C(31);
19980 op <<= 20;
19981 Value |= op;
19982 // op: rs1
19983 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19984 op &= UINT64_C(31);
19985 op <<= 15;
19986 Value |= op;
19987 // op: vd
19988 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19989 op &= UINT64_C(31);
19990 op <<= 7;
19991 Value |= op;
19992 // op: vm
19993 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
19994 op &= UINT64_C(1);
19995 op <<= 25;
19996 Value |= op;
19997 break;
19998 }
19999 case RISCV::VSOXEI8_V:
20000 case RISCV::VSOXEI16_V:
20001 case RISCV::VSOXEI32_V:
20002 case RISCV::VSOXEI64_V:
20003 case RISCV::VSOXSEG2EI8_V:
20004 case RISCV::VSOXSEG2EI16_V:
20005 case RISCV::VSOXSEG2EI32_V:
20006 case RISCV::VSOXSEG2EI64_V:
20007 case RISCV::VSOXSEG3EI8_V:
20008 case RISCV::VSOXSEG3EI16_V:
20009 case RISCV::VSOXSEG3EI32_V:
20010 case RISCV::VSOXSEG3EI64_V:
20011 case RISCV::VSOXSEG4EI8_V:
20012 case RISCV::VSOXSEG4EI16_V:
20013 case RISCV::VSOXSEG4EI32_V:
20014 case RISCV::VSOXSEG4EI64_V:
20015 case RISCV::VSOXSEG5EI8_V:
20016 case RISCV::VSOXSEG5EI16_V:
20017 case RISCV::VSOXSEG5EI32_V:
20018 case RISCV::VSOXSEG5EI64_V:
20019 case RISCV::VSOXSEG6EI8_V:
20020 case RISCV::VSOXSEG6EI16_V:
20021 case RISCV::VSOXSEG6EI32_V:
20022 case RISCV::VSOXSEG6EI64_V:
20023 case RISCV::VSOXSEG7EI8_V:
20024 case RISCV::VSOXSEG7EI16_V:
20025 case RISCV::VSOXSEG7EI32_V:
20026 case RISCV::VSOXSEG7EI64_V:
20027 case RISCV::VSOXSEG8EI8_V:
20028 case RISCV::VSOXSEG8EI16_V:
20029 case RISCV::VSOXSEG8EI32_V:
20030 case RISCV::VSOXSEG8EI64_V:
20031 case RISCV::VSUXEI8_V:
20032 case RISCV::VSUXEI16_V:
20033 case RISCV::VSUXEI32_V:
20034 case RISCV::VSUXEI64_V:
20035 case RISCV::VSUXSEG2EI8_V:
20036 case RISCV::VSUXSEG2EI16_V:
20037 case RISCV::VSUXSEG2EI32_V:
20038 case RISCV::VSUXSEG2EI64_V:
20039 case RISCV::VSUXSEG3EI8_V:
20040 case RISCV::VSUXSEG3EI16_V:
20041 case RISCV::VSUXSEG3EI32_V:
20042 case RISCV::VSUXSEG3EI64_V:
20043 case RISCV::VSUXSEG4EI8_V:
20044 case RISCV::VSUXSEG4EI16_V:
20045 case RISCV::VSUXSEG4EI32_V:
20046 case RISCV::VSUXSEG4EI64_V:
20047 case RISCV::VSUXSEG5EI8_V:
20048 case RISCV::VSUXSEG5EI16_V:
20049 case RISCV::VSUXSEG5EI32_V:
20050 case RISCV::VSUXSEG5EI64_V:
20051 case RISCV::VSUXSEG6EI8_V:
20052 case RISCV::VSUXSEG6EI16_V:
20053 case RISCV::VSUXSEG6EI32_V:
20054 case RISCV::VSUXSEG6EI64_V:
20055 case RISCV::VSUXSEG7EI8_V:
20056 case RISCV::VSUXSEG7EI16_V:
20057 case RISCV::VSUXSEG7EI32_V:
20058 case RISCV::VSUXSEG7EI64_V:
20059 case RISCV::VSUXSEG8EI8_V:
20060 case RISCV::VSUXSEG8EI16_V:
20061 case RISCV::VSUXSEG8EI32_V:
20062 case RISCV::VSUXSEG8EI64_V: {
20063 // op: vs2
20064 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20065 op &= UINT64_C(31);
20066 op <<= 20;
20067 Value |= op;
20068 // op: rs1
20069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20070 op &= UINT64_C(31);
20071 op <<= 15;
20072 Value |= op;
20073 // op: vs3
20074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20075 op &= UINT64_C(31);
20076 op <<= 7;
20077 Value |= op;
20078 // op: vm
20079 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
20080 op &= UINT64_C(1);
20081 op <<= 25;
20082 Value |= op;
20083 break;
20084 }
20085 case RISCV::VAESDF_VS:
20086 case RISCV::VAESDF_VV:
20087 case RISCV::VAESDM_VS:
20088 case RISCV::VAESDM_VV:
20089 case RISCV::VAESEF_VS:
20090 case RISCV::VAESEF_VV:
20091 case RISCV::VAESEM_VS:
20092 case RISCV::VAESEM_VV:
20093 case RISCV::VAESZ_VS:
20094 case RISCV::VGMUL_VS:
20095 case RISCV::VGMUL_VV:
20096 case RISCV::VSM4R_VS:
20097 case RISCV::VSM4R_VV: {
20098 // op: vs2
20099 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20100 op &= UINT64_C(31);
20101 op <<= 20;
20102 Value |= op;
20103 // op: vd
20104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20105 op &= UINT64_C(31);
20106 op <<= 7;
20107 Value |= op;
20108 break;
20109 }
20110 case RISCV::NDS_VD4DOTSU_VV:
20111 case RISCV::NDS_VD4DOTS_VV:
20112 case RISCV::NDS_VD4DOTU_VV: {
20113 // op: vs2
20114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20115 op &= UINT64_C(31);
20116 op <<= 20;
20117 Value |= op;
20118 // op: vs1
20119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20120 op &= UINT64_C(31);
20121 op <<= 15;
20122 Value |= op;
20123 // op: vd
20124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20125 op &= UINT64_C(31);
20126 op <<= 7;
20127 Value |= op;
20128 // op: vm
20129 op = getVMaskReg(MI, OpNo: 3, Fixups, STI);
20130 op &= UINT64_C(1);
20131 op <<= 25;
20132 Value |= op;
20133 break;
20134 }
20135 case RISCV::VGHSH_VS:
20136 case RISCV::VGHSH_VV:
20137 case RISCV::VSHA2CH_VV:
20138 case RISCV::VSHA2CL_VV:
20139 case RISCV::VSHA2MS_VV: {
20140 // op: vs2
20141 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20142 op &= UINT64_C(31);
20143 op <<= 20;
20144 Value |= op;
20145 // op: vs1
20146 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20147 op &= UINT64_C(31);
20148 op <<= 15;
20149 Value |= op;
20150 // op: vd
20151 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20152 op &= UINT64_C(31);
20153 op <<= 7;
20154 Value |= op;
20155 break;
20156 }
20157 case RISCV::TH_VMAQASU_VX:
20158 case RISCV::TH_VMAQAUS_VX:
20159 case RISCV::TH_VMAQAU_VX:
20160 case RISCV::TH_VMAQA_VX:
20161 case RISCV::VFMACC_VF:
20162 case RISCV::VFMADD_VF:
20163 case RISCV::VFMSAC_VF:
20164 case RISCV::VFMSUB_VF:
20165 case RISCV::VFNMACC_VF:
20166 case RISCV::VFNMADD_VF:
20167 case RISCV::VFNMSAC_VF:
20168 case RISCV::VFNMSUB_VF:
20169 case RISCV::VFWMACCBF16_VF:
20170 case RISCV::VFWMACC_VF:
20171 case RISCV::VFWMSAC_VF:
20172 case RISCV::VFWNMACC_VF:
20173 case RISCV::VFWNMSAC_VF:
20174 case RISCV::VMACC_VX:
20175 case RISCV::VMADD_VX:
20176 case RISCV::VNMSAC_VX:
20177 case RISCV::VNMSUB_VX:
20178 case RISCV::VWMACCSU_VX:
20179 case RISCV::VWMACCUS_VX:
20180 case RISCV::VWMACCU_VX:
20181 case RISCV::VWMACC_VX: {
20182 // op: vs2
20183 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20184 op &= UINT64_C(31);
20185 op <<= 20;
20186 Value |= op;
20187 // op: rs1
20188 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20189 op &= UINT64_C(31);
20190 op <<= 15;
20191 Value |= op;
20192 // op: vd
20193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20194 op &= UINT64_C(31);
20195 op <<= 7;
20196 Value |= op;
20197 // op: vm
20198 op = getVMaskReg(MI, OpNo: 4, Fixups, STI);
20199 op &= UINT64_C(1);
20200 op <<= 25;
20201 Value |= op;
20202 break;
20203 }
20204 case RISCV::TH_VMAQASU_VV:
20205 case RISCV::TH_VMAQAU_VV:
20206 case RISCV::TH_VMAQA_VV:
20207 case RISCV::VFMACC_VV:
20208 case RISCV::VFMADD_VV:
20209 case RISCV::VFMSAC_VV:
20210 case RISCV::VFMSUB_VV:
20211 case RISCV::VFNMACC_VV:
20212 case RISCV::VFNMADD_VV:
20213 case RISCV::VFNMSAC_VV:
20214 case RISCV::VFNMSUB_VV:
20215 case RISCV::VFWMACCBF16_VV:
20216 case RISCV::VFWMACC_VV:
20217 case RISCV::VFWMSAC_VV:
20218 case RISCV::VFWNMACC_VV:
20219 case RISCV::VFWNMSAC_VV:
20220 case RISCV::VMACC_VV:
20221 case RISCV::VMADD_VV:
20222 case RISCV::VNMSAC_VV:
20223 case RISCV::VNMSUB_VV:
20224 case RISCV::VWMACCSU_VV:
20225 case RISCV::VWMACCU_VV:
20226 case RISCV::VWMACC_VV: {
20227 // op: vs2
20228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20229 op &= UINT64_C(31);
20230 op <<= 20;
20231 Value |= op;
20232 // op: vs1
20233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20234 op &= UINT64_C(31);
20235 op <<= 15;
20236 Value |= op;
20237 // op: vd
20238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20239 op &= UINT64_C(31);
20240 op <<= 7;
20241 Value |= op;
20242 // op: vm
20243 op = getVMaskReg(MI, OpNo: 4, Fixups, STI);
20244 op &= UINT64_C(1);
20245 op <<= 25;
20246 Value |= op;
20247 break;
20248 }
20249 default:
20250 std::string msg;
20251 raw_string_ostream Msg(msg);
20252 Msg << "Not supported instr: " << MI;
20253 report_fatal_error(reason: Msg.str().c_str());
20254 }
20255 return Value;
20256}
20257
20258#ifdef GET_OPERAND_BIT_OFFSET
20259#undef GET_OPERAND_BIT_OFFSET
20260
20261uint32_t RISCVMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
20262 unsigned OpNum,
20263 const MCSubtargetInfo &STI) const {
20264 switch (MI.getOpcode()) {
20265 case RISCV::C_EBREAK:
20266 case RISCV::C_MOP1:
20267 case RISCV::C_MOP3:
20268 case RISCV::C_MOP5:
20269 case RISCV::C_MOP7:
20270 case RISCV::C_MOP9:
20271 case RISCV::C_MOP11:
20272 case RISCV::C_MOP13:
20273 case RISCV::C_MOP15:
20274 case RISCV::C_NOP:
20275 case RISCV::C_SSPOPCHK:
20276 case RISCV::C_SSPUSH:
20277 case RISCV::C_UNIMP:
20278 case RISCV::DRET:
20279 case RISCV::EBREAK:
20280 case RISCV::ECALL:
20281 case RISCV::FENCE_I:
20282 case RISCV::FENCE_TSO:
20283 case RISCV::MNRET:
20284 case RISCV::MRET:
20285 case RISCV::QC_C_DI:
20286 case RISCV::QC_C_EI:
20287 case RISCV::QC_C_MIENTER:
20288 case RISCV::QC_C_MIENTER_NEST:
20289 case RISCV::QC_C_MILEAVERET:
20290 case RISCV::QC_C_MNRET:
20291 case RISCV::QC_C_MRET:
20292 case RISCV::QC_C_PTRACE:
20293 case RISCV::QC_PCOREDUMP:
20294 case RISCV::QC_PPREGS:
20295 case RISCV::SCTRCLR:
20296 case RISCV::SFENCE_INVAL_IR:
20297 case RISCV::SFENCE_W_INVAL:
20298 case RISCV::SF_CEASE:
20299 case RISCV::SF_VTDISCARD:
20300 case RISCV::SRET:
20301 case RISCV::TH_DCACHE_CALL:
20302 case RISCV::TH_DCACHE_CIALL:
20303 case RISCV::TH_DCACHE_IALL:
20304 case RISCV::TH_ICACHE_IALL:
20305 case RISCV::TH_ICACHE_IALLS:
20306 case RISCV::TH_L2CACHE_CALL:
20307 case RISCV::TH_L2CACHE_CIALL:
20308 case RISCV::TH_L2CACHE_IALL:
20309 case RISCV::TH_SYNC:
20310 case RISCV::TH_SYNC_I:
20311 case RISCV::TH_SYNC_IS:
20312 case RISCV::TH_SYNC_S:
20313 case RISCV::UNIMP:
20314 case RISCV::WFI:
20315 case RISCV::WRS_NTO:
20316 case RISCV::WRS_STO: {
20317 break;
20318 }
20319 case RISCV::C_NOP_HINT:
20320 case RISCV::QC_C_DELAY: {
20321 switch (OpNum) {
20322 case 0:
20323 // op: imm
20324 return 2;
20325 }
20326 break;
20327 }
20328 case RISCV::QC_CLRINTI:
20329 case RISCV::QC_SETINTI: {
20330 switch (OpNum) {
20331 case 0:
20332 // op: imm10
20333 return 15;
20334 }
20335 break;
20336 }
20337 case RISCV::QC_PSYSCALLI: {
20338 switch (OpNum) {
20339 case 0:
20340 // op: imm10
20341 return 20;
20342 }
20343 break;
20344 }
20345 case RISCV::QC_E_J:
20346 case RISCV::QC_E_JAL: {
20347 switch (OpNum) {
20348 case 0:
20349 // op: imm31
20350 return 7;
20351 }
20352 break;
20353 }
20354 case RISCV::QC_SYNC:
20355 case RISCV::QC_SYNCR:
20356 case RISCV::QC_SYNCWF:
20357 case RISCV::QC_SYNCWL: {
20358 switch (OpNum) {
20359 case 0:
20360 // op: imm5
20361 return 20;
20362 }
20363 break;
20364 }
20365 case RISCV::QC_PPUTCI: {
20366 switch (OpNum) {
20367 case 0:
20368 // op: imm8
20369 return 20;
20370 }
20371 break;
20372 }
20373 case RISCV::CM_JALT:
20374 case RISCV::CM_JT: {
20375 switch (OpNum) {
20376 case 0:
20377 // op: index
20378 return 2;
20379 }
20380 break;
20381 }
20382 case RISCV::C_J:
20383 case RISCV::C_JAL: {
20384 switch (OpNum) {
20385 case 0:
20386 // op: offset
20387 return 2;
20388 }
20389 break;
20390 }
20391 case RISCV::InsnQC_EJ: {
20392 switch (OpNum) {
20393 case 0:
20394 // op: opcode
20395 return 0;
20396 case 1:
20397 // op: func3
20398 return 12;
20399 case 2:
20400 // op: func2
20401 return 15;
20402 case 3:
20403 // op: func5
20404 return 20;
20405 case 4:
20406 // op: imm31
20407 return 7;
20408 }
20409 break;
20410 }
20411 case RISCV::InsnQC_ES: {
20412 switch (OpNum) {
20413 case 0:
20414 // op: opcode
20415 return 0;
20416 case 1:
20417 // op: func3
20418 return 12;
20419 case 2:
20420 // op: func2
20421 return 30;
20422 case 4:
20423 // op: rs1
20424 return 15;
20425 case 3:
20426 // op: rs2
20427 return 20;
20428 case 5:
20429 // op: imm26
20430 return 7;
20431 }
20432 break;
20433 }
20434 case RISCV::InsnQC_EB: {
20435 switch (OpNum) {
20436 case 0:
20437 // op: opcode
20438 return 0;
20439 case 1:
20440 // op: func3
20441 return 12;
20442 case 2:
20443 // op: func5
20444 return 20;
20445 case 3:
20446 // op: rs1
20447 return 15;
20448 case 5:
20449 // op: imm12
20450 return 7;
20451 case 4:
20452 // op: imm16
20453 return 32;
20454 }
20455 break;
20456 }
20457 case RISCV::InsnS: {
20458 switch (OpNum) {
20459 case 0:
20460 // op: opcode
20461 return 0;
20462 case 1:
20463 // op: funct3
20464 return 12;
20465 case 4:
20466 // op: imm12
20467 return 7;
20468 case 2:
20469 // op: rs2
20470 return 20;
20471 case 3:
20472 // op: rs1
20473 return 15;
20474 }
20475 break;
20476 }
20477 case RISCV::InsnB: {
20478 switch (OpNum) {
20479 case 0:
20480 // op: opcode
20481 return 0;
20482 case 1:
20483 // op: funct3
20484 return 12;
20485 case 4:
20486 // op: imm12
20487 return 7;
20488 case 3:
20489 // op: rs2
20490 return 20;
20491 case 2:
20492 // op: rs1
20493 return 15;
20494 }
20495 break;
20496 }
20497 case RISCV::InsnCJ: {
20498 switch (OpNum) {
20499 case 0:
20500 // op: opcode
20501 return 0;
20502 case 1:
20503 // op: funct3
20504 return 13;
20505 case 2:
20506 // op: imm11
20507 return 2;
20508 }
20509 break;
20510 }
20511 case RISCV::InsnCSS: {
20512 switch (OpNum) {
20513 case 0:
20514 // op: opcode
20515 return 0;
20516 case 1:
20517 // op: funct3
20518 return 13;
20519 case 3:
20520 // op: imm6
20521 return 7;
20522 case 2:
20523 // op: rs2
20524 return 2;
20525 }
20526 break;
20527 }
20528 case RISCV::InsnCB: {
20529 switch (OpNum) {
20530 case 0:
20531 // op: opcode
20532 return 0;
20533 case 1:
20534 // op: funct3
20535 return 13;
20536 case 3:
20537 // op: imm8
20538 return 2;
20539 case 2:
20540 // op: rs1
20541 return 7;
20542 }
20543 break;
20544 }
20545 case RISCV::InsnCS: {
20546 switch (OpNum) {
20547 case 0:
20548 // op: opcode
20549 return 0;
20550 case 1:
20551 // op: funct3
20552 return 13;
20553 case 4:
20554 // op: imm5
20555 return 5;
20556 case 2:
20557 // op: rs2
20558 return 2;
20559 case 3:
20560 // op: rs1
20561 return 7;
20562 }
20563 break;
20564 }
20565 case RISCV::FENCE: {
20566 switch (OpNum) {
20567 case 0:
20568 // op: pred
20569 return 24;
20570 case 1:
20571 // op: succ
20572 return 20;
20573 }
20574 break;
20575 }
20576 case RISCV::C_FLD:
20577 case RISCV::C_FLW:
20578 case RISCV::C_LBU:
20579 case RISCV::C_LD:
20580 case RISCV::C_LD_RV32:
20581 case RISCV::C_LH:
20582 case RISCV::C_LHU:
20583 case RISCV::C_LH_INX:
20584 case RISCV::C_LW:
20585 case RISCV::C_LW_INX:
20586 case RISCV::QK_C_LBU:
20587 case RISCV::QK_C_LHU: {
20588 switch (OpNum) {
20589 case 0:
20590 // op: rd
20591 return 2;
20592 case 1:
20593 // op: rs1
20594 return 7;
20595 case 2:
20596 // op: imm
20597 return 5;
20598 }
20599 break;
20600 }
20601 case RISCV::FLI_D:
20602 case RISCV::FLI_H:
20603 case RISCV::FLI_Q:
20604 case RISCV::FLI_S: {
20605 switch (OpNum) {
20606 case 0:
20607 // op: rd
20608 return 7;
20609 case 1:
20610 // op: imm
20611 return 15;
20612 }
20613 break;
20614 }
20615 case RISCV::QC_E_LI: {
20616 switch (OpNum) {
20617 case 0:
20618 // op: rd
20619 return 7;
20620 case 1:
20621 // op: imm
20622 return 16;
20623 }
20624 break;
20625 }
20626 case RISCV::PLI_H:
20627 case RISCV::PLI_W:
20628 case RISCV::PLUI_H:
20629 case RISCV::PLUI_W: {
20630 switch (OpNum) {
20631 case 0:
20632 // op: rd
20633 return 7;
20634 case 1:
20635 // op: imm10
20636 return 15;
20637 }
20638 break;
20639 }
20640 case RISCV::QC_INSBI: {
20641 switch (OpNum) {
20642 case 0:
20643 // op: rd
20644 return 7;
20645 case 1:
20646 // op: imm5
20647 return 15;
20648 case 3:
20649 // op: shamt
20650 return 20;
20651 case 2:
20652 // op: width
20653 return 25;
20654 }
20655 break;
20656 }
20657 case RISCV::QC_E_ADDI:
20658 case RISCV::QC_E_ANDI:
20659 case RISCV::QC_E_LB:
20660 case RISCV::QC_E_LBU:
20661 case RISCV::QC_E_LH:
20662 case RISCV::QC_E_LHU:
20663 case RISCV::QC_E_LW:
20664 case RISCV::QC_E_ORI:
20665 case RISCV::QC_E_XORI: {
20666 switch (OpNum) {
20667 case 0:
20668 // op: rd
20669 return 7;
20670 case 1:
20671 // op: rs1
20672 return 15;
20673 case 2:
20674 // op: imm
20675 return 20;
20676 }
20677 break;
20678 }
20679 case RISCV::NDS_BFOS:
20680 case RISCV::NDS_BFOZ: {
20681 switch (OpNum) {
20682 case 0:
20683 // op: rd
20684 return 7;
20685 case 1:
20686 // op: rs1
20687 return 15;
20688 case 2:
20689 // op: msb
20690 return 26;
20691 case 3:
20692 // op: lsb
20693 return 20;
20694 }
20695 break;
20696 }
20697 case RISCV::PLI_B: {
20698 switch (OpNum) {
20699 case 0:
20700 // op: rd
20701 return 7;
20702 case 1:
20703 // op: uimm8
20704 return 16;
20705 }
20706 break;
20707 }
20708 case RISCV::QC_C_DIR:
20709 case RISCV::SSRDP: {
20710 switch (OpNum) {
20711 case 0:
20712 // op: rd
20713 return 7;
20714 }
20715 break;
20716 }
20717 case RISCV::SF_VTZERO_T: {
20718 switch (OpNum) {
20719 case 0:
20720 // op: rd
20721 return 8;
20722 }
20723 break;
20724 }
20725 case RISCV::QK_C_LBUSP:
20726 case RISCV::QK_C_LHUSP:
20727 case RISCV::QK_C_SBSP:
20728 case RISCV::QK_C_SHSP: {
20729 switch (OpNum) {
20730 case 0:
20731 // op: rd_rs2
20732 return 2;
20733 case 2:
20734 // op: imm
20735 return 7;
20736 }
20737 break;
20738 }
20739 case RISCV::CM_POP:
20740 case RISCV::CM_POPRET:
20741 case RISCV::CM_POPRETZ:
20742 case RISCV::CM_PUSH:
20743 case RISCV::QC_CM_POP:
20744 case RISCV::QC_CM_POPRET:
20745 case RISCV::QC_CM_POPRETZ:
20746 case RISCV::QC_CM_PUSH:
20747 case RISCV::QC_CM_PUSHFP: {
20748 switch (OpNum) {
20749 case 0:
20750 // op: rlist
20751 return 4;
20752 case 1:
20753 // op: stackadj
20754 return 2;
20755 }
20756 break;
20757 }
20758 case RISCV::QC_E_BEQI:
20759 case RISCV::QC_E_BGEI:
20760 case RISCV::QC_E_BGEUI:
20761 case RISCV::QC_E_BLTI:
20762 case RISCV::QC_E_BLTUI:
20763 case RISCV::QC_E_BNEI: {
20764 switch (OpNum) {
20765 case 0:
20766 // op: rs1
20767 return 15;
20768 case 1:
20769 // op: imm16
20770 return 32;
20771 case 2:
20772 // op: imm12
20773 return 7;
20774 }
20775 break;
20776 }
20777 case RISCV::CBO_CLEAN:
20778 case RISCV::CBO_FLUSH:
20779 case RISCV::CBO_INVAL:
20780 case RISCV::CBO_ZERO:
20781 case RISCV::QC_PEXIT:
20782 case RISCV::QC_PPREG:
20783 case RISCV::QC_PPUTC:
20784 case RISCV::QC_PPUTS:
20785 case RISCV::QC_PSYSCALL:
20786 case RISCV::SF_CDISCARD_D_L1:
20787 case RISCV::SF_CFLUSH_D_L1:
20788 case RISCV::SSPOPCHK:
20789 case RISCV::TH_DCACHE_CIPA:
20790 case RISCV::TH_DCACHE_CISW:
20791 case RISCV::TH_DCACHE_CIVA:
20792 case RISCV::TH_DCACHE_CPA:
20793 case RISCV::TH_DCACHE_CPAL1:
20794 case RISCV::TH_DCACHE_CSW:
20795 case RISCV::TH_DCACHE_CVA:
20796 case RISCV::TH_DCACHE_CVAL1:
20797 case RISCV::TH_DCACHE_IPA:
20798 case RISCV::TH_DCACHE_ISW:
20799 case RISCV::TH_DCACHE_IVA:
20800 case RISCV::TH_ICACHE_IPA:
20801 case RISCV::TH_ICACHE_IVA: {
20802 switch (OpNum) {
20803 case 0:
20804 // op: rs1
20805 return 15;
20806 }
20807 break;
20808 }
20809 case RISCV::C_MV: {
20810 switch (OpNum) {
20811 case 0:
20812 // op: rs1
20813 return 7;
20814 case 1:
20815 // op: rs2
20816 return 2;
20817 }
20818 break;
20819 }
20820 case RISCV::C_JALR:
20821 case RISCV::C_JR:
20822 case RISCV::QC_C_CLRINT:
20823 case RISCV::QC_C_EIR:
20824 case RISCV::QC_C_SETINT: {
20825 switch (OpNum) {
20826 case 0:
20827 // op: rs1
20828 return 7;
20829 }
20830 break;
20831 }
20832 case RISCV::HSV_B:
20833 case RISCV::HSV_D:
20834 case RISCV::HSV_H:
20835 case RISCV::HSV_W:
20836 case RISCV::SF_VLTE8:
20837 case RISCV::SF_VLTE16:
20838 case RISCV::SF_VLTE32:
20839 case RISCV::SF_VLTE64:
20840 case RISCV::SF_VSTE8:
20841 case RISCV::SF_VSTE16:
20842 case RISCV::SF_VSTE32:
20843 case RISCV::SF_VSTE64: {
20844 switch (OpNum) {
20845 case 0:
20846 // op: rs2
20847 return 20;
20848 case 1:
20849 // op: rs1
20850 return 15;
20851 }
20852 break;
20853 }
20854 case RISCV::SSPUSH: {
20855 switch (OpNum) {
20856 case 0:
20857 // op: rs2
20858 return 20;
20859 }
20860 break;
20861 }
20862 case RISCV::C_FSD:
20863 case RISCV::C_FSW:
20864 case RISCV::C_SB:
20865 case RISCV::C_SD:
20866 case RISCV::C_SD_RV32:
20867 case RISCV::C_SH:
20868 case RISCV::C_SH_INX:
20869 case RISCV::C_SW:
20870 case RISCV::C_SW_INX:
20871 case RISCV::QK_C_SB:
20872 case RISCV::QK_C_SH: {
20873 switch (OpNum) {
20874 case 0:
20875 // op: rs2
20876 return 2;
20877 case 1:
20878 // op: rs1
20879 return 7;
20880 case 2:
20881 // op: imm
20882 return 5;
20883 }
20884 break;
20885 }
20886 case RISCV::QC_C_SYNC:
20887 case RISCV::QC_C_SYNCR:
20888 case RISCV::QC_C_SYNCWF:
20889 case RISCV::QC_C_SYNCWL: {
20890 switch (OpNum) {
20891 case 0:
20892 // op: slist
20893 return 7;
20894 }
20895 break;
20896 }
20897 case RISCV::Insn16:
20898 case RISCV::Insn32:
20899 case RISCV::Insn48:
20900 case RISCV::Insn64: {
20901 switch (OpNum) {
20902 case 0:
20903 // op: value
20904 return 0;
20905 }
20906 break;
20907 }
20908 case RISCV::VID_V: {
20909 switch (OpNum) {
20910 case 0:
20911 // op: vd
20912 return 7;
20913 case 1:
20914 // op: vm
20915 return 25;
20916 }
20917 break;
20918 }
20919 case RISCV::RI_VZERO: {
20920 switch (OpNum) {
20921 case 0:
20922 // op: vd
20923 return 7;
20924 }
20925 break;
20926 }
20927 case RISCV::VMV_V_I: {
20928 switch (OpNum) {
20929 case 1:
20930 // op: imm
20931 return 15;
20932 case 0:
20933 // op: vd
20934 return 7;
20935 }
20936 break;
20937 }
20938 case RISCV::C_LI:
20939 case RISCV::C_LUI: {
20940 switch (OpNum) {
20941 case 1:
20942 // op: imm
20943 return 2;
20944 case 0:
20945 // op: rd
20946 return 7;
20947 }
20948 break;
20949 }
20950 case RISCV::C_BEQZ:
20951 case RISCV::C_BNEZ: {
20952 switch (OpNum) {
20953 case 1:
20954 // op: imm
20955 return 2;
20956 case 0:
20957 // op: rs1
20958 return 7;
20959 }
20960 break;
20961 }
20962 case RISCV::C_LI_HINT:
20963 case RISCV::C_LUI_HINT: {
20964 switch (OpNum) {
20965 case 1:
20966 // op: imm
20967 return 2;
20968 }
20969 break;
20970 }
20971 case RISCV::PREFETCH_I:
20972 case RISCV::PREFETCH_R:
20973 case RISCV::PREFETCH_W: {
20974 switch (OpNum) {
20975 case 1:
20976 // op: imm12
20977 return 25;
20978 case 0:
20979 // op: rs1
20980 return 15;
20981 }
20982 break;
20983 }
20984 case RISCV::NDS_LDGP:
20985 case RISCV::NDS_LHGP:
20986 case RISCV::NDS_LHUGP:
20987 case RISCV::NDS_LWGP:
20988 case RISCV::NDS_LWUGP: {
20989 switch (OpNum) {
20990 case 1:
20991 // op: imm17
20992 return 15;
20993 case 0:
20994 // op: rd
20995 return 7;
20996 }
20997 break;
20998 }
20999 case RISCV::NDS_SDGP:
21000 case RISCV::NDS_SHGP:
21001 case RISCV::NDS_SWGP: {
21002 switch (OpNum) {
21003 case 1:
21004 // op: imm17
21005 return 7;
21006 case 0:
21007 // op: rs2
21008 return 20;
21009 }
21010 break;
21011 }
21012 case RISCV::NDS_ADDIGP:
21013 case RISCV::NDS_LBGP:
21014 case RISCV::NDS_LBUGP: {
21015 switch (OpNum) {
21016 case 1:
21017 // op: imm18
21018 return 14;
21019 case 0:
21020 // op: rd
21021 return 7;
21022 }
21023 break;
21024 }
21025 case RISCV::NDS_SBGP: {
21026 switch (OpNum) {
21027 case 1:
21028 // op: imm18
21029 return 7;
21030 case 0:
21031 // op: rs2
21032 return 20;
21033 }
21034 break;
21035 }
21036 case RISCV::AUIPC:
21037 case RISCV::JAL:
21038 case RISCV::LUI:
21039 case RISCV::QC_LI: {
21040 switch (OpNum) {
21041 case 1:
21042 // op: imm20
21043 return 12;
21044 case 0:
21045 // op: rd
21046 return 7;
21047 }
21048 break;
21049 }
21050 case RISCV::MIPS_PREFETCH: {
21051 switch (OpNum) {
21052 case 1:
21053 // op: imm9
21054 return 20;
21055 case 0:
21056 // op: rs1
21057 return 15;
21058 case 2:
21059 // op: hint
21060 return 7;
21061 }
21062 break;
21063 }
21064 case RISCV::InsnQC_EAI: {
21065 switch (OpNum) {
21066 case 1:
21067 // op: opcode
21068 return 0;
21069 case 2:
21070 // op: func3
21071 return 12;
21072 case 3:
21073 // op: func1
21074 return 15;
21075 case 0:
21076 // op: rd
21077 return 7;
21078 case 4:
21079 // op: imm32
21080 return 16;
21081 }
21082 break;
21083 }
21084 case RISCV::InsnQC_EI:
21085 case RISCV::InsnQC_EI_Mem: {
21086 switch (OpNum) {
21087 case 1:
21088 // op: opcode
21089 return 0;
21090 case 2:
21091 // op: func3
21092 return 12;
21093 case 3:
21094 // op: func2
21095 return 30;
21096 case 0:
21097 // op: rd
21098 return 7;
21099 case 4:
21100 // op: rs1
21101 return 15;
21102 case 5:
21103 // op: imm26
21104 return 20;
21105 }
21106 break;
21107 }
21108 case RISCV::InsnI:
21109 case RISCV::InsnI_Mem: {
21110 switch (OpNum) {
21111 case 1:
21112 // op: opcode
21113 return 0;
21114 case 2:
21115 // op: funct3
21116 return 12;
21117 case 4:
21118 // op: imm12
21119 return 20;
21120 case 3:
21121 // op: rs1
21122 return 15;
21123 case 0:
21124 // op: rd
21125 return 7;
21126 }
21127 break;
21128 }
21129 case RISCV::InsnCI: {
21130 switch (OpNum) {
21131 case 1:
21132 // op: opcode
21133 return 0;
21134 case 2:
21135 // op: funct3
21136 return 13;
21137 case 3:
21138 // op: imm6
21139 return 2;
21140 case 0:
21141 // op: rd
21142 return 7;
21143 }
21144 break;
21145 }
21146 case RISCV::InsnCIW: {
21147 switch (OpNum) {
21148 case 1:
21149 // op: opcode
21150 return 0;
21151 case 2:
21152 // op: funct3
21153 return 13;
21154 case 3:
21155 // op: imm8
21156 return 5;
21157 case 0:
21158 // op: rd
21159 return 2;
21160 }
21161 break;
21162 }
21163 case RISCV::InsnCL: {
21164 switch (OpNum) {
21165 case 1:
21166 // op: opcode
21167 return 0;
21168 case 2:
21169 // op: funct3
21170 return 13;
21171 case 4:
21172 // op: imm5
21173 return 5;
21174 case 0:
21175 // op: rd
21176 return 2;
21177 case 3:
21178 // op: rs1
21179 return 7;
21180 }
21181 break;
21182 }
21183 case RISCV::InsnCR: {
21184 switch (OpNum) {
21185 case 1:
21186 // op: opcode
21187 return 0;
21188 case 2:
21189 // op: funct4
21190 return 12;
21191 case 3:
21192 // op: rs2
21193 return 2;
21194 case 0:
21195 // op: rd
21196 return 7;
21197 }
21198 break;
21199 }
21200 case RISCV::InsnCA: {
21201 switch (OpNum) {
21202 case 1:
21203 // op: opcode
21204 return 0;
21205 case 2:
21206 // op: funct6
21207 return 10;
21208 case 3:
21209 // op: funct2
21210 return 5;
21211 case 0:
21212 // op: rd
21213 return 7;
21214 case 4:
21215 // op: rs2
21216 return 2;
21217 }
21218 break;
21219 }
21220 case RISCV::InsnJ:
21221 case RISCV::InsnU: {
21222 switch (OpNum) {
21223 case 1:
21224 // op: opcode
21225 return 0;
21226 case 2:
21227 // op: imm20
21228 return 12;
21229 case 0:
21230 // op: rd
21231 return 7;
21232 }
21233 break;
21234 }
21235 case RISCV::InsnR4: {
21236 switch (OpNum) {
21237 case 1:
21238 // op: opcode
21239 return 0;
21240 case 3:
21241 // op: funct2
21242 return 25;
21243 case 2:
21244 // op: funct3
21245 return 12;
21246 case 6:
21247 // op: rs3
21248 return 27;
21249 case 5:
21250 // op: rs2
21251 return 20;
21252 case 4:
21253 // op: rs1
21254 return 15;
21255 case 0:
21256 // op: rd
21257 return 7;
21258 }
21259 break;
21260 }
21261 case RISCV::InsnR: {
21262 switch (OpNum) {
21263 case 1:
21264 // op: opcode
21265 return 0;
21266 case 3:
21267 // op: funct7
21268 return 25;
21269 case 2:
21270 // op: funct3
21271 return 12;
21272 case 5:
21273 // op: rs2
21274 return 20;
21275 case 4:
21276 // op: rs1
21277 return 15;
21278 case 0:
21279 // op: rd
21280 return 7;
21281 }
21282 break;
21283 }
21284 case RISCV::QC_C_MULIADD: {
21285 switch (OpNum) {
21286 case 1:
21287 // op: rd
21288 return 2;
21289 case 2:
21290 // op: rs1
21291 return 7;
21292 case 3:
21293 // op: uimm
21294 return 5;
21295 }
21296 break;
21297 }
21298 case RISCV::QC_C_MVEQZ: {
21299 switch (OpNum) {
21300 case 1:
21301 // op: rd
21302 return 2;
21303 case 2:
21304 // op: rs1
21305 return 7;
21306 }
21307 break;
21308 }
21309 case RISCV::QC_E_ADDAI:
21310 case RISCV::QC_E_ANDAI:
21311 case RISCV::QC_E_ORAI:
21312 case RISCV::QC_E_XORAI: {
21313 switch (OpNum) {
21314 case 1:
21315 // op: rd
21316 return 7;
21317 case 2:
21318 // op: imm
21319 return 16;
21320 }
21321 break;
21322 }
21323 case RISCV::QC_C_EXTU: {
21324 switch (OpNum) {
21325 case 1:
21326 // op: rd
21327 return 7;
21328 case 2:
21329 // op: width
21330 return 2;
21331 }
21332 break;
21333 }
21334 case RISCV::C_ADDI_HINT_IMM_ZERO:
21335 case RISCV::C_NOT:
21336 case RISCV::C_SEXT_B:
21337 case RISCV::C_SEXT_H:
21338 case RISCV::C_SLLI64_HINT:
21339 case RISCV::C_ZEXT_B:
21340 case RISCV::C_ZEXT_H:
21341 case RISCV::C_ZEXT_W: {
21342 switch (OpNum) {
21343 case 1:
21344 // op: rd
21345 return 7;
21346 }
21347 break;
21348 }
21349 case RISCV::QC_INSBRI:
21350 case RISCV::QC_WRAPI: {
21351 switch (OpNum) {
21352 case 1:
21353 // op: rs1
21354 return 15;
21355 case 0:
21356 // op: rd
21357 return 7;
21358 case 2:
21359 // op: imm11
21360 return 20;
21361 }
21362 break;
21363 }
21364 case RISCV::ADDI:
21365 case RISCV::ADDIW:
21366 case RISCV::ANDI:
21367 case RISCV::CV_ELW:
21368 case RISCV::FLD:
21369 case RISCV::FLH:
21370 case RISCV::FLQ:
21371 case RISCV::FLW:
21372 case RISCV::JALR:
21373 case RISCV::LB:
21374 case RISCV::LBU:
21375 case RISCV::LD:
21376 case RISCV::LD_RV32:
21377 case RISCV::LH:
21378 case RISCV::LHU:
21379 case RISCV::LH_INX:
21380 case RISCV::LW:
21381 case RISCV::LWU:
21382 case RISCV::LW_INX:
21383 case RISCV::ORI:
21384 case RISCV::SLTI:
21385 case RISCV::SLTIU:
21386 case RISCV::XORI: {
21387 switch (OpNum) {
21388 case 1:
21389 // op: rs1
21390 return 15;
21391 case 0:
21392 // op: rd
21393 return 7;
21394 case 2:
21395 // op: imm12
21396 return 20;
21397 }
21398 break;
21399 }
21400 case RISCV::QC_INW: {
21401 switch (OpNum) {
21402 case 1:
21403 // op: rs1
21404 return 15;
21405 case 0:
21406 // op: rd
21407 return 7;
21408 case 2:
21409 // op: imm14
21410 return 20;
21411 }
21412 break;
21413 }
21414 case RISCV::CV_CLIP:
21415 case RISCV::CV_CLIPU: {
21416 switch (OpNum) {
21417 case 1:
21418 // op: rs1
21419 return 15;
21420 case 0:
21421 // op: rd
21422 return 7;
21423 case 2:
21424 // op: imm5
21425 return 20;
21426 }
21427 break;
21428 }
21429 case RISCV::CV_ADD_SCI_B:
21430 case RISCV::CV_ADD_SCI_H:
21431 case RISCV::CV_AND_SCI_B:
21432 case RISCV::CV_AND_SCI_H:
21433 case RISCV::CV_AVGU_SCI_B:
21434 case RISCV::CV_AVGU_SCI_H:
21435 case RISCV::CV_AVG_SCI_B:
21436 case RISCV::CV_AVG_SCI_H:
21437 case RISCV::CV_CMPEQ_SCI_B:
21438 case RISCV::CV_CMPEQ_SCI_H:
21439 case RISCV::CV_CMPGEU_SCI_B:
21440 case RISCV::CV_CMPGEU_SCI_H:
21441 case RISCV::CV_CMPGE_SCI_B:
21442 case RISCV::CV_CMPGE_SCI_H:
21443 case RISCV::CV_CMPGTU_SCI_B:
21444 case RISCV::CV_CMPGTU_SCI_H:
21445 case RISCV::CV_CMPGT_SCI_B:
21446 case RISCV::CV_CMPGT_SCI_H:
21447 case RISCV::CV_CMPLEU_SCI_B:
21448 case RISCV::CV_CMPLEU_SCI_H:
21449 case RISCV::CV_CMPLE_SCI_B:
21450 case RISCV::CV_CMPLE_SCI_H:
21451 case RISCV::CV_CMPLTU_SCI_B:
21452 case RISCV::CV_CMPLTU_SCI_H:
21453 case RISCV::CV_CMPLT_SCI_B:
21454 case RISCV::CV_CMPLT_SCI_H:
21455 case RISCV::CV_CMPNE_SCI_B:
21456 case RISCV::CV_CMPNE_SCI_H:
21457 case RISCV::CV_DOTSP_SCI_B:
21458 case RISCV::CV_DOTSP_SCI_H:
21459 case RISCV::CV_DOTUP_SCI_B:
21460 case RISCV::CV_DOTUP_SCI_H:
21461 case RISCV::CV_DOTUSP_SCI_B:
21462 case RISCV::CV_DOTUSP_SCI_H:
21463 case RISCV::CV_EXTRACTU_B:
21464 case RISCV::CV_EXTRACTU_H:
21465 case RISCV::CV_EXTRACT_B:
21466 case RISCV::CV_EXTRACT_H:
21467 case RISCV::CV_MAXU_SCI_B:
21468 case RISCV::CV_MAXU_SCI_H:
21469 case RISCV::CV_MAX_SCI_B:
21470 case RISCV::CV_MAX_SCI_H:
21471 case RISCV::CV_MINU_SCI_B:
21472 case RISCV::CV_MINU_SCI_H:
21473 case RISCV::CV_MIN_SCI_B:
21474 case RISCV::CV_MIN_SCI_H:
21475 case RISCV::CV_OR_SCI_B:
21476 case RISCV::CV_OR_SCI_H:
21477 case RISCV::CV_SHUFFLEI0_SCI_B:
21478 case RISCV::CV_SHUFFLEI1_SCI_B:
21479 case RISCV::CV_SHUFFLEI2_SCI_B:
21480 case RISCV::CV_SHUFFLEI3_SCI_B:
21481 case RISCV::CV_SHUFFLE_SCI_H:
21482 case RISCV::CV_SLL_SCI_B:
21483 case RISCV::CV_SLL_SCI_H:
21484 case RISCV::CV_SRA_SCI_B:
21485 case RISCV::CV_SRA_SCI_H:
21486 case RISCV::CV_SRL_SCI_B:
21487 case RISCV::CV_SRL_SCI_H:
21488 case RISCV::CV_SUB_SCI_B:
21489 case RISCV::CV_SUB_SCI_H:
21490 case RISCV::CV_XOR_SCI_B:
21491 case RISCV::CV_XOR_SCI_H: {
21492 switch (OpNum) {
21493 case 1:
21494 // op: rs1
21495 return 15;
21496 case 0:
21497 // op: rd
21498 return 7;
21499 case 2:
21500 // op: imm6
21501 return 20;
21502 }
21503 break;
21504 }
21505 case RISCV::CV_BCLR:
21506 case RISCV::CV_BITREV:
21507 case RISCV::CV_BSET:
21508 case RISCV::CV_EXTRACT:
21509 case RISCV::CV_EXTRACTU: {
21510 switch (OpNum) {
21511 case 1:
21512 // op: rs1
21513 return 15;
21514 case 0:
21515 // op: rd
21516 return 7;
21517 case 2:
21518 // op: is3
21519 return 25;
21520 case 3:
21521 // op: is2
21522 return 20;
21523 }
21524 break;
21525 }
21526 case RISCV::TH_EXT:
21527 case RISCV::TH_EXTU: {
21528 switch (OpNum) {
21529 case 1:
21530 // op: rs1
21531 return 15;
21532 case 0:
21533 // op: rd
21534 return 7;
21535 case 2:
21536 // op: msb
21537 return 26;
21538 case 3:
21539 // op: lsb
21540 return 20;
21541 }
21542 break;
21543 }
21544 case RISCV::AES64KS1I: {
21545 switch (OpNum) {
21546 case 1:
21547 // op: rs1
21548 return 15;
21549 case 0:
21550 // op: rd
21551 return 7;
21552 case 2:
21553 // op: rnum
21554 return 20;
21555 }
21556 break;
21557 }
21558 case RISCV::BCLRI:
21559 case RISCV::BEXTI:
21560 case RISCV::BINVI:
21561 case RISCV::BSETI:
21562 case RISCV::RORI:
21563 case RISCV::RORIW:
21564 case RISCV::SLLI:
21565 case RISCV::SLLIW:
21566 case RISCV::SLLI_UW:
21567 case RISCV::SRAI:
21568 case RISCV::SRAIW:
21569 case RISCV::SRLI:
21570 case RISCV::SRLIW:
21571 case RISCV::TH_SRRI:
21572 case RISCV::TH_SRRIW:
21573 case RISCV::TH_TST: {
21574 switch (OpNum) {
21575 case 1:
21576 // op: rs1
21577 return 15;
21578 case 0:
21579 // op: rd
21580 return 7;
21581 case 2:
21582 // op: shamt
21583 return 20;
21584 }
21585 break;
21586 }
21587 case RISCV::PSLLI_B: {
21588 switch (OpNum) {
21589 case 1:
21590 // op: rs1
21591 return 15;
21592 case 0:
21593 // op: rd
21594 return 7;
21595 case 2:
21596 // op: uimm3
21597 return 20;
21598 }
21599 break;
21600 }
21601 case RISCV::PSLLI_H:
21602 case RISCV::PSSLAI_H: {
21603 switch (OpNum) {
21604 case 1:
21605 // op: rs1
21606 return 15;
21607 case 0:
21608 // op: rd
21609 return 7;
21610 case 2:
21611 // op: uimm4
21612 return 20;
21613 }
21614 break;
21615 }
21616 case RISCV::PSLLI_W:
21617 case RISCV::PSSLAI_W:
21618 case RISCV::SSLAI: {
21619 switch (OpNum) {
21620 case 1:
21621 // op: rs1
21622 return 15;
21623 case 0:
21624 // op: rd
21625 return 7;
21626 case 2:
21627 // op: uimm5
21628 return 20;
21629 }
21630 break;
21631 }
21632 case RISCV::VSETVLI: {
21633 switch (OpNum) {
21634 case 1:
21635 // op: rs1
21636 return 15;
21637 case 0:
21638 // op: rd
21639 return 7;
21640 case 2:
21641 // op: vtypei
21642 return 20;
21643 }
21644 break;
21645 }
21646 case RISCV::QC_EXT:
21647 case RISCV::QC_EXTD:
21648 case RISCV::QC_EXTDU:
21649 case RISCV::QC_EXTU:
21650 case RISCV::QC_INSB:
21651 case RISCV::QC_INSBH: {
21652 switch (OpNum) {
21653 case 1:
21654 // op: rs1
21655 return 15;
21656 case 0:
21657 // op: rd
21658 return 7;
21659 case 3:
21660 // op: shamt
21661 return 20;
21662 case 2:
21663 // op: width
21664 return 25;
21665 }
21666 break;
21667 }
21668 case RISCV::ABS:
21669 case RISCV::ABSW:
21670 case RISCV::AES64IM:
21671 case RISCV::BREV8:
21672 case RISCV::CLS:
21673 case RISCV::CLSW:
21674 case RISCV::CLZ:
21675 case RISCV::CLZW:
21676 case RISCV::CPOP:
21677 case RISCV::CPOPW:
21678 case RISCV::CTZ:
21679 case RISCV::CTZW:
21680 case RISCV::CV_ABS:
21681 case RISCV::CV_ABS_B:
21682 case RISCV::CV_ABS_H:
21683 case RISCV::CV_CLB:
21684 case RISCV::CV_CNT:
21685 case RISCV::CV_CPLXCONJ:
21686 case RISCV::CV_EXTBS:
21687 case RISCV::CV_EXTBZ:
21688 case RISCV::CV_EXTHS:
21689 case RISCV::CV_EXTHZ:
21690 case RISCV::CV_FF1:
21691 case RISCV::CV_FL1:
21692 case RISCV::FCLASS_D:
21693 case RISCV::FCLASS_D_IN32X:
21694 case RISCV::FCLASS_D_INX:
21695 case RISCV::FCLASS_H:
21696 case RISCV::FCLASS_H_INX:
21697 case RISCV::FCLASS_Q:
21698 case RISCV::FCLASS_S:
21699 case RISCV::FCLASS_S_INX:
21700 case RISCV::FMVH_X_D:
21701 case RISCV::FMVH_X_Q:
21702 case RISCV::FMV_D_X:
21703 case RISCV::FMV_H_X:
21704 case RISCV::FMV_W_X:
21705 case RISCV::FMV_X_D:
21706 case RISCV::FMV_X_H:
21707 case RISCV::FMV_X_W:
21708 case RISCV::FMV_X_W_FPR64:
21709 case RISCV::HLVX_HU:
21710 case RISCV::HLVX_WU:
21711 case RISCV::HLV_B:
21712 case RISCV::HLV_BU:
21713 case RISCV::HLV_D:
21714 case RISCV::HLV_H:
21715 case RISCV::HLV_HU:
21716 case RISCV::HLV_W:
21717 case RISCV::HLV_WU:
21718 case RISCV::LB_AQ:
21719 case RISCV::LB_AQ_RL:
21720 case RISCV::LD_AQ:
21721 case RISCV::LD_AQ_RL:
21722 case RISCV::LH_AQ:
21723 case RISCV::LH_AQ_RL:
21724 case RISCV::LR_D:
21725 case RISCV::LR_D_AQ:
21726 case RISCV::LR_D_AQ_RL:
21727 case RISCV::LR_D_RL:
21728 case RISCV::LR_W:
21729 case RISCV::LR_W_AQ:
21730 case RISCV::LR_W_AQ_RL:
21731 case RISCV::LR_W_RL:
21732 case RISCV::LW_AQ:
21733 case RISCV::LW_AQ_RL:
21734 case RISCV::MOPR0:
21735 case RISCV::MOPR1:
21736 case RISCV::MOPR2:
21737 case RISCV::MOPR3:
21738 case RISCV::MOPR4:
21739 case RISCV::MOPR5:
21740 case RISCV::MOPR6:
21741 case RISCV::MOPR7:
21742 case RISCV::MOPR8:
21743 case RISCV::MOPR9:
21744 case RISCV::MOPR10:
21745 case RISCV::MOPR11:
21746 case RISCV::MOPR12:
21747 case RISCV::MOPR13:
21748 case RISCV::MOPR14:
21749 case RISCV::MOPR15:
21750 case RISCV::MOPR16:
21751 case RISCV::MOPR17:
21752 case RISCV::MOPR18:
21753 case RISCV::MOPR19:
21754 case RISCV::MOPR20:
21755 case RISCV::MOPR21:
21756 case RISCV::MOPR22:
21757 case RISCV::MOPR23:
21758 case RISCV::MOPR24:
21759 case RISCV::MOPR25:
21760 case RISCV::MOPR26:
21761 case RISCV::MOPR27:
21762 case RISCV::MOPR28:
21763 case RISCV::MOPR29:
21764 case RISCV::MOPR30:
21765 case RISCV::MOPR31:
21766 case RISCV::ORC_B:
21767 case RISCV::PSABS_B:
21768 case RISCV::PSABS_H:
21769 case RISCV::PSEXT_H_B:
21770 case RISCV::PSEXT_W_B:
21771 case RISCV::PSEXT_W_H:
21772 case RISCV::QC_BREV32:
21773 case RISCV::QC_CLO:
21774 case RISCV::QC_COMPRESS2:
21775 case RISCV::QC_COMPRESS3:
21776 case RISCV::QC_CTO:
21777 case RISCV::QC_EXPAND2:
21778 case RISCV::QC_EXPAND3:
21779 case RISCV::QC_NORM:
21780 case RISCV::QC_NORMEU:
21781 case RISCV::QC_NORMU:
21782 case RISCV::REV8_RV32:
21783 case RISCV::REV8_RV64:
21784 case RISCV::REV16:
21785 case RISCV::REV_RV32:
21786 case RISCV::REV_RV64:
21787 case RISCV::SEXT_B:
21788 case RISCV::SEXT_H:
21789 case RISCV::SF_VSETTK:
21790 case RISCV::SF_VSETTM:
21791 case RISCV::SF_VSETTN:
21792 case RISCV::SHA256SIG0:
21793 case RISCV::SHA256SIG1:
21794 case RISCV::SHA256SUM0:
21795 case RISCV::SHA256SUM1:
21796 case RISCV::SHA512SIG0:
21797 case RISCV::SHA512SIG1:
21798 case RISCV::SHA512SUM0:
21799 case RISCV::SHA512SUM1:
21800 case RISCV::SM3P0:
21801 case RISCV::SM3P1:
21802 case RISCV::TH_FF0:
21803 case RISCV::TH_FF1:
21804 case RISCV::TH_REV:
21805 case RISCV::TH_REVW:
21806 case RISCV::TH_TSTNBZ:
21807 case RISCV::UNZIP_RV32:
21808 case RISCV::ZEXT_H_RV32:
21809 case RISCV::ZEXT_H_RV64:
21810 case RISCV::ZIP_RV32: {
21811 switch (OpNum) {
21812 case 1:
21813 // op: rs1
21814 return 15;
21815 case 0:
21816 // op: rd
21817 return 7;
21818 }
21819 break;
21820 }
21821 case RISCV::QC_E_SB:
21822 case RISCV::QC_E_SH:
21823 case RISCV::QC_E_SW: {
21824 switch (OpNum) {
21825 case 1:
21826 // op: rs1
21827 return 15;
21828 case 0:
21829 // op: rs2
21830 return 20;
21831 case 2:
21832 // op: imm
21833 return 7;
21834 }
21835 break;
21836 }
21837 case RISCV::CV_SB_rr:
21838 case RISCV::CV_SH_rr:
21839 case RISCV::CV_SW_rr: {
21840 switch (OpNum) {
21841 case 1:
21842 // op: rs1
21843 return 15;
21844 case 0:
21845 // op: rs2
21846 return 20;
21847 case 2:
21848 // op: rs3
21849 return 7;
21850 }
21851 break;
21852 }
21853 case RISCV::QC_OUTW: {
21854 switch (OpNum) {
21855 case 1:
21856 // op: rs1
21857 return 15;
21858 case 0:
21859 // op: rs2
21860 return 7;
21861 case 2:
21862 // op: imm14
21863 return 20;
21864 }
21865 break;
21866 }
21867 case RISCV::VLE8FF_V:
21868 case RISCV::VLE8_V:
21869 case RISCV::VLE16FF_V:
21870 case RISCV::VLE16_V:
21871 case RISCV::VLE32FF_V:
21872 case RISCV::VLE32_V:
21873 case RISCV::VLE64FF_V:
21874 case RISCV::VLE64_V:
21875 case RISCV::VLSEG2E8FF_V:
21876 case RISCV::VLSEG2E8_V:
21877 case RISCV::VLSEG2E16FF_V:
21878 case RISCV::VLSEG2E16_V:
21879 case RISCV::VLSEG2E32FF_V:
21880 case RISCV::VLSEG2E32_V:
21881 case RISCV::VLSEG2E64FF_V:
21882 case RISCV::VLSEG2E64_V:
21883 case RISCV::VLSEG3E8FF_V:
21884 case RISCV::VLSEG3E8_V:
21885 case RISCV::VLSEG3E16FF_V:
21886 case RISCV::VLSEG3E16_V:
21887 case RISCV::VLSEG3E32FF_V:
21888 case RISCV::VLSEG3E32_V:
21889 case RISCV::VLSEG3E64FF_V:
21890 case RISCV::VLSEG3E64_V:
21891 case RISCV::VLSEG4E8FF_V:
21892 case RISCV::VLSEG4E8_V:
21893 case RISCV::VLSEG4E16FF_V:
21894 case RISCV::VLSEG4E16_V:
21895 case RISCV::VLSEG4E32FF_V:
21896 case RISCV::VLSEG4E32_V:
21897 case RISCV::VLSEG4E64FF_V:
21898 case RISCV::VLSEG4E64_V:
21899 case RISCV::VLSEG5E8FF_V:
21900 case RISCV::VLSEG5E8_V:
21901 case RISCV::VLSEG5E16FF_V:
21902 case RISCV::VLSEG5E16_V:
21903 case RISCV::VLSEG5E32FF_V:
21904 case RISCV::VLSEG5E32_V:
21905 case RISCV::VLSEG5E64FF_V:
21906 case RISCV::VLSEG5E64_V:
21907 case RISCV::VLSEG6E8FF_V:
21908 case RISCV::VLSEG6E8_V:
21909 case RISCV::VLSEG6E16FF_V:
21910 case RISCV::VLSEG6E16_V:
21911 case RISCV::VLSEG6E32FF_V:
21912 case RISCV::VLSEG6E32_V:
21913 case RISCV::VLSEG6E64FF_V:
21914 case RISCV::VLSEG6E64_V:
21915 case RISCV::VLSEG7E8FF_V:
21916 case RISCV::VLSEG7E8_V:
21917 case RISCV::VLSEG7E16FF_V:
21918 case RISCV::VLSEG7E16_V:
21919 case RISCV::VLSEG7E32FF_V:
21920 case RISCV::VLSEG7E32_V:
21921 case RISCV::VLSEG7E64FF_V:
21922 case RISCV::VLSEG7E64_V:
21923 case RISCV::VLSEG8E8FF_V:
21924 case RISCV::VLSEG8E8_V:
21925 case RISCV::VLSEG8E16FF_V:
21926 case RISCV::VLSEG8E16_V:
21927 case RISCV::VLSEG8E32FF_V:
21928 case RISCV::VLSEG8E32_V:
21929 case RISCV::VLSEG8E64FF_V:
21930 case RISCV::VLSEG8E64_V: {
21931 switch (OpNum) {
21932 case 1:
21933 // op: rs1
21934 return 15;
21935 case 0:
21936 // op: vd
21937 return 7;
21938 case 2:
21939 // op: vm
21940 return 25;
21941 }
21942 break;
21943 }
21944 case RISCV::SF_VTMV_V_T:
21945 case RISCV::VFMV_V_F:
21946 case RISCV::VL1RE8_V:
21947 case RISCV::VL1RE16_V:
21948 case RISCV::VL1RE32_V:
21949 case RISCV::VL1RE64_V:
21950 case RISCV::VL2RE8_V:
21951 case RISCV::VL2RE16_V:
21952 case RISCV::VL2RE32_V:
21953 case RISCV::VL2RE64_V:
21954 case RISCV::VL4RE8_V:
21955 case RISCV::VL4RE16_V:
21956 case RISCV::VL4RE32_V:
21957 case RISCV::VL4RE64_V:
21958 case RISCV::VL8RE8_V:
21959 case RISCV::VL8RE16_V:
21960 case RISCV::VL8RE32_V:
21961 case RISCV::VL8RE64_V:
21962 case RISCV::VLM_V:
21963 case RISCV::VMV_V_X: {
21964 switch (OpNum) {
21965 case 1:
21966 // op: rs1
21967 return 15;
21968 case 0:
21969 // op: vd
21970 return 7;
21971 }
21972 break;
21973 }
21974 case RISCV::VSE8_V:
21975 case RISCV::VSE16_V:
21976 case RISCV::VSE32_V:
21977 case RISCV::VSE64_V:
21978 case RISCV::VSSEG2E8_V:
21979 case RISCV::VSSEG2E16_V:
21980 case RISCV::VSSEG2E32_V:
21981 case RISCV::VSSEG2E64_V:
21982 case RISCV::VSSEG3E8_V:
21983 case RISCV::VSSEG3E16_V:
21984 case RISCV::VSSEG3E32_V:
21985 case RISCV::VSSEG3E64_V:
21986 case RISCV::VSSEG4E8_V:
21987 case RISCV::VSSEG4E16_V:
21988 case RISCV::VSSEG4E32_V:
21989 case RISCV::VSSEG4E64_V:
21990 case RISCV::VSSEG5E8_V:
21991 case RISCV::VSSEG5E16_V:
21992 case RISCV::VSSEG5E32_V:
21993 case RISCV::VSSEG5E64_V:
21994 case RISCV::VSSEG6E8_V:
21995 case RISCV::VSSEG6E16_V:
21996 case RISCV::VSSEG6E32_V:
21997 case RISCV::VSSEG6E64_V:
21998 case RISCV::VSSEG7E8_V:
21999 case RISCV::VSSEG7E16_V:
22000 case RISCV::VSSEG7E32_V:
22001 case RISCV::VSSEG7E64_V:
22002 case RISCV::VSSEG8E8_V:
22003 case RISCV::VSSEG8E16_V:
22004 case RISCV::VSSEG8E32_V:
22005 case RISCV::VSSEG8E64_V: {
22006 switch (OpNum) {
22007 case 1:
22008 // op: rs1
22009 return 15;
22010 case 0:
22011 // op: vs3
22012 return 7;
22013 case 2:
22014 // op: vm
22015 return 25;
22016 }
22017 break;
22018 }
22019 case RISCV::VS1R_V:
22020 case RISCV::VS2R_V:
22021 case RISCV::VS4R_V:
22022 case RISCV::VS8R_V:
22023 case RISCV::VSM_V: {
22024 switch (OpNum) {
22025 case 1:
22026 // op: rs1
22027 return 15;
22028 case 0:
22029 // op: vs3
22030 return 7;
22031 }
22032 break;
22033 }
22034 case RISCV::FCVTMOD_W_D:
22035 case RISCV::FCVT_BF16_S:
22036 case RISCV::FCVT_D_H:
22037 case RISCV::FCVT_D_H_IN32X:
22038 case RISCV::FCVT_D_H_INX:
22039 case RISCV::FCVT_D_L:
22040 case RISCV::FCVT_D_LU:
22041 case RISCV::FCVT_D_LU_INX:
22042 case RISCV::FCVT_D_L_INX:
22043 case RISCV::FCVT_D_Q:
22044 case RISCV::FCVT_D_S:
22045 case RISCV::FCVT_D_S_IN32X:
22046 case RISCV::FCVT_D_S_INX:
22047 case RISCV::FCVT_D_W:
22048 case RISCV::FCVT_D_WU:
22049 case RISCV::FCVT_D_WU_IN32X:
22050 case RISCV::FCVT_D_WU_INX:
22051 case RISCV::FCVT_D_W_IN32X:
22052 case RISCV::FCVT_D_W_INX:
22053 case RISCV::FCVT_H_D:
22054 case RISCV::FCVT_H_D_IN32X:
22055 case RISCV::FCVT_H_D_INX:
22056 case RISCV::FCVT_H_L:
22057 case RISCV::FCVT_H_LU:
22058 case RISCV::FCVT_H_LU_INX:
22059 case RISCV::FCVT_H_L_INX:
22060 case RISCV::FCVT_H_S:
22061 case RISCV::FCVT_H_S_INX:
22062 case RISCV::FCVT_H_W:
22063 case RISCV::FCVT_H_WU:
22064 case RISCV::FCVT_H_WU_INX:
22065 case RISCV::FCVT_H_W_INX:
22066 case RISCV::FCVT_LU_D:
22067 case RISCV::FCVT_LU_D_INX:
22068 case RISCV::FCVT_LU_H:
22069 case RISCV::FCVT_LU_H_INX:
22070 case RISCV::FCVT_LU_Q:
22071 case RISCV::FCVT_LU_S:
22072 case RISCV::FCVT_LU_S_INX:
22073 case RISCV::FCVT_L_D:
22074 case RISCV::FCVT_L_D_INX:
22075 case RISCV::FCVT_L_H:
22076 case RISCV::FCVT_L_H_INX:
22077 case RISCV::FCVT_L_Q:
22078 case RISCV::FCVT_L_S:
22079 case RISCV::FCVT_L_S_INX:
22080 case RISCV::FCVT_Q_D:
22081 case RISCV::FCVT_Q_L:
22082 case RISCV::FCVT_Q_LU:
22083 case RISCV::FCVT_Q_S:
22084 case RISCV::FCVT_Q_W:
22085 case RISCV::FCVT_Q_WU:
22086 case RISCV::FCVT_S_BF16:
22087 case RISCV::FCVT_S_D:
22088 case RISCV::FCVT_S_D_IN32X:
22089 case RISCV::FCVT_S_D_INX:
22090 case RISCV::FCVT_S_H:
22091 case RISCV::FCVT_S_H_INX:
22092 case RISCV::FCVT_S_L:
22093 case RISCV::FCVT_S_LU:
22094 case RISCV::FCVT_S_LU_INX:
22095 case RISCV::FCVT_S_L_INX:
22096 case RISCV::FCVT_S_Q:
22097 case RISCV::FCVT_S_W:
22098 case RISCV::FCVT_S_WU:
22099 case RISCV::FCVT_S_WU_INX:
22100 case RISCV::FCVT_S_W_INX:
22101 case RISCV::FCVT_WU_D:
22102 case RISCV::FCVT_WU_D_IN32X:
22103 case RISCV::FCVT_WU_D_INX:
22104 case RISCV::FCVT_WU_H:
22105 case RISCV::FCVT_WU_H_INX:
22106 case RISCV::FCVT_WU_Q:
22107 case RISCV::FCVT_WU_S:
22108 case RISCV::FCVT_WU_S_INX:
22109 case RISCV::FCVT_W_D:
22110 case RISCV::FCVT_W_D_IN32X:
22111 case RISCV::FCVT_W_D_INX:
22112 case RISCV::FCVT_W_H:
22113 case RISCV::FCVT_W_H_INX:
22114 case RISCV::FCVT_W_Q:
22115 case RISCV::FCVT_W_S:
22116 case RISCV::FCVT_W_S_INX:
22117 case RISCV::FROUNDNX_D:
22118 case RISCV::FROUNDNX_H:
22119 case RISCV::FROUNDNX_Q:
22120 case RISCV::FROUNDNX_S:
22121 case RISCV::FROUND_D:
22122 case RISCV::FROUND_H:
22123 case RISCV::FROUND_Q:
22124 case RISCV::FROUND_S:
22125 case RISCV::FSQRT_D:
22126 case RISCV::FSQRT_D_IN32X:
22127 case RISCV::FSQRT_D_INX:
22128 case RISCV::FSQRT_H:
22129 case RISCV::FSQRT_H_INX:
22130 case RISCV::FSQRT_Q:
22131 case RISCV::FSQRT_S:
22132 case RISCV::FSQRT_S_INX: {
22133 switch (OpNum) {
22134 case 1:
22135 // op: rs1
22136 return 15;
22137 case 2:
22138 // op: frm
22139 return 12;
22140 case 0:
22141 // op: rd
22142 return 7;
22143 }
22144 break;
22145 }
22146 case RISCV::C_ADD: {
22147 switch (OpNum) {
22148 case 1:
22149 // op: rs1
22150 return 7;
22151 case 2:
22152 // op: rs2
22153 return 2;
22154 }
22155 break;
22156 }
22157 case RISCV::QC_C_BEXTI:
22158 case RISCV::QC_C_BSETI: {
22159 switch (OpNum) {
22160 case 1:
22161 // op: rs1
22162 return 7;
22163 case 2:
22164 // op: shamt
22165 return 2;
22166 }
22167 break;
22168 }
22169 case RISCV::C_SRAI64_HINT:
22170 case RISCV::C_SRLI64_HINT: {
22171 switch (OpNum) {
22172 case 1:
22173 // op: rs1
22174 return 7;
22175 }
22176 break;
22177 }
22178 case RISCV::HFENCE_GVMA:
22179 case RISCV::HFENCE_VVMA:
22180 case RISCV::HINVAL_GVMA:
22181 case RISCV::HINVAL_VVMA:
22182 case RISCV::SB_AQ_RL:
22183 case RISCV::SB_RL:
22184 case RISCV::SD_AQ_RL:
22185 case RISCV::SD_RL:
22186 case RISCV::SFENCE_VMA:
22187 case RISCV::SF_VTMV_T_V:
22188 case RISCV::SH_AQ_RL:
22189 case RISCV::SH_RL:
22190 case RISCV::SINVAL_VMA:
22191 case RISCV::SW_AQ_RL:
22192 case RISCV::SW_RL:
22193 case RISCV::TH_SFENCE_VMAS: {
22194 switch (OpNum) {
22195 case 1:
22196 // op: rs2
22197 return 20;
22198 case 0:
22199 // op: rs1
22200 return 15;
22201 }
22202 break;
22203 }
22204 case RISCV::TH_LDD:
22205 case RISCV::TH_LWD:
22206 case RISCV::TH_LWUD:
22207 case RISCV::TH_SDD:
22208 case RISCV::TH_SWD: {
22209 switch (OpNum) {
22210 case 1:
22211 // op: rs2
22212 return 20;
22213 case 2:
22214 // op: rs1
22215 return 15;
22216 case 0:
22217 // op: rd
22218 return 7;
22219 case 3:
22220 // op: uimm2
22221 return 25;
22222 }
22223 break;
22224 }
22225 case RISCV::NDS_LEA_B_ZE:
22226 case RISCV::NDS_LEA_D:
22227 case RISCV::NDS_LEA_D_ZE:
22228 case RISCV::NDS_LEA_H:
22229 case RISCV::NDS_LEA_H_ZE:
22230 case RISCV::NDS_LEA_W:
22231 case RISCV::NDS_LEA_W_ZE: {
22232 switch (OpNum) {
22233 case 1:
22234 // op: rs2
22235 return 20;
22236 case 2:
22237 // op: rs1
22238 return 15;
22239 case 0:
22240 // op: rd
22241 return 7;
22242 }
22243 break;
22244 }
22245 case RISCV::SF_VC_I:
22246 case RISCV::SF_VC_X: {
22247 switch (OpNum) {
22248 case 1:
22249 // op: rs2
22250 return 20;
22251 case 3:
22252 // op: rs1
22253 return 15;
22254 case 2:
22255 // op: rd
22256 return 7;
22257 case 0:
22258 // op: funct6_lo2
22259 return 26;
22260 }
22261 break;
22262 }
22263 case RISCV::CM_MVA01S:
22264 case RISCV::CM_MVSA01:
22265 case RISCV::QC_CM_MVA01S:
22266 case RISCV::QC_CM_MVSA01: {
22267 switch (OpNum) {
22268 case 1:
22269 // op: rs2
22270 return 2;
22271 case 0:
22272 // op: rs1
22273 return 7;
22274 }
22275 break;
22276 }
22277 case RISCV::C_MV_HINT: {
22278 switch (OpNum) {
22279 case 1:
22280 // op: rs2
22281 return 2;
22282 }
22283 break;
22284 }
22285 case RISCV::VSETIVLI: {
22286 switch (OpNum) {
22287 case 1:
22288 // op: uimm
22289 return 15;
22290 case 0:
22291 // op: rd
22292 return 7;
22293 case 2:
22294 // op: vtypei
22295 return 20;
22296 }
22297 break;
22298 }
22299 case RISCV::VMV_V_V: {
22300 switch (OpNum) {
22301 case 1:
22302 // op: vs1
22303 return 15;
22304 case 0:
22305 // op: vd
22306 return 7;
22307 }
22308 break;
22309 }
22310 case RISCV::VBREV8_V:
22311 case RISCV::VBREV_V:
22312 case RISCV::VCLZ_V:
22313 case RISCV::VCPOP_M:
22314 case RISCV::VCPOP_V:
22315 case RISCV::VCTZ_V:
22316 case RISCV::VFCLASS_V:
22317 case RISCV::VFCVT_F_XU_V:
22318 case RISCV::VFCVT_F_X_V:
22319 case RISCV::VFCVT_RTZ_XU_F_V:
22320 case RISCV::VFCVT_RTZ_X_F_V:
22321 case RISCV::VFCVT_XU_F_V:
22322 case RISCV::VFCVT_X_F_V:
22323 case RISCV::VFIRST_M:
22324 case RISCV::VFNCVTBF16_F_F_W:
22325 case RISCV::VFNCVT_F_F_W:
22326 case RISCV::VFNCVT_F_XU_W:
22327 case RISCV::VFNCVT_F_X_W:
22328 case RISCV::VFNCVT_ROD_F_F_W:
22329 case RISCV::VFNCVT_RTZ_XU_F_W:
22330 case RISCV::VFNCVT_RTZ_X_F_W:
22331 case RISCV::VFNCVT_XU_F_W:
22332 case RISCV::VFNCVT_X_F_W:
22333 case RISCV::VFREC7_V:
22334 case RISCV::VFRSQRT7_V:
22335 case RISCV::VFSQRT_V:
22336 case RISCV::VFWCVTBF16_F_F_V:
22337 case RISCV::VFWCVT_F_F_V:
22338 case RISCV::VFWCVT_F_XU_V:
22339 case RISCV::VFWCVT_F_X_V:
22340 case RISCV::VFWCVT_RTZ_XU_F_V:
22341 case RISCV::VFWCVT_RTZ_X_F_V:
22342 case RISCV::VFWCVT_XU_F_V:
22343 case RISCV::VFWCVT_X_F_V:
22344 case RISCV::VIOTA_M:
22345 case RISCV::VMSBF_M:
22346 case RISCV::VMSIF_M:
22347 case RISCV::VMSOF_M:
22348 case RISCV::VREV8_V:
22349 case RISCV::VSEXT_VF2:
22350 case RISCV::VSEXT_VF4:
22351 case RISCV::VSEXT_VF8:
22352 case RISCV::VZEXT_VF2:
22353 case RISCV::VZEXT_VF4:
22354 case RISCV::VZEXT_VF8: {
22355 switch (OpNum) {
22356 case 1:
22357 // op: vs2
22358 return 20;
22359 case 0:
22360 // op: vd
22361 return 7;
22362 case 2:
22363 // op: vm
22364 return 25;
22365 }
22366 break;
22367 }
22368 case RISCV::NDS_VFNCVT_BF16_S:
22369 case RISCV::NDS_VFWCVT_S_BF16:
22370 case RISCV::VFMV_F_S:
22371 case RISCV::VMV1R_V:
22372 case RISCV::VMV2R_V:
22373 case RISCV::VMV4R_V:
22374 case RISCV::VMV8R_V:
22375 case RISCV::VMV_X_S: {
22376 switch (OpNum) {
22377 case 1:
22378 // op: vs2
22379 return 20;
22380 case 0:
22381 // op: vd
22382 return 7;
22383 }
22384 break;
22385 }
22386 case RISCV::VADC_VIM:
22387 case RISCV::VADD_VI:
22388 case RISCV::VAND_VI:
22389 case RISCV::VMADC_VIM:
22390 case RISCV::VMERGE_VIM:
22391 case RISCV::VMSEQ_VI:
22392 case RISCV::VMSGTU_VI:
22393 case RISCV::VMSGT_VI:
22394 case RISCV::VMSLEU_VI:
22395 case RISCV::VMSLE_VI:
22396 case RISCV::VMSNE_VI:
22397 case RISCV::VNCLIPU_WI:
22398 case RISCV::VNCLIP_WI:
22399 case RISCV::VNSRA_WI:
22400 case RISCV::VNSRL_WI:
22401 case RISCV::VOR_VI:
22402 case RISCV::VRGATHER_VI:
22403 case RISCV::VROR_VI:
22404 case RISCV::VRSUB_VI:
22405 case RISCV::VSADDU_VI:
22406 case RISCV::VSADD_VI:
22407 case RISCV::VSLIDEDOWN_VI:
22408 case RISCV::VSLIDEUP_VI:
22409 case RISCV::VSLL_VI:
22410 case RISCV::VSRA_VI:
22411 case RISCV::VSRL_VI:
22412 case RISCV::VSSRA_VI:
22413 case RISCV::VSSRL_VI:
22414 case RISCV::VWSLL_VI:
22415 case RISCV::VXOR_VI: {
22416 switch (OpNum) {
22417 case 1:
22418 // op: vs2
22419 return 20;
22420 case 2:
22421 // op: imm
22422 return 15;
22423 case 0:
22424 // op: vd
22425 return 7;
22426 case 3:
22427 // op: vm
22428 return 25;
22429 }
22430 break;
22431 }
22432 case RISCV::VAESKF1_VI:
22433 case RISCV::VMADC_VI:
22434 case RISCV::VSM4K_VI: {
22435 switch (OpNum) {
22436 case 1:
22437 // op: vs2
22438 return 20;
22439 case 2:
22440 // op: imm
22441 return 15;
22442 case 0:
22443 // op: vd
22444 return 7;
22445 }
22446 break;
22447 }
22448 case RISCV::NDS_VFPMADB_VF:
22449 case RISCV::NDS_VFPMADT_VF:
22450 case RISCV::SF_VFNRCLIP_XU_F_QF:
22451 case RISCV::SF_VFNRCLIP_X_F_QF:
22452 case RISCV::VAADDU_VX:
22453 case RISCV::VAADD_VX:
22454 case RISCV::VADC_VXM:
22455 case RISCV::VADD_VX:
22456 case RISCV::VANDN_VX:
22457 case RISCV::VAND_VX:
22458 case RISCV::VASUBU_VX:
22459 case RISCV::VASUB_VX:
22460 case RISCV::VCLMULH_VX:
22461 case RISCV::VCLMUL_VX:
22462 case RISCV::VDIVU_VX:
22463 case RISCV::VDIV_VX:
22464 case RISCV::VFADD_VF:
22465 case RISCV::VFDIV_VF:
22466 case RISCV::VFMAX_VF:
22467 case RISCV::VFMERGE_VFM:
22468 case RISCV::VFMIN_VF:
22469 case RISCV::VFMUL_VF:
22470 case RISCV::VFRDIV_VF:
22471 case RISCV::VFRSUB_VF:
22472 case RISCV::VFSGNJN_VF:
22473 case RISCV::VFSGNJX_VF:
22474 case RISCV::VFSGNJ_VF:
22475 case RISCV::VFSLIDE1DOWN_VF:
22476 case RISCV::VFSLIDE1UP_VF:
22477 case RISCV::VFSUB_VF:
22478 case RISCV::VFWADD_VF:
22479 case RISCV::VFWADD_WF:
22480 case RISCV::VFWMUL_VF:
22481 case RISCV::VFWSUB_VF:
22482 case RISCV::VFWSUB_WF:
22483 case RISCV::VMADC_VXM:
22484 case RISCV::VMAXU_VX:
22485 case RISCV::VMAX_VX:
22486 case RISCV::VMERGE_VXM:
22487 case RISCV::VMFEQ_VF:
22488 case RISCV::VMFGE_VF:
22489 case RISCV::VMFGT_VF:
22490 case RISCV::VMFLE_VF:
22491 case RISCV::VMFLT_VF:
22492 case RISCV::VMFNE_VF:
22493 case RISCV::VMINU_VX:
22494 case RISCV::VMIN_VX:
22495 case RISCV::VMSBC_VXM:
22496 case RISCV::VMSEQ_VX:
22497 case RISCV::VMSGTU_VX:
22498 case RISCV::VMSGT_VX:
22499 case RISCV::VMSLEU_VX:
22500 case RISCV::VMSLE_VX:
22501 case RISCV::VMSLTU_VX:
22502 case RISCV::VMSLT_VX:
22503 case RISCV::VMSNE_VX:
22504 case RISCV::VMULHSU_VX:
22505 case RISCV::VMULHU_VX:
22506 case RISCV::VMULH_VX:
22507 case RISCV::VMUL_VX:
22508 case RISCV::VNCLIPU_WX:
22509 case RISCV::VNCLIP_WX:
22510 case RISCV::VNSRA_WX:
22511 case RISCV::VNSRL_WX:
22512 case RISCV::VOR_VX:
22513 case RISCV::VQDOTSU_VX:
22514 case RISCV::VQDOTUS_VX:
22515 case RISCV::VQDOTU_VX:
22516 case RISCV::VQDOT_VX:
22517 case RISCV::VREMU_VX:
22518 case RISCV::VREM_VX:
22519 case RISCV::VRGATHER_VX:
22520 case RISCV::VROL_VX:
22521 case RISCV::VROR_VX:
22522 case RISCV::VRSUB_VX:
22523 case RISCV::VSADDU_VX:
22524 case RISCV::VSADD_VX:
22525 case RISCV::VSBC_VXM:
22526 case RISCV::VSLIDE1DOWN_VX:
22527 case RISCV::VSLIDE1UP_VX:
22528 case RISCV::VSLIDEDOWN_VX:
22529 case RISCV::VSLIDEUP_VX:
22530 case RISCV::VSLL_VX:
22531 case RISCV::VSMUL_VX:
22532 case RISCV::VSRA_VX:
22533 case RISCV::VSRL_VX:
22534 case RISCV::VSSRA_VX:
22535 case RISCV::VSSRL_VX:
22536 case RISCV::VSSUBU_VX:
22537 case RISCV::VSSUB_VX:
22538 case RISCV::VSUB_VX:
22539 case RISCV::VWADDU_VX:
22540 case RISCV::VWADDU_WX:
22541 case RISCV::VWADD_VX:
22542 case RISCV::VWADD_WX:
22543 case RISCV::VWMULSU_VX:
22544 case RISCV::VWMULU_VX:
22545 case RISCV::VWMUL_VX:
22546 case RISCV::VWSLL_VX:
22547 case RISCV::VWSUBU_VX:
22548 case RISCV::VWSUBU_WX:
22549 case RISCV::VWSUB_VX:
22550 case RISCV::VWSUB_WX:
22551 case RISCV::VXOR_VX: {
22552 switch (OpNum) {
22553 case 1:
22554 // op: vs2
22555 return 20;
22556 case 2:
22557 // op: rs1
22558 return 15;
22559 case 0:
22560 // op: vd
22561 return 7;
22562 case 3:
22563 // op: vm
22564 return 25;
22565 }
22566 break;
22567 }
22568 case RISCV::VMADC_VX:
22569 case RISCV::VMSBC_VX: {
22570 switch (OpNum) {
22571 case 1:
22572 // op: vs2
22573 return 20;
22574 case 2:
22575 // op: rs1
22576 return 15;
22577 case 0:
22578 // op: vd
22579 return 7;
22580 }
22581 break;
22582 }
22583 case RISCV::SF_MM_E4M3_E4M3:
22584 case RISCV::SF_MM_E4M3_E5M2:
22585 case RISCV::SF_MM_E5M2_E4M3:
22586 case RISCV::SF_MM_E5M2_E5M2:
22587 case RISCV::SF_MM_S_S:
22588 case RISCV::SF_MM_S_U:
22589 case RISCV::SF_MM_U_S:
22590 case RISCV::SF_MM_U_U: {
22591 switch (OpNum) {
22592 case 1:
22593 // op: vs2
22594 return 20;
22595 case 2:
22596 // op: vs1
22597 return 15;
22598 case 0:
22599 // op: rd
22600 return 10;
22601 }
22602 break;
22603 }
22604 case RISCV::SF_MM_F_F: {
22605 switch (OpNum) {
22606 case 1:
22607 // op: vs2
22608 return 20;
22609 case 2:
22610 // op: vs1
22611 return 15;
22612 case 0:
22613 // op: rd
22614 return 9;
22615 }
22616 break;
22617 }
22618 case RISCV::RI_VUNZIP2A_VV:
22619 case RISCV::RI_VUNZIP2B_VV:
22620 case RISCV::RI_VZIP2A_VV:
22621 case RISCV::RI_VZIP2B_VV:
22622 case RISCV::RI_VZIPEVEN_VV:
22623 case RISCV::RI_VZIPODD_VV:
22624 case RISCV::VAADDU_VV:
22625 case RISCV::VAADD_VV:
22626 case RISCV::VADC_VVM:
22627 case RISCV::VADD_VV:
22628 case RISCV::VANDN_VV:
22629 case RISCV::VAND_VV:
22630 case RISCV::VASUBU_VV:
22631 case RISCV::VASUB_VV:
22632 case RISCV::VCLMULH_VV:
22633 case RISCV::VCLMUL_VV:
22634 case RISCV::VDIVU_VV:
22635 case RISCV::VDIV_VV:
22636 case RISCV::VFADD_VV:
22637 case RISCV::VFDIV_VV:
22638 case RISCV::VFMAX_VV:
22639 case RISCV::VFMIN_VV:
22640 case RISCV::VFMUL_VV:
22641 case RISCV::VFREDMAX_VS:
22642 case RISCV::VFREDMIN_VS:
22643 case RISCV::VFREDOSUM_VS:
22644 case RISCV::VFREDUSUM_VS:
22645 case RISCV::VFSGNJN_VV:
22646 case RISCV::VFSGNJX_VV:
22647 case RISCV::VFSGNJ_VV:
22648 case RISCV::VFSUB_VV:
22649 case RISCV::VFWADD_VV:
22650 case RISCV::VFWADD_WV:
22651 case RISCV::VFWMUL_VV:
22652 case RISCV::VFWREDOSUM_VS:
22653 case RISCV::VFWREDUSUM_VS:
22654 case RISCV::VFWSUB_VV:
22655 case RISCV::VFWSUB_WV:
22656 case RISCV::VMADC_VVM:
22657 case RISCV::VMAXU_VV:
22658 case RISCV::VMAX_VV:
22659 case RISCV::VMERGE_VVM:
22660 case RISCV::VMFEQ_VV:
22661 case RISCV::VMFLE_VV:
22662 case RISCV::VMFLT_VV:
22663 case RISCV::VMFNE_VV:
22664 case RISCV::VMINU_VV:
22665 case RISCV::VMIN_VV:
22666 case RISCV::VMSBC_VVM:
22667 case RISCV::VMSEQ_VV:
22668 case RISCV::VMSLEU_VV:
22669 case RISCV::VMSLE_VV:
22670 case RISCV::VMSLTU_VV:
22671 case RISCV::VMSLT_VV:
22672 case RISCV::VMSNE_VV:
22673 case RISCV::VMULHSU_VV:
22674 case RISCV::VMULHU_VV:
22675 case RISCV::VMULH_VV:
22676 case RISCV::VMUL_VV:
22677 case RISCV::VNCLIPU_WV:
22678 case RISCV::VNCLIP_WV:
22679 case RISCV::VNSRA_WV:
22680 case RISCV::VNSRL_WV:
22681 case RISCV::VOR_VV:
22682 case RISCV::VQDOTSU_VV:
22683 case RISCV::VQDOTU_VV:
22684 case RISCV::VQDOT_VV:
22685 case RISCV::VREDAND_VS:
22686 case RISCV::VREDMAXU_VS:
22687 case RISCV::VREDMAX_VS:
22688 case RISCV::VREDMINU_VS:
22689 case RISCV::VREDMIN_VS:
22690 case RISCV::VREDOR_VS:
22691 case RISCV::VREDSUM_VS:
22692 case RISCV::VREDXOR_VS:
22693 case RISCV::VREMU_VV:
22694 case RISCV::VREM_VV:
22695 case RISCV::VRGATHEREI16_VV:
22696 case RISCV::VRGATHER_VV:
22697 case RISCV::VROL_VV:
22698 case RISCV::VROR_VV:
22699 case RISCV::VSADDU_VV:
22700 case RISCV::VSADD_VV:
22701 case RISCV::VSBC_VVM:
22702 case RISCV::VSLL_VV:
22703 case RISCV::VSMUL_VV:
22704 case RISCV::VSRA_VV:
22705 case RISCV::VSRL_VV:
22706 case RISCV::VSSRA_VV:
22707 case RISCV::VSSRL_VV:
22708 case RISCV::VSSUBU_VV:
22709 case RISCV::VSSUB_VV:
22710 case RISCV::VSUB_VV:
22711 case RISCV::VWADDU_VV:
22712 case RISCV::VWADDU_WV:
22713 case RISCV::VWADD_VV:
22714 case RISCV::VWADD_WV:
22715 case RISCV::VWMULSU_VV:
22716 case RISCV::VWMULU_VV:
22717 case RISCV::VWMUL_VV:
22718 case RISCV::VWREDSUMU_VS:
22719 case RISCV::VWREDSUM_VS:
22720 case RISCV::VWSLL_VV:
22721 case RISCV::VWSUBU_VV:
22722 case RISCV::VWSUBU_WV:
22723 case RISCV::VWSUB_VV:
22724 case RISCV::VWSUB_WV:
22725 case RISCV::VXOR_VV: {
22726 switch (OpNum) {
22727 case 1:
22728 // op: vs2
22729 return 20;
22730 case 2:
22731 // op: vs1
22732 return 15;
22733 case 0:
22734 // op: vd
22735 return 7;
22736 case 3:
22737 // op: vm
22738 return 25;
22739 }
22740 break;
22741 }
22742 case RISCV::VCOMPRESS_VM:
22743 case RISCV::VMADC_VV:
22744 case RISCV::VMANDN_MM:
22745 case RISCV::VMAND_MM:
22746 case RISCV::VMNAND_MM:
22747 case RISCV::VMNOR_MM:
22748 case RISCV::VMORN_MM:
22749 case RISCV::VMOR_MM:
22750 case RISCV::VMSBC_VV:
22751 case RISCV::VMXNOR_MM:
22752 case RISCV::VMXOR_MM:
22753 case RISCV::VSM3ME_VV: {
22754 switch (OpNum) {
22755 case 1:
22756 // op: vs2
22757 return 20;
22758 case 2:
22759 // op: vs1
22760 return 15;
22761 case 0:
22762 // op: vd
22763 return 7;
22764 }
22765 break;
22766 }
22767 case RISCV::RI_VEXTRACT: {
22768 switch (OpNum) {
22769 case 2:
22770 // op: imm
22771 return 15;
22772 case 1:
22773 // op: vs2
22774 return 20;
22775 case 0:
22776 // op: rd
22777 return 7;
22778 }
22779 break;
22780 }
22781 case RISCV::C_FLDSP:
22782 case RISCV::C_FLWSP:
22783 case RISCV::C_LDSP:
22784 case RISCV::C_LDSP_RV32:
22785 case RISCV::C_LWSP:
22786 case RISCV::C_LWSP_INX: {
22787 switch (OpNum) {
22788 case 2:
22789 // op: imm
22790 return 2;
22791 case 0:
22792 // op: rd
22793 return 7;
22794 }
22795 break;
22796 }
22797 case RISCV::C_ADDI:
22798 case RISCV::C_ADDIW:
22799 case RISCV::C_SLLI: {
22800 switch (OpNum) {
22801 case 2:
22802 // op: imm
22803 return 2;
22804 case 1:
22805 // op: rd
22806 return 7;
22807 }
22808 break;
22809 }
22810 case RISCV::C_ANDI:
22811 case RISCV::C_SRAI:
22812 case RISCV::C_SRLI: {
22813 switch (OpNum) {
22814 case 2:
22815 // op: imm
22816 return 2;
22817 case 1:
22818 // op: rs1
22819 return 7;
22820 }
22821 break;
22822 }
22823 case RISCV::C_ADDI16SP:
22824 case RISCV::C_SLLI_HINT: {
22825 switch (OpNum) {
22826 case 2:
22827 // op: imm
22828 return 2;
22829 }
22830 break;
22831 }
22832 case RISCV::C_ADDI4SPN: {
22833 switch (OpNum) {
22834 case 2:
22835 // op: imm
22836 return 5;
22837 case 0:
22838 // op: rd
22839 return 2;
22840 }
22841 break;
22842 }
22843 case RISCV::C_FSDSP:
22844 case RISCV::C_FSWSP:
22845 case RISCV::C_SDSP:
22846 case RISCV::C_SDSP_RV32:
22847 case RISCV::C_SWSP:
22848 case RISCV::C_SWSP_INX: {
22849 switch (OpNum) {
22850 case 2:
22851 // op: imm
22852 return 7;
22853 case 0:
22854 // op: rs2
22855 return 2;
22856 }
22857 break;
22858 }
22859 case RISCV::NDS_BBC:
22860 case RISCV::NDS_BBS:
22861 case RISCV::NDS_BEQC:
22862 case RISCV::NDS_BNEC: {
22863 switch (OpNum) {
22864 case 2:
22865 // op: imm10
22866 return 8;
22867 case 0:
22868 // op: rs1
22869 return 15;
22870 case 1:
22871 // op: cimm
22872 return 7;
22873 }
22874 break;
22875 }
22876 case RISCV::CV_BEQIMM:
22877 case RISCV::CV_BNEIMM: {
22878 switch (OpNum) {
22879 case 2:
22880 // op: imm12
22881 return 7;
22882 case 0:
22883 // op: rs1
22884 return 15;
22885 case 1:
22886 // op: imm5
22887 return 20;
22888 }
22889 break;
22890 }
22891 case RISCV::FSD:
22892 case RISCV::FSH:
22893 case RISCV::FSQ:
22894 case RISCV::FSW:
22895 case RISCV::SB:
22896 case RISCV::SD:
22897 case RISCV::SD_RV32:
22898 case RISCV::SH:
22899 case RISCV::SH_INX:
22900 case RISCV::SW:
22901 case RISCV::SW_INX: {
22902 switch (OpNum) {
22903 case 2:
22904 // op: imm12
22905 return 7;
22906 case 0:
22907 // op: rs2
22908 return 20;
22909 case 1:
22910 // op: rs1
22911 return 15;
22912 }
22913 break;
22914 }
22915 case RISCV::BEQ:
22916 case RISCV::BGE:
22917 case RISCV::BGEU:
22918 case RISCV::BLT:
22919 case RISCV::BLTU:
22920 case RISCV::BNE:
22921 case RISCV::QC_BEQI:
22922 case RISCV::QC_BGEI:
22923 case RISCV::QC_BGEUI:
22924 case RISCV::QC_BLTI:
22925 case RISCV::QC_BLTUI:
22926 case RISCV::QC_BNEI: {
22927 switch (OpNum) {
22928 case 2:
22929 // op: imm12
22930 return 7;
22931 case 1:
22932 // op: rs2
22933 return 20;
22934 case 0:
22935 // op: rs1
22936 return 15;
22937 }
22938 break;
22939 }
22940 case RISCV::CSRRC:
22941 case RISCV::CSRRCI:
22942 case RISCV::CSRRS:
22943 case RISCV::CSRRSI:
22944 case RISCV::CSRRW:
22945 case RISCV::CSRRWI: {
22946 switch (OpNum) {
22947 case 2:
22948 // op: rs1
22949 return 15;
22950 case 0:
22951 // op: rd
22952 return 7;
22953 case 1:
22954 // op: imm12
22955 return 20;
22956 }
22957 break;
22958 }
22959 case RISCV::CV_LBU_ri_inc:
22960 case RISCV::CV_LB_ri_inc:
22961 case RISCV::CV_LHU_ri_inc:
22962 case RISCV::CV_LH_ri_inc:
22963 case RISCV::CV_LW_ri_inc: {
22964 switch (OpNum) {
22965 case 2:
22966 // op: rs1
22967 return 15;
22968 case 0:
22969 // op: rd
22970 return 7;
22971 case 3:
22972 // op: imm12
22973 return 20;
22974 }
22975 break;
22976 }
22977 case RISCV::TH_LBIA:
22978 case RISCV::TH_LBIB:
22979 case RISCV::TH_LBUIA:
22980 case RISCV::TH_LBUIB:
22981 case RISCV::TH_LDIA:
22982 case RISCV::TH_LDIB:
22983 case RISCV::TH_LHIA:
22984 case RISCV::TH_LHIB:
22985 case RISCV::TH_LHUIA:
22986 case RISCV::TH_LHUIB:
22987 case RISCV::TH_LWIA:
22988 case RISCV::TH_LWIB:
22989 case RISCV::TH_LWUIA:
22990 case RISCV::TH_LWUIB: {
22991 switch (OpNum) {
22992 case 2:
22993 // op: rs1
22994 return 15;
22995 case 0:
22996 // op: rd
22997 return 7;
22998 case 3:
22999 // op: simm5
23000 return 20;
23001 case 4:
23002 // op: uimm2
23003 return 25;
23004 }
23005 break;
23006 }
23007 case RISCV::QC_MULIADD: {
23008 switch (OpNum) {
23009 case 2:
23010 // op: rs1
23011 return 15;
23012 case 1:
23013 // op: rd
23014 return 7;
23015 case 3:
23016 // op: imm12
23017 return 20;
23018 }
23019 break;
23020 }
23021 case RISCV::CV_INSERT_B:
23022 case RISCV::CV_INSERT_H:
23023 case RISCV::CV_SDOTSP_SCI_B:
23024 case RISCV::CV_SDOTSP_SCI_H:
23025 case RISCV::CV_SDOTUP_SCI_B:
23026 case RISCV::CV_SDOTUP_SCI_H:
23027 case RISCV::CV_SDOTUSP_SCI_B:
23028 case RISCV::CV_SDOTUSP_SCI_H: {
23029 switch (OpNum) {
23030 case 2:
23031 // op: rs1
23032 return 15;
23033 case 1:
23034 // op: rd
23035 return 7;
23036 case 3:
23037 // op: imm6
23038 return 20;
23039 }
23040 break;
23041 }
23042 case RISCV::CV_INSERT: {
23043 switch (OpNum) {
23044 case 2:
23045 // op: rs1
23046 return 15;
23047 case 1:
23048 // op: rd
23049 return 7;
23050 case 3:
23051 // op: is3
23052 return 25;
23053 case 4:
23054 // op: is2
23055 return 20;
23056 }
23057 break;
23058 }
23059 case RISCV::QC_SELECTIIEQ:
23060 case RISCV::QC_SELECTIINE: {
23061 switch (OpNum) {
23062 case 2:
23063 // op: rs1
23064 return 15;
23065 case 1:
23066 // op: rd
23067 return 7;
23068 case 3:
23069 // op: simm1
23070 return 20;
23071 case 4:
23072 // op: simm2
23073 return 27;
23074 }
23075 break;
23076 }
23077 case RISCV::TH_SBIA:
23078 case RISCV::TH_SBIB:
23079 case RISCV::TH_SDIA:
23080 case RISCV::TH_SDIB:
23081 case RISCV::TH_SHIA:
23082 case RISCV::TH_SHIB:
23083 case RISCV::TH_SWIA:
23084 case RISCV::TH_SWIB: {
23085 switch (OpNum) {
23086 case 2:
23087 // op: rs1
23088 return 15;
23089 case 1:
23090 // op: rd
23091 return 7;
23092 case 3:
23093 // op: simm5
23094 return 20;
23095 case 4:
23096 // op: uimm2
23097 return 25;
23098 }
23099 break;
23100 }
23101 case RISCV::VFMV_S_F:
23102 case RISCV::VMV_S_X: {
23103 switch (OpNum) {
23104 case 2:
23105 // op: rs1
23106 return 15;
23107 case 1:
23108 // op: vd
23109 return 7;
23110 }
23111 break;
23112 }
23113 case RISCV::AES32DSI:
23114 case RISCV::AES32DSMI:
23115 case RISCV::AES32ESI:
23116 case RISCV::AES32ESMI:
23117 case RISCV::SM4ED:
23118 case RISCV::SM4KS: {
23119 switch (OpNum) {
23120 case 2:
23121 // op: rs2
23122 return 20;
23123 case 1:
23124 // op: rs1
23125 return 15;
23126 case 0:
23127 // op: rd
23128 return 7;
23129 case 3:
23130 // op: bs
23131 return 30;
23132 }
23133 break;
23134 }
23135 case RISCV::QC_LWM:
23136 case RISCV::QC_LWMI:
23137 case RISCV::QC_SETWM:
23138 case RISCV::QC_SETWMI:
23139 case RISCV::QC_SWM:
23140 case RISCV::QC_SWMI: {
23141 switch (OpNum) {
23142 case 2:
23143 // op: rs2
23144 return 20;
23145 case 1:
23146 // op: rs1
23147 return 15;
23148 case 0:
23149 // op: rd
23150 return 7;
23151 case 3:
23152 // op: imm
23153 return 25;
23154 }
23155 break;
23156 }
23157 case RISCV::CV_ADDN:
23158 case RISCV::CV_ADDRN:
23159 case RISCV::CV_ADDUN:
23160 case RISCV::CV_ADDURN:
23161 case RISCV::CV_MULHHSN:
23162 case RISCV::CV_MULHHSRN:
23163 case RISCV::CV_MULHHUN:
23164 case RISCV::CV_MULHHURN:
23165 case RISCV::CV_MULSN:
23166 case RISCV::CV_MULSRN:
23167 case RISCV::CV_MULUN:
23168 case RISCV::CV_MULURN:
23169 case RISCV::CV_SUBN:
23170 case RISCV::CV_SUBRN:
23171 case RISCV::CV_SUBUN:
23172 case RISCV::CV_SUBURN: {
23173 switch (OpNum) {
23174 case 2:
23175 // op: rs2
23176 return 20;
23177 case 1:
23178 // op: rs1
23179 return 15;
23180 case 0:
23181 // op: rd
23182 return 7;
23183 case 3:
23184 // op: imm5
23185 return 25;
23186 }
23187 break;
23188 }
23189 case RISCV::QC_LRB:
23190 case RISCV::QC_LRBU:
23191 case RISCV::QC_LRH:
23192 case RISCV::QC_LRHU:
23193 case RISCV::QC_LRW:
23194 case RISCV::QC_SHLADD:
23195 case RISCV::QC_SRB:
23196 case RISCV::QC_SRH:
23197 case RISCV::QC_SRW: {
23198 switch (OpNum) {
23199 case 2:
23200 // op: rs2
23201 return 20;
23202 case 1:
23203 // op: rs1
23204 return 15;
23205 case 0:
23206 // op: rd
23207 return 7;
23208 case 3:
23209 // op: shamt
23210 return 25;
23211 }
23212 break;
23213 }
23214 case RISCV::TH_ADDSL:
23215 case RISCV::TH_FLRD:
23216 case RISCV::TH_FLRW:
23217 case RISCV::TH_FLURD:
23218 case RISCV::TH_FLURW:
23219 case RISCV::TH_FSRD:
23220 case RISCV::TH_FSRW:
23221 case RISCV::TH_FSURD:
23222 case RISCV::TH_FSURW:
23223 case RISCV::TH_LRB:
23224 case RISCV::TH_LRBU:
23225 case RISCV::TH_LRD:
23226 case RISCV::TH_LRH:
23227 case RISCV::TH_LRHU:
23228 case RISCV::TH_LRW:
23229 case RISCV::TH_LRWU:
23230 case RISCV::TH_LURB:
23231 case RISCV::TH_LURBU:
23232 case RISCV::TH_LURD:
23233 case RISCV::TH_LURH:
23234 case RISCV::TH_LURHU:
23235 case RISCV::TH_LURW:
23236 case RISCV::TH_LURWU:
23237 case RISCV::TH_SRB:
23238 case RISCV::TH_SRD:
23239 case RISCV::TH_SRH:
23240 case RISCV::TH_SRW:
23241 case RISCV::TH_SURB:
23242 case RISCV::TH_SURD:
23243 case RISCV::TH_SURH:
23244 case RISCV::TH_SURW: {
23245 switch (OpNum) {
23246 case 2:
23247 // op: rs2
23248 return 20;
23249 case 1:
23250 // op: rs1
23251 return 15;
23252 case 0:
23253 // op: rd
23254 return 7;
23255 case 3:
23256 // op: uimm2
23257 return 25;
23258 }
23259 break;
23260 }
23261 case RISCV::ADD:
23262 case RISCV::ADDW:
23263 case RISCV::ADD_UW:
23264 case RISCV::AES64DS:
23265 case RISCV::AES64DSM:
23266 case RISCV::AES64ES:
23267 case RISCV::AES64ESM:
23268 case RISCV::AES64KS2:
23269 case RISCV::AMOADD_B:
23270 case RISCV::AMOADD_B_AQ:
23271 case RISCV::AMOADD_B_AQ_RL:
23272 case RISCV::AMOADD_B_RL:
23273 case RISCV::AMOADD_D:
23274 case RISCV::AMOADD_D_AQ:
23275 case RISCV::AMOADD_D_AQ_RL:
23276 case RISCV::AMOADD_D_RL:
23277 case RISCV::AMOADD_H:
23278 case RISCV::AMOADD_H_AQ:
23279 case RISCV::AMOADD_H_AQ_RL:
23280 case RISCV::AMOADD_H_RL:
23281 case RISCV::AMOADD_W:
23282 case RISCV::AMOADD_W_AQ:
23283 case RISCV::AMOADD_W_AQ_RL:
23284 case RISCV::AMOADD_W_RL:
23285 case RISCV::AMOAND_B:
23286 case RISCV::AMOAND_B_AQ:
23287 case RISCV::AMOAND_B_AQ_RL:
23288 case RISCV::AMOAND_B_RL:
23289 case RISCV::AMOAND_D:
23290 case RISCV::AMOAND_D_AQ:
23291 case RISCV::AMOAND_D_AQ_RL:
23292 case RISCV::AMOAND_D_RL:
23293 case RISCV::AMOAND_H:
23294 case RISCV::AMOAND_H_AQ:
23295 case RISCV::AMOAND_H_AQ_RL:
23296 case RISCV::AMOAND_H_RL:
23297 case RISCV::AMOAND_W:
23298 case RISCV::AMOAND_W_AQ:
23299 case RISCV::AMOAND_W_AQ_RL:
23300 case RISCV::AMOAND_W_RL:
23301 case RISCV::AMOMAXU_B:
23302 case RISCV::AMOMAXU_B_AQ:
23303 case RISCV::AMOMAXU_B_AQ_RL:
23304 case RISCV::AMOMAXU_B_RL:
23305 case RISCV::AMOMAXU_D:
23306 case RISCV::AMOMAXU_D_AQ:
23307 case RISCV::AMOMAXU_D_AQ_RL:
23308 case RISCV::AMOMAXU_D_RL:
23309 case RISCV::AMOMAXU_H:
23310 case RISCV::AMOMAXU_H_AQ:
23311 case RISCV::AMOMAXU_H_AQ_RL:
23312 case RISCV::AMOMAXU_H_RL:
23313 case RISCV::AMOMAXU_W:
23314 case RISCV::AMOMAXU_W_AQ:
23315 case RISCV::AMOMAXU_W_AQ_RL:
23316 case RISCV::AMOMAXU_W_RL:
23317 case RISCV::AMOMAX_B:
23318 case RISCV::AMOMAX_B_AQ:
23319 case RISCV::AMOMAX_B_AQ_RL:
23320 case RISCV::AMOMAX_B_RL:
23321 case RISCV::AMOMAX_D:
23322 case RISCV::AMOMAX_D_AQ:
23323 case RISCV::AMOMAX_D_AQ_RL:
23324 case RISCV::AMOMAX_D_RL:
23325 case RISCV::AMOMAX_H:
23326 case RISCV::AMOMAX_H_AQ:
23327 case RISCV::AMOMAX_H_AQ_RL:
23328 case RISCV::AMOMAX_H_RL:
23329 case RISCV::AMOMAX_W:
23330 case RISCV::AMOMAX_W_AQ:
23331 case RISCV::AMOMAX_W_AQ_RL:
23332 case RISCV::AMOMAX_W_RL:
23333 case RISCV::AMOMINU_B:
23334 case RISCV::AMOMINU_B_AQ:
23335 case RISCV::AMOMINU_B_AQ_RL:
23336 case RISCV::AMOMINU_B_RL:
23337 case RISCV::AMOMINU_D:
23338 case RISCV::AMOMINU_D_AQ:
23339 case RISCV::AMOMINU_D_AQ_RL:
23340 case RISCV::AMOMINU_D_RL:
23341 case RISCV::AMOMINU_H:
23342 case RISCV::AMOMINU_H_AQ:
23343 case RISCV::AMOMINU_H_AQ_RL:
23344 case RISCV::AMOMINU_H_RL:
23345 case RISCV::AMOMINU_W:
23346 case RISCV::AMOMINU_W_AQ:
23347 case RISCV::AMOMINU_W_AQ_RL:
23348 case RISCV::AMOMINU_W_RL:
23349 case RISCV::AMOMIN_B:
23350 case RISCV::AMOMIN_B_AQ:
23351 case RISCV::AMOMIN_B_AQ_RL:
23352 case RISCV::AMOMIN_B_RL:
23353 case RISCV::AMOMIN_D:
23354 case RISCV::AMOMIN_D_AQ:
23355 case RISCV::AMOMIN_D_AQ_RL:
23356 case RISCV::AMOMIN_D_RL:
23357 case RISCV::AMOMIN_H:
23358 case RISCV::AMOMIN_H_AQ:
23359 case RISCV::AMOMIN_H_AQ_RL:
23360 case RISCV::AMOMIN_H_RL:
23361 case RISCV::AMOMIN_W:
23362 case RISCV::AMOMIN_W_AQ:
23363 case RISCV::AMOMIN_W_AQ_RL:
23364 case RISCV::AMOMIN_W_RL:
23365 case RISCV::AMOOR_B:
23366 case RISCV::AMOOR_B_AQ:
23367 case RISCV::AMOOR_B_AQ_RL:
23368 case RISCV::AMOOR_B_RL:
23369 case RISCV::AMOOR_D:
23370 case RISCV::AMOOR_D_AQ:
23371 case RISCV::AMOOR_D_AQ_RL:
23372 case RISCV::AMOOR_D_RL:
23373 case RISCV::AMOOR_H:
23374 case RISCV::AMOOR_H_AQ:
23375 case RISCV::AMOOR_H_AQ_RL:
23376 case RISCV::AMOOR_H_RL:
23377 case RISCV::AMOOR_W:
23378 case RISCV::AMOOR_W_AQ:
23379 case RISCV::AMOOR_W_AQ_RL:
23380 case RISCV::AMOOR_W_RL:
23381 case RISCV::AMOSWAP_B:
23382 case RISCV::AMOSWAP_B_AQ:
23383 case RISCV::AMOSWAP_B_AQ_RL:
23384 case RISCV::AMOSWAP_B_RL:
23385 case RISCV::AMOSWAP_D:
23386 case RISCV::AMOSWAP_D_AQ:
23387 case RISCV::AMOSWAP_D_AQ_RL:
23388 case RISCV::AMOSWAP_D_RL:
23389 case RISCV::AMOSWAP_H:
23390 case RISCV::AMOSWAP_H_AQ:
23391 case RISCV::AMOSWAP_H_AQ_RL:
23392 case RISCV::AMOSWAP_H_RL:
23393 case RISCV::AMOSWAP_W:
23394 case RISCV::AMOSWAP_W_AQ:
23395 case RISCV::AMOSWAP_W_AQ_RL:
23396 case RISCV::AMOSWAP_W_RL:
23397 case RISCV::AMOXOR_B:
23398 case RISCV::AMOXOR_B_AQ:
23399 case RISCV::AMOXOR_B_AQ_RL:
23400 case RISCV::AMOXOR_B_RL:
23401 case RISCV::AMOXOR_D:
23402 case RISCV::AMOXOR_D_AQ:
23403 case RISCV::AMOXOR_D_AQ_RL:
23404 case RISCV::AMOXOR_D_RL:
23405 case RISCV::AMOXOR_H:
23406 case RISCV::AMOXOR_H_AQ:
23407 case RISCV::AMOXOR_H_AQ_RL:
23408 case RISCV::AMOXOR_H_RL:
23409 case RISCV::AMOXOR_W:
23410 case RISCV::AMOXOR_W_AQ:
23411 case RISCV::AMOXOR_W_AQ_RL:
23412 case RISCV::AMOXOR_W_RL:
23413 case RISCV::AND:
23414 case RISCV::ANDN:
23415 case RISCV::BCLR:
23416 case RISCV::BEXT:
23417 case RISCV::BINV:
23418 case RISCV::BSET:
23419 case RISCV::CLMUL:
23420 case RISCV::CLMULH:
23421 case RISCV::CLMULR:
23422 case RISCV::CV_ADD_B:
23423 case RISCV::CV_ADD_DIV2:
23424 case RISCV::CV_ADD_DIV4:
23425 case RISCV::CV_ADD_DIV8:
23426 case RISCV::CV_ADD_H:
23427 case RISCV::CV_ADD_SC_B:
23428 case RISCV::CV_ADD_SC_H:
23429 case RISCV::CV_AND_B:
23430 case RISCV::CV_AND_H:
23431 case RISCV::CV_AND_SC_B:
23432 case RISCV::CV_AND_SC_H:
23433 case RISCV::CV_AVGU_B:
23434 case RISCV::CV_AVGU_H:
23435 case RISCV::CV_AVGU_SC_B:
23436 case RISCV::CV_AVGU_SC_H:
23437 case RISCV::CV_AVG_B:
23438 case RISCV::CV_AVG_H:
23439 case RISCV::CV_AVG_SC_B:
23440 case RISCV::CV_AVG_SC_H:
23441 case RISCV::CV_BCLRR:
23442 case RISCV::CV_BSETR:
23443 case RISCV::CV_CLIPR:
23444 case RISCV::CV_CLIPUR:
23445 case RISCV::CV_CMPEQ_B:
23446 case RISCV::CV_CMPEQ_H:
23447 case RISCV::CV_CMPEQ_SC_B:
23448 case RISCV::CV_CMPEQ_SC_H:
23449 case RISCV::CV_CMPGEU_B:
23450 case RISCV::CV_CMPGEU_H:
23451 case RISCV::CV_CMPGEU_SC_B:
23452 case RISCV::CV_CMPGEU_SC_H:
23453 case RISCV::CV_CMPGE_B:
23454 case RISCV::CV_CMPGE_H:
23455 case RISCV::CV_CMPGE_SC_B:
23456 case RISCV::CV_CMPGE_SC_H:
23457 case RISCV::CV_CMPGTU_B:
23458 case RISCV::CV_CMPGTU_H:
23459 case RISCV::CV_CMPGTU_SC_B:
23460 case RISCV::CV_CMPGTU_SC_H:
23461 case RISCV::CV_CMPGT_B:
23462 case RISCV::CV_CMPGT_H:
23463 case RISCV::CV_CMPGT_SC_B:
23464 case RISCV::CV_CMPGT_SC_H:
23465 case RISCV::CV_CMPLEU_B:
23466 case RISCV::CV_CMPLEU_H:
23467 case RISCV::CV_CMPLEU_SC_B:
23468 case RISCV::CV_CMPLEU_SC_H:
23469 case RISCV::CV_CMPLE_B:
23470 case RISCV::CV_CMPLE_H:
23471 case RISCV::CV_CMPLE_SC_B:
23472 case RISCV::CV_CMPLE_SC_H:
23473 case RISCV::CV_CMPLTU_B:
23474 case RISCV::CV_CMPLTU_H:
23475 case RISCV::CV_CMPLTU_SC_B:
23476 case RISCV::CV_CMPLTU_SC_H:
23477 case RISCV::CV_CMPLT_B:
23478 case RISCV::CV_CMPLT_H:
23479 case RISCV::CV_CMPLT_SC_B:
23480 case RISCV::CV_CMPLT_SC_H:
23481 case RISCV::CV_CMPNE_B:
23482 case RISCV::CV_CMPNE_H:
23483 case RISCV::CV_CMPNE_SC_B:
23484 case RISCV::CV_CMPNE_SC_H:
23485 case RISCV::CV_DOTSP_B:
23486 case RISCV::CV_DOTSP_H:
23487 case RISCV::CV_DOTSP_SC_B:
23488 case RISCV::CV_DOTSP_SC_H:
23489 case RISCV::CV_DOTUP_B:
23490 case RISCV::CV_DOTUP_H:
23491 case RISCV::CV_DOTUP_SC_B:
23492 case RISCV::CV_DOTUP_SC_H:
23493 case RISCV::CV_DOTUSP_B:
23494 case RISCV::CV_DOTUSP_H:
23495 case RISCV::CV_DOTUSP_SC_B:
23496 case RISCV::CV_DOTUSP_SC_H:
23497 case RISCV::CV_EXTRACTR:
23498 case RISCV::CV_EXTRACTUR:
23499 case RISCV::CV_LBU_rr:
23500 case RISCV::CV_LB_rr:
23501 case RISCV::CV_LHU_rr:
23502 case RISCV::CV_LH_rr:
23503 case RISCV::CV_LW_rr:
23504 case RISCV::CV_MAX:
23505 case RISCV::CV_MAXU:
23506 case RISCV::CV_MAXU_B:
23507 case RISCV::CV_MAXU_H:
23508 case RISCV::CV_MAXU_SC_B:
23509 case RISCV::CV_MAXU_SC_H:
23510 case RISCV::CV_MAX_B:
23511 case RISCV::CV_MAX_H:
23512 case RISCV::CV_MAX_SC_B:
23513 case RISCV::CV_MAX_SC_H:
23514 case RISCV::CV_MIN:
23515 case RISCV::CV_MINU:
23516 case RISCV::CV_MINU_B:
23517 case RISCV::CV_MINU_H:
23518 case RISCV::CV_MINU_SC_B:
23519 case RISCV::CV_MINU_SC_H:
23520 case RISCV::CV_MIN_B:
23521 case RISCV::CV_MIN_H:
23522 case RISCV::CV_MIN_SC_B:
23523 case RISCV::CV_MIN_SC_H:
23524 case RISCV::CV_OR_B:
23525 case RISCV::CV_OR_H:
23526 case RISCV::CV_OR_SC_B:
23527 case RISCV::CV_OR_SC_H:
23528 case RISCV::CV_PACK:
23529 case RISCV::CV_PACK_H:
23530 case RISCV::CV_ROR:
23531 case RISCV::CV_SHUFFLE_B:
23532 case RISCV::CV_SHUFFLE_H:
23533 case RISCV::CV_SLE:
23534 case RISCV::CV_SLEU:
23535 case RISCV::CV_SLL_B:
23536 case RISCV::CV_SLL_H:
23537 case RISCV::CV_SLL_SC_B:
23538 case RISCV::CV_SLL_SC_H:
23539 case RISCV::CV_SRA_B:
23540 case RISCV::CV_SRA_H:
23541 case RISCV::CV_SRA_SC_B:
23542 case RISCV::CV_SRA_SC_H:
23543 case RISCV::CV_SRL_B:
23544 case RISCV::CV_SRL_H:
23545 case RISCV::CV_SRL_SC_B:
23546 case RISCV::CV_SRL_SC_H:
23547 case RISCV::CV_SUBROTMJ:
23548 case RISCV::CV_SUBROTMJ_DIV2:
23549 case RISCV::CV_SUBROTMJ_DIV4:
23550 case RISCV::CV_SUBROTMJ_DIV8:
23551 case RISCV::CV_SUB_B:
23552 case RISCV::CV_SUB_DIV2:
23553 case RISCV::CV_SUB_DIV4:
23554 case RISCV::CV_SUB_DIV8:
23555 case RISCV::CV_SUB_H:
23556 case RISCV::CV_SUB_SC_B:
23557 case RISCV::CV_SUB_SC_H:
23558 case RISCV::CV_XOR_B:
23559 case RISCV::CV_XOR_H:
23560 case RISCV::CV_XOR_SC_B:
23561 case RISCV::CV_XOR_SC_H:
23562 case RISCV::CZERO_EQZ:
23563 case RISCV::CZERO_NEZ:
23564 case RISCV::DIV:
23565 case RISCV::DIVU:
23566 case RISCV::DIVUW:
23567 case RISCV::DIVW:
23568 case RISCV::FEQ_D:
23569 case RISCV::FEQ_D_IN32X:
23570 case RISCV::FEQ_D_INX:
23571 case RISCV::FEQ_H:
23572 case RISCV::FEQ_H_INX:
23573 case RISCV::FEQ_Q:
23574 case RISCV::FEQ_S:
23575 case RISCV::FEQ_S_INX:
23576 case RISCV::FLEQ_D:
23577 case RISCV::FLEQ_H:
23578 case RISCV::FLEQ_Q:
23579 case RISCV::FLEQ_S:
23580 case RISCV::FLE_D:
23581 case RISCV::FLE_D_IN32X:
23582 case RISCV::FLE_D_INX:
23583 case RISCV::FLE_H:
23584 case RISCV::FLE_H_INX:
23585 case RISCV::FLE_Q:
23586 case RISCV::FLE_S:
23587 case RISCV::FLE_S_INX:
23588 case RISCV::FLTQ_D:
23589 case RISCV::FLTQ_H:
23590 case RISCV::FLTQ_Q:
23591 case RISCV::FLTQ_S:
23592 case RISCV::FLT_D:
23593 case RISCV::FLT_D_IN32X:
23594 case RISCV::FLT_D_INX:
23595 case RISCV::FLT_H:
23596 case RISCV::FLT_H_INX:
23597 case RISCV::FLT_Q:
23598 case RISCV::FLT_S:
23599 case RISCV::FLT_S_INX:
23600 case RISCV::FMAXM_D:
23601 case RISCV::FMAXM_H:
23602 case RISCV::FMAXM_Q:
23603 case RISCV::FMAXM_S:
23604 case RISCV::FMAX_D:
23605 case RISCV::FMAX_D_IN32X:
23606 case RISCV::FMAX_D_INX:
23607 case RISCV::FMAX_H:
23608 case RISCV::FMAX_H_INX:
23609 case RISCV::FMAX_Q:
23610 case RISCV::FMAX_S:
23611 case RISCV::FMAX_S_INX:
23612 case RISCV::FMINM_D:
23613 case RISCV::FMINM_H:
23614 case RISCV::FMINM_Q:
23615 case RISCV::FMINM_S:
23616 case RISCV::FMIN_D:
23617 case RISCV::FMIN_D_IN32X:
23618 case RISCV::FMIN_D_INX:
23619 case RISCV::FMIN_H:
23620 case RISCV::FMIN_H_INX:
23621 case RISCV::FMIN_Q:
23622 case RISCV::FMIN_S:
23623 case RISCV::FMIN_S_INX:
23624 case RISCV::FMVP_D_X:
23625 case RISCV::FMVP_Q_X:
23626 case RISCV::FSGNJN_D:
23627 case RISCV::FSGNJN_D_IN32X:
23628 case RISCV::FSGNJN_D_INX:
23629 case RISCV::FSGNJN_H:
23630 case RISCV::FSGNJN_H_INX:
23631 case RISCV::FSGNJN_Q:
23632 case RISCV::FSGNJN_S:
23633 case RISCV::FSGNJN_S_INX:
23634 case RISCV::FSGNJX_D:
23635 case RISCV::FSGNJX_D_IN32X:
23636 case RISCV::FSGNJX_D_INX:
23637 case RISCV::FSGNJX_H:
23638 case RISCV::FSGNJX_H_INX:
23639 case RISCV::FSGNJX_Q:
23640 case RISCV::FSGNJX_S:
23641 case RISCV::FSGNJX_S_INX:
23642 case RISCV::FSGNJ_D:
23643 case RISCV::FSGNJ_D_IN32X:
23644 case RISCV::FSGNJ_D_INX:
23645 case RISCV::FSGNJ_H:
23646 case RISCV::FSGNJ_H_INX:
23647 case RISCV::FSGNJ_Q:
23648 case RISCV::FSGNJ_S:
23649 case RISCV::FSGNJ_S_INX:
23650 case RISCV::MAX:
23651 case RISCV::MAXU:
23652 case RISCV::MIN:
23653 case RISCV::MINU:
23654 case RISCV::MOPRR0:
23655 case RISCV::MOPRR1:
23656 case RISCV::MOPRR2:
23657 case RISCV::MOPRR3:
23658 case RISCV::MOPRR4:
23659 case RISCV::MOPRR5:
23660 case RISCV::MOPRR6:
23661 case RISCV::MOPRR7:
23662 case RISCV::MUL:
23663 case RISCV::MULH:
23664 case RISCV::MULHSU:
23665 case RISCV::MULHU:
23666 case RISCV::MULW:
23667 case RISCV::NDS_FFB:
23668 case RISCV::NDS_FFMISM:
23669 case RISCV::NDS_FFZMISM:
23670 case RISCV::NDS_FLMISM:
23671 case RISCV::OR:
23672 case RISCV::ORN:
23673 case RISCV::PACK:
23674 case RISCV::PACKH:
23675 case RISCV::PACKW:
23676 case RISCV::QC_ADDSAT:
23677 case RISCV::QC_ADDUSAT:
23678 case RISCV::QC_CSRRWR:
23679 case RISCV::QC_CSRRWRI:
23680 case RISCV::QC_EXTDPR:
23681 case RISCV::QC_EXTDPRH:
23682 case RISCV::QC_EXTDR:
23683 case RISCV::QC_EXTDUPR:
23684 case RISCV::QC_EXTDUPRH:
23685 case RISCV::QC_EXTDUR:
23686 case RISCV::QC_INSBHR:
23687 case RISCV::QC_INSBPR:
23688 case RISCV::QC_INSBPRH:
23689 case RISCV::QC_INSBR:
23690 case RISCV::QC_SHLSAT:
23691 case RISCV::QC_SHLUSAT:
23692 case RISCV::QC_SUBSAT:
23693 case RISCV::QC_SUBUSAT:
23694 case RISCV::QC_WRAP:
23695 case RISCV::REM:
23696 case RISCV::REMU:
23697 case RISCV::REMUW:
23698 case RISCV::REMW:
23699 case RISCV::ROL:
23700 case RISCV::ROLW:
23701 case RISCV::ROR:
23702 case RISCV::RORW:
23703 case RISCV::SC_D:
23704 case RISCV::SC_D_AQ:
23705 case RISCV::SC_D_AQ_RL:
23706 case RISCV::SC_D_RL:
23707 case RISCV::SC_W:
23708 case RISCV::SC_W_AQ:
23709 case RISCV::SC_W_AQ_RL:
23710 case RISCV::SC_W_RL:
23711 case RISCV::SF_VFWMACC_4x4x4:
23712 case RISCV::SF_VQMACCSU_2x8x2:
23713 case RISCV::SF_VQMACCSU_4x8x4:
23714 case RISCV::SF_VQMACCUS_2x8x2:
23715 case RISCV::SF_VQMACCUS_4x8x4:
23716 case RISCV::SF_VQMACCU_2x8x2:
23717 case RISCV::SF_VQMACCU_4x8x4:
23718 case RISCV::SF_VQMACC_2x8x2:
23719 case RISCV::SF_VQMACC_4x8x4:
23720 case RISCV::SH1ADD:
23721 case RISCV::SH1ADD_UW:
23722 case RISCV::SH2ADD:
23723 case RISCV::SH2ADD_UW:
23724 case RISCV::SH3ADD:
23725 case RISCV::SH3ADD_UW:
23726 case RISCV::SHA512SIG0H:
23727 case RISCV::SHA512SIG0L:
23728 case RISCV::SHA512SIG1H:
23729 case RISCV::SHA512SIG1L:
23730 case RISCV::SHA512SUM0R:
23731 case RISCV::SHA512SUM1R:
23732 case RISCV::SLL:
23733 case RISCV::SLLW:
23734 case RISCV::SLT:
23735 case RISCV::SLTU:
23736 case RISCV::SRA:
23737 case RISCV::SRAW:
23738 case RISCV::SRL:
23739 case RISCV::SRLW:
23740 case RISCV::SSAMOSWAP_D:
23741 case RISCV::SSAMOSWAP_D_AQ:
23742 case RISCV::SSAMOSWAP_D_AQ_RL:
23743 case RISCV::SSAMOSWAP_D_RL:
23744 case RISCV::SSAMOSWAP_W:
23745 case RISCV::SSAMOSWAP_W_AQ:
23746 case RISCV::SSAMOSWAP_W_AQ_RL:
23747 case RISCV::SSAMOSWAP_W_RL:
23748 case RISCV::SUB:
23749 case RISCV::SUBW:
23750 case RISCV::VSETVL:
23751 case RISCV::VT_MASKC:
23752 case RISCV::VT_MASKCN:
23753 case RISCV::XNOR:
23754 case RISCV::XOR:
23755 case RISCV::XPERM4:
23756 case RISCV::XPERM8: {
23757 switch (OpNum) {
23758 case 2:
23759 // op: rs2
23760 return 20;
23761 case 1:
23762 // op: rs1
23763 return 15;
23764 case 0:
23765 // op: rd
23766 return 7;
23767 }
23768 break;
23769 }
23770 case RISCV::VLSE8_V:
23771 case RISCV::VLSE16_V:
23772 case RISCV::VLSE32_V:
23773 case RISCV::VLSE64_V:
23774 case RISCV::VLSSEG2E8_V:
23775 case RISCV::VLSSEG2E16_V:
23776 case RISCV::VLSSEG2E32_V:
23777 case RISCV::VLSSEG2E64_V:
23778 case RISCV::VLSSEG3E8_V:
23779 case RISCV::VLSSEG3E16_V:
23780 case RISCV::VLSSEG3E32_V:
23781 case RISCV::VLSSEG3E64_V:
23782 case RISCV::VLSSEG4E8_V:
23783 case RISCV::VLSSEG4E16_V:
23784 case RISCV::VLSSEG4E32_V:
23785 case RISCV::VLSSEG4E64_V:
23786 case RISCV::VLSSEG5E8_V:
23787 case RISCV::VLSSEG5E16_V:
23788 case RISCV::VLSSEG5E32_V:
23789 case RISCV::VLSSEG5E64_V:
23790 case RISCV::VLSSEG6E8_V:
23791 case RISCV::VLSSEG6E16_V:
23792 case RISCV::VLSSEG6E32_V:
23793 case RISCV::VLSSEG6E64_V:
23794 case RISCV::VLSSEG7E8_V:
23795 case RISCV::VLSSEG7E16_V:
23796 case RISCV::VLSSEG7E32_V:
23797 case RISCV::VLSSEG7E64_V:
23798 case RISCV::VLSSEG8E8_V:
23799 case RISCV::VLSSEG8E16_V:
23800 case RISCV::VLSSEG8E32_V:
23801 case RISCV::VLSSEG8E64_V: {
23802 switch (OpNum) {
23803 case 2:
23804 // op: rs2
23805 return 20;
23806 case 1:
23807 // op: rs1
23808 return 15;
23809 case 0:
23810 // op: vd
23811 return 7;
23812 case 3:
23813 // op: vm
23814 return 25;
23815 }
23816 break;
23817 }
23818 case RISCV::VSSE8_V:
23819 case RISCV::VSSE16_V:
23820 case RISCV::VSSE32_V:
23821 case RISCV::VSSE64_V:
23822 case RISCV::VSSSEG2E8_V:
23823 case RISCV::VSSSEG2E16_V:
23824 case RISCV::VSSSEG2E32_V:
23825 case RISCV::VSSSEG2E64_V:
23826 case RISCV::VSSSEG3E8_V:
23827 case RISCV::VSSSEG3E16_V:
23828 case RISCV::VSSSEG3E32_V:
23829 case RISCV::VSSSEG3E64_V:
23830 case RISCV::VSSSEG4E8_V:
23831 case RISCV::VSSSEG4E16_V:
23832 case RISCV::VSSSEG4E32_V:
23833 case RISCV::VSSSEG4E64_V:
23834 case RISCV::VSSSEG5E8_V:
23835 case RISCV::VSSSEG5E16_V:
23836 case RISCV::VSSSEG5E32_V:
23837 case RISCV::VSSSEG5E64_V:
23838 case RISCV::VSSSEG6E8_V:
23839 case RISCV::VSSSEG6E16_V:
23840 case RISCV::VSSSEG6E32_V:
23841 case RISCV::VSSSEG6E64_V:
23842 case RISCV::VSSSEG7E8_V:
23843 case RISCV::VSSSEG7E16_V:
23844 case RISCV::VSSSEG7E32_V:
23845 case RISCV::VSSSEG7E64_V:
23846 case RISCV::VSSSEG8E8_V:
23847 case RISCV::VSSSEG8E16_V:
23848 case RISCV::VSSSEG8E32_V:
23849 case RISCV::VSSSEG8E64_V: {
23850 switch (OpNum) {
23851 case 2:
23852 // op: rs2
23853 return 20;
23854 case 1:
23855 // op: rs1
23856 return 15;
23857 case 0:
23858 // op: vs3
23859 return 7;
23860 case 3:
23861 // op: vm
23862 return 25;
23863 }
23864 break;
23865 }
23866 case RISCV::FADD_D:
23867 case RISCV::FADD_D_IN32X:
23868 case RISCV::FADD_D_INX:
23869 case RISCV::FADD_H:
23870 case RISCV::FADD_H_INX:
23871 case RISCV::FADD_Q:
23872 case RISCV::FADD_S:
23873 case RISCV::FADD_S_INX:
23874 case RISCV::FDIV_D:
23875 case RISCV::FDIV_D_IN32X:
23876 case RISCV::FDIV_D_INX:
23877 case RISCV::FDIV_H:
23878 case RISCV::FDIV_H_INX:
23879 case RISCV::FDIV_Q:
23880 case RISCV::FDIV_S:
23881 case RISCV::FDIV_S_INX:
23882 case RISCV::FMUL_D:
23883 case RISCV::FMUL_D_IN32X:
23884 case RISCV::FMUL_D_INX:
23885 case RISCV::FMUL_H:
23886 case RISCV::FMUL_H_INX:
23887 case RISCV::FMUL_Q:
23888 case RISCV::FMUL_S:
23889 case RISCV::FMUL_S_INX:
23890 case RISCV::FSUB_D:
23891 case RISCV::FSUB_D_IN32X:
23892 case RISCV::FSUB_D_INX:
23893 case RISCV::FSUB_H:
23894 case RISCV::FSUB_H_INX:
23895 case RISCV::FSUB_Q:
23896 case RISCV::FSUB_S:
23897 case RISCV::FSUB_S_INX: {
23898 switch (OpNum) {
23899 case 2:
23900 // op: rs2
23901 return 20;
23902 case 1:
23903 // op: rs1
23904 return 15;
23905 case 3:
23906 // op: frm
23907 return 12;
23908 case 0:
23909 // op: rd
23910 return 7;
23911 }
23912 break;
23913 }
23914 case RISCV::SF_VC_V_FV: {
23915 switch (OpNum) {
23916 case 2:
23917 // op: rs2
23918 return 20;
23919 case 3:
23920 // op: rs1
23921 return 15;
23922 case 0:
23923 // op: rd
23924 return 7;
23925 case 1:
23926 // op: funct6_lo1
23927 return 26;
23928 }
23929 break;
23930 }
23931 case RISCV::SF_VC_V_I:
23932 case RISCV::SF_VC_V_IV:
23933 case RISCV::SF_VC_V_VV:
23934 case RISCV::SF_VC_V_X:
23935 case RISCV::SF_VC_V_XV: {
23936 switch (OpNum) {
23937 case 2:
23938 // op: rs2
23939 return 20;
23940 case 3:
23941 // op: rs1
23942 return 15;
23943 case 0:
23944 // op: rd
23945 return 7;
23946 case 1:
23947 // op: funct6_lo2
23948 return 26;
23949 }
23950 break;
23951 }
23952 case RISCV::SF_VC_FV:
23953 case RISCV::SF_VC_FVV:
23954 case RISCV::SF_VC_FVW: {
23955 switch (OpNum) {
23956 case 2:
23957 // op: rs2
23958 return 20;
23959 case 3:
23960 // op: rs1
23961 return 15;
23962 case 1:
23963 // op: rd
23964 return 7;
23965 case 0:
23966 // op: funct6_lo1
23967 return 26;
23968 }
23969 break;
23970 }
23971 case RISCV::SF_VC_IV:
23972 case RISCV::SF_VC_IVV:
23973 case RISCV::SF_VC_IVW:
23974 case RISCV::SF_VC_VV:
23975 case RISCV::SF_VC_VVV:
23976 case RISCV::SF_VC_VVW:
23977 case RISCV::SF_VC_XV:
23978 case RISCV::SF_VC_XVV:
23979 case RISCV::SF_VC_XVW: {
23980 switch (OpNum) {
23981 case 2:
23982 // op: rs2
23983 return 20;
23984 case 3:
23985 // op: rs1
23986 return 15;
23987 case 1:
23988 // op: rd
23989 return 7;
23990 case 0:
23991 // op: funct6_lo2
23992 return 26;
23993 }
23994 break;
23995 }
23996 case RISCV::C_ADDW:
23997 case RISCV::C_AND:
23998 case RISCV::C_MUL:
23999 case RISCV::C_OR:
24000 case RISCV::C_SUB:
24001 case RISCV::C_SUBW:
24002 case RISCV::C_XOR: {
24003 switch (OpNum) {
24004 case 2:
24005 // op: rs2
24006 return 2;
24007 case 1:
24008 // op: rd
24009 return 7;
24010 }
24011 break;
24012 }
24013 case RISCV::C_ADD_HINT: {
24014 switch (OpNum) {
24015 case 2:
24016 // op: rs2
24017 return 2;
24018 }
24019 break;
24020 }
24021 case RISCV::VLOXEI8_V:
24022 case RISCV::VLOXEI16_V:
24023 case RISCV::VLOXEI32_V:
24024 case RISCV::VLOXEI64_V:
24025 case RISCV::VLOXSEG2EI8_V:
24026 case RISCV::VLOXSEG2EI16_V:
24027 case RISCV::VLOXSEG2EI32_V:
24028 case RISCV::VLOXSEG2EI64_V:
24029 case RISCV::VLOXSEG3EI8_V:
24030 case RISCV::VLOXSEG3EI16_V:
24031 case RISCV::VLOXSEG3EI32_V:
24032 case RISCV::VLOXSEG3EI64_V:
24033 case RISCV::VLOXSEG4EI8_V:
24034 case RISCV::VLOXSEG4EI16_V:
24035 case RISCV::VLOXSEG4EI32_V:
24036 case RISCV::VLOXSEG4EI64_V:
24037 case RISCV::VLOXSEG5EI8_V:
24038 case RISCV::VLOXSEG5EI16_V:
24039 case RISCV::VLOXSEG5EI32_V:
24040 case RISCV::VLOXSEG5EI64_V:
24041 case RISCV::VLOXSEG6EI8_V:
24042 case RISCV::VLOXSEG6EI16_V:
24043 case RISCV::VLOXSEG6EI32_V:
24044 case RISCV::VLOXSEG6EI64_V:
24045 case RISCV::VLOXSEG7EI8_V:
24046 case RISCV::VLOXSEG7EI16_V:
24047 case RISCV::VLOXSEG7EI32_V:
24048 case RISCV::VLOXSEG7EI64_V:
24049 case RISCV::VLOXSEG8EI8_V:
24050 case RISCV::VLOXSEG8EI16_V:
24051 case RISCV::VLOXSEG8EI32_V:
24052 case RISCV::VLOXSEG8EI64_V:
24053 case RISCV::VLUXEI8_V:
24054 case RISCV::VLUXEI16_V:
24055 case RISCV::VLUXEI32_V:
24056 case RISCV::VLUXEI64_V:
24057 case RISCV::VLUXSEG2EI8_V:
24058 case RISCV::VLUXSEG2EI16_V:
24059 case RISCV::VLUXSEG2EI32_V:
24060 case RISCV::VLUXSEG2EI64_V:
24061 case RISCV::VLUXSEG3EI8_V:
24062 case RISCV::VLUXSEG3EI16_V:
24063 case RISCV::VLUXSEG3EI32_V:
24064 case RISCV::VLUXSEG3EI64_V:
24065 case RISCV::VLUXSEG4EI8_V:
24066 case RISCV::VLUXSEG4EI16_V:
24067 case RISCV::VLUXSEG4EI32_V:
24068 case RISCV::VLUXSEG4EI64_V:
24069 case RISCV::VLUXSEG5EI8_V:
24070 case RISCV::VLUXSEG5EI16_V:
24071 case RISCV::VLUXSEG5EI32_V:
24072 case RISCV::VLUXSEG5EI64_V:
24073 case RISCV::VLUXSEG6EI8_V:
24074 case RISCV::VLUXSEG6EI16_V:
24075 case RISCV::VLUXSEG6EI32_V:
24076 case RISCV::VLUXSEG6EI64_V:
24077 case RISCV::VLUXSEG7EI8_V:
24078 case RISCV::VLUXSEG7EI16_V:
24079 case RISCV::VLUXSEG7EI32_V:
24080 case RISCV::VLUXSEG7EI64_V:
24081 case RISCV::VLUXSEG8EI8_V:
24082 case RISCV::VLUXSEG8EI16_V:
24083 case RISCV::VLUXSEG8EI32_V:
24084 case RISCV::VLUXSEG8EI64_V: {
24085 switch (OpNum) {
24086 case 2:
24087 // op: vs2
24088 return 20;
24089 case 1:
24090 // op: rs1
24091 return 15;
24092 case 0:
24093 // op: vd
24094 return 7;
24095 case 3:
24096 // op: vm
24097 return 25;
24098 }
24099 break;
24100 }
24101 case RISCV::VSOXEI8_V:
24102 case RISCV::VSOXEI16_V:
24103 case RISCV::VSOXEI32_V:
24104 case RISCV::VSOXEI64_V:
24105 case RISCV::VSOXSEG2EI8_V:
24106 case RISCV::VSOXSEG2EI16_V:
24107 case RISCV::VSOXSEG2EI32_V:
24108 case RISCV::VSOXSEG2EI64_V:
24109 case RISCV::VSOXSEG3EI8_V:
24110 case RISCV::VSOXSEG3EI16_V:
24111 case RISCV::VSOXSEG3EI32_V:
24112 case RISCV::VSOXSEG3EI64_V:
24113 case RISCV::VSOXSEG4EI8_V:
24114 case RISCV::VSOXSEG4EI16_V:
24115 case RISCV::VSOXSEG4EI32_V:
24116 case RISCV::VSOXSEG4EI64_V:
24117 case RISCV::VSOXSEG5EI8_V:
24118 case RISCV::VSOXSEG5EI16_V:
24119 case RISCV::VSOXSEG5EI32_V:
24120 case RISCV::VSOXSEG5EI64_V:
24121 case RISCV::VSOXSEG6EI8_V:
24122 case RISCV::VSOXSEG6EI16_V:
24123 case RISCV::VSOXSEG6EI32_V:
24124 case RISCV::VSOXSEG6EI64_V:
24125 case RISCV::VSOXSEG7EI8_V:
24126 case RISCV::VSOXSEG7EI16_V:
24127 case RISCV::VSOXSEG7EI32_V:
24128 case RISCV::VSOXSEG7EI64_V:
24129 case RISCV::VSOXSEG8EI8_V:
24130 case RISCV::VSOXSEG8EI16_V:
24131 case RISCV::VSOXSEG8EI32_V:
24132 case RISCV::VSOXSEG8EI64_V:
24133 case RISCV::VSUXEI8_V:
24134 case RISCV::VSUXEI16_V:
24135 case RISCV::VSUXEI32_V:
24136 case RISCV::VSUXEI64_V:
24137 case RISCV::VSUXSEG2EI8_V:
24138 case RISCV::VSUXSEG2EI16_V:
24139 case RISCV::VSUXSEG2EI32_V:
24140 case RISCV::VSUXSEG2EI64_V:
24141 case RISCV::VSUXSEG3EI8_V:
24142 case RISCV::VSUXSEG3EI16_V:
24143 case RISCV::VSUXSEG3EI32_V:
24144 case RISCV::VSUXSEG3EI64_V:
24145 case RISCV::VSUXSEG4EI8_V:
24146 case RISCV::VSUXSEG4EI16_V:
24147 case RISCV::VSUXSEG4EI32_V:
24148 case RISCV::VSUXSEG4EI64_V:
24149 case RISCV::VSUXSEG5EI8_V:
24150 case RISCV::VSUXSEG5EI16_V:
24151 case RISCV::VSUXSEG5EI32_V:
24152 case RISCV::VSUXSEG5EI64_V:
24153 case RISCV::VSUXSEG6EI8_V:
24154 case RISCV::VSUXSEG6EI16_V:
24155 case RISCV::VSUXSEG6EI32_V:
24156 case RISCV::VSUXSEG6EI64_V:
24157 case RISCV::VSUXSEG7EI8_V:
24158 case RISCV::VSUXSEG7EI16_V:
24159 case RISCV::VSUXSEG7EI32_V:
24160 case RISCV::VSUXSEG7EI64_V:
24161 case RISCV::VSUXSEG8EI8_V:
24162 case RISCV::VSUXSEG8EI16_V:
24163 case RISCV::VSUXSEG8EI32_V:
24164 case RISCV::VSUXSEG8EI64_V: {
24165 switch (OpNum) {
24166 case 2:
24167 // op: vs2
24168 return 20;
24169 case 1:
24170 // op: rs1
24171 return 15;
24172 case 0:
24173 // op: vs3
24174 return 7;
24175 case 3:
24176 // op: vm
24177 return 25;
24178 }
24179 break;
24180 }
24181 case RISCV::VAESDF_VS:
24182 case RISCV::VAESDF_VV:
24183 case RISCV::VAESDM_VS:
24184 case RISCV::VAESDM_VV:
24185 case RISCV::VAESEF_VS:
24186 case RISCV::VAESEF_VV:
24187 case RISCV::VAESEM_VS:
24188 case RISCV::VAESEM_VV:
24189 case RISCV::VAESZ_VS:
24190 case RISCV::VGMUL_VS:
24191 case RISCV::VGMUL_VV:
24192 case RISCV::VSM4R_VS:
24193 case RISCV::VSM4R_VV: {
24194 switch (OpNum) {
24195 case 2:
24196 // op: vs2
24197 return 20;
24198 case 1:
24199 // op: vd
24200 return 7;
24201 }
24202 break;
24203 }
24204 case RISCV::NDS_VD4DOTSU_VV:
24205 case RISCV::NDS_VD4DOTS_VV:
24206 case RISCV::NDS_VD4DOTU_VV: {
24207 switch (OpNum) {
24208 case 2:
24209 // op: vs2
24210 return 20;
24211 case 1:
24212 // op: vs1
24213 return 15;
24214 case 0:
24215 // op: vd
24216 return 7;
24217 case 3:
24218 // op: vm
24219 return 25;
24220 }
24221 break;
24222 }
24223 case RISCV::VAESKF2_VI:
24224 case RISCV::VSM3C_VI: {
24225 switch (OpNum) {
24226 case 2:
24227 // op: vs2
24228 return 20;
24229 case 3:
24230 // op: imm
24231 return 15;
24232 case 1:
24233 // op: vd
24234 return 7;
24235 }
24236 break;
24237 }
24238 case RISCV::VGHSH_VS:
24239 case RISCV::VGHSH_VV:
24240 case RISCV::VSHA2CH_VV:
24241 case RISCV::VSHA2CL_VV:
24242 case RISCV::VSHA2MS_VV: {
24243 switch (OpNum) {
24244 case 2:
24245 // op: vs2
24246 return 20;
24247 case 3:
24248 // op: vs1
24249 return 15;
24250 case 1:
24251 // op: vd
24252 return 7;
24253 }
24254 break;
24255 }
24256 case RISCV::RI_VINSERT: {
24257 switch (OpNum) {
24258 case 3:
24259 // op: imm
24260 return 20;
24261 case 2:
24262 // op: rs1
24263 return 15;
24264 case 1:
24265 // op: vd
24266 return 7;
24267 }
24268 break;
24269 }
24270 case RISCV::CV_SB_ri_inc:
24271 case RISCV::CV_SH_ri_inc:
24272 case RISCV::CV_SW_ri_inc: {
24273 switch (OpNum) {
24274 case 3:
24275 // op: imm12
24276 return 7;
24277 case 1:
24278 // op: rs2
24279 return 20;
24280 case 2:
24281 // op: rs1
24282 return 15;
24283 }
24284 break;
24285 }
24286 case RISCV::MIPS_SDP: {
24287 switch (OpNum) {
24288 case 3:
24289 // op: imm7
24290 return 10;
24291 case 1:
24292 // op: rs3
24293 return 27;
24294 case 0:
24295 // op: rs2
24296 return 20;
24297 case 2:
24298 // op: rs1
24299 return 15;
24300 }
24301 break;
24302 }
24303 case RISCV::MIPS_LWP: {
24304 switch (OpNum) {
24305 case 3:
24306 // op: imm7
24307 return 22;
24308 case 2:
24309 // op: rs1
24310 return 15;
24311 case 0:
24312 // op: rd1
24313 return 7;
24314 case 1:
24315 // op: rd2
24316 return 27;
24317 }
24318 break;
24319 }
24320 case RISCV::MIPS_LDP: {
24321 switch (OpNum) {
24322 case 3:
24323 // op: imm7
24324 return 23;
24325 case 2:
24326 // op: rs1
24327 return 15;
24328 case 0:
24329 // op: rd1
24330 return 7;
24331 case 1:
24332 // op: rd2
24333 return 27;
24334 }
24335 break;
24336 }
24337 case RISCV::MIPS_SWP: {
24338 switch (OpNum) {
24339 case 3:
24340 // op: imm7
24341 return 9;
24342 case 1:
24343 // op: rs3
24344 return 27;
24345 case 0:
24346 // op: rs2
24347 return 20;
24348 case 2:
24349 // op: rs1
24350 return 15;
24351 }
24352 break;
24353 }
24354 case RISCV::QC_SELECTIEQI:
24355 case RISCV::QC_SELECTINEI: {
24356 switch (OpNum) {
24357 case 3:
24358 // op: rs2
24359 return 20;
24360 case 1:
24361 // op: rd
24362 return 7;
24363 case 2:
24364 // op: imm
24365 return 15;
24366 case 4:
24367 // op: simm2
24368 return 27;
24369 }
24370 break;
24371 }
24372 case RISCV::CV_LBU_rr_inc:
24373 case RISCV::CV_LB_rr_inc:
24374 case RISCV::CV_LHU_rr_inc:
24375 case RISCV::CV_LH_rr_inc:
24376 case RISCV::CV_LW_rr_inc: {
24377 switch (OpNum) {
24378 case 3:
24379 // op: rs2
24380 return 20;
24381 case 2:
24382 // op: rs1
24383 return 15;
24384 case 0:
24385 // op: rd
24386 return 7;
24387 }
24388 break;
24389 }
24390 case RISCV::CV_MACHHSN:
24391 case RISCV::CV_MACHHSRN:
24392 case RISCV::CV_MACHHUN:
24393 case RISCV::CV_MACHHURN:
24394 case RISCV::CV_MACSN:
24395 case RISCV::CV_MACSRN:
24396 case RISCV::CV_MACUN:
24397 case RISCV::CV_MACURN: {
24398 switch (OpNum) {
24399 case 3:
24400 // op: rs2
24401 return 20;
24402 case 2:
24403 // op: rs1
24404 return 15;
24405 case 1:
24406 // op: rd
24407 return 7;
24408 case 4:
24409 // op: imm5
24410 return 25;
24411 }
24412 break;
24413 }
24414 case RISCV::QC_LIEQ:
24415 case RISCV::QC_LIEQI:
24416 case RISCV::QC_LIGE:
24417 case RISCV::QC_LIGEI:
24418 case RISCV::QC_LIGEU:
24419 case RISCV::QC_LIGEUI:
24420 case RISCV::QC_LILT:
24421 case RISCV::QC_LILTI:
24422 case RISCV::QC_LILTU:
24423 case RISCV::QC_LILTUI:
24424 case RISCV::QC_LINE:
24425 case RISCV::QC_LINEI: {
24426 switch (OpNum) {
24427 case 3:
24428 // op: rs2
24429 return 20;
24430 case 2:
24431 // op: rs1
24432 return 15;
24433 case 1:
24434 // op: rd
24435 return 7;
24436 case 4:
24437 // op: simm
24438 return 27;
24439 }
24440 break;
24441 }
24442 case RISCV::QC_SELECTIEQ:
24443 case RISCV::QC_SELECTINE: {
24444 switch (OpNum) {
24445 case 3:
24446 // op: rs2
24447 return 20;
24448 case 2:
24449 // op: rs1
24450 return 15;
24451 case 1:
24452 // op: rd
24453 return 7;
24454 case 4:
24455 // op: simm2
24456 return 27;
24457 }
24458 break;
24459 }
24460 case RISCV::AMOCAS_B:
24461 case RISCV::AMOCAS_B_AQ:
24462 case RISCV::AMOCAS_B_AQ_RL:
24463 case RISCV::AMOCAS_B_RL:
24464 case RISCV::AMOCAS_D_RV32:
24465 case RISCV::AMOCAS_D_RV32_AQ:
24466 case RISCV::AMOCAS_D_RV32_AQ_RL:
24467 case RISCV::AMOCAS_D_RV32_RL:
24468 case RISCV::AMOCAS_D_RV64:
24469 case RISCV::AMOCAS_D_RV64_AQ:
24470 case RISCV::AMOCAS_D_RV64_AQ_RL:
24471 case RISCV::AMOCAS_D_RV64_RL:
24472 case RISCV::AMOCAS_H:
24473 case RISCV::AMOCAS_H_AQ:
24474 case RISCV::AMOCAS_H_AQ_RL:
24475 case RISCV::AMOCAS_H_RL:
24476 case RISCV::AMOCAS_Q:
24477 case RISCV::AMOCAS_Q_AQ:
24478 case RISCV::AMOCAS_Q_AQ_RL:
24479 case RISCV::AMOCAS_Q_RL:
24480 case RISCV::AMOCAS_W:
24481 case RISCV::AMOCAS_W_AQ:
24482 case RISCV::AMOCAS_W_AQ_RL:
24483 case RISCV::AMOCAS_W_RL:
24484 case RISCV::CV_ADDNR:
24485 case RISCV::CV_ADDRNR:
24486 case RISCV::CV_ADDUNR:
24487 case RISCV::CV_ADDURNR:
24488 case RISCV::CV_CPLXMUL_I:
24489 case RISCV::CV_CPLXMUL_I_DIV2:
24490 case RISCV::CV_CPLXMUL_I_DIV4:
24491 case RISCV::CV_CPLXMUL_I_DIV8:
24492 case RISCV::CV_CPLXMUL_R:
24493 case RISCV::CV_CPLXMUL_R_DIV2:
24494 case RISCV::CV_CPLXMUL_R_DIV4:
24495 case RISCV::CV_CPLXMUL_R_DIV8:
24496 case RISCV::CV_INSERTR:
24497 case RISCV::CV_MAC:
24498 case RISCV::CV_MSU:
24499 case RISCV::CV_PACKHI_B:
24500 case RISCV::CV_PACKLO_B:
24501 case RISCV::CV_SDOTSP_B:
24502 case RISCV::CV_SDOTSP_H:
24503 case RISCV::CV_SDOTSP_SC_B:
24504 case RISCV::CV_SDOTSP_SC_H:
24505 case RISCV::CV_SDOTUP_B:
24506 case RISCV::CV_SDOTUP_H:
24507 case RISCV::CV_SDOTUP_SC_B:
24508 case RISCV::CV_SDOTUP_SC_H:
24509 case RISCV::CV_SDOTUSP_B:
24510 case RISCV::CV_SDOTUSP_H:
24511 case RISCV::CV_SDOTUSP_SC_B:
24512 case RISCV::CV_SDOTUSP_SC_H:
24513 case RISCV::CV_SHUFFLE2_B:
24514 case RISCV::CV_SHUFFLE2_H:
24515 case RISCV::CV_SUBNR:
24516 case RISCV::CV_SUBRNR:
24517 case RISCV::CV_SUBUNR:
24518 case RISCV::CV_SUBURNR:
24519 case RISCV::TH_MULA:
24520 case RISCV::TH_MULAH:
24521 case RISCV::TH_MULAW:
24522 case RISCV::TH_MULS:
24523 case RISCV::TH_MULSH:
24524 case RISCV::TH_MULSW:
24525 case RISCV::TH_MVEQZ:
24526 case RISCV::TH_MVNEZ: {
24527 switch (OpNum) {
24528 case 3:
24529 // op: rs2
24530 return 20;
24531 case 2:
24532 // op: rs1
24533 return 15;
24534 case 1:
24535 // op: rd
24536 return 7;
24537 }
24538 break;
24539 }
24540 case RISCV::SF_VC_V_FVV:
24541 case RISCV::SF_VC_V_FVW: {
24542 switch (OpNum) {
24543 case 3:
24544 // op: rs2
24545 return 20;
24546 case 4:
24547 // op: rs1
24548 return 15;
24549 case 2:
24550 // op: rd
24551 return 7;
24552 case 1:
24553 // op: funct6_lo1
24554 return 26;
24555 }
24556 break;
24557 }
24558 case RISCV::SF_VC_V_IVV:
24559 case RISCV::SF_VC_V_IVW:
24560 case RISCV::SF_VC_V_VVV:
24561 case RISCV::SF_VC_V_VVW:
24562 case RISCV::SF_VC_V_XVV:
24563 case RISCV::SF_VC_V_XVW: {
24564 switch (OpNum) {
24565 case 3:
24566 // op: rs2
24567 return 20;
24568 case 4:
24569 // op: rs1
24570 return 15;
24571 case 2:
24572 // op: rd
24573 return 7;
24574 case 1:
24575 // op: funct6_lo2
24576 return 26;
24577 }
24578 break;
24579 }
24580 case RISCV::MIPS_CCMOV: {
24581 switch (OpNum) {
24582 case 3:
24583 // op: rs3
24584 return 27;
24585 case 2:
24586 // op: rs2
24587 return 20;
24588 case 1:
24589 // op: rs1
24590 return 15;
24591 case 0:
24592 // op: rd
24593 return 7;
24594 }
24595 break;
24596 }
24597 case RISCV::FMADD_D:
24598 case RISCV::FMADD_D_IN32X:
24599 case RISCV::FMADD_D_INX:
24600 case RISCV::FMADD_H:
24601 case RISCV::FMADD_H_INX:
24602 case RISCV::FMADD_Q:
24603 case RISCV::FMADD_S:
24604 case RISCV::FMADD_S_INX:
24605 case RISCV::FMSUB_D:
24606 case RISCV::FMSUB_D_IN32X:
24607 case RISCV::FMSUB_D_INX:
24608 case RISCV::FMSUB_H:
24609 case RISCV::FMSUB_H_INX:
24610 case RISCV::FMSUB_Q:
24611 case RISCV::FMSUB_S:
24612 case RISCV::FMSUB_S_INX:
24613 case RISCV::FNMADD_D:
24614 case RISCV::FNMADD_D_IN32X:
24615 case RISCV::FNMADD_D_INX:
24616 case RISCV::FNMADD_H:
24617 case RISCV::FNMADD_H_INX:
24618 case RISCV::FNMADD_Q:
24619 case RISCV::FNMADD_S:
24620 case RISCV::FNMADD_S_INX:
24621 case RISCV::FNMSUB_D:
24622 case RISCV::FNMSUB_D_IN32X:
24623 case RISCV::FNMSUB_D_INX:
24624 case RISCV::FNMSUB_H:
24625 case RISCV::FNMSUB_H_INX:
24626 case RISCV::FNMSUB_Q:
24627 case RISCV::FNMSUB_S:
24628 case RISCV::FNMSUB_S_INX: {
24629 switch (OpNum) {
24630 case 3:
24631 // op: rs3
24632 return 27;
24633 case 2:
24634 // op: rs2
24635 return 20;
24636 case 1:
24637 // op: rs1
24638 return 15;
24639 case 4:
24640 // op: frm
24641 return 12;
24642 case 0:
24643 // op: rd
24644 return 7;
24645 }
24646 break;
24647 }
24648 case RISCV::CV_SB_rr_inc:
24649 case RISCV::CV_SH_rr_inc:
24650 case RISCV::CV_SW_rr_inc: {
24651 switch (OpNum) {
24652 case 3:
24653 // op: rs3
24654 return 7;
24655 case 1:
24656 // op: rs2
24657 return 20;
24658 case 2:
24659 // op: rs1
24660 return 15;
24661 }
24662 break;
24663 }
24664 case RISCV::TH_VMAQASU_VX:
24665 case RISCV::TH_VMAQAUS_VX:
24666 case RISCV::TH_VMAQAU_VX:
24667 case RISCV::TH_VMAQA_VX:
24668 case RISCV::VFMACC_VF:
24669 case RISCV::VFMADD_VF:
24670 case RISCV::VFMSAC_VF:
24671 case RISCV::VFMSUB_VF:
24672 case RISCV::VFNMACC_VF:
24673 case RISCV::VFNMADD_VF:
24674 case RISCV::VFNMSAC_VF:
24675 case RISCV::VFNMSUB_VF:
24676 case RISCV::VFWMACCBF16_VF:
24677 case RISCV::VFWMACC_VF:
24678 case RISCV::VFWMSAC_VF:
24679 case RISCV::VFWNMACC_VF:
24680 case RISCV::VFWNMSAC_VF:
24681 case RISCV::VMACC_VX:
24682 case RISCV::VMADD_VX:
24683 case RISCV::VNMSAC_VX:
24684 case RISCV::VNMSUB_VX:
24685 case RISCV::VWMACCSU_VX:
24686 case RISCV::VWMACCUS_VX:
24687 case RISCV::VWMACCU_VX:
24688 case RISCV::VWMACC_VX: {
24689 switch (OpNum) {
24690 case 3:
24691 // op: vs2
24692 return 20;
24693 case 2:
24694 // op: rs1
24695 return 15;
24696 case 1:
24697 // op: vd
24698 return 7;
24699 case 4:
24700 // op: vm
24701 return 25;
24702 }
24703 break;
24704 }
24705 case RISCV::TH_VMAQASU_VV:
24706 case RISCV::TH_VMAQAU_VV:
24707 case RISCV::TH_VMAQA_VV:
24708 case RISCV::VFMACC_VV:
24709 case RISCV::VFMADD_VV:
24710 case RISCV::VFMSAC_VV:
24711 case RISCV::VFMSUB_VV:
24712 case RISCV::VFNMACC_VV:
24713 case RISCV::VFNMADD_VV:
24714 case RISCV::VFNMSAC_VV:
24715 case RISCV::VFNMSUB_VV:
24716 case RISCV::VFWMACCBF16_VV:
24717 case RISCV::VFWMACC_VV:
24718 case RISCV::VFWMSAC_VV:
24719 case RISCV::VFWNMACC_VV:
24720 case RISCV::VFWNMSAC_VV:
24721 case RISCV::VMACC_VV:
24722 case RISCV::VMADD_VV:
24723 case RISCV::VNMSAC_VV:
24724 case RISCV::VNMSUB_VV:
24725 case RISCV::VWMACCSU_VV:
24726 case RISCV::VWMACCU_VV:
24727 case RISCV::VWMACC_VV: {
24728 switch (OpNum) {
24729 case 3:
24730 // op: vs2
24731 return 20;
24732 case 2:
24733 // op: vs1
24734 return 15;
24735 case 1:
24736 // op: vd
24737 return 7;
24738 case 4:
24739 // op: vm
24740 return 25;
24741 }
24742 break;
24743 }
24744 case RISCV::QC_MVEQI:
24745 case RISCV::QC_MVGEI:
24746 case RISCV::QC_MVGEUI:
24747 case RISCV::QC_MVLTI:
24748 case RISCV::QC_MVLTUI:
24749 case RISCV::QC_MVNEI: {
24750 switch (OpNum) {
24751 case 4:
24752 // op: rs3
24753 return 27;
24754 case 2:
24755 // op: rs1
24756 return 15;
24757 case 1:
24758 // op: rd
24759 return 7;
24760 case 3:
24761 // op: imm
24762 return 20;
24763 }
24764 break;
24765 }
24766 case RISCV::QC_SELECTEQI:
24767 case RISCV::QC_SELECTNEI: {
24768 switch (OpNum) {
24769 case 4:
24770 // op: rs3
24771 return 27;
24772 case 3:
24773 // op: rs2
24774 return 20;
24775 case 1:
24776 // op: rd
24777 return 7;
24778 case 2:
24779 // op: imm
24780 return 15;
24781 }
24782 break;
24783 }
24784 case RISCV::QC_MVEQ:
24785 case RISCV::QC_MVGE:
24786 case RISCV::QC_MVGEU:
24787 case RISCV::QC_MVLT:
24788 case RISCV::QC_MVLTU:
24789 case RISCV::QC_MVNE: {
24790 switch (OpNum) {
24791 case 4:
24792 // op: rs3
24793 return 27;
24794 case 3:
24795 // op: rs2
24796 return 20;
24797 case 2:
24798 // op: rs1
24799 return 15;
24800 case 1:
24801 // op: rd
24802 return 7;
24803 }
24804 break;
24805 }
24806 }
24807 std::string msg;
24808 raw_string_ostream Msg(msg);
24809 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
24810 report_fatal_error(Msg.str().c_str());
24811}
24812
24813#endif // GET_OPERAND_BIT_OFFSET
24814
24815