1//===-- RISCVMCCodeEmitter.cpp - Convert RISC-V code to machine code ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVFixupKinds.h"
15#include "MCTargetDesc/RISCVMCAsmInfo.h"
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCCodeEmitter.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstBuilder.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Support/Casting.h"
29#include "llvm/Support/EndianStream.h"
30
31using namespace llvm;
32
33#define DEBUG_TYPE "mccodeemitter"
34
35STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
36STATISTIC(MCNumFixups, "Number of MC fixups created");
37
38namespace {
39class RISCVMCCodeEmitter : public MCCodeEmitter {
40 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
41 void operator=(const RISCVMCCodeEmitter &) = delete;
42 MCContext &Ctx;
43 MCInstrInfo const &MCII;
44
45public:
46 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
47 : Ctx(ctx), MCII(MCII) {}
48
49 ~RISCVMCCodeEmitter() override = default;
50
51 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
52 SmallVectorImpl<MCFixup> &Fixups,
53 const MCSubtargetInfo &STI) const override;
54
55 void expandFunctionCall(const MCInst &MI, SmallVectorImpl<char> &CB,
56 SmallVectorImpl<MCFixup> &Fixups,
57 const MCSubtargetInfo &STI) const;
58
59 void expandTLSDESCCall(const MCInst &MI, SmallVectorImpl<char> &CB,
60 SmallVectorImpl<MCFixup> &Fixups,
61 const MCSubtargetInfo &STI) const;
62
63 void expandAddTPRel(const MCInst &MI, SmallVectorImpl<char> &CB,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const;
66
67 void expandLongCondBr(const MCInst &MI, SmallVectorImpl<char> &CB,
68 SmallVectorImpl<MCFixup> &Fixups,
69 const MCSubtargetInfo &STI) const;
70
71 void expandQCLongCondBrImm(const MCInst &MI, SmallVectorImpl<char> &CB,
72 SmallVectorImpl<MCFixup> &Fixups,
73 const MCSubtargetInfo &STI, unsigned Size) const;
74
75 /// TableGen'erated function for getting the binary encoding for an
76 /// instruction.
77 uint64_t getBinaryCodeForInstr(const MCInst &MI,
78 SmallVectorImpl<MCFixup> &Fixups,
79 const MCSubtargetInfo &STI) const;
80
81 /// Return binary encoding of operand. If the machine operand requires
82 /// relocation, record the relocation and return zero.
83 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
84 SmallVectorImpl<MCFixup> &Fixups,
85 const MCSubtargetInfo &STI) const;
86
87 uint64_t getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
88 SmallVectorImpl<MCFixup> &Fixups,
89 const MCSubtargetInfo &STI) const;
90
91 uint64_t getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
92 SmallVectorImpl<MCFixup> &Fixups,
93 const MCSubtargetInfo &STI) const;
94
95 template <unsigned N>
96 unsigned getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
97 SmallVectorImpl<MCFixup> &Fixups,
98 const MCSubtargetInfo &STI) const;
99
100 uint64_t getImmOpValue(const MCInst &MI, unsigned OpNo,
101 SmallVectorImpl<MCFixup> &Fixups,
102 const MCSubtargetInfo &STI) const;
103
104 unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
105 SmallVectorImpl<MCFixup> &Fixups,
106 const MCSubtargetInfo &STI) const;
107
108 unsigned getRlistOpValue(const MCInst &MI, unsigned OpNo,
109 SmallVectorImpl<MCFixup> &Fixups,
110 const MCSubtargetInfo &STI) const;
111
112 unsigned getRlistS0OpValue(const MCInst &MI, unsigned OpNo,
113 SmallVectorImpl<MCFixup> &Fixups,
114 const MCSubtargetInfo &STI) const;
115};
116} // end anonymous namespace
117
118MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
119 MCContext &Ctx) {
120 return new RISCVMCCodeEmitter(Ctx, MCII);
121}
122
123// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
124// relocation types. We expand those pseudo-instructions while encoding them,
125// meaning AUIPC and JALR won't go through RISC-V MC to MC compressed
126// instruction transformation. This is acceptable because AUIPC has no 16-bit
127// form and C_JALR has no immediate operand field. We let linker relaxation
128// deal with it. When linker relaxation is enabled, AUIPC and JALR have a
129// chance to relax to JAL.
130// If the C extension is enabled, JAL has a chance relax to C_JAL.
131void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI,
132 SmallVectorImpl<char> &CB,
133 SmallVectorImpl<MCFixup> &Fixups,
134 const MCSubtargetInfo &STI) const {
135 MCInst TmpInst;
136 MCOperand Func;
137 MCRegister Ra;
138 if (MI.getOpcode() == RISCV::PseudoTAIL) {
139 Func = MI.getOperand(i: 0);
140 Ra = RISCVII::getTailExpandUseRegNo(FeatureBits: STI.getFeatureBits());
141 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
142 Func = MI.getOperand(i: 1);
143 Ra = MI.getOperand(i: 0).getReg();
144 } else if (MI.getOpcode() == RISCV::PseudoCALL) {
145 Func = MI.getOperand(i: 0);
146 Ra = RISCV::X1;
147 } else if (MI.getOpcode() == RISCV::PseudoJump) {
148 Func = MI.getOperand(i: 1);
149 Ra = MI.getOperand(i: 0).getReg();
150 }
151 uint32_t Binary;
152
153 assert(Func.isExpr() && "Expected expression");
154
155 const MCExpr *CallExpr = Func.getExpr();
156
157 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
158 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Reg: Ra).addExpr(Val: CallExpr);
159 Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
160 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
161
162 if (MI.getOpcode() == RISCV::PseudoTAIL ||
163 MI.getOpcode() == RISCV::PseudoJump)
164 // Emit JALR X0, Ra, 0
165 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Reg: RISCV::X0).addReg(Reg: Ra).addImm(Val: 0);
166 else
167 // Emit JALR Ra, Ra, 0
168 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Reg: Ra).addReg(Reg: Ra).addImm(Val: 0);
169 Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
170 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
171}
172
173void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
174 SmallVectorImpl<char> &CB,
175 SmallVectorImpl<MCFixup> &Fixups,
176 const MCSubtargetInfo &STI) const {
177 MCOperand SrcSymbol = MI.getOperand(i: 3);
178 assert(SrcSymbol.isExpr() &&
179 "Expected expression as first input to TLSDESCCALL");
180 const auto *Expr = dyn_cast<MCSpecifierExpr>(Val: SrcSymbol.getExpr());
181 MCRegister Link = MI.getOperand(i: 0).getReg();
182 MCRegister Dest = MI.getOperand(i: 1).getReg();
183 int64_t Imm = MI.getOperand(i: 2).getImm();
184 Fixups.push_back(
185 Elt: MCFixup::create(Offset: 0, Value: Expr, Kind: ELF::R_RISCV_TLSDESC_CALL, Loc: MI.getLoc()));
186 MCInst Call =
187 MCInstBuilder(RISCV::JALR).addReg(Reg: Link).addReg(Reg: Dest).addImm(Val: Imm);
188
189 uint32_t Binary = getBinaryCodeForInstr(MI: Call, Fixups, STI);
190 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
191}
192
193// Expand PseudoAddTPRel to a simple ADD with the correct relocation.
194void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
195 SmallVectorImpl<char> &CB,
196 SmallVectorImpl<MCFixup> &Fixups,
197 const MCSubtargetInfo &STI) const {
198 MCOperand DestReg = MI.getOperand(i: 0);
199 MCOperand SrcReg = MI.getOperand(i: 1);
200 MCOperand TPReg = MI.getOperand(i: 2);
201 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
202 "Expected thread pointer as second input to TP-relative add");
203
204 MCOperand SrcSymbol = MI.getOperand(i: 3);
205 assert(SrcSymbol.isExpr() &&
206 "Expected expression as third input to TP-relative add");
207
208 const auto *Expr = dyn_cast<MCSpecifierExpr>(Val: SrcSymbol.getExpr());
209 assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
210 "Expected tprel_add relocation on TP-relative symbol");
211
212 Fixups.push_back(
213 Elt: MCFixup::create(Offset: 0, Value: Expr, Kind: ELF::R_RISCV_TPREL_ADD, Loc: MI.getLoc()));
214 if (STI.hasFeature(Feature: RISCV::FeatureRelax))
215 Fixups.back().setLinkerRelaxable();
216
217 // Emit a normal ADD instruction with the given operands.
218 MCInst TmpInst = MCInstBuilder(RISCV::ADD)
219 .addOperand(Op: DestReg)
220 .addOperand(Op: SrcReg)
221 .addOperand(Op: TPReg);
222 uint32_t Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
223 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
224}
225
226static unsigned getInvertedBranchOp(unsigned BrOp) {
227 switch (BrOp) {
228 default:
229 llvm_unreachable("Unexpected branch opcode!");
230 case RISCV::PseudoLongBEQ:
231 return RISCV::BNE;
232 case RISCV::PseudoLongBNE:
233 return RISCV::BEQ;
234 case RISCV::PseudoLongBLT:
235 return RISCV::BGE;
236 case RISCV::PseudoLongBGE:
237 return RISCV::BLT;
238 case RISCV::PseudoLongBLTU:
239 return RISCV::BGEU;
240 case RISCV::PseudoLongBGEU:
241 return RISCV::BLTU;
242 case RISCV::PseudoLongQC_BEQI:
243 return RISCV::QC_BNEI;
244 case RISCV::PseudoLongQC_BNEI:
245 return RISCV::QC_BEQI;
246 case RISCV::PseudoLongQC_BLTI:
247 return RISCV::QC_BGEI;
248 case RISCV::PseudoLongQC_BGEI:
249 return RISCV::QC_BLTI;
250 case RISCV::PseudoLongQC_BLTUI:
251 return RISCV::QC_BGEUI;
252 case RISCV::PseudoLongQC_BGEUI:
253 return RISCV::QC_BLTUI;
254 case RISCV::PseudoLongQC_E_BEQI:
255 return RISCV::QC_E_BNEI;
256 case RISCV::PseudoLongQC_E_BNEI:
257 return RISCV::QC_E_BEQI;
258 case RISCV::PseudoLongQC_E_BLTI:
259 return RISCV::QC_E_BGEI;
260 case RISCV::PseudoLongQC_E_BGEI:
261 return RISCV::QC_E_BLTI;
262 case RISCV::PseudoLongQC_E_BLTUI:
263 return RISCV::QC_E_BGEUI;
264 case RISCV::PseudoLongQC_E_BGEUI:
265 return RISCV::QC_E_BLTUI;
266 }
267}
268
269// Expand PseudoLongBxx to an inverted conditional branch and an unconditional
270// jump.
271void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
272 SmallVectorImpl<char> &CB,
273 SmallVectorImpl<MCFixup> &Fixups,
274 const MCSubtargetInfo &STI) const {
275 MCRegister SrcReg1 = MI.getOperand(i: 0).getReg();
276 MCRegister SrcReg2 = MI.getOperand(i: 1).getReg();
277 MCOperand SrcSymbol = MI.getOperand(i: 2);
278 unsigned Opcode = MI.getOpcode();
279 bool IsEqTest =
280 Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ;
281
282 bool UseCompressedBr = false;
283 if (IsEqTest && STI.hasFeature(Feature: RISCV::FeatureStdExtZca)) {
284 if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 &&
285 SrcReg2.id() == RISCV::X0) {
286 UseCompressedBr = true;
287 } else if (RISCV::X8 <= SrcReg2.id() && SrcReg2.id() <= RISCV::X15 &&
288 SrcReg1.id() == RISCV::X0) {
289 std::swap(a&: SrcReg1, b&: SrcReg2);
290 UseCompressedBr = true;
291 }
292 }
293
294 uint32_t Offset;
295 if (UseCompressedBr) {
296 unsigned InvOpc =
297 Opcode == RISCV::PseudoLongBNE ? RISCV::C_BEQZ : RISCV::C_BNEZ;
298 MCInst TmpInst = MCInstBuilder(InvOpc).addReg(Reg: SrcReg1).addImm(Val: 6);
299 uint16_t Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
300 support::endian::write<uint16_t>(Out&: CB, V: Binary, E: llvm::endianness::little);
301 Offset = 2;
302 } else {
303 unsigned InvOpc = getInvertedBranchOp(BrOp: Opcode);
304 MCInst TmpInst =
305 MCInstBuilder(InvOpc).addReg(Reg: SrcReg1).addReg(Reg: SrcReg2).addImm(Val: 8);
306 uint32_t Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
307 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
308 Offset = 4;
309 }
310
311 // Save the number fixups.
312 size_t FixupStartIndex = Fixups.size();
313
314 // Emit an unconditional jump to the destination.
315 MCInst TmpInst =
316 MCInstBuilder(RISCV::JAL).addReg(Reg: RISCV::X0).addOperand(Op: SrcSymbol);
317 uint32_t Binary = getBinaryCodeForInstr(MI: TmpInst, Fixups, STI);
318 support::endian::write(Out&: CB, V: Binary, E: llvm::endianness::little);
319
320 // Drop any fixup added so we can add the correct one.
321 Fixups.resize(N: FixupStartIndex);
322
323 if (SrcSymbol.isExpr()) {
324 Fixups.push_back(Elt: MCFixup::create(Offset, Value: SrcSymbol.getExpr(),
325 Kind: MCFixupKind(RISCV::fixup_riscv_jal),
326 Loc: MI.getLoc()));
327 }
328}
329
330// Expand PseudoLongQC_(E_)Bxxx to an inverted conditional branch and an
331// unconditional jump.
332void RISCVMCCodeEmitter::expandQCLongCondBrImm(const MCInst &MI,
333 SmallVectorImpl<char> &CB,
334 SmallVectorImpl<MCFixup> &Fixups,
335 const MCSubtargetInfo &STI,
336 unsigned Size) const {
337 MCRegister SrcReg1 = MI.getOperand(i: 0).getReg();
338 auto BrImm = MI.getOperand(i: 1).getImm();
339 MCOperand SrcSymbol = MI.getOperand(i: 2);
340 unsigned Opcode = MI.getOpcode();
341 uint32_t Offset;
342 unsigned InvOpc = getInvertedBranchOp(BrOp: Opcode);
343 // Emit inverted conditional branch with offset:
344 // 8 (QC.BXXX(4) + JAL(4))
345 // or
346 // 10 (QC.E.BXXX(6) + JAL(4)).
347 if (Size == 4) {
348 MCInst TmpBr =
349 MCInstBuilder(InvOpc).addReg(Reg: SrcReg1).addImm(Val: BrImm).addImm(Val: 8);
350 uint32_t BrBinary = getBinaryCodeForInstr(MI: TmpBr, Fixups, STI);
351 support::endian::write(Out&: CB, V: BrBinary, E: llvm::endianness::little);
352 } else {
353 MCInst TmpBr =
354 MCInstBuilder(InvOpc).addReg(Reg: SrcReg1).addImm(Val: BrImm).addImm(Val: 10);
355 uint64_t BrBinary =
356 getBinaryCodeForInstr(MI: TmpBr, Fixups, STI) & 0xffff'ffff'ffffu;
357 SmallVector<char, 8> Encoding;
358 support::endian::write(Out&: Encoding, V: BrBinary, E: llvm::endianness::little);
359 assert(Encoding[6] == 0 && Encoding[7] == 0 &&
360 "Unexpected encoding for 48-bit instruction");
361 Encoding.truncate(N: 6);
362 CB.append(RHS: Encoding);
363 }
364 Offset = Size;
365 // Save the number fixups.
366 size_t FixupStartIndex = Fixups.size();
367 // Emit an unconditional jump to the destination.
368 MCInst TmpJ =
369 MCInstBuilder(RISCV::JAL).addReg(Reg: RISCV::X0).addOperand(Op: SrcSymbol);
370 uint32_t JBinary = getBinaryCodeForInstr(MI: TmpJ, Fixups, STI);
371 support::endian::write(Out&: CB, V: JBinary, E: llvm::endianness::little);
372 // Drop any fixup added so we can add the correct one.
373 Fixups.resize(N: FixupStartIndex);
374 if (SrcSymbol.isExpr()) {
375 Fixups.push_back(Elt: MCFixup::create(Offset, Value: SrcSymbol.getExpr(),
376 Kind: MCFixupKind(RISCV::fixup_riscv_jal),
377 Loc: MI.getLoc()));
378 }
379}
380
381void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI,
382 SmallVectorImpl<char> &CB,
383 SmallVectorImpl<MCFixup> &Fixups,
384 const MCSubtargetInfo &STI) const {
385 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
386 // Get byte count of instruction.
387 unsigned Size = Desc.getSize();
388
389 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
390 // expanded instructions for each pseudo is correct in the Size field of the
391 // tablegen definition for the pseudo.
392 switch (MI.getOpcode()) {
393 default:
394 break;
395 case RISCV::PseudoCALLReg:
396 case RISCV::PseudoCALL:
397 case RISCV::PseudoTAIL:
398 case RISCV::PseudoJump:
399 expandFunctionCall(MI, CB, Fixups, STI);
400 MCNumEmitted += 2;
401 return;
402 case RISCV::PseudoAddTPRel:
403 expandAddTPRel(MI, CB, Fixups, STI);
404 MCNumEmitted += 1;
405 return;
406 case RISCV::PseudoLongBEQ:
407 case RISCV::PseudoLongBNE:
408 case RISCV::PseudoLongBLT:
409 case RISCV::PseudoLongBGE:
410 case RISCV::PseudoLongBLTU:
411 case RISCV::PseudoLongBGEU:
412 expandLongCondBr(MI, CB, Fixups, STI);
413 MCNumEmitted += 2;
414 return;
415 case RISCV::PseudoLongQC_BEQI:
416 case RISCV::PseudoLongQC_BNEI:
417 case RISCV::PseudoLongQC_BLTI:
418 case RISCV::PseudoLongQC_BGEI:
419 case RISCV::PseudoLongQC_BLTUI:
420 case RISCV::PseudoLongQC_BGEUI:
421 expandQCLongCondBrImm(MI, CB, Fixups, STI, Size: 4);
422 MCNumEmitted += 2;
423 return;
424 case RISCV::PseudoLongQC_E_BEQI:
425 case RISCV::PseudoLongQC_E_BNEI:
426 case RISCV::PseudoLongQC_E_BLTI:
427 case RISCV::PseudoLongQC_E_BGEI:
428 case RISCV::PseudoLongQC_E_BLTUI:
429 case RISCV::PseudoLongQC_E_BGEUI:
430 expandQCLongCondBrImm(MI, CB, Fixups, STI, Size: 6);
431 MCNumEmitted += 2;
432 return;
433 case RISCV::PseudoTLSDESCCall:
434 expandTLSDESCCall(MI, CB, Fixups, STI);
435 MCNumEmitted += 1;
436 return;
437 }
438
439 switch (Size) {
440 default:
441 llvm_unreachable("Unhandled encodeInstruction length!");
442 case 2: {
443 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
444 support::endian::write<uint16_t>(Out&: CB, V: Bits, E: llvm::endianness::little);
445 break;
446 }
447 case 4: {
448 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
449 support::endian::write(Out&: CB, V: Bits, E: llvm::endianness::little);
450 break;
451 }
452 case 6: {
453 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI) & 0xffff'ffff'ffffu;
454 SmallVector<char, 8> Encoding;
455 support::endian::write(Out&: Encoding, V: Bits, E: llvm::endianness::little);
456 assert(Encoding[6] == 0 && Encoding[7] == 0 &&
457 "Unexpected encoding for 48-bit instruction");
458 Encoding.truncate(N: 6);
459 CB.append(RHS: Encoding);
460 break;
461 }
462 case 8: {
463 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
464 support::endian::write(Out&: CB, V: Bits, E: llvm::endianness::little);
465 break;
466 }
467 }
468
469 ++MCNumEmitted; // Keep track of the # of mi's emitted.
470}
471
472uint64_t
473RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
474 SmallVectorImpl<MCFixup> &Fixups,
475 const MCSubtargetInfo &STI) const {
476
477 if (MO.isReg())
478 return Ctx.getRegisterInfo()->getEncodingValue(Reg: MO.getReg());
479
480 if (MO.isImm())
481 return MO.getImm();
482
483 llvm_unreachable("Unhandled expression!");
484 return 0;
485}
486
487uint64_t
488RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
489 SmallVectorImpl<MCFixup> &Fixups,
490 const MCSubtargetInfo &STI) const {
491 const MCOperand &MO = MI.getOperand(i: OpNo);
492
493 if (MO.isImm()) {
494 uint64_t Res = MO.getImm();
495 return (Res - 1);
496 }
497
498 llvm_unreachable("Unhandled expression!");
499 return 0;
500}
501
502uint64_t
503RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
504 SmallVectorImpl<MCFixup> &Fixups,
505 const MCSubtargetInfo &STI) const {
506 const MCOperand &MO = MI.getOperand(i: OpNo);
507 assert(MO.isImm() && "Slist operand must be immediate");
508
509 uint64_t Res = MO.getImm();
510 switch (Res) {
511 case 0:
512 return 0;
513 case 1:
514 return 1;
515 case 2:
516 return 2;
517 case 4:
518 return 3;
519 case 8:
520 return 4;
521 case 16:
522 return 5;
523 case 15:
524 return 6;
525 case 31:
526 return 7;
527 default:
528 llvm_unreachable("Unhandled Slist value!");
529 }
530}
531
532template <unsigned N>
533unsigned
534RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
535 SmallVectorImpl<MCFixup> &Fixups,
536 const MCSubtargetInfo &STI) const {
537 const MCOperand &MO = MI.getOperand(i: OpNo);
538
539 if (MO.isImm()) {
540 uint64_t Res = MO.getImm();
541 assert((Res & ((1 << N) - 1)) == 0 && "LSB is non-zero");
542 return Res >> N;
543 }
544
545 return getImmOpValue(MI, OpNo, Fixups, STI);
546}
547
548uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
549 SmallVectorImpl<MCFixup> &Fixups,
550 const MCSubtargetInfo &STI) const {
551 bool EnableRelax = STI.hasFeature(Feature: RISCV::FeatureRelax);
552 const MCOperand &MO = MI.getOperand(i: OpNo);
553
554 MCInstrDesc const &Desc = MCII.get(Opcode: MI.getOpcode());
555 unsigned MIFrm = RISCVII::getFormat(TSFlags: Desc.TSFlags);
556
557 // If the destination is an immediate, there is nothing to do.
558 if (MO.isImm())
559 return MO.getImm();
560
561 assert(MO.isExpr() &&
562 "getImmOpValue expects only expressions or immediates");
563 const MCExpr *Expr = MO.getExpr();
564 MCExpr::ExprKind Kind = Expr->getKind();
565 unsigned FixupKind = RISCV::fixup_riscv_invalid;
566 bool RelaxCandidate = false;
567 if (Kind == MCExpr::Specifier) {
568 const auto *RVExpr = cast<MCSpecifierExpr>(Val: Expr);
569 FixupKind = RVExpr->getSpecifier();
570 switch (RVExpr->getSpecifier()) {
571 default:
572 assert(FixupKind && FixupKind < FirstTargetFixupKind &&
573 "invalid specifier");
574 break;
575 case ELF::R_RISCV_TPREL_ADD:
576 // tprel_add is only used to indicate that a relocation should be emitted
577 // for an add instruction used in TP-relative addressing. It should not be
578 // expanded as if representing an actual instruction operand and so to
579 // encounter it here is an error.
580 llvm_unreachable(
581 "ELF::R_RISCV_TPREL_ADD should not represent an instruction operand");
582 case RISCV::S_LO:
583 if (MIFrm == RISCVII::InstFormatI)
584 FixupKind = RISCV::fixup_riscv_lo12_i;
585 else if (MIFrm == RISCVII::InstFormatS)
586 FixupKind = RISCV::fixup_riscv_lo12_s;
587 else
588 llvm_unreachable("VK_LO used with unexpected instruction format");
589 RelaxCandidate = true;
590 break;
591 case ELF::R_RISCV_HI20:
592 FixupKind = RISCV::fixup_riscv_hi20;
593 RelaxCandidate = true;
594 break;
595 case RISCV::S_PCREL_LO:
596 if (MIFrm == RISCVII::InstFormatI)
597 FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
598 else if (MIFrm == RISCVII::InstFormatS)
599 FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
600 else
601 llvm_unreachable("VK_PCREL_LO used with unexpected instruction format");
602 RelaxCandidate = true;
603 break;
604 case ELF::R_RISCV_PCREL_HI20:
605 FixupKind = RISCV::fixup_riscv_pcrel_hi20;
606 RelaxCandidate = true;
607 break;
608 case RISCV::S_TPREL_LO:
609 if (MIFrm == RISCVII::InstFormatI)
610 FixupKind = ELF::R_RISCV_TPREL_LO12_I;
611 else if (MIFrm == RISCVII::InstFormatS)
612 FixupKind = ELF::R_RISCV_TPREL_LO12_S;
613 else
614 llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
615 RelaxCandidate = true;
616 break;
617 case ELF::R_RISCV_TPREL_HI20:
618 RelaxCandidate = true;
619 break;
620 case ELF::R_RISCV_CALL_PLT:
621 FixupKind = RISCV::fixup_riscv_call_plt;
622 RelaxCandidate = true;
623 break;
624 case RISCV::S_QC_ABS20:
625 FixupKind = RISCV::fixup_riscv_qc_abs20_u;
626 RelaxCandidate = true;
627 break;
628 }
629 } else if (Kind == MCExpr::SymbolRef || Kind == MCExpr::Binary) {
630 // FIXME: Sub kind binary exprs have chance of underflow.
631 if (MIFrm == RISCVII::InstFormatJ) {
632 FixupKind = RISCV::fixup_riscv_jal;
633 } else if (MIFrm == RISCVII::InstFormatB) {
634 FixupKind = RISCV::fixup_riscv_branch;
635 } else if (MIFrm == RISCVII::InstFormatCJ) {
636 FixupKind = RISCV::fixup_riscv_rvc_jump;
637 } else if (MIFrm == RISCVII::InstFormatCB) {
638 FixupKind = RISCV::fixup_riscv_rvc_branch;
639 } else if (MIFrm == RISCVII::InstFormatI) {
640 FixupKind = RISCV::fixup_riscv_12_i;
641 } else if (MIFrm == RISCVII::InstFormatQC_EB) {
642 FixupKind = RISCV::fixup_riscv_qc_e_branch;
643 } else if (MIFrm == RISCVII::InstFormatQC_EAI) {
644 FixupKind = RISCV::fixup_riscv_qc_e_32;
645 RelaxCandidate = true;
646 } else if (MIFrm == RISCVII::InstFormatQC_EJ) {
647 FixupKind = RISCV::fixup_riscv_qc_e_call_plt;
648 RelaxCandidate = true;
649 } else if (MIFrm == RISCVII::InstFormatNDS_BRANCH_10) {
650 FixupKind = RISCV::fixup_riscv_nds_branch_10;
651 }
652 }
653
654 assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
655
656 Fixups.push_back(Elt: MCFixup::create(Offset: 0, Value: Expr, Kind: FixupKind, Loc: MI.getLoc()));
657 // If linker relaxation is enabled and supported by this relocation, set
658 // a bit so that if fixup is unresolved, a R_RISCV_RELAX relocation will be
659 // appended.
660 if (EnableRelax && RelaxCandidate)
661 Fixups.back().setLinkerRelaxable();
662 ++MCNumFixups;
663
664 return 0;
665}
666
667unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
668 SmallVectorImpl<MCFixup> &Fixups,
669 const MCSubtargetInfo &STI) const {
670 MCOperand MO = MI.getOperand(i: OpNo);
671 assert(MO.isReg() && "Expected a register.");
672
673 switch (MO.getReg()) {
674 default:
675 llvm_unreachable("Invalid mask register.");
676 case RISCV::V0:
677 return 0;
678 case RISCV::NoRegister:
679 return 1;
680 }
681}
682
683unsigned RISCVMCCodeEmitter::getRlistOpValue(const MCInst &MI, unsigned OpNo,
684 SmallVectorImpl<MCFixup> &Fixups,
685 const MCSubtargetInfo &STI) const {
686 const MCOperand &MO = MI.getOperand(i: OpNo);
687 assert(MO.isImm() && "Rlist operand must be immediate");
688 auto Imm = MO.getImm();
689 assert(Imm >= 4 && "EABI is currently not implemented");
690 return Imm;
691}
692unsigned
693RISCVMCCodeEmitter::getRlistS0OpValue(const MCInst &MI, unsigned OpNo,
694 SmallVectorImpl<MCFixup> &Fixups,
695 const MCSubtargetInfo &STI) const {
696 const MCOperand &MO = MI.getOperand(i: OpNo);
697 assert(MO.isImm() && "Rlist operand must be immediate");
698 auto Imm = MO.getImm();
699 assert(Imm >= 4 && "EABI is currently not implemented");
700 assert(Imm != RISCVZC::RA && "Rlist operand must include s0");
701 return Imm;
702}
703
704#include "RISCVGenMCCodeEmitter.inc"
705