1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23
24
25static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
26 MVT LocVT, CCValAssign::LocInfo LocInfo,
27 ISD::ArgFlagsTy ArgFlags, CCState &State) {
28
29 if (ArgFlags.isSRet()) {
30 if (CC_Sparc_Assign_SRet(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
31 return false;
32 }
33
34 if (LocVT == MVT::i32 ||
35 LocVT == MVT::f32) {
36 static const MCPhysReg RegList1[] = {
37 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
38 };
39 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
40 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
41 return false;
42 }
43 }
44
45 if (LocVT == MVT::f64) {
46 if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
47 return false;
48 }
49
50 if (LocVT == MVT::v2i32) {
51 if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
52 return false;
53 }
54
55 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
56 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
57 return false;
58
59 return true; // CC didn't match.
60}
61
62
63static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
64 MVT LocVT, CCValAssign::LocInfo LocInfo,
65 ISD::ArgFlagsTy ArgFlags, CCState &State) {
66
67 if (ArgFlags.isInReg()) {
68 if (LocVT == MVT::i32 ||
69 LocVT == MVT::f32) {
70 if (CC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
71 return false;
72 }
73 }
74
75 if (LocVT == MVT::i32) {
76 LocVT = MVT::i64;
77 if (ArgFlags.isSExt())
78 LocInfo = CCValAssign::SExt;
79 else if (ArgFlags.isZExt())
80 LocInfo = CCValAssign::ZExt;
81 else
82 LocInfo = CCValAssign::AExt;
83 }
84
85 if (CC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
86 return false;
87
88 return true; // CC didn't match.
89}
90
91
92static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
93 MVT LocVT, CCValAssign::LocInfo LocInfo,
94 ISD::ArgFlagsTy ArgFlags, CCState &State) {
95
96 if (LocVT == MVT::i32) {
97 static const MCPhysReg RegList1[] = {
98 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
99 };
100 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
101 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
102 return false;
103 }
104 }
105
106 if (LocVT == MVT::f32) {
107 static const MCPhysReg RegList2[] = {
108 SP::F0, SP::F1, SP::F2, SP::F3
109 };
110 if (MCRegister Reg = State.AllocateReg(Regs: RegList2)) {
111 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
112 return false;
113 }
114 }
115
116 if (LocVT == MVT::f64) {
117 static const MCPhysReg RegList3[] = {
118 SP::D0, SP::D1
119 };
120 if (MCRegister Reg = State.AllocateReg(Regs: RegList3)) {
121 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
122 return false;
123 }
124 }
125
126 if (LocVT == MVT::v2i32) {
127 if (CC_Sparc_Assign_Ret_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
128 return false;
129 }
130
131 return true; // CC didn't match.
132}
133
134
135static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
136 MVT LocVT, CCValAssign::LocInfo LocInfo,
137 ISD::ArgFlagsTy ArgFlags, CCState &State) {
138
139 if (LocVT == MVT::f32) {
140 if (RetCC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
141 return false;
142 }
143
144 if (ArgFlags.isInReg()) {
145 if (LocVT == MVT::i32 ||
146 LocVT == MVT::f32) {
147 if (RetCC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
148 return false;
149 }
150 }
151
152 if (LocVT == MVT::i32) {
153 LocVT = MVT::i64;
154 if (ArgFlags.isSExt())
155 LocInfo = CCValAssign::SExt;
156 else if (ArgFlags.isZExt())
157 LocInfo = CCValAssign::ZExt;
158 else
159 LocInfo = CCValAssign::AExt;
160 }
161
162 if (RetCC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
163 return false;
164
165 return true; // CC didn't match.
166}
167
168#else
169
170const MCRegister CC_Sparc32_ArgRegs[] = { SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 };
171const MCRegister CC_Sparc64_ArgRegs[] = { 0 };
172const MCRegister RetCC_Sparc32_ArgRegs[] = { SP::D0, SP::D1, SP::F0, SP::F1, SP::F2, SP::F3, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 };
173const MCRegister RetCC_Sparc64_ArgRegs[] = { 0 };
174
175#endif // CC_REGISTER_LIST
176