1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcISelLowering.h"
15#include "MCTargetDesc/SparcMCTargetDesc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcRegisterInfo.h"
18#include "SparcSelectionDAGInfo.h"
19#include "SparcTargetMachine.h"
20#include "SparcTargetObjectFile.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/StringSwitch.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/CodeGen/CallingConvLower.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/SelectionDAG.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/CodeGen/TargetLowering.h"
32#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
33#include "llvm/IR/DerivedTypes.h"
34#include "llvm/IR/DiagnosticInfo.h"
35#include "llvm/IR/Function.h"
36#include "llvm/IR/Module.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/KnownBits.h"
39using namespace llvm;
40
41
42//===----------------------------------------------------------------------===//
43// Calling Convention Implementation
44//===----------------------------------------------------------------------===//
45
46static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
47 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags, CCState &State)
49{
50 assert (ArgFlags.isSRet());
51
52 // Assign SRet argument.
53 State.addLoc(V: CCValAssign::getCustomMem(ValNo, ValVT,
54 Offset: 0,
55 LocVT, HTP: LocInfo));
56 return true;
57}
58
59static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
60 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
61 ISD::ArgFlagsTy &ArgFlags, CCState &State)
62{
63 static const MCPhysReg RegList[] = {
64 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
65 };
66 // Try to get first reg.
67 if (Register Reg = State.AllocateReg(Regs: RegList)) {
68 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
69 } else {
70 // Assign whole thing in stack.
71 State.addLoc(V: CCValAssign::getCustomMem(
72 ValNo, ValVT, Offset: State.AllocateStack(Size: 8, Alignment: Align(4)), LocVT, HTP: LocInfo));
73 return true;
74 }
75
76 // Try to get second reg.
77 if (Register Reg = State.AllocateReg(Regs: RegList))
78 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
79 else
80 State.addLoc(V: CCValAssign::getCustomMem(
81 ValNo, ValVT, Offset: State.AllocateStack(Size: 4, Alignment: Align(4)), LocVT, HTP: LocInfo));
82 return true;
83}
84
85static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
86 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
87 ISD::ArgFlagsTy &ArgFlags, CCState &State)
88{
89 static const MCPhysReg RegList[] = {
90 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
91 };
92
93 // Try to get first reg.
94 if (Register Reg = State.AllocateReg(Regs: RegList))
95 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
96 else
97 return false;
98
99 // Try to get second reg.
100 if (Register Reg = State.AllocateReg(Regs: RegList))
101 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
102 else
103 return false;
104
105 return true;
106}
107
108// Allocate a full-sized argument for the 64-bit ABI.
109static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT,
110 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
111 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
112 assert((LocVT == MVT::f32 || LocVT == MVT::f128
113 || LocVT.getSizeInBits() == 64) &&
114 "Can't handle non-64 bits locations");
115
116 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
117 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
118 Align alignment = (LocVT == MVT::f128) ? Align(16) : Align(8);
119 unsigned Offset = State.AllocateStack(Size: size, Alignment: alignment);
120 unsigned Reg = 0;
121
122 if (LocVT == MVT::i64 && Offset < 6*8)
123 // Promote integers to %i0-%i5.
124 Reg = SP::I0 + Offset/8;
125 else if (LocVT == MVT::f64 && Offset < 16*8)
126 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
127 Reg = SP::D0 + Offset/8;
128 else if (LocVT == MVT::f32 && Offset < 16*8)
129 // Promote floats to %f1, %f3, ...
130 Reg = SP::F1 + Offset/4;
131 else if (LocVT == MVT::f128 && Offset < 16*8)
132 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
133 Reg = SP::Q0 + Offset/16;
134
135 // Promote to register when possible, otherwise use the stack slot.
136 if (Reg) {
137 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
138 return true;
139 }
140
141 // Bail out if this is a return CC and we run out of registers to place
142 // values into.
143 if (IsReturn)
144 return false;
145
146 // This argument goes on the stack in an 8-byte slot.
147 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
148 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
149 if (LocVT == MVT::f32)
150 Offset += 4;
151
152 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
153 return true;
154}
155
156// Allocate a half-sized argument for the 64-bit ABI.
157//
158// This is used when passing { float, int } structs by value in registers.
159static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT,
160 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
161 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
162 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
163 unsigned Offset = State.AllocateStack(Size: 4, Alignment: Align(4));
164
165 if (LocVT == MVT::f32 && Offset < 16*8) {
166 // Promote floats to %f0-%f31.
167 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg: SP::F0 + Offset/4,
168 LocVT, HTP: LocInfo));
169 return true;
170 }
171
172 if (LocVT == MVT::i32 && Offset < 6*8) {
173 // Promote integers to %i0-%i5, using half the register.
174 unsigned Reg = SP::I0 + Offset/8;
175 LocVT = MVT::i64;
176 LocInfo = CCValAssign::AExt;
177
178 // Set the Custom bit if this i32 goes in the high bits of a register.
179 if (Offset % 8 == 0)
180 State.addLoc(V: CCValAssign::getCustomReg(ValNo, ValVT, Reg,
181 LocVT, HTP: LocInfo));
182 else
183 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
184 return true;
185 }
186
187 // Bail out if this is a return CC and we run out of registers to place
188 // values into.
189 if (IsReturn)
190 return false;
191
192 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, HTP: LocInfo));
193 return true;
194}
195
196static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
197 CCValAssign::LocInfo &LocInfo,
198 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
199 return Analyze_CC_Sparc64_Full(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
200 State);
201}
202
203static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
204 CCValAssign::LocInfo &LocInfo,
205 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
206 return Analyze_CC_Sparc64_Half(IsReturn: false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
207 State);
208}
209
210static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
211 CCValAssign::LocInfo &LocInfo,
212 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
213 return Analyze_CC_Sparc64_Full(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
214 State);
215}
216
217static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
218 CCValAssign::LocInfo &LocInfo,
219 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
220 return Analyze_CC_Sparc64_Half(IsReturn: true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
221 State);
222}
223
224#include "SparcGenCallingConv.inc"
225
226// The calling conventions in SparcCallingConv.td are described in terms of the
227// callee's register window. This function translates registers to the
228// corresponding caller window %o register.
229static unsigned toCallerWindow(unsigned Reg) {
230 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
231 "Unexpected enum");
232 if (Reg >= SP::I0 && Reg <= SP::I7)
233 return Reg - SP::I0 + SP::O0;
234 return Reg;
235}
236
237bool SparcTargetLowering::CanLowerReturn(
238 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
239 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
240 const Type *RetTy) const {
241 SmallVector<CCValAssign, 16> RVLocs;
242 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
243 return CCInfo.CheckReturn(Outs, Fn: Subtarget->is64Bit() ? RetCC_Sparc64
244 : RetCC_Sparc32);
245}
246
247SDValue
248SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
249 bool IsVarArg,
250 const SmallVectorImpl<ISD::OutputArg> &Outs,
251 const SmallVectorImpl<SDValue> &OutVals,
252 const SDLoc &DL, SelectionDAG &DAG) const {
253 if (Subtarget->is64Bit())
254 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
255 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
256}
257
258SDValue
259SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
260 bool IsVarArg,
261 const SmallVectorImpl<ISD::OutputArg> &Outs,
262 const SmallVectorImpl<SDValue> &OutVals,
263 const SDLoc &DL, SelectionDAG &DAG) const {
264 MachineFunction &MF = DAG.getMachineFunction();
265
266 // CCValAssign - represent the assignment of the return value to locations.
267 SmallVector<CCValAssign, 16> RVLocs;
268
269 // CCState - Info about the registers and stack slot.
270 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
271 *DAG.getContext());
272
273 // Analyze return values.
274 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc32);
275
276 SDValue Glue;
277 SmallVector<SDValue, 4> RetOps(1, Chain);
278 // Make room for the return address offset.
279 RetOps.push_back(Elt: SDValue());
280
281 // Copy the result values into the output registers.
282 for (unsigned i = 0, realRVLocIdx = 0;
283 i != RVLocs.size();
284 ++i, ++realRVLocIdx) {
285 CCValAssign &VA = RVLocs[i];
286 assert(VA.isRegLoc() && "Can only return in registers!");
287
288 SDValue Arg = OutVals[realRVLocIdx];
289
290 if (VA.needsCustom()) {
291 assert(VA.getLocVT() == MVT::v2i32);
292 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
293 // happen by default if this wasn't a legal type)
294
295 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
296 N1: Arg,
297 N2: DAG.getConstant(Val: 0, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
298 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32,
299 N1: Arg,
300 N2: DAG.getConstant(Val: 1, DL, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
301
302 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part0, Glue);
303 Glue = Chain.getValue(R: 1);
304 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
305 VA = RVLocs[++i]; // skip ahead to next loc
306 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Part1,
307 Glue);
308 } else
309 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: Arg, Glue);
310
311 // Guarantee that all emitted copies are stuck together with flags.
312 Glue = Chain.getValue(R: 1);
313 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
314 }
315
316 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
317 // If the function returns a struct, copy the SRetReturnReg to I0
318 if (MF.getFunction().hasStructRetAttr()) {
319 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
320 Register Reg = SFI->getSRetReturnReg();
321 if (!Reg)
322 llvm_unreachable("sret virtual register not created in the entry block");
323 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
324 SDValue Val = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: PtrVT);
325 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::I0, N: Val, Glue);
326 Glue = Chain.getValue(R: 1);
327 RetOps.push_back(Elt: DAG.getRegister(Reg: SP::I0, VT: PtrVT));
328 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
329 }
330
331 RetOps[0] = Chain; // Update chain.
332 RetOps[1] = DAG.getConstant(Val: RetAddrOffset, DL, VT: MVT::i32);
333
334 // Add the glue if we have it.
335 if (Glue.getNode())
336 RetOps.push_back(Elt: Glue);
337
338 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
339}
340
341// Lower return values for the 64-bit ABI.
342// Return values are passed the exactly the same way as function arguments.
343SDValue
344SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
345 bool IsVarArg,
346 const SmallVectorImpl<ISD::OutputArg> &Outs,
347 const SmallVectorImpl<SDValue> &OutVals,
348 const SDLoc &DL, SelectionDAG &DAG) const {
349 // CCValAssign - represent the assignment of the return value to locations.
350 SmallVector<CCValAssign, 16> RVLocs;
351
352 // CCState - Info about the registers and stack slot.
353 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
354 *DAG.getContext());
355
356 // Analyze return values.
357 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_Sparc64);
358
359 SDValue Glue;
360 SmallVector<SDValue, 4> RetOps(1, Chain);
361
362 // The second operand on the return instruction is the return address offset.
363 // The return address is always %i7+8 with the 64-bit ABI.
364 RetOps.push_back(Elt: DAG.getConstant(Val: 8, DL, VT: MVT::i32));
365
366 // Copy the result values into the output registers.
367 for (unsigned i = 0; i != RVLocs.size(); ++i) {
368 CCValAssign &VA = RVLocs[i];
369 assert(VA.isRegLoc() && "Can only return in registers!");
370 SDValue OutVal = OutVals[i];
371
372 // Integer return values must be sign or zero extended by the callee.
373 switch (VA.getLocInfo()) {
374 case CCValAssign::Full: break;
375 case CCValAssign::SExt:
376 OutVal = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
377 break;
378 case CCValAssign::ZExt:
379 OutVal = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
380 break;
381 case CCValAssign::AExt:
382 OutVal = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: OutVal);
383 break;
384 default:
385 llvm_unreachable("Unknown loc info!");
386 }
387
388 // The custom bit on an i32 return value indicates that it should be passed
389 // in the high bits of the register.
390 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
391 OutVal = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: OutVal,
392 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
393
394 // The next value may go in the low bits of the same register.
395 // Handle both at once.
396 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
397 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64, Operand: OutVals[i+1]);
398 OutVal = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: OutVal, N2: NV);
399 // Skip the next value, it's already done.
400 ++i;
401 }
402 }
403
404 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: VA.getLocReg(), N: OutVal, Glue);
405
406 // Guarantee that all emitted copies are stuck together with flags.
407 Glue = Chain.getValue(R: 1);
408 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
409 }
410
411 RetOps[0] = Chain; // Update chain.
412
413 // Add the flag if we have it.
414 if (Glue.getNode())
415 RetOps.push_back(Elt: Glue);
416
417 return DAG.getNode(Opcode: SPISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
418}
419
420SDValue SparcTargetLowering::LowerFormalArguments(
421 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
422 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
423 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
424 if (Subtarget->is64Bit())
425 return LowerFormalArguments_64(Chain, CallConv, isVarArg: IsVarArg, Ins,
426 dl: DL, DAG, InVals);
427 return LowerFormalArguments_32(Chain, CallConv, isVarArg: IsVarArg, Ins,
428 dl: DL, DAG, InVals);
429}
430
431/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
432/// passed in either one or two GPRs, including FP values. TODO: we should
433/// pass FP values in FP registers for fastcc functions.
434SDValue SparcTargetLowering::LowerFormalArguments_32(
435 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
436 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
437 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
438 MachineFunction &MF = DAG.getMachineFunction();
439 MachineRegisterInfo &RegInfo = MF.getRegInfo();
440 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
441
442 // Assign locations to all of the incoming arguments.
443 SmallVector<CCValAssign, 16> ArgLocs;
444 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
445 *DAG.getContext());
446 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc32);
447
448 const unsigned StackOffset = 92;
449 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
450
451 unsigned InIdx = 0;
452 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
453 CCValAssign &VA = ArgLocs[i];
454
455 if (Ins[InIdx].Flags.isSRet()) {
456 if (InIdx != 0)
457 report_fatal_error(reason: "sparc only supports sret on the first parameter");
458 // Get SRet from [%fp+64].
459 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: 64, IsImmutable: true);
460 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
461 SDValue Arg =
462 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
463 InVals.push_back(Elt: Arg);
464 continue;
465 }
466
467 if (VA.isRegLoc()) {
468 if (VA.needsCustom()) {
469 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
470
471 Register VRegHi = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
472 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VRegHi);
473 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, Reg: VRegHi, VT: MVT::i32);
474
475 assert(i+1 < e);
476 CCValAssign &NextVA = ArgLocs[++i];
477
478 SDValue LoVal;
479 if (NextVA.isMemLoc()) {
480 int FrameIdx = MF.getFrameInfo().
481 CreateFixedObject(Size: 4, SPOffset: StackOffset+NextVA.getLocMemOffset(),IsImmutable: true);
482 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
483 LoVal = DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
484 } else {
485 Register loReg = MF.addLiveIn(PReg: NextVA.getLocReg(),
486 RC: &SP::IntRegsRegClass);
487 LoVal = DAG.getCopyFromReg(Chain, dl, Reg: loReg, VT: MVT::i32);
488 }
489
490 if (IsLittleEndian)
491 std::swap(a&: LoVal, b&: HiVal);
492
493 SDValue WholeValue =
494 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
495 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: WholeValue);
496 InVals.push_back(Elt: WholeValue);
497 continue;
498 }
499 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
500 MF.getRegInfo().addLiveIn(Reg: VA.getLocReg(), vreg: VReg);
501 SDValue Arg = DAG.getCopyFromReg(Chain, dl, Reg: VReg, VT: MVT::i32);
502 if (VA.getLocVT() == MVT::f32)
503 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: Arg);
504 else if (VA.getLocVT() != MVT::i32) {
505 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: MVT::i32, N1: Arg,
506 N2: DAG.getValueType(VA.getLocVT()));
507 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getLocVT(), Operand: Arg);
508 }
509 InVals.push_back(Elt: Arg);
510 continue;
511 }
512
513 assert(VA.isMemLoc());
514
515 unsigned Offset = VA.getLocMemOffset()+StackOffset;
516 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
517
518 if (VA.needsCustom()) {
519 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
520 // If it is double-word aligned, just load.
521 if (Offset % 8 == 0) {
522 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8,
523 SPOffset: Offset,
524 IsImmutable: true);
525 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
526 SDValue Load =
527 DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
528 InVals.push_back(Elt: Load);
529 continue;
530 }
531
532 int FI = MF.getFrameInfo().CreateFixedObject(Size: 4,
533 SPOffset: Offset,
534 IsImmutable: true);
535 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
536 SDValue HiVal =
537 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
538 int FI2 = MF.getFrameInfo().CreateFixedObject(Size: 4,
539 SPOffset: Offset+4,
540 IsImmutable: true);
541 SDValue FIPtr2 = DAG.getFrameIndex(FI: FI2, VT: PtrVT);
542
543 SDValue LoVal =
544 DAG.getLoad(VT: MVT::i32, dl, Chain, Ptr: FIPtr2, PtrInfo: MachinePointerInfo());
545
546 if (IsLittleEndian)
547 std::swap(a&: LoVal, b&: HiVal);
548
549 SDValue WholeValue =
550 DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, N1: LoVal, N2: HiVal);
551 WholeValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getValVT(), Operand: WholeValue);
552 InVals.push_back(Elt: WholeValue);
553 continue;
554 }
555
556 int FI = MF.getFrameInfo().CreateFixedObject(Size: 4,
557 SPOffset: Offset,
558 IsImmutable: true);
559 SDValue FIPtr = DAG.getFrameIndex(FI, VT: PtrVT);
560 SDValue Load ;
561 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
562 Load = DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
563 } else if (VA.getValVT() == MVT::f128) {
564 report_fatal_error(reason: "SPARCv8 does not handle f128 in calls; "
565 "pass indirectly");
566 } else {
567 // We shouldn't see any other value types here.
568 llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
569 }
570 InVals.push_back(Elt: Load);
571 }
572
573 if (MF.getFunction().hasStructRetAttr()) {
574 // Copy the SRet Argument to SRetReturnReg.
575 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
576 Register Reg = SFI->getSRetReturnReg();
577 if (!Reg) {
578 Reg = MF.getRegInfo().createVirtualRegister(RegClass: &SP::IntRegsRegClass);
579 SFI->setSRetReturnReg(Reg);
580 }
581 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl, Reg, N: InVals[0]);
582 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Copy, N2: Chain);
583 }
584
585 // Store remaining ArgRegs to the stack if this is a varargs function.
586 if (isVarArg) {
587 static const MCPhysReg ArgRegs[] = {
588 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
589 };
590 unsigned NumAllocated = CCInfo.getFirstUnallocated(Regs: ArgRegs);
591 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
592 unsigned ArgOffset = CCInfo.getStackSize();
593 if (NumAllocated == 6)
594 ArgOffset += StackOffset;
595 else {
596 assert(!ArgOffset);
597 ArgOffset = 68+4*NumAllocated;
598 }
599
600 // Remember the vararg offset for the va_start implementation.
601 FuncInfo->setVarArgsFrameOffset(ArgOffset);
602
603 std::vector<SDValue> OutChains;
604
605 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
606 Register VReg = RegInfo.createVirtualRegister(RegClass: &SP::IntRegsRegClass);
607 MF.getRegInfo().addLiveIn(Reg: *CurArgReg, vreg: VReg);
608 SDValue Arg = DAG.getCopyFromReg(Chain: DAG.getRoot(), dl, Reg: VReg, VT: MVT::i32);
609
610 int FrameIdx = MF.getFrameInfo().CreateFixedObject(Size: 4, SPOffset: ArgOffset,
611 IsImmutable: true);
612 SDValue FIPtr = DAG.getFrameIndex(FI: FrameIdx, VT: MVT::i32);
613
614 OutChains.push_back(
615 x: DAG.getStore(Chain: DAG.getRoot(), dl, Val: Arg, Ptr: FIPtr, PtrInfo: MachinePointerInfo()));
616 ArgOffset += 4;
617 }
618
619 if (!OutChains.empty()) {
620 OutChains.push_back(x: Chain);
621 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
622 }
623 }
624
625 return Chain;
626}
627
628// Lower formal arguments for the 64 bit ABI.
629SDValue SparcTargetLowering::LowerFormalArguments_64(
630 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
631 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
632 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
633 MachineFunction &MF = DAG.getMachineFunction();
634
635 // Analyze arguments according to CC_Sparc64.
636 SmallVector<CCValAssign, 16> ArgLocs;
637 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
638 *DAG.getContext());
639 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_Sparc64);
640
641 // The argument array begins at %fp+BIAS+128, after the register save area.
642 const unsigned ArgArea = 128;
643
644 for (const CCValAssign &VA : ArgLocs) {
645 if (VA.isRegLoc()) {
646 // This argument is passed in a register.
647 // All integer register arguments are promoted by the caller to i64.
648
649 // Create a virtual register for the promoted live-in value.
650 Register VReg = MF.addLiveIn(PReg: VA.getLocReg(),
651 RC: getRegClassFor(VT: VA.getLocVT()));
652 SDValue Arg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: VA.getLocVT());
653
654 // Get the high bits for i32 struct elements.
655 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
656 Arg = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: Arg,
657 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
658
659 // The caller promoted the argument, so insert an Assert?ext SDNode so we
660 // won't promote the value again in this function.
661 switch (VA.getLocInfo()) {
662 case CCValAssign::SExt:
663 Arg = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: Arg,
664 N2: DAG.getValueType(VA.getValVT()));
665 break;
666 case CCValAssign::ZExt:
667 Arg = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: Arg,
668 N2: DAG.getValueType(VA.getValVT()));
669 break;
670 default:
671 break;
672 }
673
674 // Truncate the register down to the argument type.
675 if (VA.isExtInLoc())
676 Arg = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Arg);
677
678 InVals.push_back(Elt: Arg);
679 continue;
680 }
681
682 // The registers are exhausted. This argument was passed on the stack.
683 assert(VA.isMemLoc());
684 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
685 // beginning of the arguments area at %fp+BIAS+128.
686 unsigned Offset = VA.getLocMemOffset() + ArgArea;
687 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
688 // Adjust offset for extended arguments, SPARC is big-endian.
689 // The caller will have written the full slot with extended bytes, but we
690 // prefer our own extending loads.
691 if (VA.isExtInLoc())
692 Offset += 8 - ValSize;
693 int FI = MF.getFrameInfo().CreateFixedObject(Size: ValSize, SPOffset: Offset, IsImmutable: true);
694 InVals.push_back(
695 Elt: DAG.getLoad(VT: VA.getValVT(), dl: DL, Chain,
696 Ptr: DAG.getFrameIndex(FI, VT: getPointerTy(DL: MF.getDataLayout())),
697 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
698 }
699
700 if (!IsVarArg)
701 return Chain;
702
703 // This function takes variable arguments, some of which may have been passed
704 // in registers %i0-%i5. Variable floating point arguments are never passed
705 // in floating point registers. They go on %i0-%i5 or on the stack like
706 // integer arguments.
707 //
708 // The va_start intrinsic needs to know the offset to the first variable
709 // argument.
710 unsigned ArgOffset = CCInfo.getStackSize();
711 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
712 // Skip the 128 bytes of register save area.
713 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
714 Subtarget->getStackPointerBias());
715
716 // Save the variable arguments that were passed in registers.
717 // The caller is required to reserve stack space for 6 arguments regardless
718 // of how many arguments were actually passed.
719 SmallVector<SDValue, 8> OutChains;
720 for (; ArgOffset < 6*8; ArgOffset += 8) {
721 Register VReg = MF.addLiveIn(PReg: SP::I0 + ArgOffset/8, RC: &SP::I64RegsRegClass);
722 SDValue VArg = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: MVT::i64);
723 int FI = MF.getFrameInfo().CreateFixedObject(Size: 8, SPOffset: ArgOffset + ArgArea, IsImmutable: true);
724 auto PtrVT = getPointerTy(DL: MF.getDataLayout());
725 OutChains.push_back(
726 Elt: DAG.getStore(Chain, dl: DL, Val: VArg, Ptr: DAG.getFrameIndex(FI, VT: PtrVT),
727 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
728 }
729
730 if (!OutChains.empty())
731 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: OutChains);
732
733 return Chain;
734}
735
736// Check whether any of the argument registers are reserved
737static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI,
738 const MachineFunction &MF) {
739 // The register window design means that outgoing parameters at O*
740 // will appear in the callee as I*.
741 // Be conservative and check both sides of the register names.
742 bool Outgoing =
743 llvm::any_of(Range: SP::GPROutgoingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
744 return TRI->isReservedReg(MF, Reg: r);
745 });
746 bool Incoming =
747 llvm::any_of(Range: SP::GPRIncomingArgRegClass, P: [TRI, &MF](MCPhysReg r) {
748 return TRI->isReservedReg(MF, Reg: r);
749 });
750 return Outgoing || Incoming;
751}
752
753static void emitReservedArgRegCallError(const MachineFunction &MF) {
754 const Function &F = MF.getFunction();
755 F.getContext().diagnose(DI: DiagnosticInfoUnsupported{
756 F, ("SPARC doesn't support"
757 " function calls if any of the argument registers is reserved.")});
758}
759
760SDValue
761SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
762 SmallVectorImpl<SDValue> &InVals) const {
763 if (Subtarget->is64Bit())
764 return LowerCall_64(CLI, InVals);
765 return LowerCall_32(CLI, InVals);
766}
767
768static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
769 const CallBase *Call) {
770 if (Call)
771 return Call->hasFnAttr(Kind: Attribute::ReturnsTwice);
772
773 const Function *CalleeFn = nullptr;
774 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
775 CalleeFn = dyn_cast<Function>(Val: G->getGlobal());
776 } else if (ExternalSymbolSDNode *E =
777 dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
778 const Function &Fn = DAG.getMachineFunction().getFunction();
779 const Module *M = Fn.getParent();
780 const char *CalleeName = E->getSymbol();
781 CalleeFn = M->getFunction(Name: CalleeName);
782 }
783
784 if (!CalleeFn)
785 return false;
786 return CalleeFn->hasFnAttribute(Kind: Attribute::ReturnsTwice);
787}
788
789/// IsEligibleForTailCallOptimization - Check whether the call is eligible
790/// for tail call optimization.
791bool SparcTargetLowering::IsEligibleForTailCallOptimization(
792 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
793
794 auto &Outs = CLI.Outs;
795 auto &Caller = MF.getFunction();
796
797 // Do not tail call opt functions with "disable-tail-calls" attribute.
798 if (Caller.getFnAttribute(Kind: "disable-tail-calls").getValueAsString() == "true")
799 return false;
800
801 // Do not tail call opt if the stack is used to pass parameters.
802 // 64-bit targets have a slightly higher limit since the ABI requires
803 // to allocate some space even when all the parameters fit inside registers.
804 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0;
805 if (CCInfo.getStackSize() > StackSizeLimit)
806 return false;
807
808 // Do not tail call opt if either the callee or caller returns
809 // a struct and the other does not.
810 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
811 return false;
812
813 // Byval parameters hand the function a pointer directly into the stack area
814 // we want to reuse during a tail call.
815 for (auto &Arg : Outs)
816 if (Arg.Flags.isByVal())
817 return false;
818
819 return true;
820}
821
822// Lower a call for the 32-bit ABI.
823SDValue
824SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
825 SmallVectorImpl<SDValue> &InVals) const {
826 SelectionDAG &DAG = CLI.DAG;
827 SDLoc &dl = CLI.DL;
828 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
829 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
830 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
831 SDValue Chain = CLI.Chain;
832 SDValue Callee = CLI.Callee;
833 bool &isTailCall = CLI.IsTailCall;
834 CallingConv::ID CallConv = CLI.CallConv;
835 bool isVarArg = CLI.IsVarArg;
836 MachineFunction &MF = DAG.getMachineFunction();
837
838 // Analyze operands of the call, assigning locations to each operand.
839 SmallVector<CCValAssign, 16> ArgLocs;
840 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
841 *DAG.getContext());
842 CCInfo.AnalyzeCallOperands(Outs, Fn: CC_Sparc32);
843
844 isTailCall = isTailCall && IsEligibleForTailCallOptimization(
845 CCInfo, CLI, MF&: DAG.getMachineFunction());
846
847 // Get the size of the outgoing arguments stack space requirement.
848 unsigned ArgsSize = CCInfo.getStackSize();
849
850 // Keep stack frames 8-byte aligned.
851 ArgsSize = (ArgsSize+7) & ~7;
852
853 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
854
855 // Create local copies for byval args.
856 SmallVector<SDValue, 8> ByValArgs;
857 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
858 ISD::ArgFlagsTy Flags = Outs[i].Flags;
859 if (!Flags.isByVal())
860 continue;
861
862 SDValue Arg = OutVals[i];
863 unsigned Size = Flags.getByValSize();
864 Align Alignment = Flags.getNonZeroByValAlign();
865
866 if (Size > 0U) {
867 int FI = MFI.CreateStackObject(Size, Alignment, isSpillSlot: false);
868 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
869 SDValue SizeNode = DAG.getConstant(Val: Size, DL: dl, VT: MVT::i32);
870
871 Chain = DAG.getMemcpy(Chain, dl, Dst: FIPtr, Src: Arg, Size: SizeNode, Alignment,
872 isVol: false, // isVolatile,
873 AlwaysInline: (Size <= 32), // AlwaysInline if size <= 32,
874 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
875 SrcPtrInfo: MachinePointerInfo());
876 ByValArgs.push_back(Elt: FIPtr);
877 }
878 else {
879 SDValue nullVal;
880 ByValArgs.push_back(Elt: nullVal);
881 }
882 }
883
884 assert(!isTailCall || ArgsSize == 0);
885
886 if (!isTailCall)
887 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL: dl);
888
889 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
890 SmallVector<SDValue, 8> MemOpChains;
891
892 const unsigned StackOffset = 92;
893 bool hasStructRetAttr = false;
894 unsigned SRetArgSize = 0;
895 // Walk the register/memloc assignments, inserting copies/loads.
896 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
897 i != e;
898 ++i, ++realArgIdx) {
899 CCValAssign &VA = ArgLocs[i];
900 SDValue Arg = OutVals[realArgIdx];
901
902 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
903
904 // Use local copy if it is a byval arg.
905 if (Flags.isByVal()) {
906 Arg = ByValArgs[byvalArgIdx++];
907 if (!Arg) {
908 continue;
909 }
910 }
911
912 // Promote the value if needed.
913 switch (VA.getLocInfo()) {
914 default: llvm_unreachable("Unknown loc info!");
915 case CCValAssign::Full: break;
916 case CCValAssign::SExt:
917 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
918 break;
919 case CCValAssign::ZExt:
920 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
921 break;
922 case CCValAssign::AExt:
923 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: Arg);
924 break;
925 case CCValAssign::BCvt:
926 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getLocVT(), Operand: Arg);
927 break;
928 }
929
930 if (Flags.isSRet()) {
931 assert(VA.needsCustom());
932
933 if (isTailCall)
934 continue;
935
936 // store SRet argument in %sp+64
937 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
938 SDValue PtrOff = DAG.getIntPtrConstant(Val: 64, DL: dl);
939 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
940 MemOpChains.push_back(
941 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
942 hasStructRetAttr = true;
943 // sret only allowed on first argument
944 assert(Outs[realArgIdx].OrigArgIndex == 0);
945 SRetArgSize =
946 DAG.getDataLayout().getTypeAllocSize(Ty: CLI.getArgs()[0].IndirectType);
947 continue;
948 }
949
950 if (VA.needsCustom()) {
951 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
952
953 if (VA.isMemLoc()) {
954 unsigned Offset = VA.getLocMemOffset() + StackOffset;
955 // if it is double-word aligned, just store.
956 if (Offset % 8 == 0) {
957 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
958 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
959 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
960 MemOpChains.push_back(
961 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
962 continue;
963 }
964 }
965
966 if (VA.getLocVT() == MVT::f64) {
967 // Move from the float value from float registers into the
968 // integer registers.
969 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: Arg))
970 Arg = bitcastConstantFPToInt(C, DL: dl, DAG);
971 else
972 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: Arg);
973 }
974
975 SDValue Part0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
976 N1: Arg,
977 N2: DAG.getConstant(Val: 0, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
978 SDValue Part1 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: MVT::i32,
979 N1: Arg,
980 N2: DAG.getConstant(Val: 1, DL: dl, VT: getVectorIdxTy(DL: DAG.getDataLayout())));
981
982 if (VA.isRegLoc()) {
983 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Part0));
984 assert(i+1 != e);
985 CCValAssign &NextVA = ArgLocs[++i];
986 if (NextVA.isRegLoc()) {
987 RegsToPass.push_back(Elt: std::make_pair(x: NextVA.getLocReg(), y&: Part1));
988 } else {
989 // Store the second part in stack.
990 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
991 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
992 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
993 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
994 MemOpChains.push_back(
995 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
996 }
997 } else {
998 unsigned Offset = VA.getLocMemOffset() + StackOffset;
999 // Store the first part.
1000 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1001 SDValue PtrOff = DAG.getIntPtrConstant(Val: Offset, DL: dl);
1002 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1003 MemOpChains.push_back(
1004 Elt: DAG.getStore(Chain, dl, Val: Part0, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1005 // Store the second part.
1006 PtrOff = DAG.getIntPtrConstant(Val: Offset + 4, DL: dl);
1007 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1008 MemOpChains.push_back(
1009 Elt: DAG.getStore(Chain, dl, Val: Part1, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1010 }
1011 continue;
1012 }
1013
1014 // Arguments that can be passed on register must be kept at
1015 // RegsToPass vector
1016 if (VA.isRegLoc()) {
1017 if (VA.getLocVT() != MVT::f32) {
1018 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1019 continue;
1020 }
1021 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Arg);
1022 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1023 continue;
1024 }
1025
1026 assert(VA.isMemLoc());
1027
1028 // Create a store off the stack pointer for this argument.
1029 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: MVT::i32);
1030 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + StackOffset,
1031 DL: dl);
1032 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: MVT::i32, N1: StackPtr, N2: PtrOff);
1033 MemOpChains.push_back(
1034 Elt: DAG.getStore(Chain, dl, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1035 }
1036
1037
1038 // Emit all stores, make sure the occur before any copies into physregs.
1039 if (!MemOpChains.empty())
1040 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
1041
1042 // Build a sequence of copy-to-reg nodes chained together with token
1043 // chain and flag operands which copy the outgoing args into registers.
1044 // The InGlue in necessary since all emitted instructions must be
1045 // stuck together.
1046 SDValue InGlue;
1047 for (const auto &[OrigReg, N] : RegsToPass) {
1048 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1049 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
1050 InGlue = Chain.getValue(R: 1);
1051 }
1052
1053 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1054
1055 // If the callee is a GlobalAddress node (quite common, every direct call is)
1056 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1057 // Likewise ExternalSymbol -> TargetExternalSymbol.
1058 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1059 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL: dl, VT: MVT::i32, offset: 0);
1060 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1061 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: MVT::i32);
1062
1063 // Returns a chain & a flag for retval copy to use
1064 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1065 SmallVector<SDValue, 8> Ops;
1066 Ops.push_back(Elt: Chain);
1067 Ops.push_back(Elt: Callee);
1068 if (hasStructRetAttr)
1069 Ops.push_back(Elt: DAG.getTargetConstant(Val: SRetArgSize, DL: dl, VT: MVT::i32));
1070 for (const auto &[OrigReg, N] : RegsToPass) {
1071 Register Reg = isTailCall ? OrigReg : toCallerWindow(Reg: OrigReg);
1072 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1073 }
1074
1075 // Add a register mask operand representing the call-preserved registers.
1076 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1077 const uint32_t *Mask =
1078 ((hasReturnsTwice)
1079 ? TRI->getRTCallPreservedMask(CC: CallConv)
1080 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CC: CallConv));
1081
1082 if (isAnyArgRegReserved(TRI, MF))
1083 emitReservedArgRegCallError(MF);
1084
1085 assert(Mask && "Missing call preserved mask for calling convention");
1086 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1087
1088 if (InGlue.getNode())
1089 Ops.push_back(Elt: InGlue);
1090
1091 if (isTailCall) {
1092 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1093 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL: dl, VT: MVT::Other, Ops);
1094 }
1095
1096 Chain = DAG.getNode(Opcode: SPISD::CALL, DL: dl, VTList: NodeTys, Ops);
1097 InGlue = Chain.getValue(R: 1);
1098
1099 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL: dl);
1100 InGlue = Chain.getValue(R: 1);
1101
1102 // Assign locations to each value returned by this call.
1103 SmallVector<CCValAssign, 16> RVLocs;
1104 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1105 *DAG.getContext());
1106
1107 RVInfo.AnalyzeCallResult(Ins, Fn: RetCC_Sparc32);
1108
1109 // Copy all of the result registers out of their specified physreg.
1110 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1111 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1112 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1113 SDValue Vec = DAG.getNode(Opcode: ISD::UNDEF, DL: dl, VT: MVT::v2i32);
1114 SDValue Lo = DAG.getCopyFromReg(
1115 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i++].getLocReg()), VT: MVT::i32, Glue: InGlue);
1116 Chain = Lo.getValue(R: 1);
1117 InGlue = Lo.getValue(R: 2);
1118 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Lo,
1119 N3: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
1120 SDValue Hi = DAG.getCopyFromReg(
1121 Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()), VT: MVT::i32, Glue: InGlue);
1122 Chain = Hi.getValue(R: 1);
1123 InGlue = Hi.getValue(R: 2);
1124 Vec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: dl, VT: MVT::v2i32, N1: Vec, N2: Hi,
1125 N3: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
1126 InVals.push_back(Elt: Vec);
1127 } else {
1128 Chain =
1129 DAG.getCopyFromReg(Chain, dl, Reg: toCallerWindow(Reg: RVLocs[i].getLocReg()),
1130 VT: RVLocs[i].getValVT(), Glue: InGlue)
1131 .getValue(R: 1);
1132 InGlue = Chain.getValue(R: 2);
1133 InVals.push_back(Elt: Chain.getValue(R: 0));
1134 }
1135 }
1136
1137 return Chain;
1138}
1139
1140// FIXME? Maybe this could be a TableGen attribute on some registers and
1141// this table could be generated automatically from RegInfo.
1142Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
1143 const MachineFunction &MF) const {
1144 Register Reg = StringSwitch<Register>(RegName)
1145 .Case(S: "i0", Value: SP::I0).Case(S: "i1", Value: SP::I1).Case(S: "i2", Value: SP::I2).Case(S: "i3", Value: SP::I3)
1146 .Case(S: "i4", Value: SP::I4).Case(S: "i5", Value: SP::I5).Case(S: "i6", Value: SP::I6).Case(S: "i7", Value: SP::I7)
1147 .Case(S: "o0", Value: SP::O0).Case(S: "o1", Value: SP::O1).Case(S: "o2", Value: SP::O2).Case(S: "o3", Value: SP::O3)
1148 .Case(S: "o4", Value: SP::O4).Case(S: "o5", Value: SP::O5).Case(S: "o6", Value: SP::O6).Case(S: "o7", Value: SP::O7)
1149 .Case(S: "l0", Value: SP::L0).Case(S: "l1", Value: SP::L1).Case(S: "l2", Value: SP::L2).Case(S: "l3", Value: SP::L3)
1150 .Case(S: "l4", Value: SP::L4).Case(S: "l5", Value: SP::L5).Case(S: "l6", Value: SP::L6).Case(S: "l7", Value: SP::L7)
1151 .Case(S: "g0", Value: SP::G0).Case(S: "g1", Value: SP::G1).Case(S: "g2", Value: SP::G2).Case(S: "g3", Value: SP::G3)
1152 .Case(S: "g4", Value: SP::G4).Case(S: "g5", Value: SP::G5).Case(S: "g6", Value: SP::G6).Case(S: "g7", Value: SP::G7)
1153 .Default(Value: 0);
1154
1155 // If we're directly referencing register names
1156 // (e.g in GCC C extension `register int r asm("g1");`),
1157 // make sure that said register is in the reserve list.
1158 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1159 if (!TRI->isReservedReg(MF, Reg))
1160 Reg = Register();
1161
1162 return Reg;
1163}
1164
1165// Fixup floating point arguments in the ... part of a varargs call.
1166//
1167// The SPARC v9 ABI requires that floating point arguments are treated the same
1168// as integers when calling a varargs function. This does not apply to the
1169// fixed arguments that are part of the function's prototype.
1170//
1171// This function post-processes a CCValAssign array created by
1172// AnalyzeCallOperands().
1173static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1174 ArrayRef<ISD::OutputArg> Outs) {
1175 for (CCValAssign &VA : ArgLocs) {
1176 MVT ValTy = VA.getLocVT();
1177 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1178 // varargs functions.
1179 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1180 continue;
1181 // The fixed arguments to a varargs function still go in FP registers.
1182 if (Outs[VA.getValNo()].IsFixed)
1183 continue;
1184
1185 // This floating point argument should be reassigned.
1186 // Determine the offset into the argument array.
1187 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1188 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1189 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1190 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1191
1192 if (Offset < 6*8) {
1193 // This argument should go in %i0-%i5.
1194 unsigned IReg = SP::I0 + Offset/8;
1195 if (ValTy == MVT::f64)
1196 // Full register, just bitconvert into i64.
1197 VA = CCValAssign::getReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg, LocVT: MVT::i64,
1198 HTP: CCValAssign::BCvt);
1199 else {
1200 assert(ValTy == MVT::f128 && "Unexpected type!");
1201 // Full register, just bitconvert into i128 -- We will lower this into
1202 // two i64s in LowerCall_64.
1203 VA = CCValAssign::getCustomReg(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Reg: IReg,
1204 LocVT: MVT::i128, HTP: CCValAssign::BCvt);
1205 }
1206 } else {
1207 // This needs to go to memory, we're out of integer registers.
1208 VA = CCValAssign::getMem(ValNo: VA.getValNo(), ValVT: VA.getValVT(), Offset,
1209 LocVT: VA.getLocVT(), HTP: VA.getLocInfo());
1210 }
1211 }
1212}
1213
1214// Lower a call for the 64-bit ABI.
1215SDValue
1216SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1217 SmallVectorImpl<SDValue> &InVals) const {
1218 SelectionDAG &DAG = CLI.DAG;
1219 SDLoc DL = CLI.DL;
1220 SDValue Chain = CLI.Chain;
1221 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
1222 MachineFunction &MF = DAG.getMachineFunction();
1223
1224 // Analyze operands of the call, assigning locations to each operand.
1225 SmallVector<CCValAssign, 16> ArgLocs;
1226 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1227 *DAG.getContext());
1228 CCInfo.AnalyzeCallOperands(Outs: CLI.Outs, Fn: CC_Sparc64);
1229
1230 CLI.IsTailCall = CLI.IsTailCall && IsEligibleForTailCallOptimization(
1231 CCInfo, CLI, MF&: DAG.getMachineFunction());
1232
1233 // Get the size of the outgoing arguments stack space requirement.
1234 // The stack offset computed by CC_Sparc64 includes all arguments.
1235 // Called functions expect 6 argument words to exist in the stack frame, used
1236 // or not.
1237 unsigned StackReserved = 6 * 8u;
1238 unsigned ArgsSize = std::max<unsigned>(a: StackReserved, b: CCInfo.getStackSize());
1239
1240 // Keep stack frames 16-byte aligned.
1241 ArgsSize = alignTo(Value: ArgsSize, Align: 16);
1242
1243 // Varargs calls require special treatment.
1244 if (CLI.IsVarArg)
1245 fixupVariableFloatArgs(ArgLocs, Outs: CLI.Outs);
1246
1247 assert(!CLI.IsTailCall || ArgsSize == StackReserved);
1248
1249 // Adjust the stack pointer to make room for the arguments.
1250 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1251 // with more than 6 arguments.
1252 if (!CLI.IsTailCall)
1253 Chain = DAG.getCALLSEQ_START(Chain, InSize: ArgsSize, OutSize: 0, DL);
1254
1255 // Collect the set of registers to pass to the function and their values.
1256 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1257 // instruction.
1258 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
1259
1260 // Collect chains from all the memory opeations that copy arguments to the
1261 // stack. They must follow the stack pointer adjustment above and precede the
1262 // call instruction itself.
1263 SmallVector<SDValue, 8> MemOpChains;
1264
1265 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1266 const CCValAssign &VA = ArgLocs[i];
1267 SDValue Arg = CLI.OutVals[i];
1268
1269 // Promote the value if needed.
1270 switch (VA.getLocInfo()) {
1271 default:
1272 llvm_unreachable("Unknown location info!");
1273 case CCValAssign::Full:
1274 break;
1275 case CCValAssign::SExt:
1276 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1277 break;
1278 case CCValAssign::ZExt:
1279 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1280 break;
1281 case CCValAssign::AExt:
1282 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: Arg);
1283 break;
1284 case CCValAssign::BCvt:
1285 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1286 // SPARC does not support i128 natively. Lower it into two i64, see below.
1287 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1288 || VA.getLocVT() != MVT::i128)
1289 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VA.getLocVT(), Operand: Arg);
1290 break;
1291 }
1292
1293 if (VA.isRegLoc()) {
1294 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1295 && VA.getLocVT() == MVT::i128) {
1296 // Store and reload into the integer register reg and reg+1.
1297 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1298 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1299 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1300 SDValue HiPtrOff = DAG.getIntPtrConstant(Val: StackOffset, DL);
1301 HiPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: HiPtrOff);
1302 SDValue LoPtrOff = DAG.getIntPtrConstant(Val: StackOffset + 8, DL);
1303 LoPtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: LoPtrOff);
1304
1305 // Store to %sp+BIAS+128+Offset
1306 SDValue Store =
1307 DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1308 // Load into Reg and Reg+1
1309 SDValue Hi64 =
1310 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: HiPtrOff, PtrInfo: MachinePointerInfo());
1311 SDValue Lo64 =
1312 DAG.getLoad(VT: MVT::i64, dl: DL, Chain: Store, Ptr: LoPtrOff, PtrInfo: MachinePointerInfo());
1313
1314 Register HiReg = VA.getLocReg();
1315 Register LoReg = VA.getLocReg() + 1;
1316 if (!CLI.IsTailCall) {
1317 HiReg = toCallerWindow(Reg: HiReg);
1318 LoReg = toCallerWindow(Reg: LoReg);
1319 }
1320
1321 RegsToPass.push_back(Elt: std::make_pair(x&: HiReg, y&: Hi64));
1322 RegsToPass.push_back(Elt: std::make_pair(x&: LoReg, y&: Lo64));
1323 continue;
1324 }
1325
1326 // The custom bit on an i32 return value indicates that it should be
1327 // passed in the high bits of the register.
1328 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1329 Arg = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: Arg,
1330 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1331
1332 // The next value may go in the low bits of the same register.
1333 // Handle both at once.
1334 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1335 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1336 SDValue NV = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i64,
1337 Operand: CLI.OutVals[i+1]);
1338 Arg = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i64, N1: Arg, N2: NV);
1339 // Skip the next value, it's already done.
1340 ++i;
1341 }
1342 }
1343
1344 Register Reg = VA.getLocReg();
1345 if (!CLI.IsTailCall)
1346 Reg = toCallerWindow(Reg);
1347 RegsToPass.push_back(Elt: std::make_pair(x&: Reg, y&: Arg));
1348 continue;
1349 }
1350
1351 assert(VA.isMemLoc());
1352
1353 // Create a store off the stack pointer for this argument.
1354 SDValue StackPtr = DAG.getRegister(Reg: SP::O6, VT: PtrVT);
1355 // The argument area starts at %fp+BIAS+128 in the callee frame,
1356 // %sp+BIAS+128 in ours.
1357 SDValue PtrOff = DAG.getIntPtrConstant(Val: VA.getLocMemOffset() +
1358 Subtarget->getStackPointerBias() +
1359 128, DL);
1360 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr, N2: PtrOff);
1361 MemOpChains.push_back(
1362 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff, PtrInfo: MachinePointerInfo()));
1363 }
1364
1365 // Emit all stores, make sure they occur before the call.
1366 if (!MemOpChains.empty())
1367 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
1368
1369 // Build a sequence of CopyToReg nodes glued together with token chain and
1370 // glue operands which copy the outgoing args into registers. The InGlue is
1371 // necessary since all emitted instructions must be stuck together in order
1372 // to pass the live physical registers.
1373 SDValue InGlue;
1374 for (const auto &[Reg, N] : RegsToPass) {
1375 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg, N, Glue: InGlue);
1376 InGlue = Chain.getValue(R: 1);
1377 }
1378
1379 // If the callee is a GlobalAddress node (quite common, every direct call is)
1380 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1381 // Likewise ExternalSymbol -> TargetExternalSymbol.
1382 SDValue Callee = CLI.Callee;
1383 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, Call: CLI.CB);
1384 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
1385 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL, VT: PtrVT, offset: 0);
1386 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee))
1387 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: PtrVT);
1388
1389 // Build the operands for the call instruction itself.
1390 SmallVector<SDValue, 8> Ops;
1391 Ops.push_back(Elt: Chain);
1392 Ops.push_back(Elt: Callee);
1393 for (const auto &[Reg, N] : RegsToPass)
1394 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
1395
1396 // Add a register mask operand representing the call-preserved registers.
1397 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1398 const uint32_t *Mask =
1399 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CC: CLI.CallConv)
1400 : TRI->getCallPreservedMask(MF: DAG.getMachineFunction(),
1401 CC: CLI.CallConv));
1402
1403 if (isAnyArgRegReserved(TRI, MF))
1404 emitReservedArgRegCallError(MF);
1405
1406 assert(Mask && "Missing call preserved mask for calling convention");
1407 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1408
1409 // Make sure the CopyToReg nodes are glued to the call instruction which
1410 // consumes the registers.
1411 if (InGlue.getNode())
1412 Ops.push_back(Elt: InGlue);
1413
1414 // Now the call itself.
1415 if (CLI.IsTailCall) {
1416 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1417 return DAG.getNode(Opcode: SPISD::TAIL_CALL, DL, VT: MVT::Other, Ops);
1418 }
1419 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1420 Chain = DAG.getNode(Opcode: SPISD::CALL, DL, VTList: NodeTys, Ops);
1421 InGlue = Chain.getValue(R: 1);
1422
1423 // Revert the stack pointer immediately after the call.
1424 Chain = DAG.getCALLSEQ_END(Chain, Size1: ArgsSize, Size2: 0, Glue: InGlue, DL);
1425 InGlue = Chain.getValue(R: 1);
1426
1427 // Now extract the return values. This is more or less the same as
1428 // LowerFormalArguments_64.
1429
1430 // Assign locations to each value returned by this call.
1431 SmallVector<CCValAssign, 16> RVLocs;
1432 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1433 *DAG.getContext());
1434
1435 // Set inreg flag manually for codegen generated library calls that
1436 // return float.
1437 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1438 CLI.Ins[0].Flags.setInReg();
1439
1440 RVInfo.AnalyzeCallResult(Ins: CLI.Ins, Fn: RetCC_Sparc64);
1441
1442 // Copy all of the result registers out of their specified physreg.
1443 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1444 CCValAssign &VA = RVLocs[i];
1445 assert(VA.isRegLoc() && "Can only return in registers!");
1446 unsigned Reg = toCallerWindow(Reg: VA.getLocReg());
1447
1448 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1449 // reside in the same register in the high and low bits. Reuse the
1450 // CopyFromReg previous node to avoid duplicate copies.
1451 SDValue RV;
1452 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Val: Chain.getOperand(i: 1)))
1453 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1454 RV = Chain.getValue(R: 0);
1455
1456 // But usually we'll create a new CopyFromReg for a different register.
1457 if (!RV.getNode()) {
1458 RV = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT: RVLocs[i].getLocVT(), Glue: InGlue);
1459 Chain = RV.getValue(R: 1);
1460 InGlue = Chain.getValue(R: 2);
1461 }
1462
1463 // Get the high bits for i32 struct elements.
1464 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1465 RV = DAG.getNode(Opcode: ISD::SRL, DL, VT: VA.getLocVT(), N1: RV,
1466 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
1467
1468 // The callee promoted the return value, so insert an Assert?ext SDNode so
1469 // we won't promote the value again in this function.
1470 switch (VA.getLocInfo()) {
1471 case CCValAssign::SExt:
1472 RV = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: RV,
1473 N2: DAG.getValueType(VA.getValVT()));
1474 break;
1475 case CCValAssign::ZExt:
1476 RV = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: RV,
1477 N2: DAG.getValueType(VA.getValVT()));
1478 break;
1479 default:
1480 break;
1481 }
1482
1483 // Truncate the register down to the return value type.
1484 if (VA.isExtInLoc())
1485 RV = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: RV);
1486
1487 InVals.push_back(Elt: RV);
1488 }
1489
1490 return Chain;
1491}
1492
1493//===----------------------------------------------------------------------===//
1494// TargetLowering Implementation
1495//===----------------------------------------------------------------------===//
1496
1497TargetLowering::AtomicExpansionKind SparcTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
1498 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1499 AI->getType()->getPrimitiveSizeInBits() == 32)
1500 return AtomicExpansionKind::None; // Uses xchg instruction
1501
1502 return AtomicExpansionKind::CmpXChg;
1503}
1504
1505/// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1506/// rcond condition.
1507static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) {
1508 switch (CC) {
1509 default:
1510 llvm_unreachable("Unknown/unsigned integer condition code!");
1511 case ISD::SETEQ:
1512 return SPCC::REG_Z;
1513 case ISD::SETNE:
1514 return SPCC::REG_NZ;
1515 case ISD::SETLT:
1516 return SPCC::REG_LZ;
1517 case ISD::SETGT:
1518 return SPCC::REG_GZ;
1519 case ISD::SETLE:
1520 return SPCC::REG_LEZ;
1521 case ISD::SETGE:
1522 return SPCC::REG_GEZ;
1523 }
1524}
1525
1526/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1527/// condition.
1528static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1529 switch (CC) {
1530 default: llvm_unreachable("Unknown integer condition code!");
1531 case ISD::SETEQ: return SPCC::ICC_E;
1532 case ISD::SETNE: return SPCC::ICC_NE;
1533 case ISD::SETLT: return SPCC::ICC_L;
1534 case ISD::SETGT: return SPCC::ICC_G;
1535 case ISD::SETLE: return SPCC::ICC_LE;
1536 case ISD::SETGE: return SPCC::ICC_GE;
1537 case ISD::SETULT: return SPCC::ICC_CS;
1538 case ISD::SETULE: return SPCC::ICC_LEU;
1539 case ISD::SETUGT: return SPCC::ICC_GU;
1540 case ISD::SETUGE: return SPCC::ICC_CC;
1541 }
1542}
1543
1544/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1545/// FCC condition.
1546static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1547 switch (CC) {
1548 default: llvm_unreachable("Unknown fp condition code!");
1549 case ISD::SETEQ:
1550 case ISD::SETOEQ: return SPCC::FCC_E;
1551 case ISD::SETNE:
1552 case ISD::SETUNE: return SPCC::FCC_NE;
1553 case ISD::SETLT:
1554 case ISD::SETOLT: return SPCC::FCC_L;
1555 case ISD::SETGT:
1556 case ISD::SETOGT: return SPCC::FCC_G;
1557 case ISD::SETLE:
1558 case ISD::SETOLE: return SPCC::FCC_LE;
1559 case ISD::SETGE:
1560 case ISD::SETOGE: return SPCC::FCC_GE;
1561 case ISD::SETULT: return SPCC::FCC_UL;
1562 case ISD::SETULE: return SPCC::FCC_ULE;
1563 case ISD::SETUGT: return SPCC::FCC_UG;
1564 case ISD::SETUGE: return SPCC::FCC_UGE;
1565 case ISD::SETUO: return SPCC::FCC_U;
1566 case ISD::SETO: return SPCC::FCC_O;
1567 case ISD::SETONE: return SPCC::FCC_LG;
1568 case ISD::SETUEQ: return SPCC::FCC_UE;
1569 }
1570}
1571
1572SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1573 const SparcSubtarget &STI)
1574 : TargetLowering(TM), Subtarget(&STI) {
1575 MVT PtrVT = MVT::getIntegerVT(BitWidth: TM.getPointerSizeInBits(AS: 0));
1576
1577 // Instructions which use registers as conditionals examine all the
1578 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1579 // matters much whether it's ZeroOrOneBooleanContent, or
1580 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1581 // former.
1582 setBooleanContents(ZeroOrOneBooleanContent);
1583 setBooleanVectorContents(ZeroOrOneBooleanContent);
1584
1585 // Set up the register classes.
1586 addRegisterClass(VT: MVT::i32, RC: &SP::IntRegsRegClass);
1587 if (!Subtarget->useSoftFloat()) {
1588 addRegisterClass(VT: MVT::f32, RC: &SP::FPRegsRegClass);
1589 addRegisterClass(VT: MVT::f64, RC: &SP::DFPRegsRegClass);
1590 addRegisterClass(VT: MVT::f128, RC: &SP::QFPRegsRegClass);
1591 }
1592 if (Subtarget->is64Bit()) {
1593 addRegisterClass(VT: MVT::i64, RC: &SP::I64RegsRegClass);
1594 } else {
1595 // On 32bit sparc, we define a double-register 32bit register
1596 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1597 addRegisterClass(VT: MVT::v2i32, RC: &SP::IntPairRegClass);
1598
1599 // ...but almost all operations must be expanded, so set that as
1600 // the default.
1601 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1602 setOperationAction(Op, VT: MVT::v2i32, Action: Expand);
1603 }
1604 // Truncating/extending stores/loads are also not supported.
1605 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1606 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1607 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1608 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1609
1610 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1611 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1612 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1613
1614 setTruncStoreAction(ValVT: VT, MemVT: MVT::v2i32, Action: Expand);
1615 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: VT, Action: Expand);
1616 }
1617 // However, load and store *are* legal.
1618 setOperationAction(Op: ISD::LOAD, VT: MVT::v2i32, Action: Legal);
1619 setOperationAction(Op: ISD::STORE, VT: MVT::v2i32, Action: Legal);
1620 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: MVT::v2i32, Action: Legal);
1621 setOperationAction(Op: ISD::BUILD_VECTOR, VT: MVT::v2i32, Action: Legal);
1622
1623 // And we need to promote i64 loads/stores into vector load/store
1624 setOperationAction(Op: ISD::LOAD, VT: MVT::i64, Action: Custom);
1625 setOperationAction(Op: ISD::STORE, VT: MVT::i64, Action: Custom);
1626
1627 // Sadly, this doesn't work:
1628 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1629 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1630 }
1631
1632 // Turn FP extload into load/fpextend
1633 for (MVT VT : MVT::fp_valuetypes()) {
1634 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f16, Action: Expand);
1635 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f32, Action: Expand);
1636 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f64, Action: Expand);
1637 }
1638
1639 // Sparc doesn't have i1 sign extending load
1640 for (MVT VT : MVT::integer_valuetypes())
1641 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
1642
1643 // Turn FP truncstore into trunc + store.
1644 setTruncStoreAction(ValVT: MVT::f32, MemVT: MVT::f16, Action: Expand);
1645 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f16, Action: Expand);
1646 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
1647 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f16, Action: Expand);
1648 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f32, Action: Expand);
1649 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f64, Action: Expand);
1650
1651 // Custom legalize GlobalAddress nodes into LO/HI parts.
1652 setOperationAction(Op: ISD::GlobalAddress, VT: PtrVT, Action: Custom);
1653 setOperationAction(Op: ISD::GlobalTLSAddress, VT: PtrVT, Action: Custom);
1654 setOperationAction(Op: ISD::ConstantPool, VT: PtrVT, Action: Custom);
1655 setOperationAction(Op: ISD::BlockAddress, VT: PtrVT, Action: Custom);
1656
1657 // Sparc doesn't have sext_inreg, replace them with shl/sra
1658 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i16, Action: Expand);
1659 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i8 , Action: Expand);
1660 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1 , Action: Expand);
1661
1662 // Sparc has no REM or DIVREM operations.
1663 setOperationAction(Op: ISD::UREM, VT: MVT::i32, Action: Expand);
1664 setOperationAction(Op: ISD::SREM, VT: MVT::i32, Action: Expand);
1665 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i32, Action: Expand);
1666 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i32, Action: Expand);
1667
1668 // ... nor does SparcV9.
1669 if (Subtarget->is64Bit()) {
1670 setOperationAction(Op: ISD::UREM, VT: MVT::i64, Action: Expand);
1671 setOperationAction(Op: ISD::SREM, VT: MVT::i64, Action: Expand);
1672 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i64, Action: Expand);
1673 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i64, Action: Expand);
1674 }
1675
1676 // Custom expand fp<->sint
1677 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i32, Action: Custom);
1678 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i32, Action: Custom);
1679 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i64, Action: Custom);
1680 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i64, Action: Custom);
1681
1682 // Custom Expand fp<->uint
1683 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i32, Action: Custom);
1684 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i32, Action: Custom);
1685 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i64, Action: Custom);
1686 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i64, Action: Custom);
1687
1688 // Lower f16 conversion operations into library calls
1689 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f32, Action: Expand);
1690 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f32, Action: Expand);
1691 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f64, Action: Expand);
1692 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f64, Action: Expand);
1693 setOperationAction(Op: ISD::FP16_TO_FP, VT: MVT::f128, Action: Expand);
1694 setOperationAction(Op: ISD::FP_TO_FP16, VT: MVT::f128, Action: Expand);
1695
1696 setOperationAction(Op: ISD::BITCAST, VT: MVT::f32,
1697 Action: Subtarget->isVIS3() ? Legal : Expand);
1698 setOperationAction(Op: ISD::BITCAST, VT: MVT::i32,
1699 Action: Subtarget->isVIS3() ? Legal : Expand);
1700
1701 // Sparc has no select or setcc: expand to SELECT_CC.
1702 setOperationAction(Op: ISD::SELECT, VT: MVT::i32, Action: Expand);
1703 setOperationAction(Op: ISD::SELECT, VT: MVT::f32, Action: Expand);
1704 setOperationAction(Op: ISD::SELECT, VT: MVT::f64, Action: Expand);
1705 setOperationAction(Op: ISD::SELECT, VT: MVT::f128, Action: Expand);
1706
1707 setOperationAction(Op: ISD::SETCC, VT: MVT::i32, Action: Expand);
1708 setOperationAction(Op: ISD::SETCC, VT: MVT::f32, Action: Expand);
1709 setOperationAction(Op: ISD::SETCC, VT: MVT::f64, Action: Expand);
1710 setOperationAction(Op: ISD::SETCC, VT: MVT::f128, Action: Expand);
1711
1712 // Sparc doesn't have BRCOND either, it has BR_CC.
1713 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
1714 setOperationAction(Op: ISD::BRIND, VT: MVT::Other, Action: Expand);
1715 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
1716 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Custom);
1717 setOperationAction(Op: ISD::BR_CC, VT: MVT::f32, Action: Custom);
1718 setOperationAction(Op: ISD::BR_CC, VT: MVT::f64, Action: Custom);
1719 setOperationAction(Op: ISD::BR_CC, VT: MVT::f128, Action: Custom);
1720
1721 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Custom);
1722 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f32, Action: Custom);
1723 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f64, Action: Custom);
1724 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::f128, Action: Custom);
1725
1726 setOperationAction(Op: ISD::ADDC, VT: MVT::i32, Action: Legal);
1727 setOperationAction(Op: ISD::ADDE, VT: MVT::i32, Action: Legal);
1728 setOperationAction(Op: ISD::SUBC, VT: MVT::i32, Action: Legal);
1729 setOperationAction(Op: ISD::SUBE, VT: MVT::i32, Action: Legal);
1730
1731 if (Subtarget->isVIS3()) {
1732 setOperationAction(Op: ISD::ADDC, VT: MVT::i64, Action: Legal);
1733 setOperationAction(Op: ISD::ADDE, VT: MVT::i64, Action: Legal);
1734 }
1735
1736 if (Subtarget->is64Bit()) {
1737 setOperationAction(Op: ISD::BITCAST, VT: MVT::f64,
1738 Action: Subtarget->isVIS3() ? Legal : Expand);
1739 setOperationAction(Op: ISD::BITCAST, VT: MVT::i64,
1740 Action: Subtarget->isVIS3() ? Legal : Expand);
1741 setOperationAction(Op: ISD::SELECT, VT: MVT::i64, Action: Expand);
1742 setOperationAction(Op: ISD::SETCC, VT: MVT::i64, Action: Expand);
1743 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Custom);
1744 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Custom);
1745
1746 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64,
1747 Action: Subtarget->usePopc() ? Legal : Expand);
1748 setOperationAction(Op: ISD::BSWAP, VT: MVT::i64, Action: Expand);
1749 setOperationAction(Op: ISD::ROTL , VT: MVT::i64, Action: Expand);
1750 setOperationAction(Op: ISD::ROTR , VT: MVT::i64, Action: Expand);
1751 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i64, Action: Custom);
1752 }
1753
1754 // ATOMICs.
1755 // Atomics are supported on SparcV9. 32-bit atomics are also
1756 // supported by some Leon SparcV8 variants. Otherwise, atomics
1757 // are unsupported.
1758 if (Subtarget->isV9()) {
1759 // TODO: we _ought_ to be able to support 64-bit atomics on 32-bit sparcv9,
1760 // but it hasn't been implemented in the backend yet.
1761 if (Subtarget->is64Bit())
1762 setMaxAtomicSizeInBitsSupported(64);
1763 else
1764 setMaxAtomicSizeInBitsSupported(32);
1765 } else if (Subtarget->hasLeonCasa())
1766 setMaxAtomicSizeInBitsSupported(32);
1767 else
1768 setMaxAtomicSizeInBitsSupported(0);
1769
1770 setMinCmpXchgSizeInBits(32);
1771
1772 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i32, Action: Legal);
1773
1774 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: Legal);
1775
1776 // Custom Lower Atomic LOAD/STORE
1777 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i32, Action: Custom);
1778 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i32, Action: Custom);
1779
1780 if (Subtarget->is64Bit()) {
1781 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT: MVT::i64, Action: Legal);
1782 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i64, Action: Legal);
1783 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i64, Action: Custom);
1784 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i64, Action: Custom);
1785 }
1786
1787 if (!Subtarget->isV9()) {
1788 // SparcV8 does not have FNEGD and FABSD.
1789 setOperationAction(Op: ISD::FNEG, VT: MVT::f64, Action: Custom);
1790 setOperationAction(Op: ISD::FABS, VT: MVT::f64, Action: Custom);
1791 }
1792
1793 setOperationAction(Op: ISD::FSIN , VT: MVT::f128, Action: Expand);
1794 setOperationAction(Op: ISD::FCOS , VT: MVT::f128, Action: Expand);
1795 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f128, Action: Expand);
1796 setOperationAction(Op: ISD::FREM , VT: MVT::f128, Action: Expand);
1797 setOperationAction(Op: ISD::FMA , VT: MVT::f128, Action: Expand);
1798 setOperationAction(Op: ISD::FSIN , VT: MVT::f64, Action: Expand);
1799 setOperationAction(Op: ISD::FCOS , VT: MVT::f64, Action: Expand);
1800 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f64, Action: Expand);
1801 setOperationAction(Op: ISD::FREM , VT: MVT::f64, Action: Expand);
1802 setOperationAction(Op: ISD::FMA , VT: MVT::f64, Action: Expand);
1803 setOperationAction(Op: ISD::FSIN , VT: MVT::f32, Action: Expand);
1804 setOperationAction(Op: ISD::FCOS , VT: MVT::f32, Action: Expand);
1805 setOperationAction(Op: ISD::FSINCOS, VT: MVT::f32, Action: Expand);
1806 setOperationAction(Op: ISD::FREM , VT: MVT::f32, Action: Expand);
1807 setOperationAction(Op: ISD::FMA, VT: MVT::f32, Action: Expand);
1808 setOperationAction(Op: ISD::ROTL , VT: MVT::i32, Action: Expand);
1809 setOperationAction(Op: ISD::ROTR , VT: MVT::i32, Action: Expand);
1810 setOperationAction(Op: ISD::BSWAP, VT: MVT::i32, Action: Expand);
1811 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f128, Action: Expand);
1812 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f64, Action: Expand);
1813 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f32, Action: Expand);
1814 setOperationAction(Op: ISD::FPOW , VT: MVT::f128, Action: Expand);
1815 setOperationAction(Op: ISD::FPOW , VT: MVT::f64, Action: Expand);
1816 setOperationAction(Op: ISD::FPOW , VT: MVT::f32, Action: Expand);
1817
1818 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i32, Action: Expand);
1819 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i32, Action: Expand);
1820 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i32, Action: Expand);
1821
1822 // Expands to [SU]MUL_LOHI.
1823 setOperationAction(Op: ISD::MULHU, VT: MVT::i32, Action: Expand);
1824 setOperationAction(Op: ISD::MULHS, VT: MVT::i32, Action: Expand);
1825 setOperationAction(Op: ISD::MUL, VT: MVT::i32, Action: Expand);
1826
1827 if (Subtarget->useSoftMulDiv()) {
1828 // .umul works for both signed and unsigned
1829 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i32, Action: Expand);
1830 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i32, Action: Expand);
1831 setLibcallImpl(Call: RTLIB::MUL_I32, Impl: RTLIB::sparc_umul);
1832
1833 setOperationAction(Op: ISD::SDIV, VT: MVT::i32, Action: Expand);
1834 setLibcallImpl(Call: RTLIB::SDIV_I32, Impl: RTLIB::sparc_div);
1835
1836 setOperationAction(Op: ISD::UDIV, VT: MVT::i32, Action: Expand);
1837 setLibcallImpl(Call: RTLIB::UDIV_I32, Impl: RTLIB::sparc_udiv);
1838
1839 setLibcallImpl(Call: RTLIB::SREM_I32, Impl: RTLIB::sparc_rem);
1840 setLibcallImpl(Call: RTLIB::UREM_I32, Impl: RTLIB::sparc_urem);
1841 }
1842
1843 if (Subtarget->is64Bit()) {
1844 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i64, Action: Expand);
1845 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i64, Action: Expand);
1846 setOperationAction(Op: ISD::MULHU, VT: MVT::i64,
1847 Action: Subtarget->isVIS3() ? Legal : Expand);
1848 setOperationAction(Op: ISD::MULHS, VT: MVT::i64,
1849 Action: Subtarget->isVIS3() ? Legal : Expand);
1850
1851 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i64, Action: Expand);
1852 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i64, Action: Expand);
1853 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i64, Action: Expand);
1854 }
1855
1856 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1857 setOperationAction(Op: ISD::VASTART , VT: MVT::Other, Action: Custom);
1858 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1859 setOperationAction(Op: ISD::VAARG , VT: MVT::Other, Action: Custom);
1860
1861 setOperationAction(Op: ISD::TRAP , VT: MVT::Other, Action: Legal);
1862 setOperationAction(Op: ISD::DEBUGTRAP , VT: MVT::Other, Action: Legal);
1863
1864 // Use the default implementation.
1865 setOperationAction(Op: ISD::VACOPY , VT: MVT::Other, Action: Expand);
1866 setOperationAction(Op: ISD::VAEND , VT: MVT::Other, Action: Expand);
1867 setOperationAction(Op: ISD::STACKSAVE , VT: MVT::Other, Action: Expand);
1868 setOperationAction(Op: ISD::STACKRESTORE , VT: MVT::Other, Action: Expand);
1869 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i32 , Action: Custom);
1870
1871 setStackPointerRegisterToSaveRestore(SP::O6);
1872
1873 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32,
1874 Action: Subtarget->usePopc() ? Legal : Expand);
1875
1876 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1877 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Legal);
1878 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Legal);
1879 } else {
1880 setOperationAction(Op: ISD::LOAD, VT: MVT::f128, Action: Custom);
1881 setOperationAction(Op: ISD::STORE, VT: MVT::f128, Action: Custom);
1882 }
1883
1884 if (Subtarget->hasHardQuad()) {
1885 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Legal);
1886 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Legal);
1887 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Legal);
1888 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Legal);
1889 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Legal);
1890 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Legal);
1891 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Legal);
1892 if (Subtarget->isV9()) {
1893 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Legal);
1894 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Legal);
1895 } else {
1896 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1897 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1898 }
1899
1900 if (!Subtarget->is64Bit()) {
1901 setLibcallImpl(Call: RTLIB::FPTOSINT_F128_I64, Impl: RTLIB::_Q_qtoll);
1902 setLibcallImpl(Call: RTLIB::FPTOUINT_F128_I64, Impl: RTLIB::_Q_qtoull);
1903 setLibcallImpl(Call: RTLIB::SINTTOFP_I64_F128, Impl: RTLIB::_Q_lltoq);
1904 setLibcallImpl(Call: RTLIB::UINTTOFP_I64_F128, Impl: RTLIB::_Q_ulltoq);
1905 }
1906
1907 } else {
1908 // Custom legalize f128 operations.
1909
1910 setOperationAction(Op: ISD::FADD, VT: MVT::f128, Action: Custom);
1911 setOperationAction(Op: ISD::FSUB, VT: MVT::f128, Action: Custom);
1912 setOperationAction(Op: ISD::FMUL, VT: MVT::f128, Action: Custom);
1913 setOperationAction(Op: ISD::FDIV, VT: MVT::f128, Action: Custom);
1914 setOperationAction(Op: ISD::FSQRT, VT: MVT::f128, Action: Custom);
1915 setOperationAction(Op: ISD::FNEG, VT: MVT::f128, Action: Custom);
1916 setOperationAction(Op: ISD::FABS, VT: MVT::f128, Action: Custom);
1917
1918 setOperationAction(Op: ISD::FP_EXTEND, VT: MVT::f128, Action: Custom);
1919 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f64, Action: Custom);
1920 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f32, Action: Custom);
1921
1922 // Setup Runtime library names.
1923 if (Subtarget->is64Bit() && !Subtarget->useSoftFloat()) {
1924 setLibcallImpl(Call: RTLIB::ADD_F128, Impl: RTLIB::_Qp_add);
1925 setLibcallImpl(Call: RTLIB::SUB_F128, Impl: RTLIB::_Qp_sub);
1926 setLibcallImpl(Call: RTLIB::MUL_F128, Impl: RTLIB::_Qp_mul);
1927 setLibcallImpl(Call: RTLIB::DIV_F128, Impl: RTLIB::_Qp_div);
1928 setLibcallImpl(Call: RTLIB::SQRT_F128, Impl: RTLIB::_Qp_sqrt);
1929 setLibcallImpl(Call: RTLIB::FPTOSINT_F128_I32, Impl: RTLIB::_Qp_qtoi);
1930 setLibcallImpl(Call: RTLIB::FPTOUINT_F128_I32, Impl: RTLIB::_Qp_qtoui);
1931 setLibcallImpl(Call: RTLIB::SINTTOFP_I32_F128, Impl: RTLIB::_Qp_itoq);
1932 setLibcallImpl(Call: RTLIB::UINTTOFP_I32_F128, Impl: RTLIB::_Qp_uitoq);
1933 setLibcallImpl(Call: RTLIB::FPTOSINT_F128_I64, Impl: RTLIB::_Qp_qtox);
1934 setLibcallImpl(Call: RTLIB::FPTOUINT_F128_I64, Impl: RTLIB::_Qp_qtoux);
1935 setLibcallImpl(Call: RTLIB::SINTTOFP_I64_F128, Impl: RTLIB::_Qp_xtoq);
1936 setLibcallImpl(Call: RTLIB::UINTTOFP_I64_F128, Impl: RTLIB::_Qp_uxtoq);
1937 setLibcallImpl(Call: RTLIB::FPEXT_F32_F128, Impl: RTLIB::_Qp_stoq);
1938 setLibcallImpl(Call: RTLIB::FPEXT_F64_F128, Impl: RTLIB::_Qp_dtoq);
1939 setLibcallImpl(Call: RTLIB::FPROUND_F128_F32, Impl: RTLIB::_Qp_qtos);
1940 setLibcallImpl(Call: RTLIB::FPROUND_F128_F64, Impl: RTLIB::_Qp_qtod);
1941 } else if (!Subtarget->useSoftFloat()) {
1942 setLibcallImpl(Call: RTLIB::ADD_F128, Impl: RTLIB::_Q_add);
1943 setLibcallImpl(Call: RTLIB::SUB_F128, Impl: RTLIB::_Q_sub);
1944 setLibcallImpl(Call: RTLIB::MUL_F128, Impl: RTLIB::_Q_mul);
1945 setLibcallImpl(Call: RTLIB::DIV_F128, Impl: RTLIB::_Q_div);
1946 setLibcallImpl(Call: RTLIB::SQRT_F128, Impl: RTLIB::_Q_sqrt);
1947 setLibcallImpl(Call: RTLIB::FPTOSINT_F128_I32, Impl: RTLIB::_Q_qtoi);
1948 setLibcallImpl(Call: RTLIB::FPTOUINT_F128_I32, Impl: RTLIB::_Q_qtou);
1949 setLibcallImpl(Call: RTLIB::SINTTOFP_I32_F128, Impl: RTLIB::_Q_itoq);
1950 setLibcallImpl(Call: RTLIB::UINTTOFP_I32_F128, Impl: RTLIB::_Q_utoq);
1951 setLibcallImpl(Call: RTLIB::FPTOSINT_F128_I64, Impl: RTLIB::_Q_qtoll);
1952 setLibcallImpl(Call: RTLIB::FPTOUINT_F128_I64, Impl: RTLIB::_Q_qtoull);
1953 setLibcallImpl(Call: RTLIB::SINTTOFP_I64_F128, Impl: RTLIB::_Q_lltoq);
1954 setLibcallImpl(Call: RTLIB::UINTTOFP_I64_F128, Impl: RTLIB::_Q_ulltoq);
1955 setLibcallImpl(Call: RTLIB::FPEXT_F32_F128, Impl: RTLIB::_Q_stoq);
1956 setLibcallImpl(Call: RTLIB::FPEXT_F64_F128, Impl: RTLIB::_Q_dtoq);
1957 setLibcallImpl(Call: RTLIB::FPROUND_F128_F32, Impl: RTLIB::_Q_qtos);
1958 setLibcallImpl(Call: RTLIB::FPROUND_F128_F64, Impl: RTLIB::_Q_qtod);
1959 }
1960 }
1961
1962 if (Subtarget->fixAllFDIVSQRT()) {
1963 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1964 // the former instructions generate errata on LEON processors.
1965 setOperationAction(Op: ISD::FDIV, VT: MVT::f32, Action: Promote);
1966 setOperationAction(Op: ISD::FSQRT, VT: MVT::f32, Action: Promote);
1967 }
1968
1969 if (Subtarget->hasNoFMULS()) {
1970 setOperationAction(Op: ISD::FMUL, VT: MVT::f32, Action: Promote);
1971 }
1972
1973 // Custom combine bitcast between f64 and v2i32
1974 if (!Subtarget->is64Bit())
1975 setTargetDAGCombine(ISD::BITCAST);
1976
1977 if (Subtarget->hasLeonCycleCounter())
1978 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Custom);
1979
1980 if (Subtarget->isVIS3()) {
1981 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Legal);
1982 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Legal);
1983 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i32, Action: Legal);
1984 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i64, Action: Legal);
1985
1986 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32,
1987 Action: Subtarget->is64Bit() ? Promote : Expand);
1988 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
1989 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i32,
1990 Action: Subtarget->is64Bit() ? Promote : Expand);
1991 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i64, Action: Expand);
1992 } else if (Subtarget->usePopc()) {
1993 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
1994 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
1995 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i32, Action: Expand);
1996 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i64, Action: Expand);
1997
1998 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
1999 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2000 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i32, Action: Expand);
2001 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i64, Action: Expand);
2002 } else {
2003 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Expand);
2004 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Expand);
2005 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i32,
2006 Action: Subtarget->is64Bit() ? Promote : LibCall);
2007 setOperationAction(Op: ISD::CTLZ_ZERO_UNDEF, VT: MVT::i64, Action: LibCall);
2008
2009 // FIXME here we don't have any ISA extensions that could help us, so to
2010 // prevent large expansions those should be made into LibCalls.
2011 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Expand);
2012 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Expand);
2013 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i32, Action: Expand);
2014 setOperationAction(Op: ISD::CTTZ_ZERO_UNDEF, VT: MVT::i64, Action: Expand);
2015 }
2016
2017 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
2018
2019 setMinFunctionAlignment(Align(4));
2020
2021 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
2022}
2023
2024bool SparcTargetLowering::useSoftFloat() const {
2025 return Subtarget->useSoftFloat();
2026}
2027
2028EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
2029 EVT VT) const {
2030 if (!VT.isVector())
2031 return MVT::i32;
2032 return VT.changeVectorElementTypeToInteger();
2033}
2034
2035/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2036/// be zero. Op is expected to be a target specific node. Used by DAG
2037/// combiner.
2038void SparcTargetLowering::computeKnownBitsForTargetNode
2039 (const SDValue Op,
2040 KnownBits &Known,
2041 const APInt &DemandedElts,
2042 const SelectionDAG &DAG,
2043 unsigned Depth) const {
2044 KnownBits Known2;
2045 Known.resetAll();
2046
2047 switch (Op.getOpcode()) {
2048 default: break;
2049 case SPISD::SELECT_ICC:
2050 case SPISD::SELECT_XCC:
2051 case SPISD::SELECT_FCC:
2052 Known = DAG.computeKnownBits(Op: Op.getOperand(i: 1), Depth: Depth + 1);
2053 Known2 = DAG.computeKnownBits(Op: Op.getOperand(i: 0), Depth: Depth + 1);
2054
2055 // Only known if known in both the LHS and RHS.
2056 Known = Known.intersectWith(RHS: Known2);
2057 break;
2058 }
2059}
2060
2061// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
2062// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
2063static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
2064 ISD::CondCode CC, unsigned &SPCC) {
2065 if (isNullConstant(V: RHS) && CC == ISD::SETNE &&
2066 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2067 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2068 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPICC) ||
2069 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2070 (LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC ||
2071 LHS.getOperand(i: 3).getOpcode() == SPISD::CMPFCC_V9))) &&
2072 isOneConstant(V: LHS.getOperand(i: 0)) && isNullConstant(V: LHS.getOperand(i: 1))) {
2073 SDValue CMPCC = LHS.getOperand(i: 3);
2074 SPCC = LHS.getConstantOperandVal(i: 2);
2075 LHS = CMPCC.getOperand(i: 0);
2076 RHS = CMPCC.getOperand(i: 1);
2077 }
2078}
2079
2080// Convert to a target node and set target flags.
2081SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
2082 SelectionDAG &DAG) const {
2083 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op))
2084 return DAG.getTargetGlobalAddress(GV: GA->getGlobal(),
2085 DL: SDLoc(GA),
2086 VT: GA->getValueType(ResNo: 0),
2087 offset: GA->getOffset(), TargetFlags: TF);
2088
2089 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: Op))
2090 return DAG.getTargetConstantPool(C: CP->getConstVal(), VT: CP->getValueType(ResNo: 0),
2091 Align: CP->getAlign(), Offset: CP->getOffset(), TargetFlags: TF);
2092
2093 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Val&: Op))
2094 return DAG.getTargetBlockAddress(BA: BA->getBlockAddress(),
2095 VT: Op.getValueType(),
2096 Offset: 0,
2097 TargetFlags: TF);
2098
2099 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Val&: Op))
2100 return DAG.getTargetExternalSymbol(Sym: ES->getSymbol(),
2101 VT: ES->getValueType(ResNo: 0), TargetFlags: TF);
2102
2103 llvm_unreachable("Unhandled address SDNode");
2104}
2105
2106// Split Op into high and low parts according to HiTF and LoTF.
2107// Return an ADD node combining the parts.
2108SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
2109 unsigned HiTF, unsigned LoTF,
2110 SelectionDAG &DAG) const {
2111 SDLoc DL(Op);
2112 EVT VT = Op.getValueType();
2113 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT, Operand: withTargetFlags(Op, TF: HiTF, DAG));
2114 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: withTargetFlags(Op, TF: LoTF, DAG));
2115 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2116}
2117
2118// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
2119// or ExternalSymbol SDNode.
2120SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
2121 SDLoc DL(Op);
2122 EVT VT = getPointerTy(DL: DAG.getDataLayout());
2123
2124 // Handle PIC mode first. SPARC needs a got load for every variable!
2125 if (isPositionIndependent()) {
2126 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2127 PICLevel::Level picLevel = M->getPICLevel();
2128 SDValue Idx;
2129
2130 if (picLevel == PICLevel::SmallPIC) {
2131 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
2132 Idx = DAG.getNode(Opcode: SPISD::Lo, DL, VT: Op.getValueType(),
2133 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_GOT13, DAG));
2134 } else {
2135 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
2136 Idx = makeHiLoPair(Op, HiTF: ELF::R_SPARC_GOT22, LoTF: ELF::R_SPARC_GOT10, DAG);
2137 }
2138
2139 SDValue GlobalBase = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT);
2140 SDValue AbsAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: GlobalBase, N2: Idx);
2141 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2142 // function has calls.
2143 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2144 MFI.setHasCalls(true);
2145 return DAG.getLoad(VT, dl: DL, Chain: DAG.getEntryNode(), Ptr: AbsAddr,
2146 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2147 }
2148
2149 // This is one of the absolute code models.
2150 switch(getTargetMachine().getCodeModel()) {
2151 default:
2152 llvm_unreachable("Unsupported absolute code model");
2153 case CodeModel::Small:
2154 // abs32.
2155 return makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2156 case CodeModel::Medium: {
2157 // abs44.
2158 SDValue H44 = makeHiLoPair(Op, HiTF: ELF::R_SPARC_H44, LoTF: ELF::R_SPARC_M44, DAG);
2159 H44 = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: H44, N2: DAG.getConstant(Val: 12, DL, VT: MVT::i32));
2160 SDValue L44 = withTargetFlags(Op, TF: ELF::R_SPARC_L44, DAG);
2161 L44 = DAG.getNode(Opcode: SPISD::Lo, DL, VT, Operand: L44);
2162 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: H44, N2: L44);
2163 }
2164 case CodeModel::Large: {
2165 // abs64.
2166 SDValue Hi = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HH22, LoTF: ELF::R_SPARC_HM10, DAG);
2167 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Hi, N2: DAG.getConstant(Val: 32, DL, VT: MVT::i32));
2168 SDValue Lo = makeHiLoPair(Op, HiTF: ELF::R_SPARC_HI22, LoTF: ELF::R_SPARC_LO10, DAG);
2169 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Hi, N2: Lo);
2170 }
2171 }
2172}
2173
2174SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2175 SelectionDAG &DAG) const {
2176 return makeAddress(Op, DAG);
2177}
2178
2179SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2180 SelectionDAG &DAG) const {
2181 return makeAddress(Op, DAG);
2182}
2183
2184SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2185 SelectionDAG &DAG) const {
2186 return makeAddress(Op, DAG);
2187}
2188
2189SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2190 SelectionDAG &DAG) const {
2191
2192 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Val&: Op);
2193 if (DAG.getTarget().useEmulatedTLS())
2194 return LowerToTLSEmulatedModel(GA, DAG);
2195
2196 SDLoc DL(GA);
2197 const GlobalValue *GV = GA->getGlobal();
2198 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2199
2200 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2201
2202 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2203 unsigned HiTF =
2204 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_HI22
2205 : ELF::R_SPARC_TLS_LDM_HI22);
2206 unsigned LoTF =
2207 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_LO10
2208 : ELF::R_SPARC_TLS_LDM_LO10);
2209 unsigned addTF =
2210 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_ADD
2211 : ELF::R_SPARC_TLS_LDM_ADD);
2212 unsigned callTF =
2213 ((model == TLSModel::GeneralDynamic) ? ELF::R_SPARC_TLS_GD_CALL
2214 : ELF::R_SPARC_TLS_LDM_CALL);
2215
2216 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2217 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2218 SDValue Argument = DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Base, N2: HiLo,
2219 N3: withTargetFlags(Op, TF: addTF, DAG));
2220
2221 SDValue Chain = DAG.getEntryNode();
2222 SDValue InGlue;
2223
2224 Chain = DAG.getCALLSEQ_START(Chain, InSize: 1, OutSize: 0, DL);
2225 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SP::O0, N: Argument, Glue: InGlue);
2226 InGlue = Chain.getValue(R: 1);
2227 SDValue Callee = DAG.getTargetExternalSymbol(Sym: "__tls_get_addr", VT: PtrVT);
2228 SDValue Symbol = withTargetFlags(Op, TF: callTF, DAG);
2229
2230 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2231 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2232 MF: DAG.getMachineFunction(), CC: CallingConv::C);
2233 assert(Mask && "Missing call preserved mask for calling convention");
2234 SDValue Ops[] = {Chain,
2235 Callee,
2236 Symbol,
2237 DAG.getRegister(Reg: SP::O0, VT: PtrVT),
2238 DAG.getRegisterMask(RegMask: Mask),
2239 InGlue};
2240 Chain = DAG.getNode(Opcode: SPISD::TLS_CALL, DL, VTList: NodeTys, Ops);
2241 InGlue = Chain.getValue(R: 1);
2242 Chain = DAG.getCALLSEQ_END(Chain, Size1: 1, Size2: 0, Glue: InGlue, DL);
2243 InGlue = Chain.getValue(R: 1);
2244 SDValue Ret = DAG.getCopyFromReg(Chain, dl: DL, Reg: SP::O0, VT: PtrVT, Glue: InGlue);
2245
2246 if (model != TLSModel::LocalDynamic)
2247 return Ret;
2248
2249 SDValue Hi =
2250 DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2251 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_HIX22, DAG));
2252 SDValue Lo =
2253 DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2254 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_LOX10, DAG));
2255 HiLo = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2256 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT, N1: Ret, N2: HiLo,
2257 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LDO_ADD, DAG));
2258 }
2259
2260 if (model == TLSModel::InitialExec) {
2261 unsigned ldTF = ((PtrVT == MVT::i64) ? ELF::R_SPARC_TLS_IE_LDX
2262 : ELF::R_SPARC_TLS_IE_LD);
2263
2264 SDValue Base = DAG.getNode(Opcode: SPISD::GLOBAL_BASE_REG, DL, VT: PtrVT);
2265
2266 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2267 // function has calls.
2268 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2269 MFI.setHasCalls(true);
2270
2271 SDValue TGA = makeHiLoPair(Op, HiTF: ELF::R_SPARC_TLS_IE_HI22,
2272 LoTF: ELF::R_SPARC_TLS_IE_LO10, DAG);
2273 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Base, N2: TGA);
2274 SDValue Offset = DAG.getNode(Opcode: SPISD::TLS_LD,
2275 DL, VT: PtrVT, N1: Ptr,
2276 N2: withTargetFlags(Op, TF: ldTF, DAG));
2277 return DAG.getNode(Opcode: SPISD::TLS_ADD, DL, VT: PtrVT,
2278 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset,
2279 N3: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_IE_ADD, DAG));
2280 }
2281
2282 assert(model == TLSModel::LocalExec);
2283 SDValue Hi = DAG.getNode(Opcode: SPISD::Hi, DL, VT: PtrVT,
2284 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_HIX22, DAG));
2285 SDValue Lo = DAG.getNode(Opcode: SPISD::Lo, DL, VT: PtrVT,
2286 Operand: withTargetFlags(Op, TF: ELF::R_SPARC_TLS_LE_LOX10, DAG));
2287 SDValue Offset = DAG.getNode(Opcode: ISD::XOR, DL, VT: PtrVT, N1: Hi, N2: Lo);
2288
2289 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT,
2290 N1: DAG.getRegister(Reg: SP::G7, VT: PtrVT), N2: Offset);
2291}
2292
2293SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2294 ArgListTy &Args, SDValue Arg,
2295 const SDLoc &DL,
2296 SelectionDAG &DAG) const {
2297 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2298 EVT ArgVT = Arg.getValueType();
2299 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2300
2301 ArgListEntry Entry;
2302 Entry.Node = Arg;
2303 Entry.Ty = ArgTy;
2304
2305 if (ArgTy->isFP128Ty()) {
2306 // Create a stack object and pass the pointer to the library function.
2307 int FI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2308 SDValue FIPtr = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2309 Chain = DAG.getStore(Chain, dl: DL, Val: Entry.Node, Ptr: FIPtr, PtrInfo: MachinePointerInfo(),
2310 Alignment: Align(8));
2311
2312 Entry.Node = FIPtr;
2313 Entry.Ty = PointerType::getUnqual(C&: ArgTy->getContext());
2314 }
2315 Args.push_back(x: Entry);
2316 return Chain;
2317}
2318
2319SDValue
2320SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2321 const char *LibFuncName,
2322 unsigned numArgs) const {
2323
2324 ArgListTy Args;
2325
2326 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2327 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2328
2329 SDValue Callee = DAG.getExternalSymbol(Sym: LibFuncName, VT: PtrVT);
2330 Type *RetTy = Op.getValueType().getTypeForEVT(Context&: *DAG.getContext());
2331 Type *RetTyABI = RetTy;
2332 SDValue Chain = DAG.getEntryNode();
2333 SDValue RetPtr;
2334
2335 if (RetTy->isFP128Ty()) {
2336 // Create a Stack Object to receive the return value of type f128.
2337 ArgListEntry Entry;
2338 int RetFI = MFI.CreateStackObject(Size: 16, Alignment: Align(8), isSpillSlot: false);
2339 RetPtr = DAG.getFrameIndex(FI: RetFI, VT: PtrVT);
2340 Entry.Node = RetPtr;
2341 Entry.Ty = PointerType::getUnqual(C&: RetTy->getContext());
2342 if (!Subtarget->is64Bit()) {
2343 Entry.IsSRet = true;
2344 Entry.IndirectType = RetTy;
2345 }
2346 Entry.IsReturned = false;
2347 Args.push_back(x: Entry);
2348 RetTyABI = Type::getVoidTy(C&: *DAG.getContext());
2349 }
2350
2351 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2352 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2353 Chain = LowerF128_LibCallArg(Chain, Args, Arg: Op.getOperand(i), DL: SDLoc(Op), DAG);
2354 }
2355 TargetLowering::CallLoweringInfo CLI(DAG);
2356 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2357 .setCallee(CC: CallingConv::C, ResultType: RetTyABI, Target: Callee, ArgsList: std::move(Args));
2358
2359 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2360
2361 // chain is in second result.
2362 if (RetTyABI == RetTy)
2363 return CallInfo.first;
2364
2365 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2366
2367 Chain = CallInfo.second;
2368
2369 // Load RetPtr to get the return value.
2370 return DAG.getLoad(VT: Op.getValueType(), dl: SDLoc(Op), Chain, Ptr: RetPtr,
2371 PtrInfo: MachinePointerInfo(), Alignment: Align(8));
2372}
2373
2374SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2375 unsigned &SPCC, const SDLoc &DL,
2376 SelectionDAG &DAG) const {
2377
2378 const char *LibCall = nullptr;
2379 bool is64Bit = Subtarget->is64Bit();
2380 switch(SPCC) {
2381 default: llvm_unreachable("Unhandled conditional code!");
2382 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2383 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2384 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2385 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2386 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2387 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2388 case SPCC::FCC_UL :
2389 case SPCC::FCC_ULE:
2390 case SPCC::FCC_UG :
2391 case SPCC::FCC_UGE:
2392 case SPCC::FCC_U :
2393 case SPCC::FCC_O :
2394 case SPCC::FCC_LG :
2395 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2396 }
2397
2398 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2399 SDValue Callee = DAG.getExternalSymbol(Sym: LibCall, VT: PtrVT);
2400 Type *RetTy = Type::getInt32Ty(C&: *DAG.getContext());
2401 ArgListTy Args;
2402 SDValue Chain = DAG.getEntryNode();
2403 Chain = LowerF128_LibCallArg(Chain, Args, Arg: LHS, DL, DAG);
2404 Chain = LowerF128_LibCallArg(Chain, Args, Arg: RHS, DL, DAG);
2405
2406 TargetLowering::CallLoweringInfo CLI(DAG);
2407 CLI.setDebugLoc(DL).setChain(Chain)
2408 .setCallee(CC: CallingConv::C, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args));
2409
2410 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2411
2412 // result is in first, and chain is in second result.
2413 SDValue Result = CallInfo.first;
2414
2415 switch(SPCC) {
2416 default: {
2417 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2418 SPCC = SPCC::ICC_NE;
2419 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2420 }
2421 case SPCC::FCC_UL : {
2422 SDValue Mask = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2423 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2424 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2425 SPCC = SPCC::ICC_NE;
2426 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2427 }
2428 case SPCC::FCC_ULE: {
2429 SDValue RHS = DAG.getConstant(Val: 2, DL, VT: Result.getValueType());
2430 SPCC = SPCC::ICC_NE;
2431 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2432 }
2433 case SPCC::FCC_UG : {
2434 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2435 SPCC = SPCC::ICC_G;
2436 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2437 }
2438 case SPCC::FCC_UGE: {
2439 SDValue RHS = DAG.getConstant(Val: 1, DL, VT: Result.getValueType());
2440 SPCC = SPCC::ICC_NE;
2441 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2442 }
2443
2444 case SPCC::FCC_U : {
2445 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2446 SPCC = SPCC::ICC_E;
2447 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2448 }
2449 case SPCC::FCC_O : {
2450 SDValue RHS = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2451 SPCC = SPCC::ICC_NE;
2452 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2453 }
2454 case SPCC::FCC_LG : {
2455 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2456 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2457 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2458 SPCC = SPCC::ICC_NE;
2459 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2460 }
2461 case SPCC::FCC_UE : {
2462 SDValue Mask = DAG.getConstant(Val: 3, DL, VT: Result.getValueType());
2463 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: Result.getValueType(), N1: Result, N2: Mask);
2464 SDValue RHS = DAG.getConstant(Val: 0, DL, VT: Result.getValueType());
2465 SPCC = SPCC::ICC_E;
2466 return DAG.getNode(Opcode: SPISD::CMPICC, DL, VT: MVT::Glue, N1: Result, N2: RHS);
2467 }
2468 }
2469}
2470
2471static SDValue
2472LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2473 const SparcTargetLowering &TLI) {
2474
2475 if (Op.getOperand(i: 0).getValueType() == MVT::f64)
2476 return TLI.LowerF128Op(Op, DAG,
2477 LibFuncName: TLI.getLibcallName(Call: RTLIB::FPEXT_F64_F128), numArgs: 1);
2478
2479 if (Op.getOperand(i: 0).getValueType() == MVT::f32)
2480 return TLI.LowerF128Op(Op, DAG,
2481 LibFuncName: TLI.getLibcallName(Call: RTLIB::FPEXT_F32_F128), numArgs: 1);
2482
2483 llvm_unreachable("fpextend with non-float operand!");
2484 return SDValue();
2485}
2486
2487static SDValue
2488LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2489 const SparcTargetLowering &TLI) {
2490 // FP_ROUND on f64 and f32 are legal.
2491 if (Op.getOperand(i: 0).getValueType() != MVT::f128)
2492 return Op;
2493
2494 if (Op.getValueType() == MVT::f64)
2495 return TLI.LowerF128Op(Op, DAG,
2496 LibFuncName: TLI.getLibcallName(Call: RTLIB::FPROUND_F128_F64), numArgs: 1);
2497 if (Op.getValueType() == MVT::f32)
2498 return TLI.LowerF128Op(Op, DAG,
2499 LibFuncName: TLI.getLibcallName(Call: RTLIB::FPROUND_F128_F32), numArgs: 1);
2500
2501 llvm_unreachable("fpround to non-float!");
2502 return SDValue();
2503}
2504
2505static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2506 const SparcTargetLowering &TLI,
2507 bool hasHardQuad) {
2508 SDLoc dl(Op);
2509 EVT VT = Op.getValueType();
2510 assert(VT == MVT::i32 || VT == MVT::i64);
2511
2512 // Expand f128 operations to fp128 abi calls.
2513 if (Op.getOperand(i: 0).getValueType() == MVT::f128
2514 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2515 const char *libName = TLI.getLibcallName(Call: VT == MVT::i32
2516 ? RTLIB::FPTOSINT_F128_I32
2517 : RTLIB::FPTOSINT_F128_I64);
2518 return TLI.LowerF128Op(Op, DAG, LibFuncName: libName, numArgs: 1);
2519 }
2520
2521 // Expand if the resulting type is illegal.
2522 if (!TLI.isTypeLegal(VT))
2523 return SDValue();
2524
2525 // Otherwise, Convert the fp value to integer in an FP register.
2526 if (VT == MVT::i32)
2527 Op = DAG.getNode(Opcode: SPISD::FTOI, DL: dl, VT: MVT::f32, Operand: Op.getOperand(i: 0));
2528 else
2529 Op = DAG.getNode(Opcode: SPISD::FTOX, DL: dl, VT: MVT::f64, Operand: Op.getOperand(i: 0));
2530
2531 return DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Op);
2532}
2533
2534static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2535 const SparcTargetLowering &TLI,
2536 bool hasHardQuad) {
2537 SDLoc dl(Op);
2538 EVT OpVT = Op.getOperand(i: 0).getValueType();
2539 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2540
2541 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2542
2543 // Expand f128 operations to fp128 ABI calls.
2544 if (Op.getValueType() == MVT::f128
2545 && (!hasHardQuad || !TLI.isTypeLegal(VT: OpVT))) {
2546 const char *libName = TLI.getLibcallName(Call: OpVT == MVT::i32
2547 ? RTLIB::SINTTOFP_I32_F128
2548 : RTLIB::SINTTOFP_I64_F128);
2549 return TLI.LowerF128Op(Op, DAG, LibFuncName: libName, numArgs: 1);
2550 }
2551
2552 // Expand if the operand type is illegal.
2553 if (!TLI.isTypeLegal(VT: OpVT))
2554 return SDValue();
2555
2556 // Otherwise, Convert the int value to FP in an FP register.
2557 SDValue Tmp = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: floatVT, Operand: Op.getOperand(i: 0));
2558 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2559 return DAG.getNode(Opcode: opcode, DL: dl, VT: Op.getValueType(), Operand: Tmp);
2560}
2561
2562static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2563 const SparcTargetLowering &TLI,
2564 bool hasHardQuad) {
2565 EVT VT = Op.getValueType();
2566
2567 // Expand if it does not involve f128 or the target has support for
2568 // quad floating point instructions and the resulting type is legal.
2569 if (Op.getOperand(i: 0).getValueType() != MVT::f128 ||
2570 (hasHardQuad && TLI.isTypeLegal(VT)))
2571 return SDValue();
2572
2573 assert(VT == MVT::i32 || VT == MVT::i64);
2574
2575 return TLI.LowerF128Op(Op, DAG,
2576 LibFuncName: TLI.getLibcallName(Call: VT == MVT::i32
2577 ? RTLIB::FPTOUINT_F128_I32
2578 : RTLIB::FPTOUINT_F128_I64),
2579 numArgs: 1);
2580}
2581
2582static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2583 const SparcTargetLowering &TLI,
2584 bool hasHardQuad) {
2585 EVT OpVT = Op.getOperand(i: 0).getValueType();
2586 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2587
2588 // Expand if it does not involve f128 or the target has support for
2589 // quad floating point instructions and the operand type is legal.
2590 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(VT: OpVT)))
2591 return SDValue();
2592
2593 return TLI.LowerF128Op(Op, DAG,
2594 LibFuncName: TLI.getLibcallName(Call: OpVT == MVT::i32
2595 ? RTLIB::UINTTOFP_I32_F128
2596 : RTLIB::UINTTOFP_I64_F128),
2597 numArgs: 1);
2598}
2599
2600static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2601 const SparcTargetLowering &TLI, bool hasHardQuad,
2602 bool isV9, bool is64Bit) {
2603 SDValue Chain = Op.getOperand(i: 0);
2604 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
2605 SDValue LHS = Op.getOperand(i: 2);
2606 SDValue RHS = Op.getOperand(i: 3);
2607 SDValue Dest = Op.getOperand(i: 4);
2608 SDLoc dl(Op);
2609 unsigned Opc, SPCC = ~0U;
2610
2611 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2612 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2613 LookThroughSetCC(LHS, RHS, CC, SPCC);
2614 assert(LHS.getValueType() == RHS.getValueType());
2615
2616 // Get the condition flag.
2617 SDValue CompareFlag;
2618 if (LHS.getValueType().isInteger()) {
2619 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2620 // and the RHS is zero we might be able to use a specialized branch.
2621 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2622 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC))
2623 return DAG.getNode(Opcode: SPISD::BR_REG, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2624 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32),
2625 N4: LHS);
2626
2627 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2628 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2629 if (isV9)
2630 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2631 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2632 else
2633 // Non-v9 targets don't have xcc.
2634 Opc = SPISD::BRICC;
2635 } else {
2636 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2637 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2638 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2639 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2640 } else {
2641 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2642 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2643 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2644 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2645 }
2646 }
2647 return DAG.getNode(Opcode: Opc, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest,
2648 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2649}
2650
2651static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2652 const SparcTargetLowering &TLI, bool hasHardQuad,
2653 bool isV9, bool is64Bit) {
2654 SDValue LHS = Op.getOperand(i: 0);
2655 SDValue RHS = Op.getOperand(i: 1);
2656 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
2657 SDValue TrueVal = Op.getOperand(i: 2);
2658 SDValue FalseVal = Op.getOperand(i: 3);
2659 SDLoc dl(Op);
2660 unsigned Opc, SPCC = ~0U;
2661
2662 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2663 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2664 LookThroughSetCC(LHS, RHS, CC, SPCC);
2665 assert(LHS.getValueType() == RHS.getValueType());
2666
2667 SDValue CompareFlag;
2668 if (LHS.getValueType().isInteger()) {
2669 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2670 // and the RHS is zero we might be able to use a specialized select.
2671 // All SELECT_CC between any two scalar integer types are eligible for
2672 // lowering to specialized instructions. Additionally, f32 and f64 types
2673 // are also eligible, but for f128 we can only use the specialized
2674 // instruction when we have hardquad.
2675 EVT ValType = TrueVal.getValueType();
2676 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2677 ValType == MVT::f64 ||
2678 (ValType == MVT::f128 && hasHardQuad);
2679 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2680 isNullConstant(V: RHS) && !ISD::isUnsignedIntSetCC(Code: CC) && IsEligibleType)
2681 return DAG.getNode(
2682 Opcode: SPISD::SELECT_REG, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2683 N3: DAG.getConstant(Val: intCondCCodeToRcond(CC), DL: dl, VT: MVT::i32), N4: LHS);
2684
2685 CompareFlag = DAG.getNode(Opcode: SPISD::CMPICC, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2686 Opc = LHS.getValueType() == MVT::i32 ?
2687 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2688 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2689 } else {
2690 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2691 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2692 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, DL: dl, DAG);
2693 Opc = SPISD::SELECT_ICC;
2694 } else {
2695 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2696 CompareFlag = DAG.getNode(Opcode: CmpOpc, DL: dl, VT: MVT::Glue, N1: LHS, N2: RHS);
2697 Opc = SPISD::SELECT_FCC;
2698 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2699 }
2700 }
2701 return DAG.getNode(Opcode: Opc, DL: dl, VT: TrueVal.getValueType(), N1: TrueVal, N2: FalseVal,
2702 N3: DAG.getConstant(Val: SPCC, DL: dl, VT: MVT::i32), N4: CompareFlag);
2703}
2704
2705static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2706 const SparcTargetLowering &TLI) {
2707 MachineFunction &MF = DAG.getMachineFunction();
2708 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2709 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2710
2711 // Need frame address to find the address of VarArgsFrameIndex.
2712 MF.getFrameInfo().setFrameAddressIsTaken(true);
2713
2714 // vastart just stores the address of the VarArgsFrameIndex slot into the
2715 // memory location argument.
2716 SDLoc DL(Op);
2717 SDValue Offset =
2718 DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: DAG.getRegister(Reg: SP::I6, VT: PtrVT),
2719 N2: DAG.getIntPtrConstant(Val: FuncInfo->getVarArgsFrameOffset(), DL));
2720 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
2721 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: Offset, Ptr: Op.getOperand(i: 1),
2722 PtrInfo: MachinePointerInfo(SV));
2723}
2724
2725static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2726 SDNode *Node = Op.getNode();
2727 EVT VT = Node->getValueType(ResNo: 0);
2728 SDValue InChain = Node->getOperand(Num: 0);
2729 SDValue VAListPtr = Node->getOperand(Num: 1);
2730 EVT PtrVT = VAListPtr.getValueType();
2731 const Value *SV = cast<SrcValueSDNode>(Val: Node->getOperand(Num: 2))->getValue();
2732 SDLoc DL(Node);
2733 SDValue VAList =
2734 DAG.getLoad(VT: PtrVT, dl: DL, Chain: InChain, Ptr: VAListPtr, PtrInfo: MachinePointerInfo(SV));
2735 // Increment the pointer, VAList, to the next vaarg.
2736 SDValue NextPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: VAList,
2737 N2: DAG.getIntPtrConstant(Val: VT.getSizeInBits()/8,
2738 DL));
2739 // Store the incremented VAList to the legalized pointer.
2740 InChain = DAG.getStore(Chain: VAList.getValue(R: 1), dl: DL, Val: NextPtr, Ptr: VAListPtr,
2741 PtrInfo: MachinePointerInfo(SV));
2742 // Load the actual argument out of the pointer VAList.
2743 // We can't count on greater alignment than the word size.
2744 return DAG.getLoad(
2745 VT, dl: DL, Chain: InChain, Ptr: VAList, PtrInfo: MachinePointerInfo(),
2746 Alignment: Align(std::min(a: PtrVT.getFixedSizeInBits(), b: VT.getFixedSizeInBits()) / 8));
2747}
2748
2749static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2750 const SparcSubtarget *Subtarget) {
2751 SDValue Chain = Op.getOperand(i: 0);
2752 SDValue Size = Op.getOperand(i: 1);
2753 SDValue Alignment = Op.getOperand(i: 2);
2754 MaybeAlign MaybeAlignment =
2755 cast<ConstantSDNode>(Val&: Alignment)->getMaybeAlignValue();
2756 EVT VT = Size->getValueType(ResNo: 0);
2757 SDLoc dl(Op);
2758
2759 unsigned SPReg = SP::O6;
2760 SDValue SP = DAG.getCopyFromReg(Chain, dl, Reg: SPReg, VT);
2761
2762 // The resultant pointer needs to be above the register spill area
2763 // at the bottom of the stack.
2764 unsigned regSpillArea;
2765 if (Subtarget->is64Bit()) {
2766 regSpillArea = 128;
2767 } else {
2768 // On Sparc32, the size of the spill area is 92. Unfortunately,
2769 // that's only 4-byte aligned, not 8-byte aligned (the stack
2770 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2771 // aligned dynamic allocation, we actually need to add 96 to the
2772 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2773
2774 // That also means adding 4 to the size of the allocation --
2775 // before applying the 8-byte rounding. Unfortunately, we the
2776 // value we get here has already had rounding applied. So, we need
2777 // to add 8, instead, wasting a bit more memory.
2778
2779 // Further, this only actually needs to be done if the required
2780 // alignment is > 4, but, we've lost that info by this point, too,
2781 // so we always apply it.
2782
2783 // (An alternative approach would be to always reserve 96 bytes
2784 // instead of the required 92, but then we'd waste 4 extra bytes
2785 // in every frame, not just those with dynamic stack allocations)
2786
2787 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2788
2789 Size = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Size,
2790 N2: DAG.getConstant(Val: 8, DL: dl, VT));
2791 regSpillArea = 96;
2792 }
2793
2794 int64_t Bias = Subtarget->getStackPointerBias();
2795
2796 // Debias and increment SP past the reserved spill area.
2797 // We need the SP to point to the first usable region before calculating
2798 // anything to prevent any of the pointers from becoming out of alignment when
2799 // we rebias the SP later on.
2800 SDValue StartOfUsableStack = DAG.getNode(
2801 Opcode: ISD::ADD, DL: dl, VT, N1: SP, N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2802 SDValue AllocatedPtr =
2803 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: StartOfUsableStack, N2: Size);
2804
2805 bool IsOveraligned = MaybeAlignment.has_value();
2806 SDValue AlignedPtr =
2807 IsOveraligned
2808 ? DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: AllocatedPtr,
2809 N2: DAG.getSignedConstant(Val: -MaybeAlignment->value(), DL: dl, VT))
2810 : AllocatedPtr;
2811
2812 // Now that we are done, restore the bias and reserved spill area.
2813 SDValue NewSP = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: AlignedPtr,
2814 N2: DAG.getConstant(Val: regSpillArea + Bias, DL: dl, VT));
2815 Chain = DAG.getCopyToReg(Chain: SP.getValue(R: 1), dl, Reg: SPReg, N: NewSP);
2816 SDValue Ops[2] = {AlignedPtr, Chain};
2817 return DAG.getMergeValues(Ops, dl);
2818}
2819
2820
2821static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2822 SDLoc dl(Op);
2823 SDValue Chain = DAG.getNode(Opcode: SPISD::FLUSHW,
2824 DL: dl, VT: MVT::Other, Operand: DAG.getEntryNode());
2825 return Chain;
2826}
2827
2828static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2829 const SparcSubtarget *Subtarget,
2830 bool AlwaysFlush = false) {
2831 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2832 MFI.setFrameAddressIsTaken(true);
2833
2834 EVT VT = Op.getValueType();
2835 SDLoc dl(Op);
2836 unsigned FrameReg = SP::I6;
2837 unsigned stackBias = Subtarget->getStackPointerBias();
2838
2839 SDValue FrameAddr;
2840 SDValue Chain;
2841
2842 // flush first to make sure the windowed registers' values are in stack
2843 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2844
2845 FrameAddr = DAG.getCopyFromReg(Chain, dl, Reg: FrameReg, VT);
2846
2847 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2848
2849 while (depth--) {
2850 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2851 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2852 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, PtrInfo: MachinePointerInfo());
2853 }
2854 if (Subtarget->is64Bit())
2855 FrameAddr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: FrameAddr,
2856 N2: DAG.getIntPtrConstant(Val: stackBias, DL: dl));
2857 return FrameAddr;
2858}
2859
2860
2861static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2862 const SparcSubtarget *Subtarget) {
2863
2864 uint64_t depth = Op.getConstantOperandVal(i: 0);
2865
2866 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2867
2868}
2869
2870static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2871 const SparcTargetLowering &TLI,
2872 const SparcSubtarget *Subtarget) {
2873 MachineFunction &MF = DAG.getMachineFunction();
2874 MachineFrameInfo &MFI = MF.getFrameInfo();
2875 MFI.setReturnAddressIsTaken(true);
2876
2877 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2878 return SDValue();
2879
2880 EVT VT = Op.getValueType();
2881 SDLoc dl(Op);
2882 uint64_t depth = Op.getConstantOperandVal(i: 0);
2883
2884 SDValue RetAddr;
2885 if (depth == 0) {
2886 auto PtrVT = TLI.getPointerTy(DL: DAG.getDataLayout());
2887 Register RetReg = MF.addLiveIn(PReg: SP::I7, RC: TLI.getRegClassFor(VT: PtrVT));
2888 RetAddr = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl, Reg: RetReg, VT);
2889 return RetAddr;
2890 }
2891
2892 // Need frame address to find return address of the caller.
2893 SDValue FrameAddr = getFRAMEADDR(depth: depth - 1, Op, DAG, Subtarget, AlwaysFlush: true);
2894
2895 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2896 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD,
2897 DL: dl, VT,
2898 N1: FrameAddr,
2899 N2: DAG.getIntPtrConstant(Val: Offset, DL: dl));
2900 RetAddr = DAG.getLoad(VT, dl, Chain: DAG.getEntryNode(), Ptr, PtrInfo: MachinePointerInfo());
2901
2902 return RetAddr;
2903}
2904
2905static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2906 unsigned opcode) {
2907 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2908 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2909
2910 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2911 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2912 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2913
2914 // Note: in little-endian, the floating-point value is stored in the
2915 // registers are in the opposite order, so the subreg with the sign
2916 // bit is the highest-numbered (odd), rather than the
2917 // lowest-numbered (even).
2918
2919 SDValue Hi32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f32,
2920 Operand: SrcReg64);
2921 SDValue Lo32 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f32,
2922 Operand: SrcReg64);
2923
2924 if (DAG.getDataLayout().isLittleEndian())
2925 Lo32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Lo32);
2926 else
2927 Hi32 = DAG.getNode(Opcode: opcode, DL: dl, VT: MVT::f32, Operand: Hi32);
2928
2929 SDValue DstReg64 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2930 dl, VT: MVT::f64), 0);
2931 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even, DL: dl, VT: MVT::f64,
2932 Operand: DstReg64, Subreg: Hi32);
2933 DstReg64 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd, DL: dl, VT: MVT::f64,
2934 Operand: DstReg64, Subreg: Lo32);
2935 return DstReg64;
2936}
2937
2938// Lower a f128 load into two f64 loads.
2939static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2940{
2941 SDLoc dl(Op);
2942 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
2943 assert(LdNode->getOffset().isUndef() && "Unexpected node type");
2944
2945 Align Alignment = commonAlignment(A: LdNode->getBaseAlign(), Offset: 8);
2946
2947 SDValue Hi64 =
2948 DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LdNode->getBasePtr(),
2949 PtrInfo: LdNode->getPointerInfo(), Alignment);
2950 EVT addrVT = LdNode->getBasePtr().getValueType();
2951 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
2952 N1: LdNode->getBasePtr(),
2953 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
2954 SDValue Lo64 = DAG.getLoad(VT: MVT::f64, dl, Chain: LdNode->getChain(), Ptr: LoPtr,
2955 PtrInfo: LdNode->getPointerInfo().getWithOffset(O: 8),
2956 Alignment);
2957
2958 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
2959 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
2960
2961 SDNode *InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
2962 dl, VT: MVT::f128);
2963 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2964 VT: MVT::f128,
2965 Op1: SDValue(InFP128, 0),
2966 Op2: Hi64,
2967 Op3: SubRegEven);
2968 InFP128 = DAG.getMachineNode(Opcode: TargetOpcode::INSERT_SUBREG, dl,
2969 VT: MVT::f128,
2970 Op1: SDValue(InFP128, 0),
2971 Op2: Lo64,
2972 Op3: SubRegOdd);
2973 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2974 SDValue(Lo64.getNode(), 1) };
2975 SDValue OutChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
2976 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2977 return DAG.getMergeValues(Ops, dl);
2978}
2979
2980static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
2981{
2982 LoadSDNode *LdNode = cast<LoadSDNode>(Val: Op.getNode());
2983
2984 EVT MemVT = LdNode->getMemoryVT();
2985 if (MemVT == MVT::f128)
2986 return LowerF128Load(Op, DAG);
2987
2988 return Op;
2989}
2990
2991// Lower a f128 store into two f64 stores.
2992static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2993 SDLoc dl(Op);
2994 StoreSDNode *StNode = cast<StoreSDNode>(Val: Op.getNode());
2995 assert(StNode->getOffset().isUndef() && "Unexpected node type");
2996
2997 SDValue SubRegEven = DAG.getTargetConstant(Val: SP::sub_even64, DL: dl, VT: MVT::i32);
2998 SDValue SubRegOdd = DAG.getTargetConstant(Val: SP::sub_odd64, DL: dl, VT: MVT::i32);
2999
3000 SDNode *Hi64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3001 dl,
3002 VT: MVT::f64,
3003 Op1: StNode->getValue(),
3004 Op2: SubRegEven);
3005 SDNode *Lo64 = DAG.getMachineNode(Opcode: TargetOpcode::EXTRACT_SUBREG,
3006 dl,
3007 VT: MVT::f64,
3008 Op1: StNode->getValue(),
3009 Op2: SubRegOdd);
3010
3011 Align Alignment = commonAlignment(A: StNode->getBaseAlign(), Offset: 8);
3012
3013 SDValue OutChains[2];
3014 OutChains[0] =
3015 DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Hi64, 0),
3016 Ptr: StNode->getBasePtr(), PtrInfo: StNode->getPointerInfo(),
3017 Alignment);
3018 EVT addrVT = StNode->getBasePtr().getValueType();
3019 SDValue LoPtr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: addrVT,
3020 N1: StNode->getBasePtr(),
3021 N2: DAG.getConstant(Val: 8, DL: dl, VT: addrVT));
3022 OutChains[1] = DAG.getStore(Chain: StNode->getChain(), dl, Val: SDValue(Lo64, 0), Ptr: LoPtr,
3023 PtrInfo: StNode->getPointerInfo().getWithOffset(O: 8),
3024 Alignment);
3025 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: OutChains);
3026}
3027
3028static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
3029{
3030 SDLoc dl(Op);
3031 StoreSDNode *St = cast<StoreSDNode>(Val: Op.getNode());
3032
3033 EVT MemVT = St->getMemoryVT();
3034 if (MemVT == MVT::f128)
3035 return LowerF128Store(Op, DAG);
3036
3037 if (MemVT == MVT::i64) {
3038 // Custom handling for i64 stores: turn it into a bitcast and a
3039 // v2i32 store.
3040 SDValue Val = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::v2i32, Operand: St->getValue());
3041 SDValue Chain = DAG.getStore(
3042 Chain: St->getChain(), dl, Val, Ptr: St->getBasePtr(), PtrInfo: St->getPointerInfo(),
3043 Alignment: St->getBaseAlign(), MMOFlags: St->getMemOperand()->getFlags(), AAInfo: St->getAAInfo());
3044 return Chain;
3045 }
3046
3047 return SDValue();
3048}
3049
3050static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
3051 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3052 && "invalid opcode");
3053
3054 SDLoc dl(Op);
3055
3056 if (Op.getValueType() == MVT::f64)
3057 return LowerF64Op(SrcReg64: Op.getOperand(i: 0), dl, DAG, opcode: Op.getOpcode());
3058 if (Op.getValueType() != MVT::f128)
3059 return Op;
3060
3061 // Lower fabs/fneg on f128 to fabs/fneg on f64
3062 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
3063 // (As with LowerF64Op, on little-endian, we need to negate the odd
3064 // subreg)
3065
3066 SDValue SrcReg128 = Op.getOperand(i: 0);
3067 SDValue Hi64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f64,
3068 Operand: SrcReg128);
3069 SDValue Lo64 = DAG.getTargetExtractSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f64,
3070 Operand: SrcReg128);
3071
3072 if (DAG.getDataLayout().isLittleEndian()) {
3073 if (isV9)
3074 Lo64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Lo64);
3075 else
3076 Lo64 = LowerF64Op(SrcReg64: Lo64, dl, DAG, opcode: Op.getOpcode());
3077 } else {
3078 if (isV9)
3079 Hi64 = DAG.getNode(Opcode: Op.getOpcode(), DL: dl, VT: MVT::f64, Operand: Hi64);
3080 else
3081 Hi64 = LowerF64Op(SrcReg64: Hi64, dl, DAG, opcode: Op.getOpcode());
3082 }
3083
3084 SDValue DstReg128 = SDValue(DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF,
3085 dl, VT: MVT::f128), 0);
3086 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_even64, DL: dl, VT: MVT::f128,
3087 Operand: DstReg128, Subreg: Hi64);
3088 DstReg128 = DAG.getTargetInsertSubreg(SRIdx: SP::sub_odd64, DL: dl, VT: MVT::f128,
3089 Operand: DstReg128, Subreg: Lo64);
3090 return DstReg128;
3091}
3092
3093static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
3094 if (isStrongerThanMonotonic(AO: cast<AtomicSDNode>(Val&: Op)->getSuccessOrdering())) {
3095 // Expand with a fence.
3096 return SDValue();
3097 }
3098
3099 // Monotonic load/stores are legal.
3100 return Op;
3101}
3102
3103SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3104 SelectionDAG &DAG) const {
3105 unsigned IntNo = Op.getConstantOperandVal(i: 0);
3106 switch (IntNo) {
3107 default: return SDValue(); // Don't custom lower most intrinsics.
3108 case Intrinsic::thread_pointer: {
3109 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
3110 return DAG.getRegister(Reg: SP::G7, VT: PtrVT);
3111 }
3112 }
3113}
3114
3115SDValue SparcTargetLowering::
3116LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3117
3118 bool hasHardQuad = Subtarget->hasHardQuad();
3119 bool isV9 = Subtarget->isV9();
3120 bool is64Bit = Subtarget->is64Bit();
3121
3122 switch (Op.getOpcode()) {
3123 default: llvm_unreachable("Should not custom lower this!");
3124
3125 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, TLI: *this,
3126 Subtarget);
3127 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3128 Subtarget);
3129 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3130 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3131 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3132 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3133 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, TLI: *this,
3134 hasHardQuad);
3135 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, TLI: *this,
3136 hasHardQuad);
3137 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, TLI: *this,
3138 hasHardQuad);
3139 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, TLI: *this,
3140 hasHardQuad);
3141 case ISD::BR_CC:
3142 return LowerBR_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3143 case ISD::SELECT_CC:
3144 return LowerSELECT_CC(Op, DAG, TLI: *this, hasHardQuad, isV9, is64Bit);
3145 case ISD::VASTART: return LowerVASTART(Op, DAG, TLI: *this);
3146 case ISD::VAARG: return LowerVAARG(Op, DAG);
3147 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3148 Subtarget);
3149
3150 case ISD::LOAD: return LowerLOAD(Op, DAG);
3151 case ISD::STORE: return LowerSTORE(Op, DAG);
3152 case ISD::FADD: return LowerF128Op(Op, DAG,
3153 LibFuncName: getLibcallName(Call: RTLIB::ADD_F128), numArgs: 2);
3154 case ISD::FSUB: return LowerF128Op(Op, DAG,
3155 LibFuncName: getLibcallName(Call: RTLIB::SUB_F128), numArgs: 2);
3156 case ISD::FMUL: return LowerF128Op(Op, DAG,
3157 LibFuncName: getLibcallName(Call: RTLIB::MUL_F128), numArgs: 2);
3158 case ISD::FDIV: return LowerF128Op(Op, DAG,
3159 LibFuncName: getLibcallName(Call: RTLIB::DIV_F128), numArgs: 2);
3160 case ISD::FSQRT: return LowerF128Op(Op, DAG,
3161 LibFuncName: getLibcallName(Call: RTLIB::SQRT_F128),numArgs: 1);
3162 case ISD::FABS:
3163 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3164 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, TLI: *this);
3165 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, TLI: *this);
3166 case ISD::ATOMIC_LOAD:
3167 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3168 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3169 }
3170}
3171
3172SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
3173 const SDLoc &DL,
3174 SelectionDAG &DAG) const {
3175 APInt V = C->getValueAPF().bitcastToAPInt();
3176 SDValue Lo = DAG.getConstant(Val: V.zextOrTrunc(width: 32), DL, VT: MVT::i32);
3177 SDValue Hi = DAG.getConstant(Val: V.lshr(shiftAmt: 32).zextOrTrunc(width: 32), DL, VT: MVT::i32);
3178 if (DAG.getDataLayout().isLittleEndian())
3179 std::swap(a&: Lo, b&: Hi);
3180 return DAG.getBuildVector(VT: MVT::v2i32, DL, Ops: {Hi, Lo});
3181}
3182
3183SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
3184 DAGCombinerInfo &DCI) const {
3185 SDLoc dl(N);
3186 SDValue Src = N->getOperand(Num: 0);
3187
3188 if (isa<ConstantFPSDNode>(Val: Src) && N->getSimpleValueType(ResNo: 0) == MVT::v2i32 &&
3189 Src.getSimpleValueType() == MVT::f64)
3190 return bitcastConstantFPToInt(C: cast<ConstantFPSDNode>(Val&: Src), DL: dl, DAG&: DCI.DAG);
3191
3192 return SDValue();
3193}
3194
3195SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N,
3196 DAGCombinerInfo &DCI) const {
3197 switch (N->getOpcode()) {
3198 default:
3199 break;
3200 case ISD::BITCAST:
3201 return PerformBITCASTCombine(N, DCI);
3202 }
3203 return SDValue();
3204}
3205
3206MachineBasicBlock *
3207SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3208 MachineBasicBlock *BB) const {
3209 switch (MI.getOpcode()) {
3210 default: llvm_unreachable("Unknown SELECT_CC!");
3211 case SP::SELECT_CC_Int_ICC:
3212 case SP::SELECT_CC_FP_ICC:
3213 case SP::SELECT_CC_DFP_ICC:
3214 case SP::SELECT_CC_QFP_ICC:
3215 if (Subtarget->isV9())
3216 return expandSelectCC(MI, BB, BROpcode: SP::BPICC);
3217 return expandSelectCC(MI, BB, BROpcode: SP::BCOND);
3218 case SP::SELECT_CC_Int_XCC:
3219 case SP::SELECT_CC_FP_XCC:
3220 case SP::SELECT_CC_DFP_XCC:
3221 case SP::SELECT_CC_QFP_XCC:
3222 return expandSelectCC(MI, BB, BROpcode: SP::BPXCC);
3223 case SP::SELECT_CC_Int_FCC:
3224 case SP::SELECT_CC_FP_FCC:
3225 case SP::SELECT_CC_DFP_FCC:
3226 case SP::SELECT_CC_QFP_FCC:
3227 if (Subtarget->isV9())
3228 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND_V9);
3229 return expandSelectCC(MI, BB, BROpcode: SP::FBCOND);
3230 }
3231}
3232
3233MachineBasicBlock *
3234SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3235 unsigned BROpcode) const {
3236 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3237 DebugLoc dl = MI.getDebugLoc();
3238 unsigned CC = (SPCC::CondCodes)MI.getOperand(i: 3).getImm();
3239
3240 // To "insert" a SELECT_CC instruction, we actually have to insert the
3241 // triangle control-flow pattern. The incoming instruction knows the
3242 // destination vreg to set, the condition code register to branch on, the
3243 // true/false values to select between, and the condition code for the branch.
3244 //
3245 // We produce the following control flow:
3246 // ThisMBB
3247 // | \
3248 // | IfFalseMBB
3249 // | /
3250 // SinkMBB
3251 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3252 MachineFunction::iterator It = ++BB->getIterator();
3253
3254 MachineBasicBlock *ThisMBB = BB;
3255 MachineFunction *F = BB->getParent();
3256 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3257 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
3258 F->insert(MBBI: It, MBB: IfFalseMBB);
3259 F->insert(MBBI: It, MBB: SinkMBB);
3260
3261 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3262 SinkMBB->splice(Where: SinkMBB->begin(), Other: ThisMBB,
3263 From: std::next(x: MachineBasicBlock::iterator(MI)), To: ThisMBB->end());
3264 SinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: ThisMBB);
3265
3266 // Set the new successors for ThisMBB.
3267 ThisMBB->addSuccessor(Succ: IfFalseMBB);
3268 ThisMBB->addSuccessor(Succ: SinkMBB);
3269
3270 BuildMI(BB: ThisMBB, MIMD: dl, MCID: TII.get(Opcode: BROpcode))
3271 .addMBB(MBB: SinkMBB)
3272 .addImm(Val: CC);
3273
3274 // IfFalseMBB just falls through to SinkMBB.
3275 IfFalseMBB->addSuccessor(Succ: SinkMBB);
3276
3277 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3278 BuildMI(BB&: *SinkMBB, I: SinkMBB->begin(), MIMD: dl, MCID: TII.get(Opcode: SP::PHI),
3279 DestReg: MI.getOperand(i: 0).getReg())
3280 .addReg(RegNo: MI.getOperand(i: 1).getReg())
3281 .addMBB(MBB: ThisMBB)
3282 .addReg(RegNo: MI.getOperand(i: 2).getReg())
3283 .addMBB(MBB: IfFalseMBB);
3284
3285 MI.eraseFromParent(); // The pseudo instruction is gone now.
3286 return SinkMBB;
3287}
3288
3289//===----------------------------------------------------------------------===//
3290// Sparc Inline Assembly Support
3291//===----------------------------------------------------------------------===//
3292
3293/// getConstraintType - Given a constraint letter, return the type of
3294/// constraint it is for this target.
3295SparcTargetLowering::ConstraintType
3296SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3297 if (Constraint.size() == 1) {
3298 switch (Constraint[0]) {
3299 default: break;
3300 case 'r':
3301 case 'f':
3302 case 'e':
3303 return C_RegisterClass;
3304 case 'I': // SIMM13
3305 return C_Immediate;
3306 }
3307 }
3308
3309 return TargetLowering::getConstraintType(Constraint);
3310}
3311
3312TargetLowering::ConstraintWeight SparcTargetLowering::
3313getSingleConstraintMatchWeight(AsmOperandInfo &info,
3314 const char *constraint) const {
3315 ConstraintWeight weight = CW_Invalid;
3316 Value *CallOperandVal = info.CallOperandVal;
3317 // If we don't have a value, we can't do a match,
3318 // but allow it at the lowest weight.
3319 if (!CallOperandVal)
3320 return CW_Default;
3321
3322 // Look at the constraint type.
3323 switch (*constraint) {
3324 default:
3325 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3326 break;
3327 case 'I': // SIMM13
3328 if (ConstantInt *C = dyn_cast<ConstantInt>(Val: info.CallOperandVal)) {
3329 if (isInt<13>(x: C->getSExtValue()))
3330 weight = CW_Constant;
3331 }
3332 break;
3333 }
3334 return weight;
3335}
3336
3337/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3338/// vector. If it is invalid, don't add anything to Ops.
3339void SparcTargetLowering::LowerAsmOperandForConstraint(
3340 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
3341 SelectionDAG &DAG) const {
3342 SDValue Result;
3343
3344 // Only support length 1 constraints for now.
3345 if (Constraint.size() > 1)
3346 return;
3347
3348 char ConstraintLetter = Constraint[0];
3349 switch (ConstraintLetter) {
3350 default: break;
3351 case 'I':
3352 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
3353 if (isInt<13>(x: C->getSExtValue())) {
3354 Result = DAG.getSignedTargetConstant(Val: C->getSExtValue(), DL: SDLoc(Op),
3355 VT: Op.getValueType());
3356 break;
3357 }
3358 return;
3359 }
3360 }
3361
3362 if (Result.getNode()) {
3363 Ops.push_back(x: Result);
3364 return;
3365 }
3366 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3367}
3368
3369std::pair<unsigned, const TargetRegisterClass *>
3370SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3371 StringRef Constraint,
3372 MVT VT) const {
3373 if (Constraint.empty())
3374 return std::make_pair(x: 0U, y: nullptr);
3375
3376 if (Constraint.size() == 1) {
3377 switch (Constraint[0]) {
3378 case 'r':
3379 if (VT == MVT::v2i32)
3380 return std::make_pair(x: 0U, y: &SP::IntPairRegClass);
3381 else if (Subtarget->is64Bit())
3382 return std::make_pair(x: 0U, y: &SP::I64RegsRegClass);
3383 else
3384 return std::make_pair(x: 0U, y: &SP::IntRegsRegClass);
3385 case 'f':
3386 if (VT == MVT::f32 || VT == MVT::i32)
3387 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3388 else if (VT == MVT::f64 || VT == MVT::i64)
3389 return std::make_pair(x: 0U, y: &SP::LowDFPRegsRegClass);
3390 else if (VT == MVT::f128)
3391 return std::make_pair(x: 0U, y: &SP::LowQFPRegsRegClass);
3392 // This will generate an error message
3393 return std::make_pair(x: 0U, y: nullptr);
3394 case 'e':
3395 if (VT == MVT::f32 || VT == MVT::i32)
3396 return std::make_pair(x: 0U, y: &SP::FPRegsRegClass);
3397 else if (VT == MVT::f64 || VT == MVT::i64 )
3398 return std::make_pair(x: 0U, y: &SP::DFPRegsRegClass);
3399 else if (VT == MVT::f128)
3400 return std::make_pair(x: 0U, y: &SP::QFPRegsRegClass);
3401 // This will generate an error message
3402 return std::make_pair(x: 0U, y: nullptr);
3403 }
3404 }
3405
3406 if (Constraint.front() != '{')
3407 return std::make_pair(x: 0U, y: nullptr);
3408
3409 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3410 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3411 if (RegName.empty())
3412 return std::make_pair(x: 0U, y: nullptr);
3413
3414 unsigned long long RegNo;
3415 // Handle numbered register aliases.
3416 if (RegName[0] == 'r' &&
3417 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3418 // r0-r7 -> g0-g7
3419 // r8-r15 -> o0-o7
3420 // r16-r23 -> l0-l7
3421 // r24-r31 -> i0-i7
3422 if (RegNo > 31)
3423 return std::make_pair(x: 0U, y: nullptr);
3424 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3425 char RegType = RegTypes[RegNo / 8];
3426 char RegIndex = '0' + (RegNo % 8);
3427 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3428 return getRegForInlineAsmConstraint(TRI, Constraint: Tmp, VT);
3429 }
3430
3431 // Rewrite the fN constraint according to the value type if needed.
3432 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3433 getAsUnsignedInteger(Str: RegName.begin() + 1, Radix: 10, Result&: RegNo)) {
3434 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3435 return getRegForInlineAsmConstraint(
3436 TRI, Constraint: StringRef("{d" + utostr(X: RegNo / 2) + "}"), VT);
3437 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3438 return getRegForInlineAsmConstraint(
3439 TRI, Constraint: StringRef("{q" + utostr(X: RegNo / 4) + "}"), VT);
3440 } else {
3441 return std::make_pair(x: 0U, y: nullptr);
3442 }
3443 }
3444
3445 auto ResultPair =
3446 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3447 if (!ResultPair.second)
3448 return std::make_pair(x: 0U, y: nullptr);
3449
3450 // Force the use of I64Regs over IntRegs for 64-bit values.
3451 if (Subtarget->is64Bit() && VT == MVT::i64) {
3452 assert(ResultPair.second == &SP::IntRegsRegClass &&
3453 "Unexpected register class");
3454 return std::make_pair(x&: ResultPair.first, y: &SP::I64RegsRegClass);
3455 }
3456
3457 return ResultPair;
3458}
3459
3460bool
3461SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3462 // The Sparc target isn't yet aware of offsets.
3463 return false;
3464}
3465
3466void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3467 SmallVectorImpl<SDValue>& Results,
3468 SelectionDAG &DAG) const {
3469
3470 SDLoc dl(N);
3471
3472 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3473
3474 switch (N->getOpcode()) {
3475 default:
3476 llvm_unreachable("Do not know how to custom type legalize this operation!");
3477
3478 case ISD::FP_TO_SINT:
3479 case ISD::FP_TO_UINT:
3480 // Custom lower only if it involves f128 or i64.
3481 if (N->getOperand(Num: 0).getValueType() != MVT::f128
3482 || N->getValueType(ResNo: 0) != MVT::i64)
3483 return;
3484 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3485 ? RTLIB::FPTOSINT_F128_I64
3486 : RTLIB::FPTOUINT_F128_I64);
3487
3488 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0),
3489 DAG,
3490 LibFuncName: getLibcallName(Call: libCall),
3491 numArgs: 1));
3492 return;
3493 case ISD::READCYCLECOUNTER: {
3494 assert(Subtarget->hasLeonCycleCounter());
3495 SDValue Lo = DAG.getCopyFromReg(Chain: N->getOperand(Num: 0), dl, Reg: SP::ASR23, VT: MVT::i32);
3496 SDValue Hi = DAG.getCopyFromReg(Chain: Lo, dl, Reg: SP::G0, VT: MVT::i32);
3497 SDValue Ops[] = { Lo, Hi };
3498 SDValue Pair = DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i64, Ops);
3499 Results.push_back(Elt: Pair);
3500 Results.push_back(Elt: N->getOperand(Num: 0));
3501 return;
3502 }
3503 case ISD::SINT_TO_FP:
3504 case ISD::UINT_TO_FP:
3505 // Custom lower only if it involves f128 or i64.
3506 if (N->getValueType(ResNo: 0) != MVT::f128
3507 || N->getOperand(Num: 0).getValueType() != MVT::i64)
3508 return;
3509
3510 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3511 ? RTLIB::SINTTOFP_I64_F128
3512 : RTLIB::UINTTOFP_I64_F128);
3513
3514 Results.push_back(Elt: LowerF128Op(Op: SDValue(N, 0),
3515 DAG,
3516 LibFuncName: getLibcallName(Call: libCall),
3517 numArgs: 1));
3518 return;
3519 case ISD::LOAD: {
3520 LoadSDNode *Ld = cast<LoadSDNode>(Val: N);
3521 // Custom handling only for i64: turn i64 load into a v2i32 load,
3522 // and a bitcast.
3523 if (Ld->getValueType(ResNo: 0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3524 return;
3525
3526 SDLoc dl(N);
3527 SDValue LoadRes = DAG.getExtLoad(
3528 ExtType: Ld->getExtensionType(), dl, VT: MVT::v2i32, Chain: Ld->getChain(),
3529 Ptr: Ld->getBasePtr(), PtrInfo: Ld->getPointerInfo(), MemVT: MVT::v2i32, Alignment: Ld->getBaseAlign(),
3530 MMOFlags: Ld->getMemOperand()->getFlags(), AAInfo: Ld->getAAInfo());
3531
3532 SDValue Res = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i64, Operand: LoadRes);
3533 Results.push_back(Elt: Res);
3534 Results.push_back(Elt: LoadRes.getValue(R: 1));
3535 return;
3536 }
3537 }
3538}
3539
3540// Override to enable LOAD_STACK_GUARD lowering on Linux.
3541bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const {
3542 if (!Subtarget->isTargetLinux())
3543 return TargetLowering::useLoadStackGuardNode(M);
3544 return true;
3545}
3546
3547bool SparcTargetLowering::isFNegFree(EVT VT) const {
3548 if (Subtarget->isVIS3())
3549 return VT == MVT::f32 || VT == MVT::f64;
3550 return false;
3551}
3552
3553bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
3554 bool ForCodeSize) const {
3555 if (VT != MVT::f32 && VT != MVT::f64)
3556 return false;
3557 if (Subtarget->isVIS() && Imm.isZero())
3558 return true;
3559 if (Subtarget->isVIS3())
3560 return Imm.isExactlyValue(V: +0.5) || Imm.isExactlyValue(V: -0.5) ||
3561 Imm.getExactLog2Abs() == -1;
3562 return false;
3563}
3564
3565bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
3566
3567bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
3568 // We lack native cttz, however,
3569 // On 64-bit targets it is cheap to implement it in terms of popc.
3570 if (Subtarget->is64Bit() && Subtarget->usePopc())
3571 return true;
3572 // Otherwise, implementing cttz in terms of ctlz is still cheap.
3573 return isCheapToSpeculateCtlz(Ty);
3574}
3575
3576// Override to disable global variable loading on Linux.
3577void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
3578 if (!Subtarget->isTargetLinux())
3579 return TargetLowering::insertSSPDeclarations(M);
3580}
3581
3582void SparcTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3583 SDNode *Node) const {
3584 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
3585 // If the result is dead, replace it with %g0.
3586 if (!Node->hasAnyUseOfValue(Value: 0))
3587 MI.getOperand(i: 0).setReg(SP::G0);
3588}
3589