1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
15#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16
17#include "Sparc.h"
18#include "llvm/CodeGen/TargetLowering.h"
19
20namespace llvm {
21 class SparcSubtarget;
22
23 class SparcTargetLowering : public TargetLowering {
24 const SparcSubtarget *Subtarget;
25 public:
26 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
27 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
28
29 bool useSoftFloat() const override;
30
31 /// computeKnownBitsForTargetNode - Determine which of the bits specified
32 /// in Mask are known to be either zero or one and return them in the
33 /// KnownZero/KnownOne bitsets.
34 void computeKnownBitsForTargetNode(const SDValue Op,
35 KnownBits &Known,
36 const APInt &DemandedElts,
37 const SelectionDAG &DAG,
38 unsigned Depth = 0) const override;
39
40 MachineBasicBlock *
41 EmitInstrWithCustomInserter(MachineInstr &MI,
42 MachineBasicBlock *MBB) const override;
43
44 ConstraintType getConstraintType(StringRef Constraint) const override;
45 ConstraintWeight
46 getSingleConstraintMatchWeight(AsmOperandInfo &info,
47 const char *constraint) const override;
48 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
49 std::vector<SDValue> &Ops,
50 SelectionDAG &DAG) const override;
51
52 std::pair<unsigned, const TargetRegisterClass *>
53 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
54 StringRef Constraint, MVT VT) const override;
55
56 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
57 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
58 return MVT::i32;
59 }
60
61 Register getRegisterByName(const char* RegName, LLT VT,
62 const MachineFunction &MF) const override;
63
64 /// If a physical register, this returns the register that receives the
65 /// exception address on entry to an EH pad.
66 Register
67 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
68 return SP::I0;
69 }
70
71 /// If a physical register, this returns the register that receives the
72 /// exception typeid on entry to a landing pad.
73 Register
74 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
75 return SP::I1;
76 }
77
78 /// Override to support customized stack guard loading.
79 bool useLoadStackGuardNode(const Module &M) const override;
80 void insertSSPDeclarations(Module &M) const override;
81
82 /// getSetCCResultType - Return the ISD::SETCC ValueType
83 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
84 EVT VT) const override;
85
86 SDValue
87 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
88 const SmallVectorImpl<ISD::InputArg> &Ins,
89 const SDLoc &dl, SelectionDAG &DAG,
90 SmallVectorImpl<SDValue> &InVals) const override;
91 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
92 bool isVarArg,
93 const SmallVectorImpl<ISD::InputArg> &Ins,
94 const SDLoc &dl, SelectionDAG &DAG,
95 SmallVectorImpl<SDValue> &InVals) const;
96 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
97 bool isVarArg,
98 const SmallVectorImpl<ISD::InputArg> &Ins,
99 const SDLoc &dl, SelectionDAG &DAG,
100 SmallVectorImpl<SDValue> &InVals) const;
101
102 SDValue
103 LowerCall(TargetLowering::CallLoweringInfo &CLI,
104 SmallVectorImpl<SDValue> &InVals) const override;
105 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
106 SmallVectorImpl<SDValue> &InVals) const;
107 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
108 SmallVectorImpl<SDValue> &InVals) const;
109
110 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
111 bool isVarArg,
112 const SmallVectorImpl<ISD::OutputArg> &Outs,
113 LLVMContext &Context, const Type *RetTy) const override;
114
115 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
116 const SmallVectorImpl<ISD::OutputArg> &Outs,
117 const SmallVectorImpl<SDValue> &OutVals,
118 const SDLoc &dl, SelectionDAG &DAG) const override;
119 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
120 bool IsVarArg,
121 const SmallVectorImpl<ISD::OutputArg> &Outs,
122 const SmallVectorImpl<SDValue> &OutVals,
123 const SDLoc &DL, SelectionDAG &DAG) const;
124 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
125 bool IsVarArg,
126 const SmallVectorImpl<ISD::OutputArg> &Outs,
127 const SmallVectorImpl<SDValue> &OutVals,
128 const SDLoc &DL, SelectionDAG &DAG) const;
129
130 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
134
135 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
136 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
137 SelectionDAG &DAG) const;
138 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
139
140 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
141 const SDLoc &DL, SelectionDAG &DAG) const;
142 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
143 const char *LibFuncName,
144 unsigned numArgs) const;
145 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
146 const SDLoc &DL, SelectionDAG &DAG) const;
147
148 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
149
150 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
151
152 SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
153 SelectionDAG &DAG) const;
154
155 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
156
157 bool IsEligibleForTailCallOptimization(CCState &CCInfo,
158 CallLoweringInfo &CLI,
159 MachineFunction &MF) const;
160
161 bool ShouldShrinkFPConstant(EVT VT) const override {
162 // Do not shrink FP constpool if VT == MVT::f128.
163 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
164 return VT != MVT::f128;
165 }
166
167 bool isFNegFree(EVT VT) const override;
168
169 bool isFPImmLegal(const APFloat &Imm, EVT VT,
170 bool ForCodeSize) const override;
171
172 bool isCtlzFast() const override;
173
174 bool isCheapToSpeculateCtlz(Type *Ty) const override {
175 return isCtlzFast();
176 }
177
178 bool isCheapToSpeculateCttz(Type *Ty) const override;
179
180 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
181 // FIXME: We insert fences for each atomics and generate
182 // sub-optimal code for PSO/TSO. (Approximately nobody uses any
183 // mode but TSO, which makes this even more silly)
184 return true;
185 }
186
187 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
188
189 void ReplaceNodeResults(SDNode *N,
190 SmallVectorImpl<SDValue>& Results,
191 SelectionDAG &DAG) const override;
192
193 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
194 unsigned BROpcode) const;
195
196 void AdjustInstrPostInstrSelection(MachineInstr &MI,
197 SDNode *Node) const override;
198 };
199} // end namespace llvm
200
201#endif // LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
202